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Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.
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This invention is related to computer memory systems of a type utilizing small, compact semiconductor memory cards, and particularly to a structure within the cards for densely packing a large number of integrated circuit chips of electrically erasable and programmable read-only-memory ("EEPROM") to provide a complete memory system.
Currently, standard microcomputer systems use a combination of fixed and removable (floppy) magnetic disk media for long-term, non-volatile memory. Semiconductor random access memory ("RAM") without a battery power supply backup is only temporarily used since it is volatile; that is, when power to the computer system is disconnected, contents of the RAM are lost. A small amount of read only memory ("ROM") is also included for permanent storage of certain computer system parameters that do not change.
There is currently underway an effort to develop non-volatile flash EEPROM memory systems to replace either of the existing fixed or floppy magnetic disk systems, or both. It is now becoming possible to form a megabyte or more of flash EEPROM on a single semiconductor integrated circuit chip. As a result, several megabytes of memory can be formed in a very small package.
Indeed, an industry "PC Card Standard", release 1.0, dated August 1990, of the Personal Computer Memory Card International Association (PCMCIA) sets mechanical and electrical interface standards for a memory card that is not much larger than an ordinary credit card. Although some physical dimension variations are permitted within the scope of this standard, it is less than 6.0 mm in overall outside thickness, less than 5.5 cm in width, and less than 9.0 cm in length. A female type of pin connector is provided across one of the narrow ends of the card structure. Such PC cards have been commercially implemented primarily with static random-access-memory ("SRAM") and ROM.
It is a principal object of the present invention to provide a structure for packaging a large number of flash EEPROM integrated circuit chips within such a PC card or other standard structure, thereby providing a large memory capacity in an individual card or other industry standard physical configuration.
It is another object of the present invention to provide a complete flash EEPROM system within such an individual card or other standard configuration that emulates a floppy or hard disk system.
It is a further object of the present invention to provide such a PC card structure that is easy to fabricate and test during assembly.
It is yet another object of the present invention to provide an improved computer memory system that utilizes one or more PC cards containing EEPROM integrated circuit chips.
This and additional objects are accomplished by the various aspects of the present invention, wherein, briefly and generally, according to one aspect, one or more EEPROM memory chips are directly mounted to a substrate to form a sub-board structure, and one or more of the sub-board structures are then attached to both sides of a main circuit board that extends throughout an interior of the card package and terminates along one side to form the PC card connector. Each of the sub-boards has a line of electrical terminals along one side thereof in a pattern that matches a pattern of exposed conductors on the main board.
In specific implementations, two, three or four such memory chips are provided in a row along a rectangularly shaped sub-board having terminals along one of its long dimensions and which is attached to the main board through connection of its terminals with the exposed main board contacts. Several such sub-boards can be installed on the main board, on one or both sides, within the limits of the PC card standard identified above. This sub-board structure permits a large number of EEPROM chips to be included within such a card. It also allows testing of the chips attached to each sub-board before they are assembled together on the main board, thus allowing an early identification of any problems in the mounting and initial interconnection of the circuit chips.
One type of EEPROM PC card contains only EEPROM memory chips, with the use of sub-boards as discussed above or otherwise, which are then interconnected through the card socket to a controller circuit. The controller interfaces between a computer system's main bus and the individual circuit chips. One, two or more sockets may be provided in conjunction with a given controller for respectively removably receiving one, two or more PC cards at a time. An amount of permanent EEPROM capacity may optionally be serviced by the same controller circuit.
Another type of flash EEPROM PC card contains a large number of individual memory circuit chips, either in the sub-board structure described above or otherwise, plus one or more circuit chips forming a controller. In this embodiment, each PC card communicates through its connector in a format of a computer system bus. Such a PC card is self-contained and no intervening controller circuit is required.
According to another aspect of the present invention, a flash EEPROM system is provided with physical form factors which match those of industry standard floppy and hard disk drives, along with an electrical interface that emulates such drives. Such a non-volatile flash EEPROM system is then easily usable as an alternative in a computer system designed to include such disk drives.
According to yet another aspect of the present invention, a flash EEPROM system is provided in a PC card or other industry standard memory system package with a controller for directly interfacing the system with a computer system bus. No extra adaptation is required to use such a non-volatile, non-mechanical mass memory in computer systems whose hardware and software operating systems are designed to accept and use disk systems. The internal controller converts the computer bus interface and signal protocols to those required to operate the flash EEPROM memory.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
FIG. 1 is an exploded view of first embodiment of a controller card having multiple sockets adapted to receive multiple PC cards and be connected to a host computer system bus;
FIG. 2 is a side view of the memory system of FIG. 1 with the PC cards and a connector in place;
FIG. 3 illustrates generally, in block diagram form, the electrical connections of the memory system of FIGS. 1 and 2;
FIG. 4 is an exploded view of an internal construction of a PC card showing the use of a main circuit board carrying sub-boards that each have several integrated circuit memory chips attached to them;
FIG. 5 is a sectional view of a PC card using the board structure of FIG. 4, taken at section 5--5 of FIGS. 1 and 4;
FIGS. 6 and 7 are sectional views of a sub-board in the assembly of FIGS. 4 and 5, taken respectively at sections 6--6 and 7--7 of FIG. 4;
FIG. 8 is a sectional view of a PC card showing a modification of FIG. 5 wherein a controller sub-board is included;
FIG. 9 illustrates, in an electrical block diagram form, a memory system utilizing two or more PC cards having a controller included within them in accordance with the structure of FIG. 8;
FIG. 10 is a side view of a second embodiment of a controller card having a socket adapted to receive a PC memory card, and also including fixed memory;
FIG. 11 is an end view of the controller card of FIG. 10;
FIG. 12 shows an electronic block diagram of a computer system in which a PC card containing flash EEPROM memory and its controller is used;
FIGS. 13A and 13B together form a schematic block diagram showing the electronic system within a PC card shown in the system of FIG. 12;
FIG. 14 illustrates a technique of addressing the flash EEPROM memory within the PC card system of FIGS. 13A and 13B;
FIG. 15 outlines a sector organization of the flash EEPROM integrated circuit memory cells;
FIG. 16 shows expanded detail of a portion of FIG. 13A; and
FIGS. 17, 17A, and 17B are a flow diagram which shows an operation of the system of FIGS. 13A and 13B.
Several physical configurations of a memory card system are described with respect to FIGS. 1-11. An example electronic system within such a card, including both flash EEPROM and controller integrated circuit chips, is described with respect to FIGS. 12-17.
Physical Memory Card Configurations
Referring initially to FIGS. 1-3, one embodiment of a PC card flash EEPROM memory is illustrated. A structurally rigid printed circuit board 11 contains on one side various circuit components 13 that form a memory controller. The controller circuit is operably connected with a row of connector pins 15 attached to the board 11. A connector 17, provided at an end of a ribbon cable 19, is adapted to interconnect the conductors of the cable 19 to the row of pins 15. Another end (not shown) of the ribbon cable 19 is connectable with a microcomputer system bus. Alternatively, the controller board 11 could be provided with a different type of connector that is adapted to fit directly into an expansion slot of a microcomputer system.
On an opposite side of the controller board 11 from the controller circuit chips 13 are two PC card receiving slots 21 and 23. These slots have respective rows 25 and 27 of conductor pins. The slot and pin arrangement is dimensioned to receive respective PC cards 29 and 31 for mechanical and electrical interconnection therewith. The rows of pins 25 and 27 are connected to the controller circuit 13. The PC cards 29 and 31 contain a plurality of flash EEPROM memory chips, a preferred arrangement thereof being discussed in detail below. The PC cards 29 and 31 conform to the PC Card Standard identified above, which is incorporated herein by this reference. Of course, other sized cards may be used instead, depending upon the particular application.
Although two sockets 21 and 23 are indicated in FIGS. 1-3, this embodiment may be varied to contain only one socket or to include three or more sockets. As FIG. 2 shows, both of the PC cards 29 and 31 can be inserted and electrically interconnected with the controller 13 at one time. If additional sockets are provided, additional cards can similarly be simultaneously utilized. The removability of the memory cards allows them to be used much like floppy disks are currently used. As indicated in FIG. 3, additional flash EEPROM memory 33 can be provided on the underside of the controller board 11 itself as fixed memory. An example of a controller card having an amount of fixed memory is given in another embodiment shown in FIGS. 10 and 11.
FIGS. 4 and 5 illustrate a preferred printed circuit board structure for mounting and interconnecting a plurality of individual flash EEPROM integrated circuit chips (up to 24 in this example). A main rectangularly-shaped printed circuit board 35 has outside dimensions slightly smaller than those of the outside of the PC card in which it is installed. A plurality of sub-boards 37-42 are attached to opposite surfaces of the main board 35 (in this case, six). Each of the sub-boards contains four integrated circuit EEPROM chips attached to a surface thereof opposite to that facing the main board 35. Two such chips 43 and 45 are shown in FIG. 4 in conjunction with the sub-board 37. Similarly, circuit chips 47-50 are indicated to be attached to a surface of the sub-board 40. Illustration of the remaining circuit chips is omitted for clarity.
The main board 37 includes a center (core) supporting substrate with conductor traces formed on either side. A thin dielectric layer is coated over the entire area of each of the surfaces, covering the conductor traces and any exposed portions of the core substrate material surfaces. The insulating material does not cover, however, various rows of electrical contacts.
One such row of electrical contacts 51, and a similar row on an opposite side of the main board 35 but not visible in FIG. 4, is provided across a narrow side of the main board 35 and forms the contacts for the rows of pins 21 and 23 of FIG. 1. Traces beneath the insulation layer (not shown) then interconnect these edge contacts with various rows of contacts across both surfaces for interconnecting with the sub-boards, for example, a row 53 of contacts provided across the narrow width of the main board 35. A row of contacts 55 having the same spacing and pattern as the row 53 is provided along a large edge of the rectangularly shaped sub-board 37. Thus, when the sub-board 37 is positioned on a surface of the main board 35, its contacts 55 line up with the row 53 of contacts. They are attached to one another by soldering, or some other technique. Indeed, in most cases, the soldering of these contacts is the only form of mechanical attachment of the sub-board to the main board that is required. This makes the structure quite simple and expedient to assemble. However, if additional attachment is believed necessary, a dot of epoxy can be applied between each sub-board and the main board along a side of the sub-board opposite to its row of edge contacts.
Similarly, five other rows of contacts are provided for accommodating the other five sub-boards shown in the example of FIGS. 4 and 5. Rows 57 and 59 are on the same side of the main board 35 as the row 53. All rows on the main board 37 are parallel to each other and to the short edge of the board 35. Similar rows of contacts 61, 63 and 65 are shown in dotted outline on the opposite surface of the main board 35. Most of the conductive traces are preferably provided on one side of the core substrate of the main board 35, these conductors then penetrating that sub-board to connect with the contacts on an opposite side.
Referring to the cross-sectional PC card view of FIG. 5, each of the sub-boards is shown physically attached to the main board 35 only by its electrical contacts. In either case, a plastic ring 67 surrounds its outside edges and forms the narrow sidewalls of the resulting PC card. Rows of holes 69 and 71 are provided at one end to accept socket pins, such as the pins 25 of FIG. 1, for contact with the edge connector of the main board 35, which includes the row 51 of contacts. Generally rectangularly shaped, thin metal plates 73 and 75 are attached to the edge ring 67 to form opposite sides of the PC card. Metal layers are preferred in order to provide highly desirable radio frequency shielding. The outside layers 73 and 75 are generally connected with ground potential of the memory circuit carried therein, usually V.sub.SS of the computer system with which it is interconnected.
With reference to FIGS. 4, 6 and 7, the structure of the sub-boards and attachment of the memory chips to them will now be described. Taking sub-board 37 and its attached chip 45 as an example, the chip is provided with its interconnecting pads 77 supplied along only one of the chip edges. This edge of each of the chips attached to the sub-board 37 is then positioned to face the edge carrying the sub-board contacts 55.
The sub-boards are best illustrated by the sectional views of FIGS. 6 and 7. A central core substrate layer 79 carries conductive traces on both sides. For example, in the view of FIG. 6, a conductive trace 81 is attached to the top side of the central substrate layer 79 and in the sectional view of FIG. 7, taken at a different position, a trace 83 is so provided. The traces on the top side of the core substrate layer 79 generally extend across the narrow width of the sub-board 37 while conductive traces on the bottom side, such as traces 85, 87 and 89, generally extend in the long direction of the sub-board. The result is a type of matrix that makes it easy to interconnect the large number of contacts provided by multiple integrated circuit chips and the sub-board contacts 55. An electrical contact is made through the layer 79 when it is desired to interconnect traces on opposite sides thereof, such as top trace 81 being connected with bottom trace 89 in the view of FIG. 6, and top trace 83 being interconnected with bottom trace 87 in the view of FIG. 7. Both sides of the substrate are covered with respective thin insulating layers 91 and 93.
Portions of the top side traces along the contact edge of the sub-board are exposed, however, for wire bonding to pads of the chips attached to them. For example, in the section of FIG. 6, a wire 95 is bonded between one pad of the chip 45 and the trace 81. In the section of FIG. 7, another wire 97 is bonded between a different pad of the chip 45 and an electrically separate trace 83. In the example section of FIG. 6, the trace 81 is connected with an edge contact 99, one of those in the row of sub-board contacts 55. The wire 95 is then connected directly to the pin 99 a very short distance away. Others of the chips on the sub-board 37 are similarly interconnected with the pin 99 by bonding to top traces which are interconnected with the bottom trace 89 that has been connected to the pin 99.
The section of FIG. 7 shows a different example, wherein the wire 97 is bonded to a top conductive trace 83 that is connected to a bottom trace 87. Although not shown, the bottom trace 87 is connected somehow to one of the conductors of the sub-board row of contacts 55. In the case of FIG. 7, a pin 101 is interconnected on the bottom of the central substrate 79 with the trace 85. That bottom trace then allows a pad, not shown, of the chip 45 to be electrically connected with it, and similarly for the other chips attached to the sub-board 37.
Surrounding the attached integrated circuit chips on a top side of the sub-board 37 is a plastic frame 103. That frame, in combination with an overall encapsulation (not shown) of the chips on the top surface of the sub-boards, protects those chips.
Referring to FIGS. 8 and 9, a modification of the embodiment of FIGS. 4-7 is shown with common elements indicated by the same reference number but with a prime (') added. In this case, a sub-board 105 nearest the edge connector contains integrated circuit chips forming a controller. That is, one sub-board of memory chips is replaced with an on-board controller so that the resulting PC card can be operated directly from a computer system bus without having to use the external controller 13 of the embodiment of FIGS. 1-3. Most of the traces interconnecting the edge connector of the main board 35' are connected directly with rows of main board contacts to which the controller sub-board 105 is electrically connected. Traces interconnecting the rows of contacts with which primary chip containing sub-boards are primarily attached also extend to contacts with which the controller sub-board 105 is connected. Indeed, depending upon the design, enough controller sub-board contacts may be required as to have rows along each of the opposing long sides of the sub-boards, as shown in FIG. 8, with corresponding parallel rows of contacts on the top surface of the main board 37'. Alternative to mounting the controller chips on a sub-board, they can be mounted directly onto the main board 35 in the space shown in FIG. 8 to be occupied by the sub-board 105.
Referring to FIG. 9, a system utilizing such a card with internal controller is illustrated. Two such cards 107 and 109 are shown to be connectable through a connector 111 to a microcomputer system bus through conductors 19'. of course, any number of such cards, from 1 to many, can be utilized in a single computer system having one or more such connectors. The connector 111 need not contain any electronic components, except perhaps for buffers, amplifiers and the like. But no data manipulation or other controller functions need be provided outside of the cards 107 and 109, in this embodiment. Of course, more than two such PC cards can be utilized at a time by providing an expanded connector 111.
Referring to FIGS. 10 and 11, a modification of the controller card illustrated in FIGS. 1 and 2 is shown in orthogonal side and end views, respectively. A structurally rigid printed circuit board 121 is provided with a single socket 123 for removably receiving a PC memory card 125 of the type discussed with respect to FIGS. 4-7 above. The printed circuit board 121 is wide enough in this embodiment to accept a plurality of packaged integrated circuit chips 127 that form the memory controller. A connector 129 along one edge of the board 121 provides for connection to the computer system through a ribbon cable or the like. Attached under the board 121 are a plurality of sub-boards 130, in this case, six, of the type described earlier with respect to FIGS. 6 and 7. Each sub-board contains a plurality of flash EEPROM chips. The sub-boards are connected to exposed contacts on the underside of the controller board 121 in the same manner as utilized in the PC cards as described with respect to FIG. 5.
The controller board embodiment of FIGS. 10 and 11 provides a combination of fixed system flash EEPROM capacity, attached to the underside of the board 121, and the ability to use removable PC cards also containing flash EEPROM chips. The controller formed by interconnecting through traces on the controller board 121 the packaged circuits 127 is connected with the computer system bus connector 129 and operates both the fixed and removable EEPROM memory. Of course, one or more additional sockets may be provided in order to accommodate multiple PC memory cards at one time.
In addition to packaging the flash memory within the industry standard PC memory card form factor discussed above, it is also desirable to be able to package such a memory system within an industry standard floppy disk drive or hard disk drive form factor. This allows the semiconductor memory to be easily physically substituted for a disk drive. An example standard, just being formed, is for a 1.8 inch hard disk drive with a small form factor. Its dimensions are about 19 mm. in height, 54 mm. in width, and 73 mm. in length, as a maximum. As disk drives evolve over time, their packages become smaller. The packaging techniques described above, particularly the use of sub-boards for mounting circuit chips, allow large solid state memory systems to be presented in the same small packages.
Electronic EEPROM and Controller System within a Package
It is preferred that the memory system included in a card or other standard package be self-sufficient so that it can electronically interface at its connector with a standard computer bus interface. One such standard is an integrated device electronics ("IDE") interface. This interface is being used extensively with hard disk drives that have controller circuits integrated as part of the drive. Thus, the packaged EEPROM system as part of the present invention includes controller circuits in order that the unit appears to the computer system as a disk drive.
Referring to the general block diagram of FIG. 12, bus interface circuits 137 are shown as providing individual circuit connections 138 according to the IDE interface specifications to a flash EEPROM memory package 139 that includes a controller circuit. The package 139 may be a thin PC card as discussed above with respect to the figures, a package having dimensions and capabilities similar to that of a hard disk drive, as mentioned previously, or various other convenient removable packages. The bus interface 137 is connected with a computer system bus 153. A typical computer system is shown in FIG. 12 to include a microprocessor 154, ROM 155, RAM 156 and input/output circuits 157, all connected with the common bus 153. Of course, the memory system of the present invention can be utilized with other specific computer systems.
The IDE signal lines 138 connected to the memory package 139 include, as indicated in FIG. 12, the 16-bit data bus D0-D15 and three lines of an address bus, A0-A2. These lines are connected to the corresponding lines of the system bus 153 through buffers and drivers within the interface circuit 137. Similarly provided are system control signals IOR, IOW and RESET. The signals IOR and IOW affect, respectively, a read or write operation within the memory package 139 when toggling between states.
The IDE signal lines 138 also include control lines CS1 and CS2, which serve as two of several address bit lines for the memory within the package 139. These signals are decoded from the higher level system address lines A3 and up by appropriate circuits within the bus interface circuitry 137. Alternatively, the necessary address lines may be communicated with the memory package 139 and this decoding circuitry provided within the package. However, this occupies more pins within the connector so is usually done in the manner being described.
A number of status signals are also provided by the memory within the package 139 to the computer system through the bus interface 137. An example is the signal identified as IOCS16 which notifies the system whether the memory module accepts an 8- or 16-bit transfer on the data bus. Another line INTRQ provides an interrupt request from the memory to the computer system. Of course, there are additional control and status signals, as well as voltage supply and ground lines, that are communicated over the connector according to the IDE standard.
FIGS. 13A and 13B illustrate a preferred form of the memory system 139, being substantial duplicates of FIGS. 7A and 2A, respectively, of the simultaneously filed application identified above. As described more completely in that application, a controller 133 includes a disk drive interface 411 that utilizes a commercially available peripheral interface chip 415 that is connected to the lines 138 which are, in turn, connected to the host computer system through mating connector portions. The peripheral interface 415 transfers data between the host computer and a memory controller 401 over a serial data link 421. A microprocessor 417 controls the peripheral interface 415 and memory controller 401 over an internal bus 423. An example of the peripheral interface circuit 415 is an SH 265 disk controller chip available from Cirrus Logic, Inc. An example of the microprocessor 417 is a Motorola, Inc. 68HC11 part. The buffer memory 413 is static RAM and provides temporary storage of data being transferred between the memory unit 123 and the host computer system. The memory controller 401 is described in detail in the aforementioned simultaneously filed application with respect to its FIG. 8A. It is desirable to combine as much of the interface 415 and the controller 401 onto a single integrated circuit chip.
The controller 133 of FIG. 13A is connected to at least one, and preferably a plurality, of memory modules 131 of the type illustrated in FIG. 13B. Each memory module 131 includes a plurality of EEPROM integrated circuit chips 141 physically connected together on a sub-board 143. Each of the memory chips is connected with the controller 133 over lines 135. Each of the memory chips 141 is programmed with a unique address by connection with a plurality of pads, such as the pads 147 on one of the devices, being controlled by selectively grounding them on mount 149.
Referring to FIG. 14, each of the EEPROM integrated circuits is formed on a small substrate chip with memory cells arranged in rows and columns in quadrants 201, 203, 205 and 207. These individual quadrant arrays are connected through interface circuits 209 to the controller lines 135 and a line 151. Each of the memory cells within a given quadrant, such as the quadrant 201, is addressable by proper voltages applied to intersecting column bit and row driver lines. A sector of such memory cells contiguously arranged, such as a sector 211 shown as part of the quadrant 201, is erasable simultaneously by addressing the sector.
Referring to FIG. 15, the sector 211 is shown to be formed of four rows 213 of memory cells, each row having a length 215 of enough cells to store 128 bytes. Thus, the sector 211 stores 512 bytes, the same capacity as a sector of disk storage according to prevailing disk standards. A number of such sectors are provided adjacent to each other, each of which is separately addressable and erasable by a single command in one clock cycle. An additional byte 217 of disk storage is provided as an extension of each row of EEPROM cells of the sector 211 for the purpose of providing spare EEPROM cells to replace bad cells within the sector 211. Similarly, another byte 219 stores header and other common overhead information required for each sector. Additional details of the memory system operation can be had by reference to published international patent applications of the assignee hereof, namely European publication no. 392,895, dated Oct. 17, 1990, and PCT publication no. WO 90/12400, dated Oct. 18, 1990.
The number of EEPROM cells, and thus the number of sectors, in each of the quadrants 201, 203, 205 and 207 (FIG. 14) is preferably made to be the same. A given sector of cells is addressed by first designating the integrated circuit chip, its quadrant and then the sector within the quadrant. The highest capacity memory unit is provided when all four quadrants are utilized, of course, but the quadrant approach allows memory units of lower storage capacity to be manufactured with rejected chips so long as at least one quadrant and the buffer portion 209 of a rejected chip are operable. This thus allows making use of memory chips that would otherwise be discarded, and thus the provision of a lower capacity memory unit at a much lower cost.
FIG. 14 additionally illustrates the manner in which the individual chip EEPROM integrated circuit chips 141 are addressed in order to read or write data in response to commands from the system computer. A box 221 indicates a translation of the information applied to the memory unit over the lines 138. The address from the host computer designates a disk drive head that is to be utilized for the data transfer, a data cylinder, a beginning sector number on that cylinder, and the number of contiguous sectors (sector count) in which the data is being read or written. The memory controller translates that address, as shown on the right hand side of block 221 of FIG. 14, into a chip number, the quadrant on the chip and a sector of memory cells within that quadrant that is to be addressed. If more than one sector of data is being transferred during a single access by the host computer, a number of EEPROM sector accesses equal to the disk sector count is accomplished.
The circuitry for accomplishing this address translation is illustrated in FIG. 16, a part of the controller 133 of FIG. 13A. The commercially available peripheral interface chip 415 includes a number of registers which are utilized to perform the translation. One group of registers which responds to a toggle of the IOR signal includes a status register 223, a read head address register 225, read cylinder address registers 227 and 229 (allows a 16-bit cylinder address), a read starting sector address register 231, and a read sector count register 233. Similarly, another set of registers is written into or read by toggling the IOW signal. These registers include a command register 235, a write head address register 237, write cylinder address registers 239 and 241, a write starting sector address register 243, and a write sector count register 245. Each pair of registers is addressable by the host computer with a bit pattern indicated to the right of the registers of FIG. 16, involving the signals CS1, CS0 and A0-A2. Similarly, a read buffer memory 247 and a write buffer memory 249 are separately addressable.
The group of registers provide a temporary place for storing commands from the host computer over the interface lines 138. When the computer system wants to perform a read or write operation, it writes a READ or WRITE command into the command register 235 after writing into the respective sets of registers 225-233 or 237-245 the address, in disk drive terms, of the sectors where the data is to be read or written. This is controlled by the basic input/output system ("BIOS") that is part of the computer operating system. The microprocessor 417, through a microprocessor port 251, then reads the command from the command register 235 and the address from the appropriate read or write registers, and performs the translation and command. Once a command is detected in the register 235, a BUSY signal is written into the status register 223 that the host computer can then read to know that the memory system is in the process of executing a command and cannot receive another. Data is transferred between the buffer memory 413 and the EEPROM memory through a data port 253. Once a commanded operation has been performed, the microprocessor 417 then writes a NOT BUSY indication in the status register 223. Other registers are provided in the commercially available peripheral interface chips, but those of them which are most important to the operation being described herein have been shown.
This operation under control of the microprocessor 417 (FIG. 13A) is illustrated in a general way by a flow diagram of FIG. 17. A first step in the operation is for the command register 235 to be continuously polled in order to detect a command placed there by the host computer system. Such a read operation is indicated by a block 261 and a determination as to whether a new command has been written into the register 235 or not is indicated by a block 263. If a new command has not been so written since that register was last accessed, then the steps 261 and 263 are repeated. When a new command is detected, the processing moves to a step 265 where a BUSY status signal is written in the register 223. The host computer, in polling the status register 223, will then not lead another command into the command register 235 until a NOT BUSY status is written into the register 223 at the end of the current operation.
Other than READ and WRITE, other commands from the host processor include SEEK and RESTORE. These are commands that are intended to move a disk drive read/write head inbetween read and write operations for optimal positioning. If one of these commands is detected, as indicated by a block 267, a majority of the processing is skipped, proceeding immediately to the writing of the NOT BUSY status in the register 223, as indicated by a block 269.
If the command is to READ data from the EEPROM system, or to WRITE data into it, as indicated by a block 271, then one of two paths is taken in the processing. If a READ operation is commanded, a step 273 reads the address, in disk drive terms, stored in the registers 225-223 by the host computer. A next step 275 translates that disk address into a flash memory address, as generally described in FIG. 14 with reference to an address translation block 221. This translation is most easily accomplished by an algorithm calculation or reference to a look up table that have a one-to-one correspondence between the disk address and the EEPROM address. That one-to-one correspondence is disturbed, of course, when a sector is found to have so many bad EEPROM cells that it must be taken out of service and replaced by another sector. The address translation table is then dynamically altered.
After the address has been translated into EEPROM terms, a next step 276 reads data from the flash memory and writes it into the read buffer 247.
Thereafter, in a step 277, the read data is compared with an expanded form of an error correction code ("ECC") that has been stored with the data. A common ECC format and algorithm used for disk drives is used. Next, in a step 278, the read data is transferred to the host computer. Any error that has been detected during the reading process is written into the status register 223, in a step 279. Following that, the step 269 indicates to the host computer that the operation is complete by writing NOT BUSY into the register 223. At that time, the system computer will know that the read operation is complete and that it may access the buffer read memory 247 over the interconnection lines 138 to transfer the read data to somewhere else in the computer system.
Returning to the decision block 271, the path for a WRITE command is similar to that just described for a READ command. A first step 281 in response to such a command is to read the address from registers 237-245, which have been written there by the host computer in disk drive terms. A next step 283 translates that address into EEPROM terms, in the same way described with respect to the step 275. A final step 285 is to execute the command by reading data which has been placed into the write buffer memory 249 by the host computer system and then writing that data into the address EEPROM sectors. After that is complete, the steps 279 and 269 are executed in the manner discussed above. The process then returns to the beginning steps 261 and 263 to poll the command register 235 for a new command from the host computer system.
Although the various aspects of the present invention have been described with respect to their preferred embodiments, it will be understood that the invention is entitled to protection within the full scope of the appended claims.
1. A non-volatile memory system adapted for use with a host system, comprising:
- a memory controller having a connector to receive a memory card and connectable to (1) receiving address, user data and command signals from said host system according to a given protocol and (2) providing user data and status signals to said host system according to said given protocol, said controller including at least one microprocessor that executes commands from the host system and a buffer memory that temporarily stores user data being written to or read from a memory card inserted in the controller connector,
- a plurality of said memory cards which individually include a card connector that mechanically mates with the controller connector to provide a removable electrical connection therebetween, said card connector being connected to an integrated circuit array of floating gate memory cells organized in groups of cells that are individually addressable for simultaneous erasure of the cells of a group, said memory cards additionally being individually formed of a package having a width less than 5.5 centimeters and a length less than 9.0 centimeters,
- said memory controller additionally being responsive to an address of at least one mass memory storage block from the host system for accessing through said controller and card connectors a corresponding at least one of the memory cell groups within one of the plurality of memory cards having its card connector mated with said controller connector, and
- a serial communications circuit extending through the controller and memory card connectors to transfer user data between the buffer memory of said controller and said at least one accessed memory cell group.
2. The memory system according to claim 1, wherein said memory controller further includes:
- a plurality of temporary storage registers, including at least one set for storing a storage block address received from the host system, a command register and a status register,
- means for allowing the host system to write a storage block address to said one register set, to write a command to the command register, to read a status from the status register, to write user data into the buffer memory and to read user data from the buffer memory,
- means including the microprocessor for reading from said one register set the address stored from the host system and translating said host system address into an address of one or more memory cell groups corresponding to the host system address, and
- means including the microprocessor for reading the command register and (1) in response to a read command, transferring user data within the addressed at least one memory cell group into the buffer memory and then write a completion status in the status register, or (2) in response to a write command, transferring user data from the buffer memory into the addressed at least one memory cell group and write a completion status into the status register.
3. The memory system according to claim 1 wherein said memory system includes a second controller connector to receive and connect the card connector of another of the plurality of said memory cards, thereby to establish operation of the controller simultaneously with two of said plurality of memory cards.
4. The memory system according to claim 1 wherein individual ones of the groups of memory cells that are simultaneously erasable include enough cells to store 512 bytes of user data plus overhead data related to a sector and the user data stored therein.
5. The memory system according to claim 1, wherein the memory cards individually include:
- a plurality of sub-boards each carrying a plurality of flash EEPROM integrated circuit chips and including electrical conductors attached thereto which interconnect said chips to a plurality of electrical contacts along one edge of said sub-board, said contacts having a predetermined pattern therealong,
- a main circuit board including electrical conductors attached thereto and extending between (a) a plurality of rows of electrical contacts on at least one side thereof that are each arranged in said pattern and (b) a plurality of electrical contacts at an edge thereof positioned to form part of a connector,
- said sub-boards being attached to said main board with their edge contacts being electrically connected to respective ones of said plurality of rows of contacts on the main board, and
- a cover enclosing said main printed circuit board and the attached sub-boards.
6. The memory system according to any one of claims 1-3, wherein the controller additionally includes another connector for removable mechanical and electrical connection with the host system.
7. The memory system according to claim 6 wherein said another controller connector includes conductors conforming to an industry standard IDE interface.
8. The memory system according to any one of claims 1-3, wherein the memory cells of the integrated circuit array are individually programmable into exactly two states in order to store exactly one bit of data per cell.
9. The memory system according to any one of claims 1-3, wherein the memory cells of the integrated circuit array are individually programmable into more than two states in order to store more than one bit of data per cell.
Referenced Cited
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Other references
- PC Card Standard: Release 1.0", Personal Computer Memory Card International Association, pp. 1-102, Aug. 8, 1990. Brochure: "Wafer-Stack Wafer-Scale Storage Subsystem," Anamartic, Inc., 1990. Auclair, D.L., "Optimal Solid State Disk Architecture For Portable Computers", Silicon Valley PC Design Conference (SVPC), pp. 811-815, Jul. 9-10, 1991. Miller, "Semidisk Disk Emulator," Interface Age, p. 102, Nov., 1982. Clewitt, "Bubble Memories as a Floppy Disk Replacement," 1978 MIDCON Technical Papers, vol. 2, pp. 1-7, Dec. 1978. Hancock, "Architecting a CCD Replacement for the IBM 2305 Fixed Head Disk Drive," Digest of Papers, Eighteenth IEEE Computer Society International Conference, pp. 182-184, 1979. Bleiker and Melchior, "A Four-State EEPROM Using Floating-Gate Memory Cells", IEEE Journal of Solid-State Circuits, vol. SC22, No. 3, Jun. 1987, New York, NY, USA. "CL-SH265 Advance Data Sheet," Cirrus Logic, Inc., pp. 1-83, (Dec., 1990). Cormier, "Special Report--Erasable/Programmable Solid-State Memories," Electrical Design News, vol. 30, No. 25, pp. 144-154 (Nov. 14, 1985). Lai, R., and The Waite Group, Inc., Writing MS-DOS Device Drivers, "Chapter 7--Introducing Disk Internals," pp. 237-273 (1987) and "Chapter 8--A RAM Disk Driver," pp. 277-319 (1987).
Patent History
Type: Grant
Filed: Jul 23, 1998
Date of Patent: Jan 4, 2000
Assignee: SanDisk Corporation (Sunnyvale, CA)
Inventors: Robert F. Wallace (Sunnyvale, CA), Robert D. Norman (San Jose, CA), Eliyahou Harari (Los Gatos, CA)
Primary Examiner: Do Hyun Yoo
Law Firm: Majestic, Parsons, Siebert & Hsue
Application Number: 9/121,348
International Classification: G11C 1606; G06F 1300;


text:
Community Developments Investments (August 2013)
Public–Private Partnership Helps Dream of Home Ownership Come True
Gilbert Gerst, Senior Vice President, Community Development Banking, BOK Financial Corporation
Most Indian land is owned by tribes but held in trust by the federal government. Land held in trust for a tribe typically cannot be mortgaged, and federal approval is required before a lien can be placed on land held in trust for an individual. This land ownership structure is the main reason most banks have not actively pursued mortgage lending on Indian land: The banks have been unable to obtain valid liens on property or pursue foreclosure in the event of a loan default. In the event of default, neither the U.S. Department of Housing and Urban Development (HUD) nor a lender may sell a defaulted property to a non-Native American. As a result of this ownership structure, tribes and individual Native American families have historically had limited access to private mortgage capital.
In 1992, Congress created the Indian Home Loan Guarantee Program, referred to as Section 184. This federal program is specifically designed to address the lack of mortgage capital on tribal land. Under Section 184, actively enrolled members of a federally recognized tribe are eligible to apply for, and banks can make government-guaranteed mortgage loans for, the purchase, refinancing, rehabilitation, or new construction of homes on either tribe-owned land or fee simple land that is outside of Native lands. The guarantee is provided by the Office of Loan Guarantee within HUD's Office of Native American Programs. The intent of this program is to increase the availability of mortgage lending on Indian reservations or designated Indian operating areas.
Through BOK Financial Corporation's New Mexico banking division, Bank of Albuquerque, we have used Section 184 loans as an important tool to enable individuals and families to realize the dream of home ownership. Bank of Albuquerque works with approximately 19 pueblos in New Mexico. The word "pueblo" means "town" or "village" in Spanish and is also used to refer to various tribes themselves. In 2010–2012, Bank of Albuquerque originated more than 600 loans totaling more than $90 million under this program.
According to 2010 census data, the population of American Indian or Alaska Native individuals in New Mexico totaled 219,512. To prove eligibility for Section 184, an individual must be considered an actively enrolled member in a federally recognized tribe. This membership is validated through a tribal enrollment card. Each tribe has specific tribal enrollment requirements, established to preserve the tribe's unique character and traditions. The tribes establish membership criteria based on shared customs, traditions, language, and tribal blood. Tribal enrollment criteria are set forth in each tribe's constitution, articles of incorporation, or ordinances, and vary from tribe to tribe. Common requirements for membership include lineal descendancy from someone named on the tribe's base roll or relationship to a tribal member who descended from someone named on the base roll. The base roll is the original list of members as designated in a tribal constitution or other document.
The Section 184 program is fairly easy to use, and can be used for purchase, refinance, and single close construction transactions. We use an in-house underwriter who has the authority to approve fee simple land loans, so turnaround is very quick. The maximum loan is 150 percent of the U.S. Federal Housing Administration (FHA) mortgage limit, with only 1.25 percent to 2.25 percent for down payment with no mortgage insurance. Interest rates are fixed and comparable to FHA loan rates. Terms may not exceed 30 years and there is no income limit associated with the program. The Section 184 program also has the lowest cost of any government guarantee or conventional insurance program, with no monthly premium. There is only one qualifying rate, which is a 41 percent total debt-to-income ratio, and that can be exceeded if there are compensating factors.
Tribal trust or leasehold land transactions can take a bit longer for approval, because we must have a residential lease agreement in place that has been approved by the individual tribal government. Then a title status report is issued by the U.S. Bureau of Indian Affairs. Once all of this is in place, the entire file is submitted to one of the three designated underwriters at HUD (in Denver, Colo.; Atlanta, Ga.; or Washington, D.C.). These underwriters underwrite loans for all states, and turnaround times can be two to three weeks. Performance of loans under the program has been good, with overall performance better than the FHA product. We include these loans in Ginnie Mae pools along with other government loans, which are then sold on the secondary market. While we have had defaults under the program, we work closely with tribal leadership in each case to develop the optimal solution to resolve the default.
Through this program, we are able to help individuals—many of whom never thought they would own their own home—achieve the dream of homeownership.
Gilbert Gerst, Senior Vice President, Community Development Banking, can be reached at firstname.lastname@example.com.
Community Developments Investments is produced by the OCC's Community Affairs Department. Articles by non-OCC authors represent their own views and not necessarily the OCC's.
HUD's Section 184 Home Loan Guarantee Program
The OCC has published a fact sheet describing the U.S. Department of Housing and Urban Development's Section 184 Indian Home Loan Guarantee Program, which was authorized by the Housing and Community Development Act of 1992. Section 184 is one of the most important federal programs to help Native Americans obtain home mortgages. By guaranteeing home loans, the program encourages lenders to underwrite mortgages in Indian Country.
Section 184 loans offer many advantages:
The program has other conditions as well. For more information, read the Section 184 fact sheet. For information on how to become a Section 184 lender, read HUD's Lender Section 184 Resources or contact HUD's Office of Loan Guarantee at (202) 402-2402.
Community Developments Investments is produced by the OCC's Community Affairs Department. Articles by non-OCC authors represent their own views and not necessarily the OCC's.

subset: commoncrawl


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Duke learned earlier this week that if Mason Plumlee isn�t dominating, if Seth Curry�s shots aren�t falling or Quinn Cook isn�t performing to the elevated level he has reached this season, then Tyler Thornton is capable of coming to the rescue.
Especially if he�s mad.
Duke coach Mike Krzyzewski called Thornton �the hero of the game for us� after the Blue Devils disposed of rival North Carolina three nights ago.
�He would not let us lose,� Krzyzewski said, referring to the junior guard, who owned a scoring average of 3.3 points per game prior to facing the Tar Heels.
Thornton hit three 3-pointers � he had been 2-for-14 from beyond the arc in the previous eight games � and contributed nine points off the bench during Wednesday night�s victory, in what became his highest scoring output since Jan. 2.
His last two 3s were supplied during Duke�s 16-5 run that transformed a 38-31 deficit into a 47-43 lead and put the Blue Devils ahead to stay.
Even more pleasing to Krzyzewski was the fierceness with which Thornton played, the competitive fire that met the intensity of the rivalry game against North Carolina.
�I like him because he can get angry,� Krzyzewski said. �I think anger is an emotion that gets you passed being tired and gets you past a lot of things. If anger destroys something bad, it�s good.�
The 6-foot-1, 190-pound Thornton�s toughness was on display in the second half when, with Plumlee�s fouls becoming an issue, Duke went with a four-guard lineup to help counteract North Carolina�s downsized look.
There were moments when he jostled with the Tar Heels� 6-9 James Michael McAdoo in the post and battled 6-5 P.J. Hairston for rebounds.
�They�re a big team, big at every position,� Thornton said. �It�s heart and will to win.�
Who: No. 2 Duke (22-2, 9-2) at Maryland (17-7, 5-6)
When: 6 p.m. Saturday (ESPN)
Where: Comcast Center, College Park, Md.
Series: Duke leads 113-61. The Blue Devils have won six straight in the series and 12 of the last 13 meetings.
Tip-in: Duke will be playing its 201st game in a row as a Top 10-ranked team.


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Cooks Corner
Easy-to-make Nutella pie is sure to take the cake
Royal Bavarian Schnitzel Haus on the Kennedy Causeway (1085 NE 79th St., Miami) serves a tangy yet light German potato salad that makes a great dish to complement your Fourth of July barbecue.
I've included the recipe here, so you can try it at home if you can't make it over to Schnitzel Haus' tree-covered beer garden.
Start with the boiled-potato base, then add in optional ingredients like salty, savory bacon, tangy pickles, or refreshing cucumber slices.
Cookbook Corner
"I Brake for Pie" should be my bumper sticker. One of my pastimes is to search out fabulous pies at roadside stands and diners and standalone bakeries. My favorite pie sign said "Ho' made Pie" just outside Zion National Park in Utah, and my favorite bite was a warm peach pie with a cobbler-type top with fresh peach ice cream from an orchard off Interstate 81 in Georgia.
I'd rather eat pie than cake, and so my birthday wish is always for a peach pie. Or a blueberry pie. Or a chocolate pie. So I always approach pie cookbooks with enthusiasm. Two new ones stand out:
• The Nutella Pie recipe here is from"First Prize Pies"
by Allison Kave ($29.95
, Stewart, Taboori & Chang). The author entered a pie contest in Brooklyn on a whim, stole the show, then founded a successful bakeshop. These pies are approachable, inventive and enticing — 85 recipes in all — and the photos alone will make you want pie.
•"Ms. American Pie"
by Beth Howard ($28
, Race Point) is a little more kitschy with its subtitle: "Buttery Good Pie Recipes and Bold Tales from the American Gothic House," referring to the iconic Grant Wood painting. Howard once baked pies for celebrities in Beverly Hills (Steven Spielberg liked coconut cream), but went back home to Iowa, where she runs the Pitchfork Pie Stand in the house that's in the background of the painting. Her recipes are a fun mix of standbys like apple and Shaker lemon, but there's also pie in a jar and slab pie plus intriguing anecdotes and name dropping.
Sleuth's Corner
Q: My brother remembers a roasted chicken from George Diamond's that was so juicy. Is there any way to find this recipe? It would have been in the late 1950s or before 1964. We lived in Villa Park, Ill., and maybe once a year, as a special occasion, we would be able to join the adults at George Diamond's, usually in Antioch. My cousin and I always ordered the Mister-size steak, and everyone couldn't believe two little girls could eat it. But my brother loved the chicken and talks about it to this day. He turns 60 in September and I'd love to surprise him.
Pam White
A: We can certainly hope someone out there can help, but it seems the George Diamond's steakhouses — once scattered about the Midwest and in Las Vegas and California — have all closed. The founder died in 1982. The most famous George Diamond's was the original on Wabash Avenue in Chicago, which burned down in 2006. It was known, according to a story I found in the Chicago Tribune's archives, for its humongous salads as well as its steaks — and in your brother's case, its chicken.
I found another online musing by a 1950s-era busboy who worked at the Antioch location. He recalled that George's signature meal was a full charbroiled steak dinner with baked potato and salad for $1.95. The recipe here for the "French" dressing is from a December 2011 Tribune column by Bill Daley; he in turn credits the Chicago Sun-Times archives. It's actually a lot better than the lurid orange stuff known as French dressing that was pooled over iceberg lettuce and lingers in nightmares from my college waitressing days.
Send questions and responses to email@example.com or Food, The Miami Herald, 3511 NW 91st Ave., Doral, FL 33172. Replies cannot be guaranteed.


text:
Spotlight - SenSonic ToothBrush Waterpik
By Dr. Harold Katz – Bad Breath Expert
Posted: June 22, 2009
Posted: June 22, 2009
SUMMARY: The WaterPik Sensonic Professional is a terrific gadget that cleans your mouth more effectively than an ordinary toothbrush. It removes plaque, provides for healthier gums, and leaves your teeth feeling professionally-clean. Above all, it will save you money by reducing dreaded trips to the dentist!
When I was in dental school, I was trained to teach people the proper technique for brushing: Spend 30 seconds on each quadrant of your mouth and angle the brush in the appropriate way, making sure to hit the area where the gums meet the teeth. Back in the 70's, there were very few types of toothbrushes on the market.
But, today, as you walk down the oral care aisle of any supermarket or drug store, you'll see up to 50 different types of toothbrush styles, with varying handles, bristles, colors, etc. It can be extremely confusing. However, for the most part, it's safe to say that "a toothbrush is a toothbrush." As long as you are using a soft, nylon-bristled brush, you're in pretty good shape. The one glaringly obvious exception to this rule is when we're talking about a "power toothbrush." The manufacturers of power toothbrushes claim that they have plenty of studies that show that their power toothbrush will remove more plaque (and volatile sulfur compounds!) than brushing by hand.
Now, is it possible to get the same results with a manual toothbrush? Absolutely, but the reality is that most people are lazy brushers, and you can't make as many strokes in such a short period of time as you can with a power toothbrush. To take that even one step further, with the advent of technology it's now possible to brush with a sonic toothbrush, where its sonic waves can literally help blast away even more plaque and bacterial debris.
So what exactly do I like about the Waterpik Sensonic Toothbrush? Simple - it does an incredibly effective job at cleaning your teeth, while still being gentle on the gums and easy to use. It also has a 100% Satisfaction Guarantee. When I first opened up the Sensonic to try it out, I was pleasantly surprised with the "heft" of the toothbrush. It wasn't too big or bulky, but it had a good, professional feel. To me, it felt as if I had a professional dental instrument in my hand. Included are 2 different brush heads and they are color-coded (in case you're sharing your brush with another person such as a spouse or child).
My first use was extremely easy - you just have to let the unit charge for a while, but it really was as simple as plugging it in, puting on a brush head, and starting. The toothbrush is controlled by a single button in the middle of the device that selects 3 different "levels" of speed:
- Off
- Low (for gentle cleaning and gum massage)
- High (for superior plaque removal)
- Pressing the button simply toggles between those 3 levels of speeds.
Waterpik Highlights:
- Clinically-proven to remove more plaque than ALL sonic toothbrushes
- Advanced slim brush-head design
- Extra-soft, round-ended bristles
- Dual speeds
- 2-minute timer
- Recharge indicator light
- Includes 3 brush heads (2 advanced brushes and 1 interdental brush)
One nice feature was the built-in timer with a short automatic pause after 30-seconds (a reminder to start brushing your next quadrant!). This toothbrush automatically turns off after 2 minutes (i.e. 4, 30-second intervals). I have my own suspicions on what percent of people will be able to consistently brush for the entire 2 minutes (I'm guessing less than 15% of you!), however the reality is that although you SHOULD brush for 2 minutes, any amount of brushing at all with this toothbrush is better than none.
I do have one word of warning for you, and that is to make sure you turn off the toothbrush while the bristles are still inside your mouth! The Sensonic moves so quickly, that if you pull the toothbrush out of your mouth while it is still on, you will fling small droplets of toothpaste all over your bathroom mirror!
Overall, this is a very effective power toothbrush that I highly recommend as a standard part of every person (and families) daily oral care.
Oh, one more thing: Studies show that using a power toothbrush with "old-fashioned" toothpaste (the kind that contains sodium lauryl sulfate) will create more foam than a rabid dog. This will definitely make you stop brushing in about 9 seconds. So, if you're still not a TheraBreath (or any of our other) toothpaste user, now is the time.
Related Articles
Your Toothpaste May be Giving you Canker Sores (and bad breath)
Meet the NHL dentist who stitches smiles during Stanley Cup Playoffs
Lil Wayne: Bad Breath After 8 Root Canals?
Zac Efron says: To get rid of Bad Breath, Skip the Tuna and Onions
Jennifer Lawrence laughs about bad breath in 'The Hunger Games' kissing scenes
Win $100 in Products! Enter Here


text:
Game On! Sports Schedule for February 7, 2013
The Los Angeles Lakers and Boston Celtics rekindle one of the NBA's most iconic rivalries tonight, but with a completely different feel.
These two teams, who have so often reigned supreme in the NBA, are fighting for their postseason lives.
Tonight, these teams meet in Beantown in a nationally-televised tilt as they both continue to try and get their acts together. Both have been trying to overcome big injuries. The Celtics lost Rajon Rondo a few weeks ago for the season and now the Lakers are looking at life without Pau Gasol.
Here's a look at this evening's sports schedule. All times Eastern.
Los Angeles Lakers at Boston 8 p.m. (TNT)
Chicago at Denver 10:30 p.m. (TNT)
NCAA Men's Basketball Top 25
(1) Indiana at Illinois 7 p.m. (ESPN)
North Carolina State at (4) Duke 9 p.m.
Pepperdine at (6) Gonzaga 11 p.m.
Colorado at (19) Oregon 10 p.m. (ESPNU)
(21) Missouri at Texas A&M 9 p.m. (ESPN2)
Montreal at Buffalo 7 p.m.
Tampa Bay at New Jersey 7 p.m.
New York Islanders at New York Rangers 7 p.m.
Florida at Philadelphia 7 p.m.
Washington at Pittsburgh 7 p.m.
Calgary at Columbus 7 p.m.
Carolina at Ottawa 7:30 p.m.
Toronto at Winnipeg 8 p.m.
Detroit at St. Louis 8 p.m.
Los Angeles at Nashville 8 p.m.
Vancouver at Minnesota 8 p.m.
Chicago at Phoenix 9 p.m.


text:
Plan keywords, synonyms, and Best Bets (SharePoint Server 2010)
Applies to: SharePoint Server 2010
Summary: Learn how to plan keywords, synonyms, and Best Bets so users get the most relevant search results for popular queries.
This article describes how to help users obtain more relevant search results by planning for keywords, synonyms, and Best Bets in Microsoft SharePoint Server 2010.
Keywords are search terms that users type into a search box when constructing a query. Users can use them in queries that they submit in the search box on a site, on the Search Center, or in an Advanced Search. When a user query includes a keyword that you have configured, the search results can provide a definition for the term together with links to recommended locations or documents at the top of the search results page.
You can define keywords, provide synonyms (words that closely relate to the keyword), and create Best Bets (links to featured documents or locations for the specified keyword), to provide a relevant set of search results for popular search terms. Synonyms are useful when several search terms are used for the same concept and content so that search results are merged and not scattered across several search terms. When you create a keyword, you can also provide a definition of the keyword that appears in search results. By defining terms that are often used in searches as keywords, a site collection administrator can provide a standard glossary of names, processes, and concepts that are part of the common knowledge shared by members of an organization. When keywords have synonyms and associated Best Bet links, they help guide users to recommended resources. The list that is updated when a site collection administrator creates keywords and adds synonyms is called a thesaurus. The thesaurus for SharePoint Server 2010 is compatible with the thesaurus for Microsoft Office SharePoint Server 2007.
Site collection administrators typically create keywords at the site collection level. However, you might want to coordinate keyword planning over multiple site collections to make planning and implementation consistent throughout the organization.
If you already have search set up in your production or test environment, you can use Site Collection Web Analytics Reports to help you plan keywords, synonyms, and Best Bets. The reports that are most useful for this effort include the following:
Top Queries, to view the most common search terms.
No Results Queries, to view the most common search terms that yielded no search results.
Best Bet Usage, to view the most frequently-used Best Bets.
Best Bet Suggestions, to view the suggestions for new Best Bets that the search system provides.


text:
M. Joan McCarthy ascended out of the ranks of the insurance industry when an available part-time position at a local alumni organization inspired change — in more ways than one. The career move in 1983 to work in association management at the Northeast Ohio arm of the Harvard Business School Club was a refreshing switch for Ms. McCarthy. But it also motivated her to start her own association management company after she realized a need for that type of service existed. Twenty-five years later, the president and owner of MJM Services is overseeing operations and event planning for 26 professional and alumni organizations — including Harvard Business School Club, Association for Corporate Growth's Cleveland chapter and National Association of Estate Planners and Councils, the latter of which has 220 councils nationwide. In 2010, Ms. McCarthy was awarded the ACG President's Award for Excellence in Association Management, and this year, ACG Cleveland garnered chapter of the year out of 57 chapters worldwide. "We are the back office for all our clients," Ms. McCarthy said. "Once the content of a meeting is established, we do everything from creating the invitations to sending material to members, and coordinating whatever needs to be done to organize and execute an event." The 10-employee Cleveland firm also manages accounting and other financial services for its clients, which are judiciously selected. "We do quite well with our existing clients referring us to other organizations. We continue to grow, but we only take one or two clients a year," she said, noting the assimilation process is comprehensive and sometimes time-consuming. "From our perspective, it's getting used to what a client's system is (for organizing and executing events) and integrating that system" into MJM Services' operations, she said. The Harvard Business School Club's global alumni conference in 2001 serves as an example of MJM Services' capabilities. That event drew 1,000 attendees representing 45 countries to Cleveland, where Ms. McCarthy's firm coordinated visits to cultural gems such as Severance Hall and the Rock and Roll Hall of Fame and Museum. Attendees toured NASA, swung clubs at Firestone Country Club in Akron and even witnessed an open heart surgery at the Cleveland Clinic. "It was only the fifth time (the conference) had been held in the U.S. at that time," Ms. McCarthy said. "We were the smallest market to have hosted that event, and to this day that conference drew the highest number of alums." Her community outreach includes current membership on the Notre Dame College board of trustees. "She was a superb board chair, is a great resource and is a great source of strength," college president Andrew Roth said. "She's unflappable. "Her tireless work on behalf of the college and its students has literally empowered the college to change students' lives," he said. Ms. McCarthy served for 13 years on the board of directors for Golden Age Centers. She has reconstructed four generations of family roots through genealogy — one of her hobbies — and enjoys reading biographies. Her other passion is traveling. Ms. McCarthy has been to such destinations as Australia, South Africa, Peru, Argentina, Uruguay and Brazil. This summer's agenda includes Scandinavia, Sweden and Finland. In fact, her travels coincide with this year's Crain's Cleveland Business Women of Note luncheon this Wednesday, July 25. "I'll be in Estonia that day," she said.
M. Joan McCarthy
President and owner, MJM Services
Recommended for You


text:
Find hotels & motels in Maplewood using the list below. Find cheap and discounted hotel/motel rates in or nearby Maplewood, NJ for your corporate or personal leisure travel. We list the best Maplewood New Jersey hotel/motel rooms. Review the Maplewood hotel list below to find the perfect lodging. We also have a map of the Maplewood hotels.
The Maplewood center is approximately 1 mile southwest of Seton Hall University and 2 miles south of Turtle Back Zoo.
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A comparison of cartilage and fascia in tympanoplasty for chronic noncholesteatomatous diseases of middle ear
Suche in Medline nach
|16. April 2009
Objective: To compare cartilage with fascia grafting in reconstruction of the eardrum after surgery for chronic noncholesteatomatous diseases of middle ear with respect to postoperative drum retraction and perforation and the hearing results.
Material: Between Ianuary 2002 and December 2005 a total of 74 patients aged 18 to 55 underwent surgery for noncholesteatomatous diseases of middle ear. The eardrum was reconstructed using cartilage palisades or cartilage composite grafts in 32 cases and temporalis fascia in 42 cases. Postoperatively the patients were evaluated by otomicroscopy and audiometry.
Results: All patients in the palisade group attended the follow-up examinations for at least one year. In the fascia group there were 2 patients that did not attend the follow-up examinations. In the cartilage group the mean follow up period was 20 months and 29 months in the fascia group. Two perforations (6%) and 4 (12%) retractions were found in the cartilage group versus 5 (12%) perforations and 6 (14%) retractions in the fascia group at the follow up. The hearing results were quite the same in the two groups.
Conclusions: The comparison of fascia and cartilage for drum reconstruction after chronic noncholesteatomatous diseases of middle ear in adults indicates a slight advantage for the cartilage techniques in respect to prevention of drum retraction and perforation. The hearing results were quite the same in the two groups.


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Handspun from the finest silk yarns using two colour threads in beautiful and intricate motifs. Different colours and designs make the piece look beautiful and attractive.
Kindly Note : Their might be slight variation in colour from digital image to actual piece. Dispatched in approximately 7 Working Days. To save on shipping charges buy multiple products.


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BELMONT � After Saturday�s home doubleheader with North Greenville was postponed, Belmont Abbey�s basketball team enters a huge week as it tries to win its second senior college regular season championship.
The Crusaders (17-6, 10-5) enters Monday night�s 7:30 p.m. makeup game against North Greenville in fourth place of the Conference Carolinas standings, but only 1 1-2 games behind league-leading Barton (17-5, 12-4).
King (17-6, 12-5) is close behind in second, with Limestone (15-7, 11-5) in third, with Coker (12-10, 9-7), Mount Olive (12-10, 9-7) and Queens (12-10, 9-7) all tied for fifth.
After hosting ninth-place North Greenville (9-12, 5-11), the Abbey hosts Mount Olive on Wednesday, then visits 10th place Lees-McRae (2-20, 2-14).
After this week, the Crusaders visit Barton Feb. 26 before closing the regular season March 1 at Coker.
In its school history, Belmont Abbey has won or shared six conference regular season championships dating to 1928, but only one senior college conference title. That championship came in the 2001-02 season when the Crusaders shared the Conference Carolinas regular season title.
Women�s race
The Lady Crusaders also are in a tight race, but have seen their regular season titles hope evaporate because of Limestone�s (20-2, 17-1) near-perfect start to its league slate.
The Abbey (10-11, 9-8) is currently in seventh, but can move into the top four � and homecourt advantage in the opening round of the upcoming league tournament � with a fast start to the end of the year.
Barton (16-6, 15-3) is in second, with Pfeiffer (19-4, 14-4) in third, Queens (13-9, 11-7) in fourth and Coker (14-10, 10-8) and Mount Olive (14-8, 10-8) tied for fifth.
Monday�s 5:30 p.m. opponent, North Greenville (8-13, 6-11), is in ninth. After hosting Mount Olive on Wednesday, the Lady Crusaders visits 10th-place Lees-McRae (8-13, 6-12).
Rare postponement
Saturday�s postponement was only the seventh due to weather in the past 10 seasons.
The last postponement came late in January 2011 when the Crusaders� game at Lees-McRae was pushed back one day.
Youth Hoops Summit
Every Gaston County recreation basketball 12 years old and younger gets in free with their team�s jersey for Wednesday�s doubleheader with Mount Olive.
Wednesday�s promotion caps a year in which the towns of Belmont, Cramerton, Dallas and Stanley have been honored among others.
Stanley Community Night will be held Monday after being postponed on Saturday.
Richard Walker: 704-869-1841; twitter.com/JRWalk22
Crusaders titles
Belmont Abbey basketball regular season championships:
(North Carolina Junior College Conference)
1928-29 5-1 champion
1930-31 5-1 co-champion
1931-32 3-1 champion
1937-38 12-0 champion
1938-39 8-1 champion
(Conference Carolinas)
2001-02 16-4 co-champion
Belmont Abbey basketball tournament championships:
(North Carolina Junior College Conference)
1935 d. Brevard 31-17 at Charlotte
1938 d. Campbell 32-20 at Davidson
1939 d. Campbell 46-28 at Gastonia
1941 d. Lees-McRae 47-38 at Gastonia
1949 d. Campbell 41-38 at Asheville
(Carolinas AAU)
1954 d. Camp Lejeune 93-83 at Shelby
(NAIA District 26)
1962 d. Erskine 79-58 at Spartanburg, S.C.
1988 d. High Point 85-70 at High Point
(Conference Carolinas)
2002 d. Queens 78-60 at Fort Mill, S.C.
2003 d. Pfeiffer 73-68 at Pfeiffer


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Animal Control Hoboken, NJ
Our trained animal control experts provide same day animal control and are well-versed in the removal of many species of animals. In our animal control experiences, we have performed animal removal on animals in fear, infected with rabies, or who have made your home their home. In each instance, we advise that you not attempt animal control in NJ on your own. We are committed to your satisfaction and well-being. While most animals are simply scared by human contact, this can trigger defensive measures that can lead to injury.
Animals can sometimes become violent when they feel that they are being attacked. Our animal control professionals approach each creature without making it feel defensive or scared so that we can get it out of your house without hassle or danger to you. Once we have trapped an animal, or animals, from your home or office space, our human animal control in NJ transports the animal to an area far from your home for release. We believe that each animal we capture should be treated with respect and do not seek to harm animals during our animal control process.
Alco Animal & Pest Control is available for emergency animal control in NJ. When an animal has entered your home and is behaving violently, you should call for animal control services immediately. Once we arrive and remove the animal from your premises, we will locate the animal's entry and exit point to safeguard your home from further intrusion. Our animal control professionals are knowledgable in the behavioral patterns of animals, knowing where to look in your home for each species we encounter. When you call Alco Animal & Pest Control, you receive prompt removal and attention to detail to keep you and your family safe.
Alco Pest & Animal Control has the experience and knowledge to make sure your home is free from unwanted visitors. From squirrels to raccoons and everything in between, we will carefully remove animals from your home or business so that both you and the animals are safe.


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July 2008
"The goal is to help educators act now to help schools in every stage of improvement. We must take dramatic action to improve our lowest-performing schools."
— U.S. Secretary of Education Margaret Spellings
In March 2008, Secretary Spellings announced a differentiated accountability pilot to allow states to distinguish between those schools in improvement that need substantial help and those close to meeting achievement goals. After six years of NCLB implementation, the data has shown the extent of the academic achievement problems leading to a school's identification differs widely within states.
Differentiated accountability will allow states to vary the intensity and type of interventions to match the academic reasons that lead to a school's identification. In addition, some states and districts have a large percentage of their schools identified, impacting capacity to provide meaningful, intensive reforms. Differentiated accountability will assist those states by targeting resources and interventions to those schools most in need of intensive interventions and significant reform.
After a panel of outside experts reviewed applications for the pilot, Secretary Spellings approved models from Florida, Georgia, Illinois, Indiana, Maryland, and Ohio. Illinois' approval is conditioned on the state demonstrating that the assessments administered in 2007-08 are fully compliant with NCLB. In return for this flexibility, states participating in the pilot must commit to build their capacity for school reform; take the most significant actions for the lowest-performing schools, including addressing the issue of teacher effectiveness; and use data to determine the method of differentiation and categories of intervention.
- 17 states submitted a differentiated accountability proposal: Alaska, Arkansas, Florida, Georgia, Illinois, Indiana, Louisiana, Maryland, New Jersey, New York, North Dakota, Ohio, Oklahoma, Pennsylvania, South Carolina, Tennessee, and Virginia.
- The Department submitted the proposals of all 17 states to a peer review panel of nationally recognized experts. These proposals, additional information about the pilot, and Department letters to these states may be found online at http://www.ed.gov/admins/lead/ account/differentiatedaccountability/index.html
- In June 2008, the peer teams began reviews of state proposals and met with State representatives via conference calls. On June 13-14, 2008, the peer panel met in Washington DC to review each state's differentiated accountability proposal using the Department's Peer Review Guidance, which can be found at http://www.ed.gov/policy/elsec/guid/daguidance.doc. The experts invited to participate represent a wide range of perspectives from academia to the private sector to state and local organizations. The expert review panel included Dr. Margaret (Macke) Raymond (Chair), Stanford University; Dr. Chris Cobitz, Charlotte Mecklenburg School District; Sheila Evans-Tranumn, New York Department of Education; Dr. Pete Goldschmidt, California State University, Northridge; Raul Gonzalez, National Council of La Raza; Gary Huggins, Aspen Institute; Dr. Jacquelyn Jackson, former U.S. Department of Education Director of Title I; Jim Lanich, California Business for Education Excellence; Dr. Maggie McLaughlin, University of Maryland; Peter McWalters, Rhode Island Commissioner of Education; Jim Peyser, New Schools Venture Fund; Dianne Piché, Citizens Commission on Civil Rights; Rachel Quenemoen, University of Minnesota National Center on Educational Outcomes; John Winn, former Florida Commissioner of Education; and Dr. Martin West, Brown University.
- After considering the peers' comments, the Secretary has approved six states to participate in the differentiated accountability pilot. The approved states include: Florida, Georgia, Illinois, Indiana, Maryland, and Ohio.
- As a condition of participation, the states must share data on how the differentiated accountability model is implemented and its effects on student achievement.
- March 2008 — The Department announced the eligibility criteria for states to apply for the differentiated accountability pilot program.
- May 2, 2008 — Deadline for states to submit differentiated accountability proposals.
- June 2008 — Peer review of differentiated accountability proposals from Alaska, Arkansas, Florida, Georgia, Illinois, Indiana, Louisiana, Maryland, New Jersey, New York, North Dakota, Ohio, Oklahoma, Pennsylvania, South Carolina, Tennessee, and Virginia.
- July 1, 2008 — The Department approves 6 states to participate in the differentiated accountability pilot program for 2008-09.


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In a period of angry frustration at his native Newfoundland – "… what cripples the vast majority of our culture and society here is the fact that we dont quite know what to be angry about. We never know where to throw the punch." – and inspired by a
t-shirt f-ing the many icons of New York City, writer and performer Joel Thomas Hynes sat down to write his own.
The rest, as they say, is history: "… I got a little carried away. Suddenly I was writing a quilt. Maybe a sail for a boat. Maybe a manifesto." His reworked piece wound up on stage, at a 2006 fundraiser for the Resource Centre for the Arts in St John's. Recorded (but not broadcast) by the CBC – "And f*** the CBC for not having the nuts to put this on the radio," reads the final line in the revised work – God Help Thee: A Manifesto first appeared in print, with an accompanying postscript, in the Fall 2008 issue of Riddle Fence, and later in Maisonneuve Magazine. Very little escapes Hynes' expletive-laced wrath, which reads both as backlash against the idyllic quaintness of Newfoundland tourism campaigns, and ode to a place both home and heart.
In June 2011, Running the Goat Books and Broadsides published the manifesto in chapbook form in a limited edition of 375, which promptly sold out: hand typeset (an entertaining challenge, given the unprecedented number of "F"s and "k"s), letterpress printed, hand tinted and hand sewn.
Featuring impeccable wood engravings by Abigail Rorer, this perfectly packaged diatribe is now in its second printing and is available at Swipe for just $29.95 – plenty of f*** for your buck. (2011; 2nd printing 2012: Running the Goat Books and Broadsides; ISBN 9780986611322)
Word on the street is that the book's profanity-decorated watermark-effect pages will soon be available in notebook form… We'll keep you posted.
Oh, and if you like your swearing live, you can download an audio version of God Help Thee from the Rattling Books website.


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HX-80N - Extremely Stable High Mount Outdoor Curtain PIR
The new HX-80N from Optex is an 80' x 6', high mount outdoor passive infrared detector that provides the stability and reliability necessary for an outdoor PIR sensor. The most important element in reliable outdoor detector is accuracy to distinguish a human from a small animal. The exclusive pyro element on board enables the HX to project an ideal detection pattern, thus allowing for more accurate detection of humans and less false alarms. In addition, the HX-80N's dual PIR's and 20 detection zones utilize the 'AND' detection pattern technology - upper and lower detection areas have to be activated in order to generate an alarm condition. This technology helps to prevent false alarms caused by a pet or small animal. The HX Series' detection length can be limited to avoid unwanted detection, and it's short range zones can be masked if needed. By limiting the detection range, false alarms due to unwanted movement (cars, persons or animals outside the protected area) can be eliminated.
HX-80NAM - Includes Digital Anti-Masking
The HX-80NAM includes all the great features of the HX-80N but comes with a Digital Anti-Masking feature. When an object is placed close to the lens surface for a period of more than 180 seconds, the IR Anti-Masking circuit will activate and generate a trouble signal.
- Compatable with most manufacturer's wireless systems (HX-80NRAM)
- Includes Inovonics EchoStream EN1941 and battery pre-installed (iSERIES HX-80NRAMi)
- Active IR Digital Anti-Masking
- Intelligent 'AND' logic with unique pyro-element
- Summer Night Compensation logic
- Double Conductive Shielding
- Low current draw
- Vegetation Sway Analysis logic
- Advanced temperature compensation logic
Please Note: Manufacturers Wireless Transmitter Required
Transmitter Compatibility List: (Visonic: MCT302) (DSC: WS4945) (Ademco: 5816WMWH or 5816MN) (ITI 60-362-10-319.5) (Caddx NX-650) (Rokonet WT71M433USA)
Additional Info
Additional Info
|Part Number
|What's in the box
|(1) Optex 80' Long & Narrow Range High Mount Wireless Outdoor PIR
Write Your Own Review
|Detection Method
|PIR w/ Anti-Masking
|80ft. x 6.7ft. (24m x 2m) narrow, 20 Zones
|PIR Distance Limit
|22ft, 33ft, 42ft, 59ft, 80ft (6.5m, 10m, 13m, 18m, 24m)
|3.6°F at 2ft/s
|Detectable Speed
|1ft -5ft/s
|Power Supply
|Current Consumption
|40mA max. at 12V DC
|Alarm Period
|Approx 2.0 sec
|Alarm Output
|FormC 28VDC .2A (max)
|Trouble Output
|N.C. 28VDC, .1A max
|Tamper Output
|N.C. 28VDC .1A max., N.C. when cover is removed
|Aux Input
|N.C. 28V DC, .1A max
|Warm Up Period
|Approx. 60 sec.
|LED Indicator
|Red: Warm up, Alarm, Trouble
|Operating Temperature
|-4°F to 140°F (-20˚C to +60˚C)
|Environmental Humidity
|95% max.
|RF Interference
|No Alarm 10V/m
|Mounting Height
|8.ft - 10ft (2.5m - 3m)
|1lb 9oz (720g)
|Dimensions (H x W x D)
|7.78in x 3.66in x 11.26in


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Accel Gel 24 Packets w/Caffeine-Raspberry Cream
Click to enlarge
DetailsExtends Endurance Speeds Muscle Recovery Provides More energy
IngredientsIngredients: Water maltodextrin whey protein isolate fructose sucrose salt citric acid malic acid ascorbic acid natural flavor vitamin E acetate sodium benzoate and potassium sorbate (preservatives)Red 40 Blue 1.
InstructionsFor best results consume contents and follow with water.
WarningsContains: Milk. Manufactured in a facility that processes eggs wheat soy peanuts and almonds.
Nutrition Label
|Nutrition Facts
|Serving Size 1 packet
Servings Per Container 24
|Amount Per Serving
|Calories 90
|Calories From Fat 0
|% Daily Value *
|Cholesterol 0mg
|Dietary Fiber 0g
|Potassium 65mg
|Protein 4g
|Saturated Fat 0g
|Sodium 90mg
|Sugars 7g
|Total Carbohydrate 16g
|Total Fat 0g
|Trans Fat 0g
|Vitamin A
|Vitamin C
|Vitamin E
|* The Percent Daily Values are based on a 2,000 calorie diet, so your values may change depending on your calorie needs.The values here may not be 100% accurate because the recipes have not been professionally evaluated nor have they been evaluated by the U.S. FDA.
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Inspired by Ship Shape from designers Paula Barnes and Mary Ellen Robison of Bonnie Blue Quilts
Quilt tester: Laura Boehnke
1-1/4 yards cream batik (blocks, border No. 2)
1-1/3 yards total assorted blue batiks (blocks, border No. 2)
3/8 yard golden tan batik (blocks, border No. 3)
7/8 yard light brown batik (blocks)
1/2 yard dark brown batik (border No. 1)
1-3/4 yards dark blue batik (border No. 4, binding)
3-7/8 yards backing fabric
69" square batting
Finished quilt: 60-1/2" square
Finished blocks: 10" square
Quantities are for 44/45"-wide, 100% cotton fabrics.
Measurements include 1/4" seam allowances. Sew with right sides together unless otherwise stated.


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Two Witnesses of Truth
What a blessing it is to have an account of the mission of our Lord and Savior declared in the Book of Mormon to add a second witness to the doctrine declared in the Bible. Why is it important for the world to have both the Bible and the Book of Mormon? I believe the answer is found in the 13th chapter of 1 Nephi. Nephi records: "And the angel spake unto me, saying: These last records, which thou hast seen among the Gentiles [that is, the Book of Mormon], shall establish the truth of the first [which is the Bible], which are of the twelve apostles of the Lamb, and shall make known the plain and precious things which have been taken away from them; and shall make known to all kindreds, tongues, and people, that the Lamb of God is the Son of the Eternal Father, and the Savior of the world; and that all men must come unto him, or they cannot be saved" (1 Nephi 13:40).
Neither the Bible nor the Book of Mormon in and of themselves is sufficient. Both are necessary for us to teach and learn about the complete doctrine of Christ. The need for the other does not diminish either one of them. Both the Bible and the Book of Mormon are necessary for our salvation and exaltation.


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fish & game
division cases
This information was filed in the fish and game division of Marion County District Court. All fines include court costs.
Timothy G. Bentz, Marion, May 3, boating and water activities, $246.
Christopher W. Grant, Burns, Dec. 3, possession of wildlife or certain devices, $322.
Tyler Houston Pollock, Lebanon, Missouri, May 3, boating and water activities, $196.


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Cape Fear Animal Hospital
Your Veterinarian in Fayetteville, NC
Any glimpse into the life of an animal quickens our own and makes it so much the larger and better in every way. - John Muir, Naturalist
Cape Fear Animal Hospital's mission is to provide compassionate medical care to our patients, to give excellent service to our clients, and to nurture the remarkable bond and understanding between our human clients and our animal patients.
Cape Fear Animal Hospital is a well established, full service small animal hospital offering a range of medical and surgical services in Fayetteville, North Carolina; we even offer pet boarding. Our experienced team of veterinarians and support staff proudly serve the surrounding communities of Spring Lake, Raeford, Hope Mills, Lillington, Stedman, Autryville, St Pauls and Red Springs. We welcome you to our practice; it is our daily privilege to provide compassionate and competent veterinary care to your pet. Our goal is to be a positive impact on our patients, clients, and the community.
Cape Fear Animal Hospital offers medical, surgical, and dental care for dogs and cats. We offer a variety of medical services including general wellness exams, dentistry, spays and neuters, pain management, an on-site pharmacy and basic grooming (baths, nail trims and nail dremels). We also provide a full scale health program for your pet that includes annual preventative care exams, vaccinations, and parasite control. We strive to offer optimal veterinary care, thus enabling you to enjoy your companion for a maximum number of years.
At Cape Fear Animal Hospital, we believe quality yet affordable veterinary care should be available to all animals in the greater Fayetteville area. To schedule an appointment, call us on the number listed above or request an appointment online. Also be sure to check out our online specials. Our team of skilled veterinary staff looks forward to helping you and the health of your pet.
Have you heard of canine influenza or H3N2? There have been recent confirmed cases in 8 states and while not transferrable to humans, it is highly contagious to dogs. In some cases, dogs may not show symptoms but be carriers of the infection for up to 24 days. You can find information regarding Canine Influenza by clicking here, including symptoms and prevention tips. If you have any questions or concerns, please do not hesitate to give us a call and we would be happy to speak with you!
Pain Management
In recent years, veterinarians have made great progress in understanding how animals feel pain. Read More >
Refer a Friend!
The highest compliment you can pay us is to recommend us to your family and friends! In return, we would like to say thank you by crediting your account $25 each time a new family member or friend brings their pet in for the first time. Read More >
Routine Check-Ups
Wellness exams are a simple and effective way of monitoring your pet's health. Early detection and correction of medical problems will help to ensure that your pet will love a long, healthy and active life. Read More >


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The Intersection of Neuroscience and Philosophy - On Our Mind
Date: 3/17/2014; 20 minutes
Is there a science of the soul? Does how we think about the brain define how we think about ourselves? Patricia Churchland, B. Phil., LLD (hon), Professor Emeritus, Department of Philosophy at UC San Diego, joins William Mobley, MD, PhD for a deeper look at the connections between neuroscience and philosophy.
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