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Off the back of its 2001 contract to modernize the U.S. Air Force's C-130, Boeing is offering its avionics modernization program (AMP) as a scalable architecture kit to extend the service life of the ubiquitous military transport. According to the company, more than 700 aging C-130s that could benefit from the upgrade are still in service. However, other industry sources say the actual worldwide market for the package would likely be little more than one third of that number, based
on financial costs, available resources and airframe viability.
The initial AMP program for the USAF fleet was intended as a "full boat" comprehensive package, but the available upgrade system was designed to be scalable so customers could have the flexibility to perform the modifications on an incremental basis rather than all at once. There are multiple benefits to the AMP, according to Boeing. These include a digital, all-glass cockpit, night-vision imaging system compliance, and communication navigation surveillance system/air traffic management, which will allow the aircraft to meet civil navigation safety mandates.
Given the numerous models and variants of the versatile "Herc," the AMP also offers operators the opportunity to standardize the cockpit configurations, thus increasing crew flexibility and reducing the amount of specialized training required. While the program is aimed primarily at the C-130E and H models–out of the 1,693 produced by Lockheed, more than 1,200 are believed to still be flying–more antiquated models such as As and Bs would need to be evaluated on a case-by-case basis.
According to the current low rate initial production plans, 26 AMP kits will be produced–11 to be installed by Boeing, 11 by the USAF; the remaining four sets will be offered for bidding in two pairs to other contractors to foster competition for the installation contracts. The first USAF aircraft to be upgraded, an H model, completed its 100th flight last month, the halfway milestone in the aircraft's flight-test program.
Another AMP C-130 is also undergoing testing at Edwards Air Force Base in California, while a third is currently in the process of being upgraded and modified at Boeing's support systems facility in San Antonio, Texas. In August 2006, Sweden became the first international customer for the program, with a $19.8 million contract for the engineering manufacturing development for one Swedish Air Force C-130H. The aircraft is scheduled to arrive at Boeing's San Antonio facility in September. A production contract to modify six additional Swedish C-130s is currently in the planning stages.


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Principles of Population Genetics
This work gives a presentation of theory and observation for students at the undergraduate and graduate level. It introduces the principles of genetics and statistics that are relevant to population studies, and examines the forces affecting genetic variation from the molecular to the organismic level. Integrated throughout the book are descriptions of molecular and other methods used to study natural populations as well as theory using actual data. Applications of the principles discussed are illustrated by worked examples.
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Widening the probe into Solyndra's collapse, House Republicans at a hearing Wednesday released emails showing that White House aides pressured budget officials to finalize a decision on a $535 million loan guarantee to the solar panel maker because they were eager to have Vice President Joe Biden announce the news at Solyndra's 2009 groundbreaking ceremony in Fremont.
But while the released emails indicated the White House was eager for a decision on the loan, they do not reveal that the Obama administration pushed for a particular outcome. Nor did they contain evidence that George Kaiser, a prominent Obama fundraiser and visitor to the White House, had any direct influence or involvement in the Solyndra loan.
Many conservative critics have focused on Kaiser because Argonaut Venture Capital, the investment arm of the Tulsa, Okla.-based George Kaiser Family Foundation, is Solyndra's largest private investor. They speculate that Solyndra's loan was either approved or expedited at the request of Kaiser and other political donors to President Barack Obama's 2008 presidential campaign.
The bitter bipartisan divide on Capitol Hill was clear in the four-hour hearing. Republicans on the House Energy and Commerce Committee hammered the administration's support of Solyndra as "crony capitalism run amok," while Democrats argued that the United States is losing the cleantech race to China and that Republicans were trying to discredit clean energy just as they have dismissed the scientific evidence of climate change.
Under questioning from Rep. Henry Waxman, D-Los Angeles, both Jonathan Silver, director of the Department of Energy's Loan Programs Office, and Jeffrey Zients, deputy director of the Office of Management and Budget, testified that they have never met or spoken with Kaiser.
But the two officials faced fierce questioning from House Republicans, who questioned the process by which Solyndra's original loan was approved as well as the Department of Energy's decision to restructure the debt when Solyndra was running out of cash earlier this year. And they raised concerns about pending Energy Department loans to cleantech companies. The department has about $10 billion left to spend before the loan program, which is funded by the federal Recovery Act, sunsets Sept. 30.
"Is Solyndra one bad bet or the tip of the iceberg?" Oversight and Investigations Subcommittee Chairman Cliff Stearns, R-Fla., asked in his opening statement.
The FBI and investigators with the Department of Energy's Inspector General's Office raided Solyndra's offices last week. While the search warrant affidavit remains under seal, many speculate that investigators are looking for evidence that Solyndra defrauded the government by misstating sales and revenue projections. Silver and Zients both testified that they do not know what triggered the raid.
Solyndra's loan was originally submitted in 2006, when President George W. Bush was in office, and made its way through an often cumbersome three-year interagency vetting process.
Intense pressure
The released emails show that some officials in the Office of Management and Budget felt they were under intense pressure to wrap up the process. "We would prefer to have sufficient time to do our due diligence reviews and have the approval set the date for the announcement rather than the other way around," an unnamed OMB aide wrote in an email to Biden's office.
The pressure the budget office felt apparently was the result of the Obama administration's eagerness to show its support for clean technology. In August 2009, four days after an independent credit agency issued its risk rating for the Solyndra deal, a special assistant to former White House Chief of Staff Rahm Emanuel emailed OMB and DOE staff and asked "as the closing of the Solyndra deal nears, we want to think about the potential announcement value in this. We know that the conditional agreement was already announced in March. That said, the VP will be in California in early September, and want to see if it's worth doing something here."
While Republicans alleged the White House emails revealed pressure for approval for the loan, Zients said they merely concerned "scheduling logistics."
"This had nothing to do with the decision to give the loan to the company or not," he said.
At Solyndra's groundbreaking Sept. 4, 2009, Energy Secretary Steven Chu and former Republican Gov. Arnold Schwarzenegger were in attendance, while Biden spoke via satellite.
Serious ramifications
Brian Harrison, Solyndra's CEO, and Bill Stover, Solyndra's chief financial officer, are expected to appear before the committee Sept. 23. The two did not appear Wednesday because they are seeking a buyer for the company and its assets as part of the bankruptcy proceedings. Many speculate that the two will plead the Fifth Amendment rather than testify.
House Republicans also want to invite Chu and OMB chief Jacob Lew to testify.
In a further widening of the Solyndra probe, the Treasury Department's inspector general is investigating the Federal Financing Bank's role in the loan, Bloomberg News reported Wednesday. Solyndra drew down $527 million of the $535 million before filing for bankruptcy.
Whatever the outcome of the Solyndra saga, political observers say it already has damaged Obama.
"We don't know yet whether this was an intentional effort to get around the rules or just a bad decision," said Dan Schnur, a former Republican strategist and director of the Jesse M. Unruh Institute of Politics at the University of Southern California. "But sometimes bad decisions have just as much impact as political scandals. You didn't hear the president talk about green jobs or clean technology in his speech to Congress last week. There may not be a scandal, but there are still serious political ramifications."
Contact Dana Hull at 408-920-2706. Follow her at Twitter.com/danahull.


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Future Uplifting Trance For Spire
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|47th week of 2008 patent applcation highlights part 16
|Patent application number
|FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN - An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region.
|PACKAGE AND PACKAGING ASSEMBLY OF MICROELECTROMECHANICAL SYSYEM MICROPHONE - A package of a MEMS microphone is suitable for being mounted on a printed circuit board. The package includes a substrate, at least one MEMS microphone, and a conductive sealing element. The MEMS microphone is arranged on the substrate, and electrically connected to a conductive layer on a bottom surface of the substrate. The conductive sealing element is arranged on the substrate and around the MEMS microphone for connecting the printed circuit board, and constructs an acoustic housing with the printed circuit board and the substrate. The acoustic housing has at least one acoustic hole passing through the substrate. The acoustic hole has a metal layer on the inner wall thereof for connecting the conductive layer on the bottom surface of the substrate to another conductive layer on the top surface of the substrate.
|Electronic Device Comprising a Mems Element - The device (
|PHOTOSTRUCTURABLE GLASS MICROELECTROMECHANICAL (MEMs) DEVICES AND METHODS OF MANUFACTURE - A Film Bulk Acoustic (FBA) MEMS device in a wafer level package including a photostructurable glass material and methods of manufacture are described.
|SEMICONDUCTOR DEVICE - A lower electrode is formed over a semiconductor substrate via an insulator film, first and second insulator films are formed to cover the lower electrode, an upper electrode is formed over the second insulator film, third to fifth insulator films are formed to cover the upper electrode and a void is formed between the first and second insulator films between the lower and upper electrodes. An ultrasonic transducer comprises the lower electrode, the first insulator film, the void, the second insulator film and the upper electrode. A portion of the first insulator film contacting with the lower electrode is made of silicon oxide, a portion of the second insulator film contacting with the upper electrode is made of silicon oxide and the first or second insulator film includes a silicon nitride film positioned between the upper and lower electrodes and not in contact with the upper and lower electrodes.
|MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on the first plug, including a plurality of stacked layers, and configured to hold information in accordance with an internal magnetization state, a first signal line formed on the recording element, a second plug formed on the second impurity diffusion region, an electrical conductor formed on the second plug, an area of a shape of the electrical conductor, which is projected onto the surface of the substrate, being larger than that of a shape of the recording element, which is projected onto the surface of the substrate, and a second signal line formed on the electrical conductor.
|RADIATION IMAGE DETECTOR - A thermal deformation preventing layer is located between a recording photoconductive layer, which contains a-Se as a principal constituent, and a crystallization preventing layer, which is constituted of an a-Se layer containing at least one kind of element selected from the group consisting of As, Sb, and Bi. The thermal deformation preventing layer is constituted of an a-Se layer containing at least one kind of specific substance selected from the group consisting of a metal fluoride, a metal oxide, SiO
|SEMICONDUCTOR DEVICE HAVING IMAGE SENSOR - A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area.
|Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. The image sensor comprises a pixel region defined on a substrate, an interlayer dielectric on the substrate and comprising a trench above the pixel region, a color filter within the trench, and a microlens on the color filter.
|Image Sensor and Method of Manufacturing the Same - An image sensor and method for manufacturing the same are provided. The image sensor can include a semiconductor substrate, a metal interconnection layer, a light-receiving unit, a lens-type upper electrode, and a color filter. The semiconductor substrate can include a circuit region. The metal interconnection layer can include a metal interconnection and an interlayer dielectric. The light-receiving unit can be a photodiode disposed on the metal interconnection layer. The lens-type upper electrode can be disposed on the light-receiving unit and formed in a convex lens shape. The color filter can be disposed on the lens-type upper electrode.
|Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor substrate having a first electronic circuit and a second electronic circuit formed on an active surface, a pad electrode formed on the active surface by being connected to the first electronic circuit and/or the second electronic circuit, a first opening formed to some point along a depth of the semiconductor substrate toward the pad electrode from a surface opposite to the active surface of the semiconductor substrate, a second opening formed so as to reach the pad electrode from a bottom surface of the first opening, an insulating layer formed by covering sidewall surfaces of the first opening and the second opening, a conductive layer formed by covering at least an inner wall surface of the insulating layer and a bottom surface of the second opening, a third opening formed to some point along the depth of the semiconductor substrate from the surface opposite to the active surface of the semiconductor substrate, and a heat insulator imbedded in the third opening.
|Semiconductor Package, Method of Fabricating the Same and Semiconductor Package Module For Image Sensor - Provided are a semiconductor package, a method of fabricating the same, and a semiconductor package module for an image sensor The semiconductor package includes a mounting portion on which a semiconductor chip is mounted; a semiconductor chip including a plurality of bonding pads disposed along an edge thereof, wherein the semiconductor chip adhered onto the mounting portion; a plurality of leads spaced apart from a sidewall of the semiconductor chip and having a greater height than the semiconductor chip; an encapsulant for fixing the mounting portion and the leads and encapsulating a bottom surface and a sidewall of the semiconductor package and exposing top and bottom surfaces of the leads; bonding wires for connecting the bonding pads of the semiconductor chip with the exposed top surfaces of the leads; and a transparent plate adhered onto the leads a predetermined space apart from the semiconductor chip.
|Negative Feedback Avalanche Diode - A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition of the resistor.
|Image sensor and method for manufacturing the same - Provided are an image sensor and a method for manufacturing the same. The image sensor includes a substrate, a first electrode, an intrinsic layer, a second conductive type conduction layer, and a second electrode. Circuitry including a lower interconnection is disposed on the substrate. The first electrode, the intrinsic layer, and the second conductive type conduction layer are sequentially stacked on the substrate. The second electrode is disposed on the second conductive type conduction layer and includes a non-explosive transparent electrode.
|Temperature Sensing Device - The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device, and a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element. The present invention also relates to a method of forming a temperature sensing element for integration with a semiconductor device.
|PROCESS FOR HIGH VOLTAGE SUPERJUNCTION TERMINATION - A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
|Method of Fabricating Semiconductor Device Having Self-Aligned Contact Plug and Related Device - Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.
|Semiconductor device and method for manufacturing the same - It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.
|Tapered through-silicon via structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.
|Production of a Carrier Wafer Contact in Trench Insulated Integrated Soi Circuits Having High-Voltage Components - The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact and the insulation trench are provided with components exhibiting high-blocking capability of insertion into an integrated circuit SOI wafer. A narrow trench for an insulating trench (
|Semiconductor device and method of producing the same - In a semiconductor device having element isolation made of a trench-type isolating oxide film
|SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE - A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.
|Electrical Fuse Circuit for Security Applications - A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
|ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION - An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
|SEMICONDUCTOR DEVICE - A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode of the switching element; a power supply line of the driver circuit; and a capacitor connected between the power supply line and the reference voltage line.
|High Density Capacitor Using Topographic Surface - Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.
|Semiconductor device - In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.
|Group III-Nitride Semiconductor Crystal and Manufacturing Method Thereof, and Group III-Nitride Semiconductor Device - A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has been melted, and growing group III-nitride semiconductor crystal is provided. The group III-nitride semiconductor crystal attaining a small absorption coefficient and an efficient method of manufacturing the same, as well as a group III-nitride semiconductor device attaining high light emission intensity can thus be provided.
|Seal Ring Structure with Improved Cracking Protection - An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.
|SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.
|Semiconductor Device and Its Fabrication Method - A semiconductor device and a fabrication method thereof are disclosed. The method includes attaching a wafer with a plurality of chips on a carrier board having an insulating layer, a plurality of conductive circuits and a bottom board; forming a plurality of first grooves between solder pads of adjacent chips to expose the conductive circuits, and filling the first grooves with an insulating adhesive layer; forming second grooves in the insulating adhesive layer; and cutting among the chips to separate the chips from one another.
|Silicon Compounds for Producing Sio2-Containing Insulating Layers on Chips - The present invention relates to a process for producing an SiO
|INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER AND METHOD - An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in time and a third starting component at a third point in time. The third starting component includes a halogen.
|SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a gate insulating film formed over a semiconductor substrate, and a gate electrode formed over the gate insulating film, wherein the gate insulating film is so provided as to protrude from both sides of the gate electrode, and the gate electrode includes a wholly silicided layer.
|FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION - In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.
|Electromagnetic Shielding Device for an Infrared Receiver - An electromagnetic shielding device in an infrared receiver comprises of a wiring frame (
|STACKED PACKAGED INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.
|Leadframe For a Semiconductor Device - A leadframe (
|Semiconductor Package Having Reduced Thickness - A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.
|LEAD FRAME FOR SEMICONDUCTOR PACKAGE - A lead frame (
|Chip-On-Lead and Lead-On-Chip Stacked Structure - A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, wherein the ends of first inner leads and the ends of second inner leads are arranged in rows facing each other at a distance. The active surface of first chip is fixedly connected to the lower surface of first inner leads and second inner leads via a first adhesive layer. A plurality of metal pads is provided near the central area of the active surface of first chip and is exposed. A second adhesive layer is formed on the back surface of second chip for fixedly connecting the back surface of second chip and the upper surface of first inner leads and second inner leads. The gap formed by the thickness of second adhesive layer prevents the bonding wires connecting the first chip from contacting the back surface of second chip.
|Multi-chip semiconductor device having leads and method for fabricating the same - The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads. By the multi-chip semiconductor device and the method for fabricating the same as proposed in the present invention, problems like poor reliability caused by stress induced by several types of materials in a semiconductor package into which a substrate and leads are integrated, moisture absorption by an encapsulated substrate, and cracks developed as a result of moisture absorption by the substrate can be avoided.
|SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A portion of a frame body is fixed on a surface of a heat-radiating plate, and on frame body, a semiconductor chip is die-bonded. Next, a prescribed electrode of semiconductor chip and corresponding lead terminal and the like are electrically connected by a prescribed wire. Next, the lead frame is set in a metal mold such that the semiconductor chip is covered with resin from above the semiconductor chip. Thermoplastic resin is introduced into the metal mold, and semiconductor chip and the like are sealed. By taking out the resulting body from the metal mold, a semiconductor is formed. Thus, a semiconductor device can be provided with reduced manufacturing cost.
|Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a leadframe, a die, a solder layer and several connecting components. The leadframe includes a heat dissipation pad and several leads. The heat dissipation pad is disposed in a substantial center of the leadframe. The leads are surrounding the heat dissipation pad. The die having an active surface is disposed on the leadframe. The solder layer is disposed between the active surface and the heat dissipation pad. The connecting components are disposed between the active surface and the leads. The die is electrically connected to the leadframe through the solder layer and the connecting components.
|System-in-package type semiconductor device - A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip
|SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate. The frame may be formed using, as frame members, two L-shaped semiconductor members in combination or four or more stick semiconductor members in combination.
|PACKAGE AND PACKAGING ASSEMBLY OF MICROELECTROMECHANICAL SYSYEM MICROPHONE - A package of microelectromechanical system (MEMS) microphone is suitable for being mounted on a printed circuit board. The package has a cover and at least one MEMS microphone. The cover has an inner surface and a conductive trace disposed thereon. The MEMS microphone is mounted on the inner surface of the cover and electrically connected to the conductive trace, and has an acoustic pressure receiving surface. When the cover is mounted on the printed circuit board, the cover and the printed circuit board construct an acoustic housing which has at least one acoustic hole passing through the cover or the printed circuit board, and the conductive trace on the inner surface of the cover is electrically connected to the printed circuit board.
|Wafer level package and wafer level packaging method - Provided are a wafer level package and a wafer level packaging method, which are capable of performing an attaching process at a low temperature and preventing contamination of internal devices. In the wafer level package, a device substrate includes a device region, where a device is formed, and internal pads on the top surface. The internal pads are electrically connected to the device. A cap substrate includes a getter corresponding to the device on the bottom surface. A plurality of sealing/attaching members are provided between the device substrate and the cap substrate to attach the device substrate and the cap substrate and seal the device region and the getter. The sealing/attaching members are formed of polymer. A plurality of vias penetrate the cap substrate and are connected to the internal pads. The getter provided in the sealed space defined by the sealing/attaching members can prevent the devices of the device region from being contaminated by moisture or foreign particles generated during the fabrication process, and the sealing/attaching process can be performed at a lower temperature compared with a typical sealing/attaching process using a metal.
|METHOD OF FABRICATION OF AI/GE BONDING IN A WAFER PACKAGING ENVIRONMENT AND A PRODUCT PRODUCED THEREFROM - A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.
|Housed active microstructures with direct contacting to a substrate - A microstructured component with microsensors or other active mircrocomponent is provided. The microstructured component includes a substrate and at least one housing arranged on the substrate with one or more active microstructures situated on it.
|Multi layer low cost cavity substrate fabrication for pop packages - In a method and system for fabricating a semiconductor device (
|Die stacking system and method - Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.
|Stacked package structure and fabrication method thereof - A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package.
|COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION - A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
|SEMICONDUCTOR PACKAGE USING CHIP-EMBEDDED INTERPOSER SUBSTRATE - A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.
|Electronic Device and Pressure Sensor - An electronic device requires an electronic component to be mounted for the purpose of static shielding. The mounting of such an electronic component raises a problem of avoiding thermal stresses and cracks generated due to the difference between the coefficients of linear expansion of component materials. A positioning recess, a joining-substance thickness ensuring recess, a joining-substance thickness ensuring projection, etc. are formed in a combined manner in an electronic component mount portion of each of leads, whereby spreading of cracks generated in the joining substance can be suppressed and reliability can be improved. Filling a sealing material so as to seal and restrain the electronic component mounted in the electronic component mount portion without leaving voids contributes to further suppressing spreading of cracks generated in the joining substance and ensuring more improved reliability of the joining substance.
|ELECTRONIC SYSTEM WITH EXPANSION FEATURE - An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.
|Chip Package with Pin Stabilization Layer - Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral movement of the conductor pins while leaving second ends of the conductor pins exposed.
|Integrated Circuit Packages, Methods of Forming Integrated Circuit Packages, And Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.
|SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of said circuit board on which said semiconductor element is mounted; and a sealing layer provided on the side of said circuit board on which said semiconductor element is mounted such that said semiconductor element is covered and such that only portions of said metal posts are exposed.
|INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THIN PROFILE - An integrated circuit package system is provided including attaching an external interconnect on a tape; attaching a backside element on the tape adjacent to the external interconnect; attaching an integrated circuit die with the backside element, the backside element is on a first passive side of the integrated circuit die; connecting a first active side of the integrated circuit die and the external interconnect; and forming a first encapsulation over the integrated circuit die with the backside element exposed.
|Semiconductor Packages And Method For Fabricating Semiconductor Packages With Discrete Components - A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.
|SEMICONDUCTOR DEVICE, SUBSTRATE, EQUIPMENT BOARD, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP FOR COMMUNICATION - A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.
|FASTENER FOR HEAT SINKS - This invention is related to an improvement in the structure of a fastener which includes a rod and a sleeve, wherein the rod has a flat top for depression and a rod body extending downwardly from the flat top to form three stepped portions. The upper end of the rod body is provided with a circular groove. The sleeve is formed with a through hole and a flange close to its upper end. The inner side of the sleeve is provided above the flange with a first engaging section engageable with the circular groove of the rod. The sleeve is provided with a second engaging section below the flange and a third engaging section at the lower end thereof. By means of the engagement between the circular groove of the rod and the first engaging section of the sleeve, the rod will be prevented from detaching from the sleeve. The second and third engaging sections are used for preventing the fastener from disengaging from a workpiece. By means of the three stepped portions of the elongated body, the rod can be easily inserted into the sleeve thereby fastening the workpiece on the third engaging section of the sleeve. The second stepped portion of the elongated rod is used for expanding the outer end of the sleeve so as to keep the sleeve at a firm position thus preventing the rod from detaching from the sleeve and facilitating the locking operation of the fastener.
|Semiconductor devices including interlayer conductive contacts and methods of forming the same - In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.
|Semiconductor module and method for manufacturing semiconductor module - A semiconductor module includes a first metal foil; an insulating sheet mounted on a top surface of the first metal foil; at least one second metal foil mounted on a top surface of the insulating sheet; at least one semiconductor device mounted on the second metal foil; and a resin case for surrounding the first metal foil, insulating sheet, second metal foil, and semiconductor device. A bottom end of a peripheral wall of the resin case is located above a bottom surface of the first metal foil. A resin is provided inside the resin case to fill the inside of the resin case. The bottom surface of the first metal foil and the resin form a flat bottom surface so that the flat bottom surface contacts an external mounting member.
|SEMICONDUCTOR DEVICE - Provided is a semiconductor device which is small in size and in which the deformation of leads is prevented at the time of wire-bonding. The semiconductor device includes: an island; a semiconductor element mounted on the bottom surface of the island; leads provided close to the island; and a sealing resin for integrally sealing these constituents. Moreover, in the semiconductor device according to the present invention, electrodes on the semiconductor element are bonded to the leads provided adjacent to a side of the island, the side not provided with leads which extends continuously from the island.
|Dimple free gold bump for drive IC - A conductive bump structure for an integrated circuit (IC) structure comprises a passivation layer, such as a silicon oxide/silicon nitride stack, that is formed on an upper surface of each of the conductive contact pads (e.g. Al pads) of the IC. A plurality of openings extend through the passivation layer to expose areas of the upper surface of the contact pad. The openings are larger in the longitudinal dimension than in the lateral dimension. A conductive bump, preferably comprising gold (Au), is formed on the passivation layer to extend through the openings in the passivation and into electrical contact with the exposed upper surface areas of the contact pad.
|Apparatus for connecting integrated circuit chip to power and ground circuits - In a method and system for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there between. The connector, which is disposed above the die attached to the package base, includes a center pad electrically coupled to the die by a plurality of conductive bumps and a finger extending outward from the center pad towards the package base. The finger is electrically coupled to the package base by a conductive pad. A plurality of bond wires are formed to electrically couple the package base and the die. A resistance of a conductive path via the connector is much less than a resistance of a conductive path via any one of the plurality of bond wires to facilitate an efficient transfer of the at least one of power and ground signal.
|BUMP STRUCTURE - A bump structure including at least one contact pad, at least one first polymer bump, at least one second polymer bump, and a conductive layer is provided. The contact pad is disposed on a substrate, and the first polymer bump is also disposed on the substrate. The second polymer bump is disposed on the substrate and is connected to the first polymer bump. The conductive layer covers the first polymer bump and electrically connects the contact pad.
|SEMICONDUCTOR MODULE MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND MOBILE DEVICE - A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the position of the copper plate so that a pattern unit and the corresponding trench have a predetermined positional relation, the bump and the electrode are aligned, the first principle surface of the copper plate and a semiconductor substrate are pressure-bonded via an insulating layer, and the bump and the electrode become connected electrically while the bump penetrating the insulating layer. A predetermined rewiring pattern is formed on the side of the second principle surface.
|METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: when bonding a bump of an IC chip to a bonding position of a wiring pattern that is formed on an insulating film base member and has a surface covered by a plating layer, forming a plating layer around the bonding position among the wiring pattern at least in an outer peripheral section of a peeled surface of a portion of the wiring pattern peeled from the film base member.
|CHIP ASSEMBLY - A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.
|BUMP ON VIA-PACKAGING AND METHODOLOGIES - A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections. A method of forming a semiconductor package having external package connections includes providing a semiconductor chip having under bump metallizations (UBMs) on a first surface; attaching the first surface of the semiconductor chip to a substrate, the UBMs of the semiconductor chip being in alignment with open vias formed in the substrate; encapsulating the semiconductor chip and the substrate; and filling with open vias with a conductor to form the external package connections.
|Reliable metal bumps on top of I/O pads after removal of test probe marks - In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.
|METHODS OF FABRICATING CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE, AND CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE FABRICATED USING THE METHODS - Provided are methods of fabricating a circuit board and a semiconductor package, and a circuit board and a semiconductor package fabricated using the methods. The circuit board comprises: a lower wiring pattern disposed on an upper surface of a resin substrate comprising a filler; a resin layer disposed on the lower wiring pattern; an upper wiring pattern comprising a bonding pad disposed on the resin layer; and a passivation layer comprising an upper opening exposing the bonding pad. The resin substrate comprises a substrate opening exposing a lower surface of the lower wiring pattern.
|INTEGRATED CHIP CARRIER WITH COMPLIANT INTERCONNECTS - An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top surface connected to the bottom surface of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom surface of the carrier to the top surface of the carrier layer. Each through via includes a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space.
|CONDUCTOR-DIELECTRIC STRUCTURE AND METHOD FOR FABRICATING - A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.
|SEMICONDUCTOR CONTACT STRUCTURE CONTAINING AN OXIDATION-RESISTANT DIFFUSION BARRIER AND METHOD OF FORMING - The method includes providing a patterned structure in a process chamber, where the patterned structure contains a micro-feature formed in a dielectric material and a contact layer at the bottom of the micro-feature, and depositing a metal carbonitride or metal carbide film on the patterned structure, including in the micro-feature and on the contact layer. The method further includes forming an oxidation-resistant diffusion barrier by increasing the nitrogen-content of the deposited metal carbide or metal carbide film, depositing a Ru film on the oxidation-resistant diffusion barrier, and forming bulk Cu metal in the micro-feature. A semiconductor contact structure is described.
|Method for FEOL and BEOL Wiring - A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
|Semiconductor device and method for manufacturing the same - A semiconductor device (
|SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING BOAC/COA - A BOAC/COA of a semiconductor device is manufactured by forming a conductive pad over a semiconductor device, forming a passivation oxide film over the semiconductor device including the conductive pad, forming an oxide film over the entire surface of the conductive pad and the passivation oxide film, forming an oxide film pattern defining a bond pad region on the conductive pad, sequentially forming a barrier film and a metal seed layer over the oxide film pattern, the passivation oxide film and the conductive pad, forming a metal layer over the metal seed layer, planarizing the metal layer exposing the oxide film pattern and portions of the barrier film and the metal seed layer, and removing the oxide film pattern by an etching process.
|Semiconductor Device and Method of Manufacturing the Same - A metal interconnection of semiconductor device and method for fabricating the same is provided. The semiconductor device can include a semiconductor substrate formed with device structures such as transistors. An interlayer dielectric layer can be formed on the semiconductor substrate with a metal interconnection formed therethrough. A spacer can be formed on at least a portion of a sidewall of the metal interconnection. A diffusion barrier can be formed on an upper surface of the metal interconnection.
|Electrically Conductive Line - The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSi
|Semiconductor device and method for fabricating the same - A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.
|METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
|INTEGRATED DEVICE FABRICATED USING ONE OR MORE EMBEDDED MASKS - A device fabricated using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the (poly)silicon layer until a relatively late fabrication stage. As a result, flatness of the (poly)silicon layer is preserved for the deposition of any necessary over-layers, which substantially obviates the need for filling the voids created by the structure formation with silicon oxide.
|Contact structures and semiconductor devices including the same and methods of forming the same - Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
|ENHANCED MECHANICAL STRENGTH VIA CONTACTS - The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.
|METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION - Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.
|High performance system-on-chip using post passivation process - The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
|Semiconductor device and method for manufacturing semiconductor device - A semiconductor device includes a first metal foil, an insulating sheet mounted on an upper surface of the first metal foil main, at least one second metal foil mounted on the insulating sheet, at least one solder layer mounted on the at least one second metal foil, and at least one semiconductor element mounted on the at least one second metal foil through the at least one solder layer. The at least one semiconductor has a thickness of 50 μm or greater and less than 100 μm.
|Method of reducing the surface roughness of spin coated polymer films - According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.
|SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.
|STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING - A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.
|Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
|INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE - An integrated circuit package system is provided including forming a perimeter paddle having a first external interconnect extending therefrom, mounting an integrated circuit die over the perimeter paddle, connecting a second external interconnect and the integrated circuit die, and encapsulating the integrated circuit die and the perimeter paddle with the first external interconnect exposed.
|INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES - A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.
|Semiconductor device and method of manufacturing same - A semiconductor device in a packaged form including a semiconductor includes a semiconductor substrate with an active component disposed thereon and pads disposed on a surface thereof and connected to the active component, a first interconnection disposed on the semiconductor substrate and connected to the pads, a first insulating layer disposed on the semiconductor substrate in covering relation to the first interconnection and having an opening reaching a portion of the first interconnection, and a second interconnection disposed in the opening and on the first insulating layer and connected to the first interconnection.


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Makes a nice Christmas decoration, but great at all times of the year. This one was actually created by an associate (student), Lisa Carroll.
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text: 1 Here are pictures of Andruw Jones' wife Nicole Derick Jones. She must be a nice, forgiving woman because Jones was called to testify involving a case surrounding prostitution at The Gold Club back in the 90's and is rumored to still enjoy a gentlemen's club or two these days. Pictures of Andruw Jones' wife Nicole Derick Jones8 Jul, 2012 in Picture Gallery by Rob Abruzzese


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An auction might not be the ideal place to bargain for a car. Have you ever been a part of a car auction? If yes, do let us know about your experience.
On the other hand, have you ever wondered about the kind of money that is involved in a niche car auction?
If you ever decide to get hold of a car at an auction, get ready to spend a premium, as the auctioneer charges a fee called a buyer's premium, anywhere between 5% to 20% in addition to the selling price of the car. Moreover, sometimes you are required to pay a seller's premium as well.
Drivespark cracks down on some of the most expensive cars sold at an auction till date. Be it auctioneers such as Goodings & Company or RM Auctions, listed in the photo gallery below are some of the most exotic cars to face the gavel.
1957 Ferrari 250 Testa Rossa
The Ferrari 250 Testa Rossa or better known as the Ferrari TR, is a race car that ruled the tracks in the 1950s and 60s.
Fact - Only thirty-four 250 Testa Rossas were built, from 1956 through 1961.
- Auction Price - $16,390,000
- Auctioneer - Goodings & Company
- Date of Auction - August 21, 2011
1936 Mercedes-Benz 540K Spezial Roadster
The Mercedes-Benz 540K was manufactured from 1935 to 1940. This was one of the most wanted cars of its time.
Fact - Jack Warner of Warner Brothers film studios owned a Mercedes-Benz 540K.
- Auction Price - $11,770,000
- Auctioneer - Goodings & Company
- Date of Auction - August 19, 2012
1960 Ferrari 250 GT California LWB Competizione Spyder
Ferrari had developed this model especially for North American markets. Hollywood actor James Coburn once owned this beauty.
Fact - 250 GT California Spyder LWB was a rare model. Only 50 were ever made.
- Auction Price - $11,275,000
- Auctioneer - Goodings & Company
- Date of Auction - August 19, 2012
1968 Ford GT40
If you like high performance American-British cars, the Ford GT40 has to be on your list. This car was produced between 1964 to 1969 to beat the Ferrari's.
Fact - Won the 24 hours of Le Mans four consecutive times.
- Auction Price - $11,000,000
- Auctioneer - RM Auctions
- Date of Auction - August 17, 2012
1931 Duesenberg Model J Long-Wheelbase Coupe
Duesenberg Automobile & Motors Company, Inc was active from 1913 to 1937. The model J was produced between 1928 to 1937.
Fact - Duesenberg cars were entirely built by hand.
- Auction Price - $10,340,000
- Auctioneer - RM Auctions
- Date of Auction - August 17, 2012
1931 Bugatti Royale Kellner Coupe
The Bugatti Royale was meant for Royalty. It is about 20% longer, and more than 25% heavier than the new age Rolls Royce Phantom.
Fact - Bugatti manufactured only six cars and managed to sell only three during its time. The 'Kellner' was the fifth car.
- Auction Price - $9,800,000
- Auctioneer - Christie's
- Date of Auction - November 17, 1987
1962 Ferrari 330 TRI/LM Spider
Fact - This Ferrari model is the only 4-litre Testa Rossa built, it also is the last Testa Rossa and the last front-engined sports racing car built by Ferrari.
- Auction Price - $9,281,250
- Auctioneer - RM Auctions
- Date of Auction - May 20, 2007
1955 Ferrari 410S
Fact - Only four examples of the 410 sport were built by Ferrari in 1955. It was purely developed for thenotorious Carrera Panamericana road race .
- Auction Price - $8,250,000
- Auctioneer - RM Auctions
- Date of Auction - August 17, 2012
1937 Bugatti Type 57SC Atalante Coupe
Fact - this legendary design was the vision of Jean Bugatti, son of founder Ettore Bugatti. Only 17 Atalante cars were made. The name Atalante was derived from a heroine of Greek mythology, Atalanta.
- Auction Price - $7,920,000
- Auctioneer - Gooding & Company
- Date of Auction - August 17, 2008
1929 Bentley Blower
"There's no replacement for displacement" and the Bentley 4½ Litre was full of this character.
Fact - The supercharged version of the 4½ Litre was known as the 'Blower Bentley' which produced 175 hp for the touring model and 240 hp for the racing version.
- Auction Price - $7,906,745
- Auctioneer - Bonhams
- Date of Auction - June 29, 2012