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|30th week of 2011 patent applcation highlights part 40
|Patent application number
|Method of manufacturing a semiconductor device - The invention aims to provide substrate treatment equipment that can automatically collect a substrate in a normal condition without needing manual operation. The equipment includes a substrate holder for holding substrates in a multistage manner and a substrate transfer unit for transferring the substrates into the substrate holder, wherein a substrate holding condition of the substrate holder is sensed by a sensing section. The sensing section has photo-sensors, and sensing waveforms sensed by the photo-sensors are compared with a normal waveform. A control section is provided, which controls a substrate transfer unit such that substrates other than at least a substrate that was determined to be abnormal are transferred by the unit.
|METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE - A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.
|LIQUID COMPOSITION, METHOD OF PRODUCING SILICON SUBSTRATE, AND METHOD OF PRODUCING LIQUID DISCHARGE HEAD SUBSTRATE - A liquid composition used to carry out crystal anisotropic etching of a silicon substrate provided with an etching mask formed of a silicon oxide film with the silicon oxide film used as a mask includes cesium hydroxide, an alkaline organic compound, and water.
|APPARATUS AND METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE - An apparatus and method for manufacturing a light emitting devices by separating a semiconductor layer from a substrate includes a laser beam source for emitting a laser beam, a mesh-typed mask having a plurality of apertures through which the laser beam passes to provide a plurality of unit beams; and an imaging lens for forming a plurality of beam spots by focusing the plurality of unit beams at an interface between a substrate and a semiconductor layer to separate the substrate from the semiconductor layer.
|SURFACE EMITTING SEMICONDUCTOR LASER, METHOD FOR FABRICATING SURFACE EMITTING SEMICONDUCTOR LASER, MODULE, LIGHT SOURCE APPARATUS, DATA PROCESSING APPARATUS, LIGHT SENDING APPARATUS, OPTICAL SPATIAL TRANSMISSION APPARATUS, AND OPTICAL SPATIAL TRANSMISSION SYSTEM - A surface emitting semiconductor laser includes a substrate, a lower reflective mirror formed on the substrate, an active layer formed on the lower reflective mirror, an upper reflective mirror formed on the active layer, an optical mode controlling layer formed between the lower reflective mirror and the upper reflective mirror, and a current confining layer formed between the lower reflective mirror and the upper reflective mirror. The active layer emits light. The upper reflective mirror forms a resonator between the lower reflective mirror and the upper reflective mirror. In the optical mode controlling layer, an opening is formed for selectively absorbing or reflecting off light that is emitted in the active layer. The optical mode controlling layer optically controls mode of laser light. The current confining layer confines current that is applied during driving.
|MANUFACTURING METHOD FOR LIQUID CRYSTAL APPARATUS - A manufacturing method for a liquid crystal apparatus of a transverse electric field system that is provided with a liquid crystal layer sandwiched between a first substrate and a second substrate and a pixel electrode and a common electrode formed on the first substrate and is arranged to drive liquid crystal through an electric field generated between the pixel electrode and the common electrode includes the steps of forming a material layer made of photosensitive resin on a glass substrate and performing an exposure processing with a predetermined exposure pattern, performing a development processing on the material layer and forming a resin light interruption layer having an opening section that exposes the glass substrate in a bottom section, forming an electrostatic interruption layer while covering the resin light interruption layer, and providing a colored layer in an area overlapped with the opening section on the electrostatic interruption layer.
|SEMICONDUCTOR LIGHT EMITTING DEVICE, ITS MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A method of manufacturing a semiconductor light emitting device made of nitride III-V compound semiconductors is includes an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.
|METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a semiconductor laminated structure on a substrate as a wafer including semiconductor laser structures; forming a first groove between the semiconductor laser structures on a major surface of the wafer; separating the wafer to laser bars including at least two of the semiconductor laser structures arrayed in a bar shape, after forming the first groove; forming a second groove in the first groove of the laser bars, the second groove having a width no wider than the first groove; and separating one of the laser bars into respective semiconductor lasers along the second groove.
|Method for preparing OLED by imprinting process - A method for preparing an OLED by an imprinting process is disclosed, which comprises the following steps: (A) providing a substrate, and a first electrode is formed thereon; (B) coating a mold with a first organic material ink; (C) pressing the mold coated with the first organic material ink on the substrate to transfer the first organic material ink onto the first electrode of the substrate, to obtain a first light-emitting array; (D) baking the substrate having the first light-emitting array formed thereon; and (E) forming a second electrode on the first light-emitting array.
|Micro-Electro-Mechanical System (MEMS) Sensor and Method for Making Same - The present invention discloses an MEMS sensor and a method for making the MEMS sensor. The MEMS sensor according to the present invention comprises: a substrate including an opening; a suspended structure located above the opening; and an upper structure, a portion of which is at least partially separated from a portion of the suspended structure; wherein the suspended structure and the upper structure are separated from each other by a step including metal etch.
|METHOD FOR FABRICATING MEMS DEVICE - A method for fabricating MEMS device includes: providing a single crystal substrate, having first surface and second surface and having a MEMS region and an IC region; forming SCS mass blocks on the first surface in the MEMS region; forming a structural dielectric layer over the first surface of the substrate, wherein a dielectric member of the structural dielectric layer is filled in spaces surrounding the SCS mass blocks in the MEMS region, the IC region has a circuit structure with an interconnection structure formed in the structural dielectric layer; patterning the single crystal substrate by an etching process on the second surface to expose a portion of the dielectric member filled in the spaces surrounding the SCS mass blocks; performing isotropic etching process at least on the dielectric portion filled in the spaces surrounding the SCS mass blocks. The SCS mass blocks are exposed to release a MEMS structure.
|RTA for Fabrication of Solar Cells - A method of semiconductor junction formation in RTA process for fabrication of solar cells provides for delivery of inert gases in the vicinity of the Si wafer while dopant species are being driven form a dopant source into the surface of the wafer irradiated by a laser beam. The laser beam is emitted by CW- or pulsed operated lasers including fiber lasers operative to provide annealing and diffusion operation. Optionally, the passivation of the surface and formation of the antireflection coating are performed simultaneously with the penetration the dopant species.
|FORMING SOLAR CELLS USING A PATTERNED DEPOSITION PROCESS - Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.
|METHOD OF MANUFACTURING SOLAR CELL - A method of manufacturing a solar cell includes providing a semiconductor substrate; disposing a reflection layer on one side of the semiconductor substrate, wherein the disposing the reflection layer comprises implanting gas into a surface of the one side of the semiconductor substrate and heating the gas; disposing an n+ region and a p+ region separated from each other on the other opposite facing side of the semiconductor substrate; disposing a first electrode connected to the n+ region; and disposing a second electrode connected to the p+ region.
|Light Shield for CMOS Imager - System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.
|PROCESS DEVICE FOR PROCESSING IN PARTICULAR STACKED PROESSED GOODS - The invention relates to a processing device for the processing of in particular stacked proceed goods, particularly in the form of planar substrates for the production of thin layers, particularly of conducting, semiconducting, or insulating thin layers, comprising an evacuatable processing chamber for receiving a process gas, comprising at least one tempering device, particularly at least in sections in and/or in thermal operative connection with at least one wall, particularly all walls of the processing chamber, said chamber being equipped and suited to keep at least a partial region of the wall, particularly substantially the entire process chamber wall, of the process chamber at a predetermined temperature, particularly to keep the same at a first temperature during at least part of the processing of the stacked processed goods, said temperature not being below room temperature as the second temperature, and being below a third temperature which can be generated in the processing chamber and is above room temperature; at least one gas conveying device for creating a gas flow cycle in the process chamber, particularly a forced convection; at least one heating device for heating the gas, said heating device disposed or able to be disposed in the gas flow cycle created by the gas conveying device; at least one gas guiding device,
|METHOD OF MAKING N-TYPE SEMICONDUCTOR DEVICES - An organic semiconducting composition consists essentially of an N,N-dicycloalkyl-substituted naphthalene diimide and a polymer additive comprising an insulating or semiconducting polymer having a permittivity at 1000 Hz of at least 1.5 and up to and including 5. This composition can be used to provide a semiconducting layer in a thin-film transistor that can be incorporated into a variety of electronic devices.
|THIN FILM TRANSITOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a thin film transistor ("TFT") substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.
|DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS - A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.
|Array-Molded Package-On-Package Having Redistribution Lines - A semiconductor device with a sheet-like insulating substrate (
|PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE - A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.
|PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE - A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.
|Semiconductor device - There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.
|Integrated semiconductor substrate structure using incompatible processes - A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.
|MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a plurality of element groups over an upper surface of a substrate; forming an insulating film so as to cover the plurality of element groups; selectively forming an opening to the insulating film which is located in a region between neighboring two element groups in the plurality of element groups to expose the substrate; forming a first film so as to cover the insulating film and the opening; exposing the element groups by removing the substrate; forming a second film so as to cover the surface of the exposed element groups; and cutting off between the plurality of element groups so as not to expose the insulating film.
|Stress Buffer Layer for Ferroelectric Random Access Memory - An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
|METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A PLATED THROUGH-HOLE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal, a plated through-hole and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.
|METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted, and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.
|ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME - A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component
|DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE - A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
|ETCHING SOLUTION COMPOSITION AND METHOD OF ETCHING USING THE SAME - An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH
|SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE - A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.
|Method of manufacturing TFT and array TFT - A method of manufacturing a thin film transistor includes sequentially forming a gate and at least one insulation layer on a substrate, forming a source electrode and a drain electrode on the at least one insulation layer, and forming a channel layer formed of a semiconductor on a part of the source electrode and the drain electrode, wherein the gate, the source electrode, and the drain electrode are formed by using a hybrid inkjet printing apparatus.
|THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - A TFT array panel and a manufacturing method thereof.
|SEMICONDUCTOR DEVICE WITH GROUP III-V CHANNEL AND GROUP IV SOURCE-DRAIN AND METHOD FOR MANUFACTURING THE SAME - The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.
|PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
|TRANSISTORS WITH LATERALLY EXTENDED ACTIVE REGIONS AND METHODS OF FABRICATING SAME - A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.
|Semiconductor device and method of manufacturing the semiconductor device - In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.
|SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of semiconductor pillars, respectively; upper diffusion layers formed in each upper part of the plurality of semiconductor pillars, respectively; lower diffusion layers formed in each lower part of the plurality of semiconductor pillars, respectively; gate electrodes encircling at least each channel region between each upper diffusion layer and each lower diffusion layer, respectively; and a plurality of lower electrodes short-circuiting the lower diffusion layers adjacent in the first direction.
|SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for making a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.
|TRANSISTOR HAVING V-SHAPED EMBEDDED STRESSOR - A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
|Strained Semiconductor Device and Method of Making Same - To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed.
|SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for forming a semiconductor device includes the following processes. A substrate structure having an insulating upper surface is formed. The insulating upper surface has a step. An insulating layer is formed over the insulating upper surface. The insulating layer covers the step. The insulating layer includes first and second portions which are bounded by the step. The first portion is thinner than the second portion. First and second grooves are formed in the first and second portions, respectively. The first groove is shallower than the second groove. First and second conductive films which fill up the first and second grooves, respectively are formed. The first conductive film is thinner than the second conductive film.
|SWITCHING MATERIALS COMPRISING MIXED NANOSCOPIC PARTICLES AND CARBON NANOTUBES AND METHOD OF MAKING AND USING THE SAME - An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.
|SEMICONDUCTOR STRUCTURE FORMED WITHOUT REQUIRING THERMAL OXIDATION - Briefly, in accordance with one or more embodiments, a semiconductor device is manufactured by forming at least two or more cavities below a surface of a semiconductor substrate wherein the at least two or more cavities are spaced apart from each other by a selected distance, filling at least a portion of the at least two or more cavities with a dielectric material to form at least two or more dielectric structures, removing a portion of the substrate between the at least two or more dielectric structures to form at least one additional cavity, and covering the at least one additional cavity.
|SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+
|Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions - Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition.
|PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE - The present invention relates to a process for manufacturing a structure comprising a germanium layer (
|METHOD FOR MANUFACTURING SOI SUBSTRATE - Manufacturing cost of an SOI substrate is reduced. Yield of an SOI substrate is improved. A method for manufacturing an SOI substrate includes the steps of irradiating a single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate, bonding the single crystal semiconductor substrate to a base substrate with an insulating film therebetween, and separating the single crystal semiconductor substrate and the base substrate at the embrittled region to form a semiconductor layer over the base substrate with the insulating film therebetween. In the step of forming the embrittled region, ion species which are not mass-separated are used as the ions and a temperature of the single crystal semiconductor substrate is set to 250° C. or higher at the time of irradiation with the ions.
|ANNEALING PROCESS FOR ANNEALING A STRUCTURE - The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.
|METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUBSTRATE CARRIER STRUCTURE - A substrate carrier structure includes a tray and a secondary electron absorbing material. The tray holds a semiconductor substrate having a first surface on which semiconductor device elements are formed. The secondary electron absorbing material is interposed between the tray and this first surface of the semiconductor substrate. When the semiconductor substrate is irradiated with charged particles to form lattice defects, the secondary electron absorbing material prevents unwanted trapping of secondary electrons emitted from the tray, and thereby reduces the variability of electrical characteristics of semiconductor device elements formed on the semiconductor substrate.
|METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include multiply stacking an insulating layer and a conductive layer alternately above a base member. The insulating layer includes silicon oxide. The conductive layer includes silicon. In addition, the method can form a SiOC film on a stacked body of the insulating layers and the conductive layers, pattern the SiOC film, and make a hole in the stacked body by etching the insulating layers and the conductive layers using the patterned SiOC film as a mask.
|High Pressure Apparatus and Method for Nitride Crystal Growth - An improved high pressure apparatus and methods for processing supercritical fluids is described. The apparatus includes a capsule, a heater, and at least one ceramic ring contained by a metal sleeve. The apparatus is capable of accessing pressures and temperatures of 0.2-2 GPa and 400-1200° C.
|Nano-tube MOSFET technology and devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a "Gap Filler" layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The "Gap Filler" layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
|MANUFACTURING METHOD OF MEMORY ELEMENT, LASER IRRADIATION APPARATUS, AND LASER IRRADIATION METHOD - A method for rapidly performing laser irradiation in a desired position as laser irradiation patterns are switched is proposed. A laser beam emitted from a laser oscillator is entered into a deflector, and a laser beam which has passed through the deflector is entered into a diffractive optical element to be diverged into a plurality of laser beams. Then, a photoresist formed over an insulating film is irradiated with the laser beam which is made to diverge into the plurality of laser beams, and the photoresist irradiated with the laser beam is developed so as to selectively etch the insulating film.
|THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention provides a step in which a channel-length of a TFT can be controlled with higher reproducibility. In addition, the present invention provides a step in which a short channel-length of the TFT can be manufactured. Further, the present invention provides a structure of the TFT in which a current-voltage characteristic can be improved. The present invention refers to a thin film transistor comprising a lamination layer wherein a first conductive film, a first insulating film and a second conductive film are sequentially laminated, a semiconductor film formed so as to be in contact with the side surface of the lamination layer, and a third conductive film covering the semiconductor film through a second insulating film. The first conductive film and the second conductive film are a source electrode and a drain electrode, and a region which is in contact with the first insulating film and the third conductive film is a channel forming region in semiconductor film, and the third conductive film is a gate electrode.
|Linear and Cross-Linked High Molecular Weight Polysilanes, Polygermanes, and Copolymers Thereof, Compositions Containing the Same, and Methods of Making and Using Such Compounds and Compositions - Methods are disclosed of making linear and cross-linked, HMW (high molecular weight) polysilanes and polygermanes, polyperhydrosilanes and polyperhydrogermanes, functional liquids containing the same, and methods of using the liquids in a range of desirable applications. The silane and germane polymers are generally composed of chains of Si and/or Ge substituted with R′ substituents, where each instance of R′ is, for example, independently hydrogen, halogen, alkenyl, alkynyl, hydrocarbyl, aromatic hydrocarbyl, heterocyclic aromatic hydrocarbyl, SiR″
|SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.
|METHODS OF FORMING A DUAL-DOPED EMITTER ON A SUBSTRATE WITH AN INLINE DIFFUSION APPARATUS - A method of forming a multi-doped junction is disclosed. The method includes providing a substrate doped with boron atoms, the substrate comprising a front substrate surface. The method also includes depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents; and heating the substrate in a baking ambient at a baking temperature and for a baking time period wherein a densified ink layer is formed. The method further includes exposing the substrate to a phosphorous dopant source at a drive-in temperature and for a drive-in time period.
|METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME - A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.
|Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut - A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening.
|Peripheral Gate Stacks and Recessed Array Gates - Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.
|REPLACEMENT GATE FinFET DEVICES AND METHODS FOR FORMING THE SAME - A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.
|Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
|SEMICONDUCTOR DEVICE HAVING LAMINATED ELECTRONIC CONDUCTOR ON BIT LINE - There are provided a semiconductor device and a fabrication method therefor including an ONO film (
|SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.
|METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING CONTACT PLUG - A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern.
|SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
|STABLE ELECTROLESS FINE PITCH INTERCONNECT PLATING - A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.
|SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
|METHODS OF FORMING WIRING STRUCTURES - In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (C
|METHOD FOR ELECTRON BEAM INDUCED DEPOSITION OF CONDUCTIVE MATERIAL - The invention relates to a method for electron beam induced deposition of electrically conductive material from a metal carbonyl with the method steps of providing at least one electron beam at a position of a substrate (
|METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a semiconductor device, which includes forming a TiN film as a hard mask directly on a second p-SiCOH film formed on a substrate, forming an opening passing through the TiN film and the second p-SiCOH film by photolithography and etching, cleaning the inside of the opening, removing the TiN film after cleaning the inside, and forming a second metal film filling the opening directly on the second p-SiCOH film after removing the TiN film.
|METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device and a substrate processing apparatus capable of providing a TiN film that is higher in quality than a TiN film formed by a conventional CVD method at a higher film-forming rate, that is, with a higher productivity than a TiN film formed by an ALD method. The method includes steps of: (a) loading a substrate into a processing chamber; (b) forming a predetermined film on the substrate by simultaneously supplying the first processing gas and the second processing gas into the processing chamber; (c) stopping the supply of the first processing gas and the second processing gas and removing the first processing gas and the second processing gas remaining in the processing chamber; (d) modifying the film formed on the substrate by supplying the second processing gas into the processing chamber after the step (c); and (e) unloading the substrate from the processing chamber, wherein, in the step (b), a time period for supplying the second processing gas into the processing chamber is longer than a time period for supplying the first processing gas into the processing chamber.
|Method for Removing Copper Oxide Layer - The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.
|METHODS AND SYSTEMS OF MATERIAL REMOVAL AND PATTERN TRANSFER - Polymerized material on a substrate may be removed by exposure to vacuum ultraviolet (VUV) radiation from an energy source within a gaseous atmosphere of a controlled composition. Following such removal, additional etching techniques are also described for nano-imprinting.
|METHOD AND APPARATUS FOR PATTERN COLLAPSE FREE WET PROCESSING OF SEMICONDUCTOR DEVICES - A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse.
|METHOD FOR ELECTRON BEAM INDUCED ETCHING OF LAYERS CONTAMINATED WITH GALLIUM - The invention relates to a method for electron beam induced etching of a layer contaminated with gallium (
|METHOD FOR CHEMICALLY TREATING A SUBSTRATE - A method for chemically treating a disc-shaped substrate having a bottom surface, a top surface and side surfaces by contacting a process medium that is fluid-chemically active with at least the bottom surface of the substrate. The substrate is moved relative to the process medium while forming a triple line between the substrate, the substrate medium and the atmosphere surrounding the substrate and medium. In order to chemically remove errors, particularly in the side surfaces, relative motion should be carried out while avoiding a contacting of the process medium with the top surface of the substrate, where the triple line is formed at a desired height of the side surface facing away from the process medium flow side in relation to the relative motion between the substrate and the process medium. In this way, the atmosphere can be adjusted in relation to the partial pressures of the components in the process medium such that the top surface preserves hydrophobic characteristics.
|Homogeneous Porous Low Dielectric Constant Materials - In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.
|METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Characteristics of a low-k insulating film grown on a substrate is modulated in the thickness-wise direction, by varying the ratio of high-frequency input and low-frequency input used for inducing plasma in the course of forming the film, to thereby improve the adhesion strength while keeping the dielectric constant at a low level, wherein the high-frequency input and the low-frequency input for inducing plasma are applied from a single electrode, while elevating the level of low-frequency input at least either at the start of formation or at the end of formation of the insulating film, as compared with the input level in the residual time zone, thereby the insulating film is formed to have a close-adhesion layer in at least either one of the end portions of the film in the thickness-wise direction, by the contribution of both of the high-frequency input and the low-frequency input, and to have a low-k insulating film in the residual portion of the film, by lowering or zeroing the level of the low-frequency input.
|Precursor Composition, Methods of Forming a Layer, Methods of Forming a Gate Structure and Methods of Forming a Capacitor - In a method of forming a layer, a precursor composition including a metal and a ligand chelating to the metal is stabilized by contacting the precursor composition with an electron donating compound to provide a stabilized precursor composition onto a substrate. A reactant is introduced onto the substrate to bind to the metal in the stabilized precursor composition. The stabilized precursor composition is provided onto the substrate by introducing the precursor composition onto the substrate after the electron donating compound is introduced onto the substrate. The electron donating compound is continuously introduced onto the substrate during and after the precursor composition is introduced.
|COMPOSITION AND METHOD FOR LOW TEMPERATURE DEPOSITION OF SILICON-CONTAINING FILMS SUCH AS FILMS INCLUDING SILICON, SILICON NITRIDE, SILICON DIOXIDE AND/OR SILICON-OXYNITRIDE - Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si
|TOLERANCE COMPENSATING, ELECTRIC CONNECTOR, IN PARTICULAR FOR MOTOR VEHICLE CONTROL DEVICES - An electric connector with a tolerance compensator, includes a plug-in part and a counter part. An electric connection is established when the plug-in part including at least one electrically conductive pin is plugged into the counter part in the z-direction of a Cartesian coordinate system. The counter part has volume elastic properties, is electrically conductive and forms a predetermined volume. The counter part is limited in the z-direction by, respectively, one contact surface. In order to establish an electric connection, the at least one electrically conductive pin is aligned essentially in the counterpart in the z-direction and traverses a contact surface in an essentially perpendicular manner. The volume area of the counter part is calculated such that the pin reaches the volume allowing a reliable electric connected to be established, in the framework of a permitted path tolerance in the x- and/or y-direction when plugging together.
|BROADBAND TWIST CAPSULES - A twist capsule (
|JUNCTION BOX FOR PHOTOVOLTAIC MODULES - The invention relates to a junction box for photovoltaic modules, comprising prefabricated terminal cables that are electrically connected to a punched grid which has a strip conductor structure accommodating electrical or electronic components, in particular bypass diodes. The punched grid also has bent sections pointing in a direction which deviates from the plane of the punched grid. Contact means of the photovoltaic module engage into openings that are provided in the box member and point in said direction. According to the invention, the bent sections are designed as lyre contact bridges or omega contact bridges which have two opposite legs expanding in the direction of the module and a clamping part. The legs accommodate the contact means in a guided manner while the clamping part contacts the contact means. Furthermore, the box member is designed as a closed injection-molded piece except for the openings pointing in the direction of the module.
|ELECTRICAL METAL CLAD CONNECTORS AND METHODS OF USE - A cable connector may be disclosed. The connector may include a connector housing having a first threaded portion and an insert having compression voids. The insert may be configured for insertion into the connector housing. The connector may also include a compression nut configured to engage the first threaded portion. The compression nut may be configured to compress the insert to close the compression voids when the compression nut engages the first threaded portion. The cable connector may also include an end stop having an adjustable throat diameter configured to adjust in proportion to an adjustable inner diameter of the cable connector as the connector engages or armor of an armored cable.
|ELECTRICAL CONNECTION ASSEMBLY - An electrical connection assembly includes a faceplate defining a compartment extending substantially perpendicularly therefrom. The compartment being formed from the same piece of material as the faceplate and defining a biasing member biasing a component of the connection assembly. The electrical connection assembly also includes a one-piece conductive insert disposed within the compartment. The insert has a terminal enabling electrical connection of the insert to an electrical current source.
|ELECTRICAL CONNECTOR WITH IMPROVED HANDLING PORTION - An electrical connector includes a housing, a plurality of contacts received in the housing, a shielding and a handling portion. The housing includes a mating portion and a connecting portion. The shielding includes a first upper cover and a second down cover respectively assembled on the housing from up to down and from down to up. The upper cover and the down cover respectively includes a pair of extending arm to combine to form a fastening portion located on the two sides of the shielding. The handling portion is fixed on the fastening portion and includes a connecting element, and a cover over mode on the connecting element, a pair of fastening arms inserted into the fastening portion of the shielding. The cover is apart from the housing.
|ELECTRICAL CONNECTOR ASSEMBLY WTH HIGH-DENSITY CONFIGURATION - An electrical connector assembly (
|SWITCH CONTACT AND AUDIO JACK WITH THE SAME - An audio jack adapted to be inserted into an audio plug for switch an audio function includes a housing, a switch contact and a signal contact. The housing includes a main portion, a mating portion projected from a front of the main portion and a tunnel longitudinally formed in the housing. The switch contact includes an engaging portion engaged with the housing, and a first contact portion extended to the tunnel. The signal contact includes an engaging portion engaged with the housing, and a second contact portion extended into the tunnel. The first contact portion and second contact portion connect to different positions of a lateral surface of the audio plug for switching the audio function while the audio plug is completely plugged into the tunnel of the housing.
|Method and apparatus for interconnecting distributed power sources - A method and apparatus for power wiring. In one embodiment, the apparatus comprises a splice box comprising (i) a plug having a plurality of plug pins, each plug pin of the plurality of plug pins for coupling to a conductor within a cable adapted for coupling to a power line; (ii) a first pin receptacle for coupling to a first guide pin of a connector; and (iii) a first pair of retention bars disposed within the first pin receptacle, the first pair of retention bars for retaining the first guide pin.
|ELECTRIC POWER CONNECTOR AND POWER CABLE RETAINER ARRANGEMENT - An electric power connector and power cable retainer arrangement includes an electric power connector for the connection of the electric plug or socket of an external power cable for power transmission, and a power cable retainer that has a holder base provided at the electric power connector and a clip extended from the holder base for securing the cable of the external power cable in place to prohibit disconnection of the electric plug or socket of the external power cable.
|Automatic Connector - Disclosed herein are embodiments of a connector comprising a shell with a shell axis, a shell opening, a plurality of retaining structures, an inner shell surface, and an outer shell surface; the retaining structures are, at least in part, configured to retain a spring in a compressed state; a plurality of clamping members axially located within the shell between the spring and the shell opening; and a release that is generally coaxial with the shell opening and configured to release the compressed spring when a cable is inserted past the clamping members.
|CONNECTOR DEVICE FOR BUILDING INTEGRATED PHOTOVOLTAIC DEVICE - The present invention is premised upon a connector device and method that can more easily electrically connect a plurality of PV devices or photovoltaic system components and/or locate these devices/components upon a building structure. It also may optionally provide some additional sub-components (e.g. at least one bypass diode and/or an indicator means) and may enhance the serviceability of the device.
|Connector and connecting unit - A connector includes a connector protrusion to be inserted into a connector socket and including a locking lever provided on a first surface and a connecting terminal provided on a second surface opposing the first surface or on a front surface; and a connector frame surrounding the connector protrusion and having an opening in a surface opposing the first surface of the connector protrusion. When the connector frame is moved in a direction opposite to the direction where the connector protrusion is inserted while the connector protrusion is in the connector socket, an end of the locking lever fits into the opening and the locking lever is unlocked.
|Switchboard Terminal Block - A switchboard terminal block including a body with a side face and a front side provided with a seat for labels, the seat having a top edge and bottom edge formed in the manner of a respective tooth, a relief extending in the vertical direction on the front surface of the seat, the seat being open in the transverse direction for insertion of the label from one side or the other. Also, a label for the seat, which has a top edge and bottom edge which can be shaped so as to form a respective projection in the vertical direction and is provided with a cavity on the inner face extending in the vertical direction and with a depth substantially corresponding to the height of the relief on the seat of the terminal block.
|ELECTRONIC CONNECTION DEVICE - An electronic connection device for electrically connecting two electronic devices to each other includes a connection unit for electrically connecting the two electronic devices to each other and a receiving unit. The connection unit includes a data cable. The receiving unit includes a main body and a sleeve barrel. The sleeve barrel is detachably assembled to the main body and receives the main body therein. The data cable is coiled on the sleeve barrel when the sleeve barrel assembled to the main body and is coiled on the main body when the sleeve barrel is detached.
|LOW PROFILE COMPACT RF COAXIAL TO PLANAR TRANSMISSION LINE INTERFACE - A compact, low profile coaxial to printed wiring board interface includes an interface block and an adapter. The interface block has a stepped opening for receiving the adapter and a coaxial cable. The adapter includes an outer profile with a series of steps that align and mate with the stepped opening of the interface block. An inner insulator of the coaxial cable is positioned entirely within the interface block and lies substantially flush with a first outside surface of the interface block, an outer conductor of the coaxial cable is positioned at an approximate midpoint interface of the adapter, an outer insulator of the coaxial cable lies flush with an external surface of the adapter, and a portion of the adapter positioned outside the interface block comprises a low profile such that the coaxial cable can be positioned away from a perpendicular to the interface block.
|ELECTRICAL CONNECTOR WITH METALLIC SHELL FIRMLY RETAINED WITH THE INSULATIVE HOUSING - An electrical connector (


text:
By MICHAEL T. KAUFMAN, Special to the New York Times
Published: May 20, 1983
OTTAWA, May 19— The Canadian Government has introduced legislation to set up a clandestine intelligence service with broad authority to intercept mail, install recording devices and surreptitiously break into homes or offices.
The legislation, which is raising concerns among civil liberties activists, also provides penalties of five years' imprisonment for anyone revealing information from which the identity of a covert operative or informant ''can reasonably be inferred.'' Panel Recommended Move
The bill setting up the Canadian Security Intelligence Service was introduced in Parliament Wednesday, almost two years after a blueribbon panel recommended that the Royal Canadian Mounted Police surrender responsibility for national security to a civilian agency.
The commission made its recommendation after finding that Mounties had committed crimes such as arson, forgery and breaking and entering in what some of their officers asserted were matters of national security. Though criminal charges were filed against some of the police, none have gone to jail and only one has been convicted.
In making the bill public, Robert Kaplan, who as Solicitor General is the Cabinet member responsible for the police, defended the wide latitude the measure gives to investigators, saying the powers were subject to judicial review and could be enacted only with warrants. He also pointed to a provision of the act precluding the new service from investigating the affairs of people ''solely on the basis of participation in lawful advocacy, protest or dissent.'' 'Beyond the Security Needs'
On the other hand, Alan Borovoy, general counsel of the Canadian Civil Liberties Association, denounced the bill as a ''tremendous breach of powers that seem to go beyond the security needs of the country.'' He said that, once enacted, the measures would ''enable the most intrusive powers of encroachment on peoples' privacy that modern technology permits, including electronic bugging, surreptitious entry, removal of confidential files in circmstances where there is little or no evidence that the law is being broken.''
Burt Neuborne, legal director of the American Civil Liberties Union, reached by telephone in New York, said he believed that under United States law warrants could probably be obtained for each of the actions covered by the Canadian legislation, with the possible exception of breaking and entering.
He added, however, that to obtain warrants investigators would have to demonstrate ''probable cause'' that the contemplated action would yield specified results. The Canadian legislation sets no such limits, obliging judges to be satisfied only that a ''warrant is required to enable the service to perform its duties and functions.'' U.S. and Canada Differ
In the United States, warrants for wiretaps involving national security are applied for before the Foreign Intelligence Surveillance Court, a panel of senior Federal judges sitting in highly confidential proceedings. In Canada, where a written Constitution is only a year old and where basic civil rights are far more qualified than in the United States, the issue of individual rights is unfolding in the courts. The entire issue of admissibility of illegally seized evidence has yet to be resolved, and suits are pending challenging the use of writs of assistance, documents that enable their bearers to conduct indiscriminate searches without warrants.
On the question of permissible investigative techniques, the Canadian Government's bill specifies that with a warrant, employees of the proposed intelligence agency will be able to ''enter any place or open or obtain access to any thing; to search for, remove or return, or make copies of or record in any other manner the information, record, document or thing; or to install, maintain or remove any thing.''
The language of the bill covering the duties of the agency's employees is equally broad. It says, ''The director and employees are justified in taking such reasonable actions as are reasonably necessary to enable them to perform the duties and functions of the service under this act.'' Calls for Written Report
As for instances of possible misconduct, the draft says that if the agency's director believes an employee has ''acted unlawfully in the purported performance of duties,'' he should make a written report to the Solicitor General. It does not say what if anything happens after that.
Another section that has drawn criticism from civil liberties groups is one that makes disclosure of the identity of a clandestine operative a crime. Mr. Borovoy, for example, questioned whether this protection would be used to exempt the appearances of witnesses in court cases. In the United States, when the prosecution chooses not to reveal a witness sought by the defense, in order to protect his identity and further utility, the charges are usually dismissed.
In Canada, the procedure remains unclear. The intent of the section on identity is presumably to protect employees from reprisal or attack, but several commentators in Canada pointed out that had this provision been in effect in 1970, journalists would not have been able to report on the arson and kidnapping and breaking and entering that police officials admitted carrying out in their investigation of Quebec separatists. Superficial Similarity
The basis of this provision has at least a superficial similarity to the Foreign Agents Identities bill passed by the United States Congress last year that, in far more qualifed form with specific exemptions for investigative reporters, makes the naming of Government agents a crime. That law has been criticized by American civil libertarians and faces a constiutional challenge.
In Canada, where the ruling Liberal Party has an ample majority to pass the intelligence agency bill, the greatest political attack so far has come from the New Democratic Party, which commands the third-largest parliamentary bloc after the Liberals and the Conservatives. Svend Robinson, the party's monitor of national security, deplored the legislation as ''a major onslaught on the basic civil rights of Canadians.''

subset: commoncrawl


text:
Pachacuti: 1/1 of 1
Could this be the most ethical hat in the world?
Laura Sevier
6th August, 2009All hail the rise of the Fair Trade Panama hat. Laura Sevier meets ethical fashion pioneer Carry Somers of Pachacuti more...
Pachacuti: 1/1 of 1
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text:
42 U.S. Code § 15908 - Preservation of geological and geophysical data
This section may be cited as the "National Geological and Geophysical Data Preservation Program Act of 2005".
Not later than 1 year after August 8, 2005, the Secretary shall submit to Congress a plan for the implementation of the Program.
The Secretary shall establish, as a component of the Program, a data archive system to provide for the storage, preservation, and archiving of subsurface, surface, geological, geophysical, and engineering data and samples. The Secretary, in consultation with the Advisory Committee, shall develop guidelines relating to the data archive system, including the types of data and samples to be preserved.
The system shall be comprised of State agencies that elect to be part of the system and agencies within the Department of the Interior that maintain geological and geophysical data and samples that are designated by the Secretary in accordance with this subsection. The Program shall provide for the storage of data and samples through data repositories operated by such agencies.
The Secretary may not designate a State agency as a component of the data archive system unless that agency is the agency that acts as the geological survey in the State.
The Advisory Committee shall advise the Secretary on planning and implementation of the Program.
Subject to the availability of appropriations, the Secretary shall provide financial assistance to a State agency that is designated under subsection (d)(2) for providing facilities to archive energy material.
Subject to the availability of appropriations, the Secretary shall provide financial assistance to any State agency designated under subsection (d)(2) for studies and technical assistance activities that enhance understanding, interpretation, and use of materials archived in the data archive system established under subsection (d).
The Federal share of the cost of an activity carried out with assistance under this subsection shall be not more than 50 percent of the total cost of the activity.
It is the intent of Congress that the States not use this section as an opportunity to reduce State resources applied to the activities that are the subject of the Program.
The term "Advisory Committee" means the advisory committee established under section 5 of the National Geologic Mapping Act of 1992 (43 U.S.C. 31d).
The term "Program" means the National Geological and Geophysical Data Preservation Program carried out under this section.
The term "Secretary" means the Secretary of the Interior, acting through the Director of the United States Geological Survey.
There are authorized to be appropriated to carry out this section $30,000,000 for each of fiscal years 2006 through 2010.
[1] See References in Text note below.
The National Geologic Mapping Act of 1992, referred to in subsec. (f)(2), is Pub. L. 102–285, May 18, 1992, 106 Stat. 166, which is classified principally to sections 31a to 31h of Title 43, Public Lands. Par. (3) of section 5(b) of the Act was redesignated par. (4) by Pub. L. 111–11, title XI, § 11001(f)(2)(B), Mar. 30, 2009, 123 Stat. 1415, and is now classified to section 31d(b)(4) of Title 43. For complete classification of this Act to the Code, see Short Title note set out under section 31a of Title 43 and Tables.
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text:
Men's Soccer at UHV
If you are a long-time soccer fan or you have recently discovered what a great sport soccer is, you are in luck! Come and support the UHV Jaguars as they compete against Houston Men's Soccer in the "Red and White" game! The match is Saturday at 5pm at the Cage Soccer Field at UHV, 3007 N Ben Wilson. Admission is FREE! This is bound to be an amazing game so don't miss out! Don't forget to represent our colors!