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|25th week of 2010 patent applcation highlights part 80
|Patent application number
|Scalable RFID systems: a privacy preserving protocol with constant-time identification - A protocol with constant-time complexity solves the problem of private identification of tags in low-cost, large-scale radio frequency identification (RFID) systems—assuming that an adversary has complete control over the communication channel. Each RFID tag has an internal counter, c, and is preloaded with a unique pseudonym, ψ, and a secret key, k. A RFID reader attempting to identify and authenticate a tag within its range generates and transmits a random nonce to the RFID tag, which returns a first hash of its current pseudonym and counter, and a second hash that is a function of the secret key. The reader uses the returned data to identify the RFID tag and its secret key by reference to a database and returns other hash values that authenticate the reader to the RFID tag. The most expensive operation that RFID tags are required to perform is a hash function.
|DATA SECURITY IN AN INFORMATION PROCESSING DEVICE - A device and method for data protection of inputted and stored publicly encrypted data. Publicly encrypted data can be received by a data receiver module and stored in a storage module and be decrypted by a decryption module using a first encryption key. A deciding device can determine whether or not the data needs protection. If necessary, the data can be re-encrypted by an encryption module based on a second and different internal private encryption key generated from the encryption module and stored in the storage module.
|SECURE NETWORK ATTACHED STORAGE DEVICE USING CRYPTOGRAPHIC SETTINGS - A secure storage network includes a secure storage appliance connected to a client via an IP network. The secure storage appliance facilitates storing and reading data in the secure storage network. The secure storage appliance presents a virtual disk to the client via the IP network. The virtual disk is associated with a volume mapped to shares stored on physical storage devices. The secure storage appliance receives various requests from the client. In response to a request to store data to the volume, the secure storage appliance splits and encrypts data into secondary blocks of data and stores the secondary blocks of data to the shares. In response to a request to read data from the volume, the secure storage appliance reconstitutes data from at least a portion of the secondary blocks of data stored in the shares on the physical storage devices.
|VIRTUAL TAPE BACKUP ARRANGEMENT USING CRYPTOGRAPHICALLY SPLIT STORAGE - Methods and systems for providing data backup are disclosed. One method includes receiving at a virtual tape backup system a data image to be maintained, and transmitting the contents of the data image to a secure storage appliance. The method also includes processing the contents of the data image with the secure storage appliance to cryptographically split one or more blocks of data of the data image such that each of the one or more blocks of data is split into a plurality of secondary data blocks. The method further includes storing the plurality of secondary data blocks in a corresponding plurality of shares located on a plurality of physical storage devices.
|RETRIEVAL OF CRYPTOGRAPHICALLY-SPLIT DATA BLOCKS FROM FASTEST-RESPONDING STORAGE DEVICES - A secure storage appliance is disclosed, along with methods of storing and reading data in a secure storage network. The secure storage appliance is configured to present to a client a virtual disk, the virtual disk mapped to the plurality of physical storage devices. The secure storage appliance is capable of executing program instructions configured to generate a plurality of secondary blocks of data by performing splitting and encrypting operations on a block of data received from the client for storage on the virtual disk and reconstitute the block of data from at least a portion of the plurality of secondary blocks of data stored in shares on corresponding physical storage devices in response to a request from the client.
|STORAGE OF CRYPTOGRAPHICALLY-SPLIT DATA BLOCKS AT GEOGRAPHICALLY-SEPARATED LOCATIONS - A secure storage appliance is disclosed, along with methods of storing and reading data in a secure storage network. The secure storage appliance is configured to present to a client a virtual disk, the virtual disk mapped to the plurality of physical storage devices. The secure storage appliance is capable of executing program instructions configured to generate a plurality of secondary data blocks by performing splitting and encrypting operations on a primary data block received from the client for storage on the virtual disk. For security, the secondary data blocks are stored at geographically-distributed locations. The secure storage appliance is also capable of executing program instructions configured to reconstitute the primary data block from at least a portion of the plurality of secondary data blocks stored in shares on corresponding physical storage devices in response to a request from the client.
|STORAGE COMMUNITIES OF INTEREST USING CRYPTOGRAPHIC SPLITTING - Methods and systems of presenting data in a secure data storage network are disclosed. One method includes defining a community of interest capable of accessing data stored in a secure data storage network, the community of interest including a plurality of users desiring access to a common set of data. The method also includes associating the community of interest with a workgroup key. and, upon identification of a client device as associated with a user from among the plurality of users in the community of interest, presenting a virtual disk to the client device, the virtual disk associated with the workgroup key and a volume containing the common set of data, the volume including a plurality of shares stored on a plurality of physical storage devices.
|ADAPTIVE POWER BUDGET ALLOCATION BETWEEN MULTIPLE COMPONENTS IN A COMPUTING SYSTEM - According to some embodiments, a power budget allocation engine of a multi-component computer system may receive a power budget allocation adjustment request signal from a first component. Based on the received budget allocation adjustment request signal (and, in some embodiments, a component preference), the power budget allocation engine may determine whether to adjust a power budget allocation signal provided to the first component.
|COMPUTER SYSTEM AND POWER CONTROL APPARATUS THEREOF - A power control apparatus is disclosed. The power control apparatus includes a temperature sensor, a level-controlling unit, a reset unit and a first voltage converter. The temperature sensor is for sensing an operation temperature of a computer system and accordingly outputs a sensing signal. The level-controlling unit is for deciding whether or not to output a control voltage according to the sensing signal. The reset unit is for producing a reset signal according to a plurality of reference voltages generated by dividing the power voltage and using the control voltage to adjust the levels of the reference voltages. The first voltage converter is for producing a start signal according to the reset signal, wherein the start signal is for enabling the embedded controller.
|Information processing device, information processing system, program and controller - An information processing device is provided. The information processing device which operates upon receipt of power supply from a power unit connected to an alternative current power source or from a battery includes an obtaining unit which obtains load information of parts included in the information processing device itself, a deciding unit which decides a voltage value to be supplied by the power unit which supplies electric power to the information processing device, based on the load information obtained by the obtaining unit, and an output unit which outputs a signal relative to the voltage value decided by the deciding unit to the power unit.
|NETWORK COMMUNICATION SYSTEM FOR UNINTERRUPTABLE POWER SUPPLY AND METHOD FOR DIVIDING CONTROLLER GROUP FOR PERFORMING COMMUNICATION TO CONTROL OPERATING STATUS OF LOAD DEVICE OF UNINTERRUPTIBLE POWER SUPPLY FOR EACH UNINTERRUPTIBLE POWER SUPPLY - Even if a network setting changes due to power interruption or the like, communication for controlling the operating status of load devices of an uninterruptible power supply is enabled to continue. A network communication system (
|SWITCHING POWER CIRCUIT AND COMPUTER SYSTEM - The invention relates to a switching power circuit connected to a motherboard of a computer system. The switching power circuit includes a PWM circuit and a snubber circuit. The PWM circuit includes a phase terminal, and it may output an output voltage to the motherboard via the phase terminal. The snubber circuit includes a zener diode. A negative terminal of the zener diode is connected to the phase terminal, and a positive terminal is connected to the ground terminal. The level of a breakdown voltage of the zener diode is equal to the level of the output voltage in a steady state.
|METHOD AND APPARATUS FOR CONTROLLING INTERRUPTS IN PORTABLE TERMINAL - An interrupt controlling method and apparatus is disclosed. The method and apparatus generates allows a connecting gate to output different signals according to whether charging electric power or communication electric power is supplied to the connector unit of the portable terminal and then outputs them to the power management IC. The power management IC performs a controlling operation in such a way that it can generate only a charging interrupt command if a travel adaptor is connected to the connector unit and generate a communication interrupt when the communication device is coupled to the connector unit.
|REPORTING FLASH MEMORY OPERATING VOLTAGES - Apparatus and associated systems, methods and computer program products relate to using information stored in a flash memory to adjust the operating voltage supplied to the flash memory. The voltage information indicates a minimum operating voltage at which to operate the flash memory device. In general, operating a flash memory device near a minimal operating voltage may substantially minimize power consumption. The minimum operating voltage for individual flash memory devices may vary from IC to IC, by manufacturing lot, and by manufacturer. In a product, the minimum operating voltage for a particular flash memory may be determined, for example, by a controller built-in to a flash memory reporting (automatically or in response to a query) the minimum operating voltage (e.g., 2.5 V, 3.15 V) to a memory controller or microprocessor. The stored voltage information may further include information to adjust the operating voltage based on temperature.
|REMOTE POWER MANAGEMENT SYSTEM AND METHOD FOR CLUSTER SYSTEM - A remote power management technology for a cluster system of the present invention can monitor and control the power status of multiple hosts of the cluster system individually, thereby decreasing power consumption of the cluster system. A remote power management system includes a plurality of management nodes, a power proxy server, and a power management server. The management nodes, which manage power of the hosts of the cluster system respectively, are divided into groups. The power proxy server manages each group, monitors the power status of each management node of the group to generate proxy monitoring information, and transmits a power setting command to the management node of the specific host requiring power setting. The power management server monitors the power status of the hosts using the proxy monitoring information and transmits the power setting command to the power proxy server of the group including the management node of the specific host.
|Low power polling techniques - Techniques are described to provide the capability to halt execution of a thread by a processor and potentially lower power consumption of the processor while responding to events in a timely manner. An operating system provided system call allows for identification of events that cause the execution of the thread to resume. A processor core uses a signal mask and translation unit that monitors for the identified events. In the event an event is detected, the thread unhalts and determines a manner to process the event.
|ENERGY SAVING SUBSYSTEM FOR AN ELECTRONIC DEVICE - The instant invention broadly contemplates an energy saving subsystem comprising a secondary CPU that utilizes less power than a main CPU, thereby allowing an electronic device (e.g. a laptop PC) having the secondary CPU to use less power and run for longer periods of time on a limited power supply. Thus, the invention permits the electronic device to be utilized for extended periods and extends the battery life.
|LOW POWER CONSUMPTION PROCESSOR - Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.
|SYSTEMS AND METHODS FOR IMPLEMENTING STANDBY FUNCTIONALITY USING FIELD PROGRAMMABLE GATE ARRAYS - The disclosed embodiments relate to an electronic device comprising a logic circuit comprising a plurality of logic banks. In accordance with embodiments of the present technique, at least one of the plurality of banks is configured to provide standby functionality to the electronic device. The electronic device further comprises a power supply coupled to the logic circuit, configured to power the at least one bank without powering all of the plurality of banks.
|SYSTEM AND METHOD FOR OPTIMIZING ELECTRICAL POWER CONSUMPTION - A system and a method for optimizing power in an electronic device are described. The system may be used to implement low power techniques to achieve maximum performance with low battery utilization. A processing load level monitor monitors load(s) on processors. Processor frequencies are updated through the driver until the load is close to 100%, which means that the core frequency is changed to the load processor around 100% at the minimum possible frequency.
|POWER MANAGEMENT IN A DEVICE - Implementations of power management in a device are described. The device includes a power driver configured to manage power supply to one or more components in system-on-chip (SOC) hardware. The device further includes power subsystems configured as drivers for controlling the components of the SOC hardware and a user interface configured to receive a selected power mode as an input and identify profiles of one or more applications being executed in the device. Based on the selected power mode, the power driver directs the power subsystems to change a mode of operation of at least one component determined from the profiles of the one or more applications being executed.
|Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device - A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
|SYSTEM AND METHOD FOR EXTENDING THE BATTERY LIFE OF A MOBILE DEVICE - The present invention provides a system and method for extending the battery life of a mobile device. The method of extending the battery life of a mobile device can be broadly summarized by the following steps of determining if at least one component on the mobile device can be placed in a hibernation state for a predetermined time, setting a remote clock to the current time, and powering off the at least one component on the mobile device that can be placed in the hibernation state. The method further includes waiting a predetermined interval, re-activating the at least one component on the mobile device that was placed in the hibernation state, and synchronizing a system clock with the remote clock.
|Apparatus and method for supporting selective suspend mode of USB network-device - A host computer equipment includes an apparatus configured to perform a method for supporting a selective suspend mode of a Universal Serial Bus (USB) network-device. The host includes a power manager, a status manager, and a USB driver. When there is a transition to a host suspend mode, the power manager delivers a host suspend mode notification message to the status manager. The status manager delivers a status transition message of instructing a normal status (D
|METHOD AND APPARATUS OF POWER MANAGEMENT OF PROCESSOR - A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
|Enabling a Charge Limited Device to Operate for a Desired Period of Time - A charge limited device that has only limited access to power can be operated to ensure a given operating time. The operating time may, for example, correspond to the time period between recharging of a battery. Instead of simply reducing power consumption, a budget is developed that enables dynamic monitoring of power consumption over that time to ensure that actual power consumption conforms to the budget.
|METHOD OF MONITORING THE POWERING OF A REMOTE DEVICE THROUGH A LAN LINE AND RELATIVE CIRCUIT - A circuit is for monitoring the powering of a remote device through a LAN without generating an extra biasing voltage higher than the DC power supply voltage. DC voltage used for supplying the remote device is applied to the LAN line while an AC voltage is applied to the line for monitoring whether the remote device is connected to the LAN line. The DC voltage is applied to a first or "high" terminal and the AC voltage is applied to the other or "low" terminal of the LAN line through a decoupling capacitor. This arrangement allows the supplying of the remote device with a large DC voltage compatible with a fully integrated AC signal generator, disconnection detector, and PSE controller, and enhances the reliability of the recognition of whether the powered device is connected to, or disconnected from, the LAN line.
|METHOD AND APPARATUS FOR ACCURATELY SYNCHRONIZING SIGNALS RELATED TO THE OPERATION OF A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that accurately synchronizes signals related to the operation of a computer system. During operation, the system receives a first time-domain signal associated with a first system variable and a second time-domain signal associated with a second system variable from the computer system. The system then transforms the first and the second time-domain signals into a first frequency-domain signal and a second frequency-domain signal, respectively. Next, the system computes a cross-power-spectral-density (CPSD) between the first and second frequency-domain signals to obtain a phase angle versus frequency graph between the two frequency-domain signals. The system subsequently extracts the slope of the phase angle versus frequency graph, and uses the value of the slope to synchronize the first time-domain signal and the second time-domain signal.
|HEALTH CAPABILITY DETERMINATION SYSTEM AND METHOD - A system and method are provided for the determining of the potential effect(s) that a degraded system, subsystem, or component may have on the overall capabilities of a vehicle or other system, and any mitigating actions that may need to be taken. Mission-related capabilities of the system are decomposed into a plurality of lower-level capabilities that have an impact on the mission-related capabilities. One or more faults that have an impact on at least one of the lower-level capabilities are mapped to appropriate lower-level capabilities. The lower-level capabilities to which the one or more vehicle faults is mapped are computed, and values of the mission-related capabilities are computed from each of the lower-level capabilities.
|VIRTUAL PROCESSOR METHODS AND APPARATUS WITH UNIFIED EVENT NOTIFICATION AND CONSUMER-PRODUCED MEMORY OPERATIONS - The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, "threads"). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, "thread") executing within such processor can execute a memory instruction (e.g., an "Empty" or other memory-consumer instruction) that permits the thread to wait on the availability of data generated, e.g., by another thread and to transparently wake up when that other thread makes the data available (e.g., by execution of a "Fill" or other memory-producer instruction).
|SYSTEMS AND METHODS FOR PROCESS IMPROVEMENT IN PRODUCTION ENVIRONMENTS - A computer-implemented method is provided for identifying a root cause associated with a problem in a production environment. The method includes receiving information indicative of a point-of-origin of the problem. The method further includes providing a cause-and-effect chart having a plurality of user-definable general cause categories, each of the general cause categories having at least one user-definable direct cause subcategory. The method further automatically identifies a primary direct cause of the problem based on the user-defined general cause categories and direct cause subcategories. The method further includes automatically generating a root cause analysis report associated with the primary direct cause, where generating the report includes displaying the cause-and-effect chart and prompting the user for a response to a first of a plurality of questions, wherein the response to the first of the plurality of questions automatically prompts the user for a response to a second of a plurality of questions.
|METHOD AND APPARATUS FOR INITIATING CORRECTIVE ACTION FOR AN ELECTRONIC TERMINAL - A method and device are provided for initiating corrective actions for a terminal, such as an ATM. A method of initiating corrective actions for a terminal comprises, monitoring a fault status of a first component, detecting a fault status of the first component with a first trigger plug-in, activating a first action plug-in based upon the detected fault status of the first component, and recycling the first component.
|STORAGE AVAILABILITY USING CRYPTOGRAPHIC SPLITTING - A secure storage appliance is disclosed, along with methods of storing and reading data in a secure storage network. In one aspect, a method includes assigning a volume to a primary secure storage appliance located in a secure data storage network, the secure data storage network including a plurality of secure data paths between the primary secure storage appliance and a client device and a plurality of secure data paths between the secure storage appliance and a plurality of storage systems, the volume corresponding to physical storage at each of the plurality of storage systems. The method also includes detecting a connectivity problem on at least one of the secure data paths. The method further includes assessing whether to reassign the volume to a different secure storage appliance based upon the connectivity problem.
|STORAGE AVAILABILITY USING CRYPTOGRAPHIC SPLITTING - Methods and systems for maintaining data connectivity in a secure data storage network are disclosed. In one aspect, a method includes assigning a volume to a primary secure storage appliance located in a secure data storage network the primary secure storage appliance selected from among a plurality of secure storage appliances located in the secure data storage network, the volume presented as a virtual disk to a client device and mapped to physical storage at each of a plurality of storage systems. The method further includes detecting at one of the plurality of secure storage appliances a failure of the primary secure storage appliance. The method also includes, upon detecting the failure of the primary secure storage appliance, reassigning the volume to a second secure storage appliance from among the plurality of secure storage appliances, thereby rendering the second secure storage appliance a new primary secure storage appliance.
|ETHERNET APPARATUS CAPABLE OF LANE FAULT RECOVERY AND METHODS FOR TRANSMITTING AND RECEIVING DATA - An Ethernet apparatus for performing lane fault recovery is provided. An Ethernet apparatus capable of lane fault recovery includes a data transmitter using a backup lane in the transport link to transmit data intended to be transmitted via the faulty lane when at least one faulty lane is detected from the data transfer lanes, and a data receiver recognizing the data received via the backup lane as data transferred via the faulty lane when the faulty lane is detected. In an Ethernet apparatus having a multi-lane structure, a lane fault and faulty lanes can be accurately recognized while maintaining compatibility with a standard Ethernet apparatus.
|System and Method for Providing IP PBX Service - A telecommunications system has been developed that includes an on premise IP PBX and an offsite hosted IP PBX. The system includes software that allows migration of data between the PBXs as needed by system requirements.
|Multipurpose Storage System Based Upon a Distributed Hashing Mechanism with Transactional Support and Failover Capability - A multipurpose storage system based upon a distributed hashing mechanism with transactional support and failover capability is disclosed. According to one embodiment, a system comprises a client system in communication with a network, a secondary storage system in communication with the network, and a supervisor system in communication with the network. The supervisor system assigns a unique identifier to a first node system and places the first node system in communication with the network in a location computed by using hashing. The client system stores a data object on the first node system.
|Self-Monitoring Cluster of Network Security Devices - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed.
|Memory System having Spare Memory Devices Attached to a Local Interface Bus - A memory system includes a memory controller, one or more memory channel(s), and a memory subsystem having a memory interface device (e.g. a hub or buffer device) located on a memory subsystem (e.g. a DIMM) coupled to the memory channel to communicate with the memory device(s) array. This buffered DIMM is provided with one or more spare chips on the DIMM, wherein the data bits sourced from the spare chips are connected to the memory hub device and the bus to the DIMM includes only those data bits used for normal operation. The buffered DIMM with one or more spare chips on the DIMM has the spare memory shared among all the ranks, and the memory hub device includes separate control bus(es) for the spare memory device to allow the spare memory device(s) to be utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem.
|Nonvolatile/Volatile Memory Write System and Method - Methods and systems provide memory handling for memory systems with mixed volatile and nonvolatile memory types. In various embodiments, the method or system maintains a page table that marks memory pages in nonvolatile memory as write-protected. When a write is attempted to a write-protected page in nonvolatile memory, a fault is generated. In response to the fault, memory contents of the write-protected nonvolatile page are moved to a page location in a volatile memory.
|High Availability and Disaster Recovery Using Virtualization - There is disclosed apparatus and processes which address problems in the area of providing high availability and disaster recovery for computing systems and the data in them. These apparatus and processes can be used to provide high availability and disaster recovery for a computing system to be protected. The protected computing systems may be virtual computing systems.
|MEMORY SYSTEM AND COMPUTER SYSTEM - A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.
|FETCH OPERATION SCHEDULING - Fetch operations are assigned to different threads in a multithreaded environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a sub-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. Two-level priority scheme is used to combine both priorities. The judgement of satisfactory performance is preferably based on the difference between a desired number of fetch operations attributed per sub-context switch interval to each thread and a real number of fetch operations attributed per sub-context switch interval to each thread.
|MULTIPROCESSOR SYSTEM AND CONTROL METHOD THEREOF - A multiprocessor system is disclosed. The multiprocessor system includes plural processor cores to which control to be performed is allocated. The multiprocessor system includes a monitoring processor which detects an abnormal operation that has occurred in a specific processor core to which control having a higher priority order than control to be allocated to processor cores other than the specific processor core is allocated. When the monitoring processor detects the abnormal operation in the specific processor core, the monitoring processor allocates the control having the higher priority order to one of the processor cores other than the specific processor core.
|Method, Apparatus, and System for Restarting an Emulated Mainframe IOP - A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs.
|METHOD FOR ERASURE CODING DATA ACROSS A PLURALITY OF DATA STORES IN A NETWORK - An efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. A data store is a persistent memory for storing a data block. Such data stores include, without limitation, a group of disks, a group of disk arrays, or the like. An encoding process applies a sequencing method to assign a sequence number to each data and checksum block as they are modified and updated onto their data stores. The method preferably uses the sequence number to identify data set consistency. The sequencing method allows for self-healing of each individual data store, and it maintains data consistency and correctness within a data block and among a group of data blocks. The inventive technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.
|METHOD, APPARATUS AND SYSTEM FOR RESTARTING AN EMULATED MAINFRAME IOP - A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs.
|ON-CHIP SERVICE PROCESSOR - An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
|SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TESTING A BOOT IMAGE - According to one embodiment of the present disclosure, a method for testing a boot image is disclosed. The method comprises creating a test boot image for a first logical partition, creating a second logical partition wherein the second logical partition is a duplicate of the first logical partition, initiating a boot sequence for the second logical partition using the test boot image, and returning a result of the boot sequence to a requestor.
|APPARATUS AND METHOD FOR AUTOMATIC SELF-DIAGNOSIS USING UNIVERSAL SERIAL BUS PORT IN DIGITAL EQUIPMENT - An apparatus and a method for automatically performing self-diagnosis are provided. In the method, when an external storage unit is connected, files stored in the external storage unit are searched for. When a diagnosis file for self diagnosis is stored in the external storage unit, information of at least one item required by the diagnosis file is collected. The collected information is stored as an output file in the external storage unit.
|Low Privilege Debugging Pipeline - A low privilege debug pipeline publisher advertises a debugging pipeline. Instead of having a client to which a debugger on the server has been attached interrogate the server for debugging information, the client requests information from the server. Control is returned to the server which can refuse to provide the requested information to the client. A debuggee server executes client code being debugged in an isolated context so that pausing the code at a breakpoint does not block the server. The server can apply transforms to compiled code to make the code cooperate with debugging services so that a privileged component to inspect the debuggee code is not needed.
|FAULT REPLAY SYSTEM AND METHOD - A fault replay system uploads part or all of a log file from a subject system and replays the events detailed within the log file upon physical copies of devices present in the subject system. The replay of the log file events aid the determination of at which event a fault occurred and improves the accuracy of fault determination.
|INTEGRATION AGENT DEVICE FOR NODE INCLUDING MULTI-LAYERED EQUIPMENT AND FAULT MANAGEMENT METHOD THEREOF - An integration agent device and its fault management method for a node including multi-layered devices are disclosed to effectively control a node including two or more communication devices of different layers and integrally processing relevant fault information. The integration agent device includes: one or more control and management modules controlling and managing one or more communications network devices by layer; and an inter-layer interworking processing module integrating and processing information of the communications network devices by using inter-layer interworking information, and notifying a management system accordingly, wherein the information of the communications network devices is transmitted through the one or more control and management.
|VIRTUAL MACHINE CONTROL PROGRAM, VIRTUAL MACHINE CONTROL SYSTEM, AND DUMP CAPTURING METHOD - A virtual machine control system includes a dump target setting module that sets a flag that represents that a memory area is a dump target to each memory area that has been used by a guest OS, a dumping module that dumps to a file the memory area to which the dump target setting module sets the flag, and that removes the flag from the memory area about which dumping is completed, and a virtual machine control module that controls implementation of the guest OS, which operates on the virtual machine, and stops the implementation of the guest OS until the dumping module removes the flag from the memory area when the guest OS tries to access the memory area to which the dump target setting module sets the flag.
|ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICES - A system including one or more memory devices, and an error detection and correction method are disclosed. A memory device of the system includes an input for receiving a packet. A first portion of the packet may include at least one command byte, and a second portion of the packet may include parity bits to facilitate command error detection. The memory device may include an error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte, and circuitry configured to provide the packet to the error manager.
|DETECTION OF AND RECOVERY FROM AN ELECTRICAL FAST TRANSIENT/BURST (EFT/B) ON A UNIVERSAL SERIAL BUS (USB) DEVICE - An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst controller. The USB core provides serial communications with a host device through a USB data channel. The burst controller is coupled to the USB core. The burst controller detects an EFT/B event and automatically reconnects the USB core to the host device in response to recognition of a suspend state of the USB core by the host device.
|MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD - A memory system includes a nonvolatile memory, a volatile buffer memory connected to the nonvolatile memory, an error counting unit that detects, for each of divided areas formed by dividing a storage area of the volatile buffer memory into a plurality of areas, a parity error in inputting data to and outputting data from the divided areas and counts a number of times of accumulation of the parity error, and a control unit that sets the divided area, in which the number of times of accumulation of the parity error counted by the error counting unit exceeds a predetermined number of times, in a disabled state.
|SEMICONDUCTOR DEVICE - A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (
|Method for Detecting Disturb Phenomena between Neighboring Blocks in Non-volatile Memory - A method for detecting disturb phenomena between neighboring blocks in non-volatile memory includes, sequentially erasing and writing test data (pattern) to each block of a plurality of blocks under test in the non-volatile memory at a first time point, dividing the plurality of blocks under test into a first block group and a second block group based on ordinal number included in each block of the plurality of blocks under test, reading data from each block of the first block group at a second time point, and comparing the data with the test data written at the first time point to generate a first detecting result, and determining applicability of each block of the first block group based on the first detecting result.
|SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION - Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.
|CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.
|DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK MODIFIER ON AN IC - A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.
|TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
|DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
|Control of clock gating - Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value.
|METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.
|Protecting integrity of data in multi-layered memory with data redundancy - Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.
|Acceleration of header and data error checking via simultaneous execution of multi-level protocol algorithms - An error detection system and methodology where the undesirable consequence of encapsulation (additional latency or delay) for virtualization applications such as i-PCI or iSCSI is minimized for the vast majority of data transactions. Cyclic Redundancy Checks (CRCs) and checksums are executed simultaneously in parallel, immediately on reception of a data packet regardless of the relative processing order in relation to the OSI model.
|Memory scrubbing in third dimension memory - A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell.
|MEMORY DEVICE - A memory device including: a memory cell array; an error-detecting and correcting circuit; and a buffer register disposed for temporally storing write and read data. Write data loaded in the buffer register are encoded in the error-detecting and correcting circuit to be over-written in the buffer register together with check bits, and then transferred to be written into the cell array. Read data read from the cell array and held in the buffer register together with check bits are decoded in the error-detecting and correcting circuit to be corrected, over-written in the buffer register and then output.
|Dynamic interference avoidance with asynchronous HARQ - In a wireless communications network, a wireless device may examine the received signal to determine the strength of the received signal, and also determine the level of interference and noise. If a retransmission is needed due to a message being incorrectly received, these factors may then be processed to estimate whether the probable cause of poor reception is interference from a neighboring network. If such interference is the likely cause, the retransmission may be changed to a different time and/or to different frequencies in a subsequent frame, so that the interference from the neighboring network is less likely to reoccur.
|METHOD AND APPARATUS FOR OPTIMIZING A RETRY LIMIT FOR MULTIMEDIA SYSTEMS THAT ARE PRONE TO ERRORS - Devices, systems and methods for optimizing a number of retransmission attempts in a multimedia environment and managing delays in a host MAC layer. In its various aspects, the presently claimed invention includes several methodologies and systems that are configured for determining an optimal retry limit in response to one or both of a packet error rate bound and a latency bound. To the extent that the retry limit is determined with respect to one of the aforementioned boundaries, the presently claimed invention may include determining a confidence level that the non-selected bound will also be met by the selected retry limit. The presently claimed invention details devices, systems and methods optimizing the number of retransmission attempts to ensure delivery of the selected data packets while guarding against undue delays and application disruptions.
|CIRCUITS FOR IMPLEMENTING PARITY COMPUTATION IN A PARALLEL ARCHITECTURE LDPC DECODER - A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a "compute
|Processing of Biometric Data by Transformation - Biometric data relating to a biological part are processed by obtaining, on the one hand, a first set of transformed biometric data (f(B
|BIT MAPPING/DEMAPPING METHOD AND APPARATUS FOR COMMUNICATION SYSTEM - An improved bit mapping method and apparatus for a communication system is provided. A bit mapping method of the present invention includes arranging coded bits in a codeword in an order of recovery capability; setting a shift region including a number of coded bits; rearranging the coded bits in the shift region by shifting the shift region by a number of bits equal to a number of bits that is indicated by a shift factor; and mapping the rearranged coded bits into a modulation symbol in an order of reliability from a lowest reliability bit position to a highest reliability bit position of the modulation symbol.
|APPARATUS AND METHOD FOR CODING QC-LDPC CODE - A high-speed quasi-cyclic low density parity check (QC-LDPC) coding apparatus for coding inputted information into a generator matrix having a dual diagonal matrix format includes: a parity bit generation unit configured to generate an arbitrary parity bit; a temporary parity bit generation unit configured to constitute the inputted information with circulants, and shift and combine the respective circulants at each row to generate a temporary parity bit; a corrected bit generation unit configured to generate corrected bits of parity bits by using an output of the temporary parity bit generation unit; and a parity bit correction unit configured to correct the temporary parity bit by reflecting an output of the corrected bit generation unit to the output of the temporary parity bit generation unit.
|Low complexity LDCP decoding - A technique for low-density parity-check (LDPC) coding involves utilizing a fixed point implementation in order to reduce or eliminate reliance on floating point operations. The fixed point implementation can be used to calculate check node extrinsic L-value as part of an LDPC decoder in an LDPC system. The technique can include one or more of linear approximations, offset approximations, and node-limiting approximation. A system constructed according to the technique implements one or more of linear approximations, offset approximations, and node-limiting approximation.
|METHOD FOR LOCK-FREE CLUSTERED ERASURE CODING AND RECOVERY OF DATA ACROSS A PLURALITY OF DATA STORES IN A NETWORK - The present invention provides a distributed clustering method to allow multiple active instances of consistency management processes that apply the same encoding scheme to be cooperative and function collectively. The techniques described herein facilitate an efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. The technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.
|METHOD AND APPARATUS FOR MAP DECODING AND TURBO DECODER USING THE SAME - A Maximum A Posteriori (MAP) decoder and a MAP decoding method are provided. The MAP decoder includes a first metric operation unit, a first bit-width control unit, a second metric operation unit, a Log Likelihood Ratio (LLR) operation unit, and a second bit-width control unit. The first metric operation unit outputs a first metric data using an input data. The first bit-width control unit controls a bit-width of the first metric data according to a modulation scheme of the input data. The second metric operation unit outputs a second metric data using the first metric data having the controlled bit-width. The LLR operation unit outputs LLR data using the second metric data. The second bit-width control unit outputs decoding data by re-controlling the bit-width of the LLR data.
|TELECOMMUNICATION SYSTEM AND RELATED METHODS - A telecommunication system and related methods. Implementations may include implementations of a method of encoding data for transmission, including forming a frame by encoding a message block using a short-block low density parity check (LDPC) code and an encoder to form a short encoded block, modulating the short encoded block using a modulation format and a modulator to form a modulated short encoded block, including the modulated short encoded block in a data payload of the frame, and transmitting the frame into a telecommunication channel with a transmitter. The frame may be one of a plurality of frames and each modulated short encoded block in each of the plurality of frames may have a constant number of symbols. The frame may include a modulation/code pair (ModCod) including information relating to the modulation format and the short-block LDPC code used for encoding and modulation.
|METHOD AND APPARATUS FOR PROCESSING DATA - A method of processing data, the method including decoding extracted data, correcting errors of the decoded data and generating data bits and data bit flags indicating error-corrected data bits from among the data bits, re-decoding the extracted data according to the data bits and the data bit flags, and correcting errors of the re-decoded data.
|STORAGE APPARATUS HAVING NONVOLATILE STORAGE MODULE - According to one embodiment, a storage apparatus includes a first nonvolatile storage module, a second nonvolatile storage module, and an error checking and correction module. The first nonvolatile storage module undergoes a destructive read when data is read from it. The second nonvolatile storage module stores the address data representing the storage location in the first nonvolatile storage module at which data to be read is stored. The error checking and correction module checks for and corrects an error in the data stored at the storage location in the first nonvolatile storage module which is represented by the address data stored. The error checking and correction module writes the corrected data back into the first nonvolatile storage module.
|NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a nonvolatile memory device comprises performing a read operation to read data stored in a first memory cell block including first unit groups; detecting a second unit group from among the first unit groups, the second unit group having a number of error bits included in the read data, which is greater than a set number of bits and equal to or smaller than a maximum allowable number of bits which can be corrected through an error checking and correction (ECC) processing; and after the second unit group is detected, performing a copyback operation for moving the data, that are stored in the first memory cell block, to a second memory cell block.
|CONTROL DEVICE, STORAGE APPARATUS AND CONTROLLING METHOD - A control device operable under a power supplied from a main power source, the control apparatus includes a memory for storing data with an error detection code, the data being used for execution of processing, a judging section for judging whether an error in the data stored in the memory by the power from a sub power source is detected using the error detection code after the power from the main power source to the memory has been resumed. The control apparatus includes a processing control section for continuing execution of the processing using the data stored in the memory if it has been judged that no error in the data stored in the memory is detected by the judging section, and executing a recovery processing if it has been judged that an error in the data stored in the memory is detected.
|FLASH MEMORY CONTROLLER, ERROR CORRECTION CODE CONTROLLER THEREIN, AND THE METHODS AND SYSTEMS THEREOF - An ECC controller comprises an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to generate ECC data with different lengths in response to information data to be stored into a flash memory. The ECC divider is configured to divide each ECC datum generated by the ECC encoder into one or more ECC segments according to the length of the ECC datum. The ECC constructor is configured to generate an ECC datum by combining one or more ECC segments for each information datum read from the flash memory. The ECC decoder is configured to correct the errors of the information data read from the flash memory device by using the ECC data generated by the ECC constructor.
|Data error recovery in non-volatile memory - When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify 'low confidence' memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.
|Solid-state storage device including a high resolution analog-to-digital converter - A storage device includes a solid-state storage medium having a plurality of cells adapted to store data and an analog-to-digital converter (ADC) coupled to at least one cell of the plurality of cells. The ADC includes a first operating mode having a first number of quantization levels to determine a value stored in the at least one cell based on a number of possible values represented by the at least one cell. The ADC further includes a second operating mode having a second number of quantization levels to determine the value stored in the at least one cell, where the second number of quantization levels is greater than the first number of quantization levels. The ADC selectively enables the first or the second operating mode as a selected operating mode and determines a signal representative of the value stored in the at least one cell using the selected operating mode.
|SOFT DECISION DEVICE AND SOFT DECISION METHOD - A soft decision device and method for obtaining a soft decision value as a value expressing a probability as near the actual probability as possible by simple processing. The soft decision device and method are used to output a soft decision value for each bit of each symbol used for decoding the each symbol as a value corresponding to the function value obtained by applying a predetermined function for each bit to the sampled value of the each symbol according to the demodulated signal such that the probability distribution of the sampled value in each symbol point is the Gauss distribution. The function for each bit is approximated to a curve expressing the probability that each bit is 1 or 0 for the sampled value of each symbol of the demodulated signal and defined by using a quadratic function.
|METHOD OF DETECTING AND CORRECTING A PRESCRIBED SET OF ERROR EVENTS BASED ON ERROR DETECTING CODE - A method of constructing an effective generator polynomial for error correction by which a unique set of syndromes for each error event is produced is provided. The method includes preparing a set of dominant error events from the intersymbol interference characteristics of media; and generating a codeword from the data using a non-primitive generator polynomial that produces a unique syndrome set which can completely specify each dominant error event.
|XOR CIRCUIT, RAID DEVICE CAPABLE OF RECOVERING A PLURALITY OF FAILURES AND METHOD THEREOF - An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device.
|PACKET PROCESSING APPARATUS AND METHOD CAPABLE OF GENERATING MODIFIED PACKETS BY MODIFYING PAYLOADS OF SPECIFIC PACKETS IDENTIFIED FROM RECEIVED PACKETS - A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.
|Method of detecting data transmission errors in a CAN controller, and a CAN controller for carrying out the method - A method of detecting data transmission errors in a CAN controller includes generating at least one check bit that is verifiable for ensuring the consistency of the transmitted data. A CAN controller that ensures continuous error monitoring during data transmission includes an interface unit for exchanging data with a CAN bus, a memory unit for storing received data and data to be transmitted, and an electronic unit for controlling data transmission between the memory unit and the interface unit. The interface unit of the CAN controller has an arrangement for generating check bits for received data and for verifying check bits for data to be transmitted.
|Methods and Apparatus for Internet Browsing and Searching Employing Geographic Location Information - Systems and techniques for managing Internet navigation and browsing results and other information using a visual geographic interface. A user interface including a map display is presented, along with interface elements for searching, browsing, and otherwise retrieving information. Results lists are compiled based on user inputs and geographic information is associated with each item in the results list. The items in the results list are presented to the user in a map display, with facilities for changing the organization and presentation of results according to user inputs including graphical inputs defining geographic areas of interest.
|APPLYING EFFECTS TO A VIDEO IN-PLACE IN A DOCUMENT - An application program utilizes a decoding sub-system and a three-dimensional (3D) rendering sub-system to apply effects to a video in-place in a document. The program configures pixel shaders for use with a rendering device for applying pixel-level effects to the decoded frames of the video, generates meshes, and pre-renders textures for use in implementing effects. When a request is received to play back the video in-place in the document, a decoding surface and a rendering surface are allocated. The decoding sub-system decodes frames of the video and copies the decoded frames to the decoding surface on one thread. A separate thread copies decoded frames from the decoding surface to a texture and from the texture to the rendering surface. The rendering device utilizes the pixel shaders, meshes, pre-computed textures, and other data to render the frames of the video to a rendering target.
|IDENTIFYING COMMENTS TO SHOW IN CONNECTION WITH A DOCUMENT - A system may identify a comment that includes a number of links, each of the links points to a corresponding document; identify one or more factors associated with each of the links, the one or more factors including at least one of: a click through rate associated with the links, explicit user feedback regarding the links, a length of an address associated with the links, a measure of popularity associated with the document corresponding to the links, or a comparison of a topic associated with the comment and a topic associated with the document corresponding to the links; assign a score to the links based on the one or more factors; select one of the links based on the assigned scores; and provide information regarding the comment to a client device for presentation in connection with presentation of the document corresponding to the selected link.
|PROVIDING INTERACTIVE FORMS IN WEB APPLICATION SOFTWARE - Systems and processes for providing interactive forms in Web application software and described. Example embodiments provide for receiving a specification of an interactive form, including an ordered sequence of components specifying text input fields and line separators. Embodiments also provide for dynamically generating interactive forms for display according to the specification.
|DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A technique is provided which improves the ease-of-use of the screen which integrally displays multiple content.
|Techniques for Utilizing Dynamic Components with Wikis - Various technologies and techniques are disclosed for integrating wiki content with one or more dynamic components. A web page is output that contains wiki content that can be edited in a visual text editor. A selection is received from a user to add a dynamic component to the web page from within the visual text editor. A revised version of the web page is output for display. The revised version of the web page includes the dynamic component along with the wiki content. Techniques for parsing web pages having wiki content and dynamic components are also described that use a tag to indicate that the dynamic component is present.
|ROBUST WRAPPERS FOR WEB EXTRACTION - A computer-implemented method to determine a robust wrapper includes developing a model indicative of the temporal history of a document, such as a web document written in a markup language. Based on the developed model, robustness characteristics are determined for a plurality of different wrappers representing associated paths to the data item in a representation of the document. Based on a result of the determining operation, a result wrapper of the plurality of wrappers is provided. The result wrapper has a desired robustness characteristic.
|METHOD AND SYSTEM FOR DISPLAYING VARIABLE SHAPED PRODUCTS ON A COMPUTER DISPLAY - A computerized system, method, and computer-readable media implementing a method for defining a variable shaped document for web viewing is presented. Markup language descriptions are defined for cutlines defining a shape of an item to be produced, and for content to be displayed on the item within the boundaries of the cutlines. Markup language rules area defined that prevent display of content in areas on a display screen outside the defined shape of the item to be produced.


text:
Quick goal remedy for Cup time-wasters
The Socceroos say the only way to avoid the frustration of the time-wasting tactics so often employed by Jordan is to score early in their World Cup qualifier on Tuesday.
Both Mark Bresciano and Sasa Ognenovski - who play their club football in the Middle East and know well what to expect - say an early Socceroos goal will ensure the visitors will have to play rather than park the bus at Etihad Stadium.
And it would also mean the feigning injury as a time-wasting tactic so hated by Australia's players would also not come into play on Tuesday night.
"Score early, and you make them impact the game. If they need a result, they're going to have to do that (score themselves)," said centre-half Ognenovski.
"I'm sure they won't be rolling around on the ground if they need a win."
And Bresciano added: "I'm thinking if they have the result they want, they're going to do the same thing (waste time) - that's part of their tactics.
"We've just got to hope that it's never going to get to that situation. We're hoping from the whistle that we can hurt them."
Jordan need three points as much as the Socceroos.
Otherwise a draw leaves the Jordanians facing a sudden-death situation, in which they'd need all three points against Oman in their last game to have any hope of qualifying.
Bresciano said he hoped Jordan's need for a win would encourage them to attack more, believing the Socceroos play their best against teams who play an open brand of football.
"I hope they do come out and play open, and not try to park the bus," he said.
"Personally, I think as a team, we play better when it's an open game, where we have teams that come to us and try and play their football, and obviously try to attack. They're the games we perform our best."
Ognenovski agrees.
"They're going to come into the game wanting to win, because if they do they've got one foot in the door for the World Cup.
"If they come here and attack, hopefully it works in our favour."
The Socceroos will guarantee themselves a World Cup berth with wins in both the match against Jordan and their final qualifier against Iraq on June 18 in Sydney.
Otherwise, they will need other results to go their way or possibly face a third-place finish and further playoffs through Asia and South America to win a spot in Brazil.
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subset: commoncrawl


text:
© The Financial Times Ltd 2016
FT and 'Financial Times' are trademarks of The Financial Times Ltd.
The Financial Times and its journalism are subject to a self-regulation regime under the FT Editorial Code of Practice.
September 19, 2011 12:48 am
The economic crisis in Greece is taking a heavy toll on local companies, steeply reducing demand for highly qualified executives.
Large companies are downsizing, while the small and medium-sized businesses that dominate the private sector are struggling to survive.
Yet the handful of Greek business schools, which have a combined annual intake of 800-900 students for MBA programmes, are proving surprisingly resilient. One reason is that more young Greeks are opting for a domestic institution, given circumstances at home and the cost of studying in the UK, the most popular MBA destination.
Another reason is that legislation to prise open the Greek state's formal monopoly of higher education is making its way through parliament. According to Anna Diamantopoulou, the education minister, the law – due to be approved this month – will allow sponsors from the private sector to fund graduate programmes at state universities.
"We are opening up the universities to the private sector – they will be able to co-operate with individual companies and accept sponsorship and donations," she says.
The former European commissioner admits there is no timetable for lifting Greece's constitutional ban on private universities, which has constrained the development of business education. But analysts say the government's policy of back-door liberalisation could unleash pent-up demand for high-quality offerings.
Diamantopoulou says: "We hope the legislation will encourage universities to expand graduate studies in business, technology and science, and attract Greek academics who have made careers abroad."
The law should also make life easier for private business schools that are not fully recognised by the Greek state. Alba Graduate Business School, for example, offers Amba-accredited degree courses run by academics who have studied and taught at leading institutions abroad, but is unable to win parity status with the state universities.
Professor Nickolaos Travlos, dean, says: "Greece has excellent human capital, but our potential for development has been adversely affected by the overall operating environment."
One business school belonging to a state institution has shown what can be achieved in challenging times. The MBA programme at Athens University of Economics and Business is designed for about 50 students with 3-5 years' work experience. Last year, just more than half the intake were Greeks, with the remainder coming from 13 countries. About 95 per cent of students found a suitable job within two months of graduating.
AUEB operates from a "no-frills" campus covering several unassuming buildings in a gritty downtown Athens district. "We do need a bigger campus. Our amphitheatre only fits 50 people, for example," says Professor Gregory Prastacos, rector and director of the international MBA programme.
Despite the recession, the course is oversubscribed, with international applicant numbers stable and "Greeks just a bit lighter", says Prof Prastacos.
AUEB has led the way in attracting international students to its courses, a move seen as critical to the development of business education in Greece given the country's comparatively limited number of corporate employers.
Other reasons for "internationalisation" include being able to assist Greek companies operating abroad, and as a tool for quality and culture improvement, for both students and faculty.
Greece's current predicament could even attract students from abroad, Prof Prastacos argues. "It's a unique opportunity to study a crisis, both during and within it ... It's in periods of crisis that conditions and foundations for future opportunities are created."
AUEB has built links with China and India at government level partly through leveraging the fact that each of these three countries possesses an ancient cultural heritage. China's Confucius Institute has made AUEB its third base in Europe for business and economics education, along with the London School of Economics and Political Science and the Copenhagen Business School. Following a conference in Athens on management through the lens of ancient eastern and western philosophy, a Confucius-AUEB research institute is being set up in Beijing.
The Indian government has funded a chair of international entrepreneurship at AUEB, one of 30 worldwide, which has recently been renewed for another three years.
Yet the school is not seeking to attract a flood of students from Asian countries, although Prof Prastacos would like to expand the MBA programme to about 150 students. "We are not aspiring to large numbers," he says.
Another tie-up, this time with the University of Kent in the UK, highlights what Greek business schools hope will become an increasingly important part of their offering: joint degree courses with European universities in areas relevant to Greece – shipping, tourism and heritage management.
Professor Evangelos Kyriakidis, a Greek archaeologist teaching at the University of Kent, has set up a degree course in heritage management based at Eleusis, an industrial town near Athens that is home to an important classical site. About 12 students are being selected from more than 60 applicants from Europe and the Middle East.
The 18-month course is designed as a cultural MBA with a practical side, he says. "Heritage isn't just money and tourism; it's about managing human resources, creating educational processes, narrative and content, and marketing the product."
The American College of Thessaloniki, a northern Greek city, is also taking a practical approach by intensifying the entrepreneurship segment of its MBA programme. The small programme has an intake of about 25, mainly from the region, including the southern Balkans.
Professor Nikolaos Kourkoumelis, programme director, says the priority is to develop skills that are immediately applicable in the marketplace.
"In this situation, with few jobs available for MBA graduates in northern Greece and the neighbouring countries just emerging from recession, the challenge for our students is to be able to set up and run their own small businesses," he says.
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text:
Inspections, Compliance, Enforcement, and Criminal Investigations
Ortho-Cycle Company Inc. 5/16/13
Department of Health and Human Services
|Public Health Service
Food and Drug Administration
Florida District
555 Winderley Place, Suite 200
Maitland, Florida 32751
Telephone: 407-475-4700
Fax: 407-475-4770
a. Your firm failed to perform any process validation related to the reprocessing of ceramic brackets, gold-plated brackets or expansion screws.
b. Your firm failed to validate the (b)(4) process used during the reprocessing of metal dental brackets.
c. Your firm failed to provide adequate documentation of validation for the (b)(4) Process used during the reprocessing of metal dental brackets. The documentation provided was inadequate as it did not include what percentage of (b)(4) was used, what specific (b)(4) or time was used, and it failed to document when multiple reprocessing sessions are used, or how many cycles the brackets can withstand.
d. Your firm failed to provide adequate documentation of validation for the (b)(4) Removing and Shining of Metal Attachments (b)(4) used during the reprocessing of metal dental brackets. Validation V-09 Rev. 5, dated 10/4/2011, provided by your firm was inadequate in that it failed to specify process time and (b)(4); amount of (b)(4) and (b)(4) used; number of samples inspected; worse case bracket included in the study; acceptance criteria regarding (b)(4); and no raw data was available to support testing performed.
a. Your firm's complaint handling procedures and work instructions (QMP-013, Rev. 6 and WI-006, Rev. 6) are inadequate in that they lack requirements for complaint investigations for complaints where no product is returned to the firm and it does not include a requirement for timely processing of complaints.
b. A review of your firm's complaint/return documentation for 2011, 2012, and 2013 indicates multiple complaints were received for malfunctions such as: gingival wings bent; lock doors not functioning well; spring damage on sliding doors; and loose doors. All reported malfunctions were not documented using the Consumer Complaint Report as required by your procedures and instructions. As for those complaints which were documented using report forms, the investigation documentation was not conclusive or complete. Specifically, Complaint#01-12, involving a consumer reporting "too many brackets with gingival brackets wings bent", was missing information to include, how the bent occurred, did the customer receive the product damaged, was the bent a malfunction of the device, and who determined an investigation of this issue was not needed as the firm did not conduct any investigational activities for this complaint to confirm the extent of the damage and/or malfunction of the device.
c. A review of your firm's complaint/return log for 2011, 2012, and 2013 also revealed 29 complaints that were described as "No explanation". Your firm did not have evidence of any attempt to gain additional information for each of these complaints or document if the complaint involved a device failure.
- Your procedures for quality audits fail to include all areas of the Quality System Regulation (QSR) that apply to your operations such as, process validation and complaint handling.
a. The procedure and instructions do not establish internal systems that provide for timely and effective identification, communication, and evaluation of events which may be subject to MDR requirements. For example, there are no definitions of what is considered a reportable event under 21 CFR 803. To facilitate the correct interpretation of reportable events and to assure the quality of MDR submissions, the procedure should include definitions, based on 21 CFR 803.3, of the terms: "become aware," "caused or contributed," "malfunction," and "MDR reportable event;" as well as, definitions of the terms "reasonably known" and "reasonably suggests," found respectively in 21 CFR 803.50(b)and 21 CFR 803.20(c)(1).
b. The procedure and instructions do not establish internal systems which provide a standardized review process to determine when an event meets the criteria for reporting per 21 CFR 803. For example:
The procedure states the reporting of a complaint involving death or serious injury to competent authorities where the incident occurred, FDA and Notified body no later than (b)(4) days from the initial receipt of the information. However, there are no instructions for conducting an investigation of each event and evaluating the cause of the event, as required by 21 CFR 803.50(b)(3).
The procedure does not specify who makes the decision for reporting events to FDA.
c. Your MDR procedure does not establish internal systems that provide for timely transmission of complete medical device reports. Specifically, the following are not addressed:
- Instructions for how to obtain and complete the FDA Form 3500A;
- Instructions for how you will submit all information reasonably known for each event;
- Circumstances under which you must submit initial, supplemental, or follow-up reports and the requirements for such reports; and,
- The address for where to submit MDR reports: FDA, CDRH, Medical Device Reporting, P.O. Box 3002, Rockville, MD 20847-3002.


text: 6/13/11 6/13/11 POPSUGAR Fashion Lanvin Resort 2012 Collection Lanvin Resort 2012 Collection Lanvin Resort 2012 (and the New Lanvin Children's Line) June 13, 2011 by POPSUGAR Fashion News 2 Shares Chat with us on Facebook Messenger. Learn what's trending across POPSUGAR. View On One Page Photo 27 of 49 ADVERTISEMENT () Start Slideshow Share This Link Copy What's Your Reaction? Thanks for your reaction Don't forget to share this with your friends! ← Use Arrows Keys → 27 0 previous images 18 more images Previous Next Start Slideshow Lanvin Resort 2012 CollectionIn The Looking Glass


text: Hi guys, I've been playing with timeseries for the last hour or so and it's pretty cool. Still lots of things I have to go through. In the one plotting example (using yahoo finance) I saw that one can fill missing dates before plotting so that the missing ones get masked. Though when applying some moving windows functions that caused all periods that were effected by the missing values to also become masked, which isn't the behaviour I was expecting. It does make sense to do it that way though. Obviously it's simple enough to use the original timeseries to calculate the moving window functions, or interpolate or something. The question I'm trying to get at though is if I'm going to store my timeseries in hdf5 will I fill in the missing dates before I do so, or only do that whenever I plot the timeseries? I'm working with stock prices, so the "missing" dates over the weekends will increase file size by more then 30%. Is there any other reason to fill in missing dates besides for plotting? Have a nice weekend, Christian


text:
Trek Cell Phone Games In DevelopmentBy Christian
April 24, 2001 - 11:15 PM
In the 23rd Century, Captain James T. Kirk was only able to contact the Enterprise with his Communicator. Thanks to Digital Bridges, 21st-Century cell phone owners will soon also be able to control the Enterprise and a whole set of other Starfleet vessels.
Activision, the company owning the Star Trek gaming license, and Digital Bridges, a wireless entertainment company, announced today they have started development on two games set in the Star Trek universe: 'First Duty' and 'Prime Directive.'
'First Duty' will give players an introduction to Starfleet, allowing them to learn about the principles and philosophy of the Federation and to command key stations on board major Starfleet vessels. Graduation students "are qualified for immediate action postings," the company promises, though exactly how much action the game will be able to deliver on the small, low-quality cell phone screens is unknown.
'Prime Directive' seems to be a far more ambitious undertaking, and is described as a massively multi-player game in which up to ten thousand people will be able to take part at the same time. In the game, Starfleet ships will be exploring the 'Caledonian Expanse,' a vast tract of uncharted space, which was recently linked to Federation space via a new wormhole. Skills learned in the 'First Duty' game will be put to use in 'Prime Directive.
"It's a fantastic honor to be able to develop games based in the world famous Star Trek universe [and] we are planning to do something really special," Digital Bridges' Chris Wright said. "Star Trek: Prime Directive is going to completely redefine how people think of games on the Wireless Internet. It all takes place in a persistent universe, so the game will continue whether you are on-line or not."
Though one might wonder how cell phones will even be technologically capable of delivering "something really special," Digital Bridges CEO Kevin Bradshaw said there were great possibilities. "People have been criticizing wireless gaming because of the technical limits of the handsets and data speeds," he admitted. "However, your cell phone offers possibilities which no other technology can match. Imaginesitting in a boardroom or classroom, when your phone bleeps and delivers a message telling you, your ship is under attack. You know that you're going to stand up and say 'Excuse me. I have to take this..."
'First Duty' is scheduled for release in the second quarter of this year, giving players three months to practice their starship command skills before 'Prime Directive' comes out in the third quarter. No information is yet available on pricing or distribution methods.
For more information, please check out the original press release.
Discuss this news item at Trek BBS!
Add TrekToday RSS feed to your news reader or My Yahoo!
Also a CSI: Crime Scene Investigation fan? Then visit CSIFiles.com!


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text:
ELYRIA — Three men were arrested and charged with murder Wednesday in connection with the shooting Sunday morning that left an Elyria man and father of two dead in his car.
Jeris Geiger, 21, of Grafton Street in Oberlin, and Andre A. Jackson, 19, of Middle Avenue in Elyria, were charged with murder Wednesday at a Maple Heights home. Jordan L. Williams, 25, of West River Road South in Elyria, was charged with murder for the same incident an hour later at a house in Cleveland. Williams was also charged with possession of drugs, drug abuse instruments and cocaine.
Police say the three are to blame for the death of Antonio Spraggins, 22, of Elyria.
Spraggins, who was seen playing pool at T&A Bar about 11 p.m. Saturday, was found shot to death in his car at the intersection of Foster and Lake avenues at 2:15 a.m. Sunday. Bullet holes were found in the driver's side of his car. Spraggins was declared dead at the scene.
An autopsy later determined Spraggins died from a gunshot wound to the torso.
Although police are not releasing a motive in the case, the four men knew each other, according to Elyria police Capt. Chris Costantino.
Spraggins, a 2010 graduate of Elyria High School, had a 5-year-old son and 3-year-old daughter.
Geiger and Jackson were being held at Lorain County Jail on a $1 million bond each. Williams was being held in Lorain County Jail on a $1.5 million bond.
All three have a hearing at 1 p.m. Monday in Elyria Municipal Court.
Contact Anna Merriman at 329-7245 or firstname.lastname@example.com. Follow her on Twitter at @AnnaLMerriman.