text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 1, 2005
|Filing date
|Sep 26, 2002
|Priority date
|Oct 2, 2001
|Fee status
|Also published as
|Publication number
|Eric J. Shero, Christophe Pomarede
|Original Assignee
|Asm America, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (70), Non-Patent Citations (26), Referenced by (51), Classifications (55), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The present application claims priority under 35 U.S.C. ß119(e) to U.S. provisional application No. 60/326,830, filed Oct. 2, 2001.
The present invention relates generally to thin dielectric films in integrated circuits, and more particularly to nitrogen incorporation into high k gate dielectric films.
Integrated circuit design is constantly being scaled down in pursuit of faster circuit operation and lower power consumption. Scaled dimensions in a circuit design generally requires attendant changes in fabrication processing.
A basic building block of integrated circuits is the thin film transistor (TFT). As is known in the art, the transistor typically includes a gate electrode separated from a semiconductor layer or substrate by a thin gate dielectric material. Although a common acronym for state-of-the-art transistors is MOS, for metal-oxide-silicon, the material of choice for the gate electrode has long been silicon rather than metal. Among other advantages, silicon gate electrodes are able to withstand high temperature processes and enable self-aligned doping processes used for completing the transistor, thus saving expensive masking steps.
Accordingly, conventional gate electrodes are formed of polysilicon doped with conductivity-enhancing impurities, such as arsenic, phosphorus or boron. Silicon can be deposited by CVD with in situ doping by flowing a dopant source gas (e.g., arsine, phosphine, diborane, etc.) concurrently with a silicon source gas (e.g. silane). Recently, interest has been drawn to the possibility of doping silicon electrodes with germanium, thereby reducing the electrical work function of the transistor gate electrode. Accordingly, a reduced voltage is needed to operate the circuit, consequently generating less heat. Moreover, a silicon germanium gate electrode remains compatible with surrounding materials and current integrated circuit fabrication processes. Proposals for forming silicon germanium layers include in situ doping of a silicon layer by forming germane (GeH4) along with silane (SiH4) in a chemical vapor deposition (CVD) process.
While in situ doped CVD processes have been found to be effective in producing silicon germanium, the addition of germane to the silane flow has been found to significantly increase incubation or nucleation times over dielectric materials, particularly oxides such as silicon dioxide and some of the high-k materials discussed below. Similarly slow nucleation over dielectric materials occurs when chemical vapor depositing other gate electrode materials, such as polysilicon and particularly silicon in situ doped by flowing dopant source gases (e.g., diborane, arsine or phosphine) along with a silicon source.
Slow nucleation entails longer overall deposition times, lower throughput and consequently greater fabrication costs. The semiconductor industry is very sensitive to fabrication costs. Accordingly, any increase in wafer throughput, at any stage of processing, translates to reduced production costs and higher margins.
One way in which SiGe or other in situ doped silicon deposition has been hastened is by the first formation of a nucleation layer, typically silicon, over the gate dielectric, followed by poly-SiGe deposition. This additional step unfortunately complicates the process flow, requires adjustment of the doping concentrations at the dielectric-electrode interface to ensure the desired work function for the transistor, and does not necessarily guarantee rapid and uniform nucleation. Other recent work optimizing silicon and poly-SiGe deposition processes has also focused on increasing deposition rates while maintaining layer uniformity. For example, U.S. Pat. Nos. 5,607,724; 5,614,257; 5,700,520; 5,874,121; and 5,876,797 describe methods of depositing polysilicon at high rates by CVD under "high pressure" conditions.
Another area in which process control is particularly critical is the fabrication of transistor gate dielectrics. In the pursuit of ever faster and more efficient circuits, semiconductor designs are continually scaled down with each product generation. Transistor switching time plays a large role in the pursuit of faster circuit operation. Switching time, in turn, can be reduced by reducing the channel length of the transistors. In order to realize maximum improvements in transistor performance, vertical dimensions should be scaled along with horizontal dimensions. Accordingly, effective gate dielectric thickness, junction depth, etc. will all decrease with future generation integrated circuits. To date, this scaling has reduced gate electrode widths to less than 0.25 μm. Currently, commercial products are available employing gate widths or critical dimensions of 0.18 μm or less.
Conventional gate dielectrics are formed of high quality silicon dioxide and are typically referred to as "gate oxide" layers. Ultrathin gate oxides (less than 7 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology.
While care under laboratory conditions can be used to control defect densities, such control has been difficult to achieve under commercial volume fabrication conditions. Moreover, even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide. At high fields, direct tunneling dominates over Fowler-Nordheim tunneling, and largely determines oxide scaling limits. These scaling limits have been estimated at about 2 nm for logic circuits, and about 3 nm for more leakage-sensitive memory arrays in dynamic random access memory (DRAM) circuits. See, e.g., Hu et al., "Thin Gate Oxides Promise High Reliability," SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 215-222.
Another problem with thin gate oxides is their susceptibility to dopant diffusion from the overlying gate electrode. A polysilicon gate electrode layer is typically doped with boron for its enhanced conductivity. As the gate oxide thickness is scaled down, boron can easily penetrate through the gate oxide, resulting in instabilities in device properties. Boron penetration into gate dielectrics has such undesirable consequences as positive shifts in threshold voltage, increases in sub-threshold swing, increases in charge trapping, decreases in low-field hole mobility, and degradation of current drive due to polysilicon depletion in p-MOSFETs.
Some efforts to address deficiencies of silicon dioxide include nitrogen incorporation into the gate dielectric. Silicon nitride (Si3N4) has a higher dielectric constant than SiO2, theoretically enabling thinner equivalent oxide thickness for gate dielectrics that are not tunnel-limited, and furthermore serves as an effective barrier against impurity diffusion. However, the interfaces between silicon nitride films and the underlying semiconductor substrate are generally of poor quality, resulting in a high density of charge trapping sites and pinholes, and attendant current leakage. As a consequence, attempts have been made to create SiO2 and Si3N4 hybrids, such as silicon oxynitride films, for use as gate dielectrics. Conventional methods of incorporating nitrogen into silicon oxide gate dielectrics are difficult to control, however, particularly for ultra-thin gate dielectrics of future generation devices
Other solutions to scaling problems include the use of high permittivity materials ("high k"). Theoretically, incorporating materials of high k materials into the gate dielectric opens the door to further device scaling. Due to higher dielectric constant, many materials can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness can be achieved without tunnel-limited behavior. Some high k materials under investigation include aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), barium strontium titanate (BST), strontium bismuth tantalate (SBT), tantalum oxide (Ta2O5), etc. Such dielectrics have a dielectric constant (or k) value greater than about 7. While exhibiting greatly increased dielectric strength, these materials have been difficult to integrate with existing fabrication technology.
Similar high quality, thin dielectric layers are desirable in other contexts of integrated circuit fabrication. Integrated capacitors in memory arrays must exhibit a certain minimum capacitance for proper data storage and retrieval. Some efforts to increase capacitance for a given memory cell space have focused on the use of materials characterized by high dielectric constants (high k materials), such as those listed above.
Accordingly, a need exists for improvements in the integration of dielectric layers and conductors in semiconductor fabrication, particularly at interfaces in transistor gate stacks.
In accordance with one aspect of the invention, a method is provided for forming a dielectric layer with a controlled variation in nitrogen concentration through its thickness. The method includes depositing the dielectric material onto a substrate at a substrate temperature less than about 500∞ C. A supply of nitrogen to the substrate is varied during deposition of the dielectric material.
In the illustrated embodiments, the nitrogen concentration forms two separate nitrogen peaks at the interfaces, with a low nitrogen concentration in the bulk portion therebetween. The supply of nitrogen is varied from a first level of nitrogen supply to a second intermediate level of nitrogen supply to a third level of nitrogen supply, wherein the second level is lower than each of the first level and the third level.
In one embodiment, the deposition method comprises providing a variable supply of nitrogen excited species through a remote plasma generator. In another embodiment, the deposition method comprises varying an amount of nitrogen supplied to an atomic layer deposition (ALD) process. For example, an arrangement is provided in which nitrogen and oxidant source gases are simultaneously supplied in an ALD process, with varying ratios in different cycles. Another arrangement is provided in which a separate nitrogen pulse is provided with varying frequency, depending upon the stage of deposition.
In accordance with another aspect of the invention, a dielectric layer is provided in an integrated circuit. The dielectric layer comprises a metal oxide throughout a thickness of the dielectric layer, which metal oxide has a dielectric constant greater than about 7. The dielectric layer includes a lower interface having a first nitrogen concentration, a bulk portion having a second nitrogen concentration lower than the first nitrogen concentration, and an upper interface having a third nitrogen concentration higher than the second nitrogen concentration.
The invention will be better understood from the detailed description of the preferred embodiments and from the appended drawings, which are meant to illustrate and not to limit the invention, and wherein:
While the preferred embodiments are described in the context of transistor gate stacks, the skilled artisan will readily appreciate that the principles disclosed herein have application to a variety of contexts in which thin high k materials require a graded composition, particularly those having special interface needs. An example of such a context is in the formation of capacitors including high k dielectrics, proposed for high density memory cells in random access memory (RAM) arrays. The methods described herein are particularly advantageous for maintaining the stability of and preventing diffusion to or from high k materials.
Conventional gate electrode deposition over high k gate dielectrics has been found to result in poor electrical performance of the resultant devices. In order to increase the reliability and yield of the integrated circuits including high k dielectrics, the present invention provides a varied composition for a high k dielectric, whereby nitrogen incorporation is highest near both upper and lower interfaces. Accordingly, two nitrogen peaks are produced through the thickness of the dielectric. Moreover, the processes provided herein provide excellent control by varying the nitrogen supply during low temperature dielectric formation, rather than in post-formation nitridation steps, and avoiding the diffusion problems inevitably faced during high temperature deposition.
Prior to describing the processes in greater detail, exemplary reactors for depositing layers by chemical vapor deposition (CVD) or atomic layer deposition (ALD) are first described below. Other reactor configurations may be used. For example, while not illustrated separately, the ALD processes described below can also be performed in a Pulsar™ 2000 ALCVD™ Reactor, commercially available from ASM Microchemistry Oy of Espoo, Finland.
CVD Reactor
In the illustrated reactor 10, a plurality of radiant heat sources are supported outside the chamber 12 to provide heat energy in the chamber 12 without appreciable absorption by the quartz chamber 12 walls. While the preferred embodiments are described in the context of a "cold wall" reactor for processing semiconductor wafers, it will be understood that the processing methods described herein will have utility in conjunction with other heating/cooling systems, such as those employing inductive or resistive heating.
The illustrated radiant heat sources comprise an upper heating assembly of elongated tube-type radiant heating elements 13. The upper heating elements 13 are preferably disposed in spaced-apart parallel relationship and also substantially parallel with the reactant gas flow path through the underlying reaction chamber 12. A lower heating assembly comprises similar elongated tube-type radiant heating elements 14 below the reaction chamber 12, preferably oriented transverse to the upper heating elements 13. Desirably, a portion of the radiant heat is diffusely reflected into the chamber 12 by rough specular reflector plates (not shown) above and below the upper and lower lamps 13, 14, respectively. Additionally, a plurality of spot lamps 15 supply concentrated heat to the underside of the substrate support structure (described below), to counteract a heat sink effect created by cold support structures extending through the bottom of the reaction chamber 12.
Each of the elongated tube type heating elements 13, 14 is preferably a high intensity tungsten filament lamp having a transparent quartz envelope containing a halogen gas, such as iodine. Such lamps produce full-spectrum radiant heat energy transmitted through the walls of the reaction chamber 12 without appreciable absorption. As is known in the art of semiconductor processing equipment, the power of the various lamps 13, 14, 15 can be controlled independently or in grouped zones in response to temperature sensors.
A substrate, preferably comprising a silicon wafer 16, is shown supported within the reaction chamber 12 upon a substrate support structure 18. Note that, while the substrate of the illustrated embodiment is a single-crystal silicon wafer, it will be understood that the term "substrate" broadly refers to any surface on which a layer is to be deposited. Moreover, the principles and advantages described herein apply equally well to depositing layers over numerous other types of substrates, including, without limitation, glass substrates such as those employed in flat panel displays.
The illustrated support structure 18 includes a substrate holder or susceptor 20, upon which the wafer 16 rests, and a support spider 22. The spider 22 is mounted to a rotating shaft 24, which extends downwardly through a tube 26 depending from the chamber lower wall. Preferably, the tube 26 communicates with a source of purge or sweep gas which can flow during processing, inhibiting process gases from escaping to the lower section of the chamber 12.
A plurality of temperature sensors are positioned in proximity to the wafer 16. The temperature sensors may take any of a variety of forms, such as optical pyrometers or thermocouples. The number and positions of the temperature sensors are selected to promote temperature uniformity, as will be understood in light of the description below of the preferred temperature controller. Preferably, however, the temperature sensors directly or indirectly sense the temperature of positions in proximity to the wafer.
In the illustrated embodiment, the temperature sensors comprise thermocouples, including a first or central thermocouple 28, suspended below the wafer holder 20 in any suitable fashion. The illustrated central thermocouple 28 passes through the spider 22 in proximity to the wafer holder 20. The reactor 10 further includes a plurality of secondary or peripheral thermocouples, also in proximity to the wafer 16, including a leading edge or front thermocouple 29, a trailing edge or rear thermocouple 30, and a side thermocouple (not shown). Each of the peripheral thermocouples are housed within a slip ring 32, which surrounds the substrate holder 20 and the wafer 16. Each of the central and peripheral thermocouples are connected to a temperature controller, which sets the power of the various heating elements 13, 14, 15 in response to the readings of the thermocouples. The slip ring 32 can be suspended by any suitable means. For example, the illustrated slip ring 32 rests upon elbows 34 that depend from a front chamber divider 36 and a rear chamber divider 38. The dividers 36, 38 desirably are formed of quartz. In some arrangements, the rear divider 38 can be omitted.
The illustrated reaction chamber 12 includes an inlet port 40 for the injection of reactant and carrier gases, and the wafer 16 can also be received therethrough. An outlet port 42 is on the opposite side of the chamber 12, with the wafer support structure 18 positioned between the inlet 40 and the outlet 42. An inlet component 50 is fitted to the reaction chamber 12, adapted to surround the inlet port 40, and includes a horizontally elongated slot 52 through which the wafer 16 can be inserted. A generally vertical inlet 54 receives gases from remote sources, as will be described more fully below, and communicates such gases with the slot 52 and the inlet port 40. The inlet 54 can be modified from the original EpsilonÆ design for CVD and instead be configured to keep the gas flow from different ALD precursor sources separate until entry into the chamber 12, in order to avoid CVD-like reactions. An outlet component 56 also mounts to the process chamber 12 such that an exhaust opening 58 aligns with the outlet port 42 and leads to exhaust conduits 59. The conduits 59, in turn, can communicate with suitable vacuum means (not shown) for drawing process gases through the chamber 12. A pump or fan is preferably included to aid in drawing process gases through the chamber 12, and to evacuate the chamber for low pressure processing.
The illustrated reactor 10 also includes a source 60 of excited species, preferably positioned upstream from the chamber 10. The excited species source 60 of the illustrated embodiment comprises a remote plasma generator, including a magnetron power generator and an applicator along a gas line 62. An exemplary remote plasma generator is available commercially under the trade name TRW-850 from Rapid Reactive Radicals Technology (R3T) GmbH of Munich, Germany. In the illustrated embodiment, microwave energy from a magnetron is coupled to a flowing gas in an applicator along a gas line 62. A source of precursor gases 63 is coupled to the gas line 62 for introduction into the excited species generator 60. A source of carrier gas 64 is also coupled to the gas line 62. One or more further branch lines 65 can also be provided for additional reactants. As is known in the art, the gas sources 63, 64 can comprise gas tanks, bubblers, etc., depending upon the form and volatility of the reactant species. Each gas line can be provided with a separate mass flow controller (MFC) and valves, as shown, to allow selection of relative amounts of carrier and reactant species introduced to the excited species generator 60 and thence into the reaction chamber 12. It will be understood that, in other arrangements, the excited species can be generated within or immediately adjacent the process chamber (see
Wafers are preferably passed from a handling chamber (not shown), which is isolated from the surrounding environment, through the slot 52 by a pick-up device. The handling chamber and the processing chamber 12 are preferably separated by a gate valve (not shown) of the type disclosed in U.S. Pat. No. 4,828,224, the disclosure of which is hereby incorporated herein by reference.
The total volume capacity of a single-wafer process chamber 12 designed for processing 200 mm wafers, for example, is preferably less than about 30 liters, more preferably less than about 20 liters, and most preferably less than about 10. The illustrated chamber 12 has a capacity of about 7.5 liters. Because the illustrated chamber 12 is divided by the dividers 36, 38, wafer holder 20, ring 32, and the purge gas flowing from the tube 26, however, the effective volume through which process gases flow is around half the total volume (about 3.77 liters in the illustrated embodiment). Of course, it will be understood that the volume of the single-wafer process chamber 12 can be different, depending upon the size of the wafers for which the chamber 12 is designed to accommodate. For example, a single-wafer processing chamber 12 of the illustrated type, but for 300 mm wafers, preferably has a capacity of less than about 100 liters, more preferably less than about 60 liters, and most preferably less than about 30 liters. One 300 mm wafer processing chamber has a total volume of about 24 liters, with an effective processing gas capacity of about 11.83 liters.
As mentioned, a plurality of vapor-phase precursor sources (not shown) are connected to the inlet 54 via gas lines with attendant safety and control valves, as well as mass flow controllers ("MFCs"), which are coordinated at a gas panel. The gas sources can include, for example, a source of carrier gas (e.g., H2 or N2); metal precursors (e.g., ZrCl4, HfCl4, WF6, TiCl4, CuCl, etc.); an oxidant source gas (e.g., O2, O3, O radicals, H2O, NO, N2O, etc.); a nitrogen source gas (e.g., NH3, N2, NO, N2O, hydrazine, etc.); a silicon source (e.g., SiH4, Si2H6, Si3H8, Si4H10, DCS, TCS; a source of germanium (e.g., GeH4); dopant sources (e.g., phosphine, arsine and diborane); and etchants for cleaning the reactor walls and other internal components (e.g., HCl or NF3/Cl2. The vapor-phase sources can include liquid reactant sources in a bubbler, and a gas line for bubbling and carrying vapor phase reactants from the bubbler to the reaction chamber 12.
Process gases are communicated to the inlet 54 in accordance with directions programmed into a central controller (including a memory and a microprocessor) and distributed into the process chamber 12 through injectors. After passing through the process chamber 12, unreacted process gases and gaseous reaction by-products are exhausted to a scrubber to condense environmentally dangerous fumes before exhausting to the atmosphere.
ALD Reactors with Remote Plasma Chambers
In the illustrated embodiment, two precursors are supplied to the reaction chamber 132. The first precursor is supplied to the reaction chamber 132 through a first precursor conduit 140. In a similar manner, the second precursor is supplied to the reaction chamber 132 through a second precursor supply conduit 142. Each supply conduit is connected to a precursor supply source (not shown) and preferably a purge gas source (not shown). The purge gas is an inert gas and can be, by way of example, nitrogen or argon. The purge gas can also be used as a carrier gas to transport the first and/or second precursors. The reactor 130 also includes an exhaust 144 for removing material from the reactor chamber 132.
A showerhead plate 146 is positioned within the reaction chamber 132. Preferably, the showerhead plate 146 is a single integral element. The showerhead plate 146 preferably spans across the entire reaction zone and divides the reaction chamber 132 into an upper chamber 148, defining a plasma cavity 149, and a lower chamber 150. The showerhead plate 146 defines, at least in part, a plurality of passages 152 that connect the upper chamber 148 to the lower chamber 150. In the illustrated embodiment, such passages 152 are formed by providing small holes in the showerhead plate 146 that are located generally above the substrate 136. In this manner, the showerhead plate 146 substantially prevents the second precursor from entering the lower chamber 150 until the flow from the second conduit 142 is generally above the substrate 136.
As noted, the upper chamber 148 of the illustrated reaction chamber 132 defines the separate plasma cavity 149 for creating in-situ radicals. Such in-situ radicals can be used to facilitate reactions on the surface of the substrate. To create the in-situ radicals, a plasma can be created within the plasma cavity 149 in a variety of ways, such as, for example, using a capacitor electrode positioned inside or outside the plasma cavity (i.e., a capacitively coupled plasma), a RF coil (i.e., a inductively coupled plasma), light, ionizing radiation, heat (e.g., heated tungsten filament can be used to form hydrogen radicals from hydrogen molecules), and/or chemical reactions to generate the plasma.
In embodiment of
The reactor 160 also includes an upper chamber 175 defining the plasma cavity 162, which, in the illustrated embodiment, is located generally above the reaction space 164. The upper chamber 175 defines the plasma cavity 162 in which the in-situ radicals are generated. To generate the radicals, a second precursor is introduced into the plasma cavity 162 via a second supply conduit 176. Radicals and other excited species are generated from the plasma that is generated in the upper chamber 175. To generate the plasma, the illustrated embodiment utilizes a planar RF TCP coil and RF shield 177, which are separated from the plasma cavity 162 by a window 178 made of, for example, quartz. An example of such a planar induction coil is described in the Journal of Applied Physics, Volume 88, Number 7, 3889 (2000) and the Journal of Vacuum Science Technology, A 19(3), 718 (2001), which are hereby incorporated by reference herein.
The plasma cavity 162 and the reaction space 164 are separated by a radical or showerhead plate 180. The showerhead plate 180 preferably defines a plurality passages 182 through which radicals formed in the plasma cavity can flow into the reaction space 164. Preferably, the flow through the passages 182 is generally directed towards the reaction surface of the substrate 166. In some embodiments, the space between the showerhead plate 180 and the substrate 166 can be as small as a few millimeters. Such an arrangement provides ample radical concentration at the wafer surface, even for short-lived radicals.
In some embodiments, purge gases can be continuously supplied to the plasma cavity 162 through a purge inlet 184. In such an embodiment, the upper chamber 175 can operate at a substantially constant pressure regime. In other embodiments, the showerhead plate 180 and surrounding components adjacent to the reaction chamber 163 may be heated, either as a result of the plasma on one side on the showerhead plate 180 and/or a heated wafer holder 170 on the other side, or by separately heating the showerhead plate 180.
In some embodiments, the RF power can be used to alternately switch the radical concentration in the flow. In other embodiments, the supply of precursors to the plasma cavity can be alternately switched. Preferably, there is a continuous flow from the plasma cavity 162 to the reaction space 164. Continuous flow of gases, i.e., radicals alternated with inert gas, is preferred because it prevents the first precursor in the reaction space 164 below from contaminating the plasma cavity 162. This facilitates the deposition of conductive compounds without arcing. There is also preferably a positive pressure differential between the plasma cavity 162 and the reaction space 164 with the pressure in the plasma cavity 162 being larger. Such an arrangement also promotes plasma ignition in the upper chamber 175.
General Process Flow
Referring to
Referring now to
Prior to the illustrated process, the substrate is first cleaned to remove contaminants and naturally occurring or native oxide on the semiconductor structure. Conventionally, wafer cleaning prior to gate oxide growth is conducted ex situ prior to loading the wafer into the process chamber. For example, wafers may be cleaned in an SCl/HF wet etch bath. Alternatively, an integrated HF and acetic acid vapor clean can be conducted in a neighboring module within a cluster tool, reducing transport time and opportunity for recontamination or reoxidation. For some applications, the cleaning oxide left by the SCl step is not removed, but is instead used as the initial oxide layer. In another possibility, a hydrogen bake step can be conducted within the chamber to sublimate native oxide. Small amounts of HCl vapor can be added to this step to aid in cleaning metal contaminants and the like during the hydrogen bake. In still another arrangement, plasma products can assist or conduct in situ cleaning, such as by substituting H radicals for hydrogen gas.
Either after ex situ cleaning, or prior to in situ cleaning, the wafer or other substrate is loaded into the process chamber. Cleaning of native oxide tends to leave a hydrogen-terminated surface, which advantageously inhibits spontaneous reoxidation upon exposure to the clean room environment or other source of oxidants. Such hydrogen termination may need to be desorbed prior to further processes.
With reference now to
Referring now to
The gate electrodes 115, 120 preferably contains silicon and is CVD deposited. For example, the gate electrode can comprise a CVD polysilicon, doped or undoped, or a silicon germanium alloy, preferably having the form Si1-xGex. Gate electrode formation typically comprises two stages, as illustrated in FIGS. 6-7: a seed phase and a bulk phase. The silicon seed or wetting layer 115 serves to improve nucleation relative to direct deposition of SiGe. If included, conditions are arranged in the seed phase to minimize chemical reduction of the underlying high k. The illustrated high k material comprises HfO2 or ZrO2, which has been found particularly susceptible to reduction during conventional polysilicon or poly-SiGe deposition. A low reduction seed layer deposition is described in U.S. provisional patent application No. 60/279,256, filed Mar. 27, 2001, entitled INTEGRATION OF HIGH K GATE DIELECTRIC, the disclosure of which is incorporated herein by reference. Conditions can then be arranged in the bulk phase to increase the deposition rate, relative to that of the previous step.
However, as noted below, the preferred high k dielectric 110 includes a relatively high nitrogen content at the upper interface. Accordingly, reduction of the high k dielectric may be sufficiently attenuated to avoid special low-reduction seed processing. Further, high nitrogen content at the upper interface can also improve subsequent nucleation of the gate electrode (e.g., Si, SiGe and particularly in situ doped Si and SiGe). Accordingly, the seed phase can be omitted.
Having completed the gate stack, further processing to complete the integrated circuit follows. For example, gate stacks typically are insulated by blanket deposition of a dielectric and spacer etch. Transistor active areas are then doped to form source and drain regions on either side of the patterned electrodes, and wiring or "back end" processes complete the circuit.
A gate dielectric 260, formed by the exemplary processes described below, separates the gate electrode 220 from the substrate 200. As noted in the Background section above, the gate dielectric 260 is a critical feature in the pursuit of denser and faster circuits.
Note that integrated circuit transistors can have a variety of forms that do not all resemble that of FIG. 8. The graded dielectric layer of the preferred embodiments, however, will have application to gate dielectric layers in a variety of transistor types (e.g., heterojunction BiCMOS transistors), as well as to a variety of other ultrathin dielectric layers having other functions within an integrated circuit (e.g., capacitor dielectric, tunneling dielectric, etc.).
Preferred High K Dielectric
As noted in the Background section, high k materials are generally forms of metallic oxide with k values greater than about 7, including aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium bismuth tantalate (SBT), and lanthanide oxides. The last listed dielectrics include oxides of such physically stable "rare earth" elements as scandium (Sc), yttrium (Y), lanthanum (La), cerium Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu). The high k material of the preferred embodiments can comprise any of the above-mentioned materials. Most preferably, high k materials incorporated into the dielectric layer of the illustrated embodiments comprise oxides of Group 4 metals, particularly zirconium oxide (ZrO2) hafnium oxide (HfO2), and have a dielectric constant greater than about 10.
The preferred high k dielectric layer incorporates high k material throughout the thickness of the layer, and furthermore incorporate a controlled amount and distribution of an impurity, particularly nitrogen. Preferably, this impurity is incorporated to a greater extent at upper and lower interfaces of the dielectric material, and is incorporated during the deposition process. Thus, two separate nitrogen peaks are provided through the thickness of the dielectric.
Preferably, the dielectric upper interface includes between about 1% and 10% atomic ratio of nitrogen and is preferably between about 5 Å and 20 Å in thickness, more preferably between about 5 Å and 10 Å. Typically, a higher nitrogen content in the metal oxide results in a higher amorphous content. Advantageously, this top interface serves to protect the bulk of the high k material from diffusion of impurities (e.g., electrical dopants such as boron) from the overlying gate electrode and to inhibit silicidation reactions between the overlying gate electrode and the high k material, thereby maintaining thermal stability of the high k material, particularly during subsequent source/drain reoxidation. Moreover, nitrogen content at the upper interface desirably facilitates nucleation during deposition of the overlying gate electrode, particularly SiGe, while resisting diffusion of reducing agents (e.g., hydrogen) during such deposition. Reducing agents can disadvantageously convert the high k dielectric to metallic conductors and cause electrical leakage paths through the dielectric.
The bulk of the dielectric preferably includes less than about 0.1% (atomic ratio) nitrogen, more preferably less than about 0.01% nitrogen, and for the illustrated gate dielectric function is between about 20 Å and 30 Å in thickness. Advantageously, low nitrogen content in the bulk of the illustrated high k material improves overall film quality. Substantially pure metal oxide (e.g., ZrO2 or HfO2) in the bulk avoids undercoordinated dangling bonds, which can otherwise form charge trap sites.
The lower interface preferably includes greater than about 0.1% (atomic ratio) nitrogen, more preferably between about 0.1% and 1% nitrogen. Preferably the lower interface with this content has a thickness between about 5 Å and 10 Å, more preferably closer to about 5 Å. The nitrogen content at this lower interface advantageously improves interface reliability at the substrate and inhibits oxidation of the substrate during high k deposition and subsequent processing. Such oxidation can disadvantageously lower the effective permittivity (k value) of the gate dielectric. The nitrogen level is lower than that of the upper interface, however, to reduce the advent of interface trap sites that might be induced by nitrogen at the substrate interface. Preferably, the nitrogen content in the upper interface is more than about 5 times the nitrogen content in the lower interface, more preferably about one order of magnitude greater.
The above description is particularly suited to transistor gate dielectric applications, in which the nitrogen-containing high k layers preferably have a thickness between about 20 Å and 60 Å. The described high k dielectric will also have other applications in integrated circuits. For example, for a dynamic random access memory (DRAM) application, a thicker high k layer can be employed, such as 150 Å to 200 Å in thickness, having ultrathin nitrogen-containing interfaces. Advantageously, an upper nitrogen-containing interface, as described above, can stabilize the high k material during subsequent processing. Depending upon the lower electrode materials, a lower nitrogen-containing interface can be omitted for a DRAM capacitor dielectric.
Preferred Processes for Forming High K Layer with N-containing Interfaces
The high k material, as described above, can be deposited by any suitable process, including PVD, CVD, MOCVD, ALD, etc. In the preferred embodiments, nitrogen incorporation is desirably achieved in a controlled fashion during deposition.
Conventionally, silicon oxide gate dielectric films are made by thermal oxidation of the underlying silicon substrate. To incorporate nitrogen, nitrogen-containing gases can be added to the main oxygen stream, and/or a post-deposition treatment can be performed with nitrogen-containing gases or nitrogen implantation. Such methods can either incorporate nitrogen into the oxide material to form silicon oxynitride (SiOxNy) or form a Si3N4 layer over the oxide. In other arrangements, oxide, whether deposited or thermally grown, are later treated for nitrogen incorporation by diffusion. In still other arrangements, nitrogen incorporation is varied during conventional thermal CVD, performed at relatively high temperatures, and interdiffusion inevitably takes place. In any of the prior art methods known to the inventors, it is difficult to control the nitrogen content in the film, especially for current and future generation of integrated circuit devices where the gate dielectric material is very thin (e.g., less than 7 nm). For such ultrathin dielectrics, conventional methods of incorporating nitrogen into a gate dielectric cannot be effectively controlled to provide two separate nitrogen peaks for both interfaces without also producing high nitrogen levels in the bulk of the dielectric.
Two embodiments are described hereinbelow: CVD with variable nitrogen incorporation through remotely generated nitrogen radicals, and ALD with variable nitrogen incorporation through varying the constituents of the plural cycles. ALD can optionally also employ nitrogen radicals in the controlled fashion described with respect to the CVD embodiment. Advantageously, both embodiments benefit from low temperature deposition, which helps to maintain the desired nitrogen profile. Preferably, deposition temperatures are below about 500∞ C. and more preferably below about 400∞ C.
CVD deposition of high k material with nitrogen-containing interfaces
In accordance with one aspect of the invention, a high k material is deposited with varying nitrogen content throughout the deposition process during chemical vapor deposition (CVD). Nitrogen is supplied by way of a remote plasma source 60, such as that described with respect to FIG. 1. The amount of nitrogen incorporated into the layer, as it is deposited, is varied at least in part by varying the supply of nitrogen radicals generated by the remote source.
It will be understood that this concept will have application to any of a number of deposition techniques. Preferably, high k metal oxide is deposited by a form of CVD employing metal-organic precursors (MOCVD). Advantageously, organic metal source gases tend to decompose at relatively low temperatures. For the preferred materials, a vapor phase, organic source of hafnium or zirconium is simultaneously provided with a vapor phase source of oxygen. Nitrogen is provided in the form of nitrogen radicals from a remote plasma source, advantageously also enabling low temperature reactions.
Preferably, the ratio of nitrogen radicals or excited species to oxygen is varied during the process to be higher at initial stages (representing the lower interface), low to zero during intermediate stages (representing the dielectric bulk) and higher again at the terminal stages (representing the upper interface). The nitrogen content in the deposited high k material is thereby varied in a controlled fashion, allowing for two separate nitrogen peaks (see, e.g., FIG. 9).
The relative amount of nitrogen can be varied in a variety of manners. In a first arrangement, the flow of nitrogen source gas (e.g., ammonia, diatomic nitrogen or hydrazine) through the remote plasma generator is varied, such that it is highest during terminal stages of the deposition, at an intermediate level during initial stages of the deposition, and lowest (e.g., zero) during intermediate stages of the deposition.
In a second arrangement, the flow of carrier gas through the remote plasma generator is varied. The skilled artisan will appreciate that such variation will have a non-linear effect upon the amount of nitrogen radicals generated. High carrier flow can support denser plasma generation and thus greater nitrogen radical concentration up to a point, but dilution due to greater overall gas flow during the CVD process can reduce nitrogen incorporation into the deposited film.
In a third arrangement, both oxygen source and nitrogen source gases are provided through the remote plasma generator. By ramping the power applied to the remote plasma generator, the relative rates of dissociation can be changed, thereby changing the relative generation of N radicals as compared to O radicals. For example, using N2 as the nitrogen source and O2 as the oxygen source, increasing power will increase dissociation of both sources up to a point. As power is increased further, the rate of O2 dissociation will level off while the rate of N2 dissociation continues to increase with increasing power. Alternatively, if the oxygen source is supplied separately and only nitrogen source and carrier gas are supplied to the remote plasma generator, altering power applied to the remote plasma generator will vary the amount of nitrogen excited species supplied to the CVD process in a straight forward manner. In one example, microwave power applied to a remote plasma processor can be varied between about 800 W and 2 kW.
ALD deposition of high k material with nitrogen-containing interfaces
In accordance with another preferred embodiment, the high k material is deposited by an atomic layer deposition (ALD) process. ALD is a chemically self-limiting process, whereby alternated pulses of reaction precursors saturate a substrate and leave no more than one monolayer of material per pulse. The precursors are selected to ensure self-saturating reactions, because at least one pulse per cycle leaves a chemisorbed species with a surface termination that is non-reactive with the gas phase reactants of the same pulse. Such a termination is left by "tails" or ligands of the source chemical, such as organic tails or halide tails. A subsequent pulse of different reactants do react with the tails left on the chemisorbed layer of a previous pulse to enable continued deposition. Thus, each cycle of alternated pulses leaves no more than about one molecular layer of the desired material. The principles of ALD type processes have been presented by T. Suntola, e.g. in the Handbook of Crystal Growth 3, Thin Films and Epitaxy, Part B: Growth Mechanisms and Dynamics, Chapter 14, Atomic Layer Epitaxy, pp. 601-663, Elsevier Science B.V. 1994, the disclosures of which are incorporated herein by reference. In one arrangement, the deposition is conducted in a Pulsar™2000 reactor (commercially available from ASM Microchemistry of Espoo, Finland), which is designed for ALD processes. In another arrangement, the ALD tools of
ALD facilitates the formation of thin films monolayer by monolayer. Indeed, control exists on a smaller than monolayer scale, due to steric hindrance of bulky source chemical molecules producing less than one monolayer per cycle. The capability of layering atomically thin monolayers enables forming more precise concentration gradients from the lower surface (e.g., gate dielectric/Si substrate interface) to the upper surface (e.g., gate electrode/gate dielectric interface).
Accordingly, each discrete monolayer (or partial monolayer) can be tailored by selectively introducing the desired chemistry for each monolayer to be deposited. For example, by means of ALD, a particular combination of introduced gases react with, deposit or adsorb upon the workpiece until, by the nature of the deposition chemistry itself, the process self-terminates. Regardless of the length of exposure, the process gases do not contribute further to the deposition. To deposit subsequent monolayers, different chemical combinations are introduced in the process chamber such as will react with or adsorb upon the previously formed monolayer. Desirably, the second chemistry or a subsequent chemistry forms another monolayer, also in a self-limiting manner. These self-limiting monolayers are alternated as many times as desired to form a film of suitable thickness.
The very nature of this method allows a change of chemistry for each discrete cycle. Accordingly, the composition of the resulting thin film can be changed incrementally, for example, in each cycle, in every second cycle, or in any other desired progression. Additionally, because ALD can be conducted at very low temperatures, relative to conventional thermal oxidation and conventional CVD processes, diffusion during the process can be effectively limited. For the purpose of illustrating a ratio between oxide thickness and corresponding number of layers, a thin film of 60 Å zirconium oxide, for example, is formed by an ALD process alternating ZrCl4 and H2O described below in about 100 cycles. Plenty of opportunity exists for tailoring the composition produced by each individual cycle, and the results of such compositional tailoring tend not to diffuse from their deposited positions due to the low temperature of the process. Thus, even for such an extremely thin layer, the composition can be changed such that a different impurity concentration can be incorporated into the first monolayer as compared to that incorporated into the last monolayer.
ALD of silicon oxide dielectric layers, with a graded nitrogen content, is disclosed in U.S. patent application Ser. No. 09/800,757, filed Mar. 6, 2001, entitled GRADED THIN FILMS, the disclosure of which is incorporated herein by reference.
The preferred embodiment modifies ALD deposition of a high k metal oxide by selectively incorporating nitrogen during selected stages of the deposition. A metal source gas, suitable for chemisorption of a self-limited partial or full monolayer per pulse, is alternated with an oxidant pulse. Exemplary oxidant source gases include oxygen, water, hydrogen peroxide, ozone, alcohols (e.g., methanol, ethanol, isopropanol), etc. In some arrangements (not specifically described herein), the process can include additional pulses, such as additional metal source pulses for more complex metal oxides, and gettering pulses for stripping ligands between pulses. A basic ALD process for deposition of ZrCl4 is first described prior to describing two modifications employed for incorporating nitrogen, described below with respect to
In an exemplary ALD process for depositing ZrO2, the reaction space is evacuated to vacuum with a mechanical vacuum pump. After evacuation the pressure of the reaction space was adjusted to about 5-10 mbar (absolute) with flowing nitrogen gas that had a purity of 99.9999%. Then the reaction space is stabilized at 300∞ C. A ZrCl4 source is kept between about 180∞ C. and 210∞ C., more preferably about 200.
Each cycle of the ALD process comprises a plurality of pulses. ZrCl4 vapor is introduced to the reaction chamber and exposed the wafer surface for 0.1 s. This is referred to as pulse A or the "metal pulse." The reaction chamber is purged with nitrogen gas for 1.0 s to remove surplus ZrCl4 and byproducts from the reaction chamber. This is referred to as purge A. Then water vapor is introduced to the reaction chamber and exposed to the wafer surface for 0.3 s. This is referred to as pulse B or the "oxidant pulse." Residual H2O and reaction byproducts were removed by purging the reaction chamber for 3.0 s. This is referred to as purge B. During each of the reaction phases, the reactants are supplied in sufficient quantity for the given other parameters to saturate the surface.
This exemplary high-k deposition cycle is summarized in Table I.
pulse A
purge A
pulse B
purge B
The average deposition rate using the foregoing chemicals is about 0.59 Å/cycle at 300∞ C., such that the ZrO2 thickness was about 30 Å. Similar process conditions using HrCl4 in place of ZrCl4 will produce HfO2.
More generally, temperatures during the process preferably fall between about 250∞ C. and 500∞ C., more preferably between about 300∞ C. and 350∞ C., depending upon the acceptable levels of chlorine in the film. For an amorphous ZrO2 or HfO2 layer, the temperature is more preferably at the low end of this range, between about 200∞ C. and 250∞ C., and most preferably at about 225∞ C. For a crystalline film, the temperature is more preferably at the high end of this range, between about 250∞ C. and 500∞ C., and most preferably between about 300∞ C. and 350∞ C. As will be appreciated by the skilled artisan, however, mixtures of amorphous and crystalline composition result at the boundary of these two regimes. The illustrated process utilizes temperatures between about 300∞ C. and 350∞ C., producing a largely crystalline ZrO2 or HfO2 film. More generally, the metal pulse A preferably is conducted for between about 0.05 s and 1.0 s, purge A for between about 0.5 s and 10.0 s, oxidation pulse B for between about 0.05 s and 0.5 s and purge B for between about 0.5 s and 10.0 s.
The skilled artisan will appreciate that the pulse times in particular and all parameters in general can be varied within relatively large windows within which ALD reactions can occur. One of the stricter limitations for accomplishing truly self-limited reactions in ALD is that the temperature is preferably kept above the temperatures at which the source chemicals condense, but below the temperatures at which the source chemicals thermally decompose. Unlike CVD, however, deposition rates remain constant anywhere within this relatively large temperature window, such that strict temperature uniformity across a substrate is not required in order to accomplish conformal deposition.
In the example of Table I, the metal monolayer formed in the metal phase is self-terminated with chloride, which does not readily react with excess ZrCl4 under the preferred conditions. The preferred oxygen source gas, however, reacts with or adsorbs upon the chloride-terminated surface during the oxygen phase in a ligand-exchange reaction limited by the supply of zirconium chloride complexes previously adsorbed. Moreover, oxidation leaves a hydroxyl and oxygen bridge termination that does not further react with excess oxidant in the saturative phase.
Preferably, sufficient cycles are conducted to grow between about 20 Å and 60 Å of ZrO2. More preferably, sufficient cycles are conducted to grow between about 20 Å and 40 Å. The dielectric constant of pure zirconium oxide can range between about 18 and 24.
In accordance with the preferred embodiments, an impurity source gas is also provided to at least one of the cycles in the alternating process, selected to improve the functional qualities of the dielectric. The impurity preferably comprises nitrogen, and the impurity source gas preferably comprises ammonia (NH3) or hydrazine (N2H4) added to the alternating process. Both ammonia and hydrazine are fairly reactive gases, making them suitable for low temperature ALD processing.
In a first arrangement (FIG. 10), nitrogen is incorporated during the oxidant pulses of selected cycles. In a second arrangement (FIG. 11), nitrogen is incorporated during selected cycles in its own separate pulses. In either arrangement, different amounts of nitrogen can be incorporated at different points in the deposition process, allowing for a high degree of control over nitrogen content even through the thickness of extremely thin layers, while low deposition temperatures minimize interdiffusion and ensure maintenance of the desired nitrogen profile.
With reference to
In the illustrated embodiment, a highly reactive nitrogen source gas, such as ammonia or hydrazine, is added to the oxygen phase. Different amounts of NH3 are added to different oxidant source gas pulses throughout the process. Thus, a desired amount of nitrogen can be selectively incorporated into each monolayer of metal oxide and a metal oxynitride layer results with a tailored nitrogen content profile.
The skilled artisan will appreciate, in view of the present disclosure, that the reaction between ammonia and the adsorbed metal complex will have a different thermodynamic favorability, as compared to the reaction between the oxidant and the metal complex. Accordingly, the proportions of ammonia to oxidant do not necessarily equal the proportions of nitrogen to oxygen in the resultant metal oxynitride. The skilled artisan can readily account for thermodynamic competition through routine experimentation to determine the appropriate parameters for the desired levels of nitrogen incorporation. Providing nitrogen active species through a remote plasma generator, particularly in conjunction with oxygen active species, can maximize the effect of varying the ratio of oxygen to nitrogen sources in a thermodynamically competitive single-pulse reaction.
As shown, at some point after the first cycle 301 a (forming a partial monolayer of metal oxide), a first impurity source gas pulse 306 b is provided, preferably during an oxidant source gas pulse 304 b. Desirably, a relatively low percentage of the impurity source gas (preferably comprising NH3) is provided during this first pulse 306 b. During subsequent oxidant source gas pulses 304 c, 304 d, etc., progressively greater flows of the impurity source gas are provided in pulses 306 c, 306 d, etc. Where progressively greater flows of the impurity source gas are employed, it can be advantageous to supply reactants perpendicularly to the substrate surface, such as by way of an overhead showerhead. In the case of competing adsorption of two source chemicals, all of the substrate surface is preferably exposed simultaneously to the gas mixture. The showerhead structures of
Note that
As illustrated by dotted lines, the oxidant source gas pulses 304 a, 304 b, etc. can also be reduced in the course of increasing the impurity source gas flow, depending upon the materials and the desired. Accordingly, nitrogen content in the resultant metal oxynitride dielectric layer can be increased from 0 percent in the bulk up to a maximum desired level (preferably between about 1% and 10% nitrogen by atomic ratio) at the upper interface.
While the illustrated example comprises grading a nitrogen concentration in a simple metal oxide layer, skilled artisan will readily appreciate, in view of the disclosure herein, that the same principles can be applied to forming graded profiles in other gate dielectric materials, such as binary and ternary metal oxides (e.g., BST, SBT) by ALD. Also, while not shown in
Thus, the basic alternating process depositing metal oxide (e.g., by alternating metal and oxidant pulses) initially is modified to deposit a lower interface of a metal oxynitride with relatively low levels of nitrogen (e.g., about 0.1% to 1% nitrogen by atomic ratio); continues with ALD of a substantially pure (e.g., less than about 0.1% nitrogen) metal oxide in an intermediate portion of the process; and, by the time the desired dielectric thickness is reached, the alternating process again increases the frequency of nitrogen pulses to produce an upper interface of metal oxynitride with relatively higher levels of nitrogen (e.g., about 1% to 10% nitrogen).
Advantageously, the process employs an intermediate reduction phase to remove halide tails, illustrated between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides that could be harmful to exposed metal and reduces halide content in the dielectric. It will be understood, however, that in other arrangements the reduction phase can be performed in a different sequence or omitted.
With reference to Table II above, an exemplary process recipe for forming the desired graded dielectric layer, will be described below. Four phases (each phase defined, in the illustrated embodiment, as including purge following reactant pulses) are described:
Varying proportions of these phases are utilized during the continuous deposition process, depending upon the stage of the deposition process. In the illustrated embodiment, during initial stages, for example, phases (1)-(4) are employed, with a relative small frequency of the nitrogen phase (4) to result in a low nitrogen content (e.g., 0.1% to 1% nitrogen by atomic ratio) at the substrate interface. During intermediate stages, phases (1)-(3) are employed in order to form substantially pure ZrO2 in the bulk. During terminal stages of the deposition, phases (1)-(4) are again employed, with a relatively greater frequency of phase (4) to result in a higher nitrogen content (e.g., 1% to 10% nitrogen by atomic ratio) at the gate electrode interface.
Note that the reduction phase (2) is optional for all stages of deposition. Advantageously, the reduction phase enables gettering halides left by the metal halide source gases. The reduction phase is thus preferably employed to reduce the chlorine content in the growing film. Note that the reduction phase, if employed, need not be employed in every cycle and, if employed in every cycle, need not be employed immediately subsequent to the metal phase.
Two three-phase cycles 450 are shown in FIG. 11. Such three-phase cycles 450 are conducted with highest frequency in forming the bulk of the dielectric, with lower frequency in forming the lower interface over the transistor channel, and with lowest frequency in forming the upper interface below the gate electrode.
One four-phase cycle 455 is also shown. In addition to the three phases of cycle 450, the four-phase cycle includes a nitrogen pulse and purge. Such four-phase cycles 455 are conducted with lowest frequency in forming the bulk of the dielectric, with higher frequency in forming the lower interface over the transistor channel, and with highest frequency in forming the upper interface below the gate electrode.
It will be understood that different impurities can be employed for the tailored dielectric. For example, the zirconium source gas pulse in a basic ZrO2 ALD process can be periodically substituted by a trimethyl aluminum (TMA) pulse during initial deposition, forming an alumina-doped zirconium oxide lower interface. The TMA pulse can be provided with decreasing frequency until pure zirconium dioxide (ZrO2) is formed for the bulk dielectric. In an exemplary process, TMA serves as an aluminum source gas and can be deposited at the same temperature (e.g., 300∞ C.) as the zirconium oxide ALD process. Alternatively, aluminum source gas can be introduced simultaneously and as an increasing proportion of the zirconium source gas during a metal pulse, which is continually alternating with an oxidant pulse. In this case, the skilled artisan can determine through routine experimentation what proportions of aluminum source gas to zirconium source gas should be used to obtain the desired material proportions in the layer. Similarly, the skilled artisan will readily appreciate that other gate dielectric materials can also be created in this fashion.
In the above example of aluminum oxide and zirconium oxide, aluminum oxide serves as a good barrier diffusion with good electrical interface properties, while zirconium dioxide provides a higher overall dielectric constant value for the dielectric. The gate dielectric can again be graded from a high aluminum content lower interface to substantially pure ZrO2 to a high aluminum content upper interface. The aluminum content at the interface provides an amorphous, good diffusion barrier that stabilizes the dielectric against reaction with upper or lower materials.
In either of the above-described ALD arrangements, exemplified by
It will be appreciated by those skilled in the art that various omissions, additions and modifications may be made to the processes described above without departing from the scope of the invention, and all such modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims.
All references cited herein are expressly incorporated by reference.
|Cited Patent
|Filing date
|Publication date
|Jul 3, 1943
|Feb 12, 1946
|Eastman Kodak Co
|Formation of mirrors by thermal evaporation
|Apr 19, 1974
|Jul 15, 1975
|Rca Corp
|Method of selectively depositing glass on semiconductor devices
|May 14, 1976
|Nov 1, 1977
|Data General Corporation
|Method of fabricating metal-semiconductor interfaces
|Nov 25, 1975
|Nov 15, 1977
|Tuomo Suntola
|Method for producing compound thin films
|Jan 30, 1980
|Sep 29, 1981
|Siemens Aktiengesellschaft
|Method of manufacturing semiconductor bodies composed of amorphous silicon
|Nov 13, 1980
|Aug 10, 1982
|Motorola, Inc.
|Method for improving the efficiency of solar cells having imperfections
|Jul 26, 1982
|Mar 13, 1984
|Agency Of Industrial Science & Technology
|Method for treatment of metal substrate for growth of hydrogen-containing semiconductor film
|Feb 13, 1984
|Oct 1, 1985
|Pennwalt Corporation
|Method of manufacture of EMI/RFI vapor deposited composite shielding panel
|Oct 4, 1985
|Feb 24, 1987
|U.S. Philips Corporation
|Method of manufacturing a semiconductor device
|Jun 12, 1986
|May 31, 1988
|Crystal Specialties, Inc.
|Method and apparatus for producing a constant flow, constant pressure chemical vapor deposition
|May 15, 1986
|Aug 23, 1988
|Varian Associates, Inc.
|Low pressure chemical vapor deposition of metal silicide
|Feb 25, 1987
|Jan 3, 1989
|Matsushita Electric Industrial Co., Ltd.
|Method of manufacturing a multilayer ceramic body
|Feb 1, 1990
|Feb 12, 1991
|Air Products Abd Chemicals, Inc.
|Deposition of silicon dioxide and silicon oxynitride films using azidosilane sources
|Nov 1, 1991
|Aug 4, 1992
|Thyssen Edelstalhwerke Ag
|Process for plasma-chemical cleaning prior to pvd or pecvd coating
|Sep 2, 1992
|Jan 25, 1994
|General Electric Company
|Method of fabricating a thin film transistor using hydrogen plasma treatment of the intrinsic silicon/doped layer interface
|Jul 21, 1993
|Apr 26, 1994
|Nippon Steel Corporation
|Process for forming a thin metal film by chemical vapor deposition
|Apr 25, 1994
|Sep 12, 1995
|Micron Technology, Inc.
|Method of chimical mechanical polishing for dielectric layers
|Nov 8, 1994
|Nov 19, 1996
|Micron Technology, Inc.
|Method of reducing carbon incorporation into films produced by chemical vapor deposition involving organic precursor compounds
|Oct 18, 1994
|Nov 19, 1996
|Tdk Corp.
|Method of making a semiconductor image sensor device
|Dec 23, 1993
|Dec 24, 1996
|Hitachi, Ltd.
|Plasma processing method and an apparatus for carrying out the same
|Jun 9, 1994
|Mar 10, 1998
|Motorola, Inc.
|Method of formation of semiconductor gate dielectric
|Feb 25, 1997
|Jul 14, 1998
|Samsung Electronics Co., Ltd.
|Methods for fabricating electrode structures including oxygen and nitrogen plasma treatments
|Sep 8, 1995
|Aug 18, 1998
|Micron Technology, Inc.
|Method of chemical mechanical polishing for dielectric layers
|Aug 16, 1996
|Jun 29, 1999
|Sherman; Arthur
|Sequential chemical vapor deposition
|Sep 5, 1996
|Aug 17, 1999
|Advanced Micro Devices, Inc.
|Ultrathin oxynitride structure and process for VLSI applications
|Dec 17, 1996
|Sep 7, 1999
|Intel Corporation
|In-situ pre-ILD deposition treatment to improve ILD to metal adhesion
|Dec 2, 1997
|Nov 23, 1999
|France Telecom
|Process for treating a semiconductor substrate comprising a surface-treatment step
|Sep 22, 1997
|Nov 30, 1999
|Applied Materials, Inc.
|Method for substrate processing with improved throughput and yield
|Jun 25, 1997
|Feb 1, 2000
|Advanced Micro Devices, Inc.
|Method of fabricating a semiconductor device having nitrogen-bearing gate electrode
|Mar 9, 1998
|Mar 7, 2000
|Lsi Logic Corporation
|Method of forming variable thickness gate dielectrics
|Jun 16, 1998
|May 16, 2000
|Advanced Micro Devices, Inc.
|RTCVD oxide and N2 O anneal for top oxide of ONO film
|Mar 9, 1998
|Jul 11, 2000
|Lsi Logic Corporation
|Composite semiconductor gate dielectrics
|Dec 9, 1998
|Jul 18, 2000
|Kittle; Paul A.
|Surface treatment of semiconductor substrates
|Aug 14, 1998
|Aug 8, 2000
|Advanced Micro Devices, Inc.
|Multipurpose graded silicon oxynitride cap layer
|Dec 30, 1997
|Aug 22, 2000
|Applied Materials, Inc.
|Reactive preclean prior to metallization for sub-quarter micron application
|Dec 18, 1997
|Oct 3, 2000
|Advanced Micro Devices, Inc.
|Method of manufacturing a semiconductor device having nitrogen-bearing oxide gate insulating layer
|Mar 11, 1999
|Dec 19, 2000
|Advanced Micro Devices, Inc.
|Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices
|Jan 5, 1999
|Jan 16, 2001
|Advanced Micro Devices, Inc.
|Graded compound seed layers for semiconductors
|Jul 6, 1999
|Jan 30, 2001
|Taiwan Semiconductor Manufacturing Company
|Method of generating two nitrogen concentration peak profiles in gate oxide
|Apr 30, 1998
|Feb 6, 2001
|Sharp Laboratories Of America, Inc.
|Method of forming nitrogen implanted ultrathin gate oxide for dual gate CMOS devices
|Sep 30, 1999
|Mar 13, 2001
|Sharp Laboratories Of America, Inc.
|Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET
|Mar 2, 1998
|Mar 20, 2001
|Hewlett-Packard Company
|In-situ fluid jet orifice
|Jun 24, 1997
|Mar 27, 2001
|Micron Technology, Inc.
|Method for forming a dielectric
|Sep 8, 1998
|Jun 12, 2001
|Advanced Micro Devices, Inc.
|Process for reliable ultrathin oxynitride formation
|Jun 10, 1999
|Aug 7, 2001
|Conexant Systems, Inc.
|Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials
|Dec 22, 1998
|Sep 25, 2001
|Cvc Products Inc.
|Semiconductor chip interconnect barrier material and fabrication method
|Feb 2, 2000
|Oct 2, 2001
|Paul A. Kittle
|Surface treatment of semiconductor substrates
|May 10, 2000
|Oct 23, 2001
|Advanced Micro Devices, Inc.
|Multipurpose graded silicon oxynitride cap layer
|Dec 9, 1999
|Dec 11, 2001
|International Business Machines Corporation
|Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
|Oct 8, 1998
|Mar 26, 2002
|Advanced Micro Devices, Inc.
|Alloy barrier layers for semiconductors
|Jul 28, 2000
|Apr 9, 2002
|Advanced Micro Devices, Inc.
|Method of copper interconnect formation using atomic layer copper deposition
|Nov 28, 2000
|Apr 9, 2002
|Advanced Micro Devices, Inc.
|Graded compound seed layers for semiconductors
|May 11, 1998
|Jun 4, 2002
|Taiwan Semiconductor Manufacturing Company
|PE-silane oxide particle performance improvement
|Mar 30, 1999
|Aug 20, 2002
|Cypress Semiconductor Corp.
|Method for forming nitrogen-rich silicon oxide-based dielectric materials
|Mar 6, 2001
|Mar 18, 2003
|Asm Microchemistry Oy
|Method of forming graded thin films using alternating pulses of vapor phase reactants
|Dec 1, 2000
|Dec 2, 2003
|Taiwan Semiconductor Manufacturing Co., Ltd.
|Graded dielectric layer and method for fabrication thereof
|Oct 26, 1998
|Feb 24, 2004
|Seiko Epson Corporation
|Semiconductor devices including electrode structure
|Dec 23, 2002
|Mar 9, 2004
|Asm International N.V.
|Graded thin films
|Dec 13, 2000
|Aug 23, 2001
|Martha Truninger
|In-situ fluid jet orifice
|Mar 6, 2001
|Nov 15, 2001
|Werkhoven Christian J.
|Graded thin films
|Jul 10, 1998
|Jan 17, 2002
|Ajit P. Paranjpe
|Method for forming a copper film on a substrate
|Jan 30, 2002
|Aug 1, 2002
|Cvc Products, Inc., A Delaware Corporation
|Microelectronic interconnect material with adhesion promotion layer and fabrication method
|Mar 16, 1994
|Sep 28, 1994
|AT&T Corp.
|Oxynitride dielectric process for IC manufacture
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Feb 1, 2000
|Sep 14, 2000
|Genus, Inc.
|Radical-assisted sequential cvd
|Apr 14, 2000
|Oct 19, 2000
|Arthur Sherman
|Sequential chemical vapor deposition
|Abeles, et al., Amorphous Semiconductor Superlattices. Physical Review Letters, vol. 51, No. 21, pp. 2003-2006 (1993).
|Atomic Layer Deposition Targets Thin Films, Wafer Processing, Semiconductor International, Sep. 1999.
|Bai, High K Gate Stack for Sub-0.1 UM CMOS Technology, Electrochemical Society Proceedings. vol. 99-100, pp. 39-44 (1999).
|Del Prado, et al., Full composition range silicon oxynitride films deposited by ECR-PECVD at room temperature. Thin Solid Films, vol. 344, pp. 437-440 (1999).
|Desu, et al., Enhanced Dielectric Properties of Modified Ta<SUB>2</SUB>O<SUB>5 </SUB>Thin Films. Mat Res Innovat (1999) 2:299-302.
|Guo et al., "Tunneling leakage current in oxynitride dependence on oxygen/nitrogen content" IEEE Electron device letters vol. 19 No. Jun. 1998 pp. 207-209.
|Hiltunen, et al., Nitrades of Titanium, Niobium, Tantalum and Molybdenum Grown as Thin Films by the Atomic Layer Epitaxy Method, Thin Solid Films, 166 (1988) pp. 149-154.
|Kaizuka, et al., Conformal Chemical Vapor Deposition TiN (111) Film Formations as an Underlayer of Ai for Highly Reliable Interconnects, jpn. J. Appl. Phys. vol. 33 (1994) pp. 470-474.
|Kikkawa, et al., A Quarter-Micrometer Interconnection Technology Using a TiN/Al-Si-Cu/TiN/Ai-Si-Cu/TiN/Ti Multilayer Structure, IEEE Transactions on Electron Devices. vol. 40, No. 2 Feb. 1993.
|Kikkawa, et al., Ai-Si-Cu/TiN Multilayer Interconnection and Ai-Ge Reflow Sputtering Technologies for Quarter-Micron Devices, 54/SPIE vol. 1805 Submicrometer Metallization (1992).
|Kim, H. and R. Reif, In-situ low-temperature (600∞ C) wafer surface cleaning by electron cyclotron resonance hydrogen plasma . . . , Thin Solid Films, vol. 289:192-198 (1996).
|Klaus et al. Atomically controlled growth of tungsten and tungsten nitride using sequential surface reactions, Applied Surface Science, vol. 162-163, pp. 479-491 (2000).
|Lee et al. "The high resistivity properties of tungsten nitride thin films deposited by rf & dc sputtering" Proceedings of the 5<SUP>th </SUP>intern. conference on properties and applications of dielectric materials, May 1997 p674-676.
|Lee et al., JP 2000058777 (English Abstract).
|Leskel‰, et al., Atomic Layer Epitaxy in Deposition of Various Oxide and Nitride Thin Films , Journal De Physique IV. Colloque C5, Supplement au Journal de Physique II. vol. 5, jiun 1995.
|Lucovsky, Integration of Alternative High-K Gate Dielectrics into Aggressively Scaled CMOS Si Devices: Chemical Bonding Constraints at Si-Dielectric Interfaces. Electrochemical Society Proceedings, vol. 99-10, pp. 69-80 (1999).
|Maiti. et al., Improved ultrathin oxynitride formed by thermal nitridation and low pressure chemical vapor deposition process, Applied Physics Letter, vol. 61. No. 15, pp. 1790-1792 (1992).
|Martensson, et al., Use of Atomic Layer Epitaxy for Fabrication of Si/TiN Cu Structures, J. Vac. Sci. Technol.B 17(5), Sep./Oct. 1999, pp. 2122-2128.
|Min, et al., Atomic Layer Deposition of TiN Films by Alternate Supply of Tetrakis (ethylmethylamino)-Titatium and Ammonia, Jpn. J. Appl. Phys. vol. 37 (1998) pp 4999-5004.
|Min, et al., Atomic Layer Deposition of TiN Thin Films by Sequential Introduction of Ti precursor and NH<SUB>3</SUB>. Mat Res. Soc. Symp. Proc. vol. 514 1998 Materials Research Society.
|Nakajima, et al., Atomic-layer-deposited silicon-nitride/SiO<SUB>2 </SUB>Stacked gate dielectrics for higly reliable p-metal-oxide-semiconductor filed-effect transistors, Applied Physics Letters, vol. 77, No. 18, pp 2855-2857 (2000).
|Nakajima, et al., Low-temperature formation of silicon nitride gate dielectrics by atomic-layer deposition, Applied Physics Letters, vol. 79, No. 5, pp. 665-667 (2001).
|Ramm J. and E. Beck. Low temperature epitaxial growth by molecular beam epitaxy on hydrogen-plasma-cleaned silicon wafers, Thin Solid Films, vol. 246, 158-163 (1994).
|Ritala, et al., Atomic Layer Epitaxy Growth of tiN Thin Films from TiI<SUB>4 </SUB>and NH<SUB>3</SUB>. J. Electrochemical Soc., vol. 145, No. 8, Aug. 1998 pp. 2914-2920.
|Ritala, et al., Controlled Growth of TaN, Ta<SUB>3</SUB>N<SUB>5, </SUB>and TaO<SUB>x</SUB>N<SUB>y </SUB>Thin Films by Atomic Layer Deposition. Chem. Mater., vol. 11, pp. 1712-1718 (1999).
|Ritala, et al., Perfectly Conformal TiN and Ai<SUB>2</SUB>O<SUB>3 </SUB>Films Deposited by Atomic Layer Deposition. Communications. Chemical Vapor Deposition 1999, 5, No. 1, pp. 7-9.
|Citing Patent
|Filing date
|Publication date
|Jul 30, 2004
|Jun 6, 2006
|Method and apparatus for non-aggressive plasma-enhanced vapor deposition of dielectric films
|Oct 29, 2004
|Aug 1, 2006
|Tokyo Electron Limited
|Method of manufacturing semiconductor device, film-forming apparatus, and storage medium
|Aug 2, 2004
|Apr 24, 2007
|Micron Technology, Inc.
|Method of forming metal oxide and semimetal oxide
|Aug 30, 2004
|Jan 29, 2008
|Micron Technology, Inc.
|Plasma processing, deposition and ALD methods
|Sep 23, 2005
|Apr 29, 2008
|Micron Technology, Inc.
|Methods of forming metal oxide and semimetal oxide
|Jul 24, 2006
|Jul 22, 2008
|Micron Technology, Inc.
|Plasma processing, deposition, and ALD methods
|Dec 9, 2003
|Oct 7, 2008
|Micron Technology, Inc.
|Atomic layer deposition method of depositing an oxide on a substrate
|Feb 24, 2005
|Jan 27, 2009
|L'air Liquide, Societe Anonyme A Directoire Et Conseil De Surveillance Pour L'etude Et L'exploitation Des Procedes Georges Claude
|Method for forming dielectric or metallic films
|Mar 8, 2007
|Jan 12, 2010
|Applied Materials, Inc.
|Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
|Aug 28, 2006
|Mar 2, 2010
|Asm International N.V.
|Conformal lining layers for damascene metallization
|Dec 20, 2006
|Mar 16, 2010
|Applied Materials, Inc.
|Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
|Jun 26, 2007
|Jul 6, 2010
|Applied Materials, Inc.
|Methods for depositing tungsten after surface treatment
|May 5, 2006
|Sep 21, 2010
|Applied Materials, Inc.
|Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool
|Dec 20, 2006
|Nov 23, 2010
|Applied Materials, Inc.
|Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
|Jul 20, 2006
|Nov 23, 2010
|Micron Technology, Inc.
|Atomic layer deposition method of depositing an oxide on a substrate
|Sep 26, 2007
|Mar 8, 2011
|Applied Materials, Inc.
|Fluorine plasma treatment of high-k gate stack for defect passivation
|Oct 30, 2009
|Apr 12, 2011
|Infineon Technologies Ag
|High-k dielectric film, method of forming the same and related semiconductor device
|Jun 6, 2008
|Aug 23, 2011
|Micron Technology, Inc.
|Plasma processing, deposition and ALD methods
|May 21, 2004
|Feb 21, 2012
|Applied Materials, Inc.
|Formation of a silicon oxynitride layer on a high-k dielectric material
|Jun 27, 2005
|Jun 19, 2012
|Cambridge Nanotech, Inc.
|Vapor deposition systems and methods
|Mar 19, 2008
|Aug 7, 2012
|Hitachi Kokusai Electric Inc.
|Substrate processing apparatus and method for manufacturing semiconductor device
|Jul 12, 2012
|Feb 5, 2013
|Hitachi Kokusai Electric Inc.
|Method for manufacturing semiconductor device and method for processing substrate
|May 7, 2007
|Feb 12, 2013
|University Of South Carolina
|Digital oxide deposition of SiO2 layers on wafers
|Aug 31, 2009
|Nov 12, 2013
|Micron Technology, Inc.
|Electronic devices including barium strontium titanium oxide films
|Dec 20, 2011
|Jul 28, 2015
|Asm America, Inc.
|In-situ pre-clean prior to epitaxy
|Mar 13, 2013
|Oct 27, 2015
|Asm Ip Holding B.V.
|Atomic layer deposition of GeO2
|Nov 8, 2013
|Dec 1, 2015
|Micron Technology, Inc.
|Electronic devices including barium strontium titanium oxide films
|Dec 19, 2013
|Dec 22, 2015
|Asm Ip Holding B.V.
|Cyclical deposition of germanium
|Oct 30, 2013
|May 3, 2016
|Asm Ip Holding B.V.
|Method of depositing thin film
|Mar 1, 2013
|May 3, 2016
|Taiwan Semiconductor Manufacturing Company, Ltd.
|Nitrogen-containing oxide film and method of forming the same
|Nov 27, 2011
|Jan 31, 2017
|Ultratech Inc.
|Vapor deposition systems and methods
|Dec 15, 2015
|Feb 21, 2017
|Asm Ip Holding B.V.
|Cyclical deposition of germanium
|Jul 30, 2004
|Feb 3, 2005
|Method and apparatus for non-aggressive plasma-enhanced vapor deposition of dielectric films
|Dec 9, 2003
|Jun 9, 2005
|Derderian Garo J.
|Atomic layer deposition method of depositing an oxide on a substrate
|Oct 29, 2004
|Jun 30, 2005
|Shigeru Nakajima
|Method of manufacturing semiconductor device, film-forming apparatus, and storage medium
|Feb 22, 2005
|Oct 20, 2005
|Applied Materials, Inc.
|In-situ dry clean chamber for front end of line fabrication
|Jun 27, 2005
|Feb 2, 2006
|Cambridge Nanotech Inc.
|Vapor deposition systems and methods
|Aug 2, 2004
|Feb 2, 2006
|Marsh Eugene P
|Method of forming metal oxide and semimetal oxide
|Sep 23, 2005
|Feb 2, 2006
|Marsh Eugene P
|Methods of forming metal oxide and semimetal oxide
|Aug 30, 2004
|Mar 2, 2006
|Rueger Neal R
|Plasma processing, deposition, and ALD methods
|Mar 10, 2006
|Aug 24, 2006
|Method and apparatus for non-aggressive plasma-enhanced vapor deposition of dielectric films
|Jul 20, 2006
|Nov 16, 2006
|Derderian Garo J
|Atomic layer deposition method of depositing an oxide on a substrate
|Jul 24, 2006
|Nov 23, 2006
|Rueger Neal R
|Plasma processing, deposition, and ALD methods
|Feb 20, 2004
|Feb 8, 2007
|Forschungszentrum Julich Gmbh
|Method for depositing compounds on a substrate by means of metalorganic chemical vapor deposition
|Aug 28, 2006
|May 3, 2007
|Ivo Raaijmakers
|Conformal lining layers for damascene metallization
|Feb 24, 2005
|Aug 16, 2007
|Ashutosh Misra
|Method for forming dielectric or metallic films
|Mar 19, 2008
|Oct 30, 2008
|Hitachi Kokusai Electric Inc.
|Substrate processing apparatus and method for manufacturing semiconductor device
|Jun 6, 2008
|Nov 6, 2008
|Rueger Neal R
|Plasma Processing, Deposition and ALD Methods
|Oct 30, 2009
|Feb 25, 2010
|Infineon Technologies Ag
|High-k dielectric film, method of forming the same and related semiconductor device
|Jul 12, 2012
|Nov 1, 2012
|Hitachi Kokusai Electric Inc.
|Substrate processing apparatus and method for manufacturing semiconductor device
|May 7, 2007
|Jan 17, 2013
|Asif Khan
|Digital oxide deposition of sio2 layers on wafers
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Oct 10, 2000
|Certificate of correction
|Sep 26, 2002
Owner name: ASM AMERICA, INC., ARIZONA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHERO, ERIC J.;POMAREDE, CHRISTOPHE;REEL/FRAME:013349/0664
Effective date: 20020925
|Apr 8, 2009
|Fee payment
Year of fee payment: 4
|Mar 7, 2013
|Fee payment
Year of fee payment: 8
|Apr 20, 2017
|Fee payment
Year of fee payment: 12


text:
There will probably be a lot of post on my guest house progress, as I am moving rather slow on it. But since my last post on the living room area, I have made a little bit of progress to show you.
I had the two parson chairs slip covered
I bought the fabric from OneKingsLane a couple of months back, and the quality of the fabric was unbelievable.Since the damask print was more expensive than the plain fabric, I decided to just use it on the bottom skirt.
I love the subtle strip on the main fabric. I had these made by someone else, I didn't even try to attempt it, I know my strengths, and slip covering isn't one of them. She did a wonderful job.
I bought the table at Pottery Barn. They had it displayed as a side table next to a couch, but I knew it would be perfect for the little dining area. I love the wood color and the rustic look of it with the more tailored chairs.
The rug, well it was the perfect color, but the style of it was nothing like I thought. That is the risk you take when you order on line. It is a popcorn loop, rather than a plush shag like I thought it was going to be.
I thought about returning it, but then decided it wasn't so bad, and the color was spot on, so it is a keeper.
I am thinking about getting this lamp from Pottery Barn for the glass side table
and pairing it with this damask lamp shade I bought at Homegoods for $12.99 {overlook the silk flowers, they aren't staying there}
And then adding a chandelier over the Pottery Barn round table with something like this
Or a little bit more glam like this
So the progress so far is from this
To a freshened up look of this
I still haven't finished that large cabinet, I need my husband to fix the cabinet door and drawer. Not his fault though, I keep forgetting to remind him, you know how that goes.
Unfortunately I have to keep those elephant tusks in the room. I have no where else to put them. They were never my favorite, hence the reason they are in the guest house. They make a great conversation piece when people come over, they are made with very intricate inlaid ivory. But to me they are like an elephant in the room {pun intended}

subset: commoncrawl


text: Hi all, This is my first time posting and first time rooting a phone. I have a couple questions that I hope to get help with. Let me start with info about my phone first. I have a droid X and am running Android version 2.3.3. All I have done so far is rooted it. I have Droid X Bootstrap and ClockworkMod Rom Manager. 1. I can't restart my phone into recovery mode using the Bootstrap. Not even manually by holding home then pressing the search button. Am I doing something wrong? 2. Android version 2.3.3 is running GingerBread, right? 3. I've tried deodexing but it doesn't work everytime, know a good tutorial? Thanks for you time!


text:
A BRANCH post office in Burnley looks set to be the next to form part of a national transformation programme by mail bosses.
An extra 10 hours per week will be offered to customers at the Coal Clough Lane premises, say Post Office chiefs.
An open-plan arrangement has been drawn up for the premises, which will be closed from February 10 and reopen on February 24.
While the refurbishment is ongoing customers are being advised to use the main town centre branch in Hargreaves Street or Rosehill post office in Manchester Road.
The newly-revamped branch would be open 8.30am to 6pm Mondays to Fridays and from 9am to 5.30pm on Saturdays.
Post Office area manager Sue Whittall said: "We are confident that this new modern Post Office service will meet the needs of the local community and secure services for the future."


text:
Presented by: Dan Holme and Gary Lapointe Running Time: 100 min Microsoft made important improvements to PowerShell in SharePoint 2013 and in the newest version of Office 365. In this session, Dan and Gary explore the features and capabilities of PowerShell and how it can be used to automate and configure both on-premise and Office 365 SharePoint farms.
Buy This On-Demand Training Now!
This Video is part of the Administering SharePoint with Windows PowerShell On-Demand Training.
Windows PowerShell is the preferred tool for administering and automating SharePoint 2010, 2013, and Office 365. If you've been holding back on learning PowerShell, the time has come to tackle it. There's no better way to get up to speed, fast, with PowerShell than with SharePoint MVPs Dan Holme and Gary Lapointe as they join forces in four sessions, to accelerate your learning curve in this one-of-a-kind workshop


text:
"ALL-of-the-Above" Except Biofuels
by Robert E. Kozak (Advanced Biofuels USA) Here's the President's new energy policy.
"This country needs an all-out, all-of-the-above strategy that develops every available source of American energy – a strategy that's cleaner, cheaper, and full of new jobs".
Okay that sounds good. "All-of-the-above" surely sounds like that would include biofuels. So, let's do a search of the 7,089 words of the speech. Hmm. I must have entered the search term wrong. Let me try it again. No, the same result. 7,089 words, "biofuel" or "biofuels" are NOT included.
Certainly a contrast to the focus on biofuels provided by President George W. Bush in his "switchgrass" State of the Union speech.
So what does President Obama mean when he says, All-Of-The-Above?
Let's search for natural gas. Ah! That's what All-Of-The-Above means!
"We have a supply of natural gas that can last America nearly one hundred years, and my Administration will take every possible action to safely develop this energy. Experts believe this will support more than 600,000 jobs by the end of the decade."
I wonder if those experts are the same experts whom Obama quoted in 2008 and 2009 saying there would be a million electric cars on the road in the US by 2015 (less than 15,000 were sold last year)? READ MORE and MORE (Biofuels Digest) and MORE (Ethanol Producer Magazine) and MORE (Drover Cattle Network)


text:
NEW YORK (Jun. 27)
Farband Labor Zionist Order today announced the establishment of a Foundation which will support educational, research and other endeavors associated with Jewish life in the United States and throughout the world. The major purpose of the foundation will be to help perpetuate and strengthen Jewish life in America, in Israel and in other Jewish communities.
Among the beneficiaries of the Foundation will be schools, institutions of higher learning, medical centers, old-age homes and welfare funds. Scholarships to encourage students to enter the field of Jewish studies will also be established by the Foundation, In addition, it will publish books of Jewish interest and will encourage creative endeavors of all kinds.


text:
Tag Cloud - Chicago Air & Water Show
Chicago's Sky High Thrills: Chicago Air Show
There's little chance you won't know the Chicago Air and Water Show is happening. The roaring flights of supersonic jets are hard to miss, not to mention the 2.2 million people standing along the lakefront with their eyes pointed to the skies or the waters. The Chicago Air and Water Show 2012 takes place on […]more...
About 5 years ago by rivernorth No Comments
Chicago by Air, Land & Sea
Flying overhead, rattling the windows of the John Hancock Observatory, parachuting to the ground and splashing through the water! Chicago's most exciting event, the Air & Water Show is just around the corner! Will you be one of the almost 2 million people crowding the city's lakefront to try and catch a glimpse of some of the best […]more...
About 6 years ago by rivernorth No Comments


text:
Hewlett Packard
31 Dec 2012 at 08:38
Brenda has arrived at the HP testing facility. Brenda you are lucky, what a great opportunity to go behind the scenes at HP. HP loves having Flat Stanleys visit. Today, Brenda helped out with testing and got to hang out with cool HP employees. Go Brenda!
With Brenda


text:
As the Australian implementation of Resource Description and Access (RDA) approaches, Libraries Australia will be implementing a number of changes.
System changes
We will be implementing a number of changes in the Cataloguing service including:
- Support for new MARC field 264 which will replace field 260 in RDA records
- Replacement of the current Libraries Australia Cataloguing Client templates with new RDA templates
- Changes to the Record Import Service (RIS) matching and merging to give preference to RDA records over records created according to Anglo American Cataloging Rules 2nd edition (AACR2) and older standards.
These changes will be implemented towards the end of February or early in March. The Libraries Australia Training system will also be updated at that time. We will advise you of the exact date as soon as possible.
The Libraries Australia Cataloguing system already supports the use of 33X fields via RIS and the Cataloguing Client. A list of all the MARC21 changes that have already been made to support RDA can be found at: http://www.nla.gov.au/librariesaustralia/files/2012/07/MARC21_RDA_code_changes_v5_0_12.pdf
It is also possible to search for RDA bibliographic and authority records via the Cataloguing Client using the command f sou rda.
The Libraries Australia Search service will be updated in February to support the searching and display of RDA data elements. The Document Delivery service will be updated in March. We will advise you when these changes are to be implemented.
We will be adding RDA fields 336, 337 and 338 to the LA Search WebCat input form in March. In the meantime if you wish to add these fields through WebCat there is a workaround. After saving your record, and saving again at the second save prompt, you are taken to a window which displays the MARC record that you have just created. At this point it is possible to add the 33X tags in MARC format by editing the record directly.
Trove will be updated in March to support RDA data elements in bibliographic and authority records.
Cataloguing Policy changes
As previously advised, with the introduction of RDA, Libraries Australia is replacing the current Minimum Record Standard with a new standard called Required Data Elements. In addition to the RDA changes the new standard includes a small number of additional codes and fields that will make matching and merging more accurate and result in fewer duplicate records. Most records sent to the Libraries Australia already meet the new standard, except for the new RDA data elements, and we hope that it will not be onerous for contributing libraries.
From March onwards RDA will be the standard for new records added to Libraries Australia. However, we realise that in the coming year libraries will be at different stages of their RDA implementations therefore AACR2 records will continue to be accepted for at least the next year.
From March onwards when Cataloguers use an existing non-RDA record for copy cataloguing they may choose to upgrade it to RDA; however, this is not compulsory. If upgrading a record, the entire record must be examined and upgraded before changing the coding to RDA. Cataloguers may choose to add selected RDA data elements to existing non-RDA records. However, the coding of the record should not be changed to RDA unless the entire record has been examined and upgraded.
The standards documentation on the Libraries Australia web site will be updated during February and March.
Data changes
Libraries Australia is already in the process of changing selected Authority records to reflect RDA practice. These include headings for the Bible and Koran, and spelling out abbreviations for musical terms and "Dept.". These changes will appear in the LA Cataloguing service as soon as they made but some won't appear in LA Search until it is replaced later in the year.
We will also investigate opportunities for global changes to selected bibliographic records so that they more closely reflect RDA practice. These may include addition of 33X fields (where there is no ambiguity) and the spelling out of abbreviations in some fields.
If you have any questions about the Libraries Australia RDA implementation please contact the Help Desk: Make a new Libraries Australia enquiry.
More information about the Australian implementation of RDA, including the availability of RDA training courses, may be found on the ACOC RDA web site.
With kind regards,
Rob Walls | Director, Database Services | National Library of Australia
p: +61 2 6262 1657 | f: +61 2 6273 1180 | e: firstname.lastname@example.com


text:
0 item(s)
Every purchase supports National Museums Liverpool
A pack of 5 Christmas cards with The Adoration of The Kings, a detail of the central panel of a triptych in St Mary's aisle, Truro Cathedral, Cornwall.
The greeting reads: With Christmas Greetings and all good wishes for the New Year.
Dimensions: 16 x 16cm
Brand: Museums & Galleries
Tell me when this becomes available
Email address:
We will only use your email address to inform you when this is available and not for any other purposes.
National Museums Liverpool
© Copyright 2017


text:
The Alpha Chi Honor Society inducted 79 new members on Saturday, April 26, at a ceremony in Wilde Auditorium.
The new members, as well as their families and friends, were welcomed by Provost Sharon L. Vasquez and Interim Dean of Undergraduate Studies David Goldenberg. The Alpha Chi faculty advisor, Dr. Donald Jones, and the 2013–14 President of Alpha Chi, Eyas Azzuni, led the ceremony at which the honored students received their certificates and pins. Seniors also received blue and green graduation cords.
The outgoing officers received certificates for their service in 2013–14: Eyas Azzuni – President, and Kyle Hebert – Vice President. Also announced were the new officers for 2014–15: Jamie Nagode and Colleen McLoughlin – Co-Presidents; Melitsa Vasilakis – Treasurer; and Heather Taft – Secretary.


text:
Beta Request for PG slash sequel to Wooden Horse
Expand Messages
- Hi, it's the second half of the challenge. After you've written the
story you take a sample of the work and give it to the artist you've
partnered. The artist then gives you a sample of his/her work and you
both adapt your work to take this sample into effect.
I played with Sheppard and she played with Rodney hence Rodney comes
to play in my story :) Um I was aiming for something specific with
Rodney and I'd really like to know if it can be seen. So if you do
glance over my story please let me know what you think that was.
Your message has been successfully submitted and would be delivered to recipients shortly.


text:
New Beretta PX4 Compact.
The new Compact PX4s are out now and I just bought one on an auction site today. When I get it in my hands I'll do a review of Berettas' latest. If it's as good as my full size and subcompact PX4s I'll be very happy.
I am interested. Looking forward to your report. Thanks.
I've shot the Px4 Compact 9mm and really liked it, interested to hear about the 40 that just came out
The Beretta full size and sub compact have been out for quite some time. The pistol I just bought is the newly released compact version that size wise is in between the full size and the subcompact. It's only available in 9mm but will be out in 40 calibre hopefully sometime next year.
Good for you.
Post a picture if you can.
3 Attachment(s)
Received my new Compact PX4 this afternoon, and couldn't be happier. This one is more comfortable then my full size or sub compact and feels great in hand. Size wise the grip is slightly longer than my S&W M&P9c but similar to the both the S&W and Glock 19. The fit and finish is beautiful and the action is very nice with a smooth double action and a crisp single action. This is going to be a great CC pistol and if it shoots as well as my other PX4s I'll be happy.
It's cold here in Illinois but I'm going to try to get to the range tomorrow and put some rounds thru it. Anyone who likes PX4s should definately check this latest version out. Range report to follow.
Great looking gun.
I have both the full and subcompact.
I'll be looking into this also.
Please let us know how it shoots.
3 Attachment(s)
I braved 32 degree weather this afternoon to see how this new Beretta shoots. First off I was amazed at the soft recoil, it is softer than my full size PX4 and way softer than my sub compact. Beretta reengineered the recoil spring and it has a polymer piece enclosing it, whatever they did it works. I fired a total of 200 rounds of assorted ammo and all worked flawlessly. I shot the following.
1. 100 rnds Winchester White Box 115 grn from Wal-Mart.
2. 45 rnds of Federal AE 115,124 and 147grn.
3. 15 rnds Speer Gold Dot 124 grn.
4. 15 rnds Federal HST 147 grn.
5. 15 rnds Winchester PDX1 147 grn.
6. 10 rounds Winchester Ranger T +P 124 grn.
The new Beretta flawlessly ate everything and all the non +P loads had a very mild recoil impulse. The Winchester +P was definately snappier but still comfortable. I shot groups at 10, 15 and 25 yards and this thing is accurate.
Of all the PX4s I've owned this one is my hands down favorite. All the versions are good guns but for anyone thinking about buying one the new Compact IMO is the best one.
This first photo was my 25 yard group from a rest, the 2'nd photo is my offhand group from 10 yards. The third photo is a closeup of my 10 yard offhand group, this is 25 rounds. It was cold, very cold and this being my first time out with it I was very happy with the accuracy.
Congrats on the new pistol and nice shooting. glad to hear you like it so much, I just picked up my Storm in.45cal today.
Great shooting.
And it looks like a great gun.
|All times are GMT. The time now is 12:17 PM.
Copyright ©2000 - 2017, Jelsoft Enterprises Ltd.