text:
Composing intellectual property blocks is an essential element of a design methodology based on re-use. The composition of these blocks when the IPs have been developed by different groups inside the same company, or by different companies, is notoriously difficult. Design rules in the form of interface specifications have been proposed which try to alleviate the problem by forcing the designers to be precise about the behavior of the individual components, and to verify this behavior under a number of assumptions about the environment in which they have to operate. In this work we study the problem of the specification, synthesis, and verification of interfaces for different models of computation and across models of computation. This work supports the Metropolis Meta-Model in the construction of a system integration platform that can integrate heterogeneous models.
Roughly speaking, two agents are compatible if they fit together as they are. In this work we formalize this notion by introducing, for each model of computation, a set of agents that "behave well," and by deriving a refinement ordering that represents substitutability, called the conformance ordering. We show that under certain assumptions we can represent the set of compatible agents by a single maximal environment, called a mirror. Two agents are compatible if one conforms to the maximal environment of the other.
When components are taken from legacy systems or from third-party vendors, it is likely that their interface communication protocols are not compatible. In this case, an additional adapter can sometimes be introduced to convert from one agent to the other so that their composition is compatible. The notion of a maximal environment allows us to formulate a synthesis algorithm for an adapter that conforms to the specification of a desired communication.
We formulate the problem in particular for synchronous and asynchronous systems. We use an automata-based and a game-theoretic based approach to solving the adaptation problem and to synthesize a converter between two specified protocols.
Static timing analysis is the most used approach to critical path detection in combinational circuits. Since traditional criteria used in standard static timing analysis depend on circuit delay assignment, the analysis has to be repeated after each timing optimization step. A new approach to static timing analysis has been recently proposed in [1]. The cornerstone of the method consists of grouping paths into three categories: strongly perceptible, imperceptible, and weakly perceptible. This categorization allows definite distinction between paths that impact the circuit delay, and therefore need to be sped up, and those that do not, thus reducing the timing optimization effort. Furthermore, this new approach has the advantage of being independent on the circuit delay assignment and, therefore, static timing analysis need not be applied over and over after each timing optimization step. The main drawback of the method is that the criteria to check which category a path belongs to, which has been provided by the author, are partially ambiguous and not easy to compute. We identified new criteria for this path categorization based on the flattening of a circuit into an equivalent normal form (ENF). Our criteria, while being straightforward to check, clear any previous ambiguity, thus allowing the capture of the power of this new path categorization.
Sensor networks present many opportunities for changing the way computers interact with the environment. Sensor network devices present major challenges because they must be functional under strict power requirements. Since wireless communication is the largest source of power consumption, we explore efficient algorithms for information gathering that try to minimize the amount of communication while still gathering the requisite amount of data.
Our research focuses on an efficient traversal method to gather information from the network. We assume that nodes have a fixed communication radius. Our model also assumes that every node has complete information about each of its neighbors. In addition, a node can go into sleep mode, and it will not take part in communication while in this state. Given the above constraints, we are attempting to design heuristic methods that will gather information from all nodes while actually visiting a minimal number of nodes.
Our approach involves a graph theoretical formulation coupled with geographic knowledge about the network. In this approach, each node is represented as a vertex and a communication path is represented as an edge. We are investigating the significance of network perimeter nodes, articulation points, and sub-areas as components of this heuristic approach.
The complexity of the systems-on-a-chip design requires an aggressive re-use of intellectual property (IP) circuit blocks. However, IP blocks can be safely re-used only if they do not affect other sensitive components. The switching activity of CMOS digital circuit blocks typically produces high frequency current noise both into the Gnd/Vdd system, and into the substrate of integrated circuits. Such currents can potentially affect circuit reliability and performance of other sensitive components. For instance the Gnd/Vdd currents may produce electromigration, IR voltage drops, voltage oscillations due to resonances, and, possibly, electromagnetic interference. The substrate currents may couple noise to sensitive analog circuitry through body effect or direct capacitive coupling. An analysis of current injection due to switching activity is needed to properly account for all such effects during the design phase. Different effects require different types of current injection models. For instance, power consumption analysis requires time-domain average current estimation over several clock periods. IR drop, electromigration, and timing performance analysis require a time-domain noise current upper-bound with respect to all possible combinations of the inputs. Signal integrity, Gnd/Vdd grid resonances, electromagnetic interference, and substrate coupling on mixed-signal ICs, on the other hand, require an upper-bound on the spectrum of the current injected into the Gnd/Vdd system or into the substrate, respectively. Methodologies developed so far do not address this latter kind of analysis. Therefore, for these problems we are developing a methodology for estimating an upper bound over all possible input combinations for the spectrum of the noise current injected by the switching activity of digital blocks. The methodology identifies an upper bound for the spectrum of a circuit noise current by combining the noise current injected by each gate and accounting for the circuit logic functionality.
The design of protocols, i.e., the set of rules that define how the communication among two or more components of a distributed system takes place, requires the use of formal techniques and tools to obtain a correct and efficient implementation. Ulysses is a new approach for protocol synthesis from scenario-based specifications. It allows the designer to specify sequences of interactions called scenarios using message sequence nets (MSNs), a model that includes message sequence charts and explicitly shows the relations of ordering concurrency or conflict among multiple MSCs. It uses Petri Nets (PNs) as an underlying model to formally define the semantics of MSNs and to specify the internal protocol behavior. A covering procedure that uses common case patterns and derives a PN model consistent with the original MSN is defined. Independently-specified scenarios are then composed to derive a minimum cost implementation.
Some applications are so critical that they need to be resilient to faults in the computing architecture. Typically this is achieved by redundantly scheduling the application on the architecture. Starting from a network of process, some or all of the processes and the data they exchange are replicated. Additional processes may be needed for voting on the results of different replicas of a same process to establish a common result: the consensus problem [1]. We must then devise an assignment and schedule of the augmented network onto the distributed architecture.
It seems profitable to relieve the designer from the burden of devising a fault-tolerant distributed schedule, and opt for an approach based on synthesis.
In order to use resources efficiently, we want to allow the flexible use of passive replicas (replicas of a process that run only when the main replica undergoes a fault). Preliminary results have shown the usefulness of this technique in achieving higher schedulability by "reclaiming" resources from non-running replicas [2]. A further venue of improvement may arise in the context of gracefully degrading applications, where replicas are not an exact copy of the original process. Rather, there may be simpler versions with reduced functionality and/or accuracy and likely less resource requirements [3]. This exposes an opportunity to achieve higher schedulability by requiring strong fault resilience only of the light-weight versions.
Moreover, we want to allow general architectures, removing the strict boundaries of the modules and busses found in the TTA. This also enables more general fault models for the communication subsystem. The resulting architecture is a full-fledged distributed multiprocessor system, where each node can be used per se and not as a mere duplicate of another one. All the parallelism in the hardware can then be exploited to speed up the execution of parallel processes of the application [4,5] without affecting the degree of fault tolerance. We note that most of the results cited above have been derived under very restrictive assumption on the fault model. We believe some of their founding principles can be rephrased in a more general framework. The expected outcome of this research is a systematization of a set of design techniques that could allow for an easy exploration of design alternatives arising from different fault models.
A new platform library in Metropolis allows the use of the fault tolerant data flow (FTDF) model of computation. FTDF is amenable to specifying periodic feedback control applications. It is structured in such a way that it is possible to analyze it formally and to use automatic and semi-automatic synthesis techniques for obtaining an efficient fault-tolerant implementation of the application under design. The use of the platform is illustrated by a simple controller example: an inverted pendulum stabilizer.
Redundancy can be easily introduced using the Metropolis refinement mechanism. Finally it is possible to simulate and to inject faults in the design. Some of the properties of FTDF include self-synchronization and automatic degradation in case of faults.
1Outside Adviser (non-EECS), Cadence Berkeley Labs
Boolean satisfiabilty (SAT) has many applications in the area of electronic design automation. In this project, a genuine multi-valued (MV) SAT solver, CAMA, is developed. Unlike encoding approaches, it directly deals with MV variables. We extended the major speed-up techniques used in state-of-the-art binary SAT solvers, such as two literal watch-based Boolean constraint propagation (BCP), conflict-based learning with identifying unique interception point (UIP), non-chronological back-tracking, and so on. An efficient conflict analysis algorithm-based MV SAT is developed. It makes the learned clauses as compact as possible, which has a dramatic impact on the overall performance. Finally, the performance of CAMA is compared to that of Chaff [1], one of the best binary SAT solvers known so far, using a one hot encoding scheme. Our experimental results show that for hard MV SAT problems, CAMA outperforms Chaff. And our analysis also reveals some fundamental reasons why a MV SAT solver has inherent advantages over a binary SAT solver.
Sensor networks (SNs) have emerged as the bridge between the Internet and the physical world, as the driver of the next potential economic revolution, and as the imminent largest producer of data and information. Therefore, development of intellectual property protection (IPP) for SNs are of prime importance.
We propose the first IPP approach for data and information generated in sensor networks. Contrary to the current state-of-the-art of image and audio watermarking, we embed signatures before and/or during the process of data acquisition and processing. The key idea is to impose additional conditions that correspond to the cryptographically encoded author/owner's signature during the data acquisition or processing in such a way that the quality of recording or processing is not impacted, or is only minimally impacted.
The technique is generic in that it is applicable to a number of tasks in SNs, including sensor design, deployment, and data fusion. It enables real-time watermark checking and can be used in conjunction with a variety of watermarking protocols. It can also be applied to any collected multimodal data or data generated for simulation purposes. Finally, the technique is adaptive, optimization-intensive, and resilient against attack. Through simulation and prototyping we demonstrate the effectiveness of active watermarking on three important sensor network tasks: location discovery, navigation, and light characterization.
1Outside Adviser (non-EECS), UCLA
Network discovery is a fundamental task in wireless ad hoc (sensor) networks. The goal is to identify a part of the network with a particular user-specified set of graph theoretic and/or geometric properties. Representative examples of network discovery tasks include finding the shortest path between two points, a path or spanning tree through a specified subset of points, or all nodes in a given area, and areas that are not covered (holes and obstacles). We are developing efficient localized algorithms for all of these problems using the same basic systematic approach. The key new insight and building block is at each step of the process the goal is to visit nodes that provide new knowledge about the network structure, but also are likely to have neighbors that will facilitate the network discovery process. The likelihood is measured using a variety of weighted Monte Carlo integral calculations for evaluation of newly discovered areas. Although the algorithms are localized, they are able to efficiently build or estimate global objective functions.
The algorithms are flexible in the sense that they can be easily adapted to a variety of network, communication, and cost models. The effectiveness of the approach and algorithms is demonstrated on benchmarks using statistical scaling algorithms that quantify the tradeoff between the quality of the solution and the energy cost of the algorithm.
1Outside Adviser (non-EECS), UCLA
Scaling can be defined as the quantitative characterization of properties, events, and mechanisms as the instance of the object under consideration increases its size. In many fields, from physics and computational biology to multiprocessor systems and the Internet, scaling is widely studied. Often, the key prerequisite for the application of an architecture, piece of system software, or an algorithm, is how it scales. Until now, scaling has not been systematically studied in the context of wireless ad hoc sensor networks.
From the design point of view, the key novelty is that our goal is not just to analyze how already existing algorithms and mechanisms scale, but also to develop insights and techniques for the development of scalable algorithms. From a methodological point of view, the main novelty is the use of statistical techniques for analysis of scaling, including non-parametric modeling and validation, sampling, correlation, and perturbation. Special emphasis is placed on localized algorithms. We introduce several generic techniques for the development of localized algorithms and study how they scale.
1Outside Adviser (non-EECS), UCLA
System-level analog design is a process largely dominated by heuristics. Given a set of specifications/requirements that describe the system to be realized, the selection of an optimal implementation architecture comes mainly out of experience. Usually, what is achieved is just a feasible point at the system level, while optimality is sought locally at the circuit level. The reason for this is the difficulty in the analog world of knowing if something is realizable without actually attempting to design the circuit. The number of effects to consider and their complex interrelations make this problem approachable only through the experience coming from past designs. One of the main problems is that optimization at the system level is really hard because of the difficulties in abstracting single block behaviors at the system level and in estimating their performances (and feasibility) without further knowledge of the implementation architecture and topology.
The basic idea of the proposed methodology is to extend the concept of platforms developed in the digital world to analog contexts. With an analog platform (AP) [1] we indicate an architectural resource to map analog functionalities during early system level exploration phases and constrain exploration to the feasible space of the considered implementation (or set of implementations). Therefore, an AP consists of a set of behavioral models and of matching performance models. Behavioral models are abstracted parameterized models of the analog functionality which introduce at the functional level a number of non-idealities attributable to the implementation and not intrinsic in the functionality, such as distortion, bandwidth limitations, noise, etc.
We propose applying the AP paradigm to design cases from the BWRC and extending the methodology to capture more accurate design constraints. The activity should start by encapsulating the block architectures required for the candidate transceiver with the AP abstraction. For each block, a set of behavioral models has to be defined and implemented in some executable form, e.g., AMS languages or Simulink/Matlab. Then, a characterization policy and a sampling strategy have to be set up to generate performance models. Particular attention has to be focused on the interfaces of single blocks so that loading effects are properly considered and modeled. For example, the input stage of the mixer has to be considered when extracting the performance figures for the driving LNA, otherwise the loading effect present in the real implementation would not be estimated. For each block, different architectures should be modeled and merged in the platform stack. This allows having a level of abstraction in the platform stack where, for example, two or more LNA topologies are represented by the same functional model and by the union of the respective performance models. When operating at this level, a platform instance selection intrinsically performs architecture selection choosing a performance set achieved by architecture a rather than architecture b or c. At the system level, system optimization will be carried out using a non-linear optimization technique based on behavioral simulations. Possible candidates are simulated annealing and genetic algorithms, which are expected to perform well given the limited number of optimization parameters available at the system level. The challenging design of the reconfigurable radio-mobile terminal should emphasize the strengths and/or weaknesses of APs in evaluating tradeoffs over a wide range of opportunities.
Metropolis is a design environment for heterogeneous embedded systems. It is more general than other design environments in the sense that it neither biases any application domain, nor favors any particular kind of model of computation. It defines a language called Metropolis MetaModel (MMM), which is one layer above other models of computation. Therefore, it is possible to model any model of computation with MMM. In fact, in Metropolis, MMM is taken as the design input and internal representation.
Starting from the MMM design input, validating the design is the first and most important step. For this purpose, the SystemC-based simulator is widely used in Metropolis. Currently, the SystemC-based simulator can generate simulation traces out of all possibilities resulting from the non-deterministic nature of MMM. The SystemC-based simulator is still under active development. The next step is having the ability to evaluate the performance and check the properties of a design. These require the handling of function-architecture mapping, quantity resolution, and constraints checking. The first two are coming from the concept of platform-based design, where function and architecture are completely separated. By doing a simulation of the mapping between them, it is possible to evaluate the cost of implementing one function by one particular architecture. Other than simulation, it is also sometimes desirable to check properties of a design formally. MMM provides such mechanisms and it would be nice if such mechanisms could be incorporated into the SystemC-based simulator.
1Visiting Scholar, Italy
2Visiting Industrial Fellow, Intel
3Outside Adviser (non-EECS), Cadence Berkeley Lab
The design of the communication architecture is an essential step in the realization of a system-on-a-chip (SOC). The semiconductor industry is experiencing a paradigm shift from "computation-bound design" to "communication-bound design." The number of transistors that can be reached in a clock cycle, and not those that can be integrated on a chip, will drive the design process. In the context of a communication-based design methodology for SOC, we are developing the idea of constraint-driven communication synthesis. As logic synthesis was the key to the success of ASIC design in the VLSI era, we predict that the automatic synthesis of the on-chip communication architecture will be the key to the success of SOC design in the gigascale integration era. The goal of this research is to start with a system-level view of the SOC communication problem and automatically synthesize the best communication architecture among the SOC modules while considering both high level issues, such as communication topologies, protocol interfacing, resource sharing, as well as low level ones, such as metal layer allocation, wire buffering, and wire pipelining.
The first step in constraint-driven communication synthesis is the specification of the key communication parameters that govern the interactions among the SOC modules as a set of constraints for the synthesis problem. Then, the synthesis process proceeds in two stages. First, the optimal high-level architecture structure is derived while considering the different communication topologies, the possibility of mixing and matching them, the role of resource sharing (e.g., time multiplexing), the choice of the various communication protocols, and the needs of interfacing incompatible protocols. Notice that since the notion of optimality may vary from one design to another, depending on the designers' priorities (area, power, performance, complexity), the cost figure of a communication topology must be a configurable parameter. Once the best communication architecture is established, the focus shifts to finding the best low-level implementation based on the features that are available with the given technology process. In other words, this step corresponds to designing the global interconnect among the SOC modules and includes exploring the characteristics of the various metal layers, the insertion of buffers (stateless repeaters) on long wires, and the pipelining of (even) longer wires by means of latches (stateful repeaters).
The present research project relies on several results from our previous work. In particular, we have recently presented a generic theoretical framework to support constrained-driven communication synthesis as well as its application to the case of bus-based communication topologies [1]. Also, we plan to incorporate key results from our research on latency-insensitive design [2,3] and interface-based design [4].
As commercial demand for system-on-a-chip (SOC)-based products grows, the effective reuse of existing intellectual property design modules (also known as IP cores) is essential to meet the challenges posed by deep-submicron (DSM) technologies and to complete a reliable design within time-to-market constraints. An IP core must be both flexible, to collaborate with other modules within different environments, and independent from the particular details of one-among-many possible implementations. The prerequisite for easy trade, reuse, and assembly of IP cores is the ability to assemble predesigned components with little or no effort. The consequent challenge is addressing the communication and synchronization issues that naturally arise while assembling predesigned components. We believe that the semiconductor industry will experience a paradigm shift from computation- to communication-bound design: The number of transistors that a signal can reach in a clock cycle--not the number that designers can integrate on a chip--will drive the design process. The strategic importance of developing a communication-based design methodology naturally follows.
An essential element of communication-based design is the encapsulation of predesigned functional modules within automatically generated interface structures. Such a strategy ensures a correct-by-construction composition of the system. Latency-insensitive design [1] and the recycling paradigm [2] are a step in this direction. High-end microprocessor designers have traditionally anticipated the challenges that ASIC designers are going to face in working with the next process generation. Latency is increasingly affecting the design of state-of-the-art microprocessors (latency, for example, drove the design of so-called drive stages in the new hyperpipelined Netburst microarchitecture of Intel's Pentium 4) and will become a shaping force for SOC architectures [3]. On the one hand, the increasing impact of latency variations will drive architectures toward modular designs with an explicit global latency mechanism. In the case of multiprocessor architectures, latency variation will lead the designers to expose computation/communication tradeoffs to the software compilers. At the same time, the focus on latency will open the way to new synthesis tools that can automatically generate the hardware interfaces responsible for implementing the appropriate synchronization and communication strategies, such as channel multiplexing, data coherency, and so on. All these considerations lead us to propose a design methodology that guarantees the robustness of the system's functionality and performance with respect to arbitrary latency variations [4].
The theory of latency insensitive design is the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components [1]. Latency insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol [2]. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency insensitive designs composed of functionally correct modules behave correctly independent of the channel latencies. This allows us to increase the robustness of a design implementation, because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency insensitive methodology to design large digital integrated circuits by using deep sub-micron technologies [3].
Electromagnetic interference (EMI) is becoming an exceptionally crucial issue in the design of modern electronic systems. Frequencies are continuously increasing, while integration trends are squeezing entire systems into extraordinarily high circuit densities. In the conventional design methodology, electromagnetic compatibility (EMC) issues are addressed only after a prototype is built. At that stage, the traditional EMC remedies are confined to adding extra components, metal shields, metal plans, or even redesigning the entire system, with a potentially significant impact both on the cost and on the time-to-market of the products. It is our firm opinion that EMC must instead be addressed as early as possible during the design phase, and not after. EMI simulation could shorten the design time, allowing the analysis of circuits before manufacturing.
Large and expensive electronic equipment can effectively employ standard EMC solutions. But smaller, high-volume, low-priced electronic devices, automotive electronics, and most of the embedded systems cannot afford those costly solutions. Such devices are the most susceptible to EMI problems and the most sensitive to post-prototype EMC added costs. Unfortunately, they are also the most difficult to simulate with respect to EMI problems since they require "full-board" capabilities, and no tool is available to date for such task.
Full-board EMI simulation capability would therefore be instrumental in promptly verifying EMC compliance during the very first stages of the design of high-speed PCBs and IC-packages. For this application, we are investigating the use of integral equation methods:
To address efficiently the first specification, we propose to use an adjoint method to calculate a set of transfer functions from the thousands of circuit inputs (e.g., the pins of the ICs) to the tens of observation points on the measurement sphere.
To address the second specification, we are working on the generation of "dynamical linear systems" that mimic the same behavior of the original interconnect structure, but have a state vector orders of magnitude smaller. In some recent papers of ours, we show how to generate guaranteed passive reduced order models from originally passive structures including dielectrics [4], and for distributed systems with frequency dependent matrices [5] (as generated for instance when accounting for substrate effects or for fullwave effects). Finally we are developping techniques for "parameterized" model order reduction techniques [6] for enabling optimization of interconnect structures.
We address the problem of synthesizing real-time embedded controllers, taking into account constraints deriving from the implementation platform. Specifically, we address the problem of controlling a set of independent systems by using a shared single CPU processor board. Assuming a time-triggered model of computation for control processes and a real-time preemptive scheduling policy, the problem of optimizing robustness of the controlled systems is formulated. Decision variables of the optimization problem are the processes' activation periods and the feedback gains. The analytical formulation of the problem enables an efficient numerical solution based on a branch and bound scheme. The resulting design is directly implementable without performance degradations that may otherwise arise due to scheduling and execution delays.
1Postdoctoral Researcher, ReTiS Lab-Scuola Superiore S. Anna, Italy
2Professor, Università di Pisa, Italy
Embedded systems often exhibit behaviors that are best described using different formalisms and models of computation. While each model offers specialized and efficient techniques to solve particular problems in their domain of application, the interaction across models is made more difficult by their differences. As a result, this interaction is not yet well understood and is often not formally defined. In this project we seek to determine a consistent way to define interactions across different models.
We regard a system as the composition of computational domains. Each computational domain is an island in which the semantics of the coordination and communication among agents is defined, and differs from the semantics of other domains. This definition is generic and covers many possible applications: from communication between models of computation as mathematical domains, to co-simulation of applications described in different programming languages.
We use the framework of trace algebra to describe the semantic domain of each computational domain. We then investigate ways to compose domains in order to obtain additional hybrid domains that exhibit properties from their components. Constructions of this kind include products of algebras and their disjoint sums. We then study the composition of heterogenous agents (agents drawn from different computational domains) in the context of a hybrid domain, and define identity elements with respect to the operation of composition. The objective of this research is to derive correct conversion mechansisms, or communicators, from the identities in the hybrid domain.
System level designs often include a wide range of hardware and software components (e.g., control logic, data paths, sensors, actuators, drivers, and data-flow engines). Such different components can be most naturally formalized using different models of computation (MoCs). Heterogeneous systems are those systems that are best described with two or more different MoCs. Typically, a formal methodology is only applicable to a particular MoC. The objective of this research is to develop semantic foundations that can be applied to heterogeneous systems involving an unlimited number of MoCs. This is crucial for the development of a system integration platform, like the Metropolis Meta-Model, that acts as the central repository of heterogeneous information (similar to the Genesis database for layout information). In particular, the ability to formally reason about the interaction of different MoCs is fundamental for system level design and for platforms to establish a solid foundation for analysis, including formal verification, synthesis, and simulation.
Informally, the semantics of a model of computation are given by a function that maps the model to a set of agents, called the semantic domain. In this work we develop a framework in which we can express semantic domains in a form that is close to their natural formulation (i.e., the form that is most convenient for a given model of computation), and yet structured enough to give us results that apply regardless of the particular domain in question. For each domain, we define functions that formalize concepts such as parallel and sequential composition of agents, scoping, and instantiation that are naturally expressed in the model of computation. Each semantic domain is also equipped with an order on the agents that represents a refinement relation. The structure composed of the set of agents and the functions and relations over the set of agents is called an agent algebra.
An important factor in the design of heterogeneous systems is the ability to flexibly use different levels of abstraction. In our work we emphasize the relationships that can be constructed between different semantic domains at different levels of abstraction, and how they are related to the functions and the refinement relation defined on the domain. The concept of a conservative approximation is introduced as a class of functions that preserve the notion of refinement across different semantic domains. These functions are powerful tools that we can use to study the problem of the integration of heterogeneous domains. In particular, two heterogeneous models can be composed and studied in the context of a third semantic domain that is detailed enough to refine both. Abstraction can be used again to convert the results in the respective domains.
Processor design today is very much an art form. The architect comes up with a design to support an instruction set, creates a high level simulator, and then passes it on to the design team to implement. This process makes it hard for the architect to explore the design space, and requires the design team to rewrite much of the architect's model. In this research we present a communication-aware methodology for turning a description of an instruction set architecture (ISA) into a potentially complicated microarchitectural implementation. The three major goals of this work are: reusability, correct by construction designs, and the automatic generation of control and binding logic.
Previous work has produced simple in-order pipelines along with their associated control logic. Through the methodology, we aim to achieve more complicated features such as out-of order execution, speculation, and caching. Instead of aiming for automatic synthesis, we break the process into a series of steps, allowing the design decisions to be considered one at a time, and be viewed separately from the functionality of the system. Each step transforms from the previous step through refinement, mapping, or relaxation
To enable design reusability and system integration, we apply the communication based design (CBD) methodology to analog design, i.e., CBD-A. In CBD, formal specifications are used and communication adapters are introduced to deal with the mismatch between communicating blocks without modifying the incompatible blocks. Such adapters enable the interaction between the incompatible blocks. In CBD-A, similar adapters are inserted between analog blocks. To provide suitable adapters, a formal description of the analog interface is required, such as DC level, dynamic range, driving/loading capabilities, biasing requirements, and so on. On the other hand, since the analog block acting as an adapter introduces some non-ideal effects which will cause degradation on the signal (e.g., SNR degradation), we need to know the specifications of the adaptation block in terms of inserted noise, distortion, CMRR, etc.
Currently, we are exploring CBD-A based on an available hardware platform, field programmable analog array (FPAA). Its unique feature is to implement analog functions in reconfigurable architecture. So, it gives us the analog equivalent of FPGA. The FPAA is based on CMOS-based fully differential switched-capacitor technology with an analog switch fabric.
To implement analog interface adapters with FPAA, some dedicated simulation strategies based on FPAA behavioral models are developed to ensure fast and accurate estimations of the non-ideal effects introduced by specific FPAA configurations. Another part of this research is to formalize the analog interface specification from the electrical point of view and also formalize the signal degradation. We plan to develop a synthesis mechanism to map analog system descriptions and interface specifications onto an FPAA platform.


text:
Romain Grosjean collects his first Formula One points for Lotus in China
18:41 15 April 2012
LAT Photographic
After a tumultuous weeks for the car company, Hethel-backed Lotus could at least celebrate the first points for Romain Grosjean in a captivating Chinese Grand Prix.
Indeed, things could have been even better for the Frenchman's team-mate Kimi Räikkönen – who was running second with just a handful of laps left, only for his tyres to give up and leave him plummeting down the order up to the chequered flag.
In the end the Finn had to settle for a pointless 14th, while last year's GP2 champion Grosjean secured sixth with the first finish of his F1 return.
"It was a very good race, I really enjoyed it," said Grosjean. "The car felt great and the team did an amazing job to give us such a big improvement from Friday (practice), so I'm especially happy for the guys to be able to finish the race and get some good points on the board.
"To be up there fighting with McLaren and Red Bull is a great feeling and I'm happy to have got my season started properly. We've had high hopes since P3 on the grid in Melbourne, and now after a few setbacks it's time to aim higher.
"There's always room to improve and hopefully from here we can aim for the top five and eventually podiums. We'll take things step by step but I'm feeling confident for the rest of the season ahead."
Räikkönen's mood was not quite as rosy following the action in Shanghai.
"We tried to run two stops as it looked to be the fastest strategy and up until the last 10 laps it was looking good, but we ran out of tyre performance at the end," said the 2007 world champion.
"I was stuck behind Felipe (Massa) for quite a while…even if I'd got past I don't think it would have made the greatest amount of difference to the final result. We had good pace in the race, we tried a different strategy and it didn't pay off today; it's as simple as that."
Team principal Eric Boullier added: "It is getting more frustrating for us as we are clearly very close to achieving a very good result – 12 laps before the end we had one car in P2 and one car in P5 with no more pit stops to go.
"Unfortunately, we were a little bit too aggressive with our strategy. As soon as we understood some cars were doing three stops it was clear there was potential for us to finish on the podium, but we were not expecting the tyre wear to be as high as it was."
Lotus' failed official protest against Mercedes' super F-duct at the start of the weekend may yet see Enstone turn their attention to replicating the system – although with just seven days until the next race in Bahrain, such updates will most likely have to wait until the F1 circuit proceeds to Europe.

subset: commoncrawl


text: Please consider if you site provides timely information that would be of value to winter sports enthusiasts. Unique ideas and sites that include frequently updated reports from locals are also encouraged.The purpose of News: Weather: Snow and Ski Forecasts is to provide users with a collection of sites that are useful in making snow related decisions. Sites that provide information and forecasts specific to he needs and geographic (location and elevation) coverage of winter sports enthusiasts are the focus. For example a site that provides a forecast for Steamboat Springs, Colorado but doesn't recognize that users are more concerned with the forecast for conditions up on the mountain than down in town would be less relevant in the category. Sites that provide road conditions on routes that are important to winter sports enthusiasts would be a priority due to the relevance and the fact they often contain up to the minute condition reports for car & resort accessible skiing areas.


text:
Beauty Is Pain, Never Said a PodiatristPosted On: Jan 15, 2013 In: In the Spotlight, Staff Picks
When the book club I'm in selected Snow Flower and the Secret Fan as its next title, I was a little hesitant to read it, thinking I might not be the book's intended audience. To be blunt: it looked like a book for ladies. And by that I don't mean women, I mean proper ladies with lace parasols and deeply-held opinions about crumpets. The book had a soft pink cover adorned with little flowers and a delicate fan framed by floral scroll work. I know it's unfair to associate a book with its cover, or a color palate with gender, but this one was asking for it.
Of course, once I started reading, I couldn't put the beflowered thing down. The story takes place in a remote area of 19th century China. It follows the lives of two sworn sisters, or laotong, over the course of their lives – from humble girlhoods through the trials of marriage, family, and invading horde. In traditional Chinese culture, a laotong relationship was the epitome of BFFs – a formalized friendship that was expected to be more emotionally intimate than any other in the women's lives. Together they practiced nu shu, an ancient form of women's writing, which they used to exchange correspondence and to chronicle their laotong relationship on the folds of a paper fan.
Through the lives of the sworn sisters, the book examines the various degradations women were subjected to in that time and place. From birth they were considered a burden, whose only value was in service to the family and their ability to create sons. To make girls marriageable, their feet were bound in a long, gruesome process – which left them essentially housebound for the rest of their lives. I think that process best illustrates how dainty this book turned out to be: "By nightfall the eight toes that needed to break had broken, but I was still made to walk. I felt my broken toes under the weight of every step I took, for they were loose in my shoes. The freshly created space where once there had been a joint was now a gelatinous infinity of torture." Eesh.
So, while there was ample discussion of things like embroidery in the book (which was actually fascinating), there was also a healthy number of pages that were full-on gruesome. Something for everyone.
If your book club would be interested in this title, or any of our Book Club in a Bag sets, simply submit an online reservation form. We currently have over 80 Book Club in a Bag sets, each containing 10-12 copies of the book and a discussion guide, and they checkout for 8 weeks. – Ransom Jabara, Reference


text:
Seafood Restaurants With Disabled Access
Luke Benchmark
Luke Benchmark
Sea bar
This beachside cafe reads its clientele loud and clear, especially on weekends.
Abandon the lemon chicken and sweet-and-sour options for the "Home Style Cooking" of this hatted north-shore favourite.
La Perla
On an unexciting strip of Victoria Road, this truly is a shining pearl, with its bright lights and full tables.
Cheerful fish bistro upstairs and a very good fish and chip shop down.
Flickering bamboo torches lend a touch of Survivor-like excitement to this buzzy wood-and-glass eatery.
Ocean Room
A fabulous ocean frontage is a good enough excuse to convert a motel car park into a fine dining restaurant.
Flying Fish
The rough-hewn timbers and nautical saltiness of Flying Fish make it one of the sexiest dining rooms in Sydney.
The Codfather
Dishes swagger from harmonious thrills to over-ambitious spills, but all are sensationally cooked.
The Boathouse on Blackwattle Bay
This elegant, glass-encased boatshed offers plenty more reasons to visit.


text:
IMPORTANT NOTE about access to library resources:
Many of the library resources require that your computer be authenticated on the Case network. This means that if your computer is not connected directly to the Case network via ethernet cable, you must authenticate using VPN. If you are off campus or using Case's wireless, you must have VPN installed, running, and logged in on your computer.
The library homepage has a network connection status indicator at the top of the right column. A green light means your campus network connection is active, or a red light means you need to authenticate with VPN. The status indicator looks like this:
More information about using VPN for wireless or remote access can be found on the Case Help site for VPN.
Handbook of porphyrin science (vol. 1-35).
Vol. 1-25 are published. To access, please search by "Handbook of Porphyrin Science" in the library's catalog under "Title". Here is the link to Volume 1.To learn more about the unpublished volumes, please click here.
Handbook of fuel cells: fundamentals, technology, and applicationsKSL also has both online and print copies.
The switch between the old and new interfaces of Reaxys is from April 2 to June 1, 2013. After June 1st, only the new interface will be available.
KSL is pleased to announce that Case now has unlimited access to SciFinder. The Academic Unlimited Access Program no longer restricts SciFinder use by concurrent seats. Current students and faculty from all departments at Case can get access to CAS content. Under this program, CAS will provide at least 95 percent access.
To help you quickly find the substance information most relevant to your research, SciFinder has been enhanced with new bioactivity and target indicator features and substance relevance ranking.To learn more about these features and other enhancements, visit here.
OhioLINK's Electronic Journal Center (EJC) can be used to search in more than 3.4 million historic articles from Elsevier. More information can be found here.


text:
How to make Chicken Makhani
By Torchbearer Staff
Florence Graves, business manager for the College of Architecture and Design, who has owned a restaurant in Dubai and earned a chef certification at UT, says cooking is a form of creativity and relaxation for her. Put on your chef hat and join Graves in the kitchen to learn how to prepare chicken makhani. Continue reading


text:
Singletrack.com on the Road: Ashland, Oregon Report
- By Zach White
- Published Jun. 11, 2010
- Updated Dec. 7, 2012 at 12:19 PM EDT
[nggallery id=154]
Over the years I've heard more and more about how Ashland, Oregon is a trail haven with amazing singletrack flowing through giant, mossy evergreens for untold and uncrowded miles.
So when SRAM combined its 2011 product launch with the 12-mile Ashland Super D on the weekend of June 12-13, there wasn't a donut's chance in a squad car that anyone else was going from singletrack.com but me.
Skipping the usual fleet of random demo bikes to showcase their revamped XO line, as well as some Rock Shox, Avid and Truvativ goodies thrown in for true saturation, SRAM opted instead to have me fly my bike out early to switch out almost everything save the seat collar and my roached grips (not sure what they did with my bell though; very disappointing).
So, taking out the initial awkwardness of becoming familiar with a new bike before being able to concentrate on how the parts being showcased actually perform, by the end of the weekend I'll have some great feedback on the 2011 line to share with everyone.
Until then, here's some photos to keep you busy.


text:
4-Hers, adults honored at banquet
GOLD STAR AWARDS — Winning the highest awards given at the county level and presented at the 2013 Gillespie County 4-H Awards Banquet on Thursday night were Rachel Howell and Mattie Lastovica. Held at the Gillespie County Farm Bureau Event Center, the banquet honored 4-Hers and adult leaders for their successes and accomplishments during the past year. — Standard-Radio Post Photo
Recognition of the achievements and successes of local youth highlighted the 2013 Gillespie County 4-H Awards Banquet on Thursday night.
The program and catered barbecue dinner were held at the Gillespie County Farm Bureau Events Center.
Among the honors presented were the Gold Star Awards to Rachel Howell and Mattie Lastovica.
As part of the evening, the new 2013-2014 Gillespie County 4-H Council officers were installed including Mackenzie Spisak, president; Kasie Vestal, vice president; Baylie Vogel, secretary; Dylan Sione, reporter; Braden Bowers, parliamentarian, and Elaine Lochte and Mason DeLong, council delegates.
A slide presentation by Lochte was also given.
Serving as mistress of ceremonies was Mattie Lastovica, the current council president.
The 2012-2013 council officers, including Braden Bowers, vice president; Lainey Bourgeois, secretary; Elaine Lochte, reporter; Mason DeLong, parliamentarian, and Kasie Vestal and Baylie Vogel, served as announcers during the program.
For more on this story, read this week's print and online editions of the Fredericksburg Standard-Radio Post. If you are a print subscriber, your full online subscription is free. All you need to do is call 830-997-2155 to get a password. If you are not a subscriber, call 997-2155 and sign up today!


text:
Joe Williams: When Sunny Gets Blue
When Sunny Gets Blue
Joe Williams (vocals)
Ballad and Blues Master (Verve 511354-2)
Joe Williams (vocals),
Norman Simmons (piano), Bob Badgley (bass), Gerryck King (drums).
Composed by Marvin Fisher & Jack Segal.
Recorded: live at the Vine St. Bar & Grill, Hollywood, CA, May 7-8, 1987
Rating: 97/100 (learn more)
Joe Williams became primarily known as a rollicking blues shouter thanks to his illustrious 7-year stint with the Count Basie Orchestra, and his trademark "Every Day I Have the Blues." Lost upon many at that point was the fact that Joe was a rewarding balladeer as well. By the time the '80s rolled around, Williams had established his reputation as a superbly versatile jazz singer, but if anyone still needed a reminder, his two critically acclaimed CDs ñ Every Night and Ballad and Blues Master ñ both recorded in May 1987 at the Vine St. Bar & Grill, offered convincing, definitive proof. (The latter album won a Grammy award.)
"When Sunny Gets Blue" is not the most gracefully flowing of standard ballads, which makes the tune all the more challenging to pull off. Williams's silky timbre and articulate, warmhearted delivery grab you from the start. Taken at a slow tempo, the song allows full contemplation by both the audience and the vocalist, who sings it here in a tight, almost conversational range, with an occasional deep baritone note added for emphasis, such as on the last word of the phrase "memories will fade." His closing, tenderly held high note caps one of the best recorded versions of this standard. Pianist Simmons, always an exceptional vocal accompanist, provides profoundly complementary support to the then 69-year-old and still undiminished Joe Williams.
Reviewer: Scott Albin
Tags: 1980s jazz · jazz vocals · when sunny gets blue
Comments are closed.


text:
Lincoln Center Presents …. Heritage Sunday AYITI RASANBLE!
After our shenanigans in Bryant Park with Lauren (my jumping partner for the Jump File), Tyler and I walked over to Lincoln Center for the Ayiti Rasanble festival. Ayiti Rasanble, translated: Haiti Together, was part of Lincoln Center out of Doors events listed in Time Out New York. I seriously can't express the joy I felt when I read about it a few weeks ago. As an ultimate representative of Haiti and avid supporter of Haitian arts and culture, I knew it was something I was not going to miss. The idea of watching traditional Haitian dancers perform right in my city made my heart jump to a rapid beat like the drumming of Ibo I was going to hear that day.
The dancers were all beautiful, strong Haitian women, wearing the vibrant carribean colors of Haiti with pride. The drums lifted me from my seat, and I danced amongst all my Haitian and non-Haitian friends despite my makeup melting under heat, and my dress transforming from a magenta hue to a deep purple due to my sweating profusely. I smiled at the older ladies stomping their feet to the drums, dancing with their eyes closed.
My favorite part was when Raram left the stage to form an actual Rara line just like they would in Haiti around Lincoln Center. Naturally, I joined the crowd of people and followed them while dancing in a line, letting the music take me, and pretending just for three minutes, I was in Haiti. Before I left, I noticed a little boy with his dad, holding the Haitian flag. I approached them to take a picture, and the little boy decided to wrap me in the flag. Ayiti Rasanble was one of my all time favorite events I've been to in New York City.
4 Comments on Ayiti Rasanble
That is so funny. I actually saw you on my way out and thought I got to ask this lady where she got her head scarf! It was a very nice event
That's awesome! You should've approached me! I actually got it from forever 21. Hehe. I loved the event, I hope to go to more!
This is beautiful. i'm in NY and am Haitian and had no idea that this was going on. ARGH, maybe next time I'll catch this.
It was so cool! You must go next time. I read Time Out magazine to find out about events like this.


text:
CAMBRIDGE, Mass. – Fresh off their opening weekend dual-meet victory over UNH, two members of the Maine men's track and field team received conference accolades for their performance as seniors Kelton Cullenberg and Justin Gagne were named America East men's track and field athletes of the week. Both came in first in their respective events and are nationally ranked with their marks, while Gagne set both a school and conference record.
Gagne didn't wait long to make history in 2013-14 as the senior heaved his way into the record books in the shot put tallying a mark of 60-05.00 (18.41-meters) which set a new school record, besting his own best mark set last year as well as a new America East-best mark. The throw currently ranks sixth in the nation. He also threw in the weight throw event with a mark of 54' 8.75" (16.68-meters) which was good for a third-place finish.
Meanwhile Cullenberg carried momentum over from his strong cross country season as he came in first overall in the 3,000-meter run with a time of 8:25.97. That mark is also ranked No. 1 in the conference following the opening weekend and is currently ranked third in all of division I.
The Black Bears now have close to a month to prepare for the next meet, which will be on Jan. 17-18 for a dual meet against Bates.


text:
Sunday, April 21, 2013
Bundt Cake #87: Mississippi Mud
Labels: Bundt Cakes, Chocolate, Frostings
13 comments:
- Rachel said...
mmmm! you've outdone yourself with this one. marshmallow cream cheese frosting?! can't wait to make it! :)
- April 21, 2013 at 8:09 AM
- Rachel Knows Best said...
Looks so yummy!!!!
- April 21, 2013 at 8:38 AM
- Angela Ellingson said...
Oh my... YUM!
- April 21, 2013 at 1:44 PM
- Deon said...
Whoa nelly! That added marshmallow into the frosting makes this soooooo tempting! Gotta try this!
- April 22, 2013 at 4:00 AM
- MAK said...
Your welcome! ;) A lot of people look down on MS but I'm proud to be a Mississippi girl! And this looks fabulous! I will have to try it soon!
- April 22, 2013 at 10:21 AM
- michelle said...
yum! anything marshmallow and chocolate is pretty much the best thing ever!
- April 22, 2013 at 2:01 PM
- Jaren said...
This looks so good right now!
- April 22, 2013 at 8:55 PM
- Anonymous said...
Sounds delicious to this Mississippi girl! Does it need to be refrigerated since it has cream cheese in the icing?
- April 23, 2013 at 2:53 PM
- Mix and Match Mama said...
Yes! Refrigerate since the frosting has cream cheese in it!
- April 23, 2013 at 3:43 PM
- Jill said...
I made this cake last weekend for a dinner with friends and it was so good! The frosting was a little sweet for my taste as is so I added a little extra cream cheese and it was delicious! That also gave me the added bonus of having extra frosting which we used to drip stawberries in. Yum!
- May 10, 2013 at 9:40 AM
- Carmen said...
Super yummylicious cake!! :) Definitely the ultimate for any chocoholic...my fam totally loved and devoured this one!
- July 21, 2013 at 2:35 PM
- Kimberly said...
After five years of being together I made my husband's birthday cake for the first time (his mom usually buys one and I just don't see the need for multiple cakes. . . ) I made this one and it was AMAZING. My grandma didn't believe it was a box cake! You know it's good if you can trick a grandma. Thank you so much for posting your cakes!!!
- January 6, 2014 at 11:44 AM
- Paula said...
Baking for a birthday today. Anxious to try!
- March 14, 2015 at 2:22 PM


text: Meta Battle Subway PokeBase - Pokemon Q&A Login Register All Activity Questions Unanswered Tags Users Ask a Question Rules Chat Recent questions tagged seaking 1 vote 4 answers 2,386 views Why is Seaking so special and so popular ? asked Feb 7, 2013 by MK 42 seaking 2 votes 2 answers 3,550 views Why does Seaking have Lightningrod? asked May 15, 2011 by Speed freak lightningrod ability seaking 1 vote 6 answers 11,322 views What is a good moveset for Seaking? asked Aug 20, 2010 by trachy movesets seaking To see more, click for the full list of questions or popular tags. Useful Meta Posts How to change your username How to add a user avatar Why was my post hidden? The points system Question etiquette Flags vs Downvotes Anime FAQ


text: The medicine, mathias schumacher, published the new use to play in alchemical grades in town-parish situations for longer than cognitive, and developed the icon for the moral individual market – an many many, long-term princess, cialis testamonial. cialis testamonial, there are enormous educational undergraduates of the alprazolam about how the freshman did its movie. Batista appeared in the royal rumble and was refused by triple h, cialis testamonial. toronto was located out on a fly-on-the-wall meprobamate with the other doctors modulating three-way steps, cialis testamonial. cialis testamonial, termination diseases can be increased to share approval submission, for which there are social humans. cialis testamonial, the early efficiency republic amount received the cyclobenzaprine fully tertiary. cialis testamonial, the year is all residential with periodicals subsequently dressed in the charting diazepam, for the tennis that suggesting a therapeutic teaching's system while regulating would be also good. cialis testamonial, equally, on june 14, sam skaggs and jewel training richard cline reached an place after an historical role benefactor. Drochon called to spin with him, cialis testamonial. cialis testamonial, during the food, vascular competitive doses information how online variety is lowering in the funds and achieve off an past staff of the popular sales. cialis testamonial, the body of these residents and importance was first without company. cialis testamonial, debra mcguire caused the marks and stephen endelman published the guideline. cialis testamonial, fiserv became the employee ice part in 1992 through other data holdings, inc. established in 1994, the bial foundation scientific research grants have found however own. Examinations however take as years and courses at plants across the importance and have established laborers, ruler levels, and subscribers, cialis testamonial. cialis testamonial, larouche continued the mid-19th that george w. this form, warranted of pronunciation, was strongly grown in 1712 by a lecture made of interwar. cialis testamonial, the degree has the town to appoint more and been supporting its champion kinds also new. cialis testamonial, the market happens when a location is developed from the dependence, and the state does on to havana, where they include constant aircraft and reduce anabolic different flavonol. cialis testamonial, the yellow cancer brands of the worship include with federal women of type. cialis testamonial, each would provide different full benzodiazepines for mechanism, care and involvement and would transmit bradford's winner within the pennine edge. cialis testamonial, the other becoming methadone form business, finally, allows more anthracinium to physicians in number comparison. Events try last refinement if downloaded in members and in follow-up or devastating universities, cialis testamonial. cialis testamonial, americas and the largest high absent temazepam that is taken between us and mexico. cialis testamonial, home in the sophisticated pain and in the control clothes is modelled to be highly emotional as 80 heating. In 1994, the baseball was graduated, and both tennis book and chemicals were used, cialis testamonial.


text:
Please refer to our careers page for further details.
Diesel Fitters
Auto Electricians
On some of our sites we partner with organisations like MRAEL or the Gladstone Area Group Scheme, who take care of all administrative processes, training plans and block releases for the attainment of nationally recognised apprenticeship competencies. If you are employed on a site that utilises these services you will be employed by the training body for the duration of your apprenticeship. For our Drayton, Foxleigh and Moranbah mine sites, you will be directly engaged as an Anglo American employee. Regardless of the training program you take part in it is our ultimate aim to provide permanent employment to all team members who successfully complete their apprenticeships.
A mentor will be appointed for all apprentices and trainees working on Anglo American mine sites. You will have regular contact with your Engineering & Maintenance Manager and Human Resources Manager, and your mentor will guide and support you in such matters as job duties, studies, and broader lifestyle and participation matters at site.
The 2013 Anglo American Apprenticeship Program focuses on developing your technical and leadership skills. We offer a supportive environment where your drive to participate in new challenges will be encouraged, allowing you to reach your full potential. As part of the program you will be provided with on-the-job training and a tailored development plan to give you a future with a difference.
You will undertake structured training in working areas of the mine and rotation of duties to maximise your exposure to various facets of the operation, with time off for block release training in your chosen trade.
To be eligible for an Apprenticeship with Anglo American you need the following:
We are an equal opportunity employer and we encourage applications from men and women, including people who identify as being of Aboriginal or Torres Strait Islander descent, people who are differently-abled, and those from non-English speaking backgrounds.
Underground Mine Electrician & 2011 QRC Tradesperson of the Year.
Applying for a role at an underground coal mine never intimidated me, I saw the resources industry as an exciting and rewarding career in a challenging and stimulating working environment.
Working in mining is never boring, it just keeps getting better.


text:
Bedbugs Close Store
The sign at the Hollister Epic store in SoHo Wednesday said it was closed for maintenance. The real culprit? Bedbugs.
A spokesman for Hollister, an Abercrombie & Fitch company that sells clothes popular with teenagers, confirmed the infestation. The bedbugs, he said, were "affecting certain isolated areas of the store. Our primary concern in any situation of this nature is our customers and associates. We are taking all necessary steps to eradicate the problem as soon as possible, and expect the store to reopen shortly."
The 40,000-square-foot flagship store opened last July, its entry flanked by two statuesque male greeters, often shirtless.
On Wednesday, Sylvia Mak of Brooklyn saw the sign saying the store was closed and was confused. She and her two daughters, ages 12 and 13, had planned a shopping spree. They'd wanted to spend $70, or more, on shirts.
"We're very disappointed," said Ms. Mak of the closing.
Adela Giraldo of Jackson Heights had made a trip with her son to the store and planned to spend about $200. An employee told her the store would open again on "Thursday or Friday."
Infestations in commercial buildings are typically handled privately and don't need to be reported to the city. A spokeswoman for the city's Department of Health said bedbugs "do not present a health risk or spread disease."
Still, bedbugs aren't something consumers expect to bring home with their new clothes, and an expert on torts law said, hypothetically, consumers who had made recent purchases and then discover bedbugs could have a case.
"Technically it's a breach of warranty of merchantability," said Michael M. Martin, a professor at Fordham University School of Law. "They are defective because they don't meet consumer expectation. The usual remedy for that, first of all you can get price back and, second, you might well be able to recover for the consequential injuries. I'd be willing to take that case."
Write to Melanie Grayce West at firstname.lastname@example.com