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A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.
1. A method for fabricating surface mountable integrated circuits comprising the steps of:
providing a device wafer of monocrystalline silicon material with first and second surfaces and with integrated circuits formed on the first surface of said device wafer;
forming an oxide layer between the second surface of the device wafer and a handle wafer, said oxide layer bonding the handle wafer to the device wafer for supporting the device wafer;
forming a via in the device wafer, said via comprising a first open end on the first surface of the device wafer, an elongated passage extending from said open end a controlled depth into the handle wafer and terminating at a second end closed by said handle wafer;
depositing a conductive material in the via over the elongated surface and the closed end of the via;
removing the handle wafer to expose the conductive material coated on the via surface.
2. The method of claim 1 wherein the handle wafer is removed to expose a surface of said oxide bonding layer and the conductive material of the second end of the via extends beyond the surface of the oxide bonding layer.
3. The method of claim 1 wherein the conductive material deposited over the surface of the via comprises a metal deposited on the via surface.
4. The method of claim 3 wherein the metal comprises a first layer of a barrier metal and a second layer of an adhesion metal deposited on the barrier metal.
5. The method of claim 4 wherein the barrier metal is one metal selected from the group consisting of titanium nitride, copper, lead, platinum, and nickel and the adhesion metal is another metal selected from the group consisting of titanium nitride, chromium, titanium, and titanium tungsten.
6. The method of claim 4 further comprising the step of filling the via with polysilicon.
7. The method of claim 6 further comprising the step of planarizing the layers of adhesion metal, barrier metal and polysilicon.
8. The method of claim 1 wherein the step of depositing a conductive material comprises the steps of depositing a layer of titanium nitride, depositing a layer of tungsten on the layer of titanium nitride, and depositing a layer of polysilicon over the titanium nitride to fill the via, and planarizing the layers of titanium nitride, tungsten, and polysilicon.
9. The method of claim 1 further comprising the step of dielectrically isolating the surface of the via from the monocrystalline silicon material before depositing the conductive material.
10. The method of claim 9 further comprising the step of depositing a dielectric material on the surface of the via.
11. The method of claim 10 wherein the deposited dielectric is one selected from the group consisting of silicon dioxide, silicon nitride, and diamond.
12. The method of claim 9 further comprising the step of forming a dielectric layer on the surface of the via.
13. The method of claim 12 wherein the monocrystalline silicon material in the via is oxidized to form a dielectric layer on the surface of the via.
14. The method of claim 1 wherein the via is filled to the first surface with a conductive material.
15. The method of claim 1 comprising the further steps of:
filling the via with photoresist;
developing a portion of the photoresist extending a controlled depth from the first surface of the wafer;
removing the developed portion of resist from the end of the via between the first surface and the controlled depth;
filling the via with a conductive material between the first surface and the controlled depth.
16. The method of claim 1 comprising the further steps of:
depositing a metal contact layer on the surface of the wafer;
patterning the metal contact layer to provide conductive paths between the integrated circuit and the vias.
17. The method of claim 1 wherein the exposed conductive material of the via is silicided.
This application is related to application Ser. Nos. 08/462,171, 08/461,643, 08/461,037, 08/463,388, and 08/462,876, all filed Jun. 5, 1995 and assigned to Harris Corporation.
Integrated circuits are formed upon semiconductor substrates known as wafers. A wafer holds a number of identical integrated circuits, each circuit being a die that is spaced from other identical circuits. Dies are separated from the wafer usually by a dicing operation. In the dicing operation wafers are mounted on an adhesive film and the wafer is placed in a diamond saw apparatus. The diamond saw apparatus cuts the wafer to separate the dies from each other.
After separation from the wafer individual die are ready for packaging or for otherwise connecting one die to another to form a desired system or device. To package the die, each die is removed from the adhesive substrate and placed on a lead frame. A lead frame includes a plurality of finger-like connections that extend from the periphery of the lead frame toward a center die pad. The die is mounted on the center die pad. Next, wire bonds are formed between bond pads on the die and the lead fingers of the lead frame. Thereafter, the individual die are encapsulated in plastic during a molding operation. As an alternative, the lead frame with the attached die may be mounted in a ceramic package which is then hermetically sealed. Still another alternative is to directly mount the die onto a printed circuit board that contain other die which are interconnected to form an electronic system, such as a computer.
One technique for surface mounting dies on printed circuit boards uses a solder-bump interconnection. With that technique, the bond pads of the die have solder bumps or other wettable metal terminals deposited on the bond pads of the die. The die is mounted face side down onto a printed circuit board where the solder bumps of the die are aligned to electrical contacts on the board. In a typical application, the electrical contacts are metal lands that are recessed between raised glass walls. The solder-bump forms a collapsible wall of solder. The glass dam material helps retain the solder when the solder is heated.
Such surface mountable techniques can be used without packaging the die in protective plastic or ceramic encapsulating material. As such, surface mountable techniques reduce the number of steps in fabrication of electronic systems such as computers. However, one of the drawbacks with current surface mountable techniques is that the printed circuit board receives only a single layer of die.
Accordingly, there is a need for a surface mountable technique with higher die density and multiple layers of die. In particular, there is a need for surface mounted technique and surface mounted devices which are stackable, one on top of the other. There is a need for a surface mounted technique and surface mounted apparatus where one die may be directly connected to another die using contacts on both the front and back surface of each die.
The invention provides a surface mountable integrated circuit and a method for fabricating surface mountable integrated circuits and for interconnecting surface mountable integrated circuits. The method of fabrication begins with a wafer of semiconductor material having first and second surfaces. Integrated circuits are formed in the first surface of the wafer. Vias are formed in the wafer. The vias extend from an open end adjacent the first surface into the wafer. The vias terminate at a second, closed end that is a controlled distance from the second surface of the wafer. The via is filled with a conductive material. The second surface of the wafer is removed to expose the filling of the via above the reduced second surface.
The side walls of the via are coated with an insulating or dielectric material. A layer of metal is deposited on top of the insulating or dielectric material. The metal may be deposited in two layers. A first layer is a barrier layer that will prevent migration of material into the via. A second or adhesion metal is deposited on the barrier metal. The adhesion metal sticks to both the barrier metal and to a third metal that fills the via. The third metal may be selectively deposited tungsten.
As such, the invention provides for an integrated circuit die made of semiconductor material. The die has first and second surfaces that are separated from each other by the body of semiconductor material. A conductive via extends from one end at the first surface of the die to its second end that is a controlled distance from the second surface of the die. The via has a layer of insulating or dielectric material on the wall of the via that is formed by the semiconductor material. The via is filled with a conductive material. The conductive material may be either metal or polysilicon. The via may extend a predetermined or controlled length beyond the second surface of the die. As an alternative, the conductive material may terminate inside the via a controlled depth beneath the second surface of the die. Thus, the surface mountable integrated circuit of the invention provides for conductive vias in the form of prongs which extend from the second or back surface of the die as well as conductive vias in the form of receptacles where the conductive material is disposed a predetermined distance from the second surface of the die. When the receptacle form of the invention is employed, the conductive material in the via may be suitably formed to receive a corresponding prong from another die or substrate. In this way, dies may be interconnected with each other or may be mounted on PC boards with suitable prongs or receptacles, as the case may be. So, a via may include a prong, a receptacle, or both, with the prong at one end of the via and the receptacle at the other end of the via.
The conductive material in the vias may be metal or may be polysilicon. The conductive vias of the invention may also be formed in a single, bulk wafer of silicon. As an alternative, the conductive vias may be formed in a bonded wafer that includes a device wafer bonded to a handle wafer by a suitable bonding layer such as a bonding oxide layer.
With the claimed invention it is also possible to form a coaxial connector directly on an integrated circuit. One advantage of a coaxial connector is that a signal provided to the integrated circuit is shielded to prevent noise from degrading the signal. With the coaxial connector of the invention, a first conductive via is formed in a die. A second, annular conductive via is formed around the central via and encircles or otherwise encloses it. A ring of semiconductor material separates the outer conductive via from the inner conductive via. The walls of the two vias are suitably insulated from the semiconductor material. The vias are held in place by the adhesion between the metal, the insulating material, and the semiconductor material.
The coaxial or shielded version of the invention is not limited to the annular embodiment. The noise prevention feature of the invention may also be implemented using a wall disposed across a predetermined boundary of the die. Thus, a wall can be constructed across a die that includes both digital and analog circuitry. The wall, filled with metal, can have the metal in the wall attached to a suitable ground. As such, analog signals on one side of the wall are shielded from digital signals on the other side of the wall.
The invention also provides a die and a method of fabricating a die with edge connectors. The edge connected surface mountable die has a number of fingers formed in the outside edges of the die. These fingers are separated from the body of the semiconductor material of the die by an insulating layer, typically silicon dioxide. Such edge connectors are formed by etching a stringer region enclosing the die on the wafer. The stringer region has a plurality of fingers that extend from the stringer region inward toward the integrated circuit. The stringer region is formed adjacent to the scribe region that separates one die from another. The stringer region and its fingers are formed of metal. The metal is deposited by suitable pattern operation and extends from the first or top surface of the integrated circuit to a predetermined or controlled depth with respect to the second surface of the die or wafer. The stringer is an intermediate structure which, after the fingers are suitably formed, can be removed. The fingers are then coated with solder which can be reflowed to establish an edge connection on a surface mountable printed circuit board or other surface mountable substrate.
The technique can also be used to provide vias with optical as well as electrical connections and combinations thereof. Thus, in a three die stacked connection the first die has an optical transmitter aligned with an optical via in the die above it which in turn is aligned with an optical receiver in the third die. The three dies may have other electrical vias connecting the first to the second, the second to the third and the first to the second and third.
In still another embodiment of the invention using stacked dies, a center die of a stack is provided with cooling vias disposed transverse to the electrical or optical vias. The cooling vias have passages that carry a cooling fluid to remove heat. Heat is removed from die stacked on opposite surfaces of the cooling die. Heat conductivity to the cooling die is increased by providing thermal conductive material between the cooling die and the circuit dies on either side.
FIGS. 1A to 1K illustrate section views of an integrated circuit die processed according to a first embodiment of the invention.
FIGS. 2A to 2D show section views of an integrated circuit die processed according to a second embodiment of the invention.
FIG. 3 illustrates a section view of a third embodiment of the invention where a plurality of through vias are filled with metal which extends from the backside of the integrated circuit die.
FIGS. 4A to 4F show section views of an integrated circuit die processed according to a fourth embodiment of the invention.
FIG. 4G illustrates in perspective view an integrated circuit die which has a plurality of receptacles formed on its back surface. Also shown is a substrate with a plurality of interconnect pins which are spaced so as to plug into corresponding receptacles on the integrated circuit die.
FIGS. 4H and 4I show section views of two processing variants to the fourth embodiment. These section views correspond roughly to FIG. 4B.
FIGS. 4J to 4N show section views of a seventh embodiment of the invention.
FIG. 4P illustrates a section view of a variation of the seventh embodiment of the invention.
FIG. 5 shows a section view of an eighth embodiment of the invention where multiple integrated circuit die are interconnected by stacking one die upon the next. Both electrical and optical interconnections are shown.
FIG. 6 illustrates a section view of a ninth embodiment of the invention in which a interposer is provided to furnish the contact metalization for the conductive through vias.
FIG. 7 illustrates a section view of a tenth embodiment of the invention in which a very thin integrated circuit die is stabilized and held rigid by a supportive layer applied to the frontside of the die.
FIGS. 8A and 8B show section and plan views, respectively, of an eleventh embodiment of the invention.
FIG. 9A shows a section view of a prior art multilayer ceramic package.
FIG. 9B shows a section view of a twelfth embodiment of the invention.
FIG. 9C illustrates a section view of a further embodiment of the stacked die illustrated in FIG. 4P and FIG. 5.
FIGS. 10A to 10K are a combination of section and plan views of integrated circuit dies illustrating a fourteenth embodiment of the invention where die edge connections are fabricated.
FIGS. 10L and 10M are section views showing alternative processing steps for the fourteenth embodiment.
FIG. 10N shows a perspective view of two dies fabricated in accordance with the fourteenth embodiment. The dies are connected to a substrate along three edges and connected to each other along the fourth edge.
FIG. 10P and 10Q show perspective views of dies fabricated in accordance with the fourteenth embodiment which are mounted to a substrate in a perpendicular direction.
With reference to FIG. 1A, there is shown a bonded wafer 110 having a device wafer 111 bonded to a handle wafer 116 by a bonding layer 115. In a preferred embodiment, the device wafer 111 is a wafer of monocrystalline silicon, the handle wafer is also made of silicon, and the bonding layer 115 is a layer of silicon dioxide. The device wafer 111 has one or more integrated circuit regions 119 formed in a first or upper surface 112. A second surface 113 is spaced from the first surface 112 by the thickness of the device wafer 111, which may range from several 1000 Å to 10 mils or greater in thickness. The handle wafer 116 has a first handle surface 117 that faces the oxide bonding layer 115 and the second surface 113 of the device wafer 111. The second surface 118 of handle wafer 116 is spaced from the first surface 117 by the thickness of the handle wafer 116. The integrated circuit regions 119 are completed in so far as they are passivated with a surface oxide layer 114. In a preferred embodiment, integrated circuit devices are not yet interconnected with a metalization layer. A layer of photoresist 120 is uniformly deposited over the oxide layer 114.
Turning to FIG. 1B, the photoresist layer 120 is patterned to define via openings 130. After the photoresist is removed from the via area 130, the via 130 is suitably etched by using a plasma etch with a CF4 or CHF3 +O2 chemistry, for example, to remove the exposed portion of the oxide layer 114 and a plasma etch with a NF3, HBr/Cl or SF6 chemistry, for example, to remove the silicon in the device wafer 111. The via 130 extends to or through the bond oxide layer 115 by again using an oxide plasma etch process, if necessary. The via 130 has a first end 132 that is open on the first surface 112 of the device wafer 111. The via has the side wall 131 that defines the length of its opening and has a second end 132. The second end 132 of the via 130 terminates at a predetermined distance from the second surface 118 of the handle wafer 116.
As a next step shown in FIGS. 1C, the photoresist 120 is stripped and the side wall 131 and second end 132 of via 130 is deposited with the oxide layer 134. The oxide 134 can be thermally grown, provided that the integrated circuit devices are not adversely affected by the additional high temperature processing, or deposited at low temperature using chemical vapor deposition (CVD). A barrier metal 135 is then deposited on top of the oxide layer 134. In the preferred embodiment barrier metal 135 comprises titanium nitride (TIN) deposited using CVD to a thickness in the range of 100 to 1000 Å. It may also be possible to deposit other barrier metals such as Cu, Pd, Pt or Ni using sputtering or evaporation provided the deposition method is capable of coating inside the via 130. This is an reasonable option for shallow (several microns) trenches with aspect ratios (trench depth/trench width) of approximately 1 or less. If a barrier metal other than TiN is utilized, an adhesion layer 136 (see FIG. 1D) may also be needed. Typical adhesion metals include chromium, titanium and titanium tungsten. The adhesion layer 136 is deposited using sputtering or evaporation within the same constraints as previously discussed for barrier metals other than TiN. Both barrier and adhesion metals are deposited to a thickness of approximately 1000 Å. In the preferred embodiment, a single layer of TiN functions as both a barrier metal and adhesion layer.
The deposition of barrier metal 135 and optional adhesion layer 136 is followed by a step (see FIGS. 1D) in which photoresist 140 is uniformly deposited on the surface of the device wafer 111 and fills all of the vias 130. The purpose of the photoresist 140 in the via 130 is to protect the adhesion metal 135 and optional barrier metal 136 in the bottom of the via 130. In the preferred embodiment, the photoresist is a positive resist so that exposure to ultraviolet radiation will soften the resist. The resist 140 is exposed to enough ultraviolet radiation to soften the resist to a predetermined depth D below the first surface 112 of the device wafer 111. The softened photoresist 141 is then removed using a development process, and barrier metal 135 and optional adhesion layer 136 are etched leaving only those portions that are protected by the undeveloped photoresist 142 in the vias 130. The TiN barrier/adhesion layer is etched using a wet etch of dilute hydrofluoric acid or a dry etch using SF6 or NF3 chemistry. As shown in FIG. 1E, the undeveloped photoresist 142 fills the lower portion of the via 130. The photoresist 142 is then removed from via 130 and selectively deposited metal 137, e.g. tungsten, fills via 130 as shown in FIG. 1F. The metal layer 137 is deposited to the surface of the oxide 114.
An alternate processing sequence for the via refill is shown in FIGS. 1G to 1I. This sequence could be used where the via width is wider than can be reasonably filled using a single selective deposition of metal 137 as shown in FIG. 1F and where the via has a high aspect ratio; i.e. depth: width is greater than 10:1. For example, selective deposition of tungsten is useful up to about 1 micron of deposited thickness. Thicknesses greater than 1 micron are prohibited by excessive film stress and the growth of tungsten in non-selective areas. This effectively limits the above described via refill process to vias of width less than about 3 microns, depending on the thickness of sidewall oxide 134 and barrier/adhesion metals 135, 136 respectively. For vias wider than 3 microns, an alternative refill process starts with the etched via 130 with sidewall oxide 134 as previously described, FIG. 1G. A barrier/adhesion metal 135 and metal 137 are then deposited using CVD. In the preferred embodiment, the barrier/adhesion metal 135 is titanium nitride (TIN) deposited to a thickness in the range of 100 to 1000 Å, and the metal 137 is tungsten deposited to a thickness of approximately 1 micron. A planarizing layer 138, preferably LPCVD polysilicon, is then deposited, completely filling the via, FIG. 1H. The final step uses chemical/mechanical planarization (CMP) to remove surface regions of metals 135, 137 and planarizing layer 138 stopping on the oxide 134 so as to neatly refill the via 130, as shown in FIG. 1I.
In a following step of the process which is applicable to vias refilled with either of the methods previously described, contacts to devices in the integrated circuit regions 119 are etched (not shown) This is followed by the deposition and patterning of a first metal interconnect layer 150 over the circuit area 119 and the via 139, as shown in FIG. 1J. The first metal interconnect layer 150 connects the tungsten 137 in the via 130 to an input/output terminal (not shown) of the circuit area 119. Above the first metal layer 150 is an interlevel dielectric layer 151, typically either a deposited oxide or a nitride layer. The interlevel dielectric layer 151 separates the first metal interconnect layer 150 from a second metal interconnect layer 152. Both interconnect metal layers 150, 152 serve in the normal fashion of connecting devices in the circuit region 119. After the deposition and patterning of the second metal layer 152, a passivating layer 153 is applied. Openings 154 in layer 153 may be etched which overlie metal layer 152. The openings 154 are analogous to bondpad regions of integrated circuits. Passivating layer 154 provides scratch resistance and durability for the metalization layers 150, 152, and may be formed from a deposited dielectric such as silicon dioxide or silicon nitride (or combinations thereof). Other passivating layers can include polyamide and spin-on glass (SOG).
As a next step in the process, the handle wafer 116 is removed by etching the handle wafer 116 with KOH or other suitable silicon etchant. For thick handle wafers, mechanical removal techniques, such as polishing or abrasion, may be employed prior to application of the wet etchant. By removing the handle wafer 116, a portion 139 of the via 130 extends beyond the bonding layer 115 as shown in FIG. 1K. The outer surface of the exposed portion 139 of the via will include a portion of the side wall oxide 134 which encloses a barrier metal 135. The side wall oxide layer 134 is removed by an oxide etch to expose the barrier metal 135. The side wall oxide 134 and a portion of the bond oxide 115 are removed by hydrofluoric etch. Once the barrier metal 135 is exposed, it may be coated with a suitable contact metal. Suitable contact metals include gold, aluminum and copper aluminum alloys. In one embodiment the exposed portion 139 of the filled via 130 is coated with a gold bump using electroless plating. The die on the device wafer 111 can then be separated in normal fashion by a diamond saw. Then, the separated die can be mounted right side up on multi-chip modules or on lead frames or any other suitable carrier device.
The first embodiment of the invention also has a number of variations. For example, the upper surface of each die may be coated with a polyamide or spin-on-glass (SOG) after the wafer is electrically probed and the good die are identified. Such a coating makes the die more durable for further handling after testing and for surface mounting of the die. In another variation, the region above the second metal interconnect layer 152 that is electrically in contact with the via 130 may be formed as a bond pad and may be open so that other die may be stacked on top of via 130 providing a via connection from one die to the next. Such a stackable type device is particularly useful for components such as dynamic random access memories. It is common that DRAMS are often assembled into modules comprising a plurality of identical DRAMS in order to provide a memory module for a system. So, for example, to add an additional one megabyte of memory where each word in memory comprises eight bits, it is common to assemble eight identical one megabyte memory chips together in a one megabyte memory module. Such memory modules are generally assembled on PC boards with one DRAM next to the other in a linear array on the PC board. With the invention, the DRAMS may be stacked one on top of the other and suitably interconnected to provide a one megabyte memory module.
It is a further feature of the invention that the height of the portion 139 of the via above the bond oxide layer 115 can be controlled to define the chip height between stacked chips. The latter facilitates cleaning of fluxes that are used during an attaching process.
With reference to FIG. 2A, there is shown a bulk wafer 210 having a first surface 211 spaced from a second surface 212 by the thickness of the bulk wafer 210. In the bulk wafer 210 there is formed a via 215. The via 215 has a first end 218 open on the first surface 211 of the bulk wafer 210. A second end 219 of via 215 is disposed a predetermined or controlled distance from the second surface 212 of bulk wafer 210. The walls of the via 215 are coated with a side wall oxide 216. The via itself 215 is formed in a manner similar to the formation of the via 130 as explained in the prior discussion of the first embodiment of the invention. To that end, the first surface 211 of bulk wafer 210 is coated with a uniform layer of photoresist (not shown). The photoresist is patterned to define the first end opening 218 of the via 215. The silicon wafer 210 is suitably etched using the remaining photoresist as a mask to remove semiconductor material down to the second end 219 of the via 215. After removal of the photoresist mask, a side wall oxide 216 is formed by thermal oxidation or deposition or some combination thereof. The via 215 is then filled with conductive materials such as N type doped polysilicon 217.
Turning to FIG. 2B, further processing steps known to those skilled in the art are used to form circuit area 214 in the first surface 211 of bulk wafer 210. Such integrated circuits may also be formed in an epitaxial layer of silicon grown on the top of the wafer 210. The circuit area 214 is formed proximate to the via 215. As part of the circuit area formation process, insulation layer 201 is formed over circuit area 214 and via 215 and contacts 202 to device regions (not shown) and vias are made. Subsequent steps form layers of first and second metal 225, 226, respectively. The first and second levels of metal are separated by an interlevel dielectric layer 227, such layer comprising silicon dioxide, for example. A passivation layer 228 covers the first and second metal layers 225, 226. As shown in FIG. 2B, the first level metal layer 225 contacts the polysilicon 217 that fills the via 215 at contact region 202. A portion of the circuit area 214 (not shown) is contacted by the first level metal layer 225 and is generally an input/output terminal (also not shown).
As a next step shown in FIG. 2C, the second surface 212 of the bulk wafer 210 is etched by a suitable etchant, such as KOH. This etching removes enough of the bulk silicon away from the second surface 212 in order to expose the side wall oxide 216 that fills the second end 219 of the via 215. The new second surface 212' is then coated with a deposited oxide 220. The deposited oxide 220 is of uniform thickness and passivates the new second surface 212' of the bulk wafer 210. Turning to FIG. 2D, the side wall oxide 216 in the bottom of the via 215 and a portion of the deposited oxide 220 are removed from the second end 219 of the via 215 by a process such as `backtouching` which uses mechanical polishing to expose the polysilicon 216. Next, barrier and adhesion metal layer 213 is deposited over the exposed portion of the via, including the exposed end of the polysilicon material 217. On top of the barrier and adhesion metals layer 213 there is deposited either a gold or a solder bump 222. The gold or solder bump 222 is generally deposited through a photoresist mask (not shown). After deposition of the gold or solder bump 222, the barrier and adhesion metal layer 213 overlying the backside passivation oxide layer 220 is removed resulting in the structure shown in FIG. 2D.
It should be noted that this second embodiment of the invention can also utilize a bonded wafer substrate rather than a bulk substrate. In a bonded wafer the via 215 extends past the bond oxide to form a structure analogous to that formed in the first embodiment.
One of the features of the invention is that the filled through via interconnect may be extended from the backside of the die in the form of lengths of metal of predetermined length which form connection pins. With reference to FIG. 3, there a wafer 230 has a plurality of vias 232a-e. Each via is filled with a metal 233. The via is coated with a sidewall oxide 235. The portions 237a-e of the metal 233 that extend beyond the backside oxide surface 231 to form a plurality of pins for connecting the wafer 230 into a socket (not shown) that has a plurality of receptacles for receiving the pins 237a-e. The metal 233 of each pin 237a-e is coupled to an interconnect metal layer 234 which in turn is coupled to a circuit area (not shown). A passivation or oxide layer 236 covers the topside metal interconnects 234. Pins 237a-e are about 4 mils in diameter and about 40 mils in length.
A fourth embodiment of the invention is illustrated in FIGS. 4A-4D. In the fourth embodiment of the invention, the vias are formed as receptacles for receiving metal contacts from either a PC board or from another die having extending pins, such as the pins 237 that extend from the bulk wafer 230 as shown in FIG. 3.
Turning now to FIGS. 4A-4D a device wafer 400 has a via 430 with a sidewall oxide 434 filled with polysilicon 440. Prior to forming first and second level metal layers 450, 452, the first end 431 of the polysilicon material 440 is silicided, forming silicide region 422. Passivation layer 453 is deposited over the first and second metal levels 450, 452. The handle wafer (not shown) is removed as discussed in connection with the first preferred embodiment. The bond oxide 415 and sidewall oxide 434 are etched with HF exposing the second end 432 of polysilicon 440 but leaving a residual portion of the bond oxide (this is facilitated by adjusting the sidewall 434 oxide thickness to be sufficiently thinner than the bond oxide 415 thickness), as shown in FIG. 4B. A silicon etchant removes the polysilicon material 440 from the via 430. The etch for example, KOH will stop on the silicide surface 422 that covers the first level metal 450 over the first end 431 of via 430.
After the KOH etch, as shown in FIG. 4C a suitable metal such as tungsten or aluminum is deposited via chemical vapor deposition in a uniform layer 444 over the bond oxide 415 and sidewall oxide 434. The CVD metal layer 444 is etched using a dry plasma etch to remove the CVD metal 444 from the bond oxide 115 and leave the CVD metal 444 coating the sidewall oxide 434 of the via 430 as shown in FIG. 4D. As such, the via 430 now provides a backside opening at its second end 432 for receiving a metal conductor. The metal conductor may be a pin on a printed circuit board or may be a pin such as pin 237a-e of another die. As an alternative to the plasma etching of CVD metal 444, a positive photoresist may be applied on top of CVD metal 444 filling the backside openings. Subsequent exposure to UV and developing processing removes the softened portion of the photoresist. The remaining photoresist acts to protect CVD metal 444 in the via during a wet etch step which removes unwanted CVD metal 444 overlying bond oxide 415 regions. The remaining CVD metal 444, as shown in FIG. 4E, may be reduced to a predetermined distance beneath the oxide layer 415. As a further alternative, the CVD metal layer may be patterned to provide a portion of CVD metal 445 overlapping the oxide layer 415 in a region surrounding the second end 432 of the via 430 as shown in FIG. 4F.
With reference to FIG. 4G a die 450 manufactured in accordance with the description of the fourth embodiment may be plugged into another die or substrate 452 manufactured in accordance with the description of the third embodiment. As such, the die 450 has receptacle vias with predetermined depths and conductive sidewalls. In a similar manner, the die 452 or corresponding circuit board has pins that are arranged to be insertable into and make electrical contact with the sidewalls of the vias in die 450. When the die 452 is inserted into the vias of die 450, the pins on die 452 provide an interference fit with the inside metal surface of the vias of the die on 450 resulting in a good electrical contact of the pin connections. Depending upon the materials used for the via pins and the via receptacles, it may be possible to remove and replace one or more defective dies 450, from the substrate 452. Those skilled in the art will also appreciate that one die may have both pins and receptacle vias and that one via may have a pin at one end and a receptacle at the other end of a via.
Further variants of the fourth embodiment are shown in FIGS. 4H and 4I. For simplicity, the dual level metal and passivating layers are not shown in these figures. If, prior to the first metalization layer 450 deposition and patterning, a thin oxide 460 is grown or deposited onto the polysilicon via refill, the oxide 460 will stop the subsequent KOH etch used to remove the polysilicon refill from via 430, FIG. 4H. Now, however, a short oxide etch is needed to remove oxide 460 prior to deposition of the CVD metal 444 so that good electrical contact is made from CVD metal 444 to first metalization layer 450. Care is taken during processing to make sure that the thickness of oxide layer 460 is less than the thickness of side wall oxide 434 and remaining portions of bond oxide 415. Another variant, shown in FIG. 4I utilizes a doped region 461 of the polysilicon refill which is not removed during the subsequent KOH etch of the polysilicon refill. The doped polysilicon 461 has a different selectivity with respect to an etchant than does undoped polysilicon. As such, the via 430 can be initially filled with undoped polysilicon. At the end of the filling process, dopant may be added to the process in order to change the etching characteristics of the polysilicon 461 in the via 430 at the first end 432.
The seventh embodiment of the invention is shown in FIGS. 4J-4N. In the seventh embodiment of the invention, a receptacle-type via is formed in a bulk wafer 310, FIG. 4J. The bulk wafer 310 has a top oxide layer 311 and a bottom oxide layer 312. A via 320 is formed through the top oxide layer 311 and the bulk wafer 310. The via 320 initially stops on the bottom oxide layer 312.
As shown in FIG. 4K, a following step includes the formation of a sidewall oxide layer 321 on the sidewalls 315 of via 320. Sidewall oxide 321 may be formed using a thermal oxidation process or a deposited oxide or a combination thereof. Next, a layer of polysilicon 322 is deposited by low pressure chemical vapor deposition. The polysilicon layer 322 is N+doped using POCl3 for doping the polysilicon material.
As a following step, a layer of photoresist 323 is deposited, UV exposed and developed resulting in a protective plug in the via 320. The photoresist 323 is a positive photoresist. As such, the photoresist layer is UV exposed to a controlled depth. The softened photoresist due to UV exposure is removed by a suitable development process. After removal of the UV exposed photoresist, the polysilicon layer 332 is removed by etching to leave a portion of the polysilicon layer 332 which is protected by the hardened photoresist 323 in the via 320, as shown in FIG. 4L. The hardened photoresist 323 remaining in the via 320 is removed and the wafer 310 is oxide bonded to a handle wafer 325. An oxide bonding layer 324 provides the bonding between the top oxide surface 311 and the handle wafer 325. An oxide layer 326 covers the other surface of the handle wafer 325, shown in FIG. 4M. As such, the last step provides receptacle vias in a bonded wafer. The bonded wafer is then suitably processed to provide integrated circuit regions (not shown) adjacent to the vias 320. The vias 320 are contacted by a first level of metal 327. The first metal 327 contacts the polysilicon layer 322 that covers the sidewalls of the via 320. An interlevel dielectric 328 and a second level metal 329 along with the passivation layer 336 cover the devices on bulk wafer 310. After suitable processing, the handle wafer 325 and the bonding oxide layer 324 are removed to provide a via 320 with one end 318 open on the second surface 317 of bulk wafer 310. The first surface 316 of bulk wafer 310 contains the integrated circuit devices (not shown).
During the above process, the polysilicon layer 322 is only minimally oxidized, and any surface oxidation of the polysilicon layer 322 is removed during the removal of the bonding oxide 324. The final structure is shown in FIG. 4N has receptacle type vias 320. The inside surface of the polysilicon 322 may be coated with suitable metal for improving electrical contact. The metal coating 331 may be either gold or nickel, applied by electroless plating, for example.
One variation of the seventh embodiment is shown in FIG. 4P. In this embodiment, there are shown multiple dice 335A, 335B, 335C, etc. stacked one on top of the other. Each die has a through via 320a, 320b, 320c formed by the process described above. However, in addition to the above process, the first end of the via is also open so that the vias 320A, 320B, 320C, etc. when stacked one on top of the other provide a through passage 332. The individual die 335A-335C are aligned so that the vias 320A-320C form the continuous through passage 332. The passage 332 may then be plated or otherwise filled with a conductive material which contacts the polysilicon 336 to provide interconnection between the dice 335A-335C.
In the illustrated example, the metal one and metal two layers 327, 329 as well as the interlevel dielectric layer 328 and the passivation layer 330 is removed from the first end 319 of the through via. Those skilled in the art will appreciate that the material that is removed may be either the polysilicon material or tungsten or other metal material. The passivation layer 330, interlevel dielectric layer 328, and first and second metal layers 327, 329 over the first ends 319 of the vias 320 are removed through suitable masking and etching. Once the vias 320 are aligned, the vias 320A-320C may be interconnected using electroless plating, flowing of conductive paint, threading of metal wires, or any other suitable interconnection mechanism.
With reference to FIG. 5, there is shown an alternative method for interconnecting a plurality of dice having vias extending through the die. In this technique, dice 341, 342, 343 are interconnected by electrically conductive vias 348 and an optically conductive via 344. The electrically conductive vias 348 are formed and interconnected in accordance with the above description of multiple via interconnections. The center die 342 is provided with a via 344 that is filled with an optically conductive material, such as fiber optic material. Via 344 may optionally be left untilled, providing an `air-filled` connection. The optically conductive via 344 is disposed opposite a photoreceiver 345 on die 343 opposite one end of via 344 and a phototransmitting device 346 opposite the other end of via 344 and disposed in die 341. Thus, light emitted by the optical transmitter 346, such as a laser or a light emitting diode, is conducted by the fiber optic material in optically conductive via 344 and coupled to the optical receiver 345, such as a photodiode or photosensor. As such, the above described embodiment of the invention, multiple dice 341-343 have vias 348 for electrically connecting the dies 341-343 as well as one or more optical vias 344 that interconnects the dies 341 and 343. Those skilled in the art will appreciate that further combinations of electrical and optical vias may be made apart from the particular example described above.
The conductive vias of the invention may also be used in combination with an interposer to provide a two-piece interconnection system for an integrated circuit. With reference to FIG. 6, there is shown a die 350 with a plurality of vias 351 having conductive fillings and/or conductive side walls that electrically couple one end of the via 352, such as a bond pad 352 to another end of the via 353 which includes a second, metal pad. The die 350 may be formed in accordance with one or more of the above disclosed embodiments of the invention. The die 350 are mounted onto a interposer 354. Each interposer 354 comprises a dielectric material 353 with contact metal inserts 355. The interposer 354 has several advantages. With the above described system, the metal pads 353 formed on the backside of the die 350 are easier to form and less expensive. In addition, the interposer 354 fills up the dead space beneath the die 350 and keeps the area free from fluxes used as cleaning agents that would normally be used in multi-chip module fabrication. The interposer material 354 may include dielectric material such as diamond which would conduct heat away from the die 350. In addition, it is noted that electroless plating could be used on the backside of die 350 so that a masking operation required to form the metal pads of 353 could be eliminated.
One of the features of the invention is the provision of vias in very thin die 360, i.e., die having a thickness of 10-40 microns. In this embodiment of the invention, the 10-40 micron thick device wafer is oxide bonded to a handle wafer. A trench etch is used to form the through vias through the device wafer and bond oxide, stopping on the handle wafer. However, prior to removal of the handle wafer, the device wafer receives an overcoat on its front side in order to stabilize and add rigidity. The overcoat layer 365 is shown in FIG. 7. For simplicity, features such as metalization layers, interlevel dielectrics, and passivation layers are not shown in FIG. 7. The overcoat 365 may comprise any suitable materials such as plastic, glass, polyamide, or even metal. After application of the overcoat 365, the handle wafer is removed to form the structure appearing in FIG. 7. There, the die 360 has a plurality of vias 363, each with a bond pad 364 on the backside surface of the die 360. Of course, those skilled in the art will see that the vias 363 may also be formed as receptacle vias as disclosed in connection with the above embodiments of the invention.
Another embodiment of the invention provides for coaxial connection and for shielding of a digital section of a die from an analog section. With reference to FIGS. 8A-8B, there is shown a device die 810 with a top oxide layer 811, bottom oxide layer 813 and inner via 816. The inner via 816 is filled with a conductive material 826. The conductive material 826 is separated from the adjoining annular die material 815 by a sidewall oxide 812. An outer, annular via 814 encloses the inner via 816. The outer via 814 is likewise filled with conductive material 824. The conductive material 824 is insulated from the adjoining device material by suitable sidewall oxide 812. An inner contact 817 carries a signal to the conductive material 826 of the inner via 816. An outer annular contact 818, generally coupled to ground, is also connected to the annular conductive material 824 that surrounds the inner material 826. Thus, the above described embodiment provides a coaxial connection with a cylindrical grounded metal conductor 824 surrounding a signal carrying central conductor 826. With the above embodiment, noise and induced electromagnetic fields resulting from changing signal levels in the inner conductor 826 are effectively shielded from the circuit areas that are formed in the die 810 outside the annular via 814. The metal filling the vias 814, 816 may be tungsten or other suitable material. While the outer annular vias shown in a circular configuration, those skilled in the art will appreciate that the outer annular via 814 may have any suitable geometric configuration so long as it encloses or otherwise electrically shields the inner via 816. Thus, the shape of the outer annular via 814 may be a square, a rectangular, a pentagon, or any other suitable shape.
To form the coaxial vias 814, 816 a single wafer or a bonded wafer may be used. If a single wafer is used the bottom of the wafer 810 is provided with an oxide layer 850. If a boned wafer is used, layer 850 may be the bond oxide layer on top of a handle wafer. The vias 814, 816 are etched a controlled distance into the wafer 810 and stop in the bottom oxide layer 813. At a suitable time a portion of the wafer 851 is removed to expose the second ends 853, 854 of the conductive vias on the second surface 855 of the wafer 810. The portion 850 would be a handle wafer in a bonded wafer embodiment.
The above coaxial feature may also be used to separate an entire analog section of a die from a digital section. With reference to FIG. 8B, there is shown a die 820 with a digital section 821 and an analog section 822. A wall 823 separates the digital section 821 from the analog section 822. The wall comprises a suitable via or trench that extends from the top surface of the die to the bottom surface of the die. The sidewalls of the trench are oxidized and the trench is filled with a suitable conductive material, preferably metal. The conductive material inside the wall 823 is connected via a suitable terminal to a ground connection and thereby provides a ground shield wall between the analog section 822 and the digital section 821.
With reference to FIG. 9A, there is shown a prior art ceramic package 910 with multiple layers 912-915 of co-fired ceramic and interconnects 931, 932. Signals on the packaged chip 920 are conducted via bond wires 921, 922 and interconnects 931, 932 to a ball grid array 916 disposed on the outside surface of the lowest layer 915. The package 910 has internal shoulders 918, 917 that support a lid 911.
With references to FIG. 9B, a package 950 using the invention could replace the multiple ceramic layers of package 910. In the package 950 a substrate 940 has an array of conductive vias 951 terminating in an external connection array 952 which may be flat or ball shaped like the array 916 of package 910. Individual through vias in the external connection array 952 are contacted by metalization layer 953, 954, 957, etc. and conductive vias 955, 956 to bondpads 963, 966 which are electrically connected to bondpads 964, 961 on the integrated circuit die 960 using bondwires 962, 965. While the FIG. 9B shows only a few layers of interconnect (957 and 966, for example), those skilled in the art will appreciate that additional interconnect and via layers may be used to route the through via connections 951 to the appropriate bondpad 966, for instance. As such, a package 950 including multiple interconnection layers of metalization, 957, 966 would replace the multiple layers of co-fired ceramic 912-915 and interconnect 931, 932 of package 910.
As a further embodiment of the stacked die illustrated in FIGS. 4P and 5, a chip cooler substrate 980 is shown in FIG. 9C. The chip cooler substrate 980 has a plurality of coolant passageways 982 disposed in a plane parallel to the opposite surfaces 985, 986 of cooler substrate 980. A suitable coolant fluid is circulated through the passageways 982 for removing heat from the cooler substrate 980. An integrated circuit die 990 is mounted above one surface 985. The cooler substrate 980 has conductive vias 983, 984. A support substrate 970 has a number of connection pads 973, 977. One connection between the support substrate and the integrated circuit 990 uses an interconnect 973 on the surface of support substrate 970. A ball connection 972 electrically connects pad 973 to pad 971. A conductive via 983 connects pad 971 on lower surface 986 to pad 991 on upper surface 985. A similar pad/ball connection 991, 992, 993 completes connection of pad 973 to an input/output pad 993 of integrated circuit 990. A similar connection exists between support pad 977 and input/output pad 995.
In the illustrated example of FIG. 9C the coolant passageways 982 are uniformly distributed through the cooler substrate 980. Heat radiated by the integrated circuit 990 is absorbed by coolant fluid and carried away. As a further improvement, a thermal conductive material, such as a metal, could be placed in contact with surface 985 of cooler substrate 980 and lower surface 992 of integrated circuit 990. As another alternative, a thermally conductive interposer could be used.
In FIGS. 10A-10M there is shown and described a die edge connection embodiment of the invention. With reference to FIG. 10A and 10B there are shown, respectively, plan and section views of a portion of wafer 1040 with adjoining die 1041, 1042. Each die has a top oxide 1039 and a bottom oxide 1045. Each die also has a circuit area 1043. The respective circuit areas 1043 are spaced from a scribe line region 1044 disposed between dies 1041 and 1042. The device wafer 1040 is supported by the handle wafer 1046 via the oxide bonding layer 1045 on the bottom side of device wafer 1040.
With reference to plan view FIG. 10C, masking and etching operations are used to define a trenched region 1049 surrounding each die. The trenched region 1049 terminates on the bonding oxide 1045, as shown in section view FIG. 10D. The region 1049 comprises a first stringer region 1047 and lead finger regions 1050. As such, the pattern defined by the region 1049 resembles a lead frame used in many packages with the lead finger regions 1050 connected together by a stringer region 1047. Stringer regions 1049 of adjacent die 1041, 1042 overlap into the scribe region 1044 resulting in a reduced scribe region 1048.
With reference to FIG. 10E, the next step involves oxidation of the trench sidewalls to provide a sidewall oxide layer 1055 covering the sidewalls of the trench 1049 and the top surface of the wafer 1040. The sidewall oxide 1055 may be either thermal or deposited oxide or a combination thereof. After completion of the sidewall oxide, a metal 1056 fills the trench 1049. The metal 1056 in the preferred embodiment is tungsten, but other metals may also be used. The tungsten 1056 if deposited using CVD, completely filling the trench 1049. Portions of the tungsten 1056 deposited on the surface of the wafer are removed using chemical-mechanical planarization.
With reference to FIG. 10F, the circuit area 1043 is further processed to form contact openings (not shown) to circuit elements, first and second levels of metal 1060, 1062 and an interlevel dielectric and passivation layers 1061, 1063. The first level of metal 1060 is used to connect the tungsten finger region 1050 with other levels of metalization or with the circuit area 1043. Next, a protective coating 1064 is deposited over the die and the top of the tungsten filled trench 1056 and reduced scribe regions 1048. Masking and etching operations are then used to remove the protective coating 1064 from the reduced scribe region 1048 so that the edge of the protective coating 1064 corresponds to the outside edge of the tungsten refilled trench 1049. The protective coating 1064 may comprise any suitable material such as a photosensitive polyamide. After patterning the protective coating 1064, all oxide is removed from the reduced scribe area 1048 using either wet or plasma etching.
As a next step the portion of silicon wafer 1040 in the reduced scribe region 1048 is etched and the portion of sidewall oxide 1055 adjacent to the tungsten stringer region 1047 is removed, as shown in FIG. 10G. To etch the silicon in the reduced scribe area 1048, a solution of KOH is used. The sidewall oxide 1055 is removed using a wet etch of dilute HF. Complete removal of the sidewall oxide 1055 from the outside surface of the tungsten stringer 1047 also results in removal of a portion of the bond oxide 1045 in the reduced scribe region 1048. After removal of the sidewall oxide 1055, the entire outer surface of the tungsten stringer 1047 of each die is exposed.
With reference to plan and section views, FIGS. 10H, 10I, respectively, the next step of the process is the removal of the tungsten stringer 1047 and the corresponding stringers of other die. Stringer removal is accomplished using a wet etch of hydrogen peroxide. The etch proceeds until the stringer is removed and the tungsten fingers 1050 are isolated. This etch is a timed etch so that the tungsten stringers 1047 are removed until the sidewall oxide 1055 on the inner surfaces of the stringer portion of the trench is exposed. As a further step shown in FIGS. 10J, 10K, a nickel or gold bump 1080 are applied to the tungsten leads 1050, 1051, 1052, etc. The contact bumps 1080 or castellations are deposited by providing an electroless plating of nickel or gold to the desired thickness onto the exposed tungsten.
After the bumps 1080 are formed, the dry oxide etch is used to remove the remaining bond oxide 1045 from the reduced scribe regions 1048. Each die 1041, 1042, etc. is then electrically probed for test purposes by contacting part of the edge bumps 1080-1084 which extends beyond the protective coating 1064. Die separation is accomplished by mounting the wafer topside down on sticky tape or any other suitable substrate and using a wet etch to remove the remnants of the handle wafer 1046.
The above embodiment is also subject to several variations. For example, the passivation layer 1063 could serve as the protective coating 1064 so long as the composition of the passivation layer 1063 will resist the various etching processes used in the reduced scribe region 1048, including Si etching, oxide etching, tungsten etching, etc. The material 1056 filling the trenches could also be polysilicon instead of tungsten. However, void free filling is required. Instead of the hydrogen peroxide etch used to remove the tungsten stringer, a KOH etch would be used to remove the polysilicon stringer. With reference to FIGS. 10L, 10M, if a deposited oxide 1055 is used for the trench sidewall passivation, a dry plasma etch may be used to form oxide spacers so that only the sidewalls are passivated and there is no deposited oxide on the bond oxide layer 1045. The formation of the spacer sidewall passivation will be desirable if the deposited oxide thickness and composition are otherwise not compatible with the remainder of the wafer fabrication.
It is also possible to connect two or more die along a common edge, as shown in FIG. 10N, for example. After placement of the dies 1041, 1042 on a common substrate 1070 with mating edges in close proximity, application of heat is used to reflow connections to the substrate 1080 as well as die-to-die connections 1085. Substrate connections 1080 serve to connect each of the integrated circuit die 1041, 1042 with interconnect 1090 on the substrate 1070. Die-to-die interconnections 1085 connect between die 1041 and die 1042 and do so with or without also connecting to substrate metalization 1090. A unique feature of this type of die-to-die and die-to-substrate interconnection is the capability for connecting a first die to a second die or substrate with a surface which does not lie in the same plane as the first die. Several examples of this are shown in FIGS. 10P and 10Q. FIG. 10P shows a first die 1141 connected to a substrate 1170. The surface of die 1141 is perpendicular to the surface of the substrate 1170. Edge connections 1180 on the die 1141 are reflow-connected to metalization lines 1190 on the substrate 1170. The flexibility of this type of interconnection is illustrated in FIG. 10Q. A plurality of dies 1141a-1141e are mounted onto substrate 1170. Each of the integrated circuit dies 1141a-1141e has edge connections 1180 which contact metalization lines 1190 on the substrate 1170. The metalization lines 1190 connect to bondpads 1160 or integrated circuit elements (not shown) on the substrate 1170. The structure shown in FIG. 10Q can be utilized to create a high density memory module, for example, where each of the dies 1141a-1141e are DRAM integrated circuits which are interconnected onto a base substrate 1170. The base substrate can be connected to a package in the conventional manner using bondwires.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation. The spirit and scope of the present invention are to be limited only by the terms of the appended claims.
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This creates a huge problem for downloadable programs, which obviously cannot be hardcoded as this suggests, since the coder has no idea where they will be run.
Seems to me that if the server's timezone cannot be relied on, then THAT is the the problem which needs fixed. Not, cause the coder's syntactically-correct work to generate bogus error messages.

subset: commoncrawl


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Golden Globe Nominations 2013: The Full List
Time to celebrate! Television shows Homeland, Girls, and Game Change, along with films like Lincoln, Argo, and Les Misérables, all racked up a slew of nominations when the 2013 Golden Globe nominations were announced this morning, December 13.
Game Change earned five nominations, while Homeland earned four. Some surprises include Episodes and Smash for Best Comedy, neither of which had been nominated in that category for the Emmys. On the drama side of things, both Game of Thrones and Mad Men were surprise snubs for Best Drama, with The Newsroom cracking into the top category instead.
As for the films, the most-nominated movie was Lincoln with four score and seven nods.
The telecast will air on January 13, hosted by two of our favorite people, Tina Fey and Amy Poehler.
Here's the list of TV and film nominations, thanks to The New York Times. Did your favorites make the cut?
Best Television Comedy or Musical:
The Big Bang Theory
Modern Family
Best Television Drama:
Breaking Bad
Boardwalk Empire
Downton Abbey
The Newsroom
Best Actress, Television Drama:
Connie Britton, Nashville
Glenn Close, Damages
Claire Danes, Homeland
Michelle Dockery, Downton Abbey
Julianna Margulies, The Good Wife
Best Actor, Television Drama
Steve Buscemi, Boardwalk Empire
Bryan Cranston, Breaking Bad
Jeff Daniels, The Newsroom
Jon Hamm, Mad Men
Damian Lewis, Homeland
Best Miniseries or Television Movie:
Game Change
The Girl
Hatfields & McCoys
The Hour
Political Animals
Best Actress, Television Comedy or Musical:
Zooey Deschanel, New Girl
Lena Dunham, Girls
Tina Fey, 30 Rock
Julia Louis-Dreyfus, Veep
Amy Poehler, Parks and Recreation
Best Actor, Television Comedy or Musical:
Alec Baldwin, 30 Rock
Don Cheadle, House of Lies
Louis C.K., Louie
Matt LeBlanc, Episodes
Jim Parsons, The Big Bang Theory
Best Actress in a Miniseries or Motion Picture Made for Television:
Nicole Kidman, Hemingway and Gellhorn
Jessica Lange, American Horror Story: Asylum
Sienna Miller, The Girl
Julianne Moore, Game Change
Sigourney Weaver, Political Animals
Best Actor in a Miniseries or Motion Picture Made for Television:
Kevin Costner, Hatfields and McCoys
Benedict Cumberbatch, Sherlock
Woody Harrelson, Game Change
Toby Jones, The Girl
Clive Owen, Hemingway and Gellhorn
Best Supporting Actress in a Series, Miniseries or Motion Picture Made for Television:
Hayden Panettiere, Nashville
Archie Panjabi, The Good Wife
Sarah Paulson, Game Change
Maggie Smith, Downton Abbey
Sofia Vergara, Modern Family
Best Supporting Actor in a Series, Miniseries or Motion Picture Made for Television:
Max Greenfield, New Girl
Ed Harris, Game Change
Danny Huston, Magic City
Mandy Patinkin, Homeland
Eric Stonestreet, Modern Family
Best Picture, Drama:
Django Unchained
Life of Pi
Zero Dark Thirty
Best Picture, Musical or Comedy:
The Best Exotic Marigold Hotel
Les Misérables
Moonrise Kingdom
Salmon Fishing in the Yemen
Silver Linings Playbook
Best Director:
Ben Affleck, Argo
Kathryn Bigelow, Zero Dark Thirty
Ang Lee, Life of Pi
Steven Spielberg, Lincoln
Quentin Tarantino, Django Unchained
Best Actress, Drama
Jessica Chastain, Zero Dark Thirty
Marian Cotillard, Rust and Bone
Helen Mirren, Hitchcock
Naomi Watts, The Impossible
Rachel Weisz, The Deep Blue Sea
Best Actor, Drama
Daniel Day-Lewis, Lincoln
Richard Gere, Arbitrage
John Hawkes, The Sessions
Joaquin Phoenix, The Master
Denzel Washington, Flight
Best Actor, Musical or Comedy:
Jack Black, Bernie
Bradley Cooper, Silver Linings Playbook
Hugh Jackman, Les Misérables
Ewan MCGregor, Salmon Fishing in the Yemen
Bill Murray, Hyde Park on Hudson
Best Actress, Musical or Comedy
Emily Blunt, Salmon Fishing in the Yemen
Judi Dench, The Best Exotic Marigold Hotel
Jennifer Lawrence, Silver Linings Playbook
Maggie Smith, Quartet
Meryl Streep, Hope Springs
Best Supporting Actress:
Amy Adams, The Master
Sally Field, Lincoln
Anne Hathaway, Les Misérables
Helen Hunt, The Sessions
Nicole Kidman, The Paperboy
Best Supporting Actor:
Alan Arkin, Argo
Leonardo DiCaprio, Django Unchained
Philip Seymour Hoffman, The Master
Tommy Lee Jones, Lincoln
Christoph Waltz, Django Unchained
Best Screenplay:
Mark Boal, Zero Dark Thirty
Tony Kushner, Lincoln
David O'Russell, Silver Linings Playbook
Quentin Tarantino, Django Unchained
Chris Terrio, Argo
Best Foreign Language Film:
A Royal Affair
The Intouchables
Rust and Bone
Best Animated Feature:
Rise of the Guardians
Hotel Transylvania
Wreck-It Ralph
Best Screenplay:
Mark Boal, Zero Dark Thirty
Tony Kushner, Lincoln
David O. Russell, Silver Linings Playbook
Quentin Tarantino, Django Unchained
Chris Terrio, Argo
Best Original Score:
Dario Marianelli, Anna Karenina
Alexandre Desplat, Argo
Tom Tykwer, Johnny Klimet, and Reinhold Heil, Cloud Atlas
Michael Danna, Life of Pi
John Williams, Lincoln
Best Original Song:
"For You" from Act of Valor
"Not Running Anymore" from Stand Up Guys
"Safe and Sound" from The Hunger Games
"Suddenly" from Les Misérables
"Skyfall" from Skyfall
Sources: NY Times, The Wrap


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New York-based artist Gary Simmons is known for his "erasure" technique, which he began using in the early 1990s. Initially creating semi-erased works with chalk on blackboards, the artist has evolved to works on paper, paint on canvas, and murals that mimic smudged chalk. The resulting blurred and ghostly images often refer to intersections of pop culture, race, and class.
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Boston, MA (Sports Network) - Dorell Wright scored 20 points as the Philadelphia 76ers continued their strong preseason with an 88-79 victory over the rival Boston Celtics at TD Garden.
Fellow reserves Nick Young and Spencer Hawes tallied 15 and 12 points, respectively, to help the Sixers record their fourth straight win and improve to 5-1 thus far on the preseason.
Wright netted 12 points to key a big second quarter for Philadelphia, which outscored Boston by a 30-19 margin in the period to built a 51-41 halftime advantage.
The Celtics would counter with a 12-2 run to begin the third quarter, but the 76ers answered with a 7-0 spurt capped by Jrue Holiday's three-point play to take a 60-53 lead with four minutes left in the stanza.
Boston pulled within 68-66 on two Jeff Green free throws with 10:16 remaining, but Philadelphia scored 16 of the next 18 points to pull away.
Green finished with 12 points and 10 rebounds for Boston, now 2-4 in preseason play, while Rajon Rondo had 12 points and 10 assists in a losing cause.
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(It's also worth checking your source as Press Dispensary policy is never to change the address of any published release.)
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Validated parking for the underground parking garage is available. A Portland Center staff member will stamp/validate the parking ticket. The cost of each individual parking ticket is based on the time-in and time-out as assessed by Parking Management Company (PMC) City Center Parking, Parking Lot 216. The direct costs for parking as assessed by PMC will be passed on to the department.Internal Willamette University account number required.
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American on the Move is an evidence-based nonprofit dedicated to helping you take small steps and make small lifestyle changes for a healthier way of life. This website will help you improve your health and quality of life through healthful eating and active living. Includes an online community, articles on making healthy choices, and more. En español
America on the Move (AOM)
This guide uses visual representations to show the benefits of regular exercise to those with diabetes. It gives suggestions to get more active and includes places for you to write your ideas and create your own physical activity plan.
National Institute of Diabetes and Digestive and Kidney Diseases (NIDDK)
This flipbook helps teach patients to identify ways to become more physically active. It provides color illustrations with two- to third- grade level text on the patient pages and simple teaching points on the corresponding instructor pages.
National Institute of Diabetes and Digestive and Kidney Diseases (NIDDK)
This guide will help you fit physical activity into your life—your way. Decide the number of days you'll exercise, the types of activities you'll do, and the times that fit your schedule.
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This guide shows you many types of exercise and physical activity. It also has lots of tips to help you be active in ways that suit your lifestyle, interests, health, and budget, whether you're just starting out, getting back to exercising after a break, or fit enough to run a 3-mile race. It's for everyone—people who are healthy and those who live with an ongoing health problem or disability. En español
National Institute on Aging (NIA)
This website for kids tells you cool stuff about how your body works, how eating right helps you play better and feel good, and how staying active is lots of fun! En español
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This comprehensive kit includes reproducible patient education handouts on 29 topics related to cardiometabolic risk reduction, prediabetes, diabetes, and CVD. En español
American Diabetes Association (ADA)
This website makes publicly available materials that were used in the HEALTHY intervention program, which was designed to moderate risk factors for type 2 diabetes in adolescents including nutrition, physical education, behavior, and communications and social marketing. En español
The HEALTHY Study
The National Diabetes Prevention Program lifestyle training curriculum is based on the Diabetes Prevention Program (DPP). The lifestyle program is divided into two components: Core Curriculum & Post-Core Curriculum.
Centers for Disease Control and Prevention (CDC)
This toolkit provides materials to begin a community outreach program with African Americans and Hispanics/Latinos at risk for type 2 diabetes, reinforcing the message that type 2 diabetes can be delayed or prevented. CME credit available. En español
National Diabetes Education Program (NDEP)
This easy-to-read, bilingual Spanish and English tip sheet encourages teens to be more physically active to better manage their diabetes. En español
National Diabetes Education Program (NDEP)
This easy-to-read, bilingual Spanish and English tip sheet encourages teens to lower their risk for diabetes by being active, making health food choices, and losing weight if they are overweight. En español
National Diabetes Education Program (NDEP)
This booklet helps people with diabetes choose and begin a physical activity program and safely lead an active, healthy lifestyle. En español
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Discussion in 'Hockey Talk' started by m_peroni, Jun 6, 2011.
Rome should never play an NHL game, period. Absolutely disgusting.
Oh for crying out loud Mick, that's ridiculous.
Here we go again with the cry for the length of the penalty to be determined by the result rather than the infraction.
Our sympathies and prayers are with Horton and we all hope for his speedy recovery. Unfortunately, he was going north/south and didn't keep his head up which left him vulnerable to an open ice hit which is what the defender's job is as a team enters the defensive zone. There was no more than a second's delay between his pass and the hit. That certainly was enough for an interference call. The emotions of the injury resulted in five and a game, again understandable. To go to the extent that you are advocating is uncalled for. PERIOD!!!
Oh please. Horts went on for like 10 feet after that pass. Rome aimed at his head and even left his feet off the ice. The guy should be gone for at least 10 games for interference, charging, leaving his feet of the ice, and aiming at his head.
You're a drama queen Mick. The hit was late and should be a penalty and probably will be a suspension. How late? According to TSN 28/30ths of a second after he passed the puck. The cut off established by the league is 20/30ths of a second. So the margin of difference is 8/30ths of a second. Blink of an eye. Rome had no malicious intent, it was a fast and nasty game and he made a bad hit. He got the 5 and a game like he deserved. Bottom line is that I hope Nathan Horton is ok, best wishes to him. Scott Stevens got applauded for hits like that but the NHL has changed the rules and I think rightly so. But let's not be preadolescent schoolgirls about it, ok?
As for the game, good for Boston. They've now outscored the Canucks 10-5 but trail the series 2-1. They could've used some of those goals in Vancouver. I actually thought it was a pretty even game through almost 2 periods. Vancouver didn't play all that badly although they made some boneheaded plays at times. Thomas was huge keeping the Canucks off the board until it was way too late. Ehrhoff may have played the worst game of his career, although he's coming off an injury and has had a lot more good ones than bad ones so I'll give him a pass.
For all the talk of special teams, the Canucks' PP has been pitiful. The PK unit killed off 5 minutes and they had several glorious opportunities to take control of the game and failed. If anything they were giving Boston momentum (and 2 shorthanded goals). Then again, it's one game and they all count the same, so forget about it and move on to Game 4. They're still in perfectly good position to get a split on the road and take a 3-1 lead home to Vancouver. I'm finally starting to get a good hate on the Bruins - Lucic, Ference, Peverley -- looking forward to tasting all their delicious tears when we win the Stanley Cup on home ice in Game 5.
Best wishes to Nathan Horton, hope he feels better soon.
You're over-reacting Peroni...but that hit is SUPER late. called it when i saw it, and that there'd be a suspension. I'm no fan of Rome, but he's not a dirty player, and was likely riled up by Marchant earlier and over did it. I suspect a 2 game suspension, which actually i feel is fare, and believe it or not, i think would benefit Vancouver - so AV has to play Ballard and Tanev. =)
that said, what a stinker of a game by Vancouver. great 1st period. Rome hit definitely helped inspire the Bruins further, but they were ready for a great game, and they played a hard solid game, and obviously deserved this win.
things i hated in this game:
- Rome hit
- seeing Horton carried out in a stretcher (my best wishes for his recovery)
- terrible play by Erhoff and Edler - YUK
- 1st 2 lines on Van lost focus getting into scrums with Bruins players
- terrible PP - why did AV have 2 R handers and 2 L handers on the sets of pp's??
- mistake to leave Louie in there after the 4th. rest him, dont' wreck his confidence (or worse give the Bruins more confidence - which is the greater danger)
- mistake to dress 2 slow defense-men in Alberts and Rome in a game this important. (i've proposed dressing 7 D for quite some time, given how often we end up down to 5 Defencemen and that our 4th line doenst play much anyways).
- Luongo and the team giving up completely after 3-0
- reffing sucked - bad calls on both sides, i couldnt tell what was called, and why others were not.
things liked:
- great effort and 2nd efforts on the backcheck by Bruins
- Salo somehow a plus+1 in this 8-1 debacle, guy still manages to stay solid when everyone else flails
- smart move by Julien putting THornton in there , gave them good energy
- fantastic game by Thomas - if he isnt' this good, especially early, there's no way it's an 8-1 win for Bruins, likely a bizzarre high scoring mess, given the numerous give aways and breakaways (Thomas stopped 3 alone)
- LOVE that hit Thomas put on Henrik, hilarious even for a nucks fan.
This post was edited on 6/6 9:03 PM by Original Beast
The hit was late and for that he got 5 and a game, he was doing what the Canucks have been very good at doing all season long...standing up at the blue line....
Unfortunate that Horton got hurt...
You knew something was going to happen, what with Thornton running around beaking at the Nucks bench and the Bruins continuing to wage war with their sticks, I've taken a real dislike for Seidenberg who has a nasty habit of two handing players from behind...
So Julien sez his team is above the taunting? Sure they are...
So if a player body checks Thomas with the puck in front of him while he is outside the net that would be a penalty, but Thomas can throw a body check and that's ok?
As Jeff would say, its off to game 4.....
Take care..
Even as a Canuck fan, I think Rome should be suspended. A lifetime ban is a bit much of course, but the remainder of the playoffs might be appropriate.
It was a late hit, and initial contact was to the head. Rome didn't leave his feet (popped up as a result of the contact) and didn't use his elbow, but it was a late hit to the head.
I hate seeing a player laying on the ice like that.
The video clearly shows him throw himself up at Hortons head...late (Horton was able to take 3 strides and just uner 2 seconds passed from when he passed the puck to Lucic)...it was to the head, and it was blind.
Deserves the rest of the series and 1st 10 to 20 games of next season.
I Take That Trade Off ANY Day If I Am Nucks
7th, 8th, 9th d man for Bruins overall leading goalscorer and best postseason clutch player?
If I am Vignault, I take that trade off any time.
The hit is one thing. But talk about arrogance...
As Julien said yesterday morning, the Bruins dropped the biting incident prior to game 2. "The NHL ruled on that incident. We dropped it. They decided to make a mockery of the league, the ruling, and of us as a team and individuals. They took it to a different level. Thats up to them. But they have to play us again tonight."
However, the Vancouver Canucks didnt. They MOCKED the NHL, the Bruins and Patrice Bergeron, with the garbage that LaPierre, Hansen and others did by sticking their fingers in the face of Bergeron over and over in game 2.
Just more proof that they KNOW that Burrows absolutely DID INTENTIONALLY bite Bergeron. As the video clearly shows, Bergeys glove NEVER went into Burrows mouth...it was ON his mouth and chin. The official turns his head to say something to Bergeron, and you clearly see Burrows look at the official, open his mouth, lower his head, clamp down on Bergeys finger and move his own glove (Burrows) over the fingers to hide what he was doing. When the official started turning his head back, Burrows then released Bergeys glove.
And talk about diving and embellishment.
As Keith Jones said, "Great hit by Ference on Sedin. Shoulder to shoulder and Sedin goes down...grabbing his head for some strange reason. Nothing was anywhere near his head."
And Burrows himself...slashes Tim Thomas on the glove a full 2 seconds after the whistle. Lucic gives him a baby tap slash to the skate...Burrows predictable reaction is to scream in anguish, as if he too has been shot by Seal Team 6.
If Vancouver wasnt the favorite and looking as if they were a shoo in to win this thing....Aaron Rome just clinched it.
Boston will fight. They will show up. They will bring everythingthey have.
But Aaron Rome just clinched the Cup with that cheapshot.
This post was edited on 6/7 3:21 AM by maineblackbear
There was enough time for the pass to already be on Lucics stick...
There was enough time for Horton tohave already taken 3 full strides...
There was enough time for Rome to target the head of a player who should not have to have his head up because he got rid of the puck LONG BEFORE the hit.
Great job justifying...
Would have liked to see Sedin leave the ice the same way...wonder what you'd say then.
You'd be screaming for the Bruin to be suspended.
Yup, The Bruins HAVE Played Chippy, But I Notice...
But I notice that you NEVER mention both sides of it...
You call out Thornton for barking at the Nucks bench.
What don't you acknowledge? Oh, thats right...LaPierre and others MOCKING the NHL ruling on the bite by taunnting Bergeron over and over in game 2. Their actions screamed out, "Yup, he bit him and we know it, you know it too! Ha ha."
You love to talk about the Bruins stickwork...
What do you NOT mention...how about the Bieska crosscheck to the back of Peverleys head, which immediately precipitated his slash to the back of Bieskas foot...which, predictably, resulted in a Vancouver player falling as if shot.
How about the Hansen spear in Campbells groin? No mention of that, huh? I WILL mention Marchards spear to Keslers groin...because I'll call it as it happens.
And you mention the Thomas check on Sedin.
What didnt you mention? How about how everytime they drive the net, a Vancouver player throws himself on the ice, sliding into Thomas driving him into the post. Thats happened, what? Appraoching 10 times this series? Happened once or twice to Luongo?
How about Torres?
You didnt mention his hit on McQauid...launching himself at McQuaids head and shoulder area, as a Canuck player had his arms wrapped around his ankles, having no ability to move and avoid the hit.
You make the Canucks seem like little angels.
However, as everyone is saying, the Canucks dive incessently. They love to hit you and deliver a big shot....however, when a team wont back down from them, and returns fire with big hits....they act like Seal Team 6 just located them and is sniping at them.
I will absolutely acknowledge the Bruins chippiness and stickwork.
However, here is REALITY...Vancopuver has been easily as chippy and stickwielding as the Bruins.
Plus they give you the added bonus of repeated diving.
Vancouver has always been my favorite team outside of the Bruins. And I DO love some of these guys. But man, there are some serious cowaards on that team...starting with Alexandre Burrowes himself.
He is the master of the slash and cry move.....slash the goalies hand and then cry when someone bigger comes along aqnd treats you like a rag doll.
I Apologize
Sir Rodney,
I apologize for the tone of my post. May have been a bit harsh, however, I can't believe how the Bruins are being made out to be this group of stick artists, when the fact is that they are doing nothing that Vancouver is not doing.
Thats all I`'ll say right now.
Re: Yup, The Bruins HAVE Played Chippy, But I Notice...
If the Nucks made a mockery of the NHL in game 2, then what did the Bruins do in game 3, especially after their coach stuck his chest out and said his team wouldn't stoop to something so low?...
Given the brutality of the games and if the Nucks are a team of divers, then what's with Bergeron whining about his finger?...He looked like a sissy skating to the box holding out his finger...The Nucks players were giving it to him for embellishing a minor incident..
The Bruins are looking to goon it up in hopes the Nucks respond in kind and get away from what they do best...They began in game 1 and it always seems to be from behind...
My question about Thomas was just that, a question...As far as Nucks running him over, if he stayed anywhere near his crease you'd have a point but he's causing chaos in front of him because he comes so far out and he never gets set before the contact...Its like a goalie who likes to get to the top of the blue paint to take away the deflection, only Thomas is getting half way between the top of his crease and the blue line...
Last night the breaks went Boston's way and their goals were quick...Even as the score kept climbing I never got the feeling that the Bruins had figured out a way to deal with the Nucks speed and skill, it was just one of those nights similar to others like it ...when the Nucks fall on their faces they take a big fall...
You say you like the Nucks, well Boston was my team growing up so I'm in a similar situation...
The only thing that worries me about Boston is Thomas..
Take care....
I re read your post and need you to clarify one of your remarks...
Were you suggesting that Bieksa was embellishing the two hander Peverley gave him on the back of his leg?....
If you were, that would be the first time the words embellish and Bieksa were used in the same sentence...
Take care...
Nope. Not Saying That
I dont think Bieska would ever embellish anything.
What I AM saying, is that Bieska crosschecked Peverley in the back of the head, seconds before Peverley gave that nasty slash to the back of his leg.
I think BOTH actions were flat out wrong.
Re: Bieksa...
Mick and Jeff are a couple of babies - they act like their sh*t don't stink after a questionable hit. Remember Dan Paille, Jeff? Were you calling for 20 games after his absolutely disgusting, gutless hit on Sawada? I think not.
Regardless - Rome's hit was late, and it was interference. I don't like hits like that, period, so I agree there should be and likely will be a suspension. Rome isn't that kind of player typically, but he was here. He'll get his suspension.
As for the game - all I can say is the series is 2-1 Vancouver. The game was awful, they played horribly, and I feel bad for Lu because 7 of the 8 goals he had absolutely no chance - but they are still leading the series.
I like that I hate the Bruins - they are chippy, love to slash behind the play, and have a ton of gutless babies on their team. Julien's 'holier than though' routine before the game, where he assured everybody that his team would never 'mock' the NHL's rulings, was comical - Lucic and Recchi both 'mocked' the NHL in the game. Yet another Boston baby.
All this said - and yes I'm more fired up than usual given it's the finals - but I like the animosity in this series. As I said before the series, I hate Boston fans (not the city, their sports fans) more than just about any other fans - they are whiny babies who always seem to get their way. It's nice to see Bruins fans and media are no different.
Nope...Not 20
Not 20 games, but I said a minimum 7 games.
Just as I called for 3 to 5 for Marchand when he threw his elbow from behind.
Whiney Babies?
Whiney babies?
Try these on for size:
Burrows: bites; slashes Thomas glove 3 seconds after the whistle, then acts like he was shot when Lucic slashed his boot.
Sedin: Gets hit shoulder to shoulder by Ference. He collapses to the ice grabbing his HEAD! Nothing touched his head...not Ference, not the ice....NOTHING.
Whiny babies? Maybe you should look closer at your own team. They dive incessently. It never stops.
Re: Whiney Babies?
It's probably not worth even getting into this, but it's hard because you're so far out to lunch you won't be home until after dinner. Having said that, I absolutely will cut you some slack because I know I would be wildly overreacting too if the hit had gone the other way. But let's make no mistake, these are your emotions talking, you're not right about almost anything you say.
The hit was not 2 seconds late. It was less than one. It was less than one third of a second late. It was interference. It deserved a 5 minute major. It deserves the same suspension as Chara deserved for his hit on Pacioretty. The NHL decided zero, I would have given more then and I would give more now.
And not to wade into the slapfest, but the Ference hit on Sedin a) was not shoulder to shoulder, he clearly raises his elbow, and more importantly, b) the whistle had already gone on an icing call -- which Ference obviously knew because he had got the icing call -- if Sedin hits Ference there, shoulder to shoulder or not, that's a penalty, because the play is over. Why would it be different the other way around?
Re: SERIOUSLY???
Get off your high horse Jeff. You can delude yourself with the Bruins good, Canucks bad crap all you want but enough is enough with beating some of these dead horses. Bad Lapierre for taunting. No Bruins would do that - wait a minute, two of them did last night. Bruins don't hack and cross check - it's all Canucks diving and embellishing. This Bruins as victims stuff gets old very quickly.
As for the time between the puck leaving and the Rome hit it wasn't just under 2 seconds. They did a video analysis using the slow motion frame count. For one second there are 30 frames. The hit took place after 28/30 of a second. The NHL standard for a late hit is 20/30 so it was definitely late. That's why he got an interference penalty. The shoulder made contact with the head which is why he got the five and a game. All of which is not up for debate. The "throw himself up at Hortons head" stuff is your interpretation of events which may satisfy you but I don't buy that. Watch the video and freeze it at the 36 second mark. At this point Rome's shoulder is in contact with Horton's head but both of his feet are on the ice. Any upward motion came afterwards. If Horton had kept his head up going north/south into the attacking zone as he is supposed to do, the contact would have been with the shoulder area and it would likely have resulted in a 2 minute minor for interference for the 8/30 second late hit. All of the rest of this crap about long term suspensions are a product of your biases. Mick doesn't see shades of grey. For him it is all black and white. In your case, you add some yellow to the mix.
Our thoughts and prayers remain with Horton and we wish him a speedy recovery.
Re: Whiney Babies?
Give both of them the penalties they deserved...Ference for an elbow, and Sedin for his upteen millionth dive of the series.
Re: SERIOUSLY???
3 strides Rodney.....3 strides.
Thats how many FULL strides Horton was able to take BEFORE Rome got to him.
2 strides....thats how many FULL Strides with the puck Lucic was able to make after receiving the pass, before Horton got hit.
The video also shows Horton looking at Lucic, looking for a return pass.
Seriously, if the pass receiver has the time to collect a pass and take 2 strides....the hit is unacceptably late.
Re: SERIOUSLY???
Rome gets 4 games. That's fine with me. But I have yet to hear a coherent explanation why Rome gets 4 and Chara gets 0?
Late hit? Check.
Serious injury? Check.
Norris trophy candidate? Hmm...
Re: SERIOUSLY???
Cant answer that.
Should have been suspended...just as the NHL could have avoided this entirely had they done the right thing and suspended Burrows for his bite. Heck, LaPierres mocking of the ruling and the Bruins shows that the Canucks know that Burrows bit intentionally. They thought it was a joke.
On the flipside, Marchand and Paille were suspended for their infractions. And the Bruins have seen Bergeron, Savard, Krejci and now Horton carted off on stretchers over the past 3 seasons.
They have been on both sides of the equation.
Re: Whiney Babies?
Excuse me? Watch the replay on the Daniel hit - elbow to the face. It was plain as day on the HNIC replay - easy to see.
Lucic punched Burr in the face - not saying he didn't have it coming after the Thomas slash, but keep in mind that Lucic slashed Edler twice in the legs on his way up the ice before slashing Burr and then punching him in the face.
The only difference is the Nucks don't pull a Bergeron and whine to the media after the game - that's why Boston are whiny babies.
Re: SERIOUSLY???
You're joking again right? You bring up the Lapierre mocking incident yet nothing about Recchi and Lucic last game who mocked even more? I guess that's not a joke, it only is when the Canucks do it? How about after your whiny coach whines about it after game 2, saying his team would never do that, then two separate players do it the next game?
I admit I am not objective about my team, but Jeff you always have been and always will be the biggest homer on this board.
lol whiney baby... look who is whining about the hit not being dirty. As if no Nucks fan whined about McGuin's hit on Rome in the Sharls series.
I find it laughable.
I'm consistent enough in saying that all of these hits deserve more punishment. I've been saying it since the Scott Stevens days. I've stressed even more when it happened to Booth and nothing was done, but when it happened to Savard then it was a big deal and something HAD to be done. Of course who cares about the lower end teams, but definitely care about a top player on a big team.
Whiny baby my ass. I've seen too many players have their careers hindered for careless bums like Rome. I think they should be out the same amount of time that the player is out. That'll get them thinking even before initiating such a hit.
Where do you get some of this stuff - you don't even read my posts then you respond to them. I didn't say once that the hit wasn't dirty - once again you put words in my mouth, which you do in basically every response you ever make - I said it was a suspendable offense and he got what he deserved.
You sure didn't stress much when Chara almost ended Pacioretty's career now did you?
Rome is out for the same time Horton is out - he's missing the rest of the playoffs, just like Horton. It's game over for both of them.
Oh, i absolutely blasted Chara for it and took it to Jeff too. Apparently you don't read my posts either.
Neilson Numbers For Game 3
Some interesting statistics which clearly point out who was having a bad night last night, like we didn't already know.
Re: Nope. Not Saying That
Hey Jeff - the video is attached below - where exactly did Bieksa cross-check Peverley in the head? Looks to me like a love tap to the rump - and I think it would be almost impossible to disagree.
Gutless play by a gutless little weasel. Call the antics by Burrows and Lapierre wrong - and I agree they are - at least the Canucks don't have anybody who does garbage like this.
This post was edited on 6/8 6:07 AM by Die-hard1
Again, no mention of an apology for putting words in my mouth - not surprised.
Sorry if I don't remember you getting on your high-horse 8 months ago during the Chara hit.
Re: Nope. Not Saying That
How about Hansens 2 hander to a defenseless Krejci?
Re: Nope. Not Saying That
Upon further review, you completely fabricated Bieksa's cross check to Peverley's head. Your credibility is down to zero for me at this point -- I had been taking your word even if I thought you were exaggerating, but if you're just going to make things up then what's the point?
Re: Nope. Not Saying That
Do you have video for that? I didn't see it and I've watched every minute of the series - I've even provided video that showed you were dead wrong but you didn't reply.
Please provide a link, video, something - I'd actually like to see this act because I honestly don't remember it.