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Foodie FailureAuthor: swampkitty05 // Category: Culinary Failures
While going through my pictures on Flickr, I came across this. Just wanted to post the picture quickly to show you that even us foodies have recipes that come out as an epic fail.
This blueberry/juneberry tart ended up with a crust of sugar on top because the recipe I used called for it to be mixed directly in with the berries before putting it in the oven. For whatever reason, all the sugar migrated to the top where it proceeded to form a hard crusty lump in the center. Think Mt. Sugarmore. Needless to say, this one wasn't salvagable.
Do you have any memorable kitchen failures to share?
4 Responses to "Foodie Failure"
Kay Says:
August 3rd, 2009 at 2:23 am
I needed to take something for part of the refreshments for our Bible School one evening, so I decided to add a bit of flair to a box mix of brownies. I mixed it up and put it in the pan like the instructions said. Then, I took some melted carmel and drizzled it over the top, then marbled it. It looked perfect. Then I baked it. When i got it out of the oven, there was no marbling, no caramel anywhere! Here, it had all sank to the bottom and STUCK on the bottom of the pan. I wrecked the pieces as I tried to get them out to put onto a serving platter. We ended up inhaling the whole pan ourselves at home instead and I just took finger jello to add to the refreshment table.
Amy Shropshire Says:
August 5th, 2009 at 4:55 pm
My first baking attempt – muffins! Well, that's what they would have been if the oven hadn't caught on fire!
Foodie Failure - send gift to India Says:
August 8th, 2009 at 5:30 pm
[...] Go here to read the rest: Foodie Failure [...]
Carmel Restaurants Says:
May 26th, 2010 at 7:18 pm
Big important dinner with big important dinner guests, ok? Trying to impress. It went ok until I got my baked meringue with chocolate sauce for the dessert and everybody tried to eat it. Imagine trying to dig into what looks like a soft, frothy meringue, but is hard as a rock and stuck to the dish as if with crazy glue!


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In a recent PEW poll, 18% of the general population believe that the President is a Mooslim. In another part of the poll, 30% of Republicans believe that Obama is a Mooslim.
Pew analysts attribute the findings to attacks by his opponents and Obama's limited attendance at religious services, particularly in contrast with Presidents George W. Bush and Bill Clinton, whose worship was more public.
Six in 10 of those saying Obama is a Muslim said they got the information from the media, with the largest portion 16 percent saying it was on television.
Before the election, I remember an old lady, at one of McCain's town hall meetings, saying how afraid she was, because Obama was a Mooslim. To his credit, McCain took a few minutes to assure the crazy lady that Obama wasn't a Mooslim, and she had nothing to worry about, because Obama was a "good" man.
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subset: commoncrawl


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Your Story
Mon, March 17, 2014
Gum for E.D?
Wrigley gum is expanding the meaning of "doubling your pleasure" as they have been granted a patent to develop a gum that contains a dose of the generic chemical in Viagra.
Wrigley researchers said the gum would provide "an improved dosage form and method of treating erectile dysfunction."
The gum could be used by patients suffering from weak stomachs or swallowing disorders as an Upset stomach is one of the side effects of taking Viagra.
The gum would not only be easier on the stomach, it would work faster than Viagra's little blue pill.
In the patent application, Wrigley states that a man would need to chew the gum for two minutes to about a half-hour prior to sex.


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Uncharted 3: Drake's Deception (Playstation 3) Developer: Naughty Dog Publisher: Sony Computer Entertainment Genre(s): Action Adventure, Platform, Third Person Shooter Released: November 1, 2011 ESRB Rating: T – Teen Uncharted 3 was my most anticipated game of the year. It's been a week since its release, and I have finished the single player campaign twice (Normal and Crushing), and I can safely say that it lived up to my anticipation and expectations. Uncharted 2: Among Thieves set the bar extremely high, and I believe Naughty Dog are right when they say the kind of jump between Uncharted to Uncharted 2 can only happen once a generation. Where Among Thieves vastly improved in every way over the first game, Drake's Deception is only a minor step above the second in the series. One of … [Read more...]
Review: Uncharted 3: Drake's Deception
Uncharted 3 Co-op Adventure Gameplay
The above video from GameTrailers shows off some gameplay footage of Uncharted 3's co-op adventure mode, and it looks fantastic. You'll probably recognize some Uncharted 2 characters in there (as well as one from the first game), and the different adventure maps (one of which is also from the first game). I've been playing Uncharted 3's competitive multiplayer all month long, Team Objective, but co-op is what I'm looking forward to the most (besides the single player, obviously). During the June/July beta, I played co-op (adventure and arena) almost exclusively all the way up to level 30 something. Once I beat the single player, my time spent with Uncharted 3 online will be 95% spent on co-op. If you're going to be playing co-op in Uncharted 3 next week, feel free to add me on PSN. … [Read more...]
Uncharted 3: Drake's Deception Launch Trailer
Epic trailer is seriously epic. The above launch trailer shows off why Uncharted 3 is my most anticipated game. Everything about it just screams awesome. As much as I've been enjoying the UC3 multiplayer subway promotion, it is the single player that makes Uncharted 3 so anticipated. The multiplayer is really just a bonus (and a great one at that) as far as I'm concerned. November 1st needs to hurry up and get here. Just a little over a week away now! … [Read more...]
Experience Full Uncharted 3 Multiplayer Beginning October 1st, When You Buy A Subway Soda
If you're a PS3 owner, there's a little game coming out on November 1st that you may have heard of called Uncharted 3: Drake's Deception. Okay, it's not a little game and you've definitely heard of it; it is after all kind of a big deal and one of the most anticipated titles of the Holiday season. Well good news, beginning this Saturday, October 1st, you'll be able to experience the full Uncharted 3 multiplayer. Well competitive multiplayer anyway. All you need to do is visit your local Subway and purchase a 30oz drink; you don't even need to buy a sandwich (though it has its own rewards too). Yup, you can gain complete access to Uncharted 3's multiplayer for a month before release for the price of a large soda, while also getting a sweet collector's cup. Every cup is a guaranteed … [Read more...]
Uncharted 3 PS3 Bundle Coming Soon
If you don't have a Playstation 3, hold off another month before getting one. Sony today announced a killer new bundle. For $299 you get a 320GB PS3 Slim, the game Uncharted 3, 1 PS3 controller, and Playstation Plus for one month. When I got my PS3 back in 2009, it was also $299, but it was a 120GB model (there were no 320's at the time). Of course it came with two games (InFamous and Killzone 2). But we're talking a brand new 320GB PS3 and one of the most anticipated games of the year bundled for only $299. The bundle is releasing November 1st (same day as Uncharted 3), so go pre-order the PS3 320GB Uncharted 3 Bundle now. It's definitely a purchase you won't regret. … [Read more...]


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@duhsweetness sorry the attractiveness of a number doesn't mean that a man who says that a 5 is a 2 is right. Its still a 5
@Lost Ones the two aren't mutually exclusive...
@Old Man Game @GREENE1148 @exclamatory remark Yeah i'm not going believe that until its proven, do you have a source?
@Greeed been having this argument with a friend of mine, he still thinks bosh is best midrange shooter
@Lambo Serge the III @f5alcon @Turfright eh... wasnt he talking about the browns moving from cleveland back to baltimore?
@Turfright but it's the cavs so they'll probably just draft napier at no1.
has it been mentioned perk had double digit rebounds yet?
9 turn overs.
@Lost Ones we also swept them in the regular season, they don't have anyone who can guard russ or reggie, and the only way they have a prayer is if kawhi has a monster series.
@sammasaaron @L0rv I skipped the first bit and got a completely different tone from it
@OKC_Gooner damn... wasn't he single handedly pushing the trade westbrook for cp3 bandwagon a few years back?
I feel like cartman at the end of the scott tenorman ep. BRING THEM TEARS ON!
@TheGlove @L0rv @35 4 Finals MVP Actually he has a ton of talent, which makes the flopping worse.
@[brooks' fault] @Old Man Game rams fan here, the depth on the defensive line is crazy good, got a couple of guys that regularly spell long & quinn and do a great job, I don't think he's likely to make the team but we'll see.
@Kong Lambchop looked like to me, while ibaka has his arms up he nails himself on ibaka's elbow.
@OKC035 @[brooks' fault] Russell is a basketball troll
So... lets be clear, durant fouled crawford. That wasn't a bogus call
@KingofGivingUptheMoneyBall @Messire its the playoffs...
@GREENE1148 @Julius F Wrek it looks like to me, right before the elbow hits paul flops, but i can't be sure.
seems like durant is still kind of struggling from outside, another bad 3pt shooting game. (3 of 9)
@KingofGivingUptheMoneyBall @Butterfingers it may not be coming...
@DialMforManaigo 3/3 tonight. crazy
steve with 3 blocks in 9 mins
@kevindurant35 this this. this this this this this.
@Jooseppi @bmuelle23 I wish i had been reading DT when that happened.
@Tvaddic I dont think he is, they said they were extra cautious with his injury during his rehab process, i think he said he could have played a while ago.
@El Prez @Es Wild I mean the dude had 23 points two night ago, we won't get anywhere near that producton, but i feel better having someone who can absolutely light it up from 3 on occasion, as he's proved he can do in a thunder uni.
@Perk-Punt @f5alcon @mattchant hes said a few nice things about the guy over the past few years and now people are talking about him being potientally the difference in free agency? What? Wasn't ucon a 7 seed?
so its not totally outside the realm of possibility for the spurs to lose 3 games, their next three are against dallas, houston, and pheonix
@d21 Wow! I had no idea the suns were such a successful franchise, talk about snake bitten, 19 50+ win seasons and a not a single championship.
@Butterfingers @Julius F Wrek well, they are 3 games ahead of us, I'd say they've been playing significantly better ball than we have the last two weeks, although the last few games have certainly been impressive. As a thunder fan I think we're the best team in the league but its certaintly not outrageous for a spurs fan to think they are the best in the nba. much much more outrageous things have been said on this board.
@Butterfingers that 3 gave you a like.
@King of Carrot Flowers the third We don't know whats going on behind closed doors in the organization, and its a pretty well run one, so they probably know something we don't.
getting sick of this kobe piano commercial. league pass has shown it like 5 times already
kd is going to get kicked out of this game...
@d21 @[brooks' fault] but right now it doesn't matter, so people getting all worked up about it is kinda hilarious, but in a really sad way.
lol lamb has 2 blocks too
@Legendary_Dork if they had he was gone from the game, they're not going to do that.
@MJOKC I thought it was funny people were making a big deal out of houston making up ground to OKC, and still had not beaten us this season.
fucking. kidding me.
lol that face palm


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Discussion in 'PatsFans.com - Patriots Fan Forum' started by SVN, Oct 1, 2007.
"What I think the league found was a small cache of tapes but a larger stack of notes explaining exactly what the tapes taught the team. That's what I
think, but we'll never know, will we?"
Well gosh, PK - what responsible journalism.
King is about access. He sides with those who give it to him, and hates those who don't. The Patriots have cut him off. Cut him off entirely. None of them are speaking to him. He wants their "side" of the story. He's not getting it, and it's burning him up. That's why he's keeping the fire lit.
As a Pats fan, I have lost all respect for the sports media on this issue. And I have no respect for any Pats fan who posts such articles because he/she believes the Patriots should have acted in a different manner than they have.
I commend Robert Kraft and coach Belichick for remaining quiet on videogate despite the fact that this whole thing has been a virtual witch-hunt against them. They "could have" made the NFL initiate a league-wide investigation into this practice and revealed other rule breakers, but they took the high-road.
I'm damn proud of Mr. Kraft & coach Belichick for their class & integrity!
actually he talks a lot with brady..i know he had a quote from brady last week about the eagles players saying that the pats knew all the signals in the SB. Brady said that "of course they ran screens because they blitz on every play"..or something of that sort.
FYI iam not believing pats shouldve acted differently...just posted what i read.
This is the height of stupidity. The league said they found nothing further.
What are they supposed to do? Give out daily press releases saying that for 30 straight days to keep up with the conspiracy theorists?
I think the comments are fair.
I think the league made a huge mistake by making this into a huge deal, like videotaping the opposing coaches is a major infraction that somehow damages the integrity of the game the way blackmailing an official would.
But I also think the league made a mistake by destroying the evidence as quickly as they did. I think they realized that they had overreacted and wanted the controversy to go away, but having created the firestorm they should have let it burn out. If there's not a lot to see, why destroy the evidence? It just seems nuts.
They could have simply released all the material. Why not?
King and the rest of the media will continue to bring this up until the next "big" scandal or story comes along. I foresee another knucklehead stepping forward in the near future or at least until Vick's sentencing hearing.
:blahblah: :blahblah: :bricks:
Several reasons
1) We already know what is on there. Nobody has hidden the fact that NE had been taping the D calls for years now.
2) Because the league already had issues with tapes leaking to the media.
3) Because no matter what, even if they released every tape to the media, morons like TMQ would be clamoring that they hid the "juicy" stuff.
It doesn't benefit anyone to *not* destroy the tapes.
What would the point be?
Doing that would PROLONG the life of the episode.
AhHA! So again, I am not the ONLY one who thinks this way! Regardless of CONTENTS, it was certainly an oddball way to end things, and it will ALWAYS leave questions.
Wasn't PK LAUDED last week for his article stating video was a minor piece. Now that he questions the destruction, some Pats fans are again OFF his bandwagon. Don't you see how obvious your homerism goes??
Who's the guy that applauds BB and Kraft for NOT COMMENTING?? Are you serious??? They are the good guys because YOU THINK they had the power to tell the LEAGUE to launch an all out investigation?? HAHA. The reason they were silent is because that way their stories stay straight. Nothing to say, because it could not have possibly reflected good on the team. WTF would they speak in detail about any infraction??
Anyway, it's over, now, how many fantasy points is Brady going to score for me tonight??
Why Thomas, why? Just to keep the pot boiling?
If nothing was found, then that should be the end of it. You know damn well if they released the information the vultures would have swarmed al over it. They would take the smallest ant hill and make a volcanic mountain over it.
That's why not.
Then shut the F up already!!!
We, as Patriots fans, think we know, and don't really care anyway, but by destroying whatever it was they destroyed (actually, I really have no idea what they destroyed and I don't think any of us do), they allow people to keep talking about the "imagined" destroyed evidence. It just doesn't make any sense to me.
There wouldn't be any problem with leaks if the "evidence" (whatever it was) was released.
Maybe, but now they claim that they destroyed the "juicy" stuff.
I don't even understand how the league office had time to review the stuff they destroyed it so quickly.
I'm having trouble parsing the meaning of that sentence.
To answer King's questions, yes, yes, yes, yes, and yes. The Patriots have been stealing for years. They compromised the opposing staff in the Super Bowls. That aided their victories.
So what? Maybe those lazy coaches should get off their bums and do some advanced scouting once in a while. Peter King wants to reward the lazy bums who like their 10 hours of sleep over the 8 coaches in the league who will leave no stone unturned.
I'm curious, did the commissioner ever come out and say "no further infractions were discovered, there are no additional fines to impose, case closed" ??
If he didn't, he should.
Separate names with a comma.


text:
- Ceramic Arts Daily - http://ceramicartsdaily.org -
Glass, Janet E.
Posted By Erin Pfeifer On February 13, 2009 @ 11:21 am In Artists,Portfolios | No Comments
Janet E. Glass
Clay Turtle Pottery
Mansfield, Texas
Contact Information:
Article printed from Ceramic Arts Daily: http://ceramicartsdaily.org
URL to article: http://ceramicartsdaily.org/potters-council/portfolios/glass-janet-e/
Click here to print.
Copyright © 2008-2012 Ceramic Arts Daily. All rights reserved.


text: HomeTVDancing With The StarsCarolyn Hinsey's Latest General Hospital Casting Scoopage: "They're Clearing The Deck For Kristina Wagner" Jamey Giddens March 3, 2012 Dancing With The Stars, General Hospital 40 Comments It looks like we can finally start planning Felicia Jones Scorpio's (Kristina Wagner) welcome home party! After weeks of rumors (and one fake Facebook post), veteran soap journo Carolyn Hinsey is now confirming General Hospital is set to bring half of one of the soap's most popular 80's supercouple's back to Port Charles. Tweeted Hinsey: Hey GH fans! They're clearing the decks for Kristina Wagner. Sssshhh… you heard it here first. #soapsstillmatter How awesome is this news? I sure hope GH's new showrunner Frank Valentini can book Wagner's real and reel life ex-hubby (and upcoming Dancing With The Stars foxtrotter Jack Wagner) next. Soaps Still Matter, indeed! Photo credit: ABC 40 Responses soapjunkie88 March 3, 2012 Oh that's great! But I don't think that this news would allow Jack Wagner to come back too. Would be kind of awkward on the set… I hope they really plan to bring Lexi Ainsworth back tough. Really miss her. And I'm still waiting for some good news for the Q's. But hey, Kristina Wagner is great!!!! Log in to Reply Jamey Giddens March 3, 2012 @soapjunkie88, from everything I have heard, Jack and Kristina had an amicable split. Log in to Reply soapjunkie88 March 3, 2012 Oh I heard that too, Jamey. Just don't think that working with your ex in general is such a good idea no matter how amicable the split was.^^ But if it happens and Jack Wagner returns after all those years of course that'd be great! Log in to Reply Jamey Giddens March 3, 2012 Just don't think that working with your ex in general is such a good idea no matter how amicable the split was *** Maybe they could be the Sonny and Cher of Daytime? LOL It's happened before though. Eileen Davidson and Don Diamont were hot and heavy in the 80's, then they were paired together on Y&R in the 90's, when she came back and both were even married to either people. I am holding out hope Kristina and Jack would be able to make it happen. Log in to Reply Wings1295 March 3, 2012 I hope, if Felicia is coming back, they finally mend the relationship between Felicia and Maxie. Maxie's hate at Felicia's abandonment only comes from the crappy writing to explain Kristina Wagner's absence from the show. Made no sense to me, cause Felicia was a good mom for her girls. Anyway, love Felicia, so happy to hear this news! Bobbie next, I hope! Log in to Reply pecola March 3, 2012 This will only make me miss Kirsten Storms more… Log in to Reply GHFan76 March 3, 2012 Kirsten Storms please come back!!!! Story won't have same impact without you! Log in to Reply ahanshew March 3, 2012 This makes me VERY happy! I am looking forward to Felicia, Frisco, and Maxie mending their relationship (I do wish this was with KS too). And here's to hoping that Frisco comes back with Georgie in tow. I have to believe that Jack Wagner is coming back! Log in to Reply josser March 3, 2012 I thought Jack Wagner's appearance on DWTS signaled his return to GH? Log in to Reply westvirginiafan March 3, 2012 she didn't have it first–ravenbeauty posted this back in february–let's give credit where credit is due Log in to Reply Screamer_2012 March 3, 2012 After the absolute, horrible way Felicia was written several years ago, I think the only way to redeem her character would be for the current writers to say that the reason why she stayed away, was because she was forced into some sort of mission to keep Frisco from being killed, and she couldn't say anything in Port Charles, when she went to Georgie's funeral, because she was being watched, and if she did try to tell someone what was going on, she would've put their lives in danger, also. Sorry…. that's all I can come up with.. lol. Log in to Reply GHdoolFan March 3, 2012 I don't think they even need an excuse for her staying away. Maxie was a bitch to her and it was probably easier for both of them for her to stay out of Port Charles. Frisco and Felicia are no worse of parents than Robert and Anna, but you never hear anyone complain about that. I guess because Robin was so nice and Maxie is a complete bitch. It wouldn't be like Robin to harp on it for too long, but Maxie's whole life is based on being able to bitch about her shitty parents. They could always go the mission route and I'm sure they will. I'll be so happy to have Felicia back. I agree that this will make me miss Kirsten Storms so much more than I already do. Its nothing against Jen Lilley, but when KS's Maxie ripped Felicia a new one at Georgie's funeral those scenes were epic. KS is so much of a more lovable bitch as Maxie. I pretty much just hate Maxie now. It will be fun to have Felicia back on canvas either way. I don't see any storyline for her right now other than being a parent for the first time since her kids were like 5 years old. I guess Maxie will continue to spiral out of control and get reallllly bad and Spinelli probably tracks Felicia down to try to save Maxie's life. That's all I can come up with. I hope they can get Jack Wagner!! I need Frisco. That would feel so much bigger than just Felicia and there's tons of storyline there. Log in to Reply Screamer_2012 March 3, 2012 Also, with Kristina Wagner coming back, I'd love to see Robyn Richards back as Maxie, since it seems as if Kirsten Storms won't be returning. I never understood why Robyn was fired… twice. http://i42.tinypic.com/n6rekp.jpg Log in to Reply GHFan76 March 3, 2012 I'd love to see Robyn Richards too! She looks gorgeous in that picture! Log in to Reply Screamer_2012 March 3, 2012 [quote=MissingtheoldGH]I'd love to see Robyn Richards too! She looks gorgeous in that picture![/quote] She and Kirsten look like they could be sisters. I remember her being a remarkable young actress. Again… I never understood why she was fired, twice, as Maxie, when she always did a great job. Sorry to the Jen Lilley fans, but she just isn't suitable as Maxie to me. From what I've read… Kirsten won't be returning. Log in to Reply Cyberologist March 3, 2012 I was a Robyn Richards fan. Kirsten Storms acting so dingbatty ditzy dame got real old for me it seemed to really get bad when she was paired w/Spinelli but I'm really not liking this Maxi much … Log in to Reply Screamer_2012 March 3, 2012 Here's proof as to why Robyn Richards should come back. Even back then, she was a much better actress than Jen Lilley is now. http://www.youtube.com/watch?v=pnZFgBmSzyY Log in to Reply The_Moustache March 3, 2012 YEEESSSS!!!! now bring back Lindze Letherman as Georgie and bring back Robyn Richards as The REAL Maxie. hopefully Jack Wagner can come back too. Log in to Reply Screamer_2012 March 3, 2012 [quote=The_Moustache]YEEESSSS!!!! now bring back Lindze Letherman as Georgie and bring back Robyn Richards as The REAL Maxie. hopefully Jack Wagner can come back too.[/quote] Lindze Letherman was so freakin' great as Georgie. I wish they could find a way to bring her back. I'm sure Jen Lilley fans will be pissed at me for screaming "BRING BACK ROBYN RICHARDS AS MAXIE!" But since Kirsten isn't coming back (I'm pretty sure it's been confirmed), then please bring back the incredible actress who was fired, twice… for no good reason. Log in to Reply Screamer_2012 March 3, 2012 Personally, I'd rather see Lady Gaga play Maxie, instead of Jen Lilley. At least Lady Gaga can cry real tears in her videos. Jen's performance, after finding out Robin had "died", was just… awkward. Log in to Reply GHFan777 March 3, 2012 I am so excited to see Kristina come back…. F&F go down as one of my all time favorite soap couples…They were very comedic and romantic..their chemistry was off the charts…probably why they married in real life :-)….I was horrified at how they wrote for Felicia the last few years she was on the show…So sad what they did to this once iconic soap heroine. Now all we need is to hear that Jack will be reporting to GH after DWTS…I think it may be possible for them to work with one another again. From what I read they are very amiable…and share two sons. Maybe joint parenthood has kept them friendly. I sure hope so. I have been loving the Scorpios being back…even if it is such a sad time on the show…I just love seeing all the returning vets….GH is really starting to be "Must see TV again". Log in to Reply Dale Constance March 3, 2012 Yes, this is old news for those of us who follow RavenBeauty! She reported on Feb 5 that Frisco and Felicia were returning! Log in to Reply SavePortChuck March 3, 2012 First Finola Hughes… now Kristina Wagner??? I feel like my head is going to explode, I'm sooooo excited! Log in to Reply pjc722 March 3, 2012 This is awesome news as the character of Maxie will need her mother and there could possibly be a love triangle in there between Mac, Felicia and Alexis. As for bringing back Jack Wagner's Frisco, where would they possibly fit him in the landscape with not only John from OLTL coming on board to the police station but Robert being around (for however long), Mac and Dante still there. This show needs more heroes like swiss cheese needs yet another HOLE to make it better! If you bring on another hero you need evil to make that hero. General Hospital needs to get out of the mob business, get back to love and hospital drama. While we on it, Dante is such a moron. Either you hate your dad or you don't. Either you are a good cop or you're a bad one. Right now he gives Sonny all the leeway he orders making him a bad cop. There is ABSOLUTELY no reason why Dante should not have arrested Sonny after witnessing him holding a loaded gun to Johnny and then getting confirmation from Sonny that he did the same in front of Tracey by holding the same gun to Anthony's head. NOT every bad that Sonny does can be let go because poor Dante doesn't want to upset Michael. Michael is a punk the way he is written right now with no life, no friends and no goal. Instead of worrying about what it would do to Michael to have their father arrested for being a cold blooded killer, Dante should arrest Sonny to show Michael that evil has consequences and the law is the law. Log in to Reply curacaoman March 3, 2012 [quote=westvirginiafan]she didn't have it first–ravenbeauty posted this back in february–let's give credit where credit is due[/quote] True that! I hope she comes back fighting for Mac, just after he starts a relationship with Alexis! Awesome triangle! Log in to Reply JeffHB March 3, 2012 I was thinking that a Mac, Alexis, Felicia triangle would be great too. Robyn Richards would be much better than nuMaxie. I wonder if she can play a bratty bitch though? She was Maxie when Maxie was a sweet girl. Felicia is my all-time favorite GH character. Please get her back ASAP. Log in to Reply MsAgentProvocateur1 March 3, 2012 [quote=soapjunkie88]Oh I heard that too, Jamey. Just don't think that working with your ex in general is such a good idea no matter how amicable the split was.[/quote] Jennifer Lopez & Mark Anthony sure seem to be making it work. Their series Que Viva is a hoot! I think if they're both approaching it as professionals, it could truly work. Kind of a shame, though, that there are no surprises left in Daytime TV these days. Log in to Reply blake3b March 3, 2012 Now bow down to Frank and Ron!!! Log in to Reply soapcrazy March 3, 2012 I hate to put a damper on everyone's parade but I am suspicious of so many vets returning. Does this mean General Hospital is really going off the air? So many fan favs coming back remind me of relatives coming back to pay their last respects to a family member on their death bed. Ya'll know what I mean? It's like, you haven't seen or talk to a relative in ages(robert, anna, holly, felicia) then all of sudden they just show up, cause you're dying or they want something. Log in to Reply The_Moustache March 4, 2012 @SoapCrazy if she show is indeed going off the air this year, then it's going out with a bang & back on top, back to what GH should've been all along!! Log in to Reply Ranae1221 March 4, 2012 In all fairness, Carolyn Hinsey did NOT spill this 1st. RavenBeauty Soap Diva mentioned it first on 02/06/12: Hey Guys, Frisco and Felicia done……..On their way. http://www.voy.com/191220/8976.html Log in to Reply soapjunkie88 March 4, 2012 @SoapCrazy: I don't think that Ron at the moment is thinking about bringing old fan favorites back to GH's farewell. He's trying to win fans back and is taking this show in a different direction. And that's why these people come back – so this show survives. I guess it happen to be so many of them because the two previous regimes weren't really interested in characters like Felicia, Robert or Heather. They had a different version of GH. So I guess Ron just had to call them up and that was about it. Anything else might be happening if ABC decides to wreck their daytime completely and cancel GH. Log in to Reply mafelix86 March 4, 2012 This is VERY good news, indeed!! And I'm glad to see that I'm not the only one that misses Robyn Richards. To me, she is Maxie. GH made a big mistake letting her go. Ron should bring her back as well. Bring Back Emily, Alan, Dillon and Georgie as well. THAT would be the icing on the cake!! Log in to Reply curacaoman March 4, 2012 Why are they "clearing the decks"? I am sure all it takes is a willingness to write for the character! The Luza and GagIn obviously never had that! Log in to Reply THEBEST March 4, 2012 I am all for Kristina Wagner returning! Felicia was one of my fav characters when I started watching back in 1996. Frisco would be icing on the cake, so hopefully Jack can work out a schedule with DWTS if this ever comes to fruition. Susan Lucci, Cameron Mathison, & Kelly Monaco did it. Frisco & at least Felicia HAVE to return to reconcile with Maxie. If we have to be stuck with Jen Lilley, at least this will help ground her version of Maxie. Log in to Reply aztecprincess March 4, 2012 Very excited and have been waiting for this news! Hoping they bring Jack back too and that they can work out working together. It will be great to see Felicia interact with Maxie, Anna, Holly, Robert, Mac, and others! She was always one of my favorites and I grew up watching her. I believe Jen Lilley will do a good job, she is a good actress, I know we would prefer Kirsten S. but if she's sick, nothing can be done until she recovers! Looking forward to FELICIA!!!! Log in to Reply aztecprincess March 4, 2012 Very excited and have been waiting for this news! Hoping they bring Jack back too and that they can work out working together. It will be great to see Felicia interact with Maxie, Anna, Holly, Robert, Mac, and others! She was always one of my favorites and I grew up watching her. I believe Jen Lilley will do a good job, she is a good actress, I know we would prefer Kirsten S. but if she's sick, nothing can be done until she recovers! Looking forward to FELICIA!!!! Log in to Reply TheOldSoapster March 4, 2012 great news that she's coming back. … meanwhile, can someone help me out on one of the plots she was in just before i quit watching years ago? she and luke were trying to figure out why there were two bodies in one crypt of the q's family mausoleum. the two of them and edward and lila were in the living room when — the morons at the KABC news department decided to break in with yet another L.A. freeway chase just that couldnt wait until the 5 o'clock news. the next day the show went on and this plot was NEVER mentioned again, thanks to dopey writers. i kept waiting for SOMEONE to bring it up. … so who were the two bodies? and did lila or edward kill someone? thanks. Log in to Reply waybackfan March 12, 2012 YAY! Agree with all who've said they need JW, RR, and LL and Dillon (hopefully, SC, but I'm open to a well chosen recast) back as well. I don't care how it's done, just get it done. IF they could get Amber Tamblyn, Emily's return would be wonderful. Otherwise, ugh, no thanks. I'd rather see Alan and Scotty Baldwin and AJ and most of all: Genie Francis. I'm sure they're saving the best for last though, as far as GF goes. Log in to Reply tamshanni March 12, 2012 I hope kristina wagner has taking some acting lessons .She and holly (from GH) are two of the worst actors I've ever seen in my life. and her speaking voice is terrible. it has that 'whiny little girl thing' that is so ugly in a mature female over the age of twenty-five. It's bad enough we have to put up with the dregs of the cancelled One life… yikes. the stunt casting is starting to grate. Soon we'll be begging to have them put GH out of its misery. Log in to Reply Leave a Reply Cancel Reply You must be logged in to post a comment.


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712 - Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
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|Class / Patent application number
|Number of patent applications / Date published
|Simultaneous issuance of multiple instructions
|Region-Weighted Accounting of Multi-Threaded Processor Core According to Dispatch State - According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.
|System and Method for Issuing Load-Dependent Instructions in an Issue Queue in a Processing Unit of a Data Processing System - A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to indentifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
|PROCESSOR AND INSTRUCTION SCHEDULING METHOD - An instruction scheduling method and a processor using an instruction scheduling method are provided. The instruction scheduling method includes selecting a first instruction that has a highest priority from a plurality of instructions, and allocating the selected first instruction and a first time slot to one of the functional units, allocating a second instruction and a second time slot to one of the functional units, wherein the second instruction is dependent on the first instruction.
|TEMPORAL SIMT EXECUTION OPTIMIZATION - One embodiment of the present invention sets forth a technique for optimizing parallel thread execution in a temporal single-instruction multiple thread (SIMT) architecture. When the threads in a parallel thread group execute temporally on a common processing pipeline rather than spatially on parallel processing pipelines, execution cycles may be reduced when some threads in the parallel thread group are inactive due to divergence. Similarly, an instruction can be dispatched for execution by only one thread in the parallel thread group when the threads in the parallel thread group are executing a scalar instruction. Reducing the number of threads that execute an instruction removes unnecessary or redundant operations for execution by the processing pipelines. Information about scalar operands and operations and divergence of the threads is used in the instruction dispatch logic to eliminate unnecessary or redundant activity in the processing pipelines.
|MFENCE and LFENCE Micro-Architectural Implementation Method and System - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
|PREDICTING A RESULT FOR A PREDICATE-GENERATING INSTRUCTION WHEN PROCESSING VECTOR INSTRUCTIONS - The described embodiments provide a processor that executes vector instructions. In the described embodiments, while dispatching instructions at runtime, the processor encounters a predicate-generating instruction. Upon determining that a result of the predicate-generating instruction is predictable, the processor dispatches a prediction micro-operation associated with the predicate-generating instruction, wherein the prediction micro-operation generates a predicted result vector for the predicate-generating instruction. The processor then executes the prediction micro-operation to generate the predicted result vector. In the described embodiments, when executing the prediction micro-operation to generate the predicted result vector, if the predicate vector is received, for each element of the predicted result vector for which the predicate vector is active, otherwise, for each element of the predicted result vector, generating the predicted result vector comprises setting the element of the predicted result vector to true.
|Apparatus For Storing Instructions In A Multithreading Microprocessor - A circuit for selecting one of N requesters in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requestor. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.
|METHOD AND APPARATUS FOR ON-CHIP TEMPERATURE - When an instruction is executed on an integrated circuit (IC), an activity level and temperature are measured. A relationship between the activity level and temperature is determined, to estimate the temperature from the activity level. The activity level is monitored and is input to a scheduler, which estimates the IC temperature based on the activity level. The scheduler distributes work taking into account the temperature of various IC regions and may include distributing work to the IC region that has a lowest estimated temperature or relatively lower estimated temperature (e.g., lower than the average IC or IC region temperature). When the utilization level of one or more IC regions is high, the scheduler is configured to reduce the clock speed or the voltage of the one or more IC regions, or flag the regions as being unavailable for additional workload.
|PIPELINE PROCESSOR AND AN EQUAL MODEL CONSERVATION METHOD - A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.
|PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS - A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is determined based on a number of instructions a younger dependent instruction is located from a corresponding older (in program order) instruction. When the younger dependent instruction is allocated an entry in a multi-cycle scheduler, this distance value may be used to locate an entry storing the older instruction in the scheduler. When the older instruction is picked for issue, the younger dependent instruction is marked as pre-picked. In an immediately subsequent clock cycle, the younger dependent instruction may be picked for issue, thereby reducing the latency of the multi-cycle scheduler.
|ISSUING INSTRUCTIONS WITH UNRESOLVED DATA DEPENDENCIES - The described embodiments include a processor that determines instructions that can be issued based on unresolved data dependencies. In an issue unit in the processor, the processor keeps a record of each instruction that is directly or indirectly dependent on a base instruction. Upon determining that the base instruction has been deferred, the processor monitors instructions that are being issued from an issue queue to an execution unit for execution. Upon determining that an instruction from the record has reached a head of the issue queue, the processor immediately issues the instruction from the issue queue.
|Heuristic backtracer - A heuristic backtracer is described. In one embodiment, a scanner scans a stack of an application for a pointer to a word of a machine code of the application. A preceding byte locator identifies one or more bytes immediately preceding the pointed-to machine code. A parser parses the one or more bytes immediately preceding the pointed-to machine code of the machine code for a call instruction. A return address identifier determines the pointed-to as a return address when the one or more bytes constitute the call instruction.
|Processing Unit Incorporating Issue Rate-Based Predictive Thermal Management - A circuit arrangement and method utilize an issue rate-based predictive thermal management technique in a microprocessor or other integrated circuit that tracks the rate in which instructions are issued to one or more execution units in the processing unit, and selectively delays the issuance of subsequent instructions to the execution unit(s) based upon the tracked issue rate to predictively control the thermal output of the integrated circuit.
|INSTRUCTION CONTROL DEVICE - A processor which executes threads having different characteristics is provided with an instruction control device. In the instruction control device, a first instruction control unit issues an instruction included in a first instruction sequence to an instruction execution unit. In addition, a second instruction control unit issues an instruction included in a second instruction sequence to the instruction execution unit. Here, the delay time of the second instruction control unit is shorter than the delay time of the first instruction control unit.
|PROCESSOR AND METHOD FOR SYNCHRONOUS LOAD MULTIPLE FETCHING SEQUENCE AND PIPELINE STAGE RESULT TRACKING TO FACILITATE EARLY ADDRESS GENERATION INTERLOCK BYPASS - A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.
|Processor architectures for enhanced computational capability - A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.
|Time stamping transactions to validate atomic operations in multiprocessor systems - A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor cores, where each transaction has one or more packets. The transactions include atomic transactions. The bridge element comprises a buffer unit storing a time stamp for each packet sent or received. Furthermore, a multi-core multi-node processor system is provided that has debug hardware to capture and time stamp intra-node and/or inter-node transaction packets. Atomic operations are, for example, atomic read-modify-write instructions.
|Method and Apparatus for Back to Back Issue of Dependent Instructions in an Out of Order Issue Queue - A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.
|Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch - A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
|Preferential Dispatching Of Computer Program Instructions - A computer processor that includes a plurality of execution pipelines, each execution pipeline including a configuration of one or more execution units of the processor, each execution pipeline characterized by an execution pipeline type, each execution pipeline type determined according to the types of computer program instructions executed in each execution pipeline; a plurality of hardware threads of execution, each hardware thread including computer program instructions characterized by instruction types, each hardware thread including sequences of instructions of a same instruction type, the sequences interspersed with instructions of other types; and an instruction dispatcher capable of dispatching instructions preferentially during a predefined preference period from a preferred hardware thread to a particular execution pipeline in dependence upon whether the preferred hardware thread presents a sequence of instructions, ready for execution from the preferred hardware thread, of a type for execution in the particular execution pipeline.
|Issue policy control within a multi-threaded in-order superscalar processor - A multi-threaded in-order superscalar processor
|System and Method for Adaptive Run-Time Reconfiguration for a Reconfigurable Instruction Set Co-Processor Architecture - A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.
|BLOCK ALLOCATION TIMES IN A COMPUTER SYSTEM - A method and apparatus improves the block allocation time in a parallel computer system. A pre-load controller pre-loads blocks of hardware in a supercomputer cluster in anticipation of demand from a user application. In the preferred embodiments the pre-load controller determines when to pre-load the compute nodes and the block size to allocate the nodes based on pre-set parameters and previous use of the computer system. Further, in preferred embodiments each block of compute nodes in the parallel computer system has a stored hardware status to indicate whether the block is being pre-loaded, or already has been pre-loaded. In preferred embodiments, the hardware status is stored in a database connected to the computer's control system. In other embodiments, the compute nodes are remote computers in a distributed computer system.
|MACROSCALAR PROCESSOR ARCHITECTURE - A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one or more primary instructions of a program loop that comprise a machine executable program. For each of the primary instructions received, at least one of the iteration units generates multiple secondary instructions that correspond to multiple loop iterations of the task of the respective primary instruction when executed by the one or more execution units. Other methods and apparatuses are also described.
|PROCESSES, CIRCUITS, DEVICES, AND SYSTEMS FOR SCOREBOARD AND OTHER PROCESSOR IMPROVEMENTS - A method of instruction issue (
|System and Method for Language Specification - Described are a system and method for language specification. The device may include (a) a processor running an operating system and (b) an image capturing device scanning an image. The operating system is configured to display a user interface. The image includes data that is transmitted to the operating system to execute a language installation protocol. The protocol indicates a display language for the user interface.
|ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
|System and Method for Issue Schema for a Cascaded Pipeline - The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having four or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to: (1) receiving an issue group of instructions; (2) scheduling the instructions in program order received; and (3) executing the issue group of instructions in the cascaded delayed execution pipeline unit. The present invention can also be viewed as providing methods for providing a group priority issue schema for a cascaded pipeline. The method includes: (1) receiving an issue group of instructions; (2) scheduling the instructions in the program order received; and (3) executing the issue group of instructions in the cascaded delayed execution pipeline unit.
|PROCESSOR AND SIGNATURE GENERATION METHOD, AND MULTIPLE SYSTEM AND MULTIPLE EXECUTION VERIFICATION METHOD - A processor performs instruction execution regardless of a program order. An execution unit executes an instruction, and transmits end information of the instruction whose execution has ended. A retire unit receives the end information, rearranges a result of the instruction whose execution has ended in a program order to determine the instruction execution, and transmits completed instruction information which reports that the instruction execution has been determined. A signature generation unit receives the completed instruction information from the retire unit, and generates a signature using the completed instruction information.
|SYSTEM AND METHOD OF ACCESSING A DEVICE - A method of accessing a device is provided. A command is received from an agent, over a network, for executing at least one instruction for accessing the device. Information is sent to the agent, over the network, regarding the execution of the at least one instruction.
|MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE - The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
|METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING - A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine located within the execution unit, the method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, subsequent to obtaining the number of instructions per cycle, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine when the instructions are independent of each other without incurring significant loss of performance until an issue queue in the instruction scheduling unit is filled with instruction data.
|Selecting Fixed-Point Instructions to Issue on Load-Store Unit - Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.
|Result path sharing between a plurality of execution units within a processor - A processor
|SYSTEM AND METHOD OF LOAD-STORE FORWARDING - A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to any other reason. In a first pass, the youngest store instruction in program order of all store instructions older than a load instruction is found and an indication to the store buffer entry holding information of the youngest store instruction is recorded. In a second pass, the recorded indication is used to index the store buffer and the store bypass data is forwarded to the load instruction. Simultaneously, it is verified if no new store, younger than the previously identified store and older than the load has not been issued due to out-of-order execution.
|MULTIPLEXING PER-PROBEPOINT INSTRUCTION SLOTS FOR OUT-OF-LINE EXECUTION - The present invention provides a probe system and method for multithreaded user-space programs. The system includes an instrumentation module that enables single stepping out of line processing for multithreaded programs, an establish probepoint module that divides up an area of the probed program's memory into a plurality of instruction slots, an ensure slot assigned module that ensures that an instruction slot is assigned to a probepoint, a slot acquisition module that acquires the instruction slot for the probepoint, stealing a slot from another probepoint as needed, and a free slot module that relinquishes the instruction slot owned by the probepoint when the probepoint is being unregistered.
|MULTITHREAD EXECUTION DEVICE AND METHOD FOR EXECUTING MULTIPLE THREADS - A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution speed information memory that stores target execution speed information of the instruction; an execution speed monitor that monitors an execution speed of the instruction; a feedback control unit that commands the instruction issue unit to issue the instruction such that the execution speed of the instruction approximately corresponds to the target execution speed information.
|PROCESSING CORE WITH SPECULATIVE REGISTER PREPROCESSING - A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values stored in a floating point register file, to decompress compressed values stored in a register file, to decrypt encrypted values stored in a register file, or to otherwise preprocess data that is stored in an unprocessed form in a register file.
|MECHANISM FOR SUPPRESSING INSTRUCTION REPLAY IN A PROCESSOR - A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
|Multi-Execution Unit Processing Unit with Instruction Blocking Sequencer Logic - A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency operation to one execution unit, while blocking instructions from the instruction buffer logic from being issued to that execution unit. In addition, the blocking of instructions from being issued to the execution unit does not affect the issuance of instructions to any other execution unit, and as such, other instructions from the instruction buffer logic are still capable of being issued to and executed by other execution units even while the sequencer logic is issuing the plurality of instructions associated with the long latency operation.
|MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES - A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.
|MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT - Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed.
|Replay Reduction for Power Saving - In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
|COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A computer system used to execute an application includes a motion sensing unit, a processor and an instruction transfer unit. The motion sensing unit senses a gesture of a human body and generates an input instruction based on the gesture. The processor executes the application (or a game). The instruction transfer unit is connected with the motion sensing unit and the processor and serves as a communication interface between the motion sensing unit and the application. The instruction transfer unit transfers the input instruction to a control command, and the processor controls and executes the application in accordance with the control command.
|APPARATUS AND METHOD FOR CONTROL PROCESSING IN DUAL PATH PROCESSOR - A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units and operable to perform control processing operations. The decode unit is operable to receive and decode instruction packets of a bit length of 64 bits and to detect if the instruction packet defines three control instructions each having a length of 21 bits. The decode unit detects that the instruction packet comprises the three control instructions. The control instructions are supplied to the processing channel for execution in the order in which they appear in the instruction packet. The detection uses an identification bit in the instruction packet.
|Unified Collector Structure for Multi-Bank Register File - One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
|DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS - A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
|MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS - A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.
|Method And Systems For Providing Transaction Support For Executable Program Components - Methods and systems are described for providing transaction support for executable program components. In one embodiment, transaction information is associated with an instruction included in an executable addressable entity included in an executable program component generated from source code written in a programming language, wherein the transaction information is independent of the source code and the programming language. Further, an access to the instruction is detected for executing by a processor. A transaction operation to perform in association with the executing of the instruction is determined based on the transaction information associated with the instruction. The transaction operation is performed in association with the executing of the instruction, wherein the transaction operation is performed by a program component other than the executable program component including the executable addressable entity.
|EARLY BRANCH DETERMINATION - A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to the first command issuing, within the computer processor, wherein execution of the second command by the computer processor includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, the method includes a third command issuing within the computer processor, wherein execution of the third command by the computer processor includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.
|UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPECULATIVE INSTRUCTIONS - Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields.
|Credit-Based Streaming Multiprocessor Warp Scheduling - One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.
|Information processing apparatus and instruction decoder for the information processing apparatus - An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.
|CONTROL METHOD AND SYSTEM OF MULTIPROCESSOR - A control method and a system for dispatching the execution sequence of the processes in a multiprocessors system so as to dispatch an operation sequence for executing different operation programs by a monitoring processor and a plurality of target processors. The monitoring processor obtains operation status of other processors from a buffer; the monitoring processor selects at least one target processor according to the operation status; the monitoring processor assigns the target processor to execute a corresponding slave operation program, and modifies the operation status of the target processors in the buffer module; and the monitoring processor repeats the setting the operation status and assigning other target processors to execute corresponding operation programs, till a master operation program is completed.
|MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER - A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.
|INVERTING DATA ON RESULT BUS TO PREPARE FOR INSTRUCTION IN THE NEXT CYCLE FOR HIGH FREQUENCY EXECUTION UNITS - A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
|Pipe scheduling for pipelines based on destination register number - A data processing apparatus
|Reduced Instruction Set - A method of reducing a set of instructions for execution on a processor, the method comprising: extracting information from a first instruction of the set of instructions; identifying unencoded space in one or more further instructions of the set of instructions; replacing the unencoded space of the one or more further instructions with the extracted information of the first instruction so as to form one or more amalgamated instructions; and removing the first instruction from the set of instructions.
|METHOD TO DYNAMICALLY DISTRIBUTE A MULTI-DIMENSIONAL WORK SET ACROSS A MULTI-CORE SYSTEM - A method provides efficient dispatch/completion of an N Dimensional (ND) Range command in a data processing system (DPS). The method comprises: a compiler generating one or more commands from received program instructions; ND Range work processing (WP) logic determining when a command generated by the compiler will be implemented over an ND configuration of operands, where N is greater than one (1); automatically decomposing the ND configuration of operands into a one (1) dimension (1D) work element comprising P sequentially ordered work items that each represent one of the operands; placing the 1D work element within a command queue of the DPS; enabling sequential dispatching of 1D work items in ordered sequence from to one or more processing units; and generating an ND Range output by mapping the 1D work output result to an ND position corresponding to an original location of the operand represented by the 1D work item.
|METHOD OF SCHEDULING A PLURALITY OF INSTRUCTIONS FOR A PROCESSOR - A method of scheduling a plurality of instructions for a processor comprises the steps of: establishing a functional unit resource table comprising a plurality of columns, each of which corresponds to one of a plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a functional unit of the processor; establishing a ping-pong resource table comprising a plurality of columns, each of which corresponds to one of the plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a read port or a write port of a register bank of the processor; and allotting the plurality of instructions to the plurality of operation cycles of the processor and registering the functional units and the ports of the register banks corresponding to the allotted instructions on the functional unit resource table and the ping-pong resource table.
|ZERO VALUE PREFIXES FOR OPERANDS OF DIFFERING BIT-WIDTHS - A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
|USING VECTOR ATOMIC MEMORY OPERATION TO HANDLE DATA OF DIFFERENT LENGTHS - A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported data lengths. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector of length N, wherein the virtual interior loop includes one or more vector atomic memory operation (AMO) instructions, used to resolve false conflicts.
|EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT - An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
|INSTRUCTION CONTROL CIRCUIT, PROCESSOR, AND INSTRUCTION CONTROL METHOD - In a vector processing device, a data dependence detecting unit detects a data dependence relation between a preceding instruction and a succeeding instruction which are inputted from an instruction buffer, and an instruction issuance control unit controls issuance of an instruction based on a detection result thereof. When there is a data dependence relation between the preceding instruction and the succeeding instruction, the instruction issuance control unit generates a new instruction equivalent to processing related to a vector register including the data dependence relation with the succeeding instruction in processing executed by the preceding instruction and issues the new instruction between the preceding instruction and the succeeding instruction, and thereby a data hazard can be avoided between the preceding instruction and the succeeding instruction without making a stall occur.
Patent applications in class INSTRUCTION ISSUING
Patent applications in all subclasses INSTRUCTION ISSUING


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It's hard to take a fresh look at a book that has already been so well reviewed, but I feel that I do have a few more worthwhile comments, hence another review.Even though PUZZLE PALACE has been around for eighteen years, it still seems to be the best researched book on NSA that's available. It would be nice if Bamford could update us on what has happened in those intervening years.None of the following is classified information. I was an enlisted man in the Army Security Agency, stationed in the Philippines, from 1955 to 1957. I had been trained as a French Linguist at the Army Language School. It wasn't until I got to the Philippines that I even knew that there was an organization known as the National Security Agency (NSA). Even more amazing is the fact that, until I read Bamford's book, I had no idea how what I was doing fit into the scheme of things. Thanks, James Bamford, for clearing that up for me some forty five years later. Better late than never,... read more
When "The Puzzle Palace" first came out in 1982, it caused a certain amount of controversy and angst. Bamford now has a new book on NSA scheduled to appear this Spring. I wonder what it will contain? "The Puzzle Palace" was quite a good job of investigative reporting, especially considering the customary reluctance of NSA to reveal much about itself. I found "The Puzzle Palace" an interesting read, and I learned much from it that I had not learned during my 20 years of previous occasional contact with NSA. The book is not friendly to NSA, but neither is it muckraking.In the 1980s I wished that "The Puzzle Palace" had not been written; it seemed to me to contain considerable material that would have best been left unpublished (and would have been if the United States had anything like the British Official Secrets Act.) Looking back from the vantage point of 2001, I note only one brief item in "The Puzzle Palace" that I know harmed... read more
The book is nothing short of sensational, for two reasons: itis the first and still the only really comprehensive look at globalsignals intelligence operations as dominated by the National Security Agency; and second, because all of his research was done using only open sources, including unclassified employee newsletters at Alice Springs, and he did a great job of making the most out of legally and ethically available information. James is still around, working on another book about SIGINT, and I believe that only he will be able to top this one.
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Some of the names on the move ahead of the open.» Read More
Corporate finance adviser Hampleton Partners' report said that $9.4 billion has been spent in the past three years to acquire so-called "Internet of Things" suppliers, with $5 billion, or more than half of the total, in the first nine months of 2014.. The report, which studied more than 100 transactions in the category, said that early consolidation has been led by...
Nov 6- Auto parts maker Visteon Corp reported a 33 percent rise in quarterly revenue, helped by the acquisition of Johnson Controls Inc's electronics business and increased global vehicle production. The company's revenue rose to $1.97 billion in the third quarter ended Sept.30, from $1.48 billion a year earlier. Visteon reported a net loss attributable to...
Oct 30- Johnson Controls Inc posted a better-than-expected quarterly profit, driven by higher sales of its car seats in North America and a lower expected tax bill. Johnson Controls supplies parts to automakers such as Toyota Motor Corp and General Motors, who have benefited from increasing vehicle sales in North America. Net income attributable to Johnson...
Oct 30- Johnson Controls Inc's profit tripled in the fourth quarter, driven by higher sales of its car seats in North America and a lower income tax provision. Net income attributable to Johnson Controls rose to $309 million, or 46 cents per share, in the quarter ended Sept. 30 from $105 million, or 15 cents per share, a year earlier. Revenue rose 2.6 percent to $10.98...
Sometimes different divisions of a company shouldn't be under the same roof. Cramer says this is one of those times.
Sept 10- Auto-parts maker Visteon Corp is exploring a plan to split into two companies focused on electronics and climate controls, Bloomberg reported, citing people familiar with the matter. Visteon, once a part of Ford Motor Co may consider selling or spinning off the electronics business, the report said.
Some of Friday's midday movers:
July 18- U.S. auto parts maker Johnson Controls Inc reported a 3 percent rise in quarterly revenue, as demand rose for its car seats, and the company said it expected its cooling and heating systems business to return to growth in the current quarter.
Some of the names on the move ahead of the open.
July 18- Johnson Controls Inc, the largest U.S. auto parts maker, reported a 3 percent rise in quarterly revenue, as revenue from its car seats and interior parts business rose 7 percent. Demand in the business was driven mainly by China, which contributed $1.8 billion to the division's revenue of $5.7 billion in the third quarter ended June 30.
Take a look at some of Monday's midday movers:
The Treasury Department auctioned $35 billion in five-year notes at a high yield of 1.732 percent, the rate highest since May 2011.
Some of the names on the move ahead of the open.
US stock index futures seesawed as investors awaited another wave of major earnings, including Dow-listed Boeing and Procter & Gamble.
Some of Wednesday's midday movers:
If you're looking to build a portfolio of stocks, here's how Cramer would put money to work right here and right now.
If you've got $10,000 for investment, here's how Cramer would put that money to work, right here and right now.
So far, the stock market has looked past the weather impacts on manufacturing, housing, consumer spending and even hiring.
Thursday's midday movers:
CNBC's "Earnings Squad" previews the quarterly earnings reports for Johnson Controls, Netflix, and McDonald's, with CNBC's Melissa Lee.