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Daniel Craig drives the new Range Rover Sport into New York
It was a star studded event in New York. The unveiling of all new 2014 Range Rover Sport on the eve of 2013 New York Auto Show, saw Daniel Craig aka, James Bond drive the car down into Manhattan. The event also witnessed the presence of football star, Thierry Henry and NFL player Michael Strahan. Read on to see live images and video from the official unveiling.
2013 Range Rover STARTECH REFINEMENT program at 2013 Geneva Motor Show
2013 Range Rover STARTECH REFINEMENT program at 2013 Geneva Motor Show. STARTECH has also incorporated a new rear bumper design while a stainless steel sport exhaust system is added which is as quiet as a whisper.
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Land Rover launched the new 2013 Range Rover in last year. It has now emerged, that their new SUV, which they claim is the best yet, is sold out in the US. 2013 Range Rover SUV comes with a minimum 6 months wait period in the US.
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The new Range Rover debuted which globally recently will be launched for customers in India on the 30th of November 2012. This announcement comes as…
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A Kahn DesignŌĆÖs latest collection of unique Range Rovers is Mille Miglia edition, based on recently launched 2013 Range Rover Sport. The 2013 Land Rover…


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A real-valued FFT processor implements Bergland's real-valued FFT and uses unique interstage switching/delay modules to reduce pipeline latency. Modified hybrid floating point arithmetic is also employed to provide maximum SNR. The real-valued FFT processor is particularly suited for a DMT engine and, in a multichannel CO ADSL application, the DMT engine can be multiplexed between the channels to provide an economic, low cost CO solution.
1. A pipelined, real-valued Fast Fourier Transform processor comprising:
a plurality of pipelined, Bergland butterfly computation units to compute a portion of a real-valued fast Fourier transform on a block of data; and
interstage switch/delay modules interconnecting the plurality of Bergland butterfly computation units, the switch/delay modules reordering data for a subsequent Bergland butterfly computation unit, wherein at least one delay in the switch delay/modules is reused to reduce latency of the pipelined, real-valued Fast Fourier Transform processor.
2. The Fast Fourier Transform processor, as per
3. The Fast Fourier Transform processor, as per
4. The Fast Fourier Transform processor, as per
5. The Fast Fourier Transform processor, as per
6. A DMT engine comprising the real-valued Fast Fourier Transform processor of
7. The DMT engine, as per
The invention relates generally to an FFT processor particularly suited for Discrete Multitone (DMT) processing, and in particular, to a very high-speed DMT engine that is multiplexed between the channels in a multichannel central office asymmetric digital subscriber line (CO ADSL) application.
CDSL DMT is at the core of digital subscriber line (DSL) modems. In a multichannel CO ADSL application, a DMT engine does the core processing. Each channel must have a DMT engine or a very fast DMT engine has to be multiplexed among the channels. The DMT signal is produced in the transmitter and is formally obtained by summing pairs of orthogonal sine/cosine waves, each pair having frequency different from all other pairs in the sum. Sine and cosine waves in each pair are amplitude modulated by the data item corresponding to that pair (also called tone). When the frequencies of the tones are harmonically related, as is usually the case, the most natural and easy way to generate the DMT signal is by means of an Inverse Discrete Fourier Transform, itself almost always executed with a FFT type of algorithm to substantially reduce the amount of computations performed. The DMT signal is real valued (as opposed to complex valued) so the IFFT input is conjugate symmetric. Since in a conjugate symmetric data block, half of the data is redundant (one half can be obtained from the other half by negating the imaginary part) the size of the IFFT used can be half of that usually required. This comes with a price, however, in the form of a special formatting of the data before the IFFT, called pretwiddling pass, which involves multiplications by twiddle factors and grouping. A Forward FFT performs demodulation of the DMT signal in the receiver. Here again, since the input to the Forward FFT is real valued, a half-size FFT algorithm can be used, with the price paid being the so-called post twiddling computation on the result of the Forward FFT.
Proposals have been made for more effectively producing the DMT sum of sine/cosine pairs. Some use transforms to speed up the FFT, e.g. FFT through Walsh Transform, while others have used combinations of sine and cosine transforms which are inherently real, e.g. Hartley transform or similar real valued FFTs. However, the real valued FFT algorithm used in the present invention has never been considered or even mentioned in the context of DSL modulators/demodulators, nor has it been used for a computational pipeline for a DMT engine with substantially reduced computational time. In addition, CO ADSL applications impose constraints on a DMT engine's latency and SNR, which have not been considered in previous implementations of processors using the algorithm.
The real-valued FFT processor of the present invention implements Bergland's real-valued FFT and uses unique interstage switching/delay modules to reduce pipeline latency. In one embodiment, modified hybrid floating point arithmetic is also employed to provide maximum SNR. The real-valued FFT processor is particularly suited for a DMT engine and, in a multichannel CO ADSL application, the DMT engine can be multiplexed between the channels to provide an economic, low cost CO solution. Even though algorithms exist that are more efficient in terms of computation speed, Bergland's algorithm is believed to be the most economical in resources without particularly impacting speed and, thus, is more fit than the others for a multi-channel CO ADSL application where cost-effectiveness is of a prime importance.
As is known in the art, given a series of N samples, x(n), its discrete Fourier transform, X(k), is:
The widespread application of the DFT to many fields of digital signal processing was the result of the rediscovery in the mid-1960s by Cooley and Tukey of a fast algorithm for computing the DFT, know as the Fast Fourier Transform. In a radix-r FFT, as developed by Cooley and Tukey, the DFT is decomposed into r-point DFT calculations and multiplications by rotational vectors, or so-called �twiddle factors.� These computations form the basic computational element, typically called a �butterfly.� Interconnection of the butterflies provides for the radix-r FFT. A Cooley-Tukey radix-2 decimation in time complex FFT is shown diagrammatically in
It should be noted that only the first set of butterfly computations for each group is illustrated for clarity, even though butterfly computations are performed N/2 times in each group. The set shown for each group is applied sequentially to all of the data items in the group. For instance, in group 1, the butterfly is illustrated being applied to the A0(0) and A0(8) data items. The butterfly is then sequentially applied to the A0(2) and A0(9) data items, the A0(3) and A0(10) data items, etc. Similarly, for group 2, the set of butterflies illustrated comprises a power 0 (i.e., W0) butterfly applied to the A1(0) and A1(4) data items, while a power 4 butterfly is applied to the A1(8) and A1(12) data items. This set is applied sequentially to the data items, i.e., the power 0 butterfly is next applied to the A1(1) and A1(5) data items, while the power 4 butterfly is applied to the A1(9) and A1(13) data items, etc.
The Cooley-Tukey radix-2 butterfly 102 is illustrated in
A real valued FFT algorithm was described by Glenn Bergland in �A Fast Fourier Transform Algorithm for Real-Valued Series.� Bergland's algorithm works by eliminating the redundant computations in the Cooley-Tukey FFT algorithm when it is known that the input signal is real valued (for the Forward FFT) or has conjugate symmetry (for the Inverse FFT). The net result is an algorithm requiring one less computational pass, than the regular complex FFT.
The redundant computations eliminated by the Bergland algorithm are described with reference to the Cooley-Tukey algorithm in
A direct mapping of the Bergland algorithm to the Cooley-Tukey algorithm for the forward FFT is illustrated in
Also, as shown, for the Bergland algorithm, no computations are necessary for the butterflies with the N/4 power of W, i.e. W=−j. Rather, the results of these computations can be achieved by a negation and a relabeling of half of the current outputs as imaginary inputs for the next group. This is indicated by the �no operations necessary� areas. For instance, the A1(12) value is simply relabeled as the imaginary part of the A2(8) value for the next group of computations. This allows for a computational group to be eliminated (except for one addition and one subtraction) by performing the negation and relabeling prior to the �no operation necessary points� and performing the next set of computations during these points. The final algorithm with the computational group eliminated is illustrated in
The Bergland butterfly takes two inputs for each half of the butterfly. For the W=1 (power 0) butterflies, only real values are input, however, these real values are treated as complex values. Thus, the butterfly computations are performed on two complex inputs created from the four real inputs. The resulting �real� parts are stored separately from the resulting �imaginary� parts. The �real� and �imaginary� parts resulting from the addition are each one of the real terms generated by a group. The result of the subtraction is one of the independent complex terms generated by a group. Its real part is stored separately from its imaginary part.
The input A corresponds to the first input to the butterfly, B to the second, C to the third and D to the fourth. Hence, for instance, for the butterfly illustrated for group 1 in
For the W 1 butterflies, complex values (with their imaginary and real parts stored separately) are operated on and the second complex term is multiplied by the appropriate power of the twiddle factor W. The input A still corresponds to the first input to the butterfly, B to the second, C to the third and D to the fourth, however, the C and D inputs are crossed during the calculations for butterflies with W 1, as previously described. Hence, for instance, for the power of 2 butterfly illustrated for group 2 in
The Bergland algorithm is reversed to perform an IFFT. This is illustrated in
The real-valued FFT processor according to the principles of the present invention with a computational pipeline based on the Bergland algorithm provides distinct advantages when it is a part of a DMT engine used in the context of ADSL. The Bergland algorithm does not require a pretwiddle or post twiddle computing pass. This means further increases in computation speed. The computation speed is comparable to radix-4 FFTs, however, with less round off errors in fixed-point implementations, such as the ones currently employed for ADSL. Further, radix-4 FFTs have a more complicated butterfly, which makes it more prone to overflows in a fixed-point implementation. On the other hand, the Bergland algorithm uses a butterfly almost identical to the simpler radix-2 butterfly, even though geometrically (by data addressing pattern) the Bergland butterfly looks like a radix-4 algorithm.
The real-valued FFT processor architecture of the present invention uses a pipelined architecture to implement the Bergland algorithm. A pipelined architecture is a known computational structure permitting extremely fast algorithm execution, while maintaining hardware resources at a manageable level. For example, some pipelined FFT processor designs are described in U.S. Pat. Nos. 6,081,821 and 4,534,009.
As illustrated in
Illustrated is an exemplary implementation for N=512. For N=512, there are eight butterfly processors 502 because, when N=2m, the number of butterfly stages needed for the Bergland algorithm is equal to m−1, including the multiplierless stage with one addition and one subtraction.
The I/O interface of processor 500 is preferably provided by conventional RAM type access. That is, input data is fed into and stored in input RAM 506 a, while output data is stored in output RAM 506 b. I/O RAMs 506 are preferably accessed as conventional RAM outside of processor 500, while internally it acts as a four-way pipeline. That is, four contiguous data words are read out of input RAM 506 a simultaneously to the pipeline and four contiguous data words are stored into output RAM 506 b simultaneously. For an implementation with N=512, as shown, I/O RAMs 506 store at least 512 words and are accessed internally as 4 FIFOs that are 128 words deep(to provide simultaneous access to four contiguous data words). Preferably, the unique address pattern of the Bergland FFT algorithm is embedded in the address decoders of I/O RAMs 506 so that no access time penalties are incurred as they would be if lookup table indirect addressing were performed.
Pipelined processors are known for having inherent latency, which is the period of time needed for a batch of data to exit the pipeline after it has been loaded. Latency directly impacts execution speed, and large penalties are seen in speed if a pipelined processor is used in a start/stop mode, i.e. it is not fed with a continuous stream of data. This is a very likely situation in a multichannel ADSL CO transmitter. Latency is minimized in the real-valued FFT processor architecture 500 of the present invention by performing interstage data routing with interstage switch/delay modules designed to reuse delays as described below.
In addition to substantially reduced latency, one embodiment of processor 500 provides for the appropriate level of SNR (in the sense of Signal to Quantization noise Ratio) required by ADSL DMT systems by using a modified hybrid floating point internal representation with guard bits. Hybrid floating point representation is a known technique, however, the implementation of this technique in processor 500 is modified from the usual implementation, allowing processor 500 to match the speed of processing exponents to the speed of the data processing units. The last pipeline stage also uses a scaled denormalizing technique (for removing the exponents) so as to eliminate output arithmetic overflows. The scaled denormalizing technique is performed by the overflow prevention circuit 508 (also referred to as output normalizing circuit). Overflow prevention circuit 508 is shown after output RAM 506 b, however, it can be place before output RAM 506 b. Placing overflow prevention circuit 508 before output RAM 506 b is more economical since, in this case, there would not be a need to store the exponents of the final result in the output RAM 506 b.
The hybrid floating point representation is used to eliminate interstage overflow problems without sacrificing processing speed. Parseval's theorem as applied to the Discrete Fourier Transform states that the energy of the transformed samples is N times that of the block of signal samples being transformed, where N is the size of the transform. That means a growth in the magnitude of the results is observed in each computational pass of the algorithm. While almost harmless in a floating point computing environment, this growth can cause serious problems when fixed point data format is used. Floating point numbers are �autonormalizing�, that is they automatically adjust the range of numbers that are currently represented at the expense of lack of precision. Under normal conditions they seldom underflow (i.e., try to represent unrepresentably low magnitude values) or overflow (i.e., try to represent values that are so big that they are out of any representable range).
Processor 500, however, preferably uses fixed point representation. Fixed point numbers span a set of values in a range with equal precision, and cannot represent values outside that range. Usually that range is from some minimum negative number up to some maximum positive one. It is said that overflow occurs if values outside that range have to be represented. With algorithms known to produce intermediate results that grow in magnitude, as the FFT, an overflow is very likely to occur in a fixed point system.
The usual saturation or clipping at the max positive (or negative) value, as performed in digital filters, is unacceptable if an overflow has to be handled in any of the computational stages of an FFT processor, except the final one. The reason is that the error from a saturated data word participates in the computation of many subsequent results (how many depends on the current stage), which in turn will be wrong, producing a snowball effect of errors. A classic approach to handle this situation is to scale the data words by dividing them by two (performing 1 right shift) before they enter the computation. In a radix 2 FFT, this almost guarantees no overflow. Similarly, in radix 4 FFTs, the scaling must be a divide by 4. While this works, this unconditional divide by 2 (or 4) lowers the signal to noise ratio to a value that might be unacceptable in certain situations. For instance, for the 512-point sample size implementation, a processor 500 of the present invention has 8 stages as shown. This means 8 right shifts would be used resulting in an SNR below 50 dB. A SNR of at least 60 dB, however, is required for ADSL DMT operation.
Another approach to preventing overflow is the so-called block floating point arithmetic. In this format, the arithmetic is done as usual on a fixed point hardware and, when overflow occurs, the result is corrected by scaling the result, while an exponent data word (one and the same for the entire FFT) is incremented for each divide by. At the end of a pass, all intermediate results are resealed by the number of exponent increments during the previous pass. That way all intermediate values are in the same range for the next computational stage. While attractive for not permitting overflows, block floating point arithmetic presupposes a resealing pass if an overflow had occurred in the previous pass, which slows algorithm executions and adds complexity to both software or hardware implementations. Also, permitting an overflow to occur, while still being able to correct the final result by rescaling, requires arithmetic circuits of greater width than the data words.
A modification of the block floating point scheme uses guard bits. In a guard bit block floating point scheme, the two or three (depending on the FFT radix) MSBs of a data word are required to be the same, i.e. equal to the sign bit. If an intermediate result spreads out into the guard bits, it is assumed that it will be likely to generate a real overflow in subsequent computations, although it is perfectly valid per se. This guard bit overflow condition is trapped, and acted upon in the above-explained block floating point manner. It is seen that in the guard bit case, the arithmetic units do not have to have more bits than the data words, thus, simplifying the hardware. The price to pay is a constant reduction in the dynamic range; 6 dB per guard bit.
The use of the guard bit method is justified when the dynamic range to be covered is somewhat less than the full dynamic range offered by the word length used throughout the digital hardware. This is the case for ADSL, where the requirement is an SNR at least 60 dB and the standard word length for fixed point arithmetic is 16 bits insuring 90 dB of SNR (1 bit is kept for the number sign).
Block floating point processing has to be modified for real time processing that does not permit stopping of computations and that does not necessarily have an easy access to intermediate results, e.g. a high-speed pipelined FFT engine. In those cases a system called hybrid floating point is employed. In a hybrid floating point system each data value has an exponent, but this exponent only grows (because of the nature of the FFT algorithm) so if a normalization of a result has to be performed it is obtained by right shifts only. The arithmetic operations are performed by fixed point hardware only on numbers in the same range. Since each data word carries along its exponent, there is no need for a block rescaling upon overflow, rescaling can be performed at the input of the butterfly processor (the processor executing the core FFT computing operation). That means processor operation without interruption and with guaranteed absence of overflows in all computing stages, at the expense of having an exponent for each data word. This price to pay is insignificant by modem hardware implementation standards. For example a 4 bit exponent is sufficient for FFTs of size up to 32768 and 16 bit data words, the exponent being always considered to be a positive number. This is an increase of 25% in memory requirements to insure an error free fixed point FFT operation.
As described, an embodiment of processor 500 uses such a hybrid floating point representation with guard bits to eliminate interstage overflow problems. Each data value, therefore, has an associated exponent, which is always handled as a positive number. For the exemplary implementation of processor 500, 16-bit fixed-point arithmetic is used with 4 bit exponents associated with each data word. A 4 bit exponent word encompasses shifts from 0 to 15 bit, which is sufficient for 16 bit two's complement numbers. Also, 2 MSBs following the sign bit in the 16 bit word are used as guard bits for the exemplary implementation of processor 500. This provides a SNR of 78 dB throughout the FFT computations.
To perform the hybrid floating point processing, each butterfly processor 502 has an input and output section for the overflow processing. Also, since exponents have to travel in synchrony with their associated data words, the exemplary implementation of real-valued FFT processor 500 (i.e., the pipeline equalizing delay, i.e. FIFOs 504 a-g, and switch network) are either designed to operate on 20 bit words, or two similar pipeline structures are run in parallel, one 16 bit for the data path, the other 4 bit for the exponent path. For instance, each internal FIFO 504 a-g can comprise a data FIFO and an exponent FIFO of equal depth.
The input section of first butterfly processor 502 a derives the initial exponents for the hybrid floating point representation. The data initially enters first butterfly processor 502 a in a regular fixed point format from input RAM 506 a and doesn't have an exponent. Therefore, the exponents are derived from the data. To derive the initial exponents, the three MSBs of each data word are analyzed and each data word is shifted right 0, 1, or 2 positions according to how many guard bits are different from the sign bit. The number of right shifts constitutes the data word exponent. This all happens in the input section of first butterfly processor 502 a. As will be described further below, in order to derive the initial exponents, the input section of first butterfly processor 502 a is identical to the output section of first butterfly processor 502 a.
After first butterfly processor 502 a, each data word input to a butterfly processor 502 b-h may have a different exponent. In order for an arithmetic operation to be meaningful, the data words that it uses must have the same exponent. Except for a power of 0 butterfly, all four data words participate together to produce output results. Therefore, prior to entering the processing section of each butterfly processor 502 b-h, all four input words are adjusted in the input section of each butterfly processor 502 b-h, if needed, so that their exponents are the same.
To make the four exponents equal, the maximum exponent among the four data words is determined and the remaining exponents associated with the other three data words are readjusted such that their exponents are equal to the maximum exponent. In other words, the three data words are shifted to the right by a number of shifts equal to the difference between the maximum exponent found and the corresponding data word exponent.
A classical way to find a maximum of four values is to use three comparisons. Then data word exponents are subtracted from the maximum found. The three comparisons need two levels of processing circuitry (two comparators at the first level, one at the next), followed by a subtraction from the selected maximum, i.e. a fourth level of processing, not counting the intervening multiplexers.
Processor 500, however, implements a modified technique to perform the adjustments faster, without increases to the hardware resources needed. The modified technique allows the speed of processing exponents to be matched to the speed of the data processing units. As described below, this modified technique takes into account the fact that all exponents are positive and forms all possible subtraction results in parallel.
After the input sections of butterfly processors 502 a-h derives or adjusts the exponents, the processing section of butterfly processors 502 a-h performs a butterfly computation. Once the processing section of a butterfly processor 502 a-h performs a butterfly computation, a result word (or multiple result words) may spread into the guard bits. The output sections of the butterfly processors 502 a-h correct this situation. This situation is corrected for in a similar way that the initial exponents are derived from the data as described above. The result word is shifted to the right as much as necessary to make the guard bits the same as the sign bit. The exponent corresponding to that particular result is incremented by the number of right shifts performed on the result word. The incremented exponents and shifted result words are latched into the pipeline on the next pipeline move cycle.
After the last butterfly processor 502 h, result data is in the form of a data word with an associated exponent. Each datum might have a different exponent. In order for the result data block to be used further, e.g. to be fed to a DAC for transmission, the exponents have to be removed in a meaningful way. The exponents are removed by an output normalizing circuit 508.
To remove the exponents, a data dependent conversion can be performed. That means the results are normalized by the maximum data sample, taking the exponent into account. This prevents overflow at the output stage, but some very small samples might disappear. This gain variation will have an adverse effect on the ADSL transmission.
Therefore, output normalizing circuit 508 preferably removes the exponents by making all exponents equal to some constant. The natural constant to choose is zero, since with exponent zero all numeric values will be in their natural fixed point format. This implies shifting up (or left) and, consequently, some numbers might overflow the fixed point range. This situation is very similar to the one of converting floating point numbers to fixed point by casting in C. Clipping or saturating the overflowing values, however, is sufficient at this point since these are output values and no further FFT computations depend on them. Preferably, one supplementary precaution is taken for values that are normally in range, but whose magnitude would overflow by just one bit after a left shift that puts the exponent to zero. This precaution comprises scaling by two the final result of the up shifting.
A second option is to select a fixed scale factor and saturate the values likely to overflow after having been scaled. This conversion problem is common to float/fixed conversions. It should be mentioned that a carefully selected scale factor can minimize these output overflows. In this case, the output normalizing circuit 508 works by comparing the current data sample exponent with the scaling value, and then shifts up or down depending on the result of the comparison, positive or negative. The output normalizing circuit 508 also monitors the output normalized value and saturates it, if it grows above the word width of the output memory.
Specific implementations of an input section, a processing section, an output section, and a switch/delay module will be described next.
Input section 600 equalizes the exponents using, as described above, a technique that takes into account the fact that all exponents are positive and forms all possible subtraction results in parallel. Since the exponents are positive numbers only, they are not compared or converted into two's complement for subtraction. This simplifies the circuitry needed and increases the speed of operation of the input section. Each exponent is subtracted from each other in parallel by four bit subtractors. Thus, there are four groups of subtractors, one for each exponent. For instance, subtractors 602 a correspond to exponent A and, consequently, calculate A−B, A−C, and A−D. Each subtractor group has only three subtractors because the result of subtracting an exponent from itself is known. A subtractor generates a borrow signal (i.e., the Borrow Out will be high) if the subtrahend is bigger than the minuend (e.g., in the case of A−B, a subtractor generates a borrow signal if B>A).
Thus, if an exponent is the maximum exponent, its subtractor group will not generate any borrows. For example, if A is the maximum exponent, then the A group of subtractors 602 a will not generate a borrow signal (e.g., the Borrow Out of each subtractor in group 602 a will be low). This condition is detected by corresponding NOR gates 604. The outputs of NOR gates 604 then select the outputs of multiplexers 606. Continuing the above example, for instance, if group 602 a does not generate any borrow signals (because A is the maximum exponent), NOR gate 604 a detects this and outputs a high. As long as no other exponent is equal to A, then the other subtractor groups 602 b-d generate borrow signals and, consequently, NOR gates 604 b-d output a low. These outputs are supplied to multiplexers 606, and the high from NOR gate 604 a causes the first input of each multiplexer to be output. That is, multiplexer 606 a outputs 0, multiplexer 606 b outputs A−B, multiplexer 606 c outputs A−C, and multiplexer 606 d outputs A−D.
The differences output by the multiplexers are used to control the amount a respective barrel shifter 608 shifts its exponent. Barrel shifters 608 are restricted to shift only to the right. Thus, when A is the maximum exponent, for example, shifter 608 a shifts exponent A zero times to the right. Shifter 608 b shifts exponent B an amount equal to the difference between A and B, i.e. A−B. Likewise, shifter 608 c shifts exponent C an amount equal to the difference between A and C, i.e. A−C, while shifter 608 d shifts exponent D.
The outputs of NOR gates 604 also control multiplexer 610 to output the maximum exponent to the output section as the maximum exponent.
While the example above only described exponent A as being a maximum, it should be noted that it is possible that some exponents are equal and the maximum. In this case, more than one subtractor group will not have any borrows. However, the results of the corresponding subtractions in this case will be equal, so it does not matter which difference is selected to control the corresponding shifters.
Preferably, multiplexers 606 have the structure illustrated at 612. When there is a distinctive maximum exponent, only one of the rows of AND gates receives a high, which enables them to output the values driving their other inputs. All of the other rows receive a low and, therefore, they are disabled (i.e., generate zero as an output). When some exponents are equal and the maximum, then more than one row of AND gates is enabled. However, since the exponents are equal, the values driving the other inputs of the AND gates in these rows are also equal. Thus, there will be no conflict and no misinterpretation of values. In this manner, the more complicated prioritization structures are avoided. These more complicated prioritization structures would be necessary if regular multiplexers are used.
Processing section 700 is designed to compute a butterfly computation in two cycles to reduce the amount of arithmetic circuitry used (using two cycles reduces the number of multipliers needed). The adder/subtractor network 704 calculates the W=1 butterfly, as well as preprocessing some of the data for the W 1 butterfly. As shown in the figure, a W 1 butterfly takes two steps to produce the L and N results. In the first FFT clock period, the multiplication of the twiddle factors with the preprocessed data from subtractors 704 b and 704 c forms the two parts of the L result, i.e. (A−C)*Wr and (B+D)*Wi. These parts are latched on the rising edge of the next FFT clock pulse. The latches do not introduce a pipeline delay since they are clocked every FFT clock cycle, rather than on the pipeline advance clock cycles (the pipeline advances at half the hardware (FFT) clock frequency). Also at this next pulse, the twiddle multiplexers 702 a are reversed and the computation of the second set of results is started. The reversing of the twiddle factors is simply accomplished by clocking twiddle factor multiplexers 702 a with the pipeline move clock. In this way, during the first half of the pipeline cycle, multiplexers 702 a output the data from a twiddle factor table in the arrangement needed to compute the parts of the L result as described above. The changing of the pipeline clock in the second half of the cycle then reverses the output arrangement.
The multiplication of the reversed twiddle factors with the preprocessed data from subtractors 704 b and 704 c forms the two parts of the N result, i.e. (A−C)*Wi and (B+D)*Wr. At the next positive clock edge, the second set of results, as well as the results held in the latches, are added and subtracted, respectively, and passed as result words L and N through the output section and written into the switch/delay module. In addition, result words K and M are passed through the output section and written into the switch/delay module.
The twiddle factors for each butterfly processor 502 are preferably pre-computed and stored in the proper order as a twiddle factor table. The twiddle factor tables are � of the FFT size, regardless of the stage (the position of the butterfly computation unit in the pipeline), i.e. 128 words of sine values and 128 of cosine values for a 512 size FFT. Generally, only the first stage in an IFFT computation needs all 128 distinct (complex) twiddle factors. Subsequent stages need less, e.g. stage 2 needs 64 words, stage 3, 32 and so on. For hardware simplicity and accounting for the fact that memory is inexpensive, all twiddle factor tables are preferably the same size and addressed the same way by the same type of counter. However, to insure correctness of computations, tables that would otherwise be smaller, have repeated values. So in the case where a 64 word table is needed, each value is repeated twice, so the table becomes 128 words. In the case of a 32 word table, each value is repeated four times and so on. The last butterfly processor 502 h does not require a twiddle factor table at all, since it doesn't require multiplications. For a 512 IFFT 128*2*7=1792 words are necessary.
As described above, the output section 800 shifts the result word to the right as much as necessary to make the guard bits the same as the sign bit. The exponent is also increment by 1 for each right shift of the result word. The incremented exponents and shifted result words are then latched into the pipeline on the next pipeline move cycle.
Output section 800 comprises four overflow detectors 802, one for each result word, implemented with an EXOR, EXNOR and a NOR gate. Each overflow detector 802 takes as its input the three MSBs of the corresponding 16 bit result word and produces a 2 bit shift code, which is used to drive a corresponding one of barrel shifters 804. The shift code is 00 if these bits are equal. This represents a shift of 0. It is 01 if bit MSB-2 is different from the others, which represents a shift of 1. Finally, the shift code is 10 if bit MSB-1 is different from the MSB, which represents a shift of 2. Shift code 11 cannot occur. According to the shift code, the corresponding barrel shifter shifts its result word by 0, 1 or 2 positions. Therefore, the appropriate number of right shifts is performed on each result word to make its guard bits equal its sign bit.
In addition, each corresponding exponent is incremented by the number of shifts using adders 806. Note that the exponent for each data word that is used for computations is the maximum exponent, so, in effect, only the maximum exponent has to be incremented. Therefore, only the maximum exponent is provided to the output section in each butterfly processor 502 a-h. It will be readily understood by one of skill in the art, however, that all of the exponents for each data word can be provided to the output section. Thus, to increment the corresponding exponent, the shift code for each result word is added to the maximum exponent via respective adders 806 a-d.
When section 800 is used as the input section of butterfly processor 502 a, exponent adders 806 are not needed. Rather, the shift code itself is passed through as the exponent.
To obtain the data rearrangement for the Bergland algorithm, switch/delay module 900 switches the order of the four input data items of a particular butterfly processor so as to take data items from the appropriate outputs of the previous butterfly processor, as well as delaying some data items as necessary so that they arrive synchronously in the necessary order for the next butterfly processor in the chain. As described, the switch networks 902, 904, and 906 have two positions, �a� and �b.� Switch networks 902, 904, and 906 are in position �a� when the first group of four data items is ready to pass through it. After switch networks 902, 904, and 906 are properly initialized and receive the first four data items, they continue switching between position �a� and �b� in a well defined pattern to insure correct data flow through the corresponding butterfly processor. The switching frequency is the highest for the switch/delay module at the output of the first butterfly unit (i.e., switch/delay module 504 a). For this module, the switch networks 902, 904, and 906 change positions every other data set. The switching frequency divides by two for each subsequent switch/delay module.
The design of switch/delay module 900 reuses delay modules 908 a and 908 b for appropriate data items when in the �b� position. This reuse reduces the latency required to synchronize data items. To understand how switch/delay module 900 properly rearranges the data, while reducing latency, first note that the data element numbers of the four inputs of the first butterfly processor 502 a are as follows (from right to left):
To continue, the data element numbers of the four inputs of the second butterfly processor 502 b are (from right to left):
With this in mind,
The switch networks 902, 904, and 906 are then placed into position �b� so that delays 908 a and 908 b are reused by inputting the data items 1 and 3 into these delays respectively. Data items 0 and 2, along with data items 4 and 6 are output, while data items 5 and 7 are input to delays 908 c and 908 d respectively. As can be seen, this sequence then reoccurs so that the next data items are placed into the proper order.
To understand how latency is reduced, consider that the maximum delay in the first switch/delay module 504 a before data items can be processed would typically be 3. The maximum delay doubles for each subsequent switch/delay module 504 b-g. Adding up the maximum delays from each interstage switch delay network gives 381 delays.
This number is the pipeline latency, and defines the processor speed in a start/stop scenario. In the actual hardware this number has to be doubled, since the butterfly units take two cycles to perform a computation and the pipeline speed is halved. By reusing delays, however, the total latency is reduced. Reusing delays implies reducing the delay line sizes, ultimately making them equal to the smallest non-zero delay in each particular switch/delay block. All of this means that the total delay or latency is cut by two thirds, going from the original 381 down to 127.
Because one specific switch configuration can provide a direct path from the first butterfly unit to the last, pipeline �stop� registers are preferably introduced at the output of each switch/delay module. These registers increase the latency by 7, since there are seven places where they have to be placed. Doubling the numbers because of the two cycle butterfly computation and taking into account the 128 pipeline clock cycles needed to fully load the output memory with the result data we arrive at 522 input clock cycles needed to complete one IFFT of size 512.
Although the present invention has been shown and described with respect to several embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
For instance, it should be noted that the maximum size FFT is only limited by the number of butterfly elements and the specific arrangement and size of the equalizing delays. Every FFT/IFFT up to the size permitted by these elements can be computed with slight changes in the twiddle addressing mechanism and by tapping the result data out earlier in the process, in the sense of getting the result not from the last butterfly computing unit, but from an intermediate one, e.g. for a 64 FFT this should be butterfly unit 4. Another way to perform a smaller FFT/IFFT is to spread the smaller input data block over the available input memory and fill the gaps with zeros, as in an interpolation digital filtering. This method may be preferable as it does not involve any changes in the hardware, but only a conceptual change in the input data loading and output data collecting. The output result after the FFT/IFFT in this case will be periodic, and one might need to upload only one period.
Also, while the processor has been described with regards to an IFFT, one of skill in the art can readily produce a processor according to the present invention that performs an FFT. In addition, since the FFT goes in reverse order of delays a reconfigurable architecture can also be defined.
Such a reconfigurable architecture is illustrated in FIG. 10. The input lines to switch/delay modules 1004 are multiplexed so as to insure the reverse data flow necessary for the forward FFT computation. Twiddle factor tables also have to be exchanged via multiplexers between butterfly processors 1002. Also if it is desired to keep the multiplier at its minimum, butterfly processor 1002 h has to be multiplexed with butterfly processor 1002 a for a forward FFT, since butterfly processor 1002 h processor is multiplierless and the data patterns are reversed for the forward FFT with respect to the IFFT.
The pipelines are implemented with dual ported I/O RAMs (not shown) having the same read and write address counter. Since in a forward FFT the output is in scrambled order, instead of the input like an IFFT, I/O RAMs (not shown) have to be augmented with decoding logic to handle both cases. A new value is written at a positive write pulse edge, after which the read/write address increments and the value available for reading is from that incremented address until the next write pulse positive edge.
The configurations of switch/delay modules 1004 are also changed after the write pulse positive edge, when such change is necessary. When the processor is running in the IFFT mode, the first delay is by one (two to the power of zero) and then it doubles for each subsequent switch-delay block, until it reaches 64 for the last. For the FFT algorithm the reverse delay distribution is valid, that is the first delay is 64 and then they decrease until 1 is reached before the last butterfly processor. To accommodate both the IFFT and FFT, the memories in the delay blocks are designed with the following depths: 64, 32, 16, 8, 16, 32, 64. Each delay line except the middle one 1004 d would normally require two taps, one for the FFT and for the IFFT algorithm. This would increase circuit buses and multiplexing circuitry, so another scheme that introduces modulo addressing in the read/write address counter is preferable. In fact, since the modulo is always a power of two, modulo addressing is easily performed by selectively masking high order bits from the address counters (with simple AND gates controlled by a Mode signal).
A state machine (not shown), whose state-transition diagram is shown in
This reconfigurable FFT/IFFT processor 1000 is fully symmetric in its operation, 512 points IFFT and 512 points FFT, and this symmetry cannot be altered without hardware changes. While ideal for symmetric DSL applications, for ADSL CO applications the upstream is the result of a 64-point transform, rather than a 512-point transform. As described above, however, the smaller 64-point transform can be obtained from the 512-point transform by spreading the smaller input data block over the available input memory and fill the gaps with zeros. By insert 7 zero samples after each sample of the 64 point data block to be transformed, the 512-point FFT will produce 4 periods, since the 512 resulting points represent 256 complex values. So the first 128 memory locations of the FFT output memory will contain the correct result. Scaling is not affected by the bigger size of the FFT, because the supplementary FFT gain is exactly compensated for by the decimation process gain factor.
The following are Verilog code snippets also showing example implementations of various components of a real-valued FFT processor according to the principles of the present invention:
Those skilled in the art will appreciate that numerous modifications and variations may be made to the above embodiments without departing from the spirit and scope of the invention.
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John D. "J.D." "Johnny" LeBlanc
I have fought the good fight, I have finished the race. I have kept the faith.
I have fought the good fight, I have finished the race. I have kept the faith.
Dewayne "DiDi" Joseph Lewis, age 41, a lifetime resident of Mulatto Bend, Port Allen, LA, died at his home on Friday, April 26, 2013.
Beloved husband, father, and paw paw, he passed away Friday, April 26, 2013 at Baton Rouge General at the age 71.
Eugenie "Jeanie" Bonin, 94, died on Thursday, April 25, 2013 at her daughter's home in Mandeville, LA.
A resident of Baton Rouge, he passed away Friday, April 19, 2013, at Baton Rouge General Medical Center.
A resident of Morganza and native of Geneva, IL. She passed away at 11:40 p.m. on Monday, April 22, 2013 at Our Lady of the Lake Regional Medical Center in Baton Rouge at the age of 87.
A native of Wakefield, Louisiana and a resident of Port Allen, she passed away Sunday, April 21, 2013 at the age of 105
A resident of Port Allen, La., she died Saturday, April 20 at the Baton Rouge General, Mid-City.
She was a loving mother, grandmother and great-grandmother who was very dedicated to her family.
A retired crane operator for Stupp Corp., he passed away at 6:10 a.m. Friday, April 19, 2013, at his home in Livonia. He was 83 and a native of Jarreau.


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Deputy fired after being arrested
KFDM News - A deputy is fired after being arrested and charged with criminal damage to property.
The Calcasieu Parish Sheriff's Office issued a criminal warrant, and 43-year-old Scott Helms was booked into jail and charged with criminal damage to property. The property involved was in possession of a family member.
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|By Marketwired .
Article Rating:
|December 4, 2012 06:00 PM EST
SAN FRANCISCO, CA -- (Marketwire) -- 12/04/12 --
Core News Facts
- Zite today unveiled Zite 2.0, your intelligent magazine, a complete redesign of its popular personalized news app.
- Zite helps you discover interesting things to read, by learning what you like and getting smarter as you use it. Zite is built on an intelligent discovery engine that analyzes millions of articles each day and brings you the best of your favorite magazines, newspapers, authors, blogs, and videos.
- Zite's interface was redesigned from the ground up around three major themes: making Zite smarter than ever, introducing discovery at every turn, and designing Zite to have both beauty and brains. Many features have changed, including:
- Making Zite smarter than ever
- Zite now encompasses 40,000 topics, 20x the number in the previous version.
- Your Top Stories, the main section in Zite, has been expanded to take into account even more of what you like. Simply click the heart icon on any topic and Zite will include more of that subject in Your Top Stories.
- Zite is now integrated with Facebook to give you suggestions based on your Facebook history.
- Discovery at every turn
- When you need inspiration, the Explore Page gives you suggestions of interesting topics to browse and allows you to search through all 40,000 topics.
- Topic Tags are intelligent topic suggestions on articles so you can dive deeper into a subject or explore something new.
- The Headline News module shows the most talked-about headlines in news, using technology built for CNN Trends.
- The Popular on Zite module shows stories that are popular among the Zite community.
- Design with beauty and brains
- Every pixel of Zite has been rethought and redesigned to create a stunning new user interface.
- Many of Zite's features rely on our powerful underlying technology, but they were designed to encourage discovery subtly without getting in your way.
- Zite is introducing a new logo: a curious, intelligent, approachable owl.
- Zite has dozens of page layouts to give Zite the feel of a magazine.
- Making Zite smarter than ever
- The new Zite is now available for free download in the App Store for all iOS6 devices. The original version of Zite is currently available for Android and Windows Phone 7.
- Launched as an iPad app in March 2011, Zite saw immediate success. Since then, Zite was acquired by CNN, launched a publisher program, integrated its technology into CNN.com by way of CNN Trends and released apps for the iPhone, Android Phone and Windows Phone 7.
Mark Johnson, CEO, Zite
"Zite's vision is to change the way people discover information. The original version of Zite was groundbreaking, but with Zite 2.0 we've evolved into your intelligent magazine. Zite is now smarter than ever and will have you discovering unique content, fresh voices, and fascinating topics at every turn. We will continue to push the boundaries of what was thought possible for digital magazines."
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"What really separates Zite 1.0 from Zite 2.0 is the user experience. Not only have we made Zite faster, smarter and more beautiful, but we've also been able to incorporate unique features that are made possible by our powerful discovery engine."
About Zite
Zite is your intelligent magazine that helps you explore your passions and discover new interests. Available as a free app on major mobile platforms, Zite is headquartered in San Francisco with offices in Vancouver, British Columbia. Zite is a wholly-owned subsidiary of CNN. Discover. Explore. Find out more at www.zite.com.
Audrey Craipain
Inner Circle Labs for Zite
Email Contact
(415) 684-9403
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"Matrix is an ambitious open standard and implementation that's set up to break down the fragmentation problems that exist in IP messaging and VoIP communication," explained John Woolf, Technical Evangelist at Matrix, in this SYS-CON.tv interview at @ThingsExpo, held Nov 4–6, 2014, at the Santa Clara Convention Center in Santa Clara, CA.
Nov. 27, 2014 04:00 AM EST Reads: 1,235
P2P RTC will impact the landscape of communications, shifting from traditional telephony style communications models to OTT (Over-The-Top) cloud assisted & PaaS (Platform as a Service) communication services. The P2P shift will impact many areas of our lives, from mobile communication, human interactive web services, RTC and telephony infrastructure, user federation, security and privacy implications, business costs, and scalability. In his session at @ThingsExpo, Robin Raymond, Chief Architect at Hookflash, will walk through the shifting landscape of traditional telephone and voice services ...
Nov. 26, 2014 02:00 PM EST Reads: 1,658
Explosive growth in connected devices. Enormous amounts of data for collection and analysis. Critical use of data for split-second decision making and actionable information. All three are factors in making the Internet of Things a reality. Yet, any one factor would have an IT organization pondering its infrastructure strategy. How should your organization enhance its IT framework to enable an Internet of Things implementation? In his session at Internet of @ThingsExpo, James Kirkland, Chief Architect for the Internet of Things and Intelligent Systems at Red Hat, described how to revolutioniz...
Nov. 24, 2014 07:00 PM EST Reads: 1,754
Bit6 today issued a challenge to the technology community implementing Web Real Time Communication (WebRTC). To leap beyond WebRTC's significant limitations and fully leverage its underlying value to accelerate innovation, application developers need to consider the entire communications ecosystem.
Nov. 24, 2014 12:00 PM EST Reads: 1,651
The definition of IoT is not new, in fact it's been around for over a decade. What has changed is the public's awareness that the technology we use on a daily basis has caught up on the vision of an always on, always connected world. If you look into the details of what comprises the IoT, you'll see that it includes everything from cloud computing, Big Data analytics, "Things," Web communication, applications, network, storage, etc. It is essentially including everything connected online from hardware to software, or as we like to say, it's an Internet of many different things. The difference ...
Nov. 24, 2014 11:00 AM EST Reads: 1,787
Cloud Expo 2014 TV commercials will feature @ThingsExpo, which was launched in June, 2014 at New York City's Javits Center as the largest 'Internet of Things' event in the world.
Nov. 24, 2014 09:00 AM EST Reads: 1,817


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Find records of Curtis Williams
Find birth, death, marriage, military, and other records of Curtis L Williams at Ancestry.com.Search for records
Biography & Family History Add details
Curtis L Williams (1962 - 1999) was born on March 28, 1962. He was born into the Williams family.
There are no known spouses or children on file for Curtis. Curtis died on August 28, 1999 at age 37.
Curtis L Williams's last known residence is at Sacramento, Sacramento County, California.
The data on this page comes from the official record for Curtis L Williams in the SSDI (United States Social Security Master Death Index). The death certificate for this record has been observed. This data can be considered accurate. What is the SSDI?
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- Curtis
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- Sacramento, Sacramento County, California
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Lamoine Cottage Rental Photos and Description
Cottage, 2 Bedrooms + Other (See Description), 1 Bath, (Sleeps 4-5)
This new construction ocean front property is on the ocean front and has access to three beaches within a mile - Marlboro Beach, Lamoine Beach (listed in Downeast Magazine as a hidden treasure) and Lamoine State Park. Bar Harbor and Acadia National Park are approximately 20 minutes away. Acadia National Park is one of our country's most visited National Parks with it breathing ocean views and rocky coastline. A trip of a lifetime.
Located in small town, but within 5 minutes of Ellsworth, a growing retail and recreation center.
Travel Downeast and visit rural Maine and its unique views and character. Campbello Island is a day trip away.
Cottage has tile kitchen floor and dishwasher and bar with adjacent living room with rug and plasma TV. A second living room and TV is located next.
Bathroom is tile floor, shower and sink.
The 50 foot deck looks over the ocean and is a great place to sit in sun or enjoy reading a book.
Keywords: Cottage, camp, home
- Suitability:
- Minimum Age Limit for Renters
- children welcome
- non smoking only
- pets not allowed
About Cyndi Fredette
Local attorney, member of Maine National Guard and member of Maine State Legislature. Wife is a school teacher.
Cyndi Fredette purchased this cottage in 2005
Why Cyndi Fredette chose Lamoine
Unique opportunity to enjoy Maine's breath-taking coastline near Bar Harbor and Acadia National Park. Very private.
What makes this cottage unique
Property is in quiet location, where you cannot even see you neighbor. In small town with local store, but 5 minutes will take you to thriving retail/business center with movie theater, eating establishments, Home Depot, Walmart, and many other unique Downeast establishments.


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Strip Clubs
D.C.'s Stadium Club could lose its liquor license
Convent of nuns in Chicago sue strip club
A convent of nuns in suburban Chicago has filed a lawsuit against a neighbor, a strip club.
Stadium Club seized by D.C. over owner's tax debt
The District of Columbia, for all intents and purposes, now owns a strip club, but it doesn't intend to for long.
Candance Reed fatally stabbed outside D.C. strip club
Candance Reed, 40, was fatally stabbed outside a strip club in Northwest D.C. A reward is offered for information that leads to an arrest and conviction.
Lap dances to be taxable, New York court decidesComment
Lap dances are taxable because they don't promote culture in a community the way ballet or other artistic endeavors do, New York's highest court concluded Tuesday in a sharply divided ruling.
New York court to consider strip club tax exemptionComment
New York's highest court will consider legal arguments by a strip club on whether nude dancing is an art and deserves a state tax exemption as such.
'Skin tax' in strip clubs to raise funds for rape centersComment
Illinois has passed a "skin tax" for strip clubs in an effort to raise funds for rape crisis centers in the state.
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Only On 7
The ABC7 I-team investigates cop cruiser crashesCop Cruiser Crashes happen more often than you think in the Washington area. Are officers being held accountable? And should you be paying the price? The I-Team investigates TONIGHT on ABC7 News at 11 after "Castle."


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News Archive
Behind the frontlines: Interagency cooperation supporting rangers' work in Thailand
Updating SOS on project developments from an emergency funding grant for work in Thap Lan National Park, Thailand, Eric Ash of Freeland Foundation, an IUCN Member, is succinct. "While it is critical to support front-line rangers and other park-based stakeholders first and foremost, reducing rosewood poaching requires considerable enforcement efforts at all levels, from the forest, through trafficking routes, and in end-markets" he explains. …
15 Nov 2014 | News story
Inspiring action for a protected planet: National Geographic teams up with IUCN
IUCN Member National Geographic has been announced today as the official media partner for the IUCN World Parks Congress 2014 – a global forum on protected areas taking place in Sydney, Australia this November. …
17 Oct 2014 | News story
Governments still behind on commitments to avert biodiversity crisis
Pyeongchang, Republic of South Korea, 17 October 2014 – Despite increasing recognition of the biodiversity crisis and its impacts on human well-being, the scale of the government response is far from commensurate with the magnitude of the calamity, says IUCN, International Union for Conservation of Nature, at the 12th meeting of the Conference of the Parties to the Convention on Biological Diversity (COP 12), closing today in South Korea. … | Spanish
17 Oct 2014 | International news release
Inger Andersen named IUCN Director General
IUCN, International Union for Conservation of Nature, announced today the appointment of Inger Andersen as the new Director General of the Union starting in January 2015. … | French | Spanish | Dutch
14 Oct 2014 | International news release
SOS: A Powerful Tool for governments
Learn more about SOS – Save Our Species at a celebration on resource mobilisation with colleagues also from the CBD, CEPF and LifeWeb at the Rio Convention Pavilion Wednesday, 15 October 2014, 18:30– 20:00. …
14 Oct 2014 | News story
Global targets set for failure?
Twenty targets designed to tackle the extinction crisis and restore the earth's natural capital by 2020 were agreed on by most of the world's governments at a meeting of the Convention on Biological Diversity (CBD) in Japan in 2010. Latest data, however, shows that many of those targets will not be met. As the 2014 CBD conference gets under way today in the Republic of Korea, IUCN calls for urgent commitment of action and financial resources to step up efforts to achieve the targets. …
06 Oct 2014 | Article
Nature, a wise investment – the Katrina story
In August 2005 Hurricane Katrina hit the Louisiana and Mississippi coastline of the United States, flooding New Orleans and causing catastrophic damage to coastal communities in both states. Katrina still ranks as the costliest storm in US history, inflicting an estimated US$81 billion in damages and causing 1,836 deaths. …
18 Sep 2014 | Article
A good news story unfolds for mantas and sharks
What did it take to get here? And what will it take to go further? asks Isabel Ender, Conservation Strategy Manager with the Manta Trust, an SOS Grantee. …
11 Sep 2014 | News story
Between a gill net and a hard place: more pressure on Vaquita
The world's smallest cetacean, the Critically Endangered Vaquita (Phocoena sinus), is facing its most daunting challenge yet. Despite decades of conservation work to protect this porpoise in its limited habitat in the northern Gulf of California, Mexico, an unlikely but illegal trade in wildlife has arisen all to quickly. Chinese demand for the swim bladder of another threatened species- the totoaba fish (Totoaba macdonaldi) is now accelerating the slide toward extinction for this species of porpoise. …
11 Aug 2014 | News story
Rising murder toll of park rangers calls for tougher laws
With poachers responsible for more than half of ranger deaths over the past two years, IUCN, the International Union for Conservation of Nature, and the International Ranger Federation (IRF) call for a toughened stance against wildlife crime globally, marking World Ranger Day celebrated across the globe on 31 July. … | French | Spanish
29 Jul 2014 | News story


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Arizona Cardinals
NFL Draft '14: Is it time for the Arizona Cardinals to draft a QB?
What matters come draft day is hard to quantify for each individual team, but for the Arizona Cardinals, this year it is especially hard.
They were not just on the doorstep, but had one foot inside when it came to the NFC playoffs in 2013, and if they were able to get in, you could make an argument they were the one team no one wanted to play.
For that reason, to many, the Cardinals must find an "impact player" with the 20th pick.
They have to come away from the 2014 NFL Draft with a player who will see the field, but also bring an element to the 2014 Cardinals that the 2013 team didn't have.
The problem becomes this: If you're looking for immediate impact, are you overlooking the best talent on the board?
The Cardinals don't have a huge need right now at cornerback, but if the best player on their board at 20 is Kyle Fuller, Darqueze Dennard or Justin Gilbert, do you pass for an edge rusher like Dee Ford?
The same question can be asked about players like Ra'Shede Hageman and Aaron Donald on the defensive line or C.J. Mosley from an inside linebacker perspective, instead taking a guy like Kony Ealy.
Then there is the real question: Are the Cardinals in a good enough position right now to take a quarterback if one falls?
The hot rumor around the league is that Teddy Bridgewater or Johnny Manziel may be available when the Cardinals step up to the podium on May 8, and for many Cardinals fans, that pit in your stomach begins to turn.
You harken back to the Cards passing on Aaron Rodgers because they needed a cornerback in 2005, just to realize they "needed" Matt Leinart in 2006.
We all remember how the 2004 NFL Draft turned out, and really could you ask for more than Larry Fitzgerald?
Of course Philip Rivers and Ben Roethlisberger were both taken after Fitzgerald and are still their teams' franchise QBs while the Cardinals have employed 12 different quarterbacks to get Fitzgerald the ball in that time.
Is it time for the Cardinals to pull the trigger on a QB if they get the chance?
Whether or not the Cardinals are in the right position to draft a quarterback and allow him to sit for a year and learn can be debated. But the reality is the Cardinals, at some point soon, need to find that quarterback of the future.
Could that be Bridgewater, Manziel, Blake Bortles or another player at 20?
If not, there's always next year, right?
Most Popular
Cardinals Audio
- Brock Huard, ESPN Seattle host - Friday November 21The Cardinals secondary will get physical with Seattle's wide receivers.
- Mark Schlereth- ESPN NFL analyst - Friday November 21ESPN NFL analyst Mark Schlereth breaks down the Cardinals' matchup with Seattle.
- Bickley Blast - Friday November 21Could Richard Sherman line up as a wide receiver against the Cardinals?
- It's Paul's Call with Paul Calvisi! - Friday November 21Paul�s Call tries to tackle the mystery that is Marshawn Lynch.
- Kurt Warner, Super Bowl-winning quarterback - Friday November 21Super Bowl winning-quarterback Kurt Warner thinks it's awesome how well the Cardinals are the playi


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