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Whether in a looming office tower or a sprawling community of company suites, Oregon home professionals know the relevance of obtaining a cleanse facility. For several years, this wearisome work has been entrusted to classic janitorial firms who arrived soon after the near of enterprise and labored effectively into the night time. This approach acquired the occupation carried out, but it was not quite cost-effective. Obtaining a crew in the facility late in the day meant making use of electrical power for several hours on finish, a follow which led to abnormal power use and greater payments. Luckily, the greatest of nowadays's Oregon janitorial companies have discovered an option to the outdated way of cleaning that may adjust the long term of the sector.
Daytime cleansing is a revolutionary approach that makes it possible for janitorial groups to perform during peak hrs instead of waiting right up until right after darkish. Maintenance professionals do most of the cleansing although individuals are still in the developing so that extremely minor extra electrical energy is utilised. The facility is previously lit, either artificially or naturally via glass panes, so there is no energy wasted in turning on the lights. As for plugged-in appliances, the cost for running them alongside a host of other typically employed electronics is far significantly less visible. Residence managers also have to consider the effectively-becoming of the custodians, which could involve operating the heating or cooling programs when they are on the premises. Since every person is there at the identical time with this modern approach, they will have previously activated the air conditioning or heating program for their possess staff by the time the cleaning service comes. In this way, Oregon janitorial cleaning services providers who utilize daytime cleaning have served to minimize annually power costs by up to eight per cent in some properties. Daytime cleansing also minimizes the emission of greenhouse gases, which advantages the environment on a global scale.
Skeptics of daytime cleaning have asked, +Won't the staff get in the way if they clear throughout peak hours?+ A lot of of them are stunned to locate out that the interoffice reaction is fairly the opposite. Staff like obtaining janitors on hand and offered at an instant's recognize. It keeps the region tidy and decreases the amount of contamination on surfaces and in the air. Having a clear workspace has also been proven to increase morale in most personnel, and an on-site Oregon janitorial services performs a crucial part in assembly these requirements. Additionally, employing a business that can perform in the course of the daytime drastically raises building safety. Even though Oregon janitorial services employees are sufficiently supervised and possess large amounts of integrity, the danger of crack-ins and home-theft raises drastically at night. During leaning, doorways are continually currently being opened and shut in a selection of spots around the facility. This presents uninvited attendees considerably less complicated accessibility to the facility.
In this era of environmental consciousness, property professionals have to suppose a new level of ecological obligation. Daytime cleansing is a convenient way to improve the operational performance of your developing although aiding to maintain the Earth's resources. It might just be the key to revolutionizing Portland janitorial services.


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What year did they start making the dodge charger in
kgb answers » Home & Garden » Automotive » What year did they start making the dodge charger in
Tags: dodge charger, charger, dodge
Wednesday, February 01 2012
Source: http://www.edmunds.com/dodge/charger/history.html
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text: Macatawa Bank Company Profile (NASDAQ:MCBC) Analyst Ratings Earnings Estimates Dividends Insider Trades Headlines Social Company Profile Chart Consensus Ratings for Macatawa Bank (NASDAQ:MCBC) (?) The ratings breakdown includes the most recent rating from each analyst that has rated the stock within the last twelve months. The ratings score is a calculation of the average number of sell, hold, buy and strong buy ratings (0-1.5 = Sell, 1.5-2.5 = Hold, 2.5-3.5 = Buy, >3.5 = Strong Buy). The consensus price target is a mean average of the most recent price target set by each analyst that has set a price target for the stock in the last twelve months.Ratings Breakdown: 2 Hold Rating(s)Consensus Rating:Hold (Score: 2.00)Consensus Price Target: $6.88 (1.55% upside) Analysts' Ratings History for Macatawa Bank (NASDAQ:MCBC) Show: All Ratings For This Stock Only the Most Recent Rating From Each Brokerage DateFirmActionRatingPrice TargetActions5/25/2016Hovde GroupInitiated CoverageMarket Perform$7.75 2/1/2016Keefe, Bruyette & WoodsBoost Price Target$5.50 -> $6.00 (Data available from 6/25/2014 forward) Earnings History for Macatawa Bank (NASDAQ:MCBC)DateQuarterConsensus EstimateActual EPSRevenue EstimateActual RevenueRelease LinkConference CallActions7/21/2016 4/28/2016Q1$0.09$0.10ViewN/A 1/28/2016Q4$0.10$0.10ViewN/A 10/22/2015Q315$0.09$0.09ViewN/A 7/23/2015Q2$0.09$0.09ViewN/A 4/23/2015$0.08$0.08ViewN/A 1/29/2015$0.08$0.07ViewN/A 10/23/2014Q3$0.08$0.08ViewN/A 7/24/2014$0.08$0.08ViewN/A 4/24/2014$0.06$0.08ViewN/A 1/30/2014Q4$0.08($0.56)ViewN/A 7/25/2013Q2 2013$0.08$0.10$14.56 millionViewN/A (Data available from 1/1/2011 forward) Earnings Estimates for Macatawa Bank (NASDAQ:MCBC)No earnings estimates for this company have been tracked by MarketBeat.com Dividend History for Macatawa Bank (NASDAQ:MCBC)AnnouncedPeriodAmountYieldEx-Dividend DateRecord DatePayable DateShare5/3/2016quarterly$0.031.75%5/11/20165/13/20165/27/2016 2/1/2016Quarterly$0.032/10/20162/12/20162/26/2016 10/27/2015quarterly$0.032.31%11/9/201511/12/201511/27/2015 7/28/2015quarterly$0.032.26%8/11/20158/13/20158/28/2015 4/27/2015$0.035/12/20155/14/20155/29/2015 2/3/2015quarterly$0.021.47%2/10/20152/12/20152/27/2015 10/27/2014quarterly$0.021.54%11/4/201411/6/201411/28/2014 7/28/2014quarterly$0.021.68%8/5/20148/7/20148/28/2014 4/28/2014quarterly$0.021.63%5/6/20145/8/20145/29/2014 2/24/2014quarterly$0.021.53%3/5/20143/7/20143/28/2014 (Data available from 1/1/2013 forward) Insider Trading History for Macatawa Bank (NASDAQ:MCBC)Transaction DateInsider NameTitleBuy/SellNumber of SharesAverage Share PriceTotal TransactionActions2/9/2016Mark BuggeDirectorBuy1,000$5.76$5,760.00 2/3/2016Roy Michael K LeDirectorBuy1,000$5.74$5,740.00 5/12/2015Ronald L HaanCEOBuy5,000$5.17$25,850.00 2/6/2015White Bay Capital, LllpMajor ShareholderBuy80,796$5.17$417,715.32 2/5/2015Richard L PostmaDirectorBuy33,177$5.48$181,809.96 11/13/2013Robert L HerrDirectorBuy1,000$5.10$5,100.00 (Data available from 1/1/2013 forward) Latest Headlines for Macatawa Bank (NASDAQ:MCBC)DateHeadline05/30/16 06:19 PMMacatawa Bank Corporation (NASDAQ:MCBC) Shorted Shares Increased 89.01% After Market Selling - HNN - Macatawa Bank Corporation (NASDAQ:MCBC) Shorted Shares Increased 89.01% After Market SellingHNNMacatawa Bank Corporation (NASDAQ:MCBC) has risen 38.54% since October 22, 2015 and is uptrending. It has outperformed by 36.27% the S&P500. Macatawa Bank Corporation is a bank holding company. The company has a market cap of $244.60 ...and more »05/25/16 06:09 AMCoverage initiated on Macatawa Bank Corporation by Hovde Group - 05/04/16 02:19 PMMACATAWA BANK CORP Files SEC form 8-K, Submission of Matters to a Vote of Security Holders - 04/28/16 05:57 PMMacatawa posts 1Q profit - 04/28/16 03:36 PMMacatawa Bank Corporation Reports First Quarter 2016 Results - [at noodls] - HOLLAND, Mich., April 28, 2016 (GLOBE NEWSWIRE) -- Macatawa Bank Corporation (NASDAQ:MCBC) today announced its results for the first quarter of 2016, reflecting continued improvement in financial performance. ...04/11/16 02:17 PMSchaendorf Joins the Macatawa Bank Mortgage Team - [at noodls] - HOLLAND, Mich. (March 29, 2016) - Macatawa Bank is pleased to announce Josh Schaendorf has joined the Mortgage team as Assistant Vice President, Mortgage Loan Officer in their Grand Haven market. He is ...02/18/16 03:36 PMMACATAWA BANK CORP Files SEC form 10-K, Annual Report - 02/01/16 12:30 PMMacatawa Bank Corp. Earnings Analysis: Q4, 2015 By the Numbers - 01/28/16 03:45 PMMacatawa Bank Corporation Reports Fourth Quarter and Full Year 2015 Results - [at noodls] - , (GLOBE NEWSWIRE) -- (NASDAQ:MCBC) today announced its results for the fourth quarter and full year of 2015, reflecting continued improvement in financial performance. ... This is an abstract of the original ...01/14/16 10:02 AMMacatawa Bank Chooses Vantiv Merchant Services Solutions - [at noodls] - HOLLAND, Mich. (May 12, 2015) -Macatawa Bank announced today that they have selected Vantiv, Inc. (NYSE: VNTV), a leading provider of payment processing services and related technology solutions for merchants ...01/14/16 10:02 AMConey Named Macatawa Bank Downtown Holland Branch Manager - [at noodls] - HOLLAND, Mich. (May 26, 2015) -Macatawa Bank is pleased to welcome Jason Coney as Branch Manager in our Holland market. He is located in our Downtown Holland office at 141 East 8th Street. In his new position ...01/14/16 10:02 AMMACATAWA BANK CORP Files SEC form 8-K, Change in Directors or Principal Officers, Financial Statements and Exhibits - 01/14/16 10:02 AMMacatawa Bank Corporation Reports Second Quarter 2015 Results - [at noodls] - Macatawa Bank Corporation Reports Second Quarter 2015 Results01/14/16 10:02 AMMacatawa posts 2Q profit - 01/14/16 10:02 AMMacatawa Bank Corp. Earnings Q2*, 2015 - 01/14/16 10:02 AMMacatawa Bank Corporation Reports Third Quarter 2015 Results - [GlobeNewswire] - HOLLAND, Mich., Oct. 22, 2015-- Macatawa Bank Corporation today announced its results for the third quarter of 2015, reflecting continued improvement in financial performance. Net income of $3.2 million ...01/14/16 10:02 AMMACATAWA BANK CORP Files SEC form 8-K, Results of Operations and Financial Condition, Financial Statements and Exhibi - 01/14/16 10:02 AMMacatawa posts 3Q profit - 01/14/16 10:02 AMMacatawa Bank Corporation Declares Dividend - [GlobeNewswire] - HOLLAND, Mich., Oct. 26, 2015-- Macatawa Bank Corporation today announced that its Board of Directors has declared a quarterly cash dividend of $0.03 per share on its common stock to be paid on November ...01/14/16 10:02 AMMacatawa Bank Corp. Earnings Q3, 2015 - 01/14/16 10:02 AMMACATAWA BANK CORP Financials - 01/14/16 10:02 AMMACATAWA BANK CORP Files SEC form 8-K, Change in Directors or Principal Officers, Regulation FD Disclosure, Financial - 01/14/16 10:02 AMDr. Michael K. Le Roy to serve on Macatawa Bank Corporation Board - [at noodls] - For immediate release NASDAQ Stock Market: MCBC Holland, Michigan, December 17, 2015 - Macatawa Bank Corporation (NASDAQ: MCBC) announced that Dr. Michael K. Le Roy has been appointed to the Board of Directors ... About Macatawa Bank Macatawa Bank Corporation is a bank holding company. The Company owns Macatawa Bank (the Bank). The Company focuses on commercial banking. It also offers automated teller machines (ATMs), Internet banking, telephone banking and debit cards. It offers personal trust services, which include financial planning, investment management services, trust and estate administration, and custodial services. The Company's retirement plan services provide various types of qualified retirement plans, including profit sharing, 401(k) and pension plans. Through its subsidiary, Macatawa Bank, the Company offers a range of commercial and personal banking services, including checking, savings and certificates of deposit accounts, cash management, safe deposit boxes, trust services and commercial, mortgage and consumer loans through over 30 branch offices, and a lending and operation service facility in Ottawa County, Kent County and northern Allegan County, Michigan. Industry, Sector and Symbol: Sector: Financial Services Industry: Regional - Midwest Banks Sub-Industry: N/A Exchange: NASDAQ Symbol: MCBC CUSIP: Key Metrics: Previous Close: $6.7750 Day Moving Average: $7.02200 Day Moving Average: $6.40P/E Ratio: 17.05P/E Growth: 3.83Market Cap: $229.67MCurrent Quarter EPS Consensus Estimate: $0.45 EPS Additional Links: View MCBC on Google FinanceView MCBC on Yahoo FinanceView MCBC's Company Profile on ReutersSearch for Macatawa Bank Co. on Google Macatawa Bank (NASDAQ:MCBC) Chart for Saturday, June, 25, 2016


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text:
|Publication number
|Publication type
|Application number
|Publication date
|Jul 2, 1985
|Filing date
|Jul 6, 1982
|Priority date
|Jul 6, 1982
|Fee status
|Also published as
|Publication number
|Parviz Keshtbod
|Original Assignee
|Signetics Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Non-Patent Citations (4), Referenced by (25), Classifications (7), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates generally to semiconductor memories and more particularly to non-volatile random-access memory (RAM) cells employing field-effect transistors (FET's) for information storage.
Avoiding the loss of data stored in the memory cells of a semiconductor memory during a power shutdown is an important problem in memory design and use. Such a power shutdown may be anticipated sufficiently far in advance to allow time to transfer the data from the memory cells to a separate non-volatile storage location in the memory--i.e., a storage location which does not require power for preserving the data. Commonly, however, shutdown occurs without adequate warning to allow data transfer to the separate non-volatile location. It is therefore desirable to incorporate a non-volatile storage site directly in each cell.
In "A 256-Bit Nonvolatile Static RAM," 1978 IEEE ISSCC Dig. of Tech. Papers, Feb. 16, 1978, pp. 108-9, E. Harari et al. disclose a memory cell for achieving the foregoing objective. In this static RAM cell, a pair of cross-coupled P-channel FET's form a volatile random-access location for storing a data bit. The P-channel FET's are individually connected through their drains to the drains of a pair of cross-coupled variable-threshold floating-gate N-channel FET's which form a non-volatile storage location. Just prior to a power shutdown, the cell power supply is raised from its normal value of 5-10 volts up to about 20 volts for 10 microseconds. This places the non-volatile location in a state indicative of the data bit contained in the volatile location. In particular, the threshold voltage of one of the N-channel floating-gate FET's goes to a positive value while the threshold voltage of the other floating-gate FET goes to an opposing negative value. When the power is shut down, the P-channel FET's both turn off to cause the bit in the volatile storage location to "evaporate". However, the threshold voltages of the N-channel FET's remain at their opposing values. As power is restored, the opposing threshold voltages of the N-channel FET's cause the complement of the original data bit to appear in the volatile location. B. Troutman et al. disclose substantially the same arrangement in FIG. 2b of U.S. Pat. No. 4,128,773, except that the FET polarities are reversed. In either of these non-volatile RAM cells, an additional pair of FET's serve as a load circuit.
In U.S. Pat. No. 4,095,281 with particular reference to FIG. 2, G. Denes discloses another memory cell that appears to operate in basically the same manner as that of Harari et al. or Troutman et al. The principal difference is that Denes uses P metal-nitride-oxide semiconductor (MNOS) FET's for the variable-threshold FET's and does not use an additional pair of FET's in the load circuit.
Although these prior art devices provide non-volatile data storage, none of them return the original data bit to the volatile storage locations in the memory cells when power is restored. Instead, a separate operation must normally be performed to invert the complement data to get back the data in its original form. This is undesirable since it requires further time and/or circuitry.
In "A Single 5 V Supply Nonvolatile Static RAM," 1981 IEEE ISSCC Dig. of Tech. Papers, Feb. 19, 1981, pp. 148-9, J. Drori et al. disclose a non-volatile RAM cell that avoids the inconvenience of having the complement of the original data bit returned to the cell after a power shutdown. This cell requires at least six FET's in addition to a triple polycrystalline silicon floating-gate structure for preserving the original data bit during shutdown and, consequently, is relatively complex.
A non-volatile memory cell which has a pair of cross-coupled like-polarity FET's that serve as a volatile location for storing a given data bit contains a like-polarity variable-threshold insulated-gate FET that serves as a non-volatile storage location. The cross-coupled FET's, designated for convenience as the first FET and the second FET, have their sources coupled to a reference voltage supply and their drains coupled through a load circuit to a power supply. The variable-threshold FET has its source coupled to the drain of the first FET, its insulated-gate electrode coupled to the drain of the second FET, and its drain coupled to the power supply. Preferably, the variable-threshold FET is a floating-gate device.
Just before a power shutdown which causes the data stored in the volatile cell locations in a memory containing a group of the present cells to evaporate, the power supply is pulsed to a suitable level to cause the data in the volatile locations to be transferred simultaneously to the corresponding non-volatile locations in the memory cells. When power is restored, the original data bit in each memory cell automatically returns to its volatile storage location.
More particularly, the present memory cell operates as follows. The threshold voltage of the variable-threshold FET increases as a control voltage applied from its insulated-gate electrode to its source is increased within a first voltage range and decreases as a control voltage applied from its source to its insulated-gate electrode is increased within a second voltage range (which is typically the same as the first range). The power supply provides a supply voltage at a first level VDD1 for normal storage of the given data bit in the cross-coupled FET pair. The current through the variable-threshold FET and the load circuit is so controlled that the variable-threshold FET assumes a logic state corresponding to the given data bit when the supply voltage is moved to a more extreme second level VDD2. For example, in the case of N-channel devices where the reference voltge supply is at ground reference and VDD1 is 5 volts, VDD2 is 20 volts. The original data bit is then automatically restored to the cross-coupled FET's when the supply voltage is returned to VDD1.
The load circuit contains a first impedance element coupled between the power supply and the drain of the first FET and a second impedance element coupled between the power supply and the drain of the second FET. During cell operation, the sum of the current through the first impedance element and through the variable-threshold FET when it is fully conductive significantly exceeds the current through the second impedance element which, in turn, significantly exceeds the current through the first impedance element.
In an option, the memory cell further includes another like-polarity variable-threshold insulated-gate FET in the non-volatile storage location. This second variable-threshold FET has its source coupled to the drain of the second FET, its insulated gate electrode coupled to the drain of the first FET, and its drain coupled to the power supply. The second variable-threshold FET is praferably a flcating-gate device and is controlled in the same manner as the first variable-threshold FET.
Because the variable-threshold FET's are cross-coupled in this option, one is off when the other is on. They operate as a flip-flop in storing a data bit. To enable the data bit stored in the volatile location to be transferred to the non-volatile location when the supply voltage is moved from VDD1 to VDD2 and thereafter to restore the original data bit to the volatile location whenever the supply voltage returns to VDD1, the current through either variable-threshold FET when it is fully conductive significantly exceeds the current through either impedance element.
A significant advantage of the present memory cell is that precisely the same data bit that existed in the volatile storage location before a power shutdown is returned to the volatile location after shutdown. In comparison to conventional memory cells which restore the complement of the original data bit after a power shutdown, the present memory cell is faster. It avoids the time lost due to the inconvenience of operating with the complementary data bit or the time wasted because of the necessity to perform an additional operation to convert the complementary bit back into the original bit. In comparison to conventional memory cells that do restore the original bit after power shutdown, the present memory cell contains fewer elements. This makes it both easier to fabricate and faster because storage and retrival of the data bit from the non-volatile location do not interfere with the other operation of the cell.
A particularly useful feature of a RAM utilizing a group of the present memory cells is that the variable-threshold FET's can be employed as a "permanent" memory at any time by temporarily moving the power supply to VDD2 to write the data from the volatile locations into the non-volatile locations in the cells. The power supply is then returned to VDD1 but is not turned off. The volatile locations can now be employed as a "working" RAM on which various operations are performed. If the original data is again needed, it can be restored to the volatile locations at any time by briefly turning off the power and then returning it to VDD1.
FIG. 1 is a circuit diagram of a memory circuit containing an embodiment of a memory cell in accordance with the invention.
FIG. 2 is a circuit diagram of another embodiment of a memory cell in accordance with the invention employable in the memory circuit of FIG. 1.
FIG. 3 is a layout view of the memory cell of FIG. 1.
FIG. 4 is a cross-sectional side view of the memory cell of FIG. 3.
Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items.
Referring to the drawings, FIG. 1 illustrates an MOS memory circuit which is typically one of a group of such memory circuits arranged in a matrix of rows and columns to form a non-volatile static RAM. Each of the FET's in FIG. 1 is an N-channel insulated-gate device as indicated by the "N" next to its insulated gate electrode. "E" or "D" next to the gate electrode of each fixed-threshold FET indicates that it is an enhancement-mode device or a depletion-mode device, respectively. Each fixed-threshold enhancement-mode FET has a threshold voltage (VT) of about 0.8 volt.
The memory circuit of FIG. 1 consists of a bi-stable static memory cell 20 in combination with an external circuit for writing a binary data bit into cell 20 and for reading the data bit out of cell 20. The external circuit supplies the bit to a volatile storage location 21 in cell 20. Location 21 consists of a pair of cross-coupled FET's Q1 and Q2 whose sources are connected to a reference voltage supply that provides a substantially constant reference voltage VSS at ground potential (0 volt). Each FET Q1 or Q2 has a gate width-to-length ratio (W/L) of 12/3.
The drains of FET's Q1 and Q2 are coupled by way of nodes N1 and N2, respectively, through an unbalanced load circuit to a power supply which provides a supply voltage VDD whose normal operational level VDD1 is 5 volts. The load circuit consists of a resistor R1 connected between the VDD power supply and node N1 and a resistor R2 similarly connected between the VDD supply and node N2. Resistor R1 is about 500 megaohms while resistor R2 is about 50 megaohms. Associated with nodes N1 and N2 relative to VSS are parasitic capacitances C1 and C2, respectively. When no active operation is being performed on cell 20, the resistor R1 or R2 associated with the particular FET Q1 or Q2 that is turned off only supplies leakage current to the associated node N1 or N2 to maintain the associated capacitance C1 or C2 at a charging level of 5 volts.
The data bit in both cell 20 and storage location 21 is defined to be a logical "0" (hereafter simply a "0") when FET Q1 is off and FET Q2 is fully conductive. The bit is defined to be a logical "1" (hereafter simply a "1") when FET Q1 is fully conductive and FET Q2 is off. Opposite definitions could be employed as well. The bit in location 21 "evaporates" whenever the VDD supply drops below a particular level, for example, down to 0 volt during a power shutdown.
Cell 20 contains an unbalanced non-volatile storage location 22 comprising a variable-threshold floating-gate FET Q3 whose source S3 is connected to the drain of FET Q1 and whose insulated-gate electrode G3 is connected to the drain of FET Q2. FET Q3 has a single floating-gate electrode F3 which is separated from source S3 by a thin layer of electrically insulating material whose minimum thickness is in the range of 50 to 200 angstroms which enables the threshold voltage of FET Q3 to be electrically altered. Its VT increases as a voltage V3GS applied from insulated-gate electrode G3 to source S3 is appropriately increased so as to cause electrons to tunnel from source S3 into floating-gate electrode F3. Likewise, its VT decreases as a voltage V3SG applied from source S3 to electrode G3 is appropriately increased so as to cause electrons to tunnel from floating gate F3 into source S3. Normally, voltage V3GS or V3SG must be raised above 10 volts to cause tunneling through the thin insulating layer when it has a preferred minimum thickness of 80 angstroms. Gate electrodes F3 and G3 are separated from each other by another layer of electrically insulating material that is sufficiently thick so as to prevent electron tunneling between them when voltage V3GS or V3SG is so varied. FET Q3 has a W/L of 3/15 for insulated gate G3 and a W/L of 3/17 for floating gate F3.
When the VT of FET Q3 is sufficiently negative that it is turned on while the VDD supply is at VDD1, non-volatile location 22 (as represented by FET Q3) is at the "0" logic state. Similarly, when the VT of FET Q3 is sufficiently positive that it is turned off while the VDD supply is at VDD1, location 22 is at the "1" state.
The drain D3 of FET Q3 is coupled through a current-limiting element to the VDD supply. The current-limiting element is a depletion-mode FET Q5 whose source and gate electrode are commonly connected to drain D3 and whose drain is connected to the VDD supply. FET Q5 has a W/L of 2/8 and a VT of -0.4 volt. FET Q5 is continually on as long as the VDD supply provides power to cell 20. Irrespective of the level of supply voltage VDD, FET Q5 limits the current through FET Q3 when it is fully conductive to about 1 μa. Because each of FET's Q1 and Q2 can accommodate over 100 times this current, the on/off condition of FET Q3 does not affect the logic state of volatile location 21 when the VDD supply is at 5 volts.
An access signal φA applied to the gate electrodes of a pair of FET's Q7 and Q8 in the external circuit controls access to cell 20 for read/write operations. One source/drain element SD7 of FET Q7 is connected by way of a line 23 through node N1 to the gate electrode of FET Q2. Likewise, one source/drain element SD8 of FET Q8 is connected by way of a line 24 through node N2 to the gate electrode of FET Q1. Each FET Q7 or Q8 has a W/L of 8/3.
Any one of a number of circuitry arrangements can be utilized in performing read/write operations on cell 20 through FET's Q7 and Q8. A suitable example of the read/write circuitry is illustrated in FIG. 1.
In this example, a pair of FET's Q9 and Q10 which are several times as large as FET's Q1 and Q2 are connected between the VSS supply on one hand and the other source/drain elements DS7 and DS8, respectively, of FET's Q7 and Q8, respectively, on the other hand. FET's Q9 and Q10 are controlled by data signals φL and φR, respectively. FET's Q9 and Q10 receive current from a substantially constant 5.0-volt VDD' supply by way of resistively-connected depletion-mode FET's Q11 and Q12, respectively.
In writing data into cell 20, one of data signals φL and φR is set at an appropriate value above the VT of the associated FET Q9 or Q10 to make it fully conductive while the other of data signals φL and φR is set at another appropriate value below the VT of the other FET Q10 or Q9 to keep it in the non-conductive state. The voltage at the drain of the fully-conductive FET Q9 or Q10 is then at a low value near 0 volt while the voltage at the drain of the non-conductive FET Q10 or Q9 is at a high level near 5 volts. Access signal φA is next raised to 5 volts to turn on FET's Q7 and Q8. The low and high voltages at the drains of FET's Q9 and Q10 are then transmitted to the gate electrodes of FET's Q1 and Q2. This forces one of them to turn on while causing the other to turn off. In particular, a "0" is written into volatile location 21 to turn off FET Q1 and turn on FET Q2 when signal φL is at 0 volt and signal φR is at 5 volts. A "1" is written into location 21 when signals φL and φR are reversed. Because FET's Q11 and Q12 can transmit many times the currents supplied to nodes N1 and N2 through the load R1 and R2 and FET Q3 when it is on, its on/off condition does not affect the logic state achieved in location 21 during a write operation.
For interrogating cell 20, a pair of lines 25 and 26 are connected between a sense amplifier 27 of conventional design and source/drain elements DS7 and DS8, respectively. During a read operation, signals φL and φR are set at their low values so that FET's Q9 and Q10 are off. Signal φA is raised to 5 volts to turn on FET's Q7 and Q8. When sense amplifier 27 is activated, it senses the voltage difference between nodes N1 and N2 along lines 25 and 26 to determine the logic state in location 21.
With FET's Q7 and Q8 turned off to isolate cell 20, a data bit is transferred between locations 21 and 22 in the following manner. The VDD supply is initially at its normal value VDD1 of 5 volts. FET Q3 may be on or off depending on how it was programmed in the preceding programming cycle for non-volatile location 22.
Consider first the case in which volatile location 21 contains a "0" with FET Q1 off and FET Q2 on. The voltage at node N1 is 5 volts, while the voltage at node N2 is 0 volt so that voltage V3SG is 5 volts. This is insufficient to cause tunneling between floating gate F3 and source S3.
The VDD supply is now raised for 20-40 milliseconds up to a high level VDD2 of 20 volts. This acts to write a "0" into location 22. In particular, FET Q1 remains off as current flows through resistor R1 and through FET Q3 if it is on to bring node N1 to 20 volts. This causes FET Q2 to turn on harder as it draws more current through resistor R2. Node N2 remains at 0 volt. Voltage V3SG thereby rises to 20 volts which induces about 5 volts on floating gate F3. If it does not already contain a suitable positive charge remaining from the previous programming cycle of location 21, the resultant 15-volt difference between source S3 and gate F3 causes electrons to tunnel from gate F3 through the thin oxide to source S3 to leave a positive charge on gate F3. Its VT drops down to approximately -5 volts. If not already on, FET Q3 turns on to place a "0" in non-volatile location 22.
Next, the power to cell 20 is shut down by dropping supply voltage VDD down to the 0-volt VSS level. FET's Q1 and Q2 both turn off, and the "0" in location 21 "evaporates". However, the positive charge remains on floating gate F3 during power shutdown, enabling location 22 to retain its "0".
At some future time, power is restored by bringing the VDD supply back up to the 5-volt VDD1 level. The voltage at node N2 starts to rise from 0 volt which is greater than the negative VT that FET Q3 now has. This causes FET Q3 to turn on very rapidly and provide about 1 μa to node N1. Initially, resistor R1 provides about 10 na to node N1, while resistor R2 provides about 100 na to node N2. Capacitances C1 and C2 both begin to charge as the voltages at nodes N1 and N2 rise. However, the total current supplied to node N1 through resistor R1 and FET Q3 exceeds the current supplied to node N2 through resistor R2 by a factor of approximately 10. Consequently, capacitance C1 charges approximately 10 times as fast as capacitance C2. Node N1 then reaches the 0.8-volt VT of FET Q2 to turn it on before node N2 can reach the 0.8-volt VT of FET Q1. As FET Q2 turns on, it pulls the voltage at node N2 back down so as to keep FET Q1 off. Node N1 continues to rise up to 5 volts to latch a "0" in location 21, thus restoring its original logic state.
The operation is similar in the opposite situation in which location 21 originally contains a "1". Node N1 is initially at 0 volt, and node N2 is initially at 5 volts. Voltage V3GS is also 5 volts. When the VDD supply is pulsed to 20 volts, node N1 remains at 0 volt while node N2 rises to 20 volts. FET Q2 remains off, and FET Q1 turns on harder to accommodate the increased current provided through resistor R1. Voltage V3GS rises to 20 volts which induces approximately 15 volts on gate F3. Unless it is already negatively charged from the previous programming cycle, electrons tunnel from source S3 through the thin oxide to gate F3 to charge it negatively and increase its VT to approximately 6.5 volts. If not already off, FET Q3 turns off to place a "1" in location 22.
The negative charge remains on gate F3 during the subsequent power shutdown. When the VDD supply is restored to 5 volts, the voltages at nodes N1 and N2 begin to rise. However, node N2 cannot rise above the 6.5-volt VT of FET Q3, so it remains off. Initially, resistor R1 again supplies about 10 na to node N1. Likewise resistor R2 again initially provides about 100 na to node N2. Because the current supplied to node N2 through resistor R2 exceeds the current supplied to node N1 through resistor R1 by a factor of about 10, capacitance C2 charges approximately 10 times as fast as capacitance C1. Consequently, node N2 reaches the VT of FET Q1 to turn it on before node N1 reaches the VT of FET Q2. As FET Q1 turns on, it draws current to reduce the voltage at node N1 and keep FET Q2 off. Node N2 continues to rise to 5 volts to latch location 21 at its original "1".
In a second mode of operation, the VDD supply is again pulsed from 5 to 20 volts for 20-40 msec to program the logic state of volatile location 21 into non-volatile location 22. Instead of cutting off the power to cell 20, the VDD supply is returned to 5 volts. The original logic state remains in location 21. In a memory consisting of a group of cells 20, the portion consisting of locations 21 may now be used as a "working" memory whose data may be changed in any desired way. Should the original data written into the memory be needed, this information can be recalled from the "permanent" memory consisting of locations 22. This is accomplished by turning off FET's Q7 and Q8 for each cell 20, dropping the VDD supply down to 0 volt for 20-40 msec, and then returning it to 5 volts. The events described above for the first mode when the VDD supply is raised from 0 volt to 5 volts again occur in each cell 20 so as to restore the original data.
FIG. 2 illustrates an embodiment of another bi-stable memory cell 30 employable with the external circuit shown in FIG. 1. The conventions adopted above for FIG. 1 are likewise employed in FIG. 2. Cell 30 consists of a volatile storage location 31, a balanced load circuit for location 31, and a balanced non-volatile storage location 32. Volatile location 31 consists of FET's Q1 and Q2 configured in the same manner as in location 21 and connected by lines 23 and 24 to the external circuit shown in FIG. 1. FET's Q1 and Q2 in location 31 are also the same size and have the same VT 's as in location 21.
The load in FIG. 2 consists of resistors R3 and R4 configured in the same manner as resistors R1 and R2, respectively, in FIG. 1. However, resistors R3 and R4 are substantially identical, each being about 500 megaohms.
In addition to variable-threshold FET Q3 and current-limiting FET Q5 connected in the same manner as in FIG. 1, non-volatile location 32 contains another variable-threshold FET Q4 and an associated current-limiting element. FET Q4 is substantially identical to FET Q3, likewise having a W/L of 3/15 for its insulated-gate electrode G4 and a W/L of 3/17 for its single floating-gate electrode F4. The drain of FET Q1 is connected to electrode G4 while the source S4 of FET Q4 is connected to the drain of FET Q2. Floating gate F4 is separated from source S4 by a thin layer of electrically insulating material whose thickness is the same as that of the corresponding thin insulating layer of FET Q3 so as to enable the VT of FET Q4 to be electrically altered. Its VT increases as a voltage V4GS applied from electrode G4 to source S4 is appropriately increased to cause electron tunneling from source S4 into floating gate F4 and decreases as a voltage V4SG applied from source S4 to electrode G4 is appropriately increased to cause electron tunneling back to source S4.
When the VT of FET Q3 is sufficiently negative that it is turned on and the VT of FET Q4 is sufficiently positive that it is turned off while the VDD supply is at VDD1, non-volatile location 32 (as represented by FET's Q3 and Q4) is in the "0" state. The converse exists when the VT of FET Q3 is sufficiently positive that it is off and the VT of FET Q4 is sufficiently negative that it is on while the VDD supply is at VDD1.
The current-limiting element for FET Q4 is a depletion-mode FET Q6 whose drain is connected to the VDD supply and whose gate electrode and source are connected in common to the drain D4 of FET Q4. FET Q6 is substantially identical to FET Q5, likewise having a W/L of 2/8 and a VT of -0.4 volt. FET Q6 is continually on as long as cell 30 is powered and limits the current through FET Q4 to about 1 μa. Because each FET Q1 or Q2 can accommodate over 100 times this current, the on/off condition of FET's Q3 and Q4 does not affect the logic state of location 31.
Cell 30 operates similarly to cell 20. Read and write operations are performed in the same manner.
In transferring a data bit between locations 31 and 32 with FET's Q7 and Q8 off, one of FET's Q3 and Q4 is on and the other is off. For example, first consider the case when volatile location 31 initially contains a "0" with FET Q1 turned off and FET Q2 turned on. Node N1 is at 5 volts while node N2 is at 0 volt.
In one mode of operation, the VDD supply is raised from the VDD1 level of 5 volts to the VDD2 level of 20 volts for 20-40 msec. Node N1 rises to 20 volts as FET Q2 turns on harder while node N2 remains at 0 volt and FET Q1 remains off. Voltage V3SG rises to 20 volts to induce about 5 volts on floating gate F3. Unless it is already appropriately positively charged, electrons tunnel from gate F3 to source S3 to leave a resulting positive charge on gate F3 and decrease the VT of FET Q3 to about -5 volts. Likewise, voltage V4GS rises to 20 volts to induce about 15 volts on floating gate F4. Unless it is already appropriately negatively charged, electrons tunnel from source S4 to gate F4 to leave a net negative charge on gate F4 and increase the VT of FET Q4 to about 6.5 volts. Location 32 is then at "0" with FET Q3 turned off while FET Q4 is turned on.
As with cell 20, the VDD supply is dropped down to 0 volt. The "0" in volatile location 31 evaporates, but FET's Q3 and Q4 retain the charges stored on gates F3 and F4 to enable non-volatile location 32 to maintain its "0" during power shutdown.
At a later time, the VDD supply is returned to 5 volts. At the instant that power is restored, nodes N1 and N2 are each at 0 volt. This causes FET Q3 having the negative VT to begin to conduct and provide about 1 μa to node N1. FET Q4 having the positive VT remains off. Resistor R1 provides about 10 na to node N2. Both capacitances C1 and C2 begin to charge. Because the total current supplied to node N1 through resistor R1 and FET Q3 exceeds the total current supplied to node N2 through resistor R2 by a factor of about 100, capacitance C1 charges much more rapidly than capacitance C2. Accordingly, node N1 reaches the VT of FET Q2 to turn it on before node N2 can reach the VT of FET Q1. As FET Q2 turns on, it draws node N2 back down to 0 volt so as to keep FET Q1 turned off. Node N1 continues to rise to 5 volts as volatile location 31 latches in its original "0" state.
Precisely the opposite occurs when location 31 is initially at "1" with FET Q1 on and FET Q2 off. When the VDD supply is raised from 5 volts to 20 volts, node N1 stays at 0 volt and node N2 rises from 5 volts to 20 volts. FET Q3 turns off as its VT reaches a positive level of 6.5 volts. FET Q4 turns on as its VT reaches a negative level of -5 volts. This constitutes a "1" in location 32. The resultant negative and positive charges on gates F3 and F4 remain during the subsequent power shutdown. When power is restored to 5 volts, capacitance C2 charges much more rapidly through resistor R4 and FET Q4 than capacitance C1 charges through resistor R3. Acordingly, FET Q4 turn on first while FET Q3 remains off as location 31 latches in its original "1" state.
As with cell 20, cell 30 may be operated in a second mode in which the VDD supply is pulsed to 20 volts to program the logic state of location 31 into location 32 after which the VDD supply is returned to 5 volts (rather than being shut down). In a group of memory cells 30, the portion consisting of locations 31 then serves as a "working" memory while the portion consisting of locations 32 forms a "permanent" memory. At any time, the original data in the memory can be restored in the manner described above for the second mode of operation of cell 20.
Methods for manufacturing the various elements of the present invention are well known in the semiconductor art. FIG. 3 shows a layout view of a preferred embodiment of memory cell 20 manufactured according to N-channel planar processing techniques using oxide isolation to separate active semiconductor regions in a semiconductor wafer. In particular, FIG. 3 shows the N type region 40 that encompasses FET's Q1, Q2, Q3, Q5, Q7, and Q8 and lies along the top of the wafer below overlying insulating material and electrical connections. The overlying insulation material is not shown at all except for the areas in slanted lines running from the lower left to the upper right that represent the extensions of the dielectric material located between the channels of the various FET's and their gate electrodes which are shown as unshaded areas. The area shaded in slanting lines running from the upper left to the lower right represents the recessed insulating material 42 laterally separating the various active regions such as region 40 from one another. The overlying electrical connections are indicated as thick lines extending between the insulated-gate electrodes and the contact windows which are depicted as small rectangles or squares. Each buried contact window is further indicated with an "X". In addition to the reference symbols previously defined, "S", "D", and "G" followed by a number which is the numerical part of the symbol for an FET indicate its source, drain, and insulated-gate electrode, respectively. An item that serves as a common element for two or more FET's is indicated by the appropriate reference symbol separated by a slash.
To further illustrate the construction of the memory circuit of the invention, FIG. 4 shows a cross-sectional side view of a portion of the embodiment of FIG. 3 taken through the plane 4--4 therein. All of the elements circuit of FIG. 1 not shown in FIG. 4 as well as all of the other transistors, resistors, and other elements of the present memory circuit including the external read/write circuit are preferably fabricated in the manner described below. Furthermore, memory cell 30 and its read/write circuit are fabricated in this manner.
Conventional masking, etching, and cleaning techniques are employed in creating the various doped regions shown in FIG. 4. To simplify the discussion, references to the masking, etching, cleaning, and other such well known steps in the semiconductor art are omitted from the following fabrication discussion.
Boron is utilized as the P-type impurity for creating the regions of P-type conductivity on the wafer. Phosphorus and arsenic are used selectively as the complementary N-type dopants. Other appropriate impurities may be used in place of these dopants. In many of the ion implantation steps, an impurity may alternatively be introduced into the wafer by diffusion or vice versa.
The starting material is a <100> P-type monocrystaline silicon substrate 44 having a resistivity of about 25 ohm-cm. Boron (B+) is selectively ion implanted at a dosage of 6�1013 ions/cm2 and at an energy of 60 kiloelectron volts (KEV) into the field areas--i.e., the areas outside of the intended active areas such as region 40. Oxide-isolation region 42 having a depth of about 1.0 micron is then formed according to conventional techniques to define active region 40 and laterally electrically isolate it from other such active regions. During the formation of oxide region 42, the boron implanted in the field areas diffuses further downward to form P anti-inversion region 46 that lies below region 42 and extends partly up its sidewalls.
Arsenic (As+) is then selectively implanted at a dosage of 3�1013 ions/cm2 and at an energy of 100 KEV into region 40 to create N+ region 48 generally below the intended location for the tunneling insulating layer. A 1,000-angstrom layer of silicon dioxide is grown along the upper surface of region 40. The portion of this oxide layer above the intended site for gate F3 is etched away down to the underlying silicon. At the exposed silicon, a thin layer of silicon dioxide having a thickness of about 80 angstroms is grown. A first layer of intrinsic polycrystalline silicon (polysilicon) having a thickness of about 2,500 angstroms is deposited on the top of the wafer. Arsenic (As+) is implanted at a dosage of 5�1013 ions/cm2 and at an energy of 100 KEV into the first polysilicon layer to make it conductive. Resistors R1 and R2 and gate F3 are now defined in the first polysilicon layer by appropriately patterning it. The exposed silicon dioxide on the top of the wafer is etched away down to the underlying silicon. Below gate F3, this leaves tunneling oxide layer 50 as the remaining portion of the 80-angstrom oxide layer. The top of the wafer is oxidized to grow a 700-angstrom layer of silicon dioxide from the monocrystalline silicon and a 900-angstrom oxide region 52 from the polysilicon above and along side gate F3.
The FET threshold voltages are now established by implanting arsenic (As+) at a dosage of 1.0�1012 ions/cm2 and at an energy of 100 KEV into the channel area for FET Q5 and then implanting boron (B+) at a dosage of 4�1011 ions/cm2 and at an energy of 45 KEV into the channel areas for FET's Q1, Q2, Q5, Q7, and Q8. After selectively etching the intended areas for the buried contacts down to the monocrystalline silicon, a second layer of polysilicon is deposited on the top of the wafer. Phosphorus is then diffused into the second polysilicon layer to achieve a sheet resistance of 30 ohms/square. The second polysilicon layer is patterned by selective etching so as to define electrodes G1, G2, G3, G5, G7, and G8, the intermediate electrical connections extending from these electrodes, and the electrical connections connecting the ends of resistors R1 and R2 to their buried contact areas. The exposed silicon dioxide at the top of the wafer is etched down to the underlying silicon, after which a 300 -angstrom barrier oxide layer is grown. Arsenic (As+) is selectively implanted at a dosage of 1�1016 ions/cm2 and at an energy of 120 KEV through the barrier oxide layer to form the N+ source/drain regions such as N+ source S3. The wafer is subjected to an oxidizing environment to increase the thickness of the barrier oxide layer to 600 angstroms at the source/drain areas. The polysilicon also oxidizes during this step so as to leave a 1,000-angstrom oxide layer 54 on top of electrode G3.
The wafer is now finished according to conventional techniques. A layer 56 of Vapox (silicon dioxide with about 8% P2 O5) is deposited on the top of the wafer. Holes are etched through the Vapox layer down to the underlying silicon at locations intended for the contacts for supplies VDD and VSS and lines 25 and 26. Phosphorus is then diffused through these holes into the underlying silicon to attain a sheet resistance of about 6 ohms/square. Aluminum with 1% silicon is deposited on top of the wafer and patterned to create lines 25 and 26 and the electrical conductors leading to the VDD and VSS supplies. After annealing the wafer to alloy the aluminum to the silicon and repair lattice damage, a passivation layer is deposited on the top of the wafer to provide scratch protection, and openings are formed through the passivation layer to expose the external contacts.
While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, semiconductor materials of opposite conductivity type to those described above may be employed to accomplish the same results. The variable-threshold FET(s) could be MNOS devices. Thus, various modifications, changes, and applications may be made by those skilled in the art without departing from the true scope and spirit of the invention as defined by the appended claims.
|Cited Patent
|Filing date
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|Mar 4, 1976
|Jun 13, 1978
|Rca Corporation
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|J. Drori et al., A Single 5V Supply Nonvolatile Static RAM , 1981 IEEE ISSCC Dig. of Tech. Papers, Feb. 19, 1981, pp. 148 149.
|Citing Patent
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|Feb 14, 1986
|Nov 10, 1987
|Rockwell International Corporation
|Non-volatile RAM cell with dual high voltage precharge
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|Oct 25, 1988
|Sierra Semiconductor Corporation
|Electrically alterable non-volatile memory device
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|Jul 4, 1989
|International Business Machines Corporation
|Non-clocked static memory cell
|Oct 31, 1988
|Feb 19, 1991
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|Mar 17, 1992
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|Non-Volatile, static random access memory with current limiting
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|Output circuit provided with source follower circuit having depletion type MOS transistor
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|Macronix International Co., Ltd.
|Nonvolatile static random access memory
|Jun 10, 2004
|Feb 16, 2010
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|Feb 1, 2011
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|Sense transistor protection for memory programming
|Nov 22, 2011
|Cypress Semiconductor Corporation
|Architecture of a nvDRAM array and its sense regime
|Dec 6, 2011
|Cypress Semiconductor Corporation
|Line driver circuit and method with standby mode of operation
|Aug 24, 2011
|Nov 20, 2012
|Cypress Semiconductor Corporation
|Method and apparatus to implement a reset function in a non-volatile static random access memory
|Apr 8, 2011
|Jun 11, 2013
|Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University
|Differential threshold voltage non-volatile memory and related methods
|Apr 8, 2011
|Jul 16, 2013
|Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University
|Differential threshold voltage non-volatile memory and related methods
|Mar 14, 2013
|Feb 3, 2015
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|Non-volatile latch structures with small area for FPGA
|Jun 10, 2004
|Jul 20, 2006
|Koninklijke Philips Electronics N.V.
|Non-volatile static memory cell
|Aug 25, 2006
|Jun 21, 2007
|Arun Khamesra
|Line driver circuit and method with standby mode of operation
|May 22, 2008
|Dec 4, 2008
|Fredrick Jenne
|Sense transistor protection for memory programming
|Dec 31, 2007
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|Architecture of a nvDRAM array and its sense regime
|Mar 14, 2013
|Jul 17, 2014
|Cypress Semiconductor Corporation
|Non-Volatile Latch Structures with Small Area for FPGA
|Jun 10, 2004
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|Non-volatile static memory cell
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|Arizona Board Of Regents, For And On Behalf Of Arizona State University
|Differential threshold voltage non-volatile memory and related methods
|U.S. Classification
|365/154, 257/316, 257/904
|International Classification
|Cooperative Classification
|European Classification
|Jul 16, 1982
Owner name: SIGNETICS CORPORATION, 811 EAST ARQUES, SUNNYVALE,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:KESHTBOD, PARVIZ;REEL/FRAME:004052/0817
Effective date: 19820701
|Dec 17, 1985
|Certificate of correction
|Dec 27, 1988
|Fee payment
Year of fee payment: 4
|Jan 4, 1993
|Fee payment
Year of fee payment: 8
|Feb 4, 1997
|Maintenance fee reminder mailed
|Jun 29, 1997
|Lapse for failure to pay maintenance fees
|Sep 9, 1997
|Expired due to failure to pay maintenance fee
Effective date: 19970702


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The Grossest Bugs on Earth
List Criteria: Only arthropods that are actually shuddery-gross... not necessarily scary or dangerous.
I love insects. I do. I fear spiders, but I respect them and try not to let my fear control me when I see one. However, there are bugs that are simply gross. Just really, really gross. Not just ugly (though, definitely ugly), but also nasty in their habits and their behavior. These are the grossest bugs in the world. I know I've left some off the list, so go ahead and add any I've missed. Vote up the nastiest of the nasty.
These aren't the scariest bugs you'll ever happen across, though some might give you a fright. These little dudes are just super gross - the grossest, nastiest bugs ever.
- 1+ 28- 10
Cattle TickvOh jeez. This list is seriously making me gag. Ticks are bad enough, their whole nasty family of bloodsucking disease-carriers... but Cattle Ticks? If any of you have ever spent any time around livestock, you know what I mean. Horses, sheep and cattle... you'll be walking by or maybe grooming a horse and GAAAAHHHH! It's the size of a grape. A GRAPE! and it's all white and giant, and filled with blood.And you have to get some horseshoe tongs or something and pull it off and... ok, I'm totally traumatized now. This is why I am not living on a ranch right now, people.
- 2+ 19- 7
Cave SpiderAlso known as the Tailless Whip Scorpion, this is neither a spider nor a scorpion. But it sure the @$#%#$% is terrifying.
- 3+ 26- 14vShudder. It's like a cross between two of the most creepy things - spiders and centipedes.House centipedes actually feed on spiders, bed bugs, termites, cockroaches, silverfish, ants, and other things we hate in our house. Too bad they are almost worse. It turns out that the thing that's the most creepy about them, their gazillion long legs, is how they administer their venom! GAH! So strictly speaking they sting rather than bite and they tend to do it at night. When the centipede is in danger of becoming prey itself, it can detach any legs that have become trapped.Of course it can.
- 4+ 27- 16
Camel Spiderv
- 5+ 15- 7vHey! Everyone loves cockroaches! What are they doing on this list? All filthy and skittering and impossible to smash. Hiding in dark corners and swarming on all their gross hairy legs. In our KITCHEN! Where the food is!Yes. This is the king of gross, this thing. I love bugs, and I can't STAND these things.They are FAST. I mean, they should be impressive if they weren't so nasty. They've been clocked at 3.4 mph, about 50 body lengths per second, which would be is like a human running 210 mph. They are adaptative and ridiculously bulletproof. The myth about them surviving radiation is no myth.
- 6+ 12- 5
Asian Giant HornetAdded by: KellyLacourse
- 7+ 16- 10
EarwigvThere must be something about a shiny carapace, right? Or maybe it's those little moving pincher things on the butt, which they use to capture and hold prey.Their gross name may be related to the old wives' tale that earwigs burrowed into the brains of humans through the ear and laid their eggs there. Earwigs like hiding in warm humid crevices and I suppose nothing is stopping thrm from occasionally crawling into the human ear canal (much like any other small organism). Not that I've ever heard of something like that happening. (Though a spider did once crawl into mom's ear when she was sleeping. I know. I didn't sleep for a week after that.)Earwigs can also do that cockroach thing and get all flat to fit into the tiniest places you could ever imagine. Barf.
- 8+ 17- 13
Bed Bugv
More blood suckers. And these are in your bed while you sleep.
Most species feed on humans only when other prey are unavailable. Their bites are not usually noticed at the time. The neck and jaw line are particularly favored places to feed.
It usually spends less than 20 minutes in physical contact with its host, and once its full, it will not attempt to feed again until it has either completed a molt or, if an adult, has thoroughly digested the meal.


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Tell It!
The year was 1975 and something significant had just happened to me. I needed to find my friend Francis, with whom I shared a lot of personal matters, and tell him about it. I found him in his apartment hurriedly preparing to go out, but I slowed him down. The way he stared at me, he must have sensed that I had something important to tell him. "What is it?" he asked. So I told him simply, "Yesterday I surrendered my life to Jesus!"
Francis looked at me, sighed heavily, and said, "I've felt like doing the same for a long time now." He asked me to share what happened, and I told him how the previous day someone had explained the gospel to me and how I asked Jesus to come into my life. I still remember the tears in his eyes as he too prayed to receive Jesus' forgiveness. No longer in a hurry, he and I talked and talked about our new relationship with Christ.
After Jesus healed the man with an evil spirit, He told him, "Go home to your own people and tell them how much the Lord has done for you, and how he has had mercy on you" (Mark 5:19). The man didn't need to preach a powerful sermon; he simply needed to share his story.
No matter what our conversion experience is, we can do what that man did: "[He] went away and began to tell . . . how much Jesus had done for him."
Broken to Be Made New
During World War II my dad served with the US Army in the South Pacific. During that time Dad rejected any idea of religion, saying, "I don't need a crutch." Yet the day came when his attitude toward spiritual things would change forever. Mom had gone into labor with their third child, and my brother and I went to bed with the excitement of soon seeing our new brother or sister. When I got out of bed the next morning, I excitedly asked Dad, "Is it a boy or a girl?" He replied, "It was a little girl but she was born dead." We began to weep together at our loss.
For the first time, Dad took his broken heart to Jesus in prayer. At that moment he felt an overwhelming sense of peace and comfort from God, though his daughter would always be irreplaceable. Soon he began to take an interest in the Bible and continued to pray to the One who was healing his broken heart. His faith grew through the years. He became a strong follower of Jesus—serving Him as a Bible-study teacher and a leader in his church.
Jesus is not a crutch for the weak. He is the source of new spiritual life! When we're broken, He can make us new and whole (Ps. 119:75).
Knowing and Doing
Chinese philosopher Han Feizi made this observation about life: "Knowing the facts is easy. Knowing how to act based on the facts is difficult."
A rich man with that problem once came to Jesus. He knew the law of Moses and believed he had kept the commandments since his youth (Mark 10:20). But he seems to be wondering what additional facts he might hear from Jesus. " 'Good teacher,' he asked, 'what must I do to inherit eternal life?' " (v. 17).
Jesus' answer disappointed the rich man. He told him to sell his possessions, give the money to the poor, and follow Him (v. 21). With these few words Jesus exposed a fact the man didn't want to hear. He loved and relied on his wealth more than he trusted Jesus. Abandoning the security of his money to follow Jesus was too great a risk, and he went away sad (v. 22).
What was the Teacher thinking? His own disciples were alarmed and wanted to know "Who then can be saved?" He replied, "With man this is impossible, but not with God; all things are possible with God" (v. 27). It takes courage and faith. "If you declare with your mouth, 'Jesus is Lord,' and believe in your heart that God raised him from the dead, you will be saved" (Rom. 10:9).
The Greatest Invitation
During a recent week, I received several invitations in the mail. Those inviting me to attend "free" seminars on retirement, real estate, and life insurance were immediately thrown away. But the invitation to a gathering honoring a longtime friend caused me to reply immediately, "Yes! I accept." Invitation + Desire = Acceptance
Isaiah 55:1 is one of the great invitations in the Bible. The Lord said to His people who were in difficult circumstances, "Come, all you who are thirsty, come to the waters; and you who have no money, come, buy and eat! Come, buy wine and milk without money and without cost." This is God's remarkable offer of inner nourishment, deep spiritual satisfaction, and everlasting life (vv. 2–3).
Jesus's invitation is repeated in the last chapter of the Bible: "The Spirit and the bride say, 'Come!' And let the one who hears say, 'Come!' Let the one who is thirsty come; and let the one who wishes take the free gift of the water of life" (Rev. 22:17).
We often think of eternal life as beginning when we die. In reality, it begins when we receive Jesus Christ as our Savior and Lord.
God's invitation to find eternal life in Him is the greatest invitation of all! Invitation + Desire = Acceptance.
Why Me?
Ruth was a foreigner. She was a widow. She was poor. In many parts of the world today she would be considered a nobody—someone whose future doesn't hold any hope.
However, Ruth found favor in the eyes of a relative of her deceased husband, a rich man and the owner of the fields where she chose to ask for permission to glean grain. In response to his kindness, Ruth asked, "What have I done to deserve such kindness? . . . I am only a foreigner" (Ruth 2:10 nlt).
Boaz, the good man who showed Ruth such compassion, answered her truthfully. He had heard about her good deeds toward her mother-in-law, Naomi, and how she chose to leave her country and follow Naomi's God. Boaz prayed that God, "under whose wings" she had come for refuge, would bless her (1:16; 2:11-12; see Ps. 91:4). As her kinsman redeemer (3:9), when Boaz married Ruth he became her protector and part of the answer to his prayer.
Like Ruth, we were foreigners and far from God. We may wonder why God would choose to love us when we are so undeserving. The answer is not in us, but in Him. "God showed his great love for us by sending Christ to die for us while we were still sinners" (Rom. 5:8 nlt). Christ has become our Redeemer. When we come to Him in salvation, we are under His protective wings.
Like Shooting a Fly
Macarena Valdes's skill in mapping underground mines made a real difference in the rescue of the 33 Chilean miners trapped after an explosion in October 2010. Drilling to find the exact place where the men were located was like "trying to shoot a fly from 700 meters away," she said. With her mining experience, Valdes was able to guide the probe to where the miners were entombed, which helped bring about their dramatic rescue.
In efforts to carry out spiritual rescues, it's easy to become discouraged. Although the apostle Paul faced even greater obstacles, he said, "We do not lose heart" (2 Cor. 4:1). Even though "the god of this age" had "blinded the minds of unbelievers, so that they cannot see the light of the gospel," he continued to proclaim the gospel of salvation (vv. 4-5). Compelled by God, who lovingly spoke light into his own darkness (v.6), Paul knew that what God had done for him God could do for others.
You and I may have a similar story. Compelled by the love of God, we too have reason not to lose heart. As Macarena led in the rescue of the miners, the Spirit of God can carry the light of our love and words into the hearts of those who need a rescue they may not yet understand.
The Meaning of a Name
According to a New York Times article, children in many African countries are often named after a famous visitor, special event, or circumstance that was meaningful to the parents. When doctors told the parents of one child that they could not cure the infant's illness and only God knew if he would live, the parents named their child Godknows. Another man said he was named Enough, because his mother had 13 children and he was the last one! There's a reason for everyone's name, and in some cases it also conveys a special meaning.
Before Jesus was born, an angel of the Lord told Joseph, "[Mary] will give birth to a son, and you are to give him the name Jesus, because he will save his people from their sins" (Matt. 1:21). Jesus is the Greek form of Joshua, which means "the Lord saves." In that day and culture, many children would have been named Jesus, but only one came into this world to die so that all who receive Him might live eternally, forgiven and freed from the power of sin.
Charles Wesley wrote these words we often sing as Christmas nears: "Come, Thou long-expected Jesus, born to set Thy people free; from our fears and sins release us; let us find our rest in Thee."
Jesus came to turn our darkness into light, to transform our despair into hope, and to save us from our sins.
The Heavenly Manifest
At the Kenya Airways check-in counter, I presented my passport for verification. When the agents searched for my name on their manifest—the document that lists names of passengers—my name was missing. The problem? Overbooking and lack of confirmation. My hope of reaching home that day was shattered.
The episode reminded me of another kind of manifest—the Book of Life. In Luke 10, Jesus sent His disciples on an evangelistic mission. On their return, they happily reported their success. But Jesus told them: "Do not rejoice that the spirits submit to you, but rejoice that your names are written in heaven" (v. 20). The focus of our joy is not merely that we are successful but that our names are inscribed in God's book.
But how can we be sure of that? God's Word tells us, "If you declare with your mouth, 'Jesus is Lord,' and believe in your heart that God raised him from the dead, you will be saved" (Rom. 10:9).
In Revelation 21, John makes a breathtaking description of the Holy City that awaits those who trust Christ. Then he writes, "Nothing impure will ever enter it, nor will anyone who does what is shameful or deceitful, but only those whose names are written in the Lamb's book of life" (v. 27).
The Book of Life is God's heavenly manifest. Is your name written in it?


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Relevant offers
Smart man, Ernie Merrick.
Plenty of people, football fans and otherwise, will be interested in whether the Wellington Phoenix can kick on from last Saturday's sumptuous 5-0 dismantling of the Melbourne Victory.
You can't produce football that clinical and of that much quality without also building the expectation that it could, or should, happen again.
Well, to listen to Merrick, there's little chance that the Phoenix will trouble, let alone beat, the A-League-leading Brisbane Roar at Suncorp Stadium tonight.
There's no way the Phoenix coach actually believes that. But by indicating that he expects little out of this match, he has completely removed any burden from his players.
They can now play without fear of the consequences, because Merrick has said this match will have no bearing on their season. He has asked them to perform well, but placed no emphasis on the result.
You have to admire the Scot's canniness. Behind closed doors he will have devised a gameplan to thwart the Roar and pumped the players full of the confidence required to do it.
But in public, he has only really spoken about how the absence of Carlos Hernandez and Kenny Cunningham, on international duty, and Matthew Ridenton (injury) might hamper his team and how good Brisbane are at home.
Both things are true, but you don't become the most successful coach in A-League history, as Merrick is on the back of his previous achievements at the Victory, by not being able to pick up points away from home in difficult circumstances.
The Phoenix aren't quite in the same league as Merrick's old Victory sides, but they are definitely trending in the right direction.
He has also had a bit of luck in the build-up. Brisbane might be top of the table, but their recent run of games haven't been the greatest, with losses to Newcastle and Adelaide and agoalless draw with Perth among them.
The suspension of Victory-bound Albanian striker Besart Berisha adds further pressure for the Roar. News of his departure, at season's end, will be both wounding and a distraction, given what a massive player and personality he has been for the club.
Berisha, despite not playing, is the talk of the Brisbane football market, taking all the scrutiny away from the Phoenix. Had Berisha not been suspended there might have been an element of business as usual about this.
But, with him out, you imagine the Brisbane players will be trying extra hard to show they're not bothered by his defection and that he won't be missed. It's just the sort of disruption the Phoenix could profit from.
Elsewhere, Adelaide host the Melbourne Heart and the Central Coast have their derby game against Newcastle tomorrow, with the Victory at home to Sydney FC and Perth travelling to the Western Sydney Wanderers on Sunday.
- Fairfax Media
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The BOULEVARD at Box Hill is just minutes from Bel Air, Havre de Grace and White Marsh. Bustling with activity, we're ready to meet the needs of all types of shoppers and dining guests.
Looking to shop locally? We're Harford County's premier shopping experience.
Whether shopping locally at department stores like JC Penney or Old Navy, or at specialty stores like the Loft — the BOULEVARD is your local shopping destination!
Shopping for fashion jewelry to fit every look and style? XO by Saxons offers jewelry, accessories and handbags with boutique-style flair.
Need to rejuvenate? The Spa On The Boulevard is here to pamper your mind, body and spirit. Help your pets get the pampering they need with supplies at Pet Value.
Love feeding the local birds? WildBirds Unlimited can provide you with information to get to know your local birds and their needs.
Looking for a new place to eat? The Boulevard at Box Hill is your place for great food. Enjoy elegant Asian dining at Lemon N Ginger, and two new restaurants coming this Fall, Bostons Restaurant & Sports Bar and Ocean City Brewing Company, we have you covered.
Need to eat on the go? Stop in to eat fresh at Subway. Grab a power bowl or bagel at Panera Bread. Or grab a ready to go meal at Wegmans.
Have a sweet tooth to feed? Try out the treats at Menchies Frozen Yogurt.
You can also find Sprint, ATI Physical Therapy and PNC Bank on this 40 acre open-air plaza.
Located less than a mile from I-95, BOULEVARD is just minutes away from Abingdon, Bel Air, Havre de Grace and White Marsh.
We are conveniently located to serve both Harford and Cecil Counties. For a complete list of stores and restaurants see our Directory.
News and Events
We're starting something new at the Boulevard - free live music! Grab the family, bring your chairs and blankets to the Boulevard. Relax and enjoy some great music as the sun sets in Harford County. Our first of three summer concerts will be held June... Read more
Come to Boston's (Abingdon) this Wednesday and every Wednesday for a family fun day. Bring your children to dine in their favorite costumes and be served in our dining area by our staff dressed in their favorite Disney costumes as well.Moms and Dads could join in the fun too - we won't... Read more


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Watch the highlights of the Bezos-backed Blue Origin rocket's 4th flight
The latest Blue Origin test marks the fourth time this rocket and capsule have flown to space together.
The latest Blue Origin test marks the fourth time this rocket and capsule have flown to space together.
Blue Origin aired its fourth test flight of the New Shepard suborbital space system live online Sunday.
Blue Origin will launch the fourth test flight of its New Shepard space system on Sunday. Watch it live.
Amazon is pumping money into its fastest-growing market in the world.
Amazon appears to have acquired a taste for brick and mortar.
"If you absolutely can't tolerate critics, don't do anything new or interesting."
The expansive future of artificial intelligence is mostly ahead of us says Amazon's CEO Jeff Bezos.
Jeff Bezos pulls the strings, and Amazon skyrockets.
The Blue Origin vs. SpaceX space race is just getting started.
One incremental step closer to launching humans to space.
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"If we were invested in a company that knowingly engaged in so much illegal activity, we would think twice about keeping our money in that company."
Blue Origin is gearing up for big things.
What goes up, must come down.
Bezos gave a journalistic pep talk in a town hall held at the Post's headquarters on Monday.
Jeff Bezos vs. Elon Musk. Netflix vs. NBC. Episode two of Biz Please brings the beef.
One day this video will be viewed as the beginning of something big.
Had a rough year? Well, the world's richest people might make you feel just a little better about it.
Hint: It can fit on a shelf.
This marks a revolutionary moment for private spaceflight.
Unto Elon Musk's finest moment, Bezos throws a little shade -- and gets slammed for it.
The private space race has hit another gear.
There's no shade like the shade that space-exploring billionaires throw at each other.
Jeff Bezos has joined Twitter, where we can only assume he will spend his time dealing with Amazon customer service complaints.
"Full reuse is a game changer, and we can't wait to fuel up and fly again."
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Jeff Bezos, founder and CEO of Amazon.com, announced Tuesday that Blue Origin will make Florida's Space Coast its home port for reusable rocket launches.
Tech companies believe in hard, boostrapping work -- which often leaves little time for family.
Bezos denied Amazon is a place where adults cry at their desks, coworkers undermine one another and staff are "edged out" of their roles after cancer or miscarriages.
The internet superstore is battling it out with Wal-Mart to bring you better discounts.


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The pull of patolaA saree may cost upwards of Rs. 1.5 lakh, but the Salvi family is booked with orders for three years The unassuming town of Patan in Gujarat stands amid the ruins of the once-powerful Solanki dynasty that reigned between the 10th and 13th ... The Hindu, 1 month ago
Did Kamya Punjabi borrow Rs 2.5 lakhs from Pratyusha Banerjee?
Replay Video Manasi Salvi ENDS Her 11 Years Old Marriage With Hemant Prabhu Pyaar Ka Dard Hai Meetha Meetha Pyaara Pyaara actress Manasi Salvi has decided to end her 11 years old marriage with husband Hemant Prabhu.. Check out the video to ...MSN News US, 1 month ago
Mumbai: Lack of public toilets biggest concern in H/East Ward
By Ranjeet Jadhav and Shikha Vatsala | Posted 1 hour A large part of the H-East ward is occupied by slums, where residents have to make do without drinking water or public toilets, despite fresh assurances before every election Spread across ...Mid Day, 1 week ago
Sand mining: Green tribunal appoints panel to inspect sites
The National Green Tribunal has constituted a panel to inspect the Betwa river bank in Jalaun and Hamirpur districts of Uttar Pradesh and probe the allegations of rampant illegal sand mining in the area. A Bench headed by Justice U. D. Salvi, ...The Hindu, 2 weeks ago Sand mining: NGT appoints panel to inspect Jalaun and Hamirpur Times of India, 2 weeks ago
'Anurag Thakur can easily lead BCCI into a new era'
'The main reason for having neutral venues for the Ranji Trophy is to make it more competitive and less affected by doctoring of wickets.''There is no reason why people shouldn't be able to see Virat Kohli playing a Ranji Trophy match at any location.' BCCI Secretary Ajay Shirke speaks to Harish Kotian/Rediff.com in an exclusive interview. IMAGE: BCCI Secretary Ajay Shirke, left, with board President Anurag Thakur, MP. Photograph: Sahil Salvi The Board of Control for Cricket in India has been ...Rediff.com, 3 weeks ago
NGT halts eco-park work in Surajpur wetlands
Noida: The National Green Tribunal (NGT) on Monday ordered an immediate halt to all construction activities on the Surajpur wetland in the reserved forests in Gautam Budh Nagar forest division, effectively stalling the work of an eco-park proposed ...Times of India, 3 weeks ago NGT notice to Environment Ministry on Surajpur wetlands Press Trust of India, 1 month ago
NGT notice to SDMC for construction on Saket storm water drain
New Delhi, May 15 () The National Green Tribunal has issued notice to South Delhi Municipal Corporation (SDMC) to show cause why coercive steps be not taken against it for failing to stop construction on the Saket storm water drain allegedly by ...Times of India, 1 month ago Green court notice to SDMC for construction on Saket storm water drain Millennium Post, 1 month ago DMRC to NGT: Green clearance not required for Metro projects Hindustan Times, 1 month ago
NGT notice to Centre on groundwater extraction in G'bad, Hapur
New Delhi, Apr 26 () Heeding to the plea that incessant extraction of groundwater by industries and households in the neighbouring Ghaziabad and Hapur districts has resulted in depletion of water table, the National Green Tribunal today sought ...Times of India, 1 month ago
Prison doctor removed for fudging Bhujbal's medical records
An inquiry by the prisons department into the admission of former Maharashtra Deputy Chief Minister Chhagan Bhujbal to St George Hospital in Mumbai has revealed that a doctor at Arthur Road Jail had manipulated papers to help the jailed Nationalist Congress Party leader. Bhujbal, remanded in judicial custody in an alleged money laundering case, was admitted to ICU of the multi-speciality hospital in South Mumbai on April 18 after he complained of severe chest pain and high blood pressure.Rediff.com, 2 months ago
Rakhi Sawant's solution to stopping suicides: Remove ceiling fans, use AC!
Everyone has his/her own views on TV actor Prayusha's suicide but none as ridiculous as Rakhi Sawant. IMAGE: Rakhi Sawant poses with a small ceiling fan. Photograph: Sahil Salvi Balika Vadhu actress Pratyusha Banerjee's suicide has got all kinds of reactions from the world of showbiz. While actors like Vahbbiz Dorabajee said suicide is not an option, stars like Hema Malini have called it 'senseless.' But the most startling reaction comes from Rakhi Sawant, who held a press ...Rediff.com, 2 months ago
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