A drive circuit for an LED array, comprising at least two clusters of LEDs, in which one cluster comprises a number of LEDs arranged in series which are connected to a supply voltage (UBatt), with a semiconductor switch (T) being arranged in series between each LED cluster and the associated supply voltage, which semiconductor switch (T) allows the LED current to be supplied in a pulsed manner, with a measurement resistor (RShunt) being arranged in series with the LEDs in the path for the forward current IF between the LEDs and ground. A control loop controls the semiconductor switch (T1) in a first LED cluster, referred to as the master cluster in the following text, such that a constant mean value of the LED current is achieved, wherein the master cluster has a predetermined number X of LEDs in its cluster, and with this control loop also driving at least the semiconductor switch (T2) in a further, LED cluster, referred to in the following text as the slave cluster.

The invention is based on a drive circuit for LEDs and an associated operating method. This relates in particular to reducing the drive power losses in light-emitting diodes (LEDs) by means of a pulsed LED drive circuit.
As a rule, series resistors are used for current limiting when driving light-emitting diodes (LEDs), see, for example, U.S. Pat. No. 5,907,569. A typical voltage drop across light-emitting diodes (UF) is a few volts (for example, for Power TOPLED UF=2.1 V). The known resistor Rv in series with the LED (see FIG. 1 in U.S. Pat. No. 6,400,101) produces a particularly high power loss, particularly if the battery voltage UBatt is subject to major voltage fluctuations (as is normal in motor vehicles). The voltage drop across the LED still remains constant even when such voltage fluctuations occur, that is to say the residual voltage across the series resistor Rv falls. Rv is thus alternately loaded to a greater or lesser extent. In practice, a number of LEDs are generally connected in series (cluster) in order to achieve better drive efficiency (FIG. 2 in U.S. Pat. No. 6,400,101). Depending on the vehicle power supply system (12 V or 42 V), an appropriate number of LEDs can be combined to form a cluster. With a 12 V vehicle power supply system, there is a lower limit on the battery voltage UBatt down to which legally specified safety devices (for example the hazard warning system) must be functional. This is 9 volts. This means that, in this case, up to 4 Power TOPLEDs can be combined to form a cluster (4xc3x972.1 V=8.4 V).
Furthermore, U.S. Pat. No. 6,400,101 describes the use of a pulsed LED drive to reduce the drive power loss in light-emitting diodes (LEDs). When the LEDs are driven in this way, the current is regulated autonomously in each individual LED cluster. This leads to the maximum possible reliability (intelligent LED driver module, see FIG. 4 in U.S. Pat. No. 6,400,101). However, a relatively large number of LED driver modules are required to illuminate a relatively large areaxe2x80x94as is the case with motor vehicle tail lightsxe2x80x94using this technique, and this results in considerable costs. The number of LED driver modules depends on two factors.
The smaller the available supply voltage Uv for the LED cluster, the greater is the number of clusters required.
The greater the forward voltage drop UF across the LEDs which are intended to be used for an LED cluster, the smaller is the number of LEDs which can be used in one cluster.
The greater the number of LED driver modules required, the greater are the costs.
The requirements to which an LED drive as described in U.S. Pat. No. 6,400,101 is subject are, of course, complied with, for example temperature regulation and fault identification are possible in the LED cluster.
One object of the present invention is to provide a drive circuit for LEDs which is simpler and thus considerably more cost-effective.
This object is achieved by the distinguishing features of claim 1. Particularly advantageous refinements can be found in the dependent claims.
The fundamental principle of the present invention is to cascade the already known drive system. An LED drive based on the concept in U.S. Pat. No. 6,400,101 is simplified in that the basic drive clock is governed by the clock (CLK) of the transistor T1 in a first higher-level LED cluster, which is referred to as the xe2x80x9cmasterxe2x80x9d in the following text, at the output of the comparator of the associated control loop, and this clock is also made available to other lower-level LED clusters (slaves) (FIG. 1). The resistors RSSn connected in series with the LEDs represent optional additional shunt resistors RShunt. These are not absolutely essential in operation, since their values are chosen to be very small (for example, RSS1=1xcexa9) and they do not adversely affect the setting of the forward current IF. However, if interruption identification is intended to be carried out in the slave clusters (see below) they are essential.
This concept in principle allows an area of any desired size to be illuminated using a single control loop. This is so-called master/slave current regulation, with the master cluster predetermining the clock (CLK) and all the additional LED clusters (slave clusters) being driven by the master clock.
In the simplest embodiment, only one master cluster is used. This solution is particularly cost-effective. However, in this case, it is advantageous to ensure that the number of LEDs in the slave clusters is the same as the number in the single master cluster. Otherwise, brightness and light intensity differences would occur.
In one particularly preferred embodiment, the number of LEDs in the clusters can be varied. In this case, there are two different embodiments for driving the LED clusters which have different numbers of LEDs (for example if the number of LEDs in the master cluster is greater):
In a first variant, a series load (resistor, zener diode or the like), in particular a series resistor Rxn, is connected in each n-th slave cluster, replacing the missing light-emitting diode (or light-emitting diodes). In this case, the master clock is the drive clock of that LED cluster which is driving the greatest number of light-emitting diodes (FIG. 2). The number of LEDs in the other clusters (slave clusters) may in this case be chosen to be the same, or less. It is advantageously not more than 30% less than the number in the master cluster, in order to avoid the losses becoming too large.
In a second variant, one or more additional LED control loops (second or third, etc. master control loop) is or are integrated in the LED drive module (IC), whose LED cluster operates with a smaller number of LEDs than the first master cluster. The battery voltage UBatt is in this case connected to all the transistors T. The drive clock of the second master control loop (CLK2) is then made available to the group of slave clusters having the corresponding, lesser number of LEDs (FIG. 3). This embodiment is suitable for groups of LED clusters which each have the same number of LEDs.
The failure rate of a master cluster is preferably also improved. This is because the master clock is no longer available to any of the connected slaves if the master fails, for whatever reason (for example interruption) The slaves are no longer driven, and must then likewise be switched off to protect them against destruction.
One of the slave clusters is thus advantageously in the form of a reserve master cluster. This means that a means is provided for identifying an interruption in the control loop of the master cluster and this means, for its part, is connected to a changeover switch in the control loop, with the changeover switch being connected on the one hand to the master cluster and on the other hand to the reserve master cluster. If the master fails, the switch is then changed to the reserve master cluster (FIG. 4). This redundancy ensures that, if the master is operating incorrectly (interruption), an immediate change is made to the reserve master. This ensures that the connected slaves (not shown) continue to receive their drive clock (master clock) for operation.
The reserve master is preferably used as a slave as long as the master 1 is operating normally.
Fault identification (malfunction) in the LED cluster is also preferably improved. The commonest fault types are interruptions and short-circuits. An LED failure always means an interruption. In this case, this means an interruption in the LED cluster, that is to say at least one LED has failed.
Nevertheless, it is possible for a short-circuit to occur, to be precise in the sense of an interruption in the electrical connecting line between the LED anode (A1) and ground (GND), see FIG. 5. Especially for use in motor vehicles (for example a tail light composed of LEDs), this type of fault must be detected so that appropriate countermeasures can be initiated in the event of a fault, such as immediately switching off the LED driver module or switching off only the short-circuited load circuit (LED cluster). The xe2x80x9cshort-circuitxe2x80x9d fault type can be caused, for example, by a rear impact in which the tail light is damaged.
Fault identification in all the clusters is thus highly recommended. For this purpose, detector inputs for the slave clusters are required in the driver module (IC), to be precise preferably a first input for interruption identification (FIG. 5, OL) and a second input for short-circuit identification (SC in FIG. 5). OL stands for xe2x80x9copen loadxe2x80x9d (interruption), while SC stands for short circuit.
The total number of detector inputs is governed by the number of slave clusters which are intended to be monitored. Normally, two module inputs are required per slave cluster.
The fundamental elements of an LED drive circuit are described in U.S. Pat. No. 6,400,101. Now, as shown in FIG. 5, elements are added for operation based on the master-slave method. For completeness, all of these are quoted here:
constant-current regulation of the forward current (IF=constant) for the LEDs
external, and thus flexible, forward-current adjustment
low power loss due to switched operation (no need for the large series resistor Rv)
interruption identification in the LED cluster
short-circuit identification on the LED cluster
temperature regulation in order to protect the LEDs
flexibility in driving different numbers of LEDs in the clusters, by means of a second LED master control loop
drive clock output (clock output) from the master 1 and the master 2 for the associated slave clusters with equal numbers of LEDs
increase in reliability by master switching
logic drive (microcontroller-compatible ENABLE input)
low intrinsic current draw by the drive circuit in operation and in the standby mode
resistant to polarity reversal (integrated in the IC, or can be provided externally by connector coding)
overvoltage protection
compact housing (for example Power SO housing for SMD technology)
temperature range xe2x88x9240xc2x0 C.xe2x89xa6Tj less than 150xc2x0 C.
42 V motor vehicle power supply system (also feasible for 12 V motor vehicle power supply system).

Control circuit for LED and corresponding operating method

Patent-Treuhand-Gesellschaft fuer Elektrische Gluehlampen mbH


A method for forming, within a double well formation, an array of DRAM memory cells isolated from each other by shallow trench isolation (STI), each cell comprising a MOSFET access transistor and a storage trench capacitor. A top plate of said capacitor is the trench wall within a deep N-well portion of the double well and the bottom plate is formed of a doped polysilicon layer within the trench, which layer is partially separated from the trench sidewalls by a dielectric layer whose upper portion is removed to allow the formation of a autodiffused doped channel between said polysilicon plate and the source region of the access transistor. The method uses a single dielectric layer deposition to serve as both a gate a gate dielectric for the MOSFET and a capacitor dielectric and requires only a single deposition of polysilicon to serve as both the transistor gate electrode and a capacitor plate.

1. Field of the Invention
This invention relates generally to the fabrication of dynamic random access memories (DRAM""s), particularly such memories in which the memory storage device is a deep trench capacitor and wherein individual memory cells are electrically isolated from each other by isolation trenches.
2. Description of the Related Art
Typical dynamic random access memories (DRAM""s) consist of densely packed arrays of memory cells which are themselves comprised of a charge storage device coupled to a charge accessing device. The charge storage device is usually a capacitor and the accessing device is usually a single MOS field effect transistor (MOSFET). The transistor can be connected at its source to one plate of the storage capacitor, at its drain to a conducting bit line and at its gate electrode to a conducting word line. In a normal operation in which a 1 or a 0 is written on or read from a particular memory cell, the particular cell is selected by choosing the appropriate pair of intersecting word and bit lines. Applying a given potential to the word line turns on the access transistor and a given charge applied to the bit line will then be deposited on the capacitor plate and stored. Conversely, during reading, the word line again activates the transistor and this time the presence of the charge in the capacitor is sensed by appropriate circuitry and identified as a 1 or 0.
A major problem associated with the design of increasingly dense arrays of memory cells is the necessity of decreasing the surface area of the storage capacitors while not decreasing their capacitance. Chatterjee et al. (U.S. Pat. No. 5,208,657) describes the difficulties of using planar capacitors as storage units in a DRAM module having a 5 volt power supply. Such a capacitor would require a capacitance of approximately 50 femtofarads (fF) and, in consequence, a capacitor area of approximately 20 square microns. Not only is this area overly large for the most densely packed circuits, but it presents an unacceptably vulnerable target for alpha particles which are a causal mechanism for soft error rates (SER). Chatterjee discloses the use of a trench capacitor, which is a capacitor formed in a trench or cavity that extends vertically into the substrate of the integrated circuit that can be produced by a variety of etching mechanisms. Such capacitors gain plate area and, hence, capacitance, through an increased vertical extension rather than by horizontal extension. One plate of such a capacitor is defined by the surface of the inner wall of the doped region of the substrate within which the trench is formed. Although this inner wall forms the plate boundary, charge can in fact also be stored within a depletion region formed beneath the wall surface and extending into the doped substrate. The other plate of the capacitor, which can also be a storage plate, is a conductive core that is deposited within the trench. An oxide layer is first formed over the inner trench wall to serve as a dielectric medium and to insulate one plate from the other. The prevalence of such trench capacitors within the practice of the prior art is illustrated by the work of Kato et al. (U.S. Pat. No. 4,907,047), which teaches a method of forming a memory cell comprising a storage capacitor having a first electrode formed in the side and bottom wall portions of a primary cavity and having a second electrode formed over a dielectric film which covers said first electrode. Motonami (U.S. Pat. No. 5,185,284) describes a xe2x80x9cgroovexe2x80x9d type capacitor (which is essentially a trench capacitor) which is circumscribed by a second capacitor to increase the overall capacitance of the combination. Cunningham (U.S. Pat. No. 6,177,697) describes a trench capacitor partially surrounded by a shallow trench isolation region (STI). The substrate is then doped through the inner surface of the trench capacitor, which is then lined with an oxide and filled with a polysilicon core to form a capacitor plate. A second capacitor plate is formed by the doped surface of the inner wall of the capacitor trench. Alsmeier et al. (U.S. Pat. No. 5,793,075) describes a deep trench capacitor within a lightly doped substrate wherein an inversion layer beneath the trench serves as one plate. Sakamoto et al. (U.S. Pat. No. 5,574,621) discloses a trench capacitor in which a plurality of conductor filled trenches connected by a conducting layer comprise a single bottom electrode and a second conducting layer, disposed over a dielectric layer, comprises a top electrode. Hoenigschmid et al. (U.S. Pat. No. 6,037,620) discloses a DRAM cell comprising a shallow isolation trench (STI), a storage trench capacitor partially overlaid by the STI and an access IGFET transistor connected to the perimeter of the capacitor by a conduction path that utilizes a buried strap interconnection.
The need to increase the density of memory cells and to integrate them with logic devices leads to complex fabrication processes. In particular, the fabrication of large DRAM arrays is complicated by a plurality of dielectric layer depositions to form gate and capacitor dielectrics and polysilicon depositions which are necessary to form the word and bit line connections to each cell and to provide connections between the access transistors and their associated storage capacitors. Even with the use of trench capacitors to reduce surface areas, the spacing between capacitors is limited by charge diffusion considerations. It is the purpose of the present invention to provide a method of isolating densely packed memory cells from each other while doing so in an efficient and cost effective manner that focuses on the minimization of dielectric and posysilicon depositions. In particular, the novel approach of forming the trench capacitor and the access transistor within a double well in which an isolation trench has already been formed provides an efficient method for forming cell plate connections having advantageous resistance properties.
A first object of this invention is to provide a method for forming one or a plurality of densely packed dynamic random access memory (DRAM) cells that can be efficiently and cost-effectively integrated with associated logic circuitry.
A second object of this invention is to provide such single or integrated DRAM cells that are characterized by low noise and soft error rates (SER).
A third object of this invention is to provide a method for forming one or a plurality of DRAM cells with high storage capacitance and low cell area.
A fourth object of this invention is to provide a method for forming DRAM cells and circuitry which can be diminished in dimension to levels exceeding that required by the 0.18 micron generation of devices and beyond.
A fifth object of this invention is to provide a method for forming such DRAM cells that produces a low cell plate connection resistance.
A sixth object of this invention is to provide a method for forming a DRAM memory cell that can be independently biased.
In accord with the objects of this invention there is provided a method for forming a single DRAM memory cell or an array of such DRAM memory cells in a semiconductor substrate. Each such cell includes a trench capacitor as a charge storage mechanism having a high capacitance and small surface area, a MOSFET as the accessing mechanism for storing and retrieving charge from the storage capacitor and a shallow isolation trench (STI) for electrically isolating one cell from another. Further in accord with the objects of this invention there is provided a method for forming the isolation trench, the capacitor and the transistor within a double well structure formed in the substrate, said well structure comprising a relatively shallow doped well of a first dopant type (the upper well) formed within a deeply implanted doped well of a second dopant type (the lower well). The isolation trench is contained within the upper well. The capacitor trench extends through the upper well and terminates within the lower well, wherein the trench bottom and the portion of its inner sidewall surface within said lower well forms one capacitor plate (a top plate) and the well itself provides a low resistance connection to said plate. A preferred embodiment of this invention discloses a double well which is a relatively shallow P-well substantially contained within a deep N-well formed in a silicon substrate. Further in accord with the objects of this invention, when more than one storage capacitor is to be formed within the same well structure in forming an array of memory cells, there is provided a method for separating the trench capacitors of neighboring memory cells by the formation of shallow trench isolation (STI) regions within the well structure. Yet further in accord with the objects of this invention, there is provided a method of forming the trench capacitor so that a substantial portion of the sidewalls and the bottom of the capacitor trench lie within the lower well, said portions thereby forming the top plate of the capacitor, while the bottom plate of said capacitor is formed by the deposition of a conducting layer which completely fills the interior of the trench, but is separated from the interior surface of the trench sidewall by a dielectric layer which contacts all regions of the trench sidewalls and base except a region within the upper well from which the dielectric layer has been removed and which the bottom plate thereby contacts electrically. Within the preferred embodiment, the conducting layer is a layer of doped polysilicon. Yet further in accord with the objects of this invention there is provided a method of forming an access transistor of the MOSFET type immediately adjacent to the trench capacitor, the gate electrode of said transistor being formed on a gate dielectric layer over the substrate surface above the double well and the source and drain of said transistor being formed beneath the gate electrode within the upper well of the double well formation and said transistor advantageously making direct electrical contact with the bottom plate of the trench capacitor by means of an doped region, autodiffused from the doped polysilicon bottom plate, that contacts said bottom plate through an upper region of the interior trench wall surface from which the dielectric layer has been removed. Still further in accord with the objects of this invention and to facilitate fabrication of said memory cells in an efficient and cost effective manner, there is provided a method of forming both the bottom capacitor plate, which is the conducting layer filling the trench, and the gate electrode and word line of its access transistor, using a single deposition of a conducting material, which is doped polysilicon in the preferred embodiment. Further in accord with the objects of the present invention there is provided a method of forming said DRAM structures while employing a single oxide growth process to form both the transistor gate oxide and the capacitor dielectric layer. Still further in accord with the objects of this invention there is provided a method of forming said DRAM structures and associated circuitry while using a minimum number of photolithography masking steps.

Single poly-Si process for DRAM by deep N well (NW) plate

Taiwan Semiconductor Manufacturing Company