A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter address in an offset format from the program counter address of a last transmitted program counter sync point and then transmits trace data in event offset format. If the first trace data following detection of corruption is a program counter sync point, then the trace transmits trace data in event offset format.

Advanced wafer lithography and surface-mount packaging technology are integrating increasingly complex functions at both the silicon and printed circuit board level of electronic design. Diminished physical access to circuits for test and emulation is an unfortunate consequence of denser designs and shrinking interconnect pitch. Designed-in testability is needed so the finished product is both controllable and observable during test and debug. Any manufacturing defect is preferably detectable during final test before a product is shipped. This basic necessity is difficult to achieve for complex designs without taking testability into account in the logic design phase so automatic test equipment can test the product.
In addition to testing for functionality and for manufacturing defects, application software development requires a similar level of simulation, observability and controllability in the system or sub-system design phase. The emulation phase of design should ensure that a system of one or more ICs (integrated circuits) functions correctly in the end equipment or application when linked with the system software. With the increasing use of ICs in the automotive industry, telecommunications, defense systems, and life support systems, thorough testing and extensive real-time debug becomes a critical need.
Functional testing, where the designer generates test vectors to ensure conformance to specification, still remains a widely used test methodology. For very large systems this method proves inadequate in providing a high level of detectable fault coverage. Automatically generated test patterns are desirable for full testability, and controllability and observability. These are key goals that span the full hierarchy of test from the system level to the transistor level.
Another problem in large designs is the long time and substantial expense involved in design for test. It would be desirable to have testability circuitry, system and methods that are consistent with a concept of design-for-reusability. In this way, subsequent devices and systems can have a low marginal design cost for testability, simulation and emulation by reusing the testability, simulation and emulation circuitry, systems and methods that are implemented in an initial device. Without a proactive testability, simulation and emulation plan, a large amount of subsequent design time would be expended on test pattern creation and upgrading.
Even if a significant investment were made to design a module to be reusable and to fully create and grade its test patterns, subsequent use of a module may bury it in application specific logic. This would make its access difficult or impossible. Consequently, it is desirable to avoid this pitfall.
The advances of IC design are accompanied by decreased internal visibility and control, reduced fault coverage and reduced ability to toggle states, more test development and verification problems, increased complexity of design simulation and continually increasing cost of CAD (computer aided design) tools. In the board design the side effects include decreased register visibility and control, complicated debug and simulation in design verification, loss of conventional emulation due to loss of physical access by packaging many circuits in one package, increased routing complexity on the board, increased costs of design tools, mixed-mode packaging, and design for produceability. In application development, some side effects are decreased visibility of states, high speed emulation difficulties, scaled time simulation, increased debugging complexity, and increased costs of emulators. Production side effects involve decreased visibility and control, complications in test vectors and models, increased test complexity, mixed-mode packaging, continually increasing costs of automatic test equipment and tighter tolerances.
Emulation technology utilizing scan based emulation and multiprocessing debug was introduced more than 10 years ago. In 1988, the change from conventional in circuit emulation to scan based emulation was motivated by design cycle time pressures and newly available space for on-chip emulation. Design cycle time pressure was created by three factors. Higher integration levels, such as increased use of on-chip memory, demand more design time. Increasing clock rates mean that emulation support logic causes increased electrical intrusiveness. More sophisticated packaging causes emulator connectivity issues. Today these same factors, with new twists, are challenging the ability of a scan based emulator to deliver the system debug facilities needed by today's complex, higher clock rate, highly integrated designs. The resulting systems are smaller, faster, and cheaper. They have higher performance and footprints that are increasingly dense. Each of these positive system trends adversely affects the observation of system activity, the key enabler for rapid system development. The effect is called "vanishing visibility."
FIG. 1 illustrates the trend in visibility and control over time and greater system integration. Application developers prefer the optimum visibility level illustrated in FIG. 1. This optimum visibility level provides visibility and control of all relevant system activity. The steady progression of integration levels and increases in clock rates steadily decrease the actual visibility and control available over time. These forces create a visibility and control gap, the difference between the optimum visibility and control level and the actual level available. Over time, this gap will widen. Application development tool vendors are striving to minimize the gap growth rate. Development tools software and associated hardware components must do more with less resources and in different ways. Tackling this ease of use challenge is amplified by these forces.
With today's highly integrated System-On-a-Chip (SOC) technology, the visibility and control gap has widened dramatically over time. Traditional debug options such as logic analyzers and partitioned prototype systems are unable to keep pace with the integration levels and ever increasing clock rates of today's systems. As integration levels increase, system buses connecting numerous subsystem components move on chip, denying traditional logic analyzers access to these buses. With limited or no significant bus visibility, tools like logic analyzers cannot be used to view system activity or provide the trigger mechanisms needed to control the system under development. A loss of control accompanies this loss in visibility, as it is difficult to control things that are not accessible.
To combat this trend, system designers have worked to keep these buses exposed. Thus the system components were built in a way that enabled the construction of prototyping systems with exposed buses. This approach is also under siege from the ever-increasing march of system clock rates. As the central processing unit (CPU) clock rates increase, chip to chip interface speeds are not keeping pace. Developers find that a partitioned system's performance does not keep pace with its integrated counterpart, due to interface wait states added to compensate for lagging chip to chip communication rates. At some point, this performance degradation reaches intolerable levels and the partitioned prototype system is no longer a viable debug option. In the current era production devices must serve as the platform for application development.
Increasing CPU clock rates are also limiting availability of other simple visibility mechanisms. Since the CPU clock rates can exceed the maximum I/O state rates, visibility ports exporting information in native form can no longer keep up with the CPU. On-chip subsystems are also operated at clock rates that are slower than the CPU clock rate. This approach may be used to simplify system design and reduce power consumption. These developments mean simple visibility ports can no longer be counted on to deliver a clear view of CPU activity. As visibility and control diminish, the development tools used to develop the application become less productive. The tools also appear harder to use due to the increasing tool complexity required to maintain visibility and control. The visibility, control, and ease of use issues created by systems-on-a-chip tend to lengthen product development cycles.
Even as the integration trends present developers with a tough debug environment, they also present hope that new approaches to debug problems will emerge. The increased densities and clock rates that create development cycle time pressures also create opportunities to solve them. On-chip, debug facilities are more affordable than ever before. As high speed, high performance chips are increasingly dominated by very large memory structures, the system cost associated with the random logic accompanying the CPU and memory subsystems is dropping as a percentage of total system cost. The incremental cost of several thousand gates is at an all time low. Circuits of this size may in some cases be tucked into a corner of today's chip designs. The incremental cost per pin in today's high density packages has also dropped. This makes it easy to allocate more pins for debug. The combination of affordable gates and pins enables the deployment of new, on-chip emulation facilities needed to address the challenges created by systems-on-a-chip.
When production devices also serve as the application debug platform, they must provide sufficient debug capabilities to support time to market objectives. Since the debugging requirements vary with different applications, it is highly desirable to be able to adjust the on-chip debug facilities to balance time to market and cost needs. Since these on-chip capabilities affect the chip's recurring cost, the scalability of any solution is of primary importance. "Pay only for what you need" should be the guiding principle for on-chip tools deployment. In this new paradigm, the system architect may also specify the on-chip debug facilities along with the remainder of functionality, balancing chip cost constraints and the debug needs of the product development team.
FIG. 2 illustrates an emulator system 100 including four emulator components. These four components are: a debugger application program 110; a host computer 120; an emulation controller 130; and on-chip debug facilities 140. FIG. 2 illustrates the connections of these components. Host computer 120 is connected to an emulation controller 130 external to host 120. Emulation controller 130 is also connected to target system 140. The user preferably controls the target application on target system 140 through debugger application program 110.
Host computer 120 is generally a personal computer. Host computer 120 provides access the debug capabilities through emulator controller 130. Debugger application program 110 presents the debug capabilities in a user-friendly form via host computer 120. The debug resources are allocated by debug application program 110 on an as needed basis, relieving the user of this burden. Source level debug utilizes the debug resources, hiding their complexity from the user. Debugger application program 110 together with the on-chip trace and triggering facilities provide a means to select, record, and display chip activity of interest. Trace displays are automatically correlated to the source code that generated the trace log. The emulator provides both the debug control and trace recording function.
The debug facilities are preferably programmed using standard emulator debug accesses through a JTAG or similar serial debug interface. Since pins are at a premium, the preferred embodiment of the invention provides for the sharing of the debug pin pool by trace, trigger, and other debug functions with a small increment in silicon cost. Fixed pin formats may also be supported. When the pin sharing option is deployed, the debug pin utilization is determined at the beginning of each debug session before target system 140 is directed to run the application program. This maximizes the trace export bandwidth. Trace bandwidth is maximized by allocating the maximum number of pins to trace.
The debug capability and building blocks within a system may vary. Debugger application program 110 therefore establishes the configuration at runtime. This approach requires the hardware blocks to meet a set of constraints dealing with configuration and register organization. Other components provide a hardware search capability designed to locate the blocks and other peripherals in the system memory map. Debugger application program 110 uses a search facility to locate the resources. The address where the modules are located and a type ID uniquely identifies each block found. Once the IDs are found, a design database may be used to ascertain the exact configuration and all system inputs and outputs.
Host computer 120 generally includes at least 64 Mbytes of memory and is capable of running Windows 95, SR-2, Windows NT, or later versions of Windows. Host computer 120 must support one of the communications interfaces required by the emulator. These may include: Ethernet 10T and 100T; TCP/IP protocol; Universal Serial Bus (USB); Firewire IEEE 1394; and parallel port such as SPP, EPP and ECP.
Host computer 120 plays a major role in determining the real-time data exchange bandwidth. First, the host to emulator communication plays a major role in defining the maximum sustained real-time data exchange bandwidth because emulator controller 130 must empty its receive real-time data exchange buffers as fast as they are filled. Secondly, host computer 120 originating or receiving the real-time data exchange data must have sufficient processing capacity or disc bandwidth to sustain the preparation and transmission or processing and storing of the received real-time data exchange data. A state of the art personal computer with a Firewire communication channel (IEEE 1394) is preferred to obtain the highest real-time data exchange bandwidth. This bandwidth can be as much as ten times greater performance than other communication options.
Emulation controller 130 provides a bridge between host computer 120 and target system 140. Emulation controller 130 handles all debug information passed between debugger application program 110 running on host computer 120 and a target application executing on target system 140. A presently preferred minimum emulator configuration supports all of the following capabilities: real-time emulation; real-time data exchange; trace; and advanced analysis.
Emulation controller 130 preferably accesses real-time emulation capabilities such as execution control, memory, and register access via a 3, 4, or 5 bit scan based interface. Real-time data exchange capabilities can be accessed by scan or by using three higher bandwidth real-time data exchange formats that use direct target to emulator connections other than scan. The input and output triggers allow other system components to signal the chip with debug events and vice-versa. Bit I/O allows the emulator to stimulate or monitor system inputs and outputs. Bit I/O can be used to support factory test and other low bandwidth, non-time-critical emulator/target operations. Extended operating modes are used to specify device test and emulation operating modes. Emulator controller 130 is partitioned into communication and emulation sections. The communication section supports host communication links while the emulation section interfaces to the target, managing target debug functions and the device debug port. Emulation controller 130 communicates with host computer 120 using one of industry standard communication links outlined earlier herein. The host to emulator connection is established with off the shelf cabling technology. Host to emulator separation is governed by the standards applied to the interface used.
Emulation controller 130 communicates with the target system 140 through a target cable or cables. Debug, trace, triggers, and real-time data exchange capabilities share the target cable, and in some cases, the same device pins. More than one target cable may be required when the target system 140 deploys a trace width that cannot be accommodated in a single cable. All trace, real-time data exchange, and debug communication occurs over this link. Emulator controller 130 preferably allows for a target to emulator separation of at least two feet. This emulation technology is capable of test clock rates up to 50 MHZ and trace clock rates from 200 to 300 MHZ, or higher. Even though the emulator design uses techniques that should relax target system 140 constraints, signaling between emulator controller 130 and target system 140 at these rates requires design diligence. This emulation technology may impose restrictions on the placement of chip debug pins, board layout, and requires precise pin timings. On-chip pin macros are provided to assist in meeting timing constraints.
The on-chip debug facilities offer the developer a rich set of development capability in a two tiered, scalable approach. The first tier delivers functionality utilizing the real-time emulation capability built into a CPU's mega-modules. This real-time emulation capability has fixed functionality and is permanently part of the CPU while the high performance real-time data exchange, advanced analysis, and trace functions are added outside of the core in most cases. The capabilities are individually selected for addition to a chip. The addition of emulation peripherals to the system design creates the second tier functionality. A cost-effective library of emulation peripherals contains the building blocks to create systems and permits the construction of advanced analysis, high performance real-time data exchange, and trace capabilities. In the preferred embodiment five standard debug configurations are offered, although custom configurations are also supported. The specific configurations are covered later herein.

This patent is subject to a terminal disclaimer.

Recovery from corruption using event offset format in data trace


An inventive mapped memory interface product and process are provided. The inventive product carries out the steps of transmitting an information packet between a provider and a consumer processor; using the information packet to map a portion in a shared memory to which data will be transferred from a provider processor and from which the data will be extracted via a consumer processor; using the information packet to tell the consumer processor where the data is located; directing the local memory of both the provider processor and consumer processor to the portion mapped in the shared memory; transferring data from the provider processor to the mapped portion in the shared memory; and extracting the data from the mapped portion of the shared memory and transferring it in the local memory of the consumer computer.

(1) Field of the Invention
The present invention is directed toward data transfer in multi-processor systems, and more particularly, toward a process for significantly increasing the speed at which data may be throughput between processors via a shared memory.
(2) Description of the Prior Art
Multi-processing systems using a central location from which to store and retrieve data, as well as for sending data between processors comprising the system, are becoming increasingly more popular. Such systems allow for the use of a single memory or central storage area which can be accessed by a plurality of stations. Data work products and the like can be transferred between stations in the system without having to physically transfer floppy disks.
Frequently, a central data base or disk drive is used for storing the data of the individual stations. As the systems become increasingly large, the data stored at the central data base or disk drive also becomes increasingly large. At some point in the use of the system, the data base can be filled with so much data that processing data transfer between stations becomes significantly slowed. Data transfer between multi-processors while using a central disk drive has disadvantages. As is well known in computer technology, retrieving data from a disk drive is significantly slower than retrieving data directly from memory. Using a shared memory in place of a shared disk drive has a significant speed advantage over the same.
The downside to using a shared memory to store data is that space is significantly limited as compared to a disk drive. In order to use a central memory efficiently, it is best to remove data stored therein immediately. It is frequently the case, however that all the information stored in memory is not necessarily the information which is desired to be transmitted to a station of the multi-processor system. Therefore, it is beneficial to provide a means or process for communicating to a station of a multi-processor system from another station, exactly where the data desired for transfer is located in memory.
While the prior art discussed below discloses the use of a memory which may be shared by a plurality of stations comprising a multi-processor system, the transmission of data via the central memory in the systems discussed below is not facilitated by the efficient and inventive process disclosed herein, and thereby such data transfers are inherently significantly slower.
U.S. Pat. No. 4,212,057 to Devlin et al. discloses a shared memory multi/micro processor computer system. The system includes two or more substantially independent processors each having its own bus-type interconnection structure. A shared memory is accessible by any of the processors without interfering with the proper operation of another of the processors. Access to the shared memory is controlled such that a processor is connected to the shared memory only when one request is present. When more than one request is received from the processors, the last processor having received access is given priority to access the shared memory. While a shared memory is used in Devlin et al., there exists no means for improving the efficiency of removing data from the shared memory. That is, the Devlin et al. system fails to provide a means for quick access to the data being transferred, thereby decreasing the efficiency with which the system could perform.
U.S. Pat. No. 4,410,944 to Kronies discloses an apparatus and method for maintaining cache memory integrity in a shared memory environment. Kronies discloses a data processing system having a plurality of processors and a plurality of dedicated and shared memory stations. Each processor includes its own cache for speeding up data transfers between the processor and the shared memory. The integrity of the data in each individual cache, with respect to data written on similar addresses in the shared memory, is maintained by providing the shared memory with a cache monitoring and control system. The system monitors the read and write requests of the processors and in response, maintains an accurate and updatable record of the data addresses used in each individual cache for preventing the same addresses from being overridden, and thereby protecting the integrity of the data. High speed exchange of data from a first processor to a second processor is not disclosed in the Kronies patent. In fact, in Kronies, the data in the shared memory must be scanned before reading and writing requests can be fulfilled, thereby slowing the process by which data is transferred. For such applications, it would be beneficial to facilitate communication between processors prior to the transference of the data. As such, the possibility of threatening the integrity of the data stored could be prevented while increasing throughout instead of delaying it.
U.S. Pat. No. 4,975,833 to Jinzaki discloses a multi-processor system which only allows alternate access to shared memories upon the reception of read and write request signals. The system incorporates lock-out and access flags and a control circuit for controlling access to shared local memories of a group of processors. The lock-out flag inhibits reading from the memory of another processor while the other processor is writing into the memory. The access flag permits reading of the memory by the other processor and inhibits a related processor from writing into the memory while access is given. The Jinzaki system is directed towards sharing local memories and does not incorporate a central memory. The Jinzaki system includes a process for preventing access to data after storage, via communication between processors after storage, thereby slowing data throughput.
U.S. Pat. No. 4,803,618 to Ita et al., discloses a multi processor system having a common memory. The system includes a plurality of processors which use a common memory under a time division control plan. With this system, the common memory is protected from erasure of data stored therein via use of write permission flags given from a master processor. A control unit is operative to receive a write request flag from a processor as well as a write permission flag from the master processor. If both flags are generated simultaneously, the control unit provides a write enable signal for activating the common memory and allowing access thereto. An additional control unit is provided for staggering access to the common memory upon request from a plurality of processors. The Ita et al. system, therefore, provides a means for denying access to a central memory after data has been stored therein, which slows data throughput.
There exists a need in the multi-processor system art for a high speed data transfer process which allows a plurality of processors to prepare for acquiring access of data, prior to its transference to a central memory, so as to provide an efficient data transfer system.
The primary object of this invention is to provide a system and process for significantly increasing the efficiency of data transfer within multi-processor systems.
Another object of this invention is to provide a process and system for increasing the rate of data transfer between at least two computers of a multi-processor systems which can be implemented with currently available interfacing hardware.
Yet another object of this invention is to provide a high speed data transfer process for use between at least two computers of a multi-processor system using a shared memory.
The foregoing objects are attained by the inventive mapped memory interface process and computer program product of the present invention which process includes providing a provider computer and a consumer computer, each having a local memory and each linked to a shared memory; selecting data stored in the local memory of the provider computer for transfer from the local memory of the provider computer to the shared memory; mapping a portion of the shared memory having a known address for the storage of data; communicating the address of the mapped portion to the consumer computer prior to transferring the data; transferring the selected data from the local memory of the provider computer to the known address in the shared memory; and accessing the selected data in the shared memory at the particular address of the mapped portion of the shared memory; and extracting the selected data from the shared memory and transferring it into the local memory of the consumer computer.
The process also includes allocating a portion of the shared memory to the process in accordance with the amount of data to be transferred via a master processor; communicating to the provider processor that the consumer processor is ready to extract data from the shared memory; communicating to the consumer processor that the data has been transferred into the mapped portion; signaling to the provider processor that the data has been extracted; and updating the mapped portion with more data from the provider processor.
In one embodiment, the process of the present invention is carried out by a plurality of processors having the ability to map a set of addresses, for use with data desired to be transferred, into a shared memory location. This embodiment also includes an information packet being comprised of computer readable program code including process and data identifiers, the addresses and the size of the shared memory which is to be mapped. Accordingly, in this embodiment, at least two computers communicate along a bus-line, a packet of information regarding the address at which data will be stored in a shared memory prior to the storage of the same therein. The provider computer then transfers the data desired to be transmitted to the shared memory at the selected addresses. The consumer computer, informed of the addresses of the data prior to its transfer, can then extract the data from the shared memory into its local memory. Rapid data transfer between computers can be achieved without the bottle necking which occurs in systems which use lock-out flags or the like for preventing access to data in shared memory, which is being used by another processor.
The details of the present invention are set out in the following description and drawings wherein like reference characters depict like elements.

System and method for transmission of information packets between provider and consumer processors

The United States of America as represented by the Secretary of the Navy


The invention relates to a dye

The present invention is described in the German priority application No. 198 31 095.1, filed Jul. 10, 1998, which is hereby incorporated by reference as is fully disclosed herein.
The inkjet process constitutes a contactless printing process in which droplets of the recording liquid are guided from one or more nozzles onto the substrate that is to be printed. A recording liquid consists in principle of a soluble dye which is in solution in a solvent, usually water, or in a solvent mixture. In general, the solution additionally comprises further auxiliaries, such as surface-active substances, humectants and/or preservatives, for example. In order to obtain prints of high definition and resolution, recording liquids for the inkjet printing process must meet very stringent requirements in terms, in particular, of purity, freedom from particles, storage stability, viscosity, and surface tension. These and other requirements dictate that the dyes employed to prepare the recording liquids shall contain virtually no salts or diluents and must in particular possess high solubility.
In addition, very exacting requirements are made with regard to color strength, brightness, light fastness, water fastness and rub fastness. The inkjet process and the requirements made of the dyes and recording liquids are described, for example, in Ullmann""s Encyclopedia of Industrial Chemistry, 5th Edition, Vol.A 13 (1989), 588-594.
The development of water-soluble black dyes for the inkjet printing process that have the desired combination of high color strength, high light fastness and good water fastness has hitherto proved very difficult (see for example P. Gregory, High-Technology Applications of Organic Colorants, Plenum Press, New York (1991), p. 195).
High light fastness is of great importance in particular for inkjet applications in outdoor areas and in connection with the production of inkjet prints of photographic quality.
There is therefore a need for water-soluble dyes which are superior in light fastness to the known black dyes and at the same time have the other properties required for the inkjet sector.
Black stilbene dyes have already been described in various patents. These dyes, prepared originally for the dyeing and printing of textile fibers, are in the form of, in particular, sodium salts and as a result of their preparation conventionally include considerable amounts of salts such as, for example, sodium sulfate, sodium acetate and, in particular, sodium chloride.
In addition, diluents are added to these pulverulent dyes, examples of said diluents being sodium carbonate, alkali metal phosphates, urea, and aliphatic carboxylic acids.
Solid preparations of water-soluble stilbene dyes of the formula (A)
are described, for example, in EP-A-0 057 158 and in DE-A-3 247 605.
Salt-containing dyes of this kind are unsuitable for the preparation of recording liquids for the inkjet printing process because, in particular, corrosion occurs at the nozzles, but also because of the inadequate solubility of the dyes and poor storage stability of the printing inks, which are associated with an increase in viscosity, the deposition of dye, and the blockage of the nozzles. Furthermore, disadvantages arise in respect of the surface tension, so preventing optimum ink-drop formation for use in the inkjet printing process.
Dyes of the formula (A) have been employed for the inkjet printing process in an insoluble form bound to organic or inorganic particles (EP-A-0 656 406) and for printing textile fibers, especially polyamide fibers (EP-A-0 583 133).
The inks employed in accordance with EP-A-0 583 133 for printing textile fibers contain sodium hydroxide, in order to establish an alkaline pH, and are present predominantly as sodium salts.
Because of the poor solubility of the sodium salt of the stilbene dye of the formula (A), however, this dye is not suited to the preparation of printing inks for the inkjet printing process.
The object was therefore to provide black dyes for the inkjet printing process which do not have the disadvantages of the known dyes and yet meet the abovementioned requirements on color strength, brightness, light fastness and fastness to water and rubbing.
The present invention relates to water-soluble black stilbene dye salts and to their use for preparing recording liquids for the inkjet process.
The present invention provides black stilbene dyes of the formula (1)
in which
R1 is hydrogen, alkyl of 1 to 4 carbon atoms, or alkoxy of 1 to 4 carbon atoms;
R2 is hydrogen, carboxyl, chloro or nitro;
R21 is hydrogen; or R2 and R21 together form a benzene ring which is fused on in positions 3 and 4 of the ring A and can carry 1, 2 or 3 sulfo groups;
m is a number from 0 to 1;
n is a number from 1 to 2;
M+ is a cation or a mixture of different cations, at least one equivalent of the cations
M+ per mole of the dye being lithium cations and/or cations of the formula (II)
where p is a number from 1 to 30;
X is CH2CH2, CH(CH3)CH2, CH2CH(CH3) or a combination thereof and R3, R4 and R5 independently of one another are hydrogen, a group of the formula (III)
xe2x80x94(xe2x80x94Xxe2x80x94Oxe2x80x94)pHxe2x80x83xe2x80x83(III)
or an aliphatic radical of 1 to 18 carbon atoms.
Preference is given to dyes of the formula (I) in which M+ is lithium cations or cations of the formulae (II) in which p is a number from 1 to 15. Particularly preferred dyes of the formula (I) comprise mixtures of lithium cations and cations of the formula (II).
Preference is also given to dyes of the formula (I) in which the definition of R21 is hydrogen.
Preference extends to the dyes of the formula (I) in which R1 is hydrogen, methyl, ethyl, methoxy or ethoxy.
Particularly preferred dyes are those of the formula (IB)
in which R1, M and m are as defined above and R20 is hydrogen, sulfo, chloro, nitro or carboxyl.
The preparation of the stilbene dyes in the form of the sodium salts is known per se and is described, for example, in Houben-Weyl, Methoden der Organischen Chemie, Vol. X/3 (1965), pp. 339-343.
Accordingly, stilbene dyes are synthesized by alkaline condensation of 4,4xe2x80x2-dinitrostilbene-2,2xe2x80x2-disulfonic acid of the formula (IV)
with amino azo compounds in the form of their copper complexes of the formula (V)
Aternatively, formation of the copper complex can be carried out after the alkaline condensation.
Since the alkaline condensation of 4,4xe2x80x2-dinitrostilbene-2,2xe2x80x2-disulfonic acid with amino azo compounds in accordance with the methods stated is performed with sodium hydroxide, the dyes prepared in this way are in the form of sodium salts. The lithium or ammonium salts of stilbene dyes of the formula (I) according to the invention are prepared, for example, by adjusting the sodium salts of the corresponding stilbene dyes in an aqueous medium to a pH of between 0 and 3, preferably between 0 and 2, using an acid, separating off the resultant dye acids, washing them and then combining them in an aqueous medium with lithium hydroxide and/or with the lithium salt of a sufficiently weak acid and/or with an amine of the formula (VI) or with an ammonium hydroxide of the formula (VII)
R3R4N(xe2x80x94Xxe2x80x94Oxe2x80x94)pHxe2x80x83xe2x80x83(VI)xe2x80x83xe2x80x83
in which R3, R4, R5, X and p are as already defined above to form dye salts of the formula (I) according to the invention. Acids suitable for preparing the abovementioned dye acids are inorganic acids, such as hydrochloric acid, sulfuric acid, nitric acid or phosphoric acid, or organic acids, such as trichloroacetic acid, methanesulfonic acid, trifluoromethanesulfonic acid or polystyrenesulfonic acid. It is also possible to use a mixture of organic or inorganic acids.
Conversion of the sodium salts of dyes of the formula (I) to the corresponding dye acids is preferably done by introducing the sodium salt into the aqueous solution of the organic and/or inorganic acid and then stirring the resultant suspension at temperatures between 25 and 80xc2x0 C., preferably from 40 to 60xc2x0 C., for a certain time, such as from 0.5 to 4 hours. The dye acid is normally separated off by filtration but can also be isolated, for example, by centrifugation.
Once isolated, the dye acid is judiciously washed with dilute mineral acids and/or organic solvents, preferably methanol, ethanol, n-propanol, isopropanol or ethylene glycol dimethyl ether, in order to remove the majority of the electrolyte.
Examples of lithium compounds of organic or inorganic acids that are required to neutralize the dye acid are lithium hydroxide, lithium carbonate, lithium sulfite, lithium borate, trilithium phosphate, and lithium acetate.
The lithium cation is preferably introduced using lithium hydroxide or lithium carbonate. The dye acids can also be reacted with a mixture of lithium hydroxide and/or one or more lithium salts of sufficiently weak acids and/or one or more amines of the formula (VI) or ammonium hydroxides of the formula (VII).
Alternatively, dyes of the formula (I) can be prepared by using aqueous lithium hydroxide instead of sodium hydroxide for the alkaline condensation of the precursors of the formulae (IV) and (V), at a temperature of from 60 to 140xc2x0 C. and under pressure if desired. In this case, the lithium salts of the dyes of the formula (I) are formed directly.
Highly advantageous dye salts of the formula (I) according to the invention include both lithium cations and ammonium cations of the formula (II). These dye salts are obtained when the dye acids which form are reacted with a mixture of lithium cation donors and one or more amines of the formula (VI) or ammonium hyroxides of the formula (VII). The amines of the formula (VI) are known and/or commercial substances; p is preferably a number from 1 to 15.
Examples of suitable amines of the formula (VI) are ethanolamine, diethanolamine, triethanolamine, N-methyl-N-ethanolamine, N-methyl-N-diethanolamine, 2-(2-hydroxyethoxy)ethana mine, di(2-(2-hyd roxyethoxy)ethan )a mine, tri(2-(2-hydroxyethoxy)ethan)amine, ethoxylated and propoxylated ammonia, primary, secondary and tertiary aliphatic amines having 1 or 2 C1-C18-alkyl radicals and 2 or 1 (poly)oxy(C2-C3)-alkylene chains having from 1 to 30, preferably from 1 to 25, hydroxyethyl and/or hydroxypropyl units in the chain. Ethoxylated fatty amines are available commercially under various names, for example, as (copyright)Genamins from Clariant. They usually comprise ethoxylated coconut fatty amine, sperm oil fatty amine, stearylamine and tallow fatty amine having degrees of ethoxylation of generally from 2 to 25. These products are industrial mixtures corresponding to the composition of the fatty acids used to prepare the fatty amines.
It can be judicious to employ a mixture of ethanolamine and/or diethanolamine and/or triethanolamine and a commercial ethoxylated fatty amine with degrees of ethoxylation of from 2 to 25.
In the reaction of the dye acids with lithium compounds and/or with an amine of the formula (VI) or with an ammonium hydroxide of the formula (VII) it is preferred to choose an amount which in the aqueous medium is required for the establishment of a pH of from 7 to 10, preferably of from 8 to 9.
Alternatively, the sodium salts of black stilbene dyes in preferably aqueous solution can be converted, using ammonium salts of lipophilic amines, examples being tri-n-butylamine, tri-n-pentylamine, tri-n-hexylamine and tri(2-ethylhexyl)amine, into the corresponding water-insoluble or sparingly water-soluble ammonium salts of stilbene dyes of the formula (I), which can subsequently be separated off and washed free of salt. Subsequent reaction with preferably lithium hydroxide in aqueous solution then makes it possible to form the low-salt, readily soluble lithium salts of the black stilbene dyes employed and to recover the lipophilic amines.
The stilbene dye salts of the formula (I) according to the invention can be isolated from the preferably aqueous reaction mixtures obtained initially by means of customary methods of working up: for example, by salting out, filtration or spray drying, directly or following demineralization by means of membrane filtration. Alternatively, isolation can be dispensed with and a solution comprising the dye salt of the formula (I) according to the invention can be converted directly into concentrated dye solutions or recording liquids by adding organic bases, organic solvents and/or hydrotropic substances.
Examples of suitable organic bases are monoethanolamine, diethanolamine, triethanolamine, 2-aminopropanol, 3-aminopropanol, dipropanolamine, tripropanolamine, N-methylaminoethanol, N,N-dimethylaminoethanol, N-phenylaminopropanol, ethylenediamine, tetramethylethylenediamine, tetramethylpropylenediamine, tetramethylhexylenediamine, diethylenetriamine, triethylenetetramine or polyethylenimine.
Examples of organic solvents and hydrotropic compounds which can be employed are formamide, urea, tetramethylurea, xe2x96xa1-caprolactam, ethylene glycol, diethylene glycol, triethylene glycol, polyethylene glycol, butyl glycol, methyl-Cellosolve, glycerol, N-methylpyrrolidone, 1,3-diethyl-2-imidazolidinone, thiodiglycol, sodium xylenesulfonate, sodium cumenesulfonate or sodium butyl monoglycol sulfate. Hydrotropic compounds are described, for example, in Melliand 43, 718 (1962), Angew. Chem. 63, 327 (1951).
The stilbene dyes of the invention are also suitable for the dyeing and printing of cotton, polyamide, paper or leather or as colorants in electrophotographic toners and developers, such as one-component and two-component powder toners, magnetic toners, liquid toners, polymerization toners, and also other specialty toners, and in powder coating materials.
The dye salts of the invention are also suitable as colorants for color filters and also for both additive and subtractive color generation (see for example P. Gregory, xe2x80x9cTopics in Applied Chemistry: High-Technology Applications of Organic Colorantsxe2x80x9d, Plenum Press, New York, 1991, pp. 15-25).
In particular, the dyes of the formula (I) of the invention are suitable for the preparation of recording liquids for the inkjet printing process and also for preparing inks for other printing, copying, marking, writing, drawing, stamping or registering processes.
In this context, black printed images of excellent quality are obtained which are notable for high brightness, print definition and optical density and also for excellent light fastness, abrasion resistance and water fastness, even on standard, uncoated paper stocks.
The present invention additionally provides recording liquids which comprise one or more of the water-soluble stilbene dyes of the formula (I).
The finished recording liquids generally comprise in total from 0.5 to 15% by weight, preferably from 1.5 to 8% by weight (calculated on a dry basis), of one or more, for example, 2 or 3, soluble dyes of the formula (I). Judiciously, from 5 to 99% by weight of water and from 0.5 to 94.5% by weight of organic solvent and/or hydrotropic compounds are present.
In one preferred embodiment, ready-to-use recording liquids comprise from 0.5 to 15% by weight of dye of the formula (I), from 40 to 85% by weight of water and from 10 to 50% by weight of organic solvent and/or hydrotropic compounds; in another embodiment, from 0.5 to 15% by weight of dye of the formula (I), from 5 to 20% by weight of water and from 70 to 94.5% by weight of organic solvent and/or hydrotropic compounds. The recording liquids may also include further additives, which are mentioned below.
Water used to prepare the recording liquids is preferably employed in the form of distilled or deionized water. The solvents present in the recording liquids may comprise an organic solvent or a mixture of such solvents, with preference being given to water-miscible solvents. Examples of suitable solvents are mono- or polyhydric alcohols, their ethers and esters, examples being alkanols, especially of 1 to 4 carbon atoms, such as methanol, ethanol, propanol, isopropanol, butanol and isobutanol; dihydric or trihydric alcohols, especially of 2 to 6 carbon atoms, examples being ethylene glycol, propylene glycol, 1,3-propanediol, 1,4-butanediol, 1,5-pentanediol, 1,6-hexanediol, 1,2,6-hexanetriol, glycerol, diethylene glycol, dipropylene glycol, triethylene glycol, polyethylene glycol, tripropylene glycol and polypropylene glycol; lower alkyl ethers of polyhydric alcohols, such as ethylene glycol monomethyl, monoethyl or monobutyl ether, triethylene glycol monomethyl or monoeethyl ether; ketones and ketone alcohols, such as acetone, methyl ethyl ketone, diethyl ketone, methyl isobutyl ketone, methyl pentyl ketone, cyclopentanone, cyclohexanone and diacetone alcohol; amides, such as dimethylformamide, dimethylacetamide and n-methylpyrrolidone; and also tetramethylurea, or thiodiglycol.
In addition, the recording liquids of the invention may comprise customary additives, examples being preservatives, cationic, anionic or nonionic surface-active substances (surfactants and wetting agents), and also viscosity regulators, for example, polyvinyl alcohol, cellulose derivatives, or water-soluble natural or synthetic resins as film formers and/or binders for enhancing the adhesive strength and abrasion resistance.
Amines, such as ethanolamine, diethanolamine, triethanolamine, N,N-dimethylethanolamine or diisopropylamine, for example, serve primarily to increase the pH of the recording liquid. They are normally present in proportions of from 0 to 10% by weight, preferably from 0.5 to 5% by weight, in the recording liquid.
Depending on the embodiment of the printing process as, for example, a continuous jet, intermittent jet, impulse jet or compound jet process, further additives may be added to the recording liquids for the inkjet printing process, in order, for example, to buffer the pH or to adjust the electrical conductivity, specific heat, thermoexpansion coefficient and thermal conductivity.
The storage of recording liquids of the invention is not accompanied by the deposition of precipitates leading to poorly defined printed images or nozzle blockage.
In terms of viscosity and surface tension, the recording liquids of the invention are within the ranges suitable for the inkjet process. They give printed images of high optical density with excellent light fastness, water fastness, abrasion resistance and resolution.

Water-soluble stilbene dyes, their preparation and use

Abstract: The invention relates to a dye

Abstract: in which

Abstract: where p is a number from 1 to 30;

Abstract: Dyes of the formula (I) are particularly suitable as colorants in inkjet inks.


An encode/decode 5-2-5 matrix system is combined with a discrete digital, multi-channel audio system to expand the number of independently addressable output channels. One embodiment of the system provides additional output channels by matrix encoding the additional audio information into the rear surround channels of a discrete digital five channel surround system. The expanded channels provide additional center surround and left and right overhead outputs. The 5-2-5 matrix channel separation is improved by increasing the surround channel attenuation when no dominant surround signal is present in the input to the 5-2-5 matrix decoder. In a second embodiment the system provides a surround encode/decode system offering eleven independently addressable output channels.

1. Field of the Invention
The present invention generally relates to multi-channel audio surround systems and more specifically relates to discrete multi-channel audio systems combined with multi-channel matrix surround systems.
2. Description of the Related Art
Matrix surround systems have been commonly known and used for approximately thirty years. The work of Peter Scheiber in the late sixty""s and early seventy""s is perhaps the most well known. The basic concept of a matrix system is to expand the number of audio channels available from a two channel stereo recording, or transmission media. Anyone skilled in the art is knowledgeable of the fact that the commonly known xe2x80x9cDolby Stereoxe2x80x9d cinema systems as well as the xe2x80x9cDolby Pro Logicxe2x80x9d consumer systems are based on the original patents issued to Peter Schieber. The Dolby system is referred to as a 4-2-4 matrix system. The obvious requirement of all matrix systems is that a discrete two channel recording or transmission media (Left and Right channels) must be available to allow additional channels to be added as a L+R and or Lxe2x88x92R signal. It is also obvious to the skilled artisan that any existing stereo, or pair of two or more discrete channels of audio, can be enhanced with the use of any of the existing matrix systems. This would include stereo recordings, FM stereo broadcast, cable TV transmission, internet audio and DVD audio to name a few of the countless possible applications. It also becomes obvious to anyone skilled in the art to consider the application of matrix enhancement to any of the discrete multi-channel audio formats such as Dolby Digital (AC-3), DTS (Digital Theater Systems), or the Sony format known as SDDS. The most obvious application would be to enhance the stereo rear or xe2x80x9csurroundxe2x80x9d channels by applying a 4-2-4 matrix system. Anyone skilled in the art quickly realizes that with any of the above mentioned discrete multi-channel systems, any one of the known matrix decoders including Dolby Pro-Logic, can be connected to the left and right surround outputs. The obvious result is that any dominate audio originally mixed equally in both of the surround channels would produce a center surround output from the center output of the Dolby Pro-Logic decoder.
It is also obvious to one skilled in the art that by using the Left and Right front outputs from the matrix decoder for the left and right surround outputs, center surround audio will be subtracted from the left and right output. This would provide the user with a six channel system having a potential benefit for all of the currently available releases in any of the above mentioned discrete multi-channel formats. The above described system can easily be realized, by any consumer, by connecting one of the currently available consumer xe2x80x9cDigital Systemsxe2x80x9d, Dolby Digital or DTS, with one of the available consumer matrix systems. There are several matrix decoding systems that could be used, as is obvious to those skilled in the art. The Dolby Pro-Logic system is used as an example of the most commonly available system. The combined system described above has already been realized in numerous professional cinema application and will illustrate an example of the prior art. A number of professional cinemas have connected one of the commercially available professional discrete digital systems with one of the commercially available professional matrix decoders. The combined system was connected to provide the cinema system with a center surround channel. As previously mentioned a center surround signal is naturally present in virtually all of the current source material. This demonstrates the obviousness of the simple combination of the two systems. Other prior art matrix systems have offered six output channels, which included a center surround output. One prior art system is disclosed in U.S. Pat. No. 4,589,129 and also in U.S. Pat. No. 4,680,796 both issued to David E. Blackmer and James H. Townsend. Still another example of a matrix system offering a center surround output is disclosed in U.S. Pat. No. 5,172,415 issued to James W. Fosgate.
These prior art examples did not produce the level of separation that is obtained from the present invention, and in the Blackmer system there was no steering in the surround channels, which is required to enhance channel separation. The Blackmer system simply produced a pseudo stereo output for the left and right surround outputs, and an unaltered center surround output. The above examples illustrate the ongoing desire to increase the number of output channels in a surround system in order to improve localization and increase realism.
A relatively new matrix system, which has become commercially available in the past few years is a system called Circle Surround. The Circle Surround system is a 5-2-5 matrix system allowing five channels to be encoded down to two and then decoded back to five channels. The Circle Surround 5-2-5 matrix system is disclosed in U.S. Pat. No. 5,771,295 issued to James K. Waller Jr. The benefits of the 5-2-5 system over that of the Dolby Pro-Logic 4-2-4 matrix are clearly disclosed in the Waller patent. The advantages of combining the Circle Surround 5-2-5 matrix system with a discrete multi-channel audio system will become apparent after reading the disclosure of the current invention. In summary, the prior art systems lack the ability to provide more than one additional center surround channel and did not anticipate additional side or overhead channels. The prior art systems provided the additional center channel as an L+R signal that was naturally present as the summation of the two original channels. The prior art systems also did not anticipate the possibility of stereo encoded Lxe2x88x92R channels, or symmetrically encoded channels.
The present invention discloses an improved, expanded, combined discrete multi-channel/5-2-5 matrix system and the benefits of said system. It is an object of the current invention to offer additional channel enhancement to that available with the prior art systems by enhancing a multi-channel discrete system with 5-2-5 matrix encoded audio, mixed into at least two of the available discrete audio channels. It is a further object of the invention to offer the possibility of symmetrical channel enhancement. By encoding 5-2-5 matrix audio into any two of the five channels available, with Dolby Digital and DTS (Digital Theater Systems), or seven channels available with the Sony SDDS system, and then decoding with a Circle Surround decoder, the benefits of the invention are realized. As previously mentioned, the invention can also be used with the multi-channel discrete DVD audio format, which offers multiple discrete channels of audio. It is a further object of the invention to allow adjacent and or diagonal discrete channels to be used for additional matrix encoded channels. It is yet a further object of the invention to provide additional channel separation over that of the current Circle Surround system. The requirements of the stand alone system differ from that of the disclosed invention, and further improvements in performance are derived by providing surround channel attenuation when there is no dominate Lxe2x88x92R signal present. This will be further explained in the detailed description of the invention.
In the first embodiment of the invention a 5-2-5 matrix system is added to the surround channels of a discrete digital surround system providing an additional center surround channel and a pair of additional Lxe2x88x92R channels. The additional Lxe2x88x92R channels can be used for either overhead or side channels.
In a second embodiment of the present invention a multi-channel system is disclosed that offers symmetrical side and overhead channels to be added as L+R and Lxe2x88x92R channels.
In a third embodiment of the present invention a multi-channel system is disclosed that combines both of the first two embodiments with additional channels provided by encoding L+R signals and or Lxe2x88x92R signals in the front two audio channels.
The third embodiment provides for a total of up to fourteen available and independently addressable channels. As previously stated further improvements in the system performance are also achieved by reducing the gain in the surround channels of the 5-2-5 decoder when there is no dominate Lxe2x88x92R information present in the input audio.

Discrete multi-channel/5-2-5 matrix system


An optical switching apparatus includes an optical switch having a plurality of input ports and output ports, optical amplifiers, monitor circuits, optical amplifiers monitor circuits, and a controller that controls the optical switch. The optical amplifiers are connected to the input ports of the optical switch. The monitor circuits are connected to the output ports of the optical switch. The controller selects one of the plurality of the monitor circuits based on predetermined rules to obtains the loss at the output ports and/or the differential loss between the channels of the optical switch. The controller further selects one of the optical amplifiers based on the configuration of the optical switch to compensate the loss and the differential loss among the different channels of the optical switch by pre-amplifying the optical signals before they reach the input ports of the optical switch.

1. Field of the Invention
The present invention relates to an optical communication device and methods of using this device. In particular, the present invention relates to an optical switching apparatus suitable for switching and outputting optical signals received from a plurality of optical transmission lines to other optical transmission lines, and methods for using this apparatus.
2. Prior Art of the Invention
To handle the sudden increase in data traffic through the Internet, etc. and the quickly growing demands for multimedia communication of images, sound and data, much progress has been made to increase the speed and the capacity of the transmission lines and telecommunication network nodes. To achieve a higher transmission speed, optical communication devices and optical fiber transmission lines are generally used to transmit signals between telecommunication network nodes.
In recent years, to handle the ever increasing speed of communication networks and to improve the capacity of communication devices, these communication networks and devices, use optical switching apparatuses such as optical cross-connects (hereafter, referred to as OXC) and optical add-drop multiplexing apparatuses (hereafter, referred to as OADM), which implement switching processes such as switching of transmission lines and switching of circuits without converting optical signals to electric signals before processing the signals as in the conventional communication devices.
The OXC or OADM typically includes optical switches as its main components. At present, since a single stage high-capacity optical switch is not commercially available, a high-capacity optical switch is usually implemented through a multi-stage combination of the commercially available low-capacity optical switches such as 2×2 or 8×8 switches. The optical signal power loss and differential loss among the channels of a commercial low-capacity optical switch might reach from several dB to more than ten dB. These losses between the channels night-be even larger for a high-capacity switch including a multi-stage combination of the commercially available low-capacity optical switches. Typically, an optical communication system includes optical transmitters and optical receivers before and after optical switches. Since these optical transmitters and receivers have limited optical transmission output powers, sensitivities and dynamic ranges, compensation is generally required for the optical switch loss and differential loss between the channels.
Several methods have been proposed to solve this problem. In "A Frequency Multiplexed Routing and Selecting Hybrid Switch," Denshi Joho Tsushin Gakkai [Electronic Information and Communication Association]/Tsushin Society Taikai [Communication Society Conference (1999)]/B-12-17 (Reference A), a method is disclosed to compensate for the losses by placing optical amplifiers in the middle and/or at the output of the multi-stage optical switches. In "Power Control in ADM Node Using High-speed Compact-size Optical Spectrum Monitor," Denshi Joho Tsushin Gakkai [Electronic Information and Communication Association]/Tsushin Society Taikai [Communication Society Conference (1997)]/B-10-101 (Reference B), it is disclosed that a wavelength-division-multiplexed (WDM) optical signal is first wavelength-demultiplexed by an OADM into an optical signal with multiple wavelengths, and that after controlling the optical amplitude for each of the wavelengths using variable optical attenuators, the signals are again wavelength-division-multiplexed. In this method, the amplitude for each wavelength is controlled based on the results of multiplex signal spectrum monitors after wavelength-division-multiplexing.
Kokai Patent Journal No. HEI 11 [1999]-32010 (Reference C) to the inventor of the present application discloses an OXC containing several optical switches and a few optical amplifiers between the optical switches, wherein the optical signal amplitude is controlled using a configuration wherein the amplification of optical signals is adjusted with the optical amplifiers, which is in turn controlled by the amplitude of the output optical signals.
At present, a high-capacity optical switch is usually realized by combining commercially available low-capacity optical switches in multi-stages. Therefore, it is necessary to appropriately calibrate and install an optical transmission line from the output port of an optical switch at one stage to the input port of another optical switch at the next stage. Thus, maintenance is often required for those transmission lines between the stages, and the optical transmission is interrupted during the maintenance. Further, the interruption may also occur when the high-capacity optical switch is under the normal operation.
A high-capacity switching apparatus, in which optical amplifiers are placed inside or after optical switches, such as the ones disclosed in References A and C, often causes sensitivity degradation of the optical parts on the reception side due to light surges caused by the above described interruption of light. Thus, the configuration disclosed in Reference A or C requires a surge-preventing function in the switching controlling unit of the optical switches and/or the controlling unit of the optical amplifiers. Otherwise, the disclosed high capacity switching apparatus needs to use high performance optical parts such as ones with a wide dynamic range. In addition, to compensate for the optical signals which suffer the power loss in the optical switches, the high-capacity switching apparatus includes optical amplifiers placed after the optical switches. Since the spontaneous emission noise of the optical amplifiers is added to the optical signals with a lowered power, the signal-to-noise ratio of the optical signal may decrease and cause errors in the receiver.
Furthermore, the optical signal received by the input port of an optical switch may take various inner paths before reaching the output port, and the optical switch in each stage is appropriately selected and configured. That is, because the characteristics such as the amplitude loss or the differential loss between the channels of each of the switches in the multi-stage combination is different, the loss between the channels of the optical switches between the input port and the output port will significantly vary depending on the actual configuration of optical switches in the multi-stage combination. Therefore, to offer a high performance large-capacity optical switch, it is desirable to realize compensation for the optical switch loss and the differential loss between channels that have occurred in the chosen optical path for each input/output port. The optical switching apparatuses as disclosed in Reference A or C, however, do not offer the above desired function.
Meanwhile, the OADM as disclosed in Reference B adopts a configuration wherein the spectra of wavelength-division-multiplexed optical signals are monitored and the loss is compensated for each demultiplexed wavelength in the OADM. In this configuration, since the wavelength of each signal to be compensated must be different from one another, the wavelengths and the multiplexing methods of the optical signals used as optical switching apparatuses will be limited. In addition, it is still not compatible with either an optical switch with a flexible configuration wherein the wavelengths monitored by the monitor units correspond to the wavelengths processed by the loss compensation units in a one-to-one fashion. It is desired various connections should be adopted with switching. Alternatively, an optical switch should have a flexible configuration with no restrictions in the wavelength of the optical signals in the multiplexing methods.

Optical switching apparatus and optical switching method


A light duty liquid detergent with desirable cleansing properties to the human skin and dishes comprising a C8-18 ethoxylated alkyl ether sulfate anionic surfactant, a sulfonate anionic surfactant, an alkyl polyglucoside surfactant, an amine oxide, silicone polymer and water.

This invention relates to a light duty liquid cleaning composition which is mild to the skin and which demonstrates improved sensory attributes and foam when used as a hand soap designed in particular for dishware and which is effective in grease and is high foaming and clear.
The present invention relates to light duty liquid detergent compositions with high foaming properties, which contains mixtures of anionic surfactants, amine oxide surfactant, alkyl polyglucoside surfactant and an oxyethylene functional organosilane.
The prior art is replete with light duty liquid detergent compositions containing nonionic surfactants in combination with anionic and/or betaine surfactants wherein the nonionic detergent is not the major active surfactant, as shown in U.S. Pat. No. 3,658,985 wherein an anionic based shampoo contains a minor amount of a fatty acid alkanolamide. U.S. Pat. No. 3,769,398 discloses a betaine-based shampoo containing minor amounts of nonionic surfactants. This patent states that the low foaming properties of nonionic detergents renders its use in shampoo compositions non-preferred. U.S. Pat. No. 4,329,335 also discloses a shampoo containing a betaine surfactant as the major ingredient and minor amounts of a nonionic surfactant and of a fatty acid mono- or di-ethanolamide. U.S. Pat. No. 4,259,204 discloses a shampoo comprising 0.8-20% by weight of an anionic phosphoric acid ester and one additional surfactant which may be either anionic, amphoteric, or nonionic. U.S. Pat. No. 4,329,334 discloses an anionic-amphoteric based shampoo containing a major amount of anionic surfactant and lesser amounts of a betaine and nonionic surfactants.
U.S. Pat. No. 3,935,129 discloses a liquid cleaning composition based on the alkali metal silicate content and containing five basic ingredients, namely, urea, glycerin, triethanolamine, an anionic detergent and a nonionic detergent. The silicate content determines the amount of anionic and/or nonionic detergent in the liquid cleaning composition. However, the foaming property of these detergent compositions is not discussed therein.
U.S. Pat. No. 4,129,515 discloses a heavy duty liquid detergent for laundering fabrics comprising a mixture of substantially equal amounts of anionic and nonionic surfactants, alkanolamines and magnesium salts, and, optionally, zwitterionic surfactants as suds modifiers.
U.S. Pat. No. 4,224,195 discloses an aqueous detergent composition for laundering socks or stockings comprising a specific group of nonionic detergents, namely, an ethylene oxide of a secondary alcohol, a specific group of anionic detergents, namely, a sulfuric ester salt of an ethylene oxide adduct of a secondary alcohol, and an amphoteric surfactant which may be a betaine, wherein either the anionic or nonionic surfactant may be the major ingredient.
U.S. Pat. Nos. 5,326,557 and 5,435,996 disclose oxyethylene functional organic silanes for use in body care formulations.
It has now been found that a light duty liquid detergent can be formulated with a mixture of anionic surfactants, alkyl polyglucoside,alkyl monoalkanol amide, surfactant, silicone polymer and water which has desirable cleaning properties, mildness to the skin and improved foam qualities.
An object of this invention is to provide a light duty liquid detergent composition which comprises a sulfate surfactant, a sulfonate anionic surfactant, alkyl monoalkanol amide, an alkyl polyglucoside surfactant, an oxyethylene functional organosilane, solubilizing system and water wherein the composition does not contain any polymeric thickeners, stearyl alcohol, mineral oil, sorbitol, triethanol amine, N-alkyl aldonamide, zwitterionic surfactant, silicas, abrasives, alkali metal carbonates, alkaline earth metal carbonates, alkyl glycine surfactant or a cyclic imidinium surfactant.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The light duty liquid compositions of the instant invention comprises approximately by weight:
(a) 2% to 12%, more preferably 3% to 10% of an alkali metal or ammonium salt of a C8-18 ethoxylated alkyl ether sulfate and/or an C8-18 alkyl ether sulfate;
(b) 20% to 36%, more preferably 22% to 34% of an alkali metal or alkaline earth metal salt of an anionic sulfonate surfactant;
(c) 0.5% to 10%, more preferably 1.0% to 8% of an alkyl polyglucoside surfactant;
(d) 0.5% to 6% of a sodium xylene sulfonate and/or sodium cumene sulfonate;
(e) 1% to 12% of an amine oxide surfactant;
(f) 0.1% to 6%, more preferably 1% to 5% of a silicone polymer which functions as a mildness and foam enhancing agent;
(g) 0 to 4%, more preferably 0.5% to 3% of an inorganic magnesium salt;
(h) 0 to 6%, more preferably 0.25% to 4% of a C1-C4 alkanol; and
(i) the balance being water.
The instant compositions do not contain an N-alkyl aldonamide, choline chloride or buffering system which is a nitrogenous buffer which is ammonium or alkaline earth carbonate, guanidine derivates, alkoxylalkyl amines, alkyleneamines, C3-C7 alkyl and alkenyl monobasic and dibasic acids such as C4-C7 aliphatic carboxylic diacids which do not contain a hydroxy group, phosphoric acid, amino alkylene phosphonic acid and the composition is pourable and is not a gel and the composition has a complex viscosity at 1 rads-1 of less than 0.4 Pascal seconds.
The anionic sulfonate surfactants which may be used in the instant composition of this invention are water soluble and include the magnesium sodium, potassium, ammonium and ethanolammonium salts of linear C8-C16 alkyl benzene sulfonates; C10-C20 paraffin sulfonates, alpha olefin sulfonates containing about 10-24 carbon atoms and C8-C18 alkyl sulfates and mixtures thereof. The preferred anionic sulfonate surfactant is a C12-18 paraffin sulfonate.
The paraffin sulfonates may be monosulfonates or di-sulfonates and usually are mixtures thereof, obtained by sulfonating paraffins of 10 to 20 carbon atoms. Preferred paraffin sulfonates are those of C12-18 carbon atoms chains, and more preferably they are of C14-17 chains. Paraffin sulfonates that have the sulfonate group(s) distributed along the paraffin chain are described in U.S. Pat. Nos. 2,503,280; 2,507,088; 3,260,744; and 3,372,188; and also in German Patent 735,096. Such compounds may be made to specifications and desirably the content of paraffin sulfonates outside the C14-17 range will be minor and will be minimized, as will be any contents of di- or poly-sulfonates.
Examples of suitable other sulfonated anionic detergents are the well known higher alkyl mononuclear aromatic sulfonates, such as the higher alkylbenzene sulfonates containing 9 to 18 or preferably 9 to 16 carbon atoms in the higher alkyl group in a straight or branched chain, or C8-15 alkyl toluene sulfonates. A preferred alkylbenzene sulfonate is a linear alkylbenzene sulfonate having a higher content of 3-phenyl (or higher) isomers and a correspondingly lower content (well below 50%) of 2-phenyl (or lower) isomers, such as those sulfonates wherein the benzene ring is attached mostly at the 3 or higher (for example 4, 5, 6 or 7) position of the alkyl group and the content of the isomers in which the benzene ring is attached in the 2 or 1 position is correspondingly low. Preferred materials are set forth in U.S. Pat. No. 3,320,174, especially those in which the alkyls are of 10 to 13 carbon atoms.
The C8-18 ethoxylated alkyl ether sulfate surfactants have the structure
R-(OCHCH2)nOSO3xe2x88x92M+
wherein n is about 1 to about 22 more preferably 1 to 3 and R is an alkyl group having about 8 to about 18 carbon atoms, more preferably 12 to 15 and natural cuts, for example, C12-14 or C12-16 and M is an ammonium cation or a metal cation, most preferably sodium.
The ethoxylated alkyl ether sulfate may be made by sulfating the condensation product of ethylene oxide and C8-10 alkanol, and neutralizing the resultant product. The ethoxylated alkyl ether sulfates differ from one another in the number of carbon atoms in the alcohols and in the number of moles of ethylene oxide reacted with one mole of such alcohol. Preferred ethoxylated alkyl ether polyethenoxy sulfates contain 12 to 15 carbon atoms in the alcohols and in the alkyl groups thereof, e.g., sodium myristyl (3 EO) sulfate.
Ethoxylated C8-18 alkylphenyl ether sulfates containing from 2 to 6 moles of ethylene oxide in the molecule are also suitable for use in the invention compositions. These detergents can be prepared by reacting an alkyl phenol with 2 to 6 moles of ethylene oxide and sulfating and neutralizing the resultant ethoxylated alkylphenol.
The amine oxide semi-polar nonionic surfactants used in the instant compositions comprise compounds and mixtures of compounds having the formula
wherein R1 is an alkyl, 2-hydroxyalkyl, 3-hydroxyalkyl, or 3-alkoxy-2-hydroxypropyl radical in which the alkyl and alkoxy, respectively, contain from 8 to 18 carbon atoms, R2 and R3 are each methyl, ethyl, propyl, isopropyl, 2-hydroxyethyl, 2-hydroxypropyl, or 3-hydroxypropyl, and n is from 0 to 10. Particularly preferred are amine oxides of the formula:
wherein R1 is a C12-16 alkyl and R2 and R3 are methyl or ethyl. The above ethylene oxide condensates, amides, and amine oxides are more fully described in U.S. Pat. No. 4,316,824 which is hereby incorporated herein by reference.
The alkyl polysaccharides surfactants, which are used in conjunction with the aforementioned surfactant have a hydrophobic group containing from about 8 to about 20 carbon atoms, preferably from about 10 to about 16 carbon atoms, most preferably from about 12 to about 14 carbon atoms, and polysaccharide hydrophilic group containing from about 1.5 to about 10, preferably from about 1.5 to about 4, most preferably from about 1.6 to about 2.7 saccharide units (e.g., galactoside, glucoside, fructoside, glucosyl, fructosyl; and/or galactosyl units). Mixtures of saccharide moieties may be used in the alkyl polysaccharide surfactants. The number x indicates the number of saccharide units in a particular alkyl polysaccharide surfactant. For a particular alkyl polysaccharide molecule x can only assume integral values. In any physical sample of alkyl polysaccharide surfactants there will be in general molecules having different x values. The physical sample can be characterized by the average value of x and this average value can assume non-integral values. In this specification the values of x are to be understood to be average values. The hydrophobic group (R) can be attached at the 2-, 3-, or 4- positions rather than at the 1-position, (thus giving e.g. a glucosyl or galactosyl as opposed to a glucoside or galactoside). However, attachment through the 1- position, i.e., glucosides, galactoside, fructosides, etc., is preferred. In the preferred product the additional saccharide units are predominately attached to the previous saccharide unit""s 2-position. Attachment through the 3-, 4-, and 6- positions can also occur. Optionally and less desirably there can be a polyalkoxide chain joining the hydrophobic moiety (R) and the polysaccharide chain. The preferred alkoxide moiety is ethoxide.
Typical hydrophobic groups include alkyl groups, either saturated or unsaturated, branched or unbranched containing from about 8 to about 20, preferably from about 10 to about 18 carbon atoms. Preferably, the alkyl group is a straight chain saturated alkyl group. The alkyl group can contain up to 3 hydroxy groups and/or the polyalkoxide chain can contain up to about 30, preferably less than about 10, alkoxide moieties.
Suitable alkyl polysaccharides are decyl, dodecyl, tetradecyl, pentadecyl, hexadecyl, and octadecyl, di-, tri-, tetra-, penta-, and hexaglucosides, galactosides, lactosides, fructosides, fructosyls, lactosyls, glucosyls and/or galactosyls and mixtures thereof.
The alkyl monosaccharides are relatively less soluble in water than the higher alkyl polysaccharides. When used in admixture with alkyl polysaccharides, the alkyl monosaccharides are solubilized to some extent. The use of alkyl monosaccharides in admixture with alkyl polysaccharides is a preferred mode of carrying out the invention. Suitable mixtures include coconut alkyl, di-, tri-, tetra-, and pentaglucosides and tallow alkyl tetra-, penta-, and hexaglucosides.
The preferred alkyl polysaccharides are alkyl polyglucosides having the formula
R2O(CnH2nO)r(Z)x
wherein Z is derived from glucose, R is a hydrophobic group selected from the group consisting of alkyl, alkylphenyl, hydroxyalkylphenyl, and mixtures thereof in which said alkyl groups contain from about 10 to about 18, preferably from about 12 to about 14 carbon atoms; n is 2 or 3 preferably 2, r is from 0 to 10, preferable 0; and x is from 1.5 to 8, preferably from 1.5 to 4, most preferably from 1.6 to 2.7. To prepare these compounds a long chain alcohol (R2OH) can be reacted with glucose, in the presence of an acid catalyst to form the desired glucoside. Alternatively the alkyl polyglucosides can be prepared by a two step procedure in which a short chain alcohol (R1OH) can be reacted with glucose, in the presence of an acid catalyst to form the desired glucoside. Alternatively the alkyl polyglucosides can be prepared by a two step procedure in which a short chain alcohol (C1-6) is reacted with glucose or a polyglucoside (x=2 to 4) to yield a short chain alkyl glucoside (x=1 to 4) which can in turn be reacted with a longer chain alcohol (R2OH) to displace the short chain alcohol and obtain the desired alkyl polyglucoside. If this two step procedure is used, the short chain alkylglucosde content of the final alkyl polyglucoside material should be less than 50%, preferably less than 10%, more preferably less than about 5%, most preferably 0% of the alkyl polyglucoside.
The amount of unreacted alcohol (the free fatty alcohol content) in the desired alkyl polysaccharide surfactant is preferably less than about 2%, more preferably less than about 0.5% by weight of the total of the alkyl polysaccharide. For some uses it is desirable to have the alkyl monosaccharide content less than about 10%.
The used herein, xe2x80x9calkyl polysaccharide surfactantxe2x80x9d is intended to represent both the preferred glucose and galactose derived surfactants and the less preferred alkyl polysaccharide surfactants. Throughout this specification, xe2x80x9calkyl polyglucosidexe2x80x9d is used to include alkyl polyglycosides because the stereochemistry of the saccharide moiety is changed during the preparation reaction.
An especially preferred APG glycoside surfactant is APG 625 glycoside manufactured by the Henkel Corporation of Ambler, Pa. APG25 is a nonionic alkyl polyglycoside characterized by the formula:
CnH2n+1O(C6H10O5)xH
wherein n=10 (2%); n=122 (65%); n=14 (21-28%); n=16 (4-8%) and n=18 (0.5%) and x (degree of polymerization)=1.6. APG 625 has: a pH of 6 to 10 (10% of APG 625 in distilled water); a specific gravity at 25xc2x0 C. of 1.1 g/ml; a density at 25xc2x0 C. of 9.1 lbs/gallon; a calculated HLB of 12.1 and a Brookfield viscosity at 35xc2x0 C., 21 spindle, 5-10 RPM of 3,000 to 7,000 cps.
The organosilane used in the instant composition is a mixture of dimethicone polymer and cyclomethicone. An especially preferred organosilane is manufactured by Dow Chemical as 9040 Silicone Elastomer blend.
The instant light duty liquid nonmicroemulsion compositions contain about 0 to about 10 wt. %, more preferably about 1 wt. % to about 8 wt. %, of at least one solubilizing agent selected from the group consisting of a C1-4 mono, dihydroxy or polyhydroxy alkanols such as ethanol, isopropanol, glycerol ethylene glycol, diethylene glycol and propylene glycol and mixtures thereof and an alkali metal cumene or xylene sulfonates such as sodium cumene sulfonate and sodium xylene sulfonate. The solubilizing agents are included in order to control low temperature cloud clear properties.
The magnesium inorganic salt used in the instant composition is selected from the group consisting of magnesium oxide, magnesium chloride, and magnesium sulfate hepta hydrate and mixtures thereof.
The instant cleaning compositions explicitly exclude alkali metal silicates and alkali metal builders such as alkali metal polyphosphates, alkali metal carbonates and alkali metal phosphonates because these materials, if used in the instant composition, would cause the composition to have a high pH as well as leaving residue on the surface being cleaned.
The final essential ingredient in the inventive cleaning compositions having improved interfacial tension properties is water. The proportion of water in the compositions generally is in the range of 35% to 90%, preferably 50% to 85% by weight of the cleaning composition.
The liquid cleaning composition of this invention may, if desired, also contain other components either to provide additional effect or to make the product more attractive to the consumer. The following are mentioned by way of example: Colors or dyes or perfumes in amounts up to 1.0% by weight; preservatives or antioxidizing agents, such as formalin, 5-bromo-5-nitro-dioxan-1,3; 5-chloro-2-methyl-4-isothaliazolin-3-one, 2,6-di-tert.butyl-p-cresol, etc., in amounts up to 2% by weight; and pH adjusting agents, such as sulfuric acid or sodium hydroxide, as needed. Furthermore, if opaque compositions are desired, up to 4% by weight of an opacifier may be added. Other ingredients in amounts up to 5 wt. % are ethylene diamine tetraacetic acid sodium salt, hydroxy ethylene diamine tetraacetic acid sodium salt, Dowicil 75 and sodium bisulfite.
In final form, the instant compositions exhibit stability at ambient temperatures. More specifically, such compositions remain clear and stable in the range of 15xc2x0 C. to 35xc2x0 C., especially 20xc2x0 C. to 30xc2x0 C. Such compositions exhibit a pH of 6 to 9.0. The liquid cleaning compositions are readily pourable and exhibit a viscosity in the range of 400-800 centipoise (cps) as measured at 25xc2x0 C. with a Brookfield RVT Viscometer using a #21 spindle rotating at 20 RPM.

Light duty liquid cleaning compositions comprising lauryl myristylamido propyl dimethyl amine oxide