A method and an apparatus for adjusting a power in a communication system are disclosed. The power control method includes selecting, in an active set, at least two base stations, estimating powers of respective reverse power control bits received from the at least two selected base stations, and transmitting, to the base stations, forward power control commands generated according to the estimated powers over power control groups, respectively.

1. Field of the Invention
The present invention relates to a mobile communication system, and more particularly a method and an apparatus for adjusting a power in a communication system.
2. Discussion of the Related Art
Generally, a 1x cdma2000 system is designed to support a voice service of a circuit switched mode and a medium and low-speed data service. Also, as the desire for a mobile Internet service and so on increases, a system only for a high-speed packet data communication, to the exclusion of the voice service, has been proposed, which is called a high data rate (HDR) or an 1x-evolution data only (1x-EV DO).
A combined version of the two systems is called a 1x-evolution data and voice (1x EV DV).
The 1x-EV DV system is a system that can perform the voice service and data service of the existing circuit mode simultaneously with a high-speed packet data service.
Accordingly, the 1x-EV DV system should be compatible with 1x of the existing cdma2000 system in a lower direction. Thus, all the currently considered 1x-EV DV standards support a radio configuration (RC) of the existing cdma2000 system, and have independent RC type shared channels for a packet data service in addition.
Basically, the shared channel (hereinafter, referred to as a forward packet data channel (F-PDCH)) for the packet data service can accommodate many users by using a time division multiplexing (TDM) like the HDR or using a mixed type of a code division multiplexing and the TDM.
The 1x-EV DV system uses a method of dynamically allocating an extra base station power and Walsh code to the F-PDCH in a state that voice users and data users of the existing circuit mode exist. Also, the 1x-EV DV system increases the data throughput of the base station by using a method of allocating the extra base station power and the Walsh code to a specified user having a good-quality link. At this time, for the operation of the F-PDCH is required a certain feedback channel for the respective user's transmission of the link quality between the user and the base station to the base station.
The base station performs a scheduling of the target users to whom the data is to be transmitted at the present time based on the link quality reported by the users, and selects a modulation technique and a channel coding rate suitable for the present link quality to transmits the modulation technique and the channel coding rate to the scheduled target users.
Also, in order to improve the data throughput, the F-PDCH operates a hybrid-automatic repeat request (H-ARQ) on a physical layer. For such an operation of the H-ARQ is required a reverse feedback channel for the terminal's judgment of existence/non-existence of an error in a received packet and transmission of an acknowledgement (ACK) or non-acknowledgement (NACK) bit to the base station.
The reverse feedback channel for transmitting the link quality is called a reverse channel quality indication channel (R-CQICH), and the reverse feedback channel for transmitting the ACK or NACK bit is called a reverse acknowledgement channel (R-ACKCH).
In order for the base station to properly receive the reverse feedback channels, it can be considered that a power control with respect to the reverse channels is a required process.
Basically, an IS-2000 system generates a power control bit (PCB) for a forward link power increasing or decreasing command by measuring a dedicated pilot power level of the respective terminal transmitted in a reverse direction, transmits the PCB for each power control group (PCG) by carrying the PCB on traffic information of a forward fundamental channel (F-FCH) or a forward dedicated control channel (F-DCCH), and performs the reverse power control of 800 Hz accordingly.
However, in the 1x-EV DV system, the F-FCH or F-DCCH is not always allocated to the active users (i.e., users having links set for receiving the data from a transmitting end) who will receive the packet data.
Accordingly, a certain new channel is required for the reverse power control, and the channel used for this purpose is just a forward common power control channel (F-CPCCH).
FIG. 1 is a view illustrating the construction of the conventional F-CPCCH channel.
As shown in FIG. 1, blocks for a forward common power control channel are symbol repeat blocks 102 and 109, signal point mapping blocks 103 and 110, channel gain sections 104 and 111, multiplexers 101 and 108, a relative offset calculation section 105, a decimator 106, and a long code generator 107.
The multiplexers 101 and 108 receive the power control bits (PCBs) through branches I and Q, and multiplex the PCBs by users. At this time, the multiplexers 101 and 108 adjust offset values of the PCBs by users according to the offset values provided from a relative offset calculation section 105.
The symbol repeat blocks 102 and 109 do not repeat the multiplexed PCBs through the branch I or Q in case that a transmission (Tx) diversity mode is not used, while they repeat the multiplexed PCBs only once in case that the Tx diversity mode is used.
The signal point mapping blocks 103 and 110 perform the mapping of '0' onto '+1', '1' onto '−1', and '0' in case that no transmission bit exists among the PCBs. The channel gain sections 104 and 111 adjust the channel gain to be used for the transmission in the unit of a power control group. The long code generator 107 generates a long code according to a long code mask for the power control channel, and the decimator 106 detects the long code in the unit of a chip, and provides the detected long code to the relative offset calculation section 105. Accordingly, the relative offset calculation section 105 calculates the offset values by users, and provides the offset values to the multiplexers 101 and 108.
In FIG. 1, if it is assumed that the F-CPCCH channel performs the reverse power control for 800 Hz, the power control bits (PCBs) for 24 active users are transmitted in one power control group (PCG). At this time, the PCBs for the 12 users are allocated to the branch I, and the PCBs for the remaining 12 users are allocated to the branch Q. Also, a process of randomizing positions of the PCB bits in one PCG by users through a relative offset calculation is performed. Also, if it is assumed that the F-CPCCH channel performs the reverse power control for 400 Hz and 200 Hz, the PCBs for the 48 users and the 96 users can be accommodated in one F-CPCCH channel, respectively.
The F-CPCCH channel is a common channel, and it is required that the users far apart from the base station can receive the channel with reliability. That is, the power control for the reverse feedback channels can be performed with reliability only in case that the F-CPCCH can accurately judge the PCB bits allocated to the F-CPCCH itself The simplest usable method is a method of performing the transmission with a sufficiently high power so that the users located on the edge of the cell can receive the PCB bits with a sufficient reliability.
This method has the following problem. Since PCBs for the user located far away from the base station may be included on the F-CPCCH, the base station should allocate to the F-CPCCH a high power sufficient for the user to receive its own PCB. At this time, the forward packet data channel (F-PDCH) uses all the remaining power of the base station for the packet transmission. However, if the F-CPCCH is transmitted always with a high power, the transmission power for the F-PDCH would be lost, and this causes the reduction of the data throughput of the forward link.
Accordingly, in order to solve this problem, the forward power control should be performed in the unit of a bit with respect to the respective users who belong to one power control group.

Method and apparatus for adjusting power in a communication system for a channel used for power control for reverse feedback channels


A section of a gas turbine engine includes a damper which extends from a disk between a first blade and a second blade to provide a dissipating vibratory motion energy in the form of friction heating.

The present disclosure relates to gas turbine engines and, more particularly, to damping mechanisms which reduce vibratory stress levels in the rotor blades thereof.
Gas turbine engines typically have rows of circumferentially spaced blades mounted on respective rotor disks for rotation about an engine axis. Advanced configurations feature shroudless hollow airfoils manufactured of light weight materials. The blades are designed to high tolerances to accommodate significant operational requirements such as cross-winds and inlet distortion. These requirements result in blades that may be prone to high vibratory responses and possible aeroelastic instability within some operational speed ranges. To mitigate these effects, the blades may be damped.

Non-integral platform and damper for an airfoil


Automatic non-contact measuring optical properties of an optical object is performed by a system comprising a light source, a reference pattern, and an imaging and detecting means and an image processing means for producing a measurement output. At least the reference pattern and the imaging and detecting means are disposed on an optical axis of the system. The system further comprises a support for the optical object located between the reference pattern and the imaging and detecting means for disposing thereon the optical object coaxially with the pattern and the imaging and detecting means. The light source is capable of directing to the pattern an illuminating light in such a manner as to produce a plurality of illuminating light beams outcoming from each point of the pattern at different angles. The imaging and detecting means is capable of obtaining an image of the pattern through the optical objects so that each imaging beam is conjugate with only one of the illuminating beams, and of recording the image for its processing by the image processing means.

This invention relates to automatic non-contact measurements of optical properties of optical objects, particularly, to mapping optical objects.
The present invention particularly refers to a method and system for mapping an ophthalmic element, where optical properties of the element such as its optical power are measured simultaneously along the element""s entire surface. U.S. Pat. No. 4,810,895, U.S. Pat. No. 5,825,476, and U.S. Pat. No. 5,896,194 illustrate different kinds of such methods and systems.
U.S. Pat. No. 4,810,895 discloses a method and apparatus for moire ray deflection mapping, where properties of an object are determined by producing a diverging beam of direct light from a point radiation source, passing this beam through a first optical system including the object to be examined, which system retraces the light in the form of a converging beam of reflected light from the examined object back towards the point source. The converging beam of reflected light is intercepted before reaching the point source and is passed through a second optical system which collimates the beam of reflected light. The collimated beam is then directed through first and second gratings at a preselected angular orientation with respect to each other to produce moire fringe patterns providing an indication of the properties of the examined object.
U.S. Pat. No. 5,825,476 discloses an apparatus for mapping an optical object, including a light source directing a light beam towards the optical object, an array of microlenses which divide the light beam passed through the optical object into a plurality of light beams at least some of which differ from each other, and form on a diffusive screen a corresponding plurality of images of the light source, a camera for recording these images and a computer for processing the multiple images and comparing them with a reference pattern.
U.S. Pat. No. 5,896,194 discloses an apparatus which includes a first light source for generating a lens-characteristic measuring light beam, a second light source for generating a position specifying light beam, a pattern plate with lens-characteristic measuring patterns and position specifying patterns, on which the beams from the light sources are projected through an inspected optical object to receive images of the patterns on a diffusive screen. The received images are analyzed, and the lens-characteristic mapping display of the inspected lens is performed.
It is the object of the present invention to provide a novel method and system for automatic non-contact measuring optical properties of an optical object.
In accordance with one aspect of the present invention, there is provided a method for automatic non-contact measuring optical properties of an optical object by means of a system comprising a light source, a reference pattern, an imaging and detecting means, at least the reference pattern and the imaging and detecting means being disposed on an optical axis of the system, and an image processing means.
The method of the present invention comprising the steps of:
(a) disposing said optical object between said reference pattern and said imaging and detecting means coaxially therewith;
(b) directing to said pattern an illuminating light from said light source in such a manner as to produce a plurality of illuminating light beams outcoming from each point of the pattern at different angles;
(c) imaging said pattern through said optical object by means of imaging beams each of which is conjugate with only one of said illuminating beams and detecting the image, by said imaging and detecting means, and
(d) processing said image by said image processing means and producing a measurement output, preferably by comparing the image with an image of said pattern obtained by said imaging and detecting means in the absence of said optical object.
According to another aspect of the present invention, there is provided a system for automatic non-contact measuring optical properties of an optical object, comprising a light source, a reference pattern, an imaging and detecting means, at least the reference pattern and the imaging and detecting means being disposed on an optical axis of the system, a support for the optical object located between said reference pattern and said imaging and detecting means for disposing thereon the optical object coaxially with said pattern and said imaging and detecting means, said light source being capable of directing to said pattern an illuminating light in such a manner as to produce a plurality of illuminating light beams outcoming from each point of the pattern at different angles, said imaging and detecting means being capable of obtaining an image of said pattern through said optical object so that each imaging beam is conjugate with only one of said illuminating beams, and of recording said image, and an image processing means for processing said image and producing a measurement output.
In the method and system according to the present invention, the pattern and the light source illuminating it are so designed as to ensure that the light outcoming from the illuminated reference pattern is scattered, whereby said plurality of illuminating beams outcoming from each point of the pattern is provided. The conjugation of each imaging beam with only one of said plurality of illuminating beams is achieved by said imaging and detecting means including a detector camera with a camera lens whose entrance pupil allows only an extremely narrow light beam to pass therethrough. Thereby, the detector camera in fact chooses from the plurality of illuminating beams only those whose angles of incidence on the inspected optical object suit the setup of the imaging and detecting means, and uses these beams for forming the image of the reference pattern.
To provide the scattered light outcoming from the reference pattern, the light source may be in the form of a diffusive illuminator or it may be an arbitrary monochromatic light source whose light is specifically diffused prior to its impinging the reference pattern. In this case the reference pattern may be formed on transparent material such as mineral glass or it may be rather formed on a plate with a coating providing a total internal reflection. Alternatively, the pattern itself may be made of, or formed on, a diffusing (scattering) material (reflecting or transmitting) such as milky glass, ground glass or paper.
The reference pattern is preferably in the form of a number of regularly arranged pattern elements having known dimensions and shapes and known mutual disposition. For example, these elements may be points, lines or circles, concentric circular and radial lines, staggered squares, regular grid and the like. The pattern may have highlighted origin lines. It may be designed as a black pattern on a bright background or white pattern on a dark background. It may be in the form of a plurality of openings or slits.
With the method and system of the present invention, the inspected optical object introduces, due to its refractive properties, deformation into dimensions, shapes and/or positions of the elements of the imaged pattern. Thus, spherical power leads to the magnification of the imaged pattern elements. Cylindrical optical power leads to their deformation with the direction of the deformation indicating to the orientation of the cylinder axis. Prismatic power leads to the parallel displacement of the elements of the pattern image relative to their reference position, with the direction of the displacement indicating to the orientation of the prism axis. Measurements of these deformations enable the calculation of the optical object""s refractive properties at any point and, if desired, their presentation in the form of a map of the optical object along its entire inspected area. The map may be a spherical optical power map, a cylindrical optical power map or a prismatic optical power map, the two latter maps being each accompanied by a corresponding vector field characterizing the direction of the respective cylinder or prism axes at different areas of the inspected optical object. Alternatively, the map may be in the form of a topographic map presenting point-to-point heights of the optical object""s inspected surface.

Method and system for automatic non-contact measurements of optical properties of optical objects


A plurality of switches composing a voltage changing switch circuit 17 are supplied with a plurality of types of voltages, and are provided so as to correspond to a plurality of row decoders 2, such that each switch can separately select and output any of the plurality of types of voltages to the corresponding row decoder 2. Voltage boost circuits 7, 8 generate a plurality of types of voltages by boosting a power supply voltage. A regulator circuit 9 steps down at least one of the plurality of types of voltages generated by the voltage boost circuits 7, 8 to stabilize a voltage value, and outputs the resultant voltage to each switch. Each row decoder 2 selects a memory cell by using a voltage outputted from the corresponding switch. Thus, it is possible to reduce a time required for a program/program verify operation, while reducing power consumption.

1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, more particularly, relates to a nonvolatile semiconductor memory device having a memory cell array in which a plurality of memory cells are disposed in the form of a matrix and are divided into a plurality of sectors.
2. Description of the Background Art
A conventional nonvolatile semiconductor memory device such as a flash EEPROM realizes program/erase and read operations using various high voltages. In order to generate these high voltages, a voltage boost circuit for boosting a power supply voltage and outputting a high voltage is generally used. Thus, a nonvolatile semiconductor memory device having a built-in voltage boost circuit is widely used (for example, see Japanese Laid-Open Patent Publication No. 5-290587, pages 4–5, FIG. 1).
Hereinafter, a conventional nonvolatile semiconductor memory device as shown in FIG. 16 will be described. FIG. 16 is a block diagram showing a structure of a conventional EEPROM. A memory cell array 1 is divided into N (N is natural number) sectors S1 to SN. The sectors S1 to SN are electrically rewritable nonvolatile memory cells, and floating gate memory cells MC are arranged and connected in a NOR array configuration as shown in FIG. 17. The drain of each memory cell MC is connected to a bit line BL, the source thereof is connected to a common source line SL, and a control gate thereof is connected to a word line WL. The word line WL of each of the sectors S1 to SN is selected by a row decoder 2 that is divided into N (N is natural number) decoder blocks XDEC1 to XDECN, and the bit line BL is selected by a column gate 4 that is driven by a column decoder 3. An address AD is inputted to an address/data buffer 5, and a row address and a column address are decoded by the row decoder 2 and the column decoder 3, respectively.
When data is read, bit line data selected by the column gate 4 is detected and amplified by a sense amplifier 6, and outputted from an I/O terminal via the address/data buffer 5. Also, when data is written, data DB inputted from the I/O terminal is latched by the sense amplifier 6 via the address/data buffer 5, and the latched data DB is transferred to the bit line BL selected by the column gate 4.
The high-voltage generation boost circuit 7 and the low-voltage generation boost circuit 8 are provided for generating a boost voltage higher than a power supply voltage that is necessary to program/erase/read data. A low boost output voltage VPPL of the low-voltage generation boost circuit 8 is supplied to a regulator circuit 9. After the voltage is stabilized, the regulator circuit 9 outputs a regulator output voltage VRO. Also, a high boost output voltage VPPH of the high-voltage generation boost circuit 7 is supplied to a voltage changing switch circuit 10 along with the regulator output voltage VRO of the regulator circuit 9. In accordance with a switch control signal supplied from a control circuit 11, the voltage changing switch circuit 10 selects the high boost output voltage VPPH or the regulator output voltage VRO of the regulator circuit 9, and supplies the selected voltage to the row decoder 2 as word line supply voltages Vwll to VwlN. In accordance with to a mode signal MD, a chip enable signal CEB, a program enable signal WEB, and an output enable signal OEB, the control circuit 11 controls the address/data buffer 5, the high-voltage generation boost circuit 7, the low-voltage generation boost circuit 8, the regulator circuit 9, and the voltage changing switch circuit 10 so that each circuit performs a predetermined operation according to a data program/erase/read mode.
FIG. 18 shows one example of the high-voltage generation boost circuit 7. In FIG. 18, a two-phase clock voltage boost circuit driven by a boost clock is shown. In this two-phase clock voltage boost circuit, diode-connected NMOS transistors Mn1 to Mn6, and Mn10 are connected in series to form a seven-stage circuit. An input terminal of the first NMOS transistor Mn1 is fixed to a power supply potential Vcc (=2.5V), smoothing capacitance Co and a Zener diode Dzh are inserted between an output terminal, which supplies the high boost output voltage VPPH, and a ground potential Vss, and a switch circuit 12 that is electrically connected/disconnected in accordance with a stop mode signal is inserted between the output terminal and the power supply potential Vcc.
FIG. 19 shows one example of the low-voltage generation boost circuit 8. In FIG. 19, any component elements that have similar counterparts in FIG. 18 are denoted by the same reference numerals as those used therein. In FIG. 19, diode-connected NMOS transistors Mn1 to Mn4, and Mn10 are connected in series to form a five-stage circuit, and a Zener diode Dzl is inserted between an output terminal, which supplies the low boost output voltage VPPL, and the ground potential Vss.
As shown in FIG. 20, the regulator circuit 9 includes a comparator CMP, which uses the low boost output voltage VPPL as a power supply, and a PMOS transistor Mp1 that is controlled to turn ON/OFF by an output of the comparator CMP and is connected in series between a VPPL node and a VSS terminal. In this case, the drain terminal of the PMOS transistor Mp1 functions as an output terminal, and supplies the regulator output voltage VRO. A VRO output terminal is provided with a resistance voltage divider circuit, in which resistances R1 to R3 are connected in series, and a feedback voltage VFB of the resistance R3 is fed back to a noninverting input terminal of the comparator CMP. A reference voltage VREF is inputted to an inverting input terminal of the comparator CMP. Therefore, ON/OFF control of the PMOS transistor Mp1 is performed so that a feedback voltage VFB is equal to the reference voltage VREF. Also, a short-circuit PMOS transistor Mp2, which is controlled by a mode control signal RDB, is connected between a node NR, which exists between the resistances R1 and R2, and the VRO output terminal. For example, a potential is controlled so that a mode control signal RDB is deactivated and the PMOS transistor Mp2 is turned ON in a read operation, whereas the PMOS transistor Mp2 is turned OFF in a program verify operation. As a result, for example, it is possible to output a VRO of 4.5V in a read operation, and output a VRO of 5.5V in a program verify operation. Also, a switch circuit 13, which is controlled by a stop mode signal, is inserted between the VRO output terminal and a Vcc power supply terminal, and a switch circuit 14, which is controlled by a stop mode bar signal, is provided between a node N1 of the resistance R3 and a Vss ground terminal.
FIG. 21 shows one example of a unit decoder comprising the row decoder 2. The unit decoder consists of a NAND gate G1 carrying out the logical product (AND) between a plurality of row addresses ADR, a level shift circuit 15, and a driver circuit 16. In a unit decoder selected from among the N decoder blocks, a node N2 is deactivated. The level shift circuit 15 consists of PMOS transistors Mp3 and Mp4, NMOS transistors Mn11 and Mn12, and an inverter gate G2. A signal of the node N2 is inputted to a gate of the NMOS transistor Mn11, and an inversion signal of the node N2 is inputted to a gate of the NMOS transistor Mn12. The driver circuit 16 is an inverter circuit consisting of an NMOS transistor Mn13 and a PMOS transistor Mp5. The driver circuit 16 uses an output of the level shift circuit 15 as an input, and uses a word line supply voltage Vwll as a power supply. An output voltage of the driver circuit 16 is applied to the control gate of the memory cell MC. Also, in this case, all N-well nodes NW of the PMOS transistors Mp3 to Mp5 are connected to the word line supply voltage Vwll.
Hereinafter, an operation of the above-described nonvolatile semiconductor memory device will be described. In a data program operation, the high boost output voltage VPPH (=10V) is applied, as a word line WL voltage, to the control gate of the memory cell MC that is selected in accordance with a program address AD and a data DB input, and 0V is applied to a non-selected word line WL. At this time, in accordance with the data DB to be written, 5V or 0V is applied to the bitline BL. Also, 0V is applied to the common source line SL. As a result, writing is performed on the memory cell MC that is connected to a selected word line WL and whose drain terminal is provided with 5V via the bit line BL, an electron is added to the floating gate, and a threshold value of the memory cell MC increases in a normal direction.
Specific operations of the power supply circuit and the decoder 2 are as follows: A boost clock is inputted to the high-voltage generation boost circuit 7 as shown in FIG. 18 from the control circuit 11. A boost voltage higher than a power supply voltage is generated by a known charge transfer operation, and clamped to 10V by the Zener diode Dzh provided on the output terminal, and the high boost output voltage VPPH (=10V) is supplied to the voltage changing switch circuit 10. At this time, a stop mode signal inputted from the control circuit 11 is deactivated, and the switch circuit 12 is electrically disconnected. Also, a boost clock is inputted to the low-voltage generation boost circuit 8 as shown in FIG. 19 in a similar manner. A boost voltage higher than a power supply voltage is generated and clamped to 7V by the Zener diode Dzl provided on the output terminal, and the low boost output voltage VPPL (=7V) is supplied to the regulator circuit 9. At this time, a stop mode signal is activated and a stop mode bar signal is deactivated since the regulator circuit 9 as shown in FIG. 20 stops during a program operation. As a result, the switch circuit 13 is electrically connected, whereas the switch circuit 14 is electrically disconnected, and the regulator output voltage VRO (=Vcc) is supplied to the voltage changing switch circuit 10.
In the voltage changing switch circuit 10, the high boost output voltage VPPH (=10V) is selected in accordance with a switch control signal supplied from the control circuit 11, and supplied to all the decoder blocks XDEC1 to XDECN of the row decoder 2 as word line supply voltages Vwll to VwlN. At this time, as shown in FIG. 21, a very large load capacitance such as the N-well node NW, which is used in common by all the decoder blocks XDEC1 to XDECN, is charged by the word line supply voltages Vwll to VwlN. After charge is completed, a predetermined word line WL is selected, and only a node N2 of a unit decoder driving the selected word line WL is deactivated. Thus, the high boost output voltage VPPH (=10V) is outputted and applied to the control gate of the selected memory cell MC. Voltages of non-selected word lines WL are not changed (=0V).
Next, in a program verify operation, 1V is applied to the selected bit line BL at the same time as the regulator output voltage VRO (=5.5V) is applied to a control gate of a cell for which writing is performed. Also, 0V is applied to the common source line. At this time, a bit line potential is detected and amplified by the sense amplifier 6 to determine whether the above cell is a cell for which writing has been performed or a cell for which erasure has been performed. When it is determined that the above cell is a cell for which writing has been performed, a next program operation is cancelled. On the other hand, when it is determined that the above cell is a cell for which erasure has been performed, a next program operation is performed. Specific circuit operations of the power supply circuit and the row decoder 2 are as follows: a stop mode signal is activated at the same time as a boost clock to be supplied to the high-voltage generation boost circuit 7 as shown in FIG. 18 is stopped, and the switch circuit 12 is electrically connected. As a result, a power supply potential Vcc is supplied to the voltage changing switch circuit 10.
As is the case with the program operation, a boost clock is inputted to the low-voltage generation boost circuit 8 as shown in FIG. 19. A boost voltage higher than a power supply voltage is generated and clamped to 7V by the Zener diode Dzl provided on the output terminal, and the low boost output voltage VPPL (=7V) is supplied to the regulator circuit 9. At this time, in the regulator circuit 9 as shown in FIG. 20, a mode control signal RDB is activated, the PMOS transistor Mp2 is OFF, and the resistance R1 is enabled. At the same time, a stop mode signal is deactivated and as top mode bar signal is activated, whereby the switch circuits 13 and 14 are electrically disconnected and connected, respectively. As a result, the regulator output voltage VRO (=5.5V) is supplied to the voltage changing switch circuit 10.
Next, in the voltage changing switch circuit 10, the regulator output voltage VRO (=5.5V) is selected in accordance with a switch control signal supplied from the control circuit 11, and supplied to all the decoder blocks XDEC1 to XDECN of the row decoder 2 as word line supply voltages Vwll to VwlN. At this time, as shown in FIG. 21, a load capacitance such as the N-well node NW, which is used in common by all the decoder blocks XDEC1 to XDECN, is charged by the word line supply voltages Vwll to VwlN. After charge is completed, a predetermined word line WL is selected, and the regulator output voltage VRO (=5.5V) is outputted and applied to a control gate of the selected memory cell MC. Voltages of non-selected word lines WL are not changed (=0V).
FIG. 22 shows a timing chart indicating a voltage system supplied to a word line WL during the above-described program/program verify operation. First, in a stop state (STOP), word line supply voltages Vwll to VwlN coincide with a power supply potential Vcc due to a stopped state of the high-voltage generation boost circuit 7, the low-voltage generation boost circuit 8, and the regulator circuit 9. Next, when a transition is made to a program state (Program), the high-voltage generation boost circuit 7 and the low-voltage generation boost circuit 8 enter an operation state. In this state, the high-voltage generation boost circuit 7 charges a load capacitance from the power supply potential Vcc up to a high boost output voltage VPPH (=10V), and the low-voltage generation boost circuit 8 charges a load capacitance from the power supply potential Vcc up to a low boost output voltage VPPL (=7V). At this time, the voltage changing switch circuit 10 causes the high boost output voltage VPPH (=10V) to pass through the row decoder 2, whereby a load capacitance seen by the high-voltage generation boost circuit 7 becomes very large. As a result, it is necessary to take a very long setup time 11.
Next, when a transition is made from a program state to a program verify state (PV), the high-voltage generation boost circuit 7 enters a stopped state, and the high boost output voltage VPPH (=10V) is discharged to a power supply potential Vcc. Also, the regulator circuit 9 is in an operation state, and the regulator output voltage VRO (=5.5V) obtained by stepping down the low boost output voltage VPPL (=7V) is supplied to the row decoder 2 via the voltage changing switch circuit 10. In the case where it is not determined that writing is completed in the above PV operation, a transition is made to next Program and PV operations. Note that a load capacitance is charged from the regulator output voltage VRO (=5.5V) . Thus, a setup time τ l to reach the high boost output voltage VPPH (=10V) in a second or later program mode is slightly shorter than the first setup time τ l1. Hereinafter, the above-described program/program verify operation is repeated until writing is performed for all desired memory cells MC.
As described above, in a method in which a program/program verify operation is repeated, if necessary, a plurality of times, a very large load capacitance such as the N-well node NW of the row decoder 2 has to be charged by the high boost output voltage VPPH (=10V) every time a transition is made to a program mode. As a result, it is necessary to take a very long setup time τ l every time a loop is executed. Thus, the conventional nonvolatile semiconductor memory device has disadvantages in that power consumption of the high-voltage generation boost circuit 7 which supplies a high boost charge is increased due to a very long time required for a program/program verify operation and a very large load capacitance to be charged and discharged by a high boost charge. Also, another disadvantage is that power consumption is increased if current supply capacity of the high-voltage generation boost circuit 7 generating VPPH is enhanced in order to reduce τ l.
As such, the above-described structure has disadvantages in that it is difficult to reduce a time required for a program/program verify operation and power consumption, and that power consumption is increased by reducing a time required for a program/program verify operation.

Matsushita Electric Industrial Co., Ltd.


A fowl retention system is used to passively retain fowl in a preselected natural habitat or a preselected created habitat and to compress the fowl territory. The fowl retention system includes a food/water station contained within a barrier assembly, a protective structure, and a man-made field strip. The fowl retention system provides for the compression of fowl territories, thereby increasing the fowl population per unit area. Further compression of the fowl territory locations provides an additional level of compression by propagating the high density population of the fowl. The protective structure is designed to shield the fowl from the elements and predators. The field strip is planted with native vegetation for both cover and the production of food. The food and water station provides a continuous food and water supply for the fowl.

1. Field of the Invention
The present invention relates to retaining fowl and, more particularly, but not by way of limitation, to the retention of fowl in a natural environment.
2. Background of the Invention
In the bird hunting industry, the production and retention of birds in a predetermined location is key to the continuing success of hunters, as well as to the success of the operators of a hunting establishment. Many hunters return to proven hunting grounds or establishments, on at least an annual basis. The continued operation of the hunting establishment is directly tied to the ability of the hunting establishment to retain fowl in a prescribed area. Those operations that excel at the retention of the fowl will have increased quantities of the fowl for harvest, as well as increased chances for reproduction of the fowl at the preselected location.
As fowl in a natural setting are able to fly, those involved in retaining the fowl must provide all of the necessary elements of the fowl habitat. Retention of the fowl is largely dependent upon the proper habitat, and the availability of food and water sources within the local environment. In a natural setting, non-migratory fowl are territorial. As such, proper habitats must be established to provide each province with all required aspects of the fowl habitat. If an appropriate habitat is not available in the immediate area, the fowl will move to a more correct habitat. Challenges arise when multiple habitats must be created in controlled areas or on tracts of land that are not naturally conducive to the desired type of fowl. Variations of topography within a specific plat of land can also present problems, as sections of the site may include suitable habitats and other sections may be unsuitable for the fowl.
Further complications arise when a large number of territories are established on acreage with preexisting boundaries, as the territories may be too close together. Alternatively, if the territories are separated by great distances, frequent visits to a large number of territories to properly feed and ensure proper water supplies can prove to be overwhelming. The operators of the hunting establishments must continually be able to provide food and water to the territories. The distribution of small quantities of food product is not optimal, as the operators will continually be required to provide feed and water on a high-frequency rate. However, the distribution of food in large quantities is not feasible if unprotected, as other native animals will likely consume any unprotected food product.
Accordingly, a fowl retention system that promotes the propagation and retention of fowl in a natural environment would be beneficial to operators of hunting establishments, as well as those raising large quantities of fowl.

This patent is subject to a terminal disclaimer.

Fowl retention and territory compression system


A power transmission belt (20) having an elastic main body (17) includes a top layer as the belt backing and a bottom section having a power transmission zone. The power transmission zone and/or the top layer has/have a coating (15, 16), characterized in that the coating (15, 16) of the power transmission zone and/or the top layer includes at least the following layer construction: a base coating (18) made of a textile material, wherein the base coating (18) forms a bond with the elastic main body (17) and has a surface coating (19) including at least a mixture A, which contains at least one reactive diluent as per DIN 55945:2007-03. The invention further relates to a method for producing such a power transmission belt. The novel coating concept is applicable in particular in a toothed belt.

Force transmission belts, which are also referred to as drive belts and which form endless loops in the operational state, can be configured as flat belts, V-belts, V-ribbed belts and toothed belts.
The surface of these force transmission belts and of a toothed belt in particular has to have good gliding properties and be wear resistant. Such a surface is achieved through a coating with or without textile cover ply. When the force transmission belt is operated under an oil atmosphere, an additional requirement is good oil resistance to protect the coating and the rubber mixture(s) underneath from the penetration of oil.
Mixtures of a flexible polymeric layer with fillers are typically used for this because they are both readily glidable and oil resistant.
DE4400434A1, EP0662571A1 and U.S. Pat. No. 6,419,775 describe woven fabric coatings that consist of a polyurethane coating with particulate fluoropolymers and provide good abrasion resistance. The two-component coating mass has a low viscosity, penetrates into the woven fabric relatively deeply and undergoes crosslinking to form an abrasion-resistant layer. However, these layers have an open structure and so are insufficiently abrasion-resistant for many applications. Furthermore, owing to this open structure they are not oil-resistant and owing to the polyurethanes used their thermal stability is insufficient for many applications.
The lack of heat resistance is taken up in U.S. Pat. No. 7,946,940 where 1,2-diols are disclosed as not being as heat-resistant as the longer-chain 1-omega diols. There are again issues with abrasion and oil resistance.
DE102008013570A1 describes coating systems for woven fabric surfaces of force transmission belts, wherein the coating contains a polyisocyanurate-polyurea formed from an isocyanate having at least two NCO groups as base component. This coating exhibits outstanding glidability coupled with good heat resistance, but possesses unfavorable processability owing to the sensitivity of the coating masses. Moreover, because of the solvents needed, coating to deeply penetrate the woven fabric is not possible.
Gliding systems for belts having uninterrupted surfaces are described in U.S. Pat. No. 6,739,997, U.S. Pat. No. 7,985,152, U.S. Pat. No. 7,749,118 and EP1881229A1 for dry applications and in U.S. Pat. No. 7,749,118 and WO2007036960A1 for applications in oil. What is common to the systems described in the references cited is that they consist of a coating composed of an elastomeric matrix and a glidant which is present in less than 50% quantity and preferably is fluoropolymer containing. The elastomeric matrix is always based on commercially available polymers which, owing to their high molecular weight of >5000 g/mol, are incapable of penetrating into the woven fabric if applied with no or almost no solvent. The layer thus covers the woven fabric, but does not penetrate thereinto, leading to a slight breakdown of the woven fabric and, on the other hand, in use, to cracks through which oil, for example, is easily able to penetrate.
An improved heat resistance and an improved resistance to the skipping of teeth are said to be ensured by the toothed belt disclosed in U.S. Pat. No. 5,234,387. In this toothed belt, the tooth rubber and the backing rubber comprise a hydrogenated nitrile rubber polymer crosslinked with organic peroxide, and a co-crosslinker comprising N,N′-m-phenylenedimaleimide in combination with a compound from various acrylates, isocyanurates, mellitates, phthalates, carboxylates or metal salts. Advantages in respect of abrasion and/or oil resistance are not known for this.

Power transmission belt, in particular toothed belt, and method for the production thereof


A process for fabricating a semiconductor transistor in which a semiconductor substrate is provided and a gate dielectric layer formed on an upper surface of the semiconductor substrate. A base conductive layer is then deposited on an upper surface of the gate dielectric layer. The base conductive layer is patterned to form base sections of a first and a second gate structure. Source/drain impurity distributions are introduced into the semiconductor substrate using the base sections as a mask to form source/drain structures within the semiconductor substrate. An insulating support layer is then formed on a topography defined by the semiconductor substrate and the base section. The insulating support layer is planarized until an upper surface of the insulating support layer is substantially planar with upper surfaces of the base sections. A second conductive layer is then deposited. The second conductive layer includes gate portions and interconnect portions. The gate portions reside above the base sections of the first and second gate structures. The interconnect portions reside above the insulating support layer. The second conductive layer is then patterned by removing selected areas of the interconnect portions of the second conductive layer. This process completes the first and second gate structures wherein each of the gate structures includes the base section and the gate portion of the second conductive layer. In this manner, a completed thickness of the first and second gate structures is greater than a thickness of the gate structures prior to the introduction of the source/drain impurity distributions.

1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a two step deposition process for forming gate structures in MOS integrated circuits for improved lithography control coupled with a low overhead local interconnect.
2. Description of the Relevant Art
Integrated circuits employing MOS transistors have been widely known and extensively used in the electronics industry for over 30 years. The basic structure and processing sequence for forming an MOS transistor and MOS integrated circuits has been extensively described in the literature. Typically, a thin oxide is grown on a lightly doped silicon substrate. Thereafter, a gate structure is formed over the thin oxide layer typically by depositing polysilicon and patterning the polysilicon with conventional photolithography masking and etch techniques. After the MOS transistor gate has been formed, it is used as a mask for a subsequent implant during which source/drain structures are formed within the silicon substrate. The source/drain structures are of opposite conductivity type than the silicon substrate. Current flow between the source and drain structures is negligible under equilibrium conditions because back to back pn junctions exist between the source and drain structures. Upon application of an appropriate bias to the MOS transistor gate, however, a conductive channel is induced at the silicon-oxide interface providing a path between the source and drain structure through which current may flow upon appropriate biasing of the source and drain terminals. In this manner, the MOS transistor functions as a switch controlled by the transistor gate.
Present day semiconductor integrated circuits include a large number (i.e., greater than 10.sup.6) of MOS transistors fabricated within a single silicon substrate. The operating characteristics of each of these transistors are dictated, to a large extent, by the physical geometries of the transistors. It will be appreciated by those skilled in the art that small variations in operating characteristics of the individual transistors fabricated with a given semiconductor process may result in large an often unacceptable variations in the operating characteristics of the semiconductor device as a whole. For example, the speed of an integrated circuit, measured by the time required to complete a function, is related to the operating characteristics of the integrated circuits transistors. The saturated drain current I.sub.dsat represents the current flowing from the drain terminal to the source terminal when the gate is biased to induce a strong channel in the silicon substrate (i.e., V.sub.G >V.sub.T where V.sub.T represents the transistor threshold voltage) and the drain terminal is strongly biased with respect to the source terminal (i.e., V.sub.DS >=V.sub.G). The I.sub.dsat characteristic of a particular semiconductor process is a speed indicator because higher drain currents result in faster transistor switching times. The integrated circuit transistor gate, which functions as an input of the transistor in a typical configuration, has a small but finite capacitance associated with it. Because of the gate capacitance, the gate voltage cannot change instantaneously from an "on" value (i.e., .vertline.V.sub.G .vertline.>=.vertline.V.sub.T .vertline.) to an "off" value. Instead, the output current from the preceding transistor stage, typically the drain current of the preceding stage, charges the gate capacitance such that the gate voltage transitions to a new value. It will be appreciated, therefore, that higher saturated drain current results in faster switching times for a typical integrated circuit.
It is well known in the field of semiconductor processing that the saturated drain current I.sub.dsat, to a first order approximation, varies directly with the width of the transistor and varies inversely with the length of the transistor. The desire to maximize I.sub.dsat has resulted in a steady trend within the semiconductor processing industry towards shorter and shorter channel lengths for integrated circuit transistors. With present day integrated circuit transistors, the channel length is not uncommonly less than one micron. In this submicron region, control of the integrated circuit transistor dimensions becomes increasingly important. Not only is it more important to fabricate smaller and smaller devices, it is equally important to minimize variations among the individual transistors comprising the integrated circuit. Minimizing transistor variability requires improved control over each aspect of the semiconductor process. Typical semiconductor processes include a transistor gate formation sequence in which polysilicon or other suitable material is deposited typically to a thickness in the range of approximately 1000 to 3000 angstroms and thereafter patterned with a photolithography/etch sequence. To minimize variability of the integrated circuit, it is desirable if the etch process used to form the transistor gate produces sidewalls that are substantially perpendicular to the upper surface of the semiconductor substrate. Typically, however, semiconductor processes including polysilicon etch processes result in sloped sidewall profiles. Sloped sidewalls in transistor gates are typically undesirable because the final dimension of the transistor gate varies with the vertical displacement above the oxide-gate interface. Referring to FIG. 1, a gate structure 10 is shown fabricated on a silicon dioxide layer 14 over a silicon substrate 20. Gate structure 10 includes a pair of sidewalls 12a and 12b. Sidewalls 12a and 12b extend between a gate upper surface 13 and a gate-oxide interface at an angle .alpha.. The slope of sidewalls 12a and 12b represented by the angle .alpha. produce a transistor gate 10 in which a lateral dimension d.sub.1 of transistor gate 10 near the gate-oxide interface is greater than a lateral dimension d.sub.2 describing the lateral dimension of gate 10 proximal to upper surface 13. It will be further appreciated that the discrepancy between the first lateral displacement d.sub.1 and the second lateral displacement d.sub.2 increases with increasing gate thickness t.sub.g. The sloped sidewalls 12a and 12b are undesirable because the lateral dimension of gate 10 as patterned with the photolithography/etch sequence varies from the as drawn dimension. It will be appreciated to those skilled in the art of semiconductor processing that the critical dimension or channel length of the transistor fabricated in FIG. 1 will be defined by the first displacement d.sub.1 typically resulting in transistor channel lengths that are greater than desirable. Furthermore, variability in the angle .alpha. results in further unwanted variations in the transistor channel length.
In addition to the variability control problems identified with respect to FIG. 1, typical semiconductor processes include a sequence for forming a so called local interconnect layer in addition to the process sequence used to fabricate transistor gate 10. In the typical semiconductor process, the transistor gate is fabricated with a single polysilicon deposition process. If a local interconnect is desired, it must be fabricated with a subsequent deposition of a conductive material. Dedicated processing steps such as a process step dedicated solely to the formation of semiconductor interconnects are typically undesirable because of the increased complexity and cost associated with additional processing.

Thin polysilicon masking technique for improved lithography control


A method is provided to promote secretion of cholecystokinin (CCK) by administering an active component. The active component includes acrylic acid and/or an unsaturated aldehyde having a main chain of 4 to 12 carbon atoms having a double bond in at least position 2 or 4, where the main chain has 4 to 9 carbon atoms when there is a double bond in only position 2, and the main chain has 9 to 12 carbon atoms when there is a double bond in only position 4. The cholecystokinin secretion-promoting composition can be used as an appetite suppressant. By adding this cholecystokinin secretion-promoting composition to food, appetite-suppressing food products can be provided.

The term "obesity" refers to a state of having a larger body weight or a state of having an excessive accumulation of body fat compared to a normal state. Obesity is a contemporary lifestyle disease caused by biased dietary habits, lack of exercise, or lack of sleep. Obesity caused by a metabolic disorder or an endocrine disease is called symptomatic obesity. Either obesity can be a risk factor of diseases such as hyperlipidemia, hypercholesterolemia, hypertriglyceridemia, hypertension, arteriosclerosis, ischemic heart disease, stroke, and arteriosclerosis obliterans. Accordingly, prophylaxis or treatment of obesity can be an effective means for preventing these diseases.
Cholecystokinin (hereinafter, referred to as CCK) is a gastrointestinal hormone secreted from the duodenal mucosal cells by ingestion of a lipid, protein, or other nutrients. This hormone is known to accelerate the enzyme secretion from the pancreas, to contract the gallbladder, and to delay the transfer of gastric contents to the duodenum by closing the pylorus of the stomach (Non-Patent Literature 1). This hormone also directly acts on the central nervous system to suppress the appetite. Thus, the hormone has a physiological function of inducing a feeling of fullness.
By focusing on the physiological effects of CCK, materials having a CCK secretion stimulating activity have been searched, and the uses of the materials have been developed. For example, Patent Literature 1 (Arginine-containing peptide having a cholecystokinin secretion-stimulating activity and food containing the peptide) discloses that a pepsin digestion product of soybean β-conglycinin promotes the CCK-secreting activity in rats to reduce the food intake and that the soybean β-conglycinin is used in a food intake-suppressing food. Non-Patent Literatures 2 and 3 ("Soybean β-Conglycinin Bromelain Hydrolysate Stimulates Cholecystokinin Secretion by Enteroendocrine STC-1 Cells to Suppress the Appetite of Rats under Meal-Feeding Conditions" and "Acute effect of soybean beta-conglycinin hydrolysate ingestion on appetite sensations in healthy humans") report on that a bromelain hydrolysate of soybean β-conglycinin having a CCK secretion-promoting action suppresses the appetite of rats and human beings. Non-Patent Literature 4 (Development of peptide regulating appetite by controlling a gastrointestinal hormone with high safety) reports on a food containing a bromelain digestion product or peptide of β-conglycinin.
Patent Literature 2 (Composition containing pork-derived peptide having a food intake-suppressing action) discloses a composition containing a peptide having a cholecystokinin secretion-stimulating activity or food intake-suppressing activity prepared by digesting pork or pork-derived protein with pepsin on the basis that the pig-derived peptide promotes CCK secretion and reduces the food intake of rats.
Patent Literature 3 (Pharmacological composition for suppressing appetite) discloses a pharmacological composition for suppressing appetite containing an ingredient showing a cholecystokinin secretion-stimulating action prepared from yeast. This ingredient is low in calorie and has high heat resistance and high enzymolysis resistance.
The list of patent literature and non-patent literature documents as described herein is as follows:


An electronics assembly for use in a vehicle is provided. The assembly comprises a heat sink, a dam coupled to the heat sink, the dam and the heat sink combining to form a reservoir, an electronic component positioned within the reservoir, and a thermally conductive layer conformally molded to the electronic component and disposed between the electronic component and the heat sink.

Electric and hybrid electric vehicles often use sources of high voltage such as battery packs or fuel cells that deliver direct current (DC) to drive vehicle motors, electric traction systems (ETS), and other vehicle systems. A power inverter is typically used to convert the source DC signal to an alternating current (AC) signal which is directed to, for example, an electric traction machine or other AC system. Because such systems often use a significant amount of power, many of the components within the inverter including integrated gate bipolar transistor (IGBT) modules and power diodes may generate considerable heat. Accordingly, other accompanying components within the inverter such as, for example, gate drive circuit boards are often exposed to elevated temperatures especially during periods of peak power demand.
Because the performance characteristics of many electronic components can be affected by high temperatures, power inverters generally include a cooling system to dissipate heat. Such a cooling system typically includes a heat sink having a large thermal mass that may assume the form of a manifold thermally coupled to the primary cooling system of the vehicle and configured to cool individual components. For example, the gate drive circuit board is typically thermally coupled to the surface of the heat sink through a pre-formed, resilient, thermal interfacing pad positioned between the board and the heat sink. The circuit board is then typically fastened to the heat sink against the resilience of the underlying pad to secure the board and improve thermal contact by compressing the pad. In this case, however, heat transfer may be hindered because of a lack of conformity between the pad and the often highly irregular surface of the board.
Accordingly, it is desirable to provide an electronics assembly for a vehicle having a thermal interface that provides improved heat transfer and vibration dampening to electronic components such as circuit boards. Further, it is also desirable if such an assembly reduces circuit board deflection and part count, and is simpler to fabricate. Furthermore, it is also desirable to provide methods for fabricating such an assembly. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.


The erasion level appending range of a file is instructed. According to this instruction, the erasion level is set. When this setting range does not agree with the cell unit of the current cell, the current cell is divided to set a sequence of divided cells. Playback management information of each of the divided cells and current cell is re-created, and erasion level information is appended to playback management information of the divided cell that belongs to the appending range.

In recent years, systems for playing back the contents of optical discs such as video CDs that record video data, audio data, and the like have been developed, and have prevailed for the purpose of playing back movie software titles, karaoke data, and the like.
Among such systems, a DVD (Digital Versatile Disc) standard that uses MPEG2 (Moving Picture Experts Group 2) international standards has been proposed.
This standard supports MPEG2 as a moving picture compression scheme, and AC-3 audio, MPEG audio, and the like as audio schemes. The standard is appended with sub-picture data for superimposed dialogs and menus obtained by compressing bitmap data, and control data (navigation data) for special playback control. Furthermore, this standard supports the UDF (Universal Disc Format) Bridge (a hybrid of UDF and ISO9660) to allow a computer to read data.
Also, optical discs such as a DVD-RAM and the like on which digital data can be written or rewritten have been developed. A function that allows one to easily edit the recorded contents is required of a digital video system using such DVD-RAM or the like.
However, a home-use digital video system which allows end-users to easily edit the recorded contents has not become available yet.


A cooking range with a cooking zone plate made of glass, glass ceramics or similar materials. A frame for the cooking zone plate serves as edge protection on the one hand and as closing for the upper edge of the plate. On the other hand, the cooking zone plate is bonded with the frame on the edge side.. According to the invention, the frame includes an attachment frame part and a visual frame part separated from the attachment frame part. The attachment frame is a standardized component that is connected with the lower plate edge. The visual frame serves as protection edge and upper closing. In this way a frame modular system can be put together for all applications in a simple, economical manner.

The invention relates generally to a cooking range with a cooking plate made of glass, glass ceramics or a similar material, and particularly to a framing means for framing the cooking plate. The framing means may have attachment means that are bonded with the edge of the plate, means of edge protection and lateral closure of the plate, and a cooking range casing that surrounds the plate at its bottom and has sides and a bottom.
Such a cooking range was made known from German patent DE 31 26 013 C2.
In the known case, the frame is designed in one piece. Seen from the side, it has a middle ridge on which, at the proper level, a flange is formed that can be bonded to the lower rim of the plate. This flange holds the plate, so to speak. The section of the frame projecting over this, i.e., the outer flange, protects the shock-sensitive edges of the plate, a necessity particularly with brittle glass or glass ceramic plates. Furthermore, this section of the frame forms the transition to the sill plate in the case of built-in cooking ranges or for outside covering in the case of upright stoves. In this instance, the part of the flange that is visible from the outside must meet aesthetic and hygienic requirements. The familiar cooking range also has a cooking range casing designed in one piece, which takes in the frame and which has heating elements and the like arranged on its bottom. To be able to be gain access to the inside of the cooking range for a repair, the frame with the plate bonded in place is attached on the cooking range casing via a detachable snap and screw connection and can be removed by lifting it upward.
Comparable one-piece frames with another detachable connection to the cooking range casing are also shown in German patents DE-U 86 24 136 and 77 18 108.
The known cooking ranges with one-piece frames have the disadvantage that a frame built for an upright stove cannot also be used as frame for a built-in stove and vice versa. For this reason, a new design of the frame is necessary for an upright stove as well as for a built-in stove, with additional, expensive production tools also needed.


Within an ATM node, a cell handling unit (CHU) receives incoming ATM cells from an ATM switch and provides outgoing ATM cells back to the ATM switch. The cell handling unit consults a combined or consolidated table to obtain ATM parameters (e.g., VCI) for use in headers of outgoing ATM cells. The combined table can be utilized both for ATM cells with AAL2 protocol and ATM cells of a second type AAL protocol. The second type AAL protocol is preferably AAL2 prime, which requires that AAL2 packets carried in the ATM cell payload be whole packets and that the ATM payload not have an AAL2-type start field. The combined table is structured to have plural intervals, including a first interval for AAL2 protocol connections and plural other intervals for the second type AAL protocol connections. Each row for the AAL2 protocol interval associates (1) a unique incoming VCI value; (2) an output link value; (3) an outgoing VCI value; and (4) an offset value. The offset value points to the one of the plural intervals for the second AAL protocol connection. Each of the rows for the table intervals for the second AAL protocol connections associates (1) an incoming VCI value; (2) a channel identifier (CID); (3) an output link value; and (4) an ATM parameter for use in an ATM header of an outgoing ATM cell.

1. Field of the Invention
The present invention pertains to communications systems, and particularly to communications systems which employ ATM technology.
2. Related Art and other Considerations
Asynchronous Transfer Mode (ATM) is becoming increasingly used in communication networks. ATM is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and have a fixed size.
As shown in FIG. 1, an ATM cell consists of 53 octets, five of which form a header and forty eight of which constitute a xe2x80x9cpayloadxe2x80x9d or information portion of the cell. The header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual path is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
Between termination points of an ATM network a plurality of nodes are typically situated, such as switching nodes having ports which are connected together by physical transmission paths or links. The switching nodes each typically have several functional parts, a primary of which is a switch core. The switch core essentially internal to the switch core are selectively controlled so that particular ports of the switch are connected together to allow a cells ultimately to travel from an ingress side of the switch to an egress side of the switch.
A protocol reference model has been developed for illustrating layering of ATM. The protocol reference model layers include (from lower to higher layers) a physical layer (including both a physical medium sublayer and a transmission convergence sublayer), an ATM layer, and an ATM adaptation layer (AAL), and higher layers. The basic purpose of the AAL layer is to isolate the higher layers from specific characteristics of tile ATM layer by mapping the higher-layer protocol data units (PDU) into the information field of the ATM cell and vise versa. There are several differing AAL types or categories, including AAL0, AAL1, AAL2, AAL3/4, and AAL5.
AAL2 is a standard defined by ITU recommendation I.363.2. An AAL2 packet is shown in FIG. 2 as comprising a three octet packet header, as well as a packet payload, The AAL2 packet header includes an eight bit channel identifier (CID), a six bit length indicator (LI), a five bit User-to-User indicator (UUI), and five bits of header error control (HEC). The AAL2 packet payload, which carries user data, can vary from one to forty-five octets
FIG. 3 shows how plural AAL2 packets can be inserted into a standard ATM cell. In particular, FIG. 3 shows a first ATM cell 201 and a second ATM cell 202. Each ATM cell 20 has a header 22 (e.g., cell 201 has header 221 and cell 202 has header 222). The payload of the ATM cells 20 begin with a start field 24 (e.g., cell 201 has start field 241 and cell 202 has start field 242). After each start field 24, the ATM cell payload contains AAL2 packets. For example, the payload of ATM cell 201 contains AAL2 packets 261 and 262 in their entirety, as well as a portion of AAL2 packet 263. The payload of c ell 202 contains the rest of AAL2 packet 263, and AAL2 packets 264 and 265 in their entirety. In addition, the payload of cell 202 has padding 28.
The start field 24, shown in FIG. 3A, facilitates one AAL2 packet bridging two ATM cells. Start field 24 includes a six bit offset field (OSF), a one bit sequence number (SN), and one parity bit (P). The six bit offset field (OSF) contains a value, represented by offset displacement 29 in FIG. 3, indicative of the octet in the payload whereat the first full AAL2 packet begins. For ATM cell 221, the value of the offset field (OSF) is one, since AAL2 packet starts just after start field 241. For ATM cell 222, the value of the offset field (OSF) is the sum of one (in view of start field 241) and the number of octets of AAL2 packet 263 protruding into cell 222.
AAL2 advantageously allows multiplexing of data from many users within a single ATM VCC. In such multiplexing scheme, each user""s data is carried in a separate AAL2 packet, but AAL2 packets of differing users are carried in the same ATM cells or cells borne on the same ATM VC. Thus, assuming each user has a different channel identifier (CID) value, as many as 248 user channels can be multiplexed onto one ATM VC. AAL2 thus allows more efficient utilization of low speed links than standard ATM while still maintaining low delay properties.
A problem with using AAL2 arises when terminating AAL2 channels at different nodes or different addresses in the same node. Since the individual AAL2 channels may be multiplexed into one ATM-VCC, it is not possible to direct the individual AAL2 channels (e.g., the AAL2 packets on which the channel data is carried) to different destinations using conventional ATM switches.
One approach for switching AAL2 packets is set forth by Mauger and Rosenberg, xe2x80x9cQoS Guarantees for Multimedia Services on TDMA-Based Satellite Networkxe2x80x9d, IEEE Communications Magazine July 1997). In that approach, fixed-cell ATM switches work in conjunction with separate variable-cell ATM switches for handling AAL2 packets.
Within an ATM node, a cell handling unit (CHU) receives incoming ATM cells from an ATM switch and provides outgoing ATM cells back to the ATM switch. Some of the incoming ATM cells can be of a first type AAL protocol (AAL2 protocol), while others of the incoming ATM cells are of a second type AAL protocol. The cell handling unit includes a demultiplexer function which demultiplexes an ATM cell with AAL2 protocol into outgoing ATM cells of the second type AAL protocol; as well as a multiplexer function which multiplexes ATM cells of the second type AAL protocol into an outgoing ATM cell with AAL2 protocol. In generating an outgoing ATM cell, a new ATM parameter (e.g., new VCI value) must be generated for the cell header.
The present invention provides a combined or consolidated table from which ATM parameters for use in headers of outgoing ATM cells can be determined. The table is consolidated in the sense that the table is structured and formatted so that it can be utilized for both incoming ATM cells with AAL2 protocol and ATM cells of the second type AAL protocol. The second type AAL protocol is preferably AAL2 prime, which requires that AAL2 packets carried in the ATM cell payload be whole packets and that the ATM payload not have an AAL2-type start field.
The combined table is structured to have plural intervals, including a first interval for AAL2 protocol connections and plural other intervals for the second type AAL protocol connections. Each interval is a set of rows, the rows also being referred to as subintervals. Each row for the AAL2 protocol interval (i.e., the first interval) is associated with (1) a unique incoming VCI value for its corresponding AAL2 protocol AAL connection, (2) an output link value; (3) an outgoing VCI value; and (4) an offset value. The offset value points to the one of the plural intervals for the second AAL type connection.
The combined table further has subintervals or rows for each of the plural intervals for the second AAL type connections. Each of the rows for the second AAL type connections has (1) an incoming VCI value; (2) a channel identifier (CID) for a particular one of the AAL2 connections; (3) an output link value; and (4) an ATM parameter for use in an ATM header of an outgoing ATM cell.
In a multiplexing operation, an incoming VCI value and incoming channel identifier (CID) value are ascertained from an incoming ATM cell having an AAL2 protocol. The incoming VCI value is used to locate an appropriate row in the AAL2 interval or portion of the table. From the appropriate AAL2 row an appropriate offset value is obtained. The appropriate offset value is then used to locate an appropriate one of the plural intervals for second type AAL protocol connections. Within the appropriate second AAL type protocol interval, an appropriate row of the interval is located by matching the incoming CID value with the CID values of the rows of the interval. From the thusly-determined appropriate row, an ATM parameter (e.g., outgoing VCI value) is obtained for use in an ATM header of the outgoing ATM cell.
In a demultiplexing operation, an incoming VCI value is ascertained from an incoming ATM cell. The plural intervals for the second type AAL protocol connections are searched to find and an appropriate row thereof which has its associated incoming VCI value matching the incoming VCI value of the incoming ATM cell. From the appropriate row an appropriate output link value is obtained. Then, the AAL2 interval of the table is searched to find an appropriate row thereof having an associated output link value which matches the appropriate output link value obtained from the appropriate row of the appropriate second type AAL protocol interval. From the appropriate row of the AAL2 portion of the table is obtained the associated ATM parameter (e.g., VCI value) for use in the header of the outgoing ATM cell.

Combined header parameter table for ATM node


A method for video playback includes displaying a video on a screen, detecting a split-screen request, pausing the video and displaying a split-screen including a static upper section, a static lower section and a middle section including at least one active icon. In an example embodiment, the middle section includes an action bar including a number of active icons providing actions such as playing a new video in a new window, hyperlinking to a website, interacting with social media, etc. In a further example embodiment, the display of the split-screen involves capturing a static image of a screen of the video that was paused and animating a split of the static image to display the action bar in the middle section of the split-screen.

Electronic commerce, often known as "e-commerce", includes advertising as well as the buying and selling of products or services over electronic systems such as the Internet. The amount of trade conducted electronically has grown immensely with the widespread adoption of Internet technology. One particularly explosive area of growth in e-commerce is in the field of advertising and, in particular, video advertising on the Internet.
Video advertising over the Internet is supported by many hardware platforms, sometimes referred to herein as "client" or "user" devices. For example, video advertising can be displayed in web browsers of computers. Video advertising is also increasingly being implemented on mobile devices such as smartphones and tablet computers. With such advertising, the video advertisement is typically "streamed" from a server to the client device over a network such as the Internet, a wireless telephone network, a private network, etc.
A popular form of video advertisement is referred to as an "in-stream ad." With this technology, a short video advertisement (e.g. 15-30 seconds long) is play before ("pre-roll"), during ("mid-roll") or after ("post-roll") streaming video content that a client has requested. Since in-stream ads are frequently used to monetize the video content the publisher is delivering they usually must be played until completion. This is particularly true with pre-roll in-stream ads. As a result, they are not interactive media and the brand interaction of such ads is limited. Furthermore, the pre-roll advertisement can sometimes have the negative effect of brand degradation if users are forced to passively view an entire advertisement before being able to view their requested video content.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.

Video playback with split-screen action bar functionality


An object is to directly detect the emptiness of a solvent cartridge being mounted. An emptiness detection unit body includes a light transmissive tube which constitutes part of internal piping of a printer body, a light emitter, and a light receiver. The light transmissive tube is composed of a transparent tube, typically, a glass tube or a fluororesin (PFA) tube. The light emitter and the light receiver are arranged to face the light transmissive tube. The light transmissive tube is filled with a solvent supplied from the solvent cartridge. On the other hand, the light transmissive tube is filled with gas when the solvent cartridge is empty. The emptiness of the solvent cartridge is detected by a change in the amount of light received by the light receiver associated with the change in the light transmissive tube.

1. Field of the Invention
The present invention relates to a continuous type ink jet recording apparatus which adjusts the viscosity of an ink liquid using a solvent supplied from a solvent cartridge, and more specifically to an ink jet recording apparatus having a function of detecting the emptiness of the solvent cartridge.
2. Description of Related Art
An ink jet recording apparatus is used for printing characters or graphics on the surface of a workpiece (JP 2007-190724 A). The ink jet recording apparatus is generally called "ink jet printer". The ink jet printer includes a head which is placed above a manufacturing line and a controller body which supplies ink to the head. The ink jet printer charges an ink liquid and forms the ink liquid into droplets, and deflects the ink droplets to thereby perform printing on the surface of a workpiece.
In the ink jet recording apparatus disclosed in JP 2007-190724 A, the ink liquid is continuously supplied to the head even when ink droplets are not printed on a workpiece and the supplied ink liquid is collected through a gutter as an ink receiver. That is, the ink jet recording apparatus disclosed in JP 2007-190724 A is a continuous type ink jet printer.
As a method for replenishing an ink jet recording apparatus with an ink or solvent, there are employed many methods in which a reserve tank is installed in an ink jet recording apparatus (JP 2007-190724 A). However, in the methods in which a reserve tank is installed in an ink jet recording apparatus, filling the reserve tank with ink may cause contamination of the surroundings of the reserve tank. In view of such a circumstance, an ink jet recording apparatus that employs a cartridge system using a cartridge which can be attached to and detached from the ink jet recording apparatus has come to be available (JP 2011-500353 W).
When the cartridge system is employed, there may be employed a system which maintains the internal pressure of a cartridge at atmospheric pressure when sucking out a liquid inside the cartridge by a pump, or a negative pressure system which sucks out a liquid from a cartridge in a sealed state. JP 2011-500353 W employs the latter system, that is, the system which sucks out a liquid from a cartridge in a sealed state. In the negative pressure system, the internal pressure of the cartridge becomes a negative pressure by sucking out the liquid from the cartridge.
When the cartridge system is employed, it is necessary to detect that a cartridge mounted therein has become empty in order to perform accurate cartridge replacement. In order to achieve this object, an ink jet printer disclosed in JP 2011-500353 W includes a pump which is placed inside a main body thereof, that is, a pump for sucking out a liquid inside a cartridge. A pressure sensor which is placed on a tube path between the pump and the cartridge detects whether the cartridge has become empty.
According to the description in JP 2011-500353 W, when the volume of the cartridge becomes almost zero, the pressure in the tube path rapidly decreases. It is possible to confirm that the cartridge has become empty using this phenomenon.
When employing, for example, the method disclosed in JP 2011-500353 W, that is, the method which measures the pressure in the tube path which communicates with the cartridge as means for confirming the emptiness of the cartridge, the pressure in the tube path and the remaining amount in the cartridge therefore do not necessarily correspond to each other because the method is an indirect method. A container for storing liquid, the container constituting the cartridge, is crushed by suction performed by the pump and the volume thereof is reduced (volume reduction). The degree of crushability has an individual difference between containers more or less. Further, the pressure in the tube path changes depending on the individual difference. This fact shows that although the method of JP 2011-500353 W is effective to confirm that the cartridge has become almost empty, it is virtually not possible to more accurately detect that the cartridge has actually become empty.

Cartridge type ink jet recording apparatus


In a method and arrangement for forming reception pulses, output signals of an upstream comparator which recognizes light pulses are used to evaluate a downstream arrangement and are newly formed and emitted as pulses. The aim is to produce a method and an associated circuit arrangement for forming reception pulses which represent a saving in energy, whereby said arrangement can be integrated into existing receiver systems, requires no external time base and can work with the signal of an upstream comparator. In a first step, an input signal delivered by an upstream comparator is delayed, whereupon a time reference is produced in a controlled manner and an output pulse begins to be formed in a controlled manner by means of the delayed input signal from the first step. The input signal level is examined once production of the time reference is completed. The examination refers back to the length of the received pulse, and the duration of the output impulse is adjusted according to the results of the examination.

The invention relates to a method and arrangement for forming reception pulses in a receiver operating according to the IrDA standard, wherein the output signals of an upstream comparator that recognizes light pulses are used for evaluation by a downstream arrangement, and re-formed and emitted as pulses.
In data transfer by means of infrared light according to the IrDA standard (Infrared Data Association) in the specification of FIR (Fast Infrared), for example, wherein the 4 PPM (four pulse position modulation) modulation type is used, post-processing steps must be done for the output pulses produced by a comparator. In this modulation type two data bits are consolidated to one data bit pair (DBP). A period of 500 ns, divided into four 125 ns time slices, is available for transferring a DBP. One position or one chip, which is represented by an optical pulse, is discretely allocated to each of the four possible 2-bit words. Thus the coding depends on the position of the single pulse within the 500 ns time period. Consequently it may happen that the fourth position of the code "n" is occupied and immediately following the first position of the code "n+1". In this case both single pulses merge into a double-wide [viz. double-duration] so-called double pulse. Due to the properties of this 4 PPM modulation type both single pulses with a 125 ns pulse duration and double-pulses with 250 ns pulse duration are transferred and made recognizable as such at the output of a circuit for post-processing of the pulses produced by the comparator at the digital output RxD of a receiver.
An amplifier built into the infrared receiver must have an appropriately large bandwidth in order satisfy these transfer requirements. In practice, due to the high power consumption in a correspondingly large bandwidth, a limited bandwidth is available whose value is defined by the requirements for transferring the single and the double pulses. Thus in the critical case, depending on the input current amplitude, there is an lengthening of the single pulses and a shortening of the double impulses within the transfer range.
A circuit for post-processing of the output signals of a comparator consists in the simplest case of a monoflop for forming the single pulse. In the case of transferring a double pulse a combinatorial lengthening of the single pulse supplied by the monoflop corresponding to the amplifier dynamics of said pulse. Thus, although the single pulse is newly produced, the double pulse is composed only from a produced single pulse and the pulse remnant dependent on and distorted by the amplifier dynamics.
Furthermore, for example as taught by U.S. Pat. No. 6,198,766 B1, more complex circuits for subsequent processing are known which define an ideal time pattern using an external time basis and synchronize the comparator pulses either in this pattern or even modify them adaptively.
The very simple and space-optimum solution of a single monoflop for forming the single pulses has the significant drawbacks that on the one hand excessively long single pulses with strongly varying pulse duration at the comparator output are stretched beyond the monoflop time by the logic required for the transfer of the double pulses at the output RxD of the subsequent processing circuit. On the other hand the double pulse itself is transferred only combinatorily and is not processed at all. Accordingly, at the RxD output only the direct and unstable pulse duration of the comparator appears at all times. Both effects can result, independently of each other, in a stalling of the data transfer according to the IrDA standard, if in certain dynamic areas the pulse durations no longer conform with the requirements imposed on minimum and/or maximum pulse duration requirement. On the other hand, the demand of transfer of the light pulses as faithfully as possible to the pulse via the amplifier compels greater amplifier bandwidth. This results on the one hand in high operating power and on the other hand, because of the low lower cut-off frequency, for example, large, area intensive coupling capacities.
Systems approaches with external synchronization require either an additional clock input or an integrated quartz oscillator that generates an adequate time base. For the jitter requirements of 20 ns given in the FIR specification to be maintained this solution requires sampling rates of at least 40 MHz which is equivalent also to the clock rate of the I/O circuit. Along with a circuit that is more complex and requires more space with this timing and its utilization there is also an interference source on the chip which is isolated from the sensitive amplifier complex by means of additional shielding schemes that also occupy considerable space.

Method and arrangement for forming reception pulses in an infrared receiver


A molecular detection device including a support member (36) and a plurality of molecular receptors (34) arranged at a plurality of sites of the support member (36). In a first aspect, the molecular receptors (34) are arranged in accordance with a mapping selected from the group consisting of a random mapping and a pseudorandom mapping. In a second aspect, data associated with the mapping is written to a member associated with the support member (36). In a third aspect, the molecular receptors (34) includes a first plurality of molecular receptors germane to an application and at least one molecular receptor extraneous to the application.

An increased effort has been directed toward developing chips for molecular detection. A typical molecular detection chip includes a substrate on which an array of recognition sites, binding sites, or hybridization sites is arranged. Each site has a respective molecular receptor which binds or hybridizes with a molecule having a predetermined structure.
A sample solution is applied to the molecular detection chip, and molecules in the sample bird or hybridize at one or more of the sites. The sites at which binding occurs are detected, and one or more molecular structures within the sample are subsequently deduced.
Of particular interest are DNA chips for sequencing and diagnostic applications. A DNA chip includes an array of binding sites each having single-stranded DNA probes or like synthetic probes for recognizing a respective DNA sequence. A sample of single-stranded DNA fragments, referred to as target DNA, is applied to the DNA chip. The DNA fragments attach to one or more of the probes. In sequencing applications, a sequence of nucleotide bases within the DNA fragment can be determined by detecting which probes have DNA fragments bound thereto. In diagnostic applications, a genomic sample from an individual is screened with respect to predetermined set of probes to determine if the individual has a genetically-inherited disease or a genetic predisposition to a disease.
The prospect of determining an individual's predisposition to disease based on his/her genome has led to warnings of a potential for genetic-based discrimination. For example, genetic information could be used to exclude high-risk individuals from health care either by denying health insurance coverage or by charging a prohibitive rate. The fear of discrimination may inhibit an individual from divulging his/her genetic status, even in light of the benefits of preventative measures and treatments which can be prescribed based on an early diagnosis of a genetic predisposition to a disease.
Accordingly, there is a need for a molecular detection devices and methods that provide increased security with respect to genetic information.

Molecular detection devices and methods of forming same


The invention is based on the principle that the antitheft device has a body of a hard material which cannot be easily cut through and which covers the points of connection of at least one rib with the steering wheel rim and the steering wheel hub. As a result, even though the uncovered rim portion or uncovered ribs are cut through, the device still preserves its antitheft functions, and the vehicle remain non-steerable. The body of the device has a U-shaped cross-sectional configuration so that the device can be hooked up over the wheel rim and then locked to the rim by a lock. The device has a side stopper which is constantly shifted into the space between the ribs and a second stopper that rests onto the dashboard of the vehicle, so that in an attempt to turn the steering wheel with respect to the device, the movement of the steering wheel device is limited due to contact of the steering wheel ribs with the side stopper of the device and due to contact of the foldable stopper of the device with the dashboard of the vehicle.

Nowadays in United States alone a vehicle is stolen every 19 seconds. Losses from car theft are costing $8 billion a year nationally. Autotheft is a growing problem, affecting both urban and rural communities, as well as all vehicle makes and models.
Heretofore devices of various types have been proposed and introduced in market for preventing the car theft. These devices roughly can be classified as alarms that produces a sound signal, ignition cut-off switches that prevents the car from being started unless the switch is tripped, and steering wheel locking bars that prevent the wheel from turning.
The last group of devices find a very wide application because of simplicity of the use and low cost of the device itself.
One such steering wheel locking bar-type device is produced by Winner International Corporation, USA under the trademark "Club". Unfortunately, none of these devices can guarantee that the vehicle will not be stolen. This is because, even though the auxiliary bars of the antitheft device is difficult to cut, the steering wheel itself is a weak link in the protection system. In other words, while many of the known steering wheel locking bars are relatively indestructible, the steering wheel is not. As a result, an automobile to be protected is actually subject to theft by the simple expedient of cutting through the plastic covered steering wheel rim and removing the protection bar via the cut. The automobile is then steerable and the steering wheel may actually have suffered only relatively minor damage and may be used as it is or with a piece of tape applied over the cut in order to hold the adjacent cut edges of the rim in circular alignment.
The above problem was completely solved by means of an antitheft locking device disclosed by the applicant in his earlier patent application Ser. No. 519715 filed on Aug. 28, 1995 for which a decision to grant a patent was made.
This antitheft locking device has a steering wheel and an engaging member with an end wall covering the steering wheel over its part that includes at least two ribs of the steering wheel. A peripheral wall of the device extends over at least a part of the outer periphery of the steering wheel rim. The device also has a pair of spaced stops protruding from the end wall in the direction perpendicular to the plane of the steering wheel and engageable with the lateral surface ribs. A stop member which protrudes from the periphery of the rim engaging portion is engageable with the dashboard of the vehicle or with any other stationary part of the vehicle body for preventing rotation of the steering wheel. The device is locked in a fixed position by means of a special locking mechanism.
A main distinction of the aforementioned earlier Applicant's device consists in that the durable metal rim-engaging portion of the device which is hard to cut by conventional tools covers a part of the rim periphery and at least two ribs over the entire length of these ribs including the points of connection of the ribs to the rim and steering wheel hub. This means, that even though a thief may cut the portions of the rim not protected by the device, the vehicle still remain non-drivable. This because the device still cannot be removed from the remaining portion of the steering wheel and thus the protection function of the device remains intact.
Although the aforementioned device is efficient and reliable in operation, it is heavier, more expensive than the conventional bar-type antitheft devices, and is inconvenient for storage and handling because of large dimensions and heavy weight.