An air cleaner for an internal combustion engine includes a body having a chamber space, an air inlet pipe connected to the body for introducing air into the chamber space, a drain cock formed on a bottom surface of the body for collecting particles and moisture present in the introduced air, and a drain valve mounted to the drain cock for discharging the particles and moisture. The air inlet pipe is integrally formed with the body and is not inserted in the body.

(a) Field of the Invention
The present invention relates to an air cleaner for an internal combustion engine, and in particular, to an improved air cleaner that enhances engine performance by integrally forming an air cleaner body and an air inlet pipe.
(b) Description of the Related Art
An air cleaner is needed to protect an engine and fuel system by removing dirt, abrasive particles and other foreign substances, as well as moisture present in the air before the air is supplied to the engine and fuel system. The air cleaner may be mounted to a carburetor air horn, fuel injection throttle body, or intake manifold by an air transfer duct.
FIG. 3 shows a prior art air cleaner. All incoming air is introduced into a cleaning chamber 104 defined by a housing 101 through an air inlet pipe 102 such that the air undergoes an initial cleaning process. That is, relatively large particles and moisture present in the air drop downwardly by the gravity exerted on these substances. The air having gone through the initial cleaning process then passes through the air filter before entering an engine such that the air undergoes a second cleaning process. The large particles and moisture that drop after entering the cleaning chamber 104 collect in a drain outlet 106 formed on a bottom surface of the housing 101 to be discharged through a drain valve 110 mounted to the drain outlet 106 by means of a clamp. The air inlet pipe 102 is connected to the housing 101 by means of a pop-riveting process in a state inserted into the cleaning chamber 104.
In this air cleaner, however, the air inlet pipe 102 and the cleaning chamber 104 are separately manufactured before being connected to each other. Accordingly, it is difficult to completely seal the air inlet pipe 102. Also, the air flow in the cleaning chamber 104 is not smooth because the air inlet pipe 102 is inserted into the cleaning chamber 104.
The present invention has been made in an effort to solve the above problems of the prior art.
It is an object of the present invention to provide an improved air cleaner capable of completely sealing an air inlet pipe and smoothing an air flow in a cleaning chamber by integrally forming the air inlet pipe and an air cleaner body.
To achieve the above object, the air cleaner for an internal combustion engine comprises a body having a chamber space, an air inlet pipe connected to the body for introducing air into the chamber space, a drain cock formed on a bottom surface of the body for collecting particles and moisture present in the introduced air, and a drain valve mounted to the drain cock for discharging the particles and moisture. The air inlet pipe is integrally formed with the body and is not inserted in the body.

Air cleaner for internal combustion engine with internally formed air inlet pipe


A tandem color laser printer, in which processing units can be smoothly attached to and detached from its casing, is provided while an adequate accuracy of exposure to photosensitive drums is maintained. In the color laser printer, scanning units are fixed to the printer casing. The processing units and the scanning units are alternately aligned and overlapped. A top cover is provided to a side opposite to a transfer position where the photosensitive drums contact a conveyor belt so as to freely open and close with respect to the printer casing. With this structure, the adequate accuracy of exposure by the scanning units can be maintained. The processing units can be attached to and detached from the printer casing via an upper opening of the printer casing defined by the opened top cover. Thus, the processing units can be smoothly attached to and detached from the printer casing without being interfered by the scanning units.

1. Field of Invention
The invention relates to an image forming apparatus such as a color laser printer.
2. Description of Related Art
As an electrophotographic color laser printer, there exists a so-called tandem color laser printer that includes a plurality of processing units, each of which has a developing agent hopper, a developing roller and a photosensitive drum, with respect to toner colors of yellow, magenta, cyan, and black.
In the above tandem color laser printer, toner images of the respective colors are formed on the respective photosensitive drums at almost the same instant by which toner particles stored in the developing agent hopper are supplied onto the photosensitive drum by the developing roller in each of the processing units. Therefore, a color image can be formed at a speed that is almost the same as an image forming speed of a monochrome laser printer.
As the above tandem color laser printer, Japanese Laid-Open Patent Publication No. 9-274423 discloses a color laser printer that is structured as described below. In each processing unit of the color laser printer, a photosensitive drum is disposed opposite to a conveyor belt for conveying a sheet. A developing roller is disposed on one side of the photosensitive drum. A recording head, which exposes the photosensitive drum to light in order to form an electrostatic latent image thereon, is provided opposite to the conveyor belt while sandwiching the photosensitive drum therebetween.

Image forming apparatus with processing unit that can be removed from the image forming apparatus without removing exposing devices


Skin care compositions, such as creams and lotions, wherein improved rub-off resistance is attained by including an effective amount of a copolymer comprising:. a) 10-75% by wt. of a C.sub.1 to C.sub.18 alkyl acrylate/methacrylate, PA0 b) 10-70% by wt. of C.sub.1 to C.sub.18 N-substituted alkyl acrylamide, and PA0 c) 5-40% by wt. of unsaturated carboxylic acid having 3 to 5 carbon atoms.

This invention is directed to skin care compositions for application to the skin wherein improved rub-off resistance is attained.
The use of skin care products, often described as cosmetic or health care products, is a large and continuously growing consumer market. These products which include creams and lotions as well as various powders, sprays and other topical skin products must satisfy a number of different physical and chemical properties while imparting one or more attributes of beauty, health and comfort. Some of the properties that skin care products are concerned with include stability, compatibility, insensitivity (non-irritating) to skin, ease of application, aesthetics or appearance, toxicological and other health and safety considerations, effectiveness, fragrance or odor, moisturization and water-resistance. In view of the varying needs and types of application, it is easy to understand why many similar products exist and why no one product can meet all of the different requirements.
One area of interest for many skin care products is the ability of the product to resist physical rub-off or prevent physical removal of the active ingredients from the skin thus obtaining extended effectiveness. While many of these products are directly or indirectly concerned with the property of rub-off resistance, there still is the need to provide skin care compositions which, while satisfying the many chemical and physical needs, have significantly improved rub-off resistance.

Skin care compositions with improved rub-off resistance

National Starch and Chemical Investment Holding Corporation


There are provided systems and methods for an artificial intelligence (AI) orchestration layer to facilitate migrations between different AI platforms. A service provider may provide AI portability functions through an orchestration layer that connects different AI services and platforms. The orchestration layer may be used to monitor user interactions with a first AI platform that request AI predictive services and outputs. Using these monitored interactions, the service provider may build and train a simulated AI model that attempts to mirror or replicate the AI model trained for the user on the first AI platform. Thereafter, when the user begins use of a second AI platform that includes the same or similar functionalities to the first AI platform, the service provider may utilize the orchestration layer to assist in training an AI model on the second AI platform based on the previously trained AI model on the first AI platform.

Service providers may provide artificial intelligence (AI) systems and AI models trained for a particular user over time based on training data provided to the AI system. For example, a particular AI platform may be associated with providing natural language processing, automating chat assistance and responses, processing search queries through search engines, performing text and/or image processing and recognition, automating device and/or vehicle operations, and the like. As a user uses the AI system over time, the AI system may become more accurate in making predictions and recommendations or automating operations based on the user's input. For example, a machine learning (ML) and/or neural network system may retrain weights, attributes, and classifiers as the model becomes more sophisticated and has a larger amount of training data for a user. However, when the user moves to a new AI platform and system, the system is required to relearn the specific user's behavior, which leads to less precise performance prior to receiving enough training data. Thus, the AI platform may make incorrect or inaccurate decisions and require the user to go through lengthy input processes to provide sufficient training data to adequately train the AI platform to the user.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures, wherein showings therein are for purposes of illustrating embodiments of the present disclosure and not for purposes of limiting the same.

Artificial intelligence orchestration layer to facilitate migrations between different artificial intelligence platforms


The present invention provides improved tests for the detection of methicillin-resistant Staphylococcus aureus. The tests are particularly useful for eliminating false positive results due to the presence of a mixed bacterial population in patient samples.

Methicillin-resistant Staphylococcus aureus (MRSA) is a major nosocomial but also community acquired pathogen that can cause serious infections such as surgical wound infections, pneumonia, endocarditis and septicemia. Resistance to methicillin is due to the presence of the mecA gene that encodes a modified Penicillin-Binding protein, PBP2a or PBP2′, with reduced affinity for B-lactam drugs. The mecA gene is carried by a cassette named the SCCmec (Staphylococcal Cassette Chromosome mec; Ito et al., 2001, Antimicrob. Agents Chemother. 45(5):1323-1336; Hiramatsu, et al., 2001, Trends Microbiol. October; 9(10):486-93), a mobile element that can be incorporated into the chromosome of S. aureus and other coagulase negative Staphylococci, mainly S. epidermidis and S. haemolyticus. SCCmec is characterized by the presence of terminal inverted and direct repeats, a set of site-specific recombinase genes (ccrA and ccrB), and the mecA gene complex (Ito et al., 1999, Antimicrob. Agents Chemother. 43:1449-1458; Katayama et al., 2000, Antimicrob. Agents Chemother. 44:1549-1555). The site of insertion of this mecA gene cassette SCCmec into the Staphylococcus aureus genome is known and the sequence conserved (Ito et al., 2001, Antimicrob. Agents Chemother. 45:1323-1336). After insertion into the S. aureus chromosome, the SCCmec has a left extremity junction region and a right extremity junction region (see FIG. 1), where the SCCmec sequence is contiguous with the S. aureus chromosomal sequence. The nucleotide sequence of the regions surrounding the left and right boundaries of SCCmec DNA (i.e. attL and attR, respectively), as well as those of the regions around the SCCmec DNA integration site (i.e., attBscc, the bacterial chromosome attachment site for SCCmec DNA), have previously been analyzed. Sequence analysis of the integration sites revealed that attBscc is located at the 3′ end of a novel open reading frame (ORF), orfX. orfX encodes a putative 159-amino acid polypeptide that exhibits sequence homology with some previously identified polypeptides of unknown function (Ito et al., 1999, Antimicrob. Agents Chemother. 43:1449-1458). Organization of the mecA region of SCCmec has additionally been studied (Oliveira, D. C., et al., 2000, Antimicrob. Agents Chemother. 44(7):1906-1910).
MRSA can be carried by healthy people without causing any disease but these healthy carriers, when entering the hospital, can contaminate hospitalized patients. Additionally, a patient can contaminate himself, e.g., if one undergoes surgery, the risk of infection is increased. MRSA healthy carriers constitute a reservoir of MRSA and screening of these carriers must be performed to eradicate the strains by local decontamination. MRSA screening is now recognized as a major tool to reduce the prevalence of MRSA strains in the world. Typically, in an MRSA assay in a patient, a nasal swab is taken from the patient and cultured repeatedly, to determine if an MRSA strain is present. The need to culture could be obviated by an assay for identifying MRSA directly from a nasal swab. Culture identification methods typically require minimally 24 hours, and more typically 72 hours, to obtain results. New chromogenic media (having substrate(s) within the media and, typically, antibiotic (e.g., cefoxitin) to select methicillin-resistant strains) can potentially restrict this time to result to a 24-48 hour time period. However, in the case of MRSA infection, results are needed in a matter of hours, since the patient should be isolated until results are obtained. Therefore, a reliable molecular MRSA test which can provide results in a matter of 2-4 hours is highly desirable.
Amplification is a well known art, and various methods have been developed, including transcription-based amplification such as transcription-mediated amplification (TMA; U.S. Pat. Nos. 5,766,849 5,399,491; 5,480,784; 5,766,849; and 5,654,142) and nucleic acid sequence-based amplification (NASBA; 5,130,238; 5,409,818; 5,654,142; and 6,312,928), and cycling nucleic acid amplification technologies (thermocycling) such as polymerase chain reaction (PCR; U.S. Pat. Nos. 4,683,195; 4,965,188; 4,683,202) and ligase chain reaction (LCR; U.S. Pat. No. 5,792,607). Known amplification methods also include strand displacement amplification (SDA), self-sustained sequence replication (3SR), Q-β replicase, and cascade rolling circle amplification (CRCA).
Detection methods utilizing nucleic acids are also well known in the art. Nucleic acids are often labeled for various detection purposes. For example, methods described in U.S. Pat. No. 4,486,539 (Kourlisky); U.S. Pat. No. 4,411,955 (Ward); U.S. Pat. No. 4,882,269 (Schneider) and U.S. Pat. No. 4,213,893 (Carrico), illustrate preparation of labeled detection probes for detecting specific nucleic acid sequences. Probe designs for different detection methods, such as target-capture, HPA, TAQman, molecular beacons and sandwich hybridization have also been described (e.g., U.S. Pat. No. 4,486,539, and U.S. Pat. Nos. 4,751,177; 5,210,015; 5,487,972; 5,804,375; 5,994,076). Nucleic acid hybridization techniques and conditions are known to the skilled artisan and have been described for example, in Sambrook et al. Molecular Cloning A Laboratory Manual, 2nd Ed. Cold Spring Lab. Press, December 1989; U.S. Pat. No. 4,563,419 (Ranki) and U.S. Pat. No. 4,851,330 (Kohne) and in Dunn, et al., Cell 12, pp. 23-26 (1978) among many other publications. Probe designs for different detection methods are also known, such as target-capture, HPA, TaqMan, molecular beacons and sandwich hybridization (e.g., U.S. Pat. No. 4,486,539, and U.S. Pat. Nos. 4,751,177; 5,210,015; 5,487,972; 5,804,375; 5,994,076).
Earlier molecular methods developed to detect and identify MRSA based on the detection of the mecA gene and S. aureus-specific chromosomal sequences have been described. (Saito et al., 1995, J. Clin. Microbiol. 33:2498-2500; Ubukata et al., 1992, J. Clin. Microbial. 30:1728-1733; Murakami et al., 1991, J. Clin. Microbiol, 29:2240-2244; Hiramatsu et al., 1992, Microbial. Immunol. 36:445-453). However, positive results for the presence in a sample of both mecA gene and S. aureus chromosomal sequences cannot guarantee MRSA is present, since, for example, in tests based on the detection of mecA and S. aureus specific marker, false positives can be observed in the presence of MSSA and methicillin resistant coagulase negative Staphylococcus that possess the mecA gene. Furthermore, in tests based on the detection of the cassette junction only, false positives have been observed with methicillin-susceptible S. aureus isolates containing a small fragment of the right extremity of the SCCmec (see Rupp, J. et al., J. Clin. Microbiol. 44(6): 2317 (2006)). Additionally, Ramakrishnan and Riccelli describe a method for detecting MRSA utilizing oligonucleotide probes having sequences that are complementary to regions near the left junction of the SCCmec cassette insertion site, including part of the SCCmec cassette sequence and part of the S. aureus sequence in the region of insertion (the left extremity junction region) (U.S. patent publication No. US20060057613).
However, previous attempts to determine MRSA by molecular methods have had difficulties with false positive results. Such results have been postulated to be the result of any of the presence of a mixed population in swabs, the presence in an MSSA of a residual SCCmec right extremity fragment following the deletion of the mecA gene and/or non-specific amplification. To date, two concepts for determining resistance to methicillin carried specifically by S. aureus have been published:
the SCCmec right extremity junction amplification concept (Hiramatsu et al. WO97/31125; EP 0 887 424; U.S. Pat. No. 6,156,507; and further, Huletsky and Rossbach WO02/099034 (2002); Huletsky et al. J. Clin. Microbiol. 42(5): 1875-1884 (2004))
the immuno-enrichment concept described by François and co-workers (François, P et al. J. Clin. Microbiol. 41(1):254-260 (2003); WO02/082086), in which the immuno-enrichment is followed by amplification of three markers (mecA gene, S. aureus-specific marker, and S. epidermidis-specific marker).
The SCCmec right extremity junction concept is based on the amplification of a region covering the right extremity junction region of the SCCmec integration site. The principle is the following: the SCCmec cassette always integrates the S. aureus chromosome upstream of a S. aureus specific open reading frame called orfX; the PCR assay combines multiple forward primers located on the right part of the cassette, one reverse primer and a beacon probe, both located in the S. aureus chromosomal orfX, i.e., downstream of the right extremity junction of SCCmec with orfX ("right extremity junction region" of orfX). Hiramatsu et al, describe a test with two forward primers in the right extremity junction region of the cassette to amplify the main SCCmec types described at that time (one primer for SCCmec types I and II and a second primer for type III). Huletsky et al. set forth that several MRSA strains were not detected if only the two forward primers described by Hiramatsu were used, and they determined new types of cassettes named as MREJ types having sequence variations in the right part of the SCCmec cassette. A commercially available (Infectio Diagnostics Inc.) test combines (refer to FIG. 1) five forward primers located in the right part of the cassette (one primer was designed for the detection of MREJ types i and ii and the four others for the MREJ types iii, iv, v and vii), one reverse primer located in the orfX, and three generic beacons covering the same portion of the orfX region and required to identify the orfX variants identified. This test is performed in real-time PCR. However, the specificity of this test as reported (Huletsky et al. 2004) shows that 4.6% of MSSA (26 out of 569 tested) were misidentified. False-positive result has also been reported with another commercial test using a single-locus (right extremity SCCmec cassette-orfX junction) PCR assay (Rupp, J, et al., J. Clin. Microbiol. (44)6: 2317 (2006)).
Thus false positives remain an issue, and there is a strong need for an improved test for MRSA to reduce false positive results obtained with current tests. The challenge for such a test is that, due to the presence of a mixed population in nasal swabs, the following mixtures can be present: one or more of (1) MRSA, (2) methicillin sensitive coagulase-negative Staphylococci (e.g., methicillin sensitive Staphylococcus epidermidis (MSSE)), (3) methicillin sensitive Staphylococcus aureus (MSSA), and (4) methicillin resistant coagulase-negative Staphylococci (MR-CNS) (mainly methicillin resistant Staphylococcus epidermidis (MRSE)). Furthermore, there has been report of clinical MSSA isolates retaining SCCmec elements without the mecA gene. (Donnio, P.-Y., et al., J Clin Microbiol. 2005 August; 43(8): 4191-4193). Because only the presence of a MRSA will lead to decontamination of the carrier, the test must ensure that resistance to methicillin is carried by S. aureus and not by S. epidermidis (or coagulase (−) Staphylococcus strain). Thus, also, amplification and detection of the mecA gene (associated or not with a S. aureus specific marker) directly on the mixed population present on the swabs is not appropriate; indeed in both situations (MRSA+MSSE or MSSA+MRSE), both markers (mecA and S. aureus specific marker) will be detected whereas only the first situation with an MRSA is desired to be specifically detected by the clinician. The present invention addresses primary sources of MRSA false positives and thus provides a much-needed, improved test to detect MRSA that has not been addressed by currently available tests.


A test apparatus for testing circuitized substrates such as PCB test coupons for thru-hole failure in which the substrate may be cooled to a temperature less than the ambient temperature surrounding the test apparatus housing in which the testing is accomplished. A method of testing substrates is also provided.

Today's miniaturization requirements for organic circuitized substrates, including multilayered printed circuit boards (PCBs), laminate chip carriers, and the like, require the formation of multiple circuits in a minimum volume or space. These circuits typically comprise a stack of electrically conductive copper or copper alloy layers of signal, ground and/or power planes (lines) separated from each other by a layer of organic dielectric material, typically fiber-glass reinforce resin material known in the art commonly as "FR4." Selected lines or pads of one conductive layer are often in electrical contact with selected lines and/or pads of other conductive layers using plated holes passing through the dielectric layers. The plated holes are often referred to as "buried vias" if internally located, "blind vias" if extending a predetermined depth within the board from an external surface, or "plated-thru-holes" (PTHs) if extending substantially through the board's full thickness. By the term "thru-hole" as used herein is meant to include all three types of such substrate openings.
Before placing a given circuitized substrate through the component assembly operation, it is desirable to test the substrate, including the electrical interconnection integrity thereof, to determine whether it is able to withstand the thermal/mechanical stresses experienced during the actual manufacturing assembly process and the product's end use environment. There are presently a number of accelerated stress test methods by which substrates are tested, with each test generally designed to simulate, usually in an accelerated manner, a particular stress that would cause deterioration resulting during the assembly and natural end use conditions of the substrate. In general, these accelerated stress tests involve some element of heat, humidity, or cycling between temperature extremes, and accordingly, will artificially reproduce and hasten inherent failure modes within the tested substrate. One common type of such stress tests is the accelerated thermal cycle, also referred to as "ATC", in which the substrate is exposed to multiple cycles of hot and cold extremes. ATC tests have the effect of mechanically straining the layers of the substrate and the thru-hole interconnections (also referred to simply as interconnects) by means of repeated cycles of thermal expansion and contraction, such as occurs during assembly cycles, product on-off cycles, and outdoor environmental temperature changes. Accordingly, in ATC tests, latent defects in the board will be revealed as the cyclic stressing mechanically exercises any weak or defective element to failure. When such ATC fatigue cycling is performed on an accelerated basis, relative to what is normally experienced in manufacturing assembly and in the field, reliability predictions relating to the substrate can be derived from the test.
Various methods of performing accelerated thermal cycle tests involve the use of a specific test "coupon", which is typically a smaller substrate (e.g., a small PCB) which can be manufactured in replicate on its own test vehicle panel, or can be manufactured concurrently on a larger product PCB, but solely for test purposes. Test coupons that are manufactured as an integral part of the actual product substrate are therefore subject to the same manufacturing conditions and processes as the larger substrate (e.g., PCB) with which the coupons are associated. Therefore, the quality of a given test coupon can be a reliable indication of the quality of its associated, larger substrate.
One ATC thermal test procedure using test coupons involves thermally cycling the test coupon by repeated exposure to hot and cold air to both heat and cool the coupon. This particular approach has been endorsed as the benchmark standard by the Institute for Interconnecting and Packaging Electronic Circuits ("IPC"). The industry standard method has been published in Mil-Standard 202F, Method 107G (also referred to in the industry simply as "Mil-T"). Although Mil-T cycling is presently sanctioned by IPC, there are a number of known drawbacks to this approach, particularly for PCB's. For example, a complete test of a given coupon may take as long as forty days for the coupon to be processed through the one hundred to one thousand cycles necessary to simulate expected life usage. Further, the operation of a Mil-T chamber can be expensive insofar as the chilled portion of the chamber typically relies upon liquid nitrogen, which is costly to ship, store, and use, and which presents certain environmental concerns. Chamber testing is further limited by the maximum high temperature, which is typically 175C, thus not allowing direct evaluation of assembly temperature cycles from assembly, which are typically at least 220C.
Variations on air-to-air chamber testing have also been developed specifically for small test coupons to increase the rate of temperature cycling, and thus decrease the total test time. One such test unit is referred to as "HATS", or "Highly Accelerated Test System", one known company providing such a system under this name being Integrated Reliability Test Systems, Inc., of Anaheim, Calif. The HATS system is capable of cycling coupons between −60 to 160 degrees C. and achieves faster cycling than conventional chambers due to more efficient exchange between hot and cold air, though the relatively low efficiency of heat transfer in air still limits the actual rate of coupon cycling. One publication listed 10.6 minute cycles (about 6 cycles per hour) as the cycle rate for a −40 to 145 degrees C. test. As with other chamber cycle tests, a maximum high temperature of 160 degrees C. limits the range of cycling possible, especially to represent assembly reflow temperatures. The inability to stress coupons with a reflow cycle with HATS, or other air to air chamber tests, has at least two consequences. First, direct comparisons of cycle to fail data between cold cycling and reflow cycling on the same coupon design is not possible. Second, in the common situation where some number of reflow cycles is required as preconditioning prior to a cold cycle stress test, those reflow cycles must be performed in a separate reflow oven.
Other substrate testing approaches have also been developed. Wet thermal shock is one, in which substrates are cyclically immersed in cold and hot liquids. This approach is fast due to the increased efficiency of heat transfer in the liquid. However, drawbacks of the wet thermal shock are that the cycle is uncontrolled during the hot and cold immersions, so that rate of change is a function of sample mass. Accordingly, results are sometimes not repeatable. Further, wet thermal shock does not facilitate continuous electrical monitoring during the cycling, and, as with chamber cycling, is also limited to a high temperature of less than 175 degrees C. Another method heats and cools the test coupon by exposing it to a fluidized sand bath. This method is awkward to use and maintain, and is typically limited to a low temperature of 50 degrees C. Yet another method is referred to as the "Power Cycling Technique" ("PCT"), or, more recently, as "Current Induced Thermal Cycling". Through this method, direct current (DC) is passed through the coupon, which causes the coupon to heat up, so that the substrate is thermally stressed. A variation of this testing procedure is referred to as an "Interconnect Stress Test" (IST), one known company referring to such testing by this name being Digital Equipment Corporation of Maynard, Mass. Current Induced Thermal Cycle methods can achieve cycle rates as fast as 10 to 30 cycles per hour because the heat is generated internally within the coupon and therefore is not dependent on heat transfer through an external medium such as air or liquid, at least for the heat up part of the cycle. Temperatures up to and above assembly reflow conditions are also easily attained.
As defined herein, the present invention involves the use of a test coupon which is subjected to thermal testing through the application of DC current to the coupon to raise and lower its temperature to the extent that the thru-holes and the interconnects thereof (e.g., between the thru-hole and the adjacent conductor lines, islands or planes) are sufficiently thermally stressed to thereby enable the tester to determine if said thru-holes and associated connecting structures (e.g., adjacent "lands") will successfully withstand the same conditions which corresponding larger substrates will be subjected to. It has been found that a main cause of thru-hole failure may be traced to significant differences in thermal expansion between the copper or other metal plating which lines the thru-hole and the surrounding substrate dielectric material (e.g., the aforementioned "FR4" material), which have significantly different coefficients of thermal expansion. When the differential expansion causes strain that exceeds the strength of the copper thru-hole plated material, a rupture intermediate the ends of the thru-hole structure may develop due to the thermal stresses generated. This undesirable occurrence may result in one or more open circuits or intermittent contacts which in turn may lead to failure of the substrate and any system in which it is utilized.
A particular problem associated with such DC voltage thermal testing is the inability to satisfactorily test each coupon across as wide temperature range to which the associated larger substrate will be eventually exposed. Present current induced thermal testing typically uses ambient temperature as the coolest temperature surrounding the test coupon, allowing the current applied through the test coupon to raise the coupon to a predetermined elevated higher temperature. Because many substrates may be required to operate at significantly lower temperatures as well as at much higher temperatures for the lowest operating temperature, testing coupons at ranges where ambient temperature is the only "low" temperature is limited. The present invention overcomes this limitation and is considered a significant advancement in the art. The following patents, all of which are incorporated herein by reference, represent various structures and methods used in testing coupons and the like.
In U.S. Pat. No. 6,521,841 (Kawaguchi), there is described a test coupon used to evaluate characteristics of multi-layer printed circuit boards. The coupon includes a multi-layer substrate which has at least first and second wiring layers. The first and second wiring layers are configured to correspond to a tested wiring layer and another wiring layer of the multi-layer printed circuit boards, respectively. Each of first and second thru-hole groups has a plurality of thru-holes which pass through the multi-layer substrate and which are arranged in an arranging direction. First and second conductor patterns provided on the first and second wiring layers, respectively, extend substantially along the arranging direction
In U.S. Pat. No. 5,701,667 (Birch et al), there is described an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined, the system stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This patent also describes the test coupon, which is designed to allegedly uniformly dissipate the heat created during the stress cycling. The above system is also described in U.S. Pat. No. 5,392,219 (Birch et al), a divisional of U.S. Pat. No. 5,701,667.
In U.S. Pat. No. 5,325,068 (Rauf), the electrical resistance of specimens formed on test coupons is measured when a test voltage applied to each specimen yields a leakage current. An operational amplifier having very high impedance inputs receives the leakage current signal and generates an output voltage that is low in magnitude and varies in the leakage current. The test voltage is applied to a plurality of specimens and leakage current from each specimen is simultaneously converted by operational amplifiers whose low impedance outputs are applied through switches in a sequential fashion to an analog to digital converter whose output is fed to a central processing unit wherein the leakage current is computed in terms of the resistance of the electrical insulation under examination.
In U.S. Pat. No. 5,198,756 (Jenkins et al), there is described a wiring test system in which test probes are oriented to engage contact points on a production circuit board. The system includes a wiring integrity verification plate comprising, in combination, a thin insulative base plate, multiple contact pads and leads attached to the plate. Each of the leads extends between and interconnects two of the contact pads, whereby multiple circuit sections are formed on the board. Each circuit section includes two pads interconnected by a lead, these two pads located so as to be contacted by the probes of the wiring test system to provide an electrical continuity test.
In U.S. Pat. No. 5,172,063 (Munikoto et al), the reliability of conductive circuitry of a printed circuit board and particularly the integrity of the conductive barrels of the board's through-holes is tested by cyclically passing a current through a plurality of interconnected barrels. The current is sufficient to resistively heat the conductive barrels to a temperature at which the glass epoxy substrate adjacent each barrel reaches a transition temperature at which the glass epoxy changes state from a solid to a semi-solid. After sufficiently heating the glass epoxy, it is allowed to cool to ambient temperature. This cycle is repeated for a predetermined number of cycles and the resistance of the barrels is measured after each cycle. A measured resistance that exceeds a predetermined value indicates that one or more defects are present in the interconnected barrels.
U.S. Pat. No. 4,510,446 (Braun et al), there is described a test coupons having predetermined respective test patterns, formed in a multilayer printed circuit board simultaneously with the fabrication of the latter. The test coupons are probed with conventional electrical instruments to provide information as to the occurrence of a misregistration of any given subsurface printed plane or trace, whether or not the misregistration exceeds a specified limit, and if desired, a measure of the degree of misregistration. The foregoing is allegedly accomplished in a timely manner without the need for cross-sectioning portions of the board and the visual observation of the subsurface printed layers.
The present invention allows the substrate test operator, in which current is induced into the substrate, to select a "low" ambient temperature lower than that surrounding the apparatus housing and then test the various substrates using this temperature as the base. As mentioned, heretofore, such testing was usually conducted with an initial room temperature ambient temperature, thereby limiting the test to only said temperature as the "low" ambient. Because substrates such as PCBs very often operate at much lower ambient temperatures (e.g., during automotive and military applications), a room temperature ambient as the initial temperature is deemed unsatisfactory to fully evaluate a substrate's end use conditions. A test system capable of both very hot and very cold cycling on the same coupon provides at least two significant advantages. First, in a single test setup, the very same coupon can be exposed to a number of high temperature reflow cycles as a precondition, and then tested to failure at a different cycle to very cold temperatures. Secondly, sets of coupons such as different cells in a designed experiment can be tested to failure at very different test conditions for direct comparison on the same coupon design and test system. That is, one cell of a particular coupon can be tested to failure at a cycle from ambient to reflow conditions, while a second cell of the same coupon can be tested to failure at a cold cycle representative of extreme use conditions, both using the same test system. Techniques of acceleration modeling can then be used to quantify the relative fatigue damage and other affects of a reflow cycle vs. a field cycle. It is therefore believed that an apparatus and associated method for providing low temperatures other than ambient for this type of testing, in combination with the intrinsic fast cycle rates and the ability to also test to very high reflow temperatures on the very same coupon, will represent significant advancements in the art.

Substrate test apparatus and method of testing substrates

Endicott Interconnect Technologies, Inc.


In one embodiment, a scheduler for a queue hierarchy only accesses sub-groups of bucket nodes in order to determine the best eligible queue bucket to transmit next. Etherchannel address hashing is performed after scheduling so that an Etherchannel queue including a single queue in the hierarchy is implemented to guarantee quality of service.

A Hierarchical Queuing Framework (HQF) provides a hierarchy of queues used by a network device such as a switch. One type of queue hierarchy includes physical, logical, and class levels of queues.
The physical level of the hierarchy is used for policing or shaping the physical interface and can only be identified by class default. In an example system, the logical level of the hierarchy is classified by VLAN ID. At this level, the classification can match on VLAN tag (802.1Q or Inter-Switch Link [ISL]) or 802.1Q tunnel tags (Q-in-Q). Traffic at the class level of the hierarchy is classified by class of service (CoS), IP Precedence, IP differentiated services code point (DSCP), and MPLS EXP bits.
For example, the three levels of queues include 4096 class level queues, 1024 logical level queues, and 1 physical level queue available on each Enhanced Services port. For each logical level queue, there can be 1 to 8 class level queues. These queues can also be serviced by multiple Quality of Service (QoS) functions such as policing, shaping, and sharing.
EtherChannel allows multiple physical Fast Ethernet links to combine into one logical channel to allow load sharing of traffic among the links in the channel as well as redundancy in the event that one or more links in the channel fail. In order to distribute frames across a channel, EtherChannel uses a hash algorithm to reduce part of the binary pattern formed by the addresses in a frame to a numerical value that selects one of the links in the channel. The hash algorithm computes a value that assigns the channel, the user can not control the channel used by a particular flow.

3-level queuing scheduler supporting flexible configuration and etherchannel


A single phase W-Ti sputter target and a method of manufacturing the target are disclosed. The target is produced by mixing powders of tungsten and titanium and subjecting the mixed powders to a pressing operation for a time, temperature and pressure sufficient to achieve a mutual solid solution of W and Ti, forming single .beta.(Ti,W) phase. The single phase sputtering target emits much less particulate during sputtering than conventional multiphase W-Ti targets of comparable density and composition.

In the manufacture of semiconductor devices, alloys of tungsten and titanium are used as diffusion barriers between silicon substrates and aluminum alloy metallizations. The tungsten-titanium ("W-Ti") thin film barriers are formed by sputtering W-Ti targets. In general, these targets are fabricated by mixing starting powders of tungsten and titanium and applying heat and pressure to the mixed powders using a forming method such as inert gas hot pressing, vacuum hot pressing, hot isostatic pressing, and cold pressing/sintering.
One problem associated with known W-Ti targets is particulate emission by the target during sputtering. Particulate generated during sputtering contaminates the thin film and thus negatively affects the reliability and productivity of the thin film generated, causing manufacturing yield losses. Accordingly, there has been considerable interest in evaluating causes of particulate generation during the sputtering of W-Ti targets and minimizing target particulate emission. Because most conventional W-Ti target structures consist of multiple phases, including tungsten, titanium, and .beta.(Ti,W), most studies have evaluated particulate generation by multiple phase W-Ti targets.
Studies of particulate emission by multiple phase targets have concluded that particulate generation is determined by the method of forming the target, the density of the target, or the percentage of .beta.(Ti,W) phase in the target structure. For example, early studies indicated that vacuum hot processing was the preferred technique for forming multiple phase targets that produced low particulate during sputtering. Later investigation of multiple phase targets indicated that low particulate generation was a function of a higher target density. U.S. Pat. No. 5,234,487 teaches that decreased particulate emission from multiple phase W-Ti targets can be achieved by having substantially zero .beta.(Ti,W) phase in the target structure. U.S. Pat. No. 5,234,487 further teaches that .beta.(Ti,W) phase is responsible for high particulate emission due to the fact that the .beta.(Ti,W) phase is hard and brittle.
The .beta.(Ti,W) phase consists of finely dispersed tungsten within titanium. This .beta.(Ti,W) phase forms by the interdiffusion of W into Ti during high temperature processing of W-Ti target materials and is the result of a solid-state precipitation, a eutectoid reaction. The phase diagram for tungsten-titanium indicates that at temperatures above 740.degree. C., a 10 weight percent titanium alloy will consist of single .beta.(Ti,W) phase solid solution. To achieve equilibrium for the W-Ti system, the 10 weight present W-Ti alloy must be held at a temperature above 740.degree. C. for a sufficient time to homogenize by diffusion the titanium and tungsten powders. Lower temperatures require longer holding times to achieve equilibrium. Conversely, higher temperatures require less time to achieve equilibrium.
In the manufacture of tungsten-titanium sputtering targets, equilibrium typically is not achieved because tungsten and titanium are not uniform throughout the microstructure of the target. Diffusion of tungsten into regions of titanium tends to produce areas represented by the titanium-rich region of the phase diagram. As these titanium-rich areas cool, the solubility of tungsten in titanium drops, precipitating tungsten. This fine distribution of tungsten in the surrounding titanium is the .beta.(Ti,W) phase. As a consequence of the failure to achieve equilibrium, a resulting typical multiple phase target microstructure consists of three phases--Ti, W, and .beta.(Ti,W). The formation of a single .beta.(Ti,W) phase target has been difficult to accomplish. Consequently, the properties of single phase .beta.(Ti,W) targets and the parameters affecting particle generation by such targets are not well understood.
Despite the extensive research to better understand the relationship among multiple phase W-Ti target manufacturing processes, microstructure, and particulate emission, there is still a need for a method of producing single .beta.(Ti,W) phase sputtering targets. Furthermore, there is a need for W-Ti sputter targets that emit less particulate during sputtering than conventional multiple phase W-Ti targets.

Single phase tungsten-titanium sputter targets and method of producing same


An NIR spectroscopy fluid analyzing system using a series of LED's, each having its own preselected center wavelength, as illumination sources. These wavelengths have overlapping spectral widths, such that the measurement covers a broad spectrum. The LED's illuminate the fluid sample sequentially, and subsequently the transmission absorbance through the sample and the reflectance or scattering from the sample is measured for the wavelength range of each LED. The measurements are performed using photodetectors. The concentrations of component parts of the fluid are expressed in the form of a polynomial, which is a function of the measured transmitted and/or reflected intensities, and of empirical coefficients, which are extracted by prior statistical analysis on measured intensities obtained from a large number of test samples having known concentrations of the component. A novel sample chamber, capable of performing optical absorption measurements on a flowing sample of fluid, is described.

Measurement of the component parts of milk, and real time knowledge of the results of these measurements, is an important factor in the efficient management of a dairy farm. Knowledge of the levels of almost all of the various component parts of the milk is important for different aspects of the herd management. These components include fat, total protein, casein, lactose, somatic cells, blood, progesterone, amino-acids urea, and nucleic acid. The fat and protein content, for instance, are major factors in determining the price that the farmer will obtain for his milk, because they are important economic indicators of the overall milk quality. Changes in these values can indicate to the farmer an incorrect diet. Thus, changes in the fat content could indicate an imbalance in the forage-to-concentrate ratio in the feed; low total protein level may indicate a dietetic energy deficiency; the somatic cell count and the blood count may be used as diagnostic indicators of a specific clinical state of the cow; and fluctuations in lactose content, which is generally very stable for a cow, can indicate the presence of mastitis.
Several methods are described in the prior art for performing on-line milk analysis, with the object of more efficient milk production and herd management. The use of near infra-red (NIR) spectroscopy for analyzing milk has been known for almost 15 years, and the early methods used laboratory-type NIR spectrometers for analyzing the milk off-line. A number of such instruments are available commercially, but they are expensive, and their use is thus generally limited to centralized laboratories, to which the farmer would send milk samples for testing typically only once a month.
In the article "Near Infra-Red Spectroscopy for Dairy Management: Measurement of Unhomogenized Milk Composition" by R. Tsenkova et al., published in Journal of Dairy Science, Vol. 82, pp. 2344–2351, 1999, there is proposed a method whereby the milk content is spectroscopically analyzed in the NIR range of from 400 nm to 2500 nm. A proposal is made therein to use fiberoptic probes and relatively inexpensive silicon detectors for detecting the radiation within the range 700 nm to 1100 nm, thereby making the method affordable enough to be applied at the milking station for real-time analysis during milking. However, no details are given of an apparatus suitable for performing this analysis using such silicon detectors. Furthermore, although the use of inexpensive detectors is proposed, no mention is made of the sources that could be used with these detectors to provide the NIR illumination.
The article presents an analysis and comparison of the results obtained in the 1100 to 2400 nm spectral range, to those obtained in the 700 to 1100 nm spectral range, where inexpensive silicon detectors can be used. Essentially continuous measurements (every 2 nm) were made across the whole of these spectral ranges. Though not specifically stated in the article, such spectral coverage can generally be obtained from the internal blackbody illuminating source of most NIR spectrometers. The methods described in the Tsenkova et al. article are largely directed at statistical methods of extracting the desired concentration levels from the overall absorption spectra. A commercial software program was used to develop models for determining fat, total protein and lactose content, and calibration of the models was performed using the Partial Least Squares (PLS) regression technique.
Further descriptions of methods of milk analysis using NIR spectroscopy are given in the articles "Fresh raw milk composition analysis by NIR spectroscopy" by Z. Schmilovitch et al, published in Proceedings of the International Symposium on the Prospects for Automatic Milking, Wageningen, Netherlands, EAAP Publication No. 65, pp. 193–198 (1992), and in "Low Cost Near Infra-red Sensor for On-line Milk Composition Measurement" by Z. Schmilovitch et al., published in the Proceedings of the XIV Memorial CIGR World Congress, 2000, Tsukuba, Japan, some of the authors of which are co-applicants for the present invention.
The spectroscopic measurements themselves in the above-mentioned Tsenkova et al article were performed off-line on collected samples, using a commercial NIR spectroscopic milk analyzer, the Milko-Scan, supplied by Foss-Electric A/S, Hillerod, Denmark. The cost of such instruments is such that they are only generally feasibly economical for installation in central laboratories, and not in every cowshed, let alone at every milking station.
There therefore exists an important need for an inexpensive and simple apparatus and method for the on-line qualitative analysis of milk, which will be sufficiently inexpensive that it can be widely used to enable real-time data to be obtained during the milking process, even at each milking station, but without significantly compromising the accuracy of the measurements required for efficient dairy herd management. Furthermore, the apparatus must be capable of performing its analyses on the type of milk flows typically obtained from milking machines. Such flows are highly pulsed in nature, and generally very turbulent, such that a conventional optical sensing path which measures the optical transmission through the flow from side to side of the flow channel is of limited use.
The disclosures of all publications mentioned in this section and in the other sections of the specification, and the disclosures of all documents cited in the above publications, are hereby incorporated by reference, each in its entirety.

S.A.E. Afikim Computerized Dairy Management System

Agricultural Research Organization of the State of Israel Ministry of Agriculture


Various technologies described herein pertain to enforcing control flow integrity by adding instrumentation when source code is compiled or binary code is rewritten. An indirect call to a control transfer target (e.g., in the source code, in the binary code, etc.) can be identified. Moreover, the instrumentation can be inserted prior to the indirect call. The instrumentation can use a bit from a bitmap maintained by a runtime to verify whether the control transfer target is valid. When an executable image that includes the inserted instrumentation runs, execution can be terminated and/or other appropriate actions can be taken when the control transfer target is determined to be invalid; alternatively, execution can continue when the control transfer target is determined to be valid.

Various memory safety vulnerabilities associated with computer software may allow for unauthorized access. For instance, a buffer overrun can occur when a program tries to store more data in a buffer than that buffer is intended to hold. Moreover, an attacker can use the buffer overrun to run arbitrary code on a computer of a victim. In order to accomplish the foregoing, the attacker can rely on the ability to divert a flow of execution in a manner that was not originally intended by the program, such as by corrupting a function pointer, virtual table pointer, or return address.
Some conventional approaches to mitigate such memory safety vulnerabilities attempt to enforce various forms of control flow integrity (CFI), which place constraints pertaining to where an attacker can divert the flow of execution. These techniques can generally rely on compile-time or runtime instrumentation that makes use of certain data structures to determine validity of a target address before permitting control flow to be transferred. However, the conventional techniques that use the foregoing instrumentation oftentimes are impractical for large-scale retail deployment due to technical limitations, performance costs (e.g., processing, memory, etc.), incompatibility with legacy environments, agility, and overall effectiveness. These problems have made it generally impractical to realize the benefits of CFI at scale, and have therefore left open problems in software security unmitigated in practice.

Control flow integrity enforcement at scale


A new and distinct Solidago plant named ‘Dansol21’ particularly characterized by having a plant height of 70-75 cm, large, yellow inflorescences, green leaves, a rapid growth cycle and an even growth rate.

The present invention relates to a new and distinct cultivar of the goldenrod plant, botanically known as Solidago sp., and hereinafter referred to by the cultivar name 'Dansol21'.
Solidago, of the sunflower family, Asteraceae, consists of approximately 100 species of goldenrod plants found in North America, most of which are geographically located in the East. Goldenrods are perennial plants that commonly grow along stream banks, ditches, roadsides and other areas where the soil is moist and rich.
The new Solidago cultivar is a product of a planned breeding program conducted by the inventor, Gabriel Danziger, in Moshav Mishmar Hashiva, Israel. The objective of the breeding program was to develop a new Soligado variety with a large yellow inflorescence, green leaves, a rapid growth cycle, and an even growth rate.
The new Solidago cultivar originated from a cross made by a planned breeding program discovered by the inventor in 2001 in Moshav Mishmar Hashiva, Israel. The female or seed parent is Solidago sp. cultivar designated as '4-gy-8' (unpatented). The male or pollen parent is unknown. The new Solidago cultivar 'Dansol21' was selected by the inventor as a flowering plant within the progeny of the stated cross in a controlled environment in Moshav Mishmar Hashiva, Israel.
Asexual reproduction of the new Solidago cultivar by leaf cuttings was first performed in October, 2001, in Moshav Mishmar Hashiva, Israel, and has demonstrated that the combination of characteristics as herein disclosed for the new Solidago cultivar are firmly fixed and retained through successive generations of asexual reproduction. The newly cultivar reproduces true to type.


A control circuit for controlling an output voltage of a DC--DC converter which supplies power to various semiconductor device, such as a processor and a memory, by way of an output transistor. The control circuit drives the output transistor in response to an external control signal. The control circuit gradually reduces an operating time of the output transistor by performing a discharge operation in response to the external control signal being inactive.

The present invention relates to a control circuit for controlling an output voltage of a DC--DC converter. More particularly, the present invention relates to a control circuit for use with a DC--DC converter which supplies operational power to various types of semiconductor integrated circuit (IC) devices, such as a central processing unit (CPU) and a memory (RAM, ROM, etc.), mounted on any of various types of electronic apparatuses.
In portable electronic equipment which operates on power from a battery serving as a power source, if an internal circuit must be supplied with a DC voltage differing from the voltage of the battery, the desired DC voltage is produced by a DC--DC converter which operates on power from a battery power source. If a plurality of source voltages are used, there is a risk of damaging a device if a sequence of turn-on and shutdown of the power sources is not taken account. Accordingly, there is a need to control the rising and falling forms of an output voltage from the DC--DC converter.
FIG. 1 shows an example of a conventional DC--DC converter used as a power supply circuit of semiconductor integrated circuit devices, such as a CPU or a microcomputer. The DC--DC converter 101 comprises a control circuit 102 formed on a single integrated circuit chip, and a plurality of external elements. The control circuit 102 receives a control signal CTL and is activated when the control signal CTL is high.
A first output signal OUT1 of the control circuit 102 is input to the gate of an output transistor 103, and the drain of the output transistor 103 is connected to a power source Vcc. The output transistor 103 is an N-channel MOS transistor.
The source of the output transistor 103 is connected to the drain of a synchronous rectifying transistor 104, and a second output signal OUT2 from the control circuit 102 is input to the gate of the synchronous rectifying transistor 104 whose source is connected to a ground GND. The synchronous rectifying transistor 104 is also an N-channel MOS transistor.
The source of the output transistor 103 is connected to an output terminal To via an output coil 105. The source of the output transistor 103 is also connected to the cathode of a fly-wheel diode 106 whose anode is connected to the ground GND. The output terminal To is connected to the ground GND via a capacitor 107.
In the DC--DC converter 101, the first and second output signals OUT1 and OUT2 are output from the control circuit 102 when the control circuit 102 is activated. The first and second output signals OUT1 and OUT2 are output in the form of complementary pulse signals. Accordingly, the output transistor 103 and the synchronous rectifying transistor 104 are alternately turned on.
An electric current output from the output transistor 103 is smoothed by means of the output coil 105 and the capacitor 107 through switching operation of the output transistor 103. When the output transistor 103 is turned off, an output voltage Vo output from the output terminal To is smoothed by means of the electrical current supplied to the output coil 105 via the flywheel diode 106 from the capacitor 107. Further, the synchronous rectifying transistor 104 is turned on by the second output signal OUT2, so that a forward voltage drop of the flywheel diode 106 is reduced to substantially zero, thereby improving smoothing efficiency.
At this time, the synchronous rectifying transistor 104 is turned on, after the output transistor 103 has been turned off, and is turned off before the output transistor 103 is turned back on. Therefore, a through current is prevented from flowing from the power source Vcc to the ground GND via the output transistor 103 and the synchronous rectifying transistor 104.
Through the foregoing operations, a DC output voltage Vo is output from the output terminal To, and the voltage level of the output voltage Vo is maintained constant by adjustment of the duty factor of each of the first and second output signals OUT1 and OUT2.
If the control signal CTL goes low, deactivating the control circuit 102 while the output transistor 103 is performing a switching operation, the output transistor 103 and the synchronous rectifying transistor 104 are held in an off state.
The electric charge stored in the capacitor 107 is discharged via a load connected to the output terminal To. As a result, as shown in FIG. 2, the output voltage Vo is reduced to low (ground GND).
At this time, the time required for the output voltage Vo to decrease to low differs according to the value of the discharge current flowing into the load and the time constant defined by the capacitance of the capacitor 107. Accordingly, the time required for the output voltage Vo to decrease to low is dependent on the load connected to the output terminal To.
Under these circumstances, the time required to stop the supply of power to the load in response to the trailing edge of the control signal CTL becomes unstable. For this reason, in the semiconductor integrated circuit device that operates on a plurality of source voltages, there arises a risk of erroneous operations of a CPU, or the like, connected to the power supply circuit as a load.
As indicated by a dotted line in FIG. 1, an N-channel MOS transistor, which is turned on when the control signal CTL goes low, is connected as a discharge transistor 108 between the output terminal To and the ground GND. The current drive capability of the discharge transistor 108 is set to be sufficiently greater than the discharge current drive capability of the load.
With the foregoing configuration, the rate at which the output voltage Vo decreases, in response to the reduction of the voltage level of the control signal CTL, to low level is substantially constant, as determined by the time constant of the capacitance 107 and the discharge transistor 108, regardless of the load.
The foregoing configuration, however, requires addition of the discharge transistor 108 having a large current drive capability, thereby increasing the cost and the size of the DC--DC converter.
If the DC--DC converter is configured such that the synchronous rectifying transistor 104 is turned on when the control signal CTL goes low, there is no need to add the discharge transistor 108 to the DC--DC converter.
However, such a configuration requires addition to the control circuit 102 of a circuit for turning on the synchronous rectifying transistor 104 when the control signal CTL goes low. Accordingly, the chip area of the semiconductor device equipped with the control circuit 102 is increased, thereby hindering a reduction in the size of the DC--DC converter.
A plurality of semiconductor integrated circuit devices (ICs) are mounted on an electronic apparatus. These semiconductor integrated circuit devices individually require operational power. In general, the operational power is provided by a DC--DC converter. If there is a failure to provide the ICs with stable power supply or to execute a power-up sequence of the ICs, the ICs cause faulty operation. For this reason, there is a demand for highly accurate power-up operation.
A DC power produced by conversion of a commercial power by means of a power supply circuit (an AC-DC converter) is commonly used as the power source for various types of electronic equipment. The thus-converted DC power is further converted into operational power corresponding to each of the ICs by means of the DC--DC converter 101. The thus-converted operational power is supplied to the corresponding IC. Referring to FIG. 5, an electronic device 300 includes semiconductor integrated circuit devices 301, such as a central processing unit (CPU), a chip selector, and a memory (RAM or ROM); a power supply circuit 302; and a DC--DC converter 201. The power supply circuit 302 converts a commercial power VA into various types of DC power Vcc and Vin. The DC--DC converter 201 regulates the thus-converted DC voltage Vin to obtain stable operational power (i.e., an output voltage Vout) and supplies the thus-obtained operational power to each of the semiconductor integrated circuit devices 301.
FIG. 3 is a circuit diagram of the DC--DC converter 201. The DC--DC converter 201 comprises a control circuit 202 formed on a one-chip semiconductor integrated circuit device, and a plurality of external elements. A signal SG1 output from the control circuit 202 is supplied to the gate of an output transistor 203 composed of an enhanced N-channel MOS transistor. A DC supply voltage Vin is supplied to the drain of the output transistor 203 from the power supply circuit 302 shown in FIG. 5, and the source of the output transistor 203 is connected to an output terminal 205 via an output coil 204. The output terminal 205 is also connected to each of the semiconductor integrated circuit devices 301 which serve as loads.
The source of the output transistor 203 is connected to the cathode of the flywheel diode 206 composed of a Schottky diode. The anode of the flywheel diode 206 is connected to the ground GND. A junction between the output coil 204 and the output terminal 205 is connected to the ground GND via a capacitor 207, and a smoothing circuit is formed from a combination of the output coil 204 and the capacitor 207. The junction between the output coil 204 and the output terminal 205 is connected to the control circuit 202 via a resistor 208, such that the output voltage Vout is provided to the control circuit 202.
The control circuit 202 comprises a reference voltage generation circuit 211; an initial malfunction prevention circuit 212; a triangular wave oscillation circuit 213; a dead time circuit 214; an error amplification circuit 215; a constant current circuit 216; a PWM comparison circuit 217; an output circuit 218; and first and second transistors 219, 220.
A drive source voltage Vcc is supplied to the reference voltage generation circuit 211 from the power supply circuit 302, and the reference voltage generation circuit 211 receives a control signal SG2 from an unillustrated external device via an external control input terminal 221. The reference voltage generation circuit 211 is composed of a band-gap reference circuit and generates a reference voltage Vref (<Vcc) from the drive source voltage Vcc as a first reference voltage in response to the control signal SG2 being high. As shown in FIG. 4, if the control signal SG2 goes high at time t0, the reference voltage Vref rises at a given rate and reaches a specified voltage Vref1 (<Vcc). Subsequently, the reference voltage Vref is maintained at the specified voltage Vref1.
The initial malfunction prevention circuit 212 receives the drive source voltage Vcc from the power supply circuit 302 and the reference voltage Vref as a bias voltage from the reference voltage generation circuit 211. The initial malfunction prevention circuit 212 is designed to output a cancel signal SG3 which goes from high to low when the reference voltage Vref which is in the course of rising to the specified voltage Vref1 reaches a given voltage Vref2, as shown in FIG. 4; i.e., at time t1, at which time the reference voltage Vref reaches the bias voltage (=Vref2), which permits operation of the initial malfunction prevention circuit 212.
The triangular wave oscillation circuit 213 receives the drive source voltage Vcc from the power supply circuit 302 and the reference voltage Vref as the bias voltage from the reference voltage generation circuit 211. When the reference voltage Vref increases to a given voltage Vref3 (>Vref2) as shown in FIG. 4, the triangular wave oscillation circuit 213 commences at a point in time between time t1 and time t2, at which time the reference voltage Vref reaches the bias voltage (=Vref3), which permits oscillation of the triangular wave oscillation circuit 213, thereby outputting a triangular wave signal SG4 which oscillates within a given voltage range.
The dead time circuit 214 is composed of a potential dividing circuit including a plurality of resistors connected in series and receives the reference voltage Vref from the reference voltage generation circuit 211 and divides it. The thus-divided voltage is output as a limit signal SG5. As shown in FIG. 4, if the control signal SG2 goes high at time t0, the limit signal SG5 rises at a given rate, as does the reference voltage Vref. The limit signal SG5 reaches a rated or predetermined voltage Vk (<Vref1) at time t2 and is maintained at the rated voltage Vk thereafter. The rated voltage Vk of the limit signal SG5 is set to a value slightly lower than the maximum value of the triangular wave signal SG4 by control of the voltage-dividing ratio of the resistors in the dead time circuit 214. More specifically, the rated voltage Vk is set to a value such that the duty ratio of a pulse signal of an output signal SG1 from the output circuit 218 becomes 90% when the triangular wave signal SG4 is compared with the limit signal SG5 by means of the PWM comparison circuit 217.
The error amplification circuit 215 has an inverting input terminal, which serves as an input terminal for receiving a detected voltage, and first and second noninverting input terminals, which serve as first and second reference voltage input terminals. The inverting input terminal receives the output voltage Vout via the resistor 208. The error amplification circuit 215 receives the drive source voltage Vcc from the power supply circuit 302 and the reference voltage Vref as the bias voltage from the reference voltage generation circuit 211. The second noninverting input terminal of the error amplification circuit 215 is connected to the ground GND via an external capacitor 222 for gentle start-up purposes. The capacitor 222 receives a constant current from the constant current circuit 216, which operates on the reference voltage Vref received from the reference voltage generation circuit 211. The capacitor 222 is charged by the constant current received from the constant current circuit 216, and the charge voltage Vsof of the constant current increases to the reference voltage Vref. That is, the charge voltage Vsof serves as a second reference voltage with respect to the reference voltage Vref that serves as the first reference voltage. The charge voltage Vsof is produced by the reference voltage generation circuit 211 and the capacitor 222.
The second noninverting input terminal of the error amplification circuit 215 is also connected to the collector of the first transistor 219 for gentle start-up purposes, and the emitter of the first transistor 219 is connected to the ground GND. The base of the first transistor 219 receives the cancel signal SG3 from the initial malfunction prevention circuit 212. Accordingly, if the cancel signal SG3 drops to low from high at time t1 to thereby switch the first transistor 219 from an on state to an off state, the charging of the capacitor 222 with the constant current from the constant current circuit 216 is started. As a result, as shown in FIG. 4, the charge voltage Vsof starts increasing at time t1.
A series circuit comprising an external capacitor 223 and a resistor 224 is connected between an output terminal and the inverting input terminal of the error amplification circuit 215, thereby preventing oscillation of the error amplification circuit 215.
The error amplification circuit 215 compares either the reference voltage Vref or the charge voltage Vsof, whichever voltage is lower, with the output voltage Vout. The error amplification circuit 215 produces an error output signal SG6 by amplification of a difference between the thus-compared voltages and outputs the error output signal SG6 to the PWM comparison circuit 217 in the following stage.
As shown in FIG. 4, the error amplification circuit 215 outputs the output voltage SG6 corresponding to the reference voltage Vref without comparison and amplification until the reference voltage Vref reaches a given voltage; i.e., until time t1, at which time the initial malfunction prevention circuit 212 outputs the cancel signal SG3 low. In other words, since logical inversion occurs when at least one of the first and second noninverting input terminals has a voltage near zero volts, the bias voltage, or the error output signal SG6 having the same amplitude as that of the reference voltage Vref, is output.
After time t1, the error amplification circuit 215 compares the output voltage Vout with either the reference voltage Vref or the charge voltage Vsof, whichever voltage is lower, and amplifies a potential difference between the voltages.
The PWM comparison circuit 217 receives the drive source voltage Vcc from the power supply circuit 302 and has an inverting input terminal and first and second noninverting input terminals. The noninverting input terminal of the PWM comparison circuit 217 receives the triangular wave signal SG4 from the triangular wave oscillation circuit 213. The first noninverting input terminal of the PWM comparison circuit 217 receives an error input signal SG6 from the error amplification circuit 215. The second noninverting input terminal of the PWM comparison circuit 217 receives the limit signal SG5 from the dead time circuit 214.
The PWM comparison circuit 217 compares either the error output signal SG6 or the limit signal SG5, whichever has a lower voltage, with the triangular wave signal SG4. The PWM comparison circuit 217 outputs a pulse signal to the output circuit 218 as a duty control signal SG7, which goes low when the triangular wave signal SG4 has a voltage higher than that of the compared signal, and goes high when the triangular wave signal SG4 has a voltage equal to or smaller than that of the compared signal.
The output terminal of the PWM comparison circuit 217 is connected to the collector of the second transistor 220, and the emitter of the second transistor 220 is connected to the ground GND. The base of the second transistor 220 receives the cancel signal SG3 from the initial malfunction prevention circuit 212. Accordingly, when the cancel signal SG3 decreases to low to thereby turn off the second transistor 220, the duty control signal SG7 is output to the output circuit 218 in the following stage. The output circuit 218 receives the drive source voltage Vcc from the power supply circuit 302. The output circuit 218 outputs to the gate of the transistor 203 the duty control signal SG7 as the above-described output signal SG1.
The DC--DC converter 201 is in a suspended state when the reference voltage generation circuit 211 receives the control signal SG2 low from an external device while the drive source voltage Vcc is supplied to each of the circuits 211-213, 215, 217, and 218 in the control circuit 202 from the power supply circuit 302 shown in FIG. 5.
That is, the reference voltage Vref used for generating a reference voltage is zero volts. Accordingly, a reference voltage Vref of zero volts is supplied to the first noninverting input terminal of the error amplification circuit 215, and the initial error malfunction prevention circuit 212 receives the reference voltage Vref of zero volts. The cancel signal SG3 is high, and therefore the first and second transistors 219 and 220 are in an on state. As a result, the first noninverting input terminal of the error amplification circuit 215 is zero volts. Further, since the second transistor 220 is in an on state, the output signal SG1 goes low. Accordingly, the output transistor 203 is in an off state, and the output voltage Vout is zero volts.
When the control signal SG2 high is supplied to the reference voltage generation circuit 211 from an external device at time t0, the DC--DC converter 201 commences operation. In response to the control signal SG2 high, the reference voltage generation circuit 211 generates the reference voltage Vref on the basis of the drive source voltage Vcc. At this time, as shown in FIG. 4, the reference voltage Vref increases at a given rate to the specified voltage Vref1. The gradually increasing reference voltage Vref is supplied to the initial malfunction prevention circuit 212, the triangular wave oscillation circuit 213, the dead time circuit 214, the noninverting input terminal of the error amplification circuit 215, and the constant current circuit 216.
At this time, although the increasing reference voltage Vref is supplied to the first noninverting input terminal of the error amplification circuit 215, the charge voltage Vsof input to the second noninverting input terminal of the error amplification circuit 215 is zero volts. Therefore, the error output signal SG6 of the error amplification circuit 215 increases in such a way as to have the same magnitude as that of the increasing reference voltage Vref. Further, the dead time circuit 214 supplies to the PWM comparison circuit 217 the limit signal SG5 proportional to the reference voltage Vref.
Consequently, the PWM comparison circuit 217 compares the limit signal SG5 from the dead time circuit 214 with the triangular wave signal SG4 from the triangular wave oscillation circuit 213. At this time, the triangular wave oscillation circuit 213 has not yet commenced oscillation, and hence the triangular wave signal SG4 is zero volts. As a result, the PWM comparison circuit 217 outputs the duty control signal SG7 high. However, since the second transistor 220 is in an on state, the duty control signal SG7 goes low. The output circuit 218 still outputs the signal SG1 low, so that the output transistor 203 is left in an off state.
At time t1, the initial malfunction prevention circuit 212 outputs the cancel signal SG3 low to the base of each of the first and second transistors 219, 220, thereby turning off the first and second transistors 219, 220. When the first transistor 219 is turned off, the capacitor 222 commences accumulation of electric current, and the charge voltage Vsof is supplied to the second noninverting input terminal of the error amplification circuit 215. The charge voltage Vsof is lower than the reference voltage Vref, and hence the error amplification circuit 215 compares the output voltage Vout with the charge voltage Vsof and amplifies a difference between the voltages. The error output signal SG6 is then output to the PWM comparison circuit 217. Immediately after time t1, the output voltage Vout is zero volts, and the charge voltage Vsof is slightly larger than zero volts. Therefore, since the difference between the charge voltage Vsof and the output voltage Vout is small, the error output signal SG6 from the error amplification circuit 215 decreases.
At time t1, the triangular wave oscillation circuit 213 has not yet commenced oscillation. Therefore, the PWM comparison circuit 217 compares the limit signal SG5 with the triangular wave signal SG4 until the error output signal SG6 from the error amplification circuit 215 becomes smaller than the limit signal SG5 from the dead time circuit 214. When the error output signal SG6 becomes smaller than the limit signal SG5, the PWM comparison circuit 217 compares the error output signal SG6 with the triangular wave signal SG4. However, the triangular wave oscillation circuit 213 has not yet commenced oscillation, and the triangular wave signal SG4 is zero volts. As a result, the PWM comparison circuit 217 outputs a duty control signal SG7 high.
At this time, the second transistor 220 is in an off state, and therefore the duty control signal SG7 high is output to the output circuit 218. Accordingly, the signal SG1 output from the output circuit 218 goes high, and the output transistor 203 is turned on. The source voltage Vin is supplied to the output terminal 205 via the output coil 204, and the output voltage Vout increases to the source voltage Vin from zero volts. The thus-increasing output voltage Vout is supplied to the error amplification circuit 215.
The triangular wave oscillation circuit 213 oscillates and outputs the triangular wave SG4. When the triangular wave signal SG4 becomes greater than the error output signal SG6, the duty control signal SG7 of the PWM comparison circuit 217 goes low. The output signal SG1 from the output circuit 218 goes low, and the output transistor 203 is turned off. As a result, the supply of the source voltage Vin to the capacitor 207 is interrupted, so that the capacitor 207 discharges, thereby resulting in a drop in the output voltage Vout.
The error amplification circuit 215 compares the decreasing output voltage Vout with the charge voltage Vsof and outputs the error output signal SG6 to the PWM comparison circuit 217. Since the decreasing output voltage Vout is greater than the charge voltage Vsof, the error output signal SG6 from the error amplification circuit 215 is smaller than the triangular wave signal SG4. Accordingly, the PWM comparison circuit 217 maintains output of the duty control signal SG7 low. More specifically, the output voltage Vout continues decreasing while the output transistor 203 is maintained in an off state.
When the output voltage Vout becomes smaller than the charge voltage Vsof, the voltage of the error output signal SG6 from the error amplification circuit 215 increases and reaches a voltage range corresponding to the oscillation range of the triangular wave signal SG4. When the error output signal SG6 reaches the voltage range corresponding to the oscillation range of the triangular wave signal SG4, the PWM comparison circuit 217 outputs the duty control signal SG7, which goes high when the error output signal SG6 is larger than the triangular wave signal SG4, and goes low when the error output signal SG6 is smaller than the triangular wave signal SG4.
The DC--DC converter 201 controls the output voltage Vout such that it follows the increasing charge voltage Vsof. When the charge voltage Vsof reaches the specified voltage Vref1, the DC--DC converter 201 controls the output voltage Vout such that the output voltage Vout is maintained at the reference voltage Vref; i.e., the specified voltage Vref1.
That is, in an ordinary state, the error amplification circuit 215 compares the reference voltage Vref (predetermined voltage value Vref1) with the output voltage Vout and outputs the error output signal SG6 to the PWM comparison circuit 217. The PMW comparison circuit 217 compares the error output signal SG6 with the triangular wave signal SG4 and outputs the duty control signal SG7 in order to control the output transistor 203 through duty control. Thus, the DC--DC converter 201 is controlled such that the output voltage Vout is maintained at the reference voltage Vref (predetermined voltage value Vref1).
Upon power-up (i.e., upon receipt of the control signal SG2 low), the DC--DC converter 201 performs gentle start-up operation, in which the output voltage Vout is increased, gradually, to the specified voltage Vref1 of the reference voltage Vref. By means of a gentle start-up circuit composed of the first transistor 219, the capacitor 222, the error amplification circuit 215, and the constant current supply circuit 216, the DC--DC converter 201 increases the output voltage Vout to the reference voltage Vref in accordance with an increase in the charge voltage Vsof. In a case where the output voltage Vout is increased to the predetermined voltage specified voltage Vref1 of the reference voltage Vref, the output transistor 203 is kept in an on state. However, by virtue of the gentle start-up circuit, the output transistor 203 is prevented from being held in an on state, which in turn prevents deterioration of the transistor 203.
When the initial malfunction prevention circuit 212 outputs the cancel signal SG3 low at the time of the gentle start-up operation being performed by the DC--DC converter, the duty control signal SG7 immediately goes high irrespective of the charge voltage Vsof, and the output transistor 203 is immediately turned on. In other words, the gentle start-up function becomes temporarily inactive. This is attributable to the fact that the triangular wave oscillation circuit 213 does not oscillate even when the triangular wave oscillation circuit 213 goes low.
The output transistor 203 becomes temporarily turned on before the gentle start-up operation is performed, so that an excess electric current flows to the output transistor 203, thereby deteriorating the output transistor 203.
As a result of the output transistor 203 being abruptly turned on, the output voltage Vout sharply increases and becomes unstable. Such an unstable output voltage Vout is supplied as operational power to each of the semiconductor integrated circuit devices, thereby resulting in fault operations between the semiconductor integrated circuit devices. Particularly, a problem arises in a case where the semiconductor integrated circuit devices 301 are required to be turned on at predetermined timings; i.e., in accordance with a predetermined sequence.
Upon receipt of an uncertain input, the PWM comparison circuit 217 may output the duty control signal SG7 high. In such a case, similar problems arise.
Accordingly, a first object of the present invention is to provide a discharge control circuit which enables control of the trailing edge of an output voltage regardless of a load while reducing the size of a circuit area.
A second object of the present invention is to provide a DC--DC converter control circuit which ensures execution of gentle start-up operation and enables stable supply of an output voltage.


A turbine mechanical output computation device computes a gas turbine mechanical output P from the following equation

1. Field of the Invention
This invention relates to a turbine mechanical output computation device for computing the mechanical output of a turbine which rotationally drives a generator, and a gas turbine control device equipped with the turbine mechanical output computation device.
2. Description of the Related Art
In controlling a lowNOx combustor in a gas turbine, it is necessary to maintain the ratio between the amounts of fuel and combustion air, which are supplied to the combustor, i.e., fuel-air ratio, at a value in a predetermined range. For this purpose, the amount of fuel needs to be detected accurately and promptly.
In the fuel-air ratio control of the gas turbine by a gas turbine control device, the mechanical output of the gas turbine has been taken as an indicator of the amount of fuel. To measure the gas turbine mechanical output, generator output (generator effective power) has been used. That is, based on the relationship of the equation shown below, generator output is used as a signal representing the amount of fuel. The reason for the use of generator output is that compared with a flow meter for measuring the amount of fuel, a power converter (generator effective power wattmeter) for measuring the output of a generator is characterized by high precision, high speed detection, and high reliability (multiplexing is also easy).Amount of fuel=Amount of energy fed into gas turbine=Gas turbine mechanical output=Generator output
Japanese Patent Publication No. 1995-111148 discloses an example of an acceleration control method for a two-shaft gas turbine using a gas turbine rotational speed signal.
When a generator effective power wattmeter is used for measuring gas turbine mechanical output, as described above, all of gas turbine mechanical output is converted into generator output, in an ordinary stable operating state where the gas turbine rotates at a constant rotational speed. Thus, the following relationship holds, and no problem is posed:Gas turbine mechanical output=Generator output (Generator effective power)
Generally, however, even when the amount of fuel supplied to the combustor is nearly constant, and the generator is operated with constant output, there may be a case where disturbance occurs in an electric power system to which the generator is connected (i.e., such as switching of a power transmission system). In this case, current fluctuations occur in the electric power system, causing changes in effective power, reactive power, and power factor. That is, in the event of a disturbance in the electric power system or the like, the electric power system falls into a state where it cannot receive electric power stably, with the result that the relationship of the above equation is transiently impaired. In such a state, not all of the gas turbine mechanical output is converted into the generator output, and the portion of the gas turbine mechanical output not converted into the generator output is converted into the rotational energy of the gas turbine. As a result, the rotational speed of the gas turbine changes. In such a transient period, therefore, fuel-air ratio control deviates from the optimal state, thus presenting problems, such as the occurrence of combustion vibrations in the combustor. The occurrence of combustion vibrations becomes the cause of a misfire in or damage to the combustor.

Turbine mechanical output computation device and gas turbine control device equipped therewith

Abstract: P  =      Pe    +          J      ×      g      ×                        (                                    2                            π                        60                    )                2            ×      N      ×                        ⅆ          N                          ⅆ          t                    where Pe represents a generator effective power measured by a generator effective power wattmeter, N represents the rotational speed of a gas turbine measured by a gas turbine tachometer, J represents the moment of inertia of the gas turbine, and g represents gravitational acceleration. A combustion air amount controller controls the amount of combustion air based on the gas turbine mechanical output P.


A window tracking analog to digital convertor (10) and method of signal conversion is disclosed. A sample and hold amplifier (16) samples an analog input signal and passes the sampled signal to a window comparator (20). The window comparator (20) analyzes the analog input signal to determine if its amplitude falls between upper and lower reference levels which establish a tracking "window." If the amplitude of the signal falls outside of the window, a control processor (34) and window reference tracker (24) adjusts the reference levels in the direction of the reference level which was exceeded until the analog input signal falls within the window, the adjusted reference level in the direction of adjustment representing the level of the sampled signal. A continuous interval timer (38) counts the amount of time that the analog input signal remained within the window. Once the window is adjusted, a digital output signal represented by the amplitude of the sampled signal and the number of timing intervals is sent an instrument such as a computer for use.

1. Field of the Invention
This invention pertains generally to analog to digital converters and conversion techniques, and more particularly a window tracking apparatus and method for analog to digital conversion.
2. Description of the Background Art
Analog to digital converters are commonly employed to change an analog signal into a collection of digital data bits that accurately represent the signal. While the amplitude of the analog input signal can be continuously variable without discontinuity, the digital output signal into which it is physically changed will contain certain discontinuities which are characteristic of its digital form.
Conventional analog to digital converters measure the amplitude of an analog signal at a given instant during a sampling period and then change the signal to the closest digital form. Therefore, in order to provide for accurate digital representation of an analog signal, the digital form of the signal must change as the analog signal changes. If the sampling rate is too low, the digital form of the signal will not accurately represent the analog signal and low frequency aliasing can occur. It is generally accepted that, in order to convert an analog signal into a usable digital form without aliasing, the sampling rate must be at least twice the highest frequency component of the analog signal. However, the output of a conventional analog to digital converter will contain not only the digital form of the analog signal, but double sideband images of the analog signal centered at multiples of the sampling frequency. Therefore, the output signal must be filtered in order to make it usable. This can require the use of complex filters and filtering techniques in order to eliminate the sideband signals without eliminating a portion of the desired signal.
Furthermore, conventional analog to digital converters are subject to quantization error since, at each sampling instant, there will be a difference between the analog signal and the closest available digital representation. Resolution can be increased by increasing the number of data bits used, but data communications rates between the analog to digital converter and the device receiving the output signal are often limited. As a result, there are practical limitations to the accuracy of conventional analog to digital convertors.
Therefore, there is a need for an analog to digital conversion apparatus and method which overcomes the foregoing limitations of conventional devices. The present invention satisfies that need and overcomes the deficiencies in analog to digital convertors heretofore developed.


The present disclosure relates to a test paper counting technology, in particular to a portable test paper counting device and method based on a single photon detector. A portable test paper counting device based on a single photon detector is provided, which includes a box-shaped housing, two guide rail pairs, two hanger rods, a laser, a reflecting mirror, a single photon detector, a power supply, and a PC computer. A rectangular operating hole penetrating from left to right is formed in a lower edge of a right side wall of the box-shaped housing. A right part of a bottom wall of the box-shaped housing is provided with an assembly hole penetrating from up to down. A left side wall of the box-shaped housing is provided with a threading hole penetrating from left to right. Sliders of the two guide rail pairs both face downwards.

In recent years, along with unceasing progress of society, more and more talents are needed, and accordingly there are more and more examinations. In an examination process, test paper counting is a necessary part. At present, the test paper counting is usually carried out manually. Practice has proven that manually counting the test papers is not only time-consuming and laborious, but also low in accuracy rate. In view of this, it is necessary to invent a portable test paper counting device and method based on a single photon detector to solve the problems that manually counting the test papers is not only time-consuming and laborious, but also low in accuracy rate.

Portable test paper counting device and method based on single photon detector