A Z buffer hidden surface removal device calculates the lightness of the sun appearing from behind the cloud and decides whether two planes cross each other or not. The device includes an input-output portion for inputting Z data, an address, and counter data, from the outside and outputting a counter value, Z data, and a write control signal, to the outside. The device further includes a Z buffer portion for reading and writing Z data according to a Z buffer address and a Z buffer portion control signal, a Z operation circuit portion for inputting a Z value and outputting the write control signal and a result of a Z operation, and a counter portion for counting a number of Z data in which the result of the Z operation circuit portion matches with a predetermined condition, among the data that were input to the Z operation circuit portion. There is also disclosed a device in which an A modulator portion for outputting an opacity value from the Z operation result is provided instead of the counter portion. The operations are performed on a pixel basis.

1. Field of the Invention
The present invention relates to a Z buffer hidden surface removal device (HSRD), and more particularly to a hidden surface removal device that uses the depth information (Z data) of an object drawn in a three-dimensional or two-dimensional image display device to perform hidden surface removal by a Z buffer.
2. Description of the Related Art
A conventional graphic engine usually has a frame buffer and a Z buffer. The frame buffer serves as a memory for holding the digital expressions of the color and brightness of each pixel within an image, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The Z buffer serves as a memory for holding a numeral for each pixel within the frame buffer. The numeral stored in this Z buffer is called Z data or a Z value and is depth information representative of the distance between an observer and an object displayed with pixels. Smaller Z data indicates that the object is closer to the observer.
As shown in FIG. 5, a conventional Z buffer HSRD comprises an input-output portion 1 for performing input-output of data such as a Z value, a counter value, and an address, with the outside, a Z buffer portion 2 for storing a Z value, and a Z operation circuit portion 6 for inputting the Z value and outputting a write control signal and an operation result.
Next, the operation of this conventional Z buffer HSRD will be described along the flowchart of FIG. 6.
By the Z operation circuit portion 6, two data of Z data (Zs) and a write address (Adr) are read out from the input-output portion 1 (step S101). By the Z operation circuit portion 6, Z data (Zd) being currently stored in an address (Adr) within the Z buffer portion 2 is taken out of the Z buffer portion 2 (step S102). The Z data (Zs) from the input-output portion 1 and the Z data (Zd) taken out of the Z buffer portion 2 are compared (step S103). When the Z data (Zs) is smaller (step S104), i.e., when a desired pixel is on the side closer to the observer, a "1" is output as a write control signal (step S105). This write control signal is also used in the writing to the Z buffer portion 2, and in the case of "1,"the Z data (Zs) from the input-output portion 1 is written to the position of the address (Adr) of the Z buffer portion 2 (step S106). Also, when it is determined in the step S104 that Zd is smaller than Zs, a "0" is output as a write control signal (step S107), and in this case, nothing is written to the Z buffer portion 2.
The above-described operation is performed for each of Z data that are desired to be written.
FIGS. 7A to 7C show ideal hidden surface removal processes. In the figures, the right direction represents a Z-axis direction and the arrow represents a direction in which an observer is seeing. FIG. 7A shows data written first, and FIG. 7B shows data that is newly written with respect to the first data. FIG. 7C shows a result in which ideal hidden surface removal was accomplished by overlapping two pixel data. Thus, only pixels close to the view point of the observer remain.
FIGS. 8A to 8C show the results obtained as data was written in the same method as a write method of normal memories. In normal writing, data is always overwritten. If data is written over the first data of FIG. 8A, the result will become as shown in FIG. 8B. As a result, since data written later always remains as shown in FIG. 8C, consequently, hidden surface removal will not be performed correctly.
FIGS. 9A to 9C show the processes of removing a hidden surface by a conventional Z buffer method. If data to be written is laid over the data of FIG. 9A, the result will become as shown in FIG. 9B. If greater Z data is not written like the crosshatched pixels of FIG. 9B or if it is overwritten by other Z data, then it does not remain in the Z buffer. Among Z data finally written in all addresses of the Z buffer, the smallest data remains as shown in FIG. 9C.
The hidden surface removal is performed in this way, and what is output from the conventional Z buffer HSRD is a write control signal representative of the possibility and impossibility of writing for each data, and Z data that finally remained within the Z buffer.
However, the Z data of the above-described HSRD is insufficient in applications such as virtual reality in which an image of high picture quality needs to be generated with real time.
FIG. 10A illustrates the sun appearing from behind the cloud and the glow generated around it. When you see a very light object with your naked eyes, the light passing through the eyelashes is diffracted and radial rays generate around the object.
The drawing method of the sun and the cloud will hereinafter be described.
First an image of the cloud is drawn with a certain Z value, as shown in FIG. 10B, and then an image of the sun is drawn with a greater Z value than that, as shown in FIG. 10C. Finally an image of the glow is drawn with a Z value smaller than the cloud. When ideal hidden surface removal is performed, there is no possibility that a pixel being in a longer distance is written over a pixel being in a shorter distance, so there is no possibility that the image of the sun is written over the image of the cloud. Therefore, a result like FIG. 10C is obtained. Incidentally, it is preferable that for reality, the glow of the sun change according to the lightness of the sun. The lightness of the sun can be approximated with constant times the visual field area of the sun not hidden by other object, i.e., the uncovered visual field area of the sun. The uncovered visual field area can be obtained in the process of the hidden surface removal. First, all objects that can become an obstacle are drawn, and finally the image of the sun is drawn. If the number of pixels that were hidden-surface removed is subtracted from the number of pixels of the image of the sun, the number of uncovered pixels of the sun will be obtained.
The hidden surface removal is performed as described above, but what is output from the conventional Z buffer HSRD was binary data indicating that the pixel having the Z value can be drawn to the frame buffer or the pixel having the Z value cannot be drawn to the frame buffer.
However, when the above-described HSRD is used in applications such as virtual reality in which there is the need of generating an image of high picture quality with real time, the device having only binary information is often insufficient.
FIGS. 11A, 11B and FIGS. 12A and 12B are examples of the case where binary hidden surface removal is insufficient.
FIGS. 11A and 11B which are a first example is a case where an object whose outline is dim and which projects from a wall is drawn. In this case, as shown in FIG. 11A, it is preferable that the object be drawn so that it becomes transparent as it comes closer to the wall. However, when hidden surface removal is performed with only binary information, a boundary line between the object and the wall, indicated by the arrow of FIG. 11B, becomes clear and the dim feeling of the object disappears.
FIGS. 12A and 12B which are a second example is a case where an object projecting from muddy water is drawn. In this case, as shown in FIG. 12A, it is preferable that the water around the object projecting from muddy water be transparent. However, when hidden surface removal is performed with only binary information, a boundary line between the object and the wall becomes clear and the transparent feeling of water disappears, as shown in FIG. 12B.
As described above, when the image of the sun is sufficiently large, it can be used as an uncovered visual field area of the sun, but since the conventional Z buffer HSRD outputs only a write control signal representative of the possibility or impossibility of writing for each data, and Z data that finally remained in the Z buffer, the above-described number of uncovered visual field pixels and number of pixels to be drawn could not be provided to an observer. Therefore, the number of uncovered visual field pixels and the number of pixels to be drawn, which are used when the lightness of the sun appearing from behind the cloud is calculated, cannot be output.
Also, since the conventional HSRD outputs a result of a Z operation only as binary data indicating that a pixel with the Z value can be drawn to the frame buffer or a pixel with the Z value cannot be drawn to the frame buffer, sufficient information cannot be provided when an object whose lightness changes according to the distance and thickness is drawn.


A method for manufacturing insulating structures in a semiconductor substrate includes forming a first insulating layer on the semiconductor substrate, forming a stop layer on the first insulating layer, and forming a barrier layer on the stop layer. The barrier layer is selective with respect to the stop layer. A screen layer is formed on the barrier layer. A portion of the screen layer is selectively removed for forming an opening therethrough for exposing a portion of the barrier layer. The exposed barrier layer is removed for exposing a portion of the stop layer. The exposed stop layer is removed for exposing a portion of the semiconductor substrate. The method further includes removing the remaining barrier layer, and removing a portion of the exposed semiconductor substrate for forming a trench therein.

A basic technological step for manufacturing integrated circuits includes manufacturing an insulating structure for allowing the different electronic components composing the circuit to be electrically separated. A local oxidation step of a silicon substrate should be performed, for a predetermined depth and width, so that the electrical charges generated by the electronic components are limited to very definite substrate areas.
Moreover, there is a general trend in microelectronics to provide a continuous reduction in the size of the different structures forming the integrated circuit. Therefore, the conditions for manufacturing insulating structures become more critical, especially from a geometric and size point of view.
The term STI (Shallow Trench Isolation) indicates a method for manufacturing an insulating structure suitable for technological generations below 0.25 μm. Referring to FIG. 1, the basic steps for manufacturing this kind of insulating structure are summarized below. In particular, a very thin oxide layer 2, called padox, being about 10 nm thick, is grown on a semiconductor substrate 1, whereon a silicon nitride layer 3 is grown, which is typically 100–200 nm thick. The nitride layer 3 serves as a stopping layer for the following planarizing treatments, while the oxide layer 2 is used as a buffer since the nitride layer 3 and the semiconductor substrate 1 have a very different network pitch.
Afterwards, a mask or resist layer 4 is formed on the nitride layer 3 through a traditional photolithographic technique, wherein openings 4′ are defined and the nitride layer 3 and the padox layer 2 are removed in correspondence thereof. Through a following removal step, a trench 5 is then formed in the semiconductor substrate 1 in correspondence with these openings 4′. The trench 5 is formed with vertical walls, as shown in FIG. 2, or with sloping side walls with respect to the semiconductor substrate 1 surface, as shown in FIG. 3.
After etching and subsequently removing the resist mask 4, a CVD (Chemical Vapor Deposition) deposition step fills the trench 5 with a further oxide layer, not shown in the figures, which is then planarized by using CMP (Chemical Mechanical Polishing) technology.
The shape and the features of the trench 5 formed by plasma etching are thus very important. In fact the trench 5 depth, the shape thereof, the cross dimensions, and the roughness of the different surfaces have considerable implications on several parameters. These parameters include the following: the electric insulation effectiveness, the active area quality, the presence or absence of crystallographic dislocations, and the stability of following treatments.
During the semiconductor substrate 1 plasma etching, the resist layer 4 is also slowly removed. If this layer 4 is too thin, after plasma etching the final structure shows a different geometry with respect to the expected geometry, as shown in FIG. 3.
With respect to the STI insulation manufacturing, if the resist mask 4 is not sufficiently thick to mask the nitride layer 3 during the entire etching step for forming the trench 5, the nitride layer could be reduced in thickness. This would lead, after the CMP step and the thickening and wet etching steps, to a different insulating structure from the one obtained with a layer 3 having a completely regular shape of the nitride layer 3 during the entire etching step.
The resist layer 4 provides for a low side resistance to the plasma etching step. A low side resistance involves, during the etching step, a progressive erosion of the resist layer 4 perpendicularly to the etching direction. Subsequently, this leads to a reduction of the cross dimension of the layer 4 which serves to screen the etching.
As shown in FIGS. 4 to 9, the side dimension of the surface being exposed to the etching constantly increases. The areas covered by the resist layer 4 are progressively exposed to plasma and are thus etched. This derives first a sloped side profile of the nitride layer 3 with a subsequent side reduction (often considerable) of the structure final size f in the nitride layer 3 with respect to the starting size I which was to be defined, as evident from FIG. 9.
In the case of Flash memory cells formed by floating gate transistors and formed with an STI insulation, the manufacturing process is modified as shown in FIGS. 10 to 18. Through this process it is possible to form the floating gate region of floating gate transistors without using a supplementary mask, which could cause misalignment problems with the underlying structures. In particular, these figures are sectional views of a Flash memory portion in a perpendicular plane to the floating gate region direction.
The trench 5 is formed in the semiconductor substrate 1, as previously described. Due to the low side resistance of the resist layer 4, the nitride layer 3 formed on the semiconductor substrate 1 has sloped side walls after the etching step of the nitride layer 3, as shown in FIG. 10. In the Flash memory manufacturing process, after filling the trench 5 with an oxide layer 60 to form an insulating region, the nitride layer 3 is removed.
A semiconductor layer 70 called POLY1 is then formed, which is then planarized through CMP, as shown in FIG. 14. The oxide layer 60 is then partially removed to define floating gate regions. Two further layers are then formed. A first insulating layer 80 called ONO is formed, and a semiconductor layer 90 called POLY2 is formed. The entire stack comprising the semiconductor layer 90, the first insulating layer 80 and the semiconductor layer 70 is then etched through a three-step removal process of the layers POLY2/ONO/POLY1 to expose the substrate 1. It is essential that the etching of the POLY1 layer 70 is performed in a chemically selective way with respect to the insulating layer 80 to preserve a very thin gate oxide layer interposed between the POLY1 layer 70 and the semiconductor layer 1, which is not shown in the figures.
Nevertheless, as shown in FIG. 18, after etching the POLY1 layer 70 definite vertical portions 81 of the ONO layer 80 remain, which are indicated with the term "ONO fences". Since the side walls of the POLY1 layer 70 are not completely vertical, and since the vertical portions 81 are sloping with respect to the semiconductor 1 and they screen, when removing the polysilicon layers 70, 90, a portion of the POLY1 layer 70 thus generates a POLY1 residual 71 with a subsequent short circuit between two adjacent cells.
An important parameter of this memory device manufacturing method, called POLY CMP, is forming a nitride layer 3 whose side profile is vertical. In fact, the side profile of the obtained floating gate regions depends on the nitride layer 3 profile. It even practically takes the same shape thereof.
The problem linked to the low resistance of the resist layer 4, during a plasma removal step of layers underlying this resist layer 4, is more evident the more the memory device size is reduced, such as for example, when using a 193 nm photolithographic technique. In fact, one of the basic features of the photoresist layer being used in the 193 nm photolithographic technique is its low resistance to plasma etching. For the same chemistry being used, the etch rate is generally between 10% and 20% higher than the one being used with traditional photolithographic techniques, such as a 248 nm technique, for example.
This drawback is much more evident when considering the thickness of the resist layer. As the device size decreases, the resist layer should be even thinner to allow reduced-size geometric structures to be focused. For example, the thickness of the resist layer of 5400 Å used in the traditional 248 nm photolithographic technique ranges to a thickness of 3200 Å used in the 193 nm photolithographic technique.
The drawback linked to the low side resistance becomes more critical when etching materials for which a fluoride chemistry (CF4, CH2F2, CHF3, etc.) is required, such as silicon nitride (Si3N4) and silicon oxide (SiO2) layers. In these cases, the etch rate increase is even higher, with values of about 25%–35%.
In the case of an etching step based on a fluoride chemistry, another parameter is very critical: the LER (Line Edge Roughness). Due to the LER, the upper profile of the nitride layer 3, forming the stopping layer, completely rectilinear after the lithography, is turned into a highly ragged profile, as shown in FIGS. 19 and 20.
A first known technical approach to address the above-mentioned problems and meet the need to protect the nitride layer 3 during the plasma etching step of the semiconductor substrate 1 is to interpose an oxide layer 6, called a hard mask, between the nitride layer 3 and the resist mask 4, as shown in FIGS. 21 to 24. Although advantageous under several aspects, this first approach does not succeed in solving the problems linked to the side etch rate and LER, since the etching of the nitride layer 3 is not selective with respect to the hard mask 6.
When two considerably thick layers are to be etched, such as for example, a 600 Å thermal oxide layer 6 and a 1600 Å nitride layer 3, with a necessarily fluorine-based chemistry, the problem of the very low side resistance to the nitride layer etching occurs in a particularly extreme form, even if this layer is protected by an oxide hard mask 6.
The use of the hard mask 6 depends on predetermined factors limiting the use modes of this mask. First of all, the chemistry used in the final part of the semiconductor substrate 1 etching should be selective thereon, otherwise its effectiveness would be limited. Moreover, the hard mask 6 should be formed using a material which can be easily removed (traditionally by wet etching) and without damaging structures which compose the final device. Such a method providing the use of a hard mask is not completely effective.
A further approach for solving the above-mentioned problems provides the use of a hard mask made of a metallic material, such as for example, tungsten, titanium and titanium nitride. In fact, it is possible to selectively etch the silicon nitride layer with respect to the metallic layer. Moreover, the metallic layer can be removed in a wet way.
This approach also has some drawbacks. All the final process steps for forming an electronic device called a frontend should be meticulously preserved from the risk of harmful metallic contaminations for the oxide layers. These oxide layers include the following: HV and LV gate layers, tunnel layer, ONO layer, and active areas, etc. Different technical approaches are involved which considerably increases the manufacturing method complexity.

Method for the fabrication of isolation structures


The present invention discloses a generic approach to the design of single-path, switchless multi-resonant, multi-band power amplifiers. In the preferred embodiments, the amplifier includes one or more amplification stages, a switchless, multi-resonant, input impedance network, a switchless, multi-resonant, output impedance network, and if multi-stage, a switchless, multi-resonant, interstage impedance network between each amplification stage. Multi-band amplification is accomplished without the need for externally-applied, frequency-indicating control signals. Moreover, the amplifier may be designed to provide concurrent multi-band amplification or non-concurrent amplification.

Multi-band wireless transceiver systems have been proposed to address an increasing demand for bandwidth enhancement and flexibility of wireless telecommunication systems. Many different standards for such systems are currently in use around the world. Each of these standards sets forth specifications for various aspects of the communication link, such as the frequency of the transmitted signal, its spectral purity to avoid interference with other services and the scheme used for encoding information in the signal. Examples of different systems currently in use are the GSM900 mobile communication system popular in Europe and parts of Asia and the PCS1900 system in North America. Many other systems are used for various purposes, and most of these systems specify a different frequency for operation.
The use of different standards in different or even the same area on the globe creates challenges to system providers who would like to offer flexible systems capable of complying with a multitude of the standards in use. The increased flexibility of such multi-band communication systems can potentially provide various benefits to the end-user. For example, a dual-band cellular phone complying both with the GSM900 and the PCS1900 systems can use these services in North America, Asia and Europe, and its user would not be required to use a different phone when traveling outside its service area. Another application could be a communication system that uses different standards in the same area depending on outside circumstances such as to select the best frequency band that offers the best reception. Other possible applications are systems that use different frequency bands for different functionalities, such as equipment combining a GSM900 cellular phone with a global-positioning system (GPS) device. Many such applications are possible.
In wireless transmitters, signal amplifiers are often tuned for the frequency of intended operation. Tuning provides improved operation with respect to the gain provided by the amplifier, the spectral purity of the amplified signal, and the mode of operation (e.g. Class, A, Class AB, Class B and Class F, among others), all of which are designed to comply with the communication standards set for the intended use. Furthermore, tuning may also allow more efficient operation with respect to power consumption than can be achieved by broadband amplifiers.
Thus, communication systems designed to transmit signals at a multitude of frequencies must be able to amplify signals at each one of these frequencies. This is hereinafter called "multi-band" amplification.
Various design strategies have been disclosed in the art that ostensibly expand the functionality of power amplifiers that are designed into wireless transmitters. For example, U.S. Pat. No. 5,060,294 to Schwent et al. describes a dual-mode power amplifier. A dual-mode power amplifier is an amplifier operating in one of two different modes in a single frequency band. Such an amplifier, however, is not capable of operating in more than one frequency band, but rather is capable of being operated either in linear (analog) mode or saturated (digital) mode, thereby improving the utility of the amplifier for applications requiring differently modulated signals.
U.S. Pat. No. 5,774,017 to Adar describes a dual-band power amplifier, defined as an amplifier that tunes a signal at two frequencies of operation. This is accomplished by applying an external frequency-indicating control signal to the networks, and more specifically by (1) selectively coupling the signal to a variety of impedance networks; or (2) selectively coupling the signal to parts of the impedance networks; or (3) by changing component impedances in the impedance-tuning networks used in the amplifier, depending on the signal frequency.
In general, selective coupling can be achieved in several conventional ways. In one method, active components are used, namely, components that act as switches or variable conductors controlled by a signal indicating the frequency of signal. In a second method, filters connected in parallel are employed, such that each of these filters accept a signal at only one frequency and reject signals at all other frequencies. In this way, a signal is routed through only one of the filters depending on the frequency of the signal. This latter method is known as diplexing.
Unfortunately, designs involving techniques of selective coupling as mentioned above, however, suffer from several drawbacks. Techniques employing switched networks or diplexers use some or all components in the networks only for one frequency band, hence they tend to employ more components than is desirable. Reducing the components count can directly benefit a system's cost and reliability. Moreover, switches used to route the signal introduce losses while offering little other functionality. Finally, techniques using selectively coupled networks or selectively controlled component impedances, are inherently incapable of amplifying signals in more than one frequency band at the same time.
Thus it would be highly desirable to have a multi-band power amplifier design that minimizes component count and that does not rely on selective coupling or diplexing.
Recent advances in design methodology of dual-band receivers, and in particular of dual-band low-noise receiver amplifiers, have shown improvements in existing functionality of dual-band low-noise receiver amplifiers as well as introducing the possibility for concurrent dual-band operation by the use of inherently dual-resonant impedance networks instead of selective impedance network coupling or network impedance controlling schemes such as described in U.S. Pat. No. 5,774,017.
It is therefore an object of the invention to provide a switchless multi-resonant, multi-band power amplifier that can operate without any frequency indicating control signal schemes.

Switchless multi-resonant, multi-band power amplifier


An anchor key generation method, device, and system, where the method includes generating, by a unified data management network element (UDM), an intermediate key based on a cipher key (CK), an integrity key (IK), and indication information regarding an operator; sending, by the UDM, the intermediate key to an authentication server function (AUSF); receiving, by the AUSF, the intermediate key; generating, by the AUSF, an anchor key based on the intermediate key; sending, by the AUSF, the anchor key to a security anchor function (SEAF); and generating, by the SEAF, a key (Kamf) based on the anchor key, where the Kamf is used to derive a 3rd Generation Partnership Project (3GPP) key.

A key is critical to an encryption operation, a decryption operation, and a cryptosystem. Therefore, in an information security system, key negotiation is an important part in an authentication process. FIG. 1 shows a key negotiation process in an existing fourth generation (4G) system. Network elements required for executing the process include a user equipment (UE), an evolved NodeB (eNodeB), a mobility management entity (MME), a home subscriber server (HSS), an authentication center (AuC), and the like. The execution process is roughly as follows below.
Step 1: The AuC generates an integrity key (IK) and a cipher key (CK) based on a root key K, and sends the IK and the CK to the HSS. Correspondingly, the HSS receives the IK and the CK sent by the AuC.
Step 2: The HSS generates an intermediate key (KASME) based on the IK and the CK, and sends the KASME to the MME. Correspondingly, the MME receives the KASME sent by the HSS.
Step 3: The MME generates, based on the KASME, a non-access stratum (NAS) integrity key (KNAsenc) or performing encryption protection on an NAS message, and a NAS integrity protection key (KNASint) for performing integrity protection.
Step 4: The MME generates a base station key (KeNB) based on the KASME, and sends the KeNB to the eNodeB. Correspondingly, the eNodeB receives the KeNB sent by the MME.
Step 5: The eNodeB separately generates, based on the KeNB, a user plane cipher key (KUPenc) for performing encryption protection on user plane data, a user plane integrity key (KUPint) for performing integrity protection on the user plane data, a control plane cipher key (KRRCenc) for performing encryption protection on control plane data, and a control plane integrity key (KRRCint) for performing integrity protection on the control plane data.
Step 6: The UE generates by itself an integrity key (IK), a cipher key (CK), an intermediate key (KASME), a user plane cipher key (KUPenc a user plane integrity key (KUPint), a control plane cipher key (KRRCenc), and a control plane integrity key (KRRCint) based on the root key K.
After the key negotiation process shown in FIG. 1 is completed, a key architecture shown in FIG. 2 is generated in the 4G system.
It may be understood that FIG. 1 shows a key negotiation process in a process of accessing a core network by a terminal in a 3rd Generation Partnership Project (3GPP) access mode in a 4G application scenario. To meet requirements of various application scenarios, the terminal may access the core network in various different access modes, for example, a 3GPP access mode, a trusted non-3GPP access mode, and an untrusted 3GPP access mode. In different access modes, key negotiation processes are also different. In a fifth generation (5G) standard, it is specified that one unified anchor key needs to be generated in key negotiation processes of different access modes, in order to implement compatibility with various access modes. However, how to generate the unified anchor key is a problem that a person skilled in the art needs to resolve.

Anchor key generation method, device, and system


An anvil assembly for use with a circular surgical stapler is disclosed. The anvil assembly includes an anvil body, an anvil disposed around the anvil body and engaged therewith, and a tether line having a first end connected to the anvil body and a second end connected to the anvil. The anvil assembly is configured so that upon completion of the stapling operation, the anvil is disengaged from the anvil body, rotated, and withdrawn from the patient via the tether line. A method of using the anvil assembly is also disclosed.

1. Field of the Invention
This invention relates to an instrument and method for circular surgical stapling of hollow body organs, and more particularly, to an improved anvil assembly having a tether line for retrieving a disengaged anvil portion from the hollow body organ after stapling.
2. Description of the Prior Art
There are several known types of surgical staplers in which the stapling function takes place at a location which is relatively remote from the location at which the stapler is held and actuated by the operator. One example of such a stapler is the circular anastomosis surgical stapler shown illustratively in Conta et al. U.S. Pat. No. 4,304,236. Typically, in instruments of this type exemplified by this reference, tissue to be stapled is clamped between an anvil assembly and a staple holding assembly, both of which are located at the distal end of the instrument. The clamped tissue is stapled by driving one or more staples from the staple holding assembly so that the ends of the staples pass through the tissue and are clinched by contact with the anvil assembly. The forces required to operate the instrument are applied by the operator of the instrument to one or more actuator elements located at or near the proximal end of the instrument. The distal and proximal portions of the instrument are joined by a longitudinal connecting shaft structure along which the actuating forces and motions are transmitted to the distal operating elements.
In use in the typical application of joining two intestinal sections together, instruments of the type mentioned above are first positioned so that the staple holding assembly is inside the end of a first intestinal section and the anvil assembly is inside the end of a second intestinal section. The severed ends of the intestinal sections are typically secured by purse strings and then clamped between the staple holding assembly and the anvil assembly. The instrument is then operated so as to drive staples from the staple holding assembly through the clamped tissue, and against an anvil portion of the anvil assembly. The same operation of the instrument which drives the staples also drives a knife to cut away the waste or excess tissue inside the annular array of staples and thereby clear the lumen between the connected organ sections.
The joining of the intestinal sections now complete, the instrument can be removed. To remove the instrument from the stapled tissue, the anvil assembly is typically moved away from the staple holding assembly so that the tissue is no longer clamped by the instrument. The entire instrument is then pulled out of the first intestinal section.
In withdrawing the instrument, the anvil portion of the anvil assembly is withdrawn past the stapled tissue. Since the outer circumferential surface of the anvil has a diameter greater than that of the intestinal sections at the point where the intestinal sections have been recently stapled, the stapled tissue is stretched by the contact of the anvil with the stapled tissue. Reducing contact between the full circumference of the anvil and the stapled tissue, can decrease the degree of stretching of the newly stapled tissue.
In view of the foregoing, there is a need to provide an anvil assembly, and method of using same, which facilitates withdrawal of the anvil assembly from a hollow body organ. There is also a need for an anvil assembly which minimizes stretching of tissue upon withdrawal.


A compliance user or auditor is enabled to inject failures into a sandbox environment, which may be similar to a production service. The sandbox environment may be monitored by the same automation that watches compliance controls in the production service. As the user injects compliance failures into the sandbox, they may detect the appropriate alerts fire in the monitoring system, thereby gaining trust that the monitoring works as it should. A rich report resulting from the test activities may allow the user or auditor to see how a failure of a compliance control leads to the expected monitoring alert.

The proliferation of computerized automation of processes in every aspect of life, data storage and processing have become a major component of networked systems handling financial and other transactions. In such systems, data is entered, modified, or deleted from a number of sources. The same data is maintained in multiple data stores in same or different formats, and a data store has to pick up or synchronize changes to data based on changes in a different store. Various data stores from simple tables to complicated databases is maintained and synchronized as new entries or modifications are made by different sources. The changes are synchronized at regular intervals. In addition, variety of services are offered to enable internal and external parties' interactivity with the data hosted by the data stores. Consumers of the data as well as providers usually demand certifications associated with the services to enable compliance-associated processes between the parties.
In maintaining a compliant cloud service, providing proof of compliance to compliance customers is part of the process. The proof may need to include a showing that the compliance controls implemented on the service are actually operating as expected. Conventional systems employ an independent third party (an auditor) to collect evidence from a sample of service components and test them manually. For example, records from 10% of servers may be collected and examined for an indication of compliance. Due to the scale in cloud services, however, even small samples (e.g., 1% or servers) may mean testing thousands of objects. Approaches that provide automated testing in the environment (providing a report of aggregated test results to determine compliance) face the challenge that for customers or auditors, the automation is a black box—they do not have any reason to trust that it is in fact testing the compliance controls in an effective way.

This patent is subject to a terminal disclaimer.

Compliance testing through sandbox environments


An actuator unit for an electro-hydraulic brake system of the ‘brake-by-wire’ type, the first and second pistons thereof being preloaded by a resetting spring each in opposition to the actuating direction. The first pressure chamber of the tandem master cylinder is connected to a hydraulic chamber limited by a simulator element. On the other hand, the simulator element defines a simulator chamber that accommodates a simulator spring and is connected to a pressure fluid reservoir. A valve device is provided to open or close the hydraulic connection between simulator chamber and pressure fluid reservoir. To increase the reliability in operation of a hydraulic fallback mode, at least one channel portion through the pressure chamber, closed at the edge at least in areas, is provided for the purposeful removal of pressure fluid contaminants by means of a compulsory pressure fluid scavenging operation.

DE 198 22 411 A1 discloses an actuator unit of this general type.
Because a vehicle operator is decoupled from the physical generation of brake force in electro-hydraulic brake systems (EHB) and the braking demand is realized electrically 'by wire', a travel simulator is used reproducing the tactile pedal feedback which simulates the reaction force of a conventional brake system. In addition, the actuator unit includes means allowing a hydraulic emergency braking operation when the electronics is defective by means of direct application of the wheel brakes (so-called hydraulic fallback mode). Outside the hydraulic fallback mode a request for actuation is detected in the by-wire mode as a result of sensing e.g. an actuating travel of the brake pedal, and separating valves are closed to shut off the direct hydraulic throughgrip in the direction of the wheel brakes. While the braking pressure buildup is initiated in an electrohydraulic fashion, a reaction force is imparted to the vehicle operator due to a volume displacement into the travel simulator corresponding to the actuating movement.
The hydraulic fallback mode is of utmost importance. Air that is drawn into the hydraulic circuit (due to leakages or the like) can impair or prevent the functioning of the hydraulic fallback mode because the pressure fluid when mixed with air) reacts compressibly. The minimum requirement of an emergency braking operation as mandated by law—without servo boosting—is not reached. Any air that enters the system will migrate to the highest points of the brake system. Preferred concentration points are the pressure chambers, what is due to a principally inclined mounting position of the actuator unit in the motor vehicle.
The above-mentioned publication does not disclose measures that would allow eliminating or significantly reduce a malfunction that occurs in by-wire brake systems, which is caused by compressibility (or other contamination).
Patent application DE 10147180.7, which is not prior-published, discloses an electronically controllable brake actuation system with means for the electronically controlled separation of contaminants contained and/or dissolved in the brake fluid.

Actuator unit for an electro-hydraulic brake system


To improve an S/N of an AM signal in a diversity reception circuit while suppressing an increase in a circuit size of A/D conversion circuits therein. In the diversity reception circuit, a single AM signal is supplied to each of the A/D conversion circuits provided for A/D converting a plurality of FM signals, and a plurality of obtained results of the conversions are added by an adding circuit, thereby improving the S/N.

In recent years, a diversity reception technique, which is a method of receiving electric waves by a plurality of antennas, respectively, and selecting an antenna in a best reception state, thereby increasing reception sensitivity, has attracted attention. This technique is used to avoid fading. The fading is a phenomenon in which when an electric wave propagates through a space, the electric wave is strengthened or weakened depending on a location due to interference caused by a reflected wave from a terrain or building. As the frequency of the electric wave is increased, the influence caused by the fading increases (the intensity of the electric wave is increased or decreased in a narrower range). Accordingly, the effect of diversity reception is increased. For this reason, the diversity reception technique is employed in case where an FM broadcast with a high frequency is received by a radio. On this occasion, signals received by the respective antennas are digitized for comparison. A plurality of A/D converters having the same performance thus becomes necessary (refer to Patent Document 1).
There is also a demand to increase conversion accuracy though there is no need to perform multiple receptions. Take, for example, radio reception again. Noise immunity of an AM broadcast is lower than the FM broadcast. In other words, in FM, information is represented by a change in frequency, while in AM, the information is represented by the change in amplitude. When an external noise is included, the amplitude is more influenced by the external noise or the amplitude has a lower noise immunity. Accordingly, a high signal-to-noise (S/N) ratio is required. On the other hand, the frequency of the AM broadcast is low. Thus, the effect obtained by the diversity reception is low, so that only one system of an A/D converter suffices.


A system and method provide for relaying a medical device alarm to a remote location without having a device electrically interconnected with the medical device. The system includes a relay device having software that can store specific alarm patterns or sequences for one or more alarms for a medical device. The relay device can then detect one or more of an audible, visual or tactile alarm from the medical device through corresponding devices or sensors in the relay device. Upon detection of an alarm, the relay device can transmit information pertaining to the alarm to a remote device to notify a user of the remote device of the medical device alarm.

Many medical devices include monitoring systems that monitor various conditions and provide alarms in response to various predetermined events. Such monitored conditions and events can, for example, pertain to the medical device itself, such as battery level, or to the patient being treated with the medical device, including a number of physiological parameters or conditions of the patient.
With the increase in home and self medical care, these alarms must be monitored by patients themselves rather than trained medical personnel. In the case of a child or other individual needing another to oversee medical assistance, such alarms need to be monitored by a caregiver such as a parent or other adult. In such situations, monitoring of medical device alarms at night while members of the household are asleep can be particularly challenging given that the caregiver responsible for the patient will generally be sleeping in a room separate from the patient and associated medical device and therefore may not hear an alarm or alert from the medical device.
Therefore, there is a need for a system and a method that aids in alerting a parent or other caregiver to a medical device alarm condition of a child or other individual whose treatment is the responsibility of the parent or other caregiver when the medical device is in a remote location.

System and method for detecting and transmitting medical device alarm with a smartphone application


A cooling tray includes a container, springs placed within the container to exerting a vertical thrust, a platform residing within the container and coupled to each spring, and a bowl for residing above the container. When ice is placed on the platform, the plurality of springs are each compressed such that the cooling material contacts an undersurface of the bowl. As the ice melts, the water flows below the platform, and the springs decompress and maintain the remaining ice in contact with the undersurface of the bowl. In this manner, food that requires refrigeration may be served from the portable cooling tray at the appropriate temperature. A formed ice block may be used to impart greater and more efficient cooling as a greater surface area of the ice contacts the undersurface of the bowl. The bowl may be of aluminum to further increase the efficiency.

In the food service industry, storing food at the proper temperature is important for food safety. For example, U.S. Food and Drug Administration regulations require refrigerated food to be stored at 40° F. or below. This requirement applies when the food is being served as well. Often, the food service is to be portable, such as for the catering of events. However, existing portable devices for serving refrigerated food is inadequate for maintaining the food at the required 40° F. or below. These existing portable devices either are not able to lower the temperature of the food to the required temperature or are unable to maintain the temperature consistently. Often, food servers either opt to not serve food that requires refrigeration, place food plates directly onto a bed of ice, or use bulky, expensive and/or non-portable devices that require electricity.


A system and method of producing a bold character from a base character which has been transformed in orientation, size, or both, the method comprising overstriking the transformed character non-orthogonally, asymmetrically, or both, to produce the bold character. A preferred embodiment for overstriking the transformed character non-orthogonally, asymmetrically, or both, includes overstriking the transformed character relative to the CTM. Further, overstriking the transformed character relative to the CTM preferably includes (a) determining a multistrike quantity representative of a number of offset overstrikes, (b) determining a horizontal vector and a vertical vector, relative to the fixed reference point, based on the multistrike quantity, (c) transforming the horizontal vector into a transformed horizontal vector and the vertical vector into a transformed vertical vector, using the CTM, and (d) overstriking the transformed character at points along the transformed horizontal vector and transformed vertical vector to produce the bold character.

Far East fonts are very large compared to fonts for western languages. There can be as many as 30 times as many characters in a Japanese, Korean, or Traditional or Simplified Chinese font as in a font containing just Latin 1, 2, and 5 character sets. Computer products such as operating systems and printers which contain western fonts usually include complete font families, i.e., base, italic, bold, and bold italic. However, products containing Far East fonts frequently only include the base fonts but do not include complete font families, due to the large size, cost, and time required to design those fonts. These products usually implement algorithmic enhancements (e.g., shearing, double-striking) to create italic and bold characters. Character glyphs created this way are not typographically correct but are adequate for most users of these products. For purposes of this discussion, bold character glyphs created by algorithmic means will be referred to as "pseudo-bold" characters.
Prior approaches to creating pseudo-bold characters include double striking and multistriking of the base characters. In the double-strike approach, a character is printed twice, once at the normal position and once offset one pixel to the right. This solution is common in low-resolution devices such as dot-matrix printers and video display drivers. The disadvantage of this solution is that it does not adjust for variable point size and resolution. As a result, on high-resolution devices or at large point sizes, a double-struck character is not noticeably bolder than the original character.
In the multistrike approach, the character is overstruck multiple times with variable offsets in the horizontal (X) and vertical (Y) directions. The number of times a character is overstruck in each direction is proportional to its point size and the resolution of the device. For example, if a 10-point character on a 300 dots per inch (dpi) device is overstruck 2 times in both the X and Y directions, then a 20-point character at 300 dpi would be overstruck 4 times (double point size) and a 10-point character at 600 dpi would also be overstruck 4 times (double resolution.)
In a typical multistrike implementation for a printer, the pseudo-bold character is constructed as a bitmap image in RAM before it is printed. The process of creating a pseudo-bold character starts with the original (base) character as a bitmap image. A temporary memory block large enough to hold the base character overstruck n times in the X direction (where n is the multistrike quantity) is allocated. Then the base character is copied into the temporary memory block n times offset by one pixel to the right each time. This has the effect of overstriking the character n times to the right. Then a new memory block large enough to hold the pseudo-bold character is allocated. Then the image in the temporary memory block is copied into the new memory block n times offset by one pixel up each time. The new memory block now holds the pseudo-bold character ready for printing, and the temporary memory block is deallocated.
Stated otherwise, for example, using pixel coordinates where x increases to the right and y increases toward the top of the page, assume the base character is printed at (0,0). The conventional multistrike method overstrikes a base character n times along the X-axis, moving the character one pixel to the right with each overstrike, resulting in an intermediate bitmap. That is, the character is overstruck at (1,0), (2,0), . . . , (n,0). Then the conventional multistrike method repeats the process with the intermediate bitmap, overstriking it n times along the Y-axis, which creates the pseudo-bold character. That is, the resulting intermediate bitmap is overstruck at (0,1), (0,2), . . . , (0,n).
The conventional multistrike method is limited. For non-orthogonal orientations or asymmetrical scaling of the base character, the multistrike method produces a pseudo-bold character which is not true to the shape of the base character.
Accordingly, objects of the present invention are to provide a new system and method for creating pseudo-bold characters at arbitrary orientations (including non-orthogonal orientations), scaling (including non-asymmetric scaling), point sizes, and device resolutions.

Method for printing pseudo-bold characters at arbitrary orientations, scaling, and resolutions


An embodiment of the invention relates to an engine system, and a method in an engine system comprising an internal combustion engine having at least one cylinder (2) at which a piston (3), at least one inlet valve (5), at least one exhaust valve (7), and fuel injection means (11), for injection of fuel directly into the cylinder (2), are provided. The method comprises performing the following steps in at least one of the at least one cylinder: controlling (204) at least one of the at least one intake valve (5) so as to introduce air into the cylinder (2), performing (203, 206) at least one main combustion fuel injection (P21, P22) for a main combustion with air introduced into the cylinder (2), controlling (201), during an exhaust stroke and an intake stroke, the intake and exhaust valves (5, 7) so as to form a negative valve overlap (NVO) to capture main combustion residues, and performing (202) at least one pilot fuel injection (P1) during the negative valve overlap. The amount of fuel in the at least one pilot fuel injection (P1) is at least partly dependent on said introduction of air and at least one of the at least one main combustion fuel injection (P21, P22).

In Homogenous Charge Compression Ignition (HCCI) operation of internal combustion engines, the temperature of the charge for the combustion should not be too low. If the temperature is too low, the combustion will be phased lately, resulting in a lower efficiency, and if even later also increased carbon oxide (CO) and hydro carbon (HC) emissions. At an even lower temperature, the combustion will fail to appear, i.e. there will be a misfire, resulting in decreased comfort for persons in a vehicle in which the engine is operating.
In order to solve this problem, U.S. Pat. No. 7,194,996B2 suggests in a direct fuel injection engine during HCCI operation performing a pilot fuel injection during a negative valve overlap at an exhaust stroke and an intake stroke of the piston, in order for the pilot fuel to react with residuals from a previous combustion. Subsequently, air and additional fuel are introduced during the intake stroke and/or a compression stroke for the main combustion. The purpose of the pilot fuel and residual reaction is to heat the charge for the subsequent main combustion. The heated charge will prevent the main combustion from occurring too late.
Although this known method has proven advantageous, there is still use for a solution increasing the combustion control at HCCI operation. For example, a reaction with the fuel from the pilot injection requires a presence of oxygen in the residuals, and therefore the preceding main combustion has to take place with a lean mixture so that there is a surplus of air, some of which is retained during the negative valve overlap. However, the inventors have discovered that an excess of pilot fuel, providing a rich mixture with the air in the residuals, has a cooling effect on the charge for the subsequent main combustion.
Thus, in one embodiment, a method for an engine system is provided, the engine system including an internal combustion engine having at least one cylinder at which a piston, at least one inlet valve, at least one exhaust valve, and a fuel injector for injection of fuel directly into the cylinder. The method comprises performing the following in at least one of the at least one cylinder:                controlling at least one of the at least one intake valve so as to introduce air into the cylinder,        performing at least one main combustion fuel injection for a main combustion with air introduced into the cylinder,        controlling, during an exhaust stroke and an intake stroke, the intake and exhaust valves so as to form a negative valve overlap to capture main combustion residues, and        performing at least one pilot fuel injection during the negative valve overlap; and        where an amount of fuel in the at least one pilot fuel injection is at least partly dependent on said introduction of air and at least one of the at least one main combustion fuel injection
In this way, it is possible to ensure that the pilot fuel amount is not in excess in view of the oxygen amount in the residuals, in order to avoid un-oxidized pilot fuel to cool down the charge for the next main combustion. Thus, it is possible to improve combustion stability at homogenous charge compression ignition operation of an internal combustion engine. Further, it is also possible to increase efficiency at homogenous charge compression ignition operation of an internal combustion engine. Further still, it is possible to decrease emissions at homogenous charge compression ignition operation of an internal combustion engine. Finally, it is also possible to to reduce risks of discomfort for persons in a vehicle in which the engine is operating with homogenous charge compression ignition.
Also, by the above operation it can be ensured that enough pilot fuel is injected in view of the oxygen amount in the residuals in order to reach enough heating of the charge for the main combustion.
A late main combustion at HCCI operation will reduce the combustion efficiency and the thermodynamic efficiency. By avoiding cooling of the main combustion charge, risks of a late main combustion are reduced, which will increase engine efficiency, reduce fuel consumption, and reduce risks of increased CO and HC emissions. Also, passenger comfort in a vehicle in which the engine is operating is secured, since risks of misfire will be reduced.
Regarding the different steps of the example method, the step of performing at least one main combustion fuel injection for a main combustion could be done by performing the at least one main combustion fuel injection during an intake stroke and/or during a compression stroke of the piston. The step of controlling the intake and exhaust valves to form a negative valve overlap to capture residues from the main combustion, can be carried out by closing the exhaust valve during an exhaust stroke of the piston following immediately upon a power stroke of the piston, in turn following immediately upon said compression stroke, and opening the intake valve during an intake stroke of the piston following immediately upon said exhaust stroke, to form a negative valve overlap between said exhaust valve closing and said intake valve opening.
It should be noted that the intake stroke and the power stroke are defined as periods during which the piston moves downward from the top dead centre (TDC) position to the bottom dead centre (BDC) position, regardless of positions of the inlet valve(s) and the exhaust valve(s) during this downward movement. Similarly, the exhaust stroke and the compression stroke are defined as periods during which the piston moves upward from the BDC position to the TDC position, regardless of positions of the inlet valve(s) and the exhaust valve(s) during this upward movement.
In another example, the method may comprise:                introducing a first amount of air into the cylinder,        performing the at least one main combustion fuel injection for a main combustion with air in the first amount of air,        capturing, during the negative valve overlap, residues from the main combustion, and        determining the amount of fuel in the at least one pilot fuel injection at least partly based on said first amount of air and the amount of fuel injected in at least one of the at least one main combustion fuel injection.
This means that each pilot fuel can be determined at least partly based on the amount of fuel injected and the amount of air introduced for the main combustion preceding the pilot fuel injection, which will result in a very accurate fuel amount determination.
The first amount of air can be introduced into the cylinder by controlling the intake valve so as to be open during at least a part of an intake stroke and/or during a part of a compression stroke of the piston. The introduced amount of air can be the amount of air allowed into the cylinder, or the amount of air captured in the cylinder. If the intake valve closes in the compression stroke, some air allowed into the cylinder may be pushed back into the air intake duct, and thereby the mount of air allowed into the cylinder and the amount of air captured in the cylinder would differ. Which of these amounts correspond to the amount of air introduced into the cylinder, as stated in claim 1, would depend on the manner in which air transportation to the cylinder is determined. The introduced amount of air may be regarded as the amount of air captured in the cylinder.
In still another alternative, the method comprises:                determining a flow of air into the cylinder,        determining a flow of fuel for a plurality of main combustion fuel injections for a plurality of main combustions with air introduced into the cylinder, and        determining the amount of fuel in the at least one pilot fuel injection (P1), at least partly based on the flow of air and the flow of fuel for the plurality of main combustion fuel injections (P21, P22).
For example, the amount of fuel in the at least one pilot fuel injection can be determined based on a flow of fuel for a plurality of pilot fuel injections, in turn determined at least partly based on the flow of air and the flow of fuel for the plurality of main combustion fuel injections.
In the art, the ratio, between the actual air/fuel ratio and the stoichiometric air fuel ratio, is referred to as the lambda value. The amount of fuel in the at least one pilot fuel injection may be such that the lambda value of a charge with the amount of fuel in the at least one pilot fuel injection and a second amount of air in the residues from the main combustion captured in the negative valve overlap is higher than a predetermined lambda threshold value. In one example, the predetermined lambda threshold value is 1. Thereby, it is ensured that substantially all pilot fuel will be consumed in a reaction with oxygen in the residuals, so that un-oxidized pilot fuel will not cool down the charge for the next main combustion.
The amount of fuel in the at least one pilot fuel injection may be such that said lambda value is within the range of 1.0-1.6. Keeping the lambda value within this range will secure avoiding said cooling effect and still provide enough pilot fuel to obtain a reaction with residual oxygen for a sufficient heating of the main combustion charge.
Additionally, one of the at least one main combustion fuel injection is a first main combustion fuel injection and another of the at least one main combustion fuel injection is a second main combustion fuel injection, the amount of fuel in the at least one pilot fuel injection being determined partly based on the first and second main combustion fuel injections. Thereby, where there are a plurality of main combustion fuel injections for each main combustion, based on the amount of air and the total amount of fuel injected for the previous main combustion, it is possible to properly determine the amount of oxygen in the trapped residuals at the pilot injection. As exemplified below, the first main combustion fuel injection can be a main fuel injection effected at the intake stroke during the negative valve overlap and after a reaction between a previous pilot injection and residual oxygen, and the second main combustion fuel injection can be a post fuel injection effected during the subsequent compression stroke shortly before the main combustion.

Internal combustion engine system, and a method in such an engine system


An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.

1. Field of the Invention
The present invention relates generally to a floating gate memory cell, and more particularly, to an air tunnel floating gate memory cell and a method for making such a memory cell.
2. Description of the Related Art
As shown in FIG. 1, a conventional floating gate memory cell 100 includes a substrate 110 with doped source 120 and drain 130. A tunnel oxide layer 140 is situated between a floating gate 150 and the substrate 110. An oxide-nitride-oxide (ONO) stack 160 is disposed over the floating gate 150, and a control gate 170 is formed over the ONO stack 160.
The conventional floating gate memory cell 100 uses the tunnel oxide layer 140 as an insulator layer to preserve the charge stored at the floating gate 150. The thickness of the tunnel oxide layer 140 is usually greater than 7 nm. The tunnel oxide layer 140 also serves as a charge transport media for the program/erase operation of the conventional floating gate memory cell 100. However, after a large number of program/erase cycles, the large quantities of injected charge through the tunnel oxide layer 140 induce severe stress-induced leakage current (SILC), leading to the degradation of the tunnel oxide layer 140. The degradation of the tunnel oxide layer 140 will slow down the program/erase speed and reduce the charge retention ability of the floating gate 150 of the conventional floating gate memory cell 100.
In order to enhance the program/erase speed of the conventional floating gate memory cell 100, a larger electric field can be applied to the conventional floating gate memory cell 100. However, the larger electric field will cause more severe degradation of tunnel oxide layer 140. Therefore, the tunnel oxide layer 140, having a program/erase speed upper bound, limits the performance of the conventional floating gate memory cell 100.
In view of the foregoing, there is a need for an improved floating gate memory cell that will enhance the performance and avoid the problems of a conventional floating gate memory cell.


The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path. Then, the synchronizing signal detection circuit acquires detection positions of synchronizing pulses of the synchronizing signals of every path, selects a synchronizing signal of every path at which a difference in time between each of the detection positions of every path and the predicted detection position is minimal, and sets the selected synchronizing signal as an output synchronizing signal.

The present invention relates to a synchronizing signal detection circuit which detects a corresponding synchronizing signal from a video signal including synchronizing signals.
A patent document 1 (Japanese Unexamined Patent Publication No. 2001-275014) has disclosed a video signal processing device which, even though a pedestal level of an analog video signal inputted thereto varies, outputs a digital video signal whose pedestal level is always controlled to a preset black level. Using such a device makes it possible to avoid abnormalities in the hue of a reproduced image.
Meanwhile, a synchronization failure or error such as video blurring caused by an inability to accurately detect a synchronizing signal contained in a video signal due to the influence of high-frequency noise or the like becomes a problem as well as a problem associated with an abnormality in brightness such as a hue abnormality that causes an abnormality in video reproduction.
FIG. 1 shows a synchronizing signal detection circuit for a conventional video signal. In the figure, an input video signal S10 inputted from a video signal input terminal 10 is inputted to an IIR filter unit 11. The IIR filter unit 11 outputs a video signal S11 obtained by eliminating high-frequency noise components from the input video signal S10. The video signal S11 is inputted to a synchronizing signal extraction unit 21, which detects a synchronizing signal contained in the video signal S11 and outputs it as a synchronizing signal S21.
However, error detection of a synchronizing signal still occurs depending on such related arts. Since the difference in level between effective data and a synchronizing signal is large where, for example, the end of an effective data period of a video signal is terminated at high-brightness data, the synchronizing signal is rounded in its waveform and erroneously detected depending on the effective data when it is caused to pass through an IIR filter. The error detection of the synchronizing signal leads to synchronization errors and becomes the cause of occurrence of video blurring.


A sonar buoy adapted to be deployed by a cruise missile. This sonar buoy includes a flotation device for keeping a portion of the buoy afloat, a hydrophone, a transmitter for communicating contact and position information and releasable means for attaching the sonar buoy to the cruise missile. By means of this device, a means of monitoring littoral and other waters for enemy submarines and other threats is provided with a low degree of risk to friendly forces. A system for deploying this sonar buoy in a sonar buoy field is also disclosed.

(1) Field of the Invention
The present invention relates to acoustic wave systems and devices, and more particularly to sonobuoys with component activating or deployment means.
(2) Brief Description of the Prior Art
Expanding mission requirements caused by the increased frequency of regional conflicts and state-sponsored terrorism, have forced fast attack submarines into littoral operations. Submarines are well suited for this type of mission, allowing on-station, forward deployment, without the vulnerability, or force telegraphing of a surface ship and the associated political and tactical ramifications. Whether alone, or acting in conjunction with a battle group, the submarine will increasingly be called on to patrol and prosecute hostile contacts in this challenging environment as well as deliver precision missile strikes on inland targets.
Hostile submarines are a serious threat to friendly submarines, as well as to friendly surface ships. One such danger comprises diesel-electric type submarines, commonly known as diesel boats. While relatively cumbersome for extended, deep-water operations, diesel boats are well suited for coastal defense in the littoral regions. Relatively small, inexpensive and quiet (when operating on battery power), diesel boats can lie in wait for an approaching battle group, or patrol quietly just off the shore in search of submarines and surface craft.
While fast attack submarines possess many operational advantages, there are still considerable risks associated with entering shallow or xe2x80x9cbrownxe2x80x9d water to search for enemy submarines. A nuclear-powered fast attack submarine would prove a priceless propaganda trophy for any hostile country. Many of the same risks would attend operations by surface ships in such waters.
Another submarine hunting method is using an Anti-Submarine Warfare (ASW) helicopter launched from a surface ship at standoff distance. This method, however, also entails considerable risk due to the amount of time the helicopter must spend hovering, while dipping sonar to locate the hostile submarine, leaving it seriously vulnerable to fire from shore or from small craft.
The prior art also discloses the use of buoys or other discrete deployable devices for housing a sonar apparatus or other sensors that may be used to monitor an area for hostile submarine threats. U.S. Pat. No. 4,186,374 to Ouellette, for example, discloses a transducer housing for an air dropped sonar transducer including a smooth cylindrical case for stowage on board an aircraft. The case is formed with a separation device, which permits ejection of the transducer from the case upon impact with the surface of the ocean, the device being formed of tabs on the case and chamfers on a cover plate of the case. The impact of the water on the cover plate is directed by the chamfers against the tabs to spread them apart thereby releasing the cover plate and the transducer. Pins on the cover plate project through apertures in the tabs and press against the side of the apertures with a preset force to essentially lock the tabs to the plate until the preset force is overcome by the water impact.
U.S. Pat. No. 5,691,957 to Spiesberger discloses an acoustic tomography telemetry system and method that allows spatially averaged ocean temperatures to be measured in real-time. This system includes autonomous acoustic sources mounted on subsurface mooring and receivers that are either suspended from drifting surface buoys or cabled to shore. The telemetry method largely eliminates, in real-time, corruption of acoustic travel times due to wander of the source""s mooring by shifting the start times of tomographic transmissions. Corrections to source wander are obtained without expending battery energy over and above that used in conventional tomography experiments. Standard techniques are used to correct clock errors at the source in real-time.
U.S. Pat. No. 5,973,994 to Woodall discloses a sonobuoy device for tracking and targeting submarines. The sonobuoy device consists of a sonobuoy having aft and forward sections interconnected with each other, fin means mounted on the aft section for flight stabilization of the device during travel above water from the platform, separation means responsive to impact of the device with the water upon completion of the travel thereof for separating the sections of the device from each other, payload means within the forward section of the device for listening for an acoustical signal in response to submergence thereof within the water following the separation of the sections of the device, flotation means mounted within the device and inflated in response to the impact with the water for anchoring the payload means and tethering means connecting the flotation means to the payload means for limiting the submergence thereof while anchored by the flotation means to a predetermined depth at which the payload means receives an acoustical signal. An apparatus comprised of a device with a launching system and a method for deploying the device also is disclosed.
A further improved means for efficiently and cost effectively deploying sonar buoys with a low degree of risk to friendly forces is still needed.
It is an object of the present invention to provide a device and method for efficiently and cost effectively monitoring littoral and other waters for enemy submarines and other threats with a low degree of risk to friendly forces.
It is a further object of the present invention to provide a means for a submarine-launched cruise missile to lay a wide-area field of sonar buoys from a standoff distance.
This and other objects are accomplished by the apparatus of the present invention, which is a sonar buoy adapted to be deployed by a cruise missile. This sonar buoy includes a flotation device for keeping a portion of the buoy afloat, a hydrophone, a transmitter for communicating contact and position information and a releasable means for attaching the sonar buoy to the cruise missile. By means of this device, a means of monitoring littoral and other waters for enemy submarines and other threats is provided with a low degree of risk to friendly forces.
Preferably, this sonar buoy may be deployed by a submarine-launched Tomahawk UGM 109D cruise missile outfitted with sonar buoys. Originally designed to deliver small sub-munitions to multiple targets, the UGM 109D features four payload modules, each holding six packs of sub-munitions. The Tomahawk sonar buoy device replaces each pack with a payload shell containing a sonar buoy.
This apparatus allows a submarine to lay a wide area field of sonar buoys from a standoff distance, allowing anti-submarine warfare (ASW) forces to pinpoint and track hostile contacts from a safe range before attacking.

The United States of America as represented by the Secretary of the Navy


An extruded metal matrix composite incorporates boron carbide in fine particulate form. The composition is useful as a radiation shield.

Due to its unique combination of relatively low cost, low toxicity and high radiation absorption capacity, boron has long been used for shielding of neutron radiation in connection with nuclear reactors. Boron has a high absorption cross section, a meaning that the probability is high that a neutron passing through a sheet or layer containing boron atoms will interact with a boron nucleus and hence be prevented from passing through. Native boron contains both B.sup.10 and B.sup.11 isotopes, the former having a fivefold higher neutron absorption capacity than the latter. Through an enrichment process, the B.sup.10 content can be increased above the naturally occurring level of about 19 atomic percent.
Generally, radiation shields using boron are in the form of a composite material. This is necessitated by the inability of boron, or compounds thereof (e.g., boron carbide), to provide minimum acceptable levels of thermal shock resistance, fracture toughness and tensile strength. Incorporating boron into a composite can provide greater control of the physical properties of the shield since the non-boron components can be selected for strength or other important properties rather than their radiation shielding effect. Despite this greater control, however, prior art boron composites have suffered from many drawbacks.
It is known, for example, to mix isotopic B.sup.10 (i.e., highly enriched boron) with molten aluminum and then cast it as an ingot. The ingot is then rolled to form a sheet. During the casting process there is significant clumping of the boron due to solidification effects. The clumped boron particles, due to their larger size, are prone to fracturing during the rolling step, which in turn causes smearing of the boron into "stringers," i.e., elongated boron particulates. This can be seen in FIG. 1, which is a photomicrograph of a boronated aluminum alloy formed using an ingot metallurgy technique. The large particles in the photomicrograph are clumped boron carbide particulates. During the rolling process, some of the clumps fracture and form stringers which can be in excess of 300 .mu.m in length. Void spaces are formed between the fractured particles which may lead to corrosion. Furthermore, the performance of the shield is degraded because of the loss of uniformity caused by clumping and subsequent fracturing.
Why this occurs can be explained in terms of the measurement of "nearest neighbor distance" between the boron particulates. In a highly uniform matrix, the distance between adjacent boron particulates falls within a narrow statistical distribution. Thus, throughout the matrix, the distance between a given boron particle and the nearest neighboring particle is relatively constant. Conversely, the more non-uniform the distribution, the greater the variance in nearest neighbor distance. The clumping of boron particulates during casting increases the non-uniformity due to migration of smaller particulates from more uniformly distributed positions into consolidated larger particulates. FIG. 2 is a histogram of nearest neighbor distances for the same boronated aluminum alloy of FIG. 1. As can be seen from FIG. 2, the nearest neighbor distances vary widely with a standard deviation of 14.95 .mu.m.
The effect of nearest neighbor distance on radiation absorption is as follows. Neutron radiation entering a matrix with uniform distribution of boron particulates will be absorbed at a uniform rate according to the statistical probability of the neutrons encountering a boron nucleus. However, for a non-uniform matrix, the neutron absorption is also non-uniform. In areas of the matrix where the nearest neighbor distances are small, for example, neutrons are successfully intercepted. Where the nearest neighbor distances are large, significant radiation may pass through because the statistical odds of encountering a boron nucleus are diminished. Since pass through of radiation over even small areas of the matrix is generally unacceptable, non uniform matrices have limited utility. Neutron absorption by non-uniform matrices can be enhanced by increasing the percentage of B.sup.10 in the particulates, however, highly enriched boron is expensive and significantly increases the cost of the radiation shielding. The absorption may also be increased by increasing the thickness of the shield. This solution also has drawbacks because the shield must fall within specified weight and size restrictions.
An alternative to casting and rolling is powder metallurgy. This technique holds the promise of providing highly uniform dispersions of boron particulates. Prior to the present invention, however, the full benefit of this technique had not been realized. Also, compromises in shield effectiveness were necessary in order to provide adequate adhesion of the powder particulates. U.S. Pat. No. 5,700,962, for example, describes metal matrix compositions formed by blending a metal matrix powder material with boron carbide powder. Included with the boron carbide powder are small amounts of silicon, iron and aluminum, which function as chelating agents by forming intermetallic bonds with the metal matrix material. The metal matrix material can be aluminum or an aluminum alloy. The powders are mixed, isostatically compressed, degassed, sintered and then extruded.
Prior to the sintering step, the ingots (billets) are heated to burn off binder and water. The composition of the binder is not disclosed, however, it is assumed to be organic in nature. This debinderizing step (designated S10 in FIG. 2 of the patent) results in microstructural discontinuities and limits the maximum size of the product. Although organic binders are fugitive, beyond an ingot diameter of about three inches, diffusion effects become significant enough to prevent complete removal of binder even at temperatures well above that of binder decomposition. If significant binder is left in the ingot, decomposition and subsequent generation of hydrogen gas can occur in later processing stages, e.g. welding, creating a hazardous explosive environment. Attempts to remove all the binder from large diameter billets results in long heating cycles and increased costs, as well as difficulties in controlling the debinderization conditions.
The use of chelating agents is also problematic because many of those mentioned in U.S. Pat. No. 5,700,962 can significantly degrade performance of the neutron shielding material. Iron in particular is very harmful because it transmutates to radioactive isotopes with longer half lives.
Another approach to radiation shielding is the product known as BORAL, manufactured by AAR Advanced Structures. This product is a composite plate material having a core of mixed aluminum and boron carbide particles with aluminum cladding on both sides. This structure cannot be welded and is furthermore subject to corrosion if the aluminum cladding is breached. Since the core is not full density, hydrogen gas can be rapidly generated in the presence of water and result in blistering of the skin/cladding layer.
Hence, there remains a need in the art for a radiation shielding composition which can be easily manufactured, is not subject to corrosion, can be formed into a variety of shapes, including structurally self supporting elements, can be welded, and which form strong metal particle-to-metal particle bonds without the need for binders or chelating agents.

Radiation absorbing refractory composition


The gain of a parasitic lateral bipolar device in an MOS SOI structure is reduced to increase the differential between the snap-back sustaining voltage and the maximum recommended power supply voltage. Prior to insulated gate structure definition, very lightly doped source and drain regions are implanted to the underlying insulator layer. The source and drain regions have a doping concentration that is within an order of magnitude of the doping concentration of the well portion of the semiconductor layer. After the very lightly doped regions have been implanted, the implant mask is stripped and an insulated gate structure is formed atop the channel surface portion of the well layer between the source and drain regions. Using the insulated gate structure as a mask, off-axis, high angle implants of the same conductivity type as the source and drain regions are carried out to a first depth that only partially penetrates the depth of the deep source and drain implants. Very shallow high impurity concentration ohmic contact regions are then formed in surface portions of the first and second regions, and ohmic contact layers are formed on the conductive gate layer and the high impurity concentration ohmic contact regions.

FIGS. 1-17 diagrammatically illustrate the cross-section of a MOSFET architecture at respective steps in the course of its manufacture using a conventional off-axis, high angle (e.g. 30.degree. to 60.degree.)/rotated wafer, lightly doped drain (LDD) ion implantation process to enhance parametric characteristics of the device, in particular, for suppressing the kink effect and snap-back in N-channel SOI transistors and related lateral bipolar effects in P-channel SOI transistors.
More particularly, FIG. 1 shows an N type semiconductor (silicon) substrate 11 having a buried oxide layer 13 and a silicon epitaxial layer 15 formed to a prescribed thickness on the top surface of the substrate 11. Following initial oxidation of the top surface 21 of the epitaxial silicon layer 15 to form a surface pad oxide layer 23, a layer of polysilicon 25, which is to serve as an etch-stop, is deposited on pad oxide layer 23 and the structure is selectively etched down to buried oxide layer 13, so as to form a trench 28 which effectively patterns the silicon into a mesa architecture, shown in FIG. 2 as comprising respective mesas 31 and 32 into which complementary field effect transistor devices are to be introduced.
FIG. 3 shows the formation of a trench oxide layer 41 which fills the trench pattern 28 that surrounds mesas 31, 32 and also overlies the mesas themselves, together with a planarization photoresist structure 36 including photoresist plugs 43 and a topside layer of photoresist 45. The structure of FIG. 3 is planarized, for example by means of a reactive ion etch, which terminates at the top surface 27 of the polysilicon etch stop layer 25, so as to realize the planar configuration shown in FIG. 4, in which oxide layer 41 fills the mesa-surrounding trench pattern 28 up to a level that is coplanar with the top surface 27 of polysilicon layer 25. Following geometry definition of the trench oxide, the etch-stop polysilicon layer 25 is removed, as shown in FIG. 5.
Complementary retrograde wells are next introduced through surface pad oxide layer 23 into mesas 31 and 32, by selectively masking mesas 31 and 32 and performing deep and shallow conductivity type-determining implants in each of the mesas to form an N-well 51 in mesa 31 and a P-well 52 in mesa 32, as illustrated in FIGS. 6 and 7, respectively. After photoresist masking material has been removed, then, to the extent necessary, a shallow P-threshold adjustment implant is performed, as shown at 55 in FIG. 8, and the structure is annealed, to set the conductivity characteristics of the N and P wells 51 and 52.
The structure of FIG. 8 is then subjected to an oxide etch which removes pad oxide layer 23 and a portion of the trench oxide 41, as shown in FIG. 9. A gate oxide layer 56 is formed atop the N and P wells 51, 52 to realized gate oxide layers 61, 62 as shown in FIG. 10, followed by the formation and (N+) doping of a polysilicon layer, which is then selectively etched into doped polysilicon gate layers 63, 65 overlying N and P wells 51, 52, respectively, as shown in FIG. 10.
The structure of FIG. 10 is next selectively masked and subjected to off-axis, high angle (e.g. 30.degree. to 60.degree.)/rotated wafer, lightly doped source and drain (LDD) ion implantations, shown at 71, 72 in FIGS. 11 and 12, respectively, so as to form shallow P type source and drain regions 81, 82 in N well 51, and shallow N type source and drain regions 91, 92 in P well 52. As pointed out earlier, this high angle implant serves to suppress the kink effect and snap-back in the N-channel SOI transistor formed in P well 52.
After removal of surface masking material, a layer of spacer oxide material 101 is non-selectively deposited on the complementary well structure, as shown in FIG. 13 and the surface oxide is then etched down to the top surface 21 of the epitaxial silicon layer 15, leaving spacers 111, 112 contiguous with the sidewalls of polysilicon gate 63 overlying gate oxide layer 61 and spacers 121, 122 contiguous with the sidewalls of polysilicon gate 65 overlying gate oxide layer 62, as shown in FIG. 14.
The structure shown in FIG. 14 is subjected to a nonselective surface reoxidation, which forms source and drain oxide layers 131, 132 on the complementary wells (and also atop polysilicon gates 63, 65), as shown in FIG. 15. The respective P channel and N channel devices are next implanted with deep, high impurity concentration source and drain regions, which must fully bottom out on buried oxide layer 13, in order to prevent backwall (device-to-device) parasitic shorts and minimize junction leakage. The respective implants are low angle (vertical) implants, self-aligned with spacers 111, 112, and 121, 122 of gate structures 63, 65 as shown in FIGS. 16 and 17, respectively, forming deep P+ source and drain regions 141, 142 in the P-channel device formed in N-well 51, and deep N+ source and drain regions 151, 152 in the N-channel device formed in P-well 52.
The substantially increased (overcompensating) doping levels of deeply implanted regions 141, 142 and 151, 152 is due to the fact that the these regions are typically implanted at energy levels that will not penetrate the insulated gate structures 63, 65, which are employed as self-alignment masks, as described above, and to ensure that the (retrograde) doping of the wells 51, 52 will be effectively overcompensated, as necessary. (Hence, high doping levels are needed to ensure that the dopant reaches the backwall interface of buried oxide layer 13). After the oxide overlying the gate structures is removed, a silicide layer is formed atop the gate polysilicon, and the source and drain regions.
As a consequence of the high doping concentration of the deep implants, and especially in the case of the N-channel transistor formed in P-well 52, which is individually illustrated in FIG. 18 absent the silicide layer, the gain of a lateral parasitic NPN bipolar device (established in the source-channel-drain path, as shown schematically at 160) can seriously degrade the breakdown characteristics of the transistor. To prevent snap-back, the sustaining voltage V.sub.SUS should be kept well above the maximum recommended power supply voltage of the circuit.
Since an increase in the gain of the parasitic NPN bipolar device 160 reduces the sustaining voltage of the MOS device, it is desirable to degrade the injection efficiency of its emitter region (the source region of the N-channel MOS device). However, the high doping level required to realize oxide-bottomed out source and drain implants 151, 152, goes directly against this objective, so that the physical structure of the conventional SOI MOS device incurs an inherent performance penalty.

Reduction of bipolar gain and improvement in snap-back sustaining voltage in SOI field effect transistor


An adapter plate permits an arm mount with a single abutment plate to support two monitors. The adapter plate includes a first hole, a second hole, and a third hole. The holes may be part of a first set of holes, a second set of holes, and a third set of holes, respectively. Each of the sets of holes is preferably configured in a symmetric pattern compliant with VESA standard configurations for flat panel monitor mounts. One set of holes aligns with the abutment plate on the arm mount and the other two sets of holes align with the two monitors respectively to receive support members, such as bolts, therethrough to couple the two monitors to the single abutment plate on the arm mount.

Technical Field
The present disclosure relates generally to the field of mounting devices for flat panel monitors. More particularly, the present invention relates to an adapter plate for connecting two monitors to an arm mount. Specifically, the present invention relates to an adapter plate forming three sets of holes therein, one set of holes aligned to an arm mount, one set of holes aligned with a first monitor, and one set of holes aligned with a second monitor.
Background Information
With the advent of flat panel monitor technology, a wide variety of mounting device began to develop in order to mount monitors to various locations. One particular mount is known as an arm mount. An arm mount is attached to a solid structure, such as a wall, at one end and is coupled to a monitor at an opposite end. The arm mount includes an abutment plate defining holes arranged in an industry standard VESA alignment. The holes in the abutment plate align with a set of VESA arranged nuts in a monitor. Bolts extend through the holes in the abutment plate threadedly into the set of nuts to connect the flat panel monitor to the arm mount. Additionally, some arm mounts may be extendable or collapsible about a pivot joint.
Some computer processors are programmed to provide a visual output or display across two monitors. This is often colloquially known as a "dual screen mode." Dual screen modes are advantageous inasmuch as they allow the display of more information to the operator at a single time. Further, many operators express that they prefer utilizing two screens over the use of one screen.

Adapter plate for connecting two monitors to an arm mount