The invention relates to a glass substrate having on at least one of its faces an antireflection coating formed by a stack of thin dielectric material layers having alternately high and low refractive indices. To prevent the modification of the optical properties of the coating in the case where the substrate is subject toga heat treatment such as tempering, bending or annealing, the layer or layers of the stack which are liable to deteriorate on contact with alkali ions such as sodium ions are separated form the substrate by at least one layer forming part of the antireflection coating and forming a xe2x80x9cshieldxe2x80x9d with respect to the diffusion of alkali.

1. Field of the Invention
The invention relates to transparent and in particular glass substrates, which are provided with an antireflection coating, as well as to their production method. It also relates to the use thereof, particularly as glazings.
2. Discussion of the Background
An antireflection coating is usually formed by a stack of thin interface layers, generally an alternation of low and high refractive index layers. When deposited on a transparent substrate, such a coating has the function of reducing its light reflection, i.e. of increasing its light transmission. Thus, a substrate coated in this way is subject to an increase in its transmitted light to reflected light ratio, which improves the visibility of objects positioned behind it.
An antireflection coating can then be used in numerous applications, e.g. for protecting a panel illuminated by a light placed behind the observer, or for forming or constituting part of a shop display window, so as to make it easier to see what is in the window, even when the internal illumination is weak compared with the external illumination.
The performance characteristics of an antireflection coating can be measured or evaluated on the basis of different criteria. Clearly the fist criteria are of an optical nature. It can be considered that a xe2x80x9cgoodxe2x80x9d antireflection coating must be able to lower the light reflection of a standard clear glass substrate to a given value, e.g. 2%, or even 1% and less. It can also be important that the coating ensures that the substrate retains a satisfactory, e.g. neutral calorimetry, very close to that of the bare substrate. Other secondary criteria can be taken into account as a function of the envisaged application, particularly the chemical and/or mechanical durability of the coating, the cost of the materials used or the methods to be used for producing the same.
Patent application WO-92/04185 discloses an antireflection coating deposited on a transparent substrate and constituted by an alternation of layers having a high niobium oxide index and a low silicon oxide index. Its optical performance characteristics are interesting. It is advantageous to use niobium oxide from the industrial standpoint, because it is a material which can be deposited faster than other high index oxides of the titanium oxide type using known vacuum methods, such as reactive cathodic sputtering. However, it is found that such a stack is sensitive to any heat treatment and at high temperature its optical properties are unfavorably modified, particularly with respect to its colorimetry in reflection. This is disadvantageous if it is wished to give the particular substrate already provided with its coating mechanical or esthetic properties which can only be obtained by heat treatments at temperatures which may approach the softening temperature or point of the glass. Such treatment can, e.g., consist of bending or giving the substrate a certain curvature, an annealing for hardening it, or a tempering to prevent injury in the case of shattering.
One object of the invention is to obviate this disadvantage by developing a new type of antireflection, multilayer coating, which has good optical performance characteristics and which retains the latter, no matter whether or not the substrate then undergoes a heat treatment.
The invention relates to a glass substrate having on at least one of its face an antireflection coating incorporating a stack of thin layers of dielectric materials with alternatively high and low reflective indices. The invention prevents modification to the optical properties of the coating in the case where the substrate is subject to a heat treatment of the tempering, bending or annealing type by ensuring that the layer or layers of the stack which may be subject to deterioration in contact with alkali metal ions, for example of the sodium ion type, emitted by diffusion of the substrate are separated from said substrate by at least one layer forming part of the antireflection coating and which forms a xe2x80x9cshieldxe2x80x9d to the diffusion of the alkali ions.
Thus, it has surprisingly been found that the unfavorable modification of the optical appearance of antireflection coatings under the effect of heat was due to the diffusion of alkali ions from the glass, the ions being inserted in at least some of the layers of the coating thereby structurally modifying these layers leading to a deterioration thereof. The solution according to the invention involves not removing from the antireflection, coating of any material sensitive to the alkali ions, but instead isolating the same from the surface of the glass by means of a shielding layer blocking the alkali diffusion process. This layer is also chosen so as to fulfill, in parallel, an adequate optical function within the antireflection coating. Thus, it is not an additional layer which makes the structure of a conventional antireflection coating more complicated, which is very advantageous from the industrial standpoint.
Thus, these shielding layers make it possible to produce antireflection coatings able to withstand heat treatments without any significant optical modification, while incorporating materials sensitive to alkali, but offering many other advantages.

Transparent substrate with antireflection coating


Method for optimization of a progressive spectacle lens, which method comprises: defining a starting nominal astigmatism distribution for the spectacle lens; determining a transformed nominal astigmatism distribution and optimizing the spectacle lens on the basis of the transformed nominal astigmatism distribution, wherein the determination of a transformed nominal astigmatism distribution comprises multiplication of the maximum temporal nominal astigmatism of the starting nominal astigmatism distribution by a factor k as a result of which a modified maximum temporal astigmatism is obtained, wherein k is a function of a prescription value, and/or at least of one parameter of the spectacle lens or of the arrangement thereof in front of the eyes, and transformation of the starting nominal astigmatism distribution on the basis of the modified maximum temporal astigmatism.

Aspects of the present invention relate to a computer-implemented method for optimizing and producing a progressive spectacle lens, corresponding devices for optimizing and producing a progressive spectacle lens, corresponding computer program products and storage media, as well as to a use of a spectacle lens.
An optimization of a progressive spectacle lens is usually performed by minimizing a target function in which required or target values for at least one optical parameter, e.g. astigmatism and/or refractive power, or required or target values for at least one aberration, e.g. astigmatic error and/or refractive error, of the progressive spectacle lens are taken into account. In the optimization process of the spectacle lens, the individual prescription values (sph, cyl, axis, add, prism, base), parameters of the individual position or arrangement of the spectacle lens in front of the spectacles wearer's eye (e.g. corneal vertex distance (CVD), face form angle (FFA), forward inclination or pantoscopic angle), as well as physiological parameters (e.g. pupillary distance) can be taken into account. The progressive spectacle lens can be optimized and calculated "online" as one-of-a-kind after receipt of order.
Moreover, DE 10 2008 015 189, DE 10 2009 005 206, or DE 10 2009 005 214 suggest determining the target astigmatism distribution, on the basis of which the progressive spectacle lens is optimized, by means of a transformation of an existing or predetermined design (starting design, base design). For example, DE 10 2008 015 189 suggests calculating target astigmatism distributions for different additions by means of a transformation of a predetermined base or starting target astigmatism distribution, which has been specified for a predetermined base addition. DE 10 2009 005 206 and DE 10 2009 005 214 suggest creating target astigmatism distributions with different widths of the distance and/or near zone(s) from a predetermined target astigmatism distribution by means of manipulation of a predetermined base target astigmatism line. The methods described in DE 10 2008 015 189, DE 10 2009 005 206, or DE 10 2009 005 214 make it possible to simplify the method for optimizing and producing a progressive spectacle lens and making it more efficient and flexible.

Prescription-dependent and individualization-dependent modification of the temporal peripheral nominal astigmatism and adaption of the object distance function to changed object distances for near and/or far vision


An apparatus may include an orthogonal frequency division multiplexing (OFDM) physical layer interface. An adaptive subcarrier demodulator or an adaptive subcarrier modulator may be coupled to the OFDM physical layer interface to implement adaptive bit loading (ABL). A decoder or an encoder may be coupled to the adaptive subcarrier demodulator or to the adaptive subcarrier modulator to implement low density parity checking.

The claimed invention relates to multicarrier communications and, more particularly, to adaptive modulation in multicarrier communications.
Multicarrier communications may be described as a communications technique in which multiple carriers or subcarriers are used to communicate information. As an example of multicarrier communications, Orthogonal Frequency Division Multiplexing (OFDM) may be described as a communications technique that divides a communications channel into a number of spaced frequency bands. In OFDM, a subcarrier carrying a portion of the user information may be transmitted in each band. In OFDM, each subcarrier may be orthogonal, differentiating OFDM from the commonly used frequency division multiplexing (FDM). An OFDM symbol may include, for example, a multicarrier symbol transmitted simultaneously on the OFDM subcarriers during the OFDM symbol period. The individual symbols on particular subcarriers may be referred to as subcarrier symbols.
In wireless systems that are susceptible to dynamic or frequency selective fading, such systems may benefit substantially from channel interleavers that interleave at the transmission bit level to break up fading that may be correlated within a transmission symbol. Some OFDM communication systems may also use Adaptive Bit Loading (ABL), which may also be referred to as adaptive subcarrier modulation, where the modulation density may be changed on a subcarrier-by-subcarrier basis based on channel conditions. Techniques such as ABL may complicate the bit interleaving process, however, because each OFDM symbol may contain a different number of bits whenever a new channel adaptation is made (e.g., transmission). It may be difficult to implement an efficient interleaving scheme when the number of bits may vary among OFDM symbols.

Adaptive bit loading with low density parity check forward error correction


A switching circuit can include a logic circuit having a logic circuit input and a logic circuit output and at least three input transistors coupled to provide three separate paths between three input/output (I/O) nodes and the logic circuit input. The switching circuit can further include at least three output transistors coupled to provide three separate paths between the three I/O nodes and the logic circuit output. Methods of fabricating such switch circuits and devices and/or systems including such switching circuits are also disclosed.

Integrated circuit (IC) devices can include a number of sections formed in one or more substrates that are electrically interconnected to one another. In order to provide increased operating speeds, it is desirable to provide as fast a signal transmission speed as possible for signal paths that interconnect different sections. For some integrated circuit devices, critical timing paths can be identified prior to the fabrication of the device, and thus optimized (e.g., utilize large signal driving devices, minimize routing lengths, or increase signal line cross sectional size to reduce resistance).
However for other integrated circuit devices, signal paths can be configured after the device has been manufactured by connecting different signal paths with switches. In such cases, complete signal routing paths are unknown at the time of fabrication and thus cannot be optimized in the manner described above. Further, because the configuration of signal paths can depend upon a series of switches, signal switch construction can limit overall performance of such devices. For example, programmable logic devices (PLDs) can often include signal paths configurable by enabling (placing into a relatively low impedance state) or disabling (placing into a relatively high impedance state) various switching devices. Programmable logic devices can include, as but a few examples, complex PLDs (CPLDs) and programmable gate arrays (PGAs) including field PGAs (FPGAs).
Programmable logic devices can include various sections that provide programmable functions. Such sections can be interconnected to one another by signal lines disposed in different directions. In order to provide flexibility in routing paths it is desirable to provide switching circuits that can be programmed to connect one signal path disposed in one direction, to any of various signal paths disposed in the same or a different direction.

Programmable switch circuit and method, method of manufacture, and devices and systems including the same


Devices for straightening portions of a vehicle, particularly the unibody and/or frame of a vehicle following a collision. A device comprising a clamp which is attachable to a pulling device which exerts a pulling force in a direction P. The clamp comprises jaws which open in the general direction of pulling force P to engage a flange or other portion of a vehicle extending away from the direction of the pulling force P. This aspect is particularly useful for repairing the wheelhouse of a vehicle. Another aspect is a clamp with two openings, preferably in a single set of jaws. One opening may, for example, open proximally, i.e., in the general direction of pulling force P, while the other opening may open in a direction away from pulling force P. Another aspect of the present invention comprises providing a plurality of clamps in a single pulling device wherein the clamps are connectable, via a chain, to a single pulling arm, and where the clamps are independently positionable relative to each other. For example, the clamps can be rotated, twisted, extended and/or retracted independently of each other for connection to portions of a vehicle all of which can then be pulled in a single pulling step. Another aspect comprises a device having a plurality of clamps which allow portions of a vehicle to be pulled sequentially during a single pulling operation.

When a vehicle has been in an accident, it is common for the frame, in the case of vehicles having a frame, or the unibody to be bent or deformed. It is well known that it is necessary to straighten the portions of the frame or unibody in order to affect an acceptable repair. As used herein in connection with repairing a damaged vehicle, the term "straighten" refers to returning one or more portions of a vehicle closer to its original configuration than the configuration it was in prior to starting the repair. The term "straighten" when used in this context does not necessarily indicate that the portion of the vehicle being repaired is made linear.
It is common in the vehicle repair industry to attach a powerful hydraulic straightening device to one or more portions of a vehicle utilizing a clamp which is attached directly to the vehicle and to a chain which connects the clamp to the straightening device. Certain portions of a vehicle have been inherently difficult to repair. For example, the wheelhouse of a vehicle typically comprises a curved portion, the edge of which extends inwardly, i.e. toward the center of the vehicle. In some instances, these edges comprise a welded seam of two sections of sheet metal.
Some previously known devices for pulling out a crushed wheelhouse comprise a curved bar which is designed to rest on top of the inwardly projecting edge and against the inner side of the wheelhouse. Such devices typically comprise structure which extends from the curved bar in the directions inwardly, downwardly, outwardly, and upwardly for attachment to the chain of a straightening device. These devices are maintained in position solely by outwardly directed forces applied manually during positioning and applied by the straightening device during the straightening procedure. Since such devices are not actually clamped onto the wheelhouse, they present a risk of slipping during positioning and during the straightening procedure. It would be more suitable, and particularly safer, to provide a more secure attachment between a clamp and the wheelhouse of a vehicle being required. It would also be desirable in some instances to be able to affect a straightening procedure using a single clamp which is attachable to different portions of a vehicle.
It would also be desirable to attach a single clamp to different portions of a vehicle for sequentially and/or simultaneously pulling those vehicle portions.
As used herein, the term "jaw" is used to indicate one side of the portion of the clamp which is used to grasp a portion of the vehicle. Thus, it will be understood that a clamp requires at least two jaws which are tightened onto a portion of a vehicle to which force will be exerted by the pulling device. In many accidents, closely positioned portions of a vehicle are damaged and it would be desirable to apply straightening forces during vehicle repair to multiple portions of a vehicle simultaneously and/or sequentially without having to reposition a clamp. It would, therefore, be desirable to provide a clamping device comprising one or more clamps capable of grasping multiple portions of a damaged vehicle.


A haptic presentation apparatus that includes a force sensor that detects force input to an operation portion that is operated by a user, and generates an electric signal corresponding to the detected force, a vibration actuator that presents tactile sensation to the user, a vibration damping member to be interposed between the force sensor and the vibration actuator; a first mechanical part contacting the force sensor; and a second mechanical part contacting the vibration actuator, and the vibration damping member is provided between the first mechanical part and the second mechanical part, such that the vibration damping member contact neither the force sensor nor the vibration actuator.

In recent years, as medical robot systems used when endoscopic surgery is carried out, master-slave medical robot systems have been known that make it possible to approach affected sites without making large incisions on the bodies of patients. In such a medical robot system, a surgeon (user) such as a doctor operates a master apparatus including an input interface, and a slave apparatus including a medical instrument such as forceps or tweezers is remotely operated in accordance with the operation of the surgeon. The slave apparatus is configured, for example, as an arm robot with a surgical instrument held on the front end, and can change the position or attitude of the surgical instrument in the abdomen with a high degree of freedom and a wide movable area. In the medical robot system, in the case where force generated in a slave apparatus is not transmitted to a surgeon, the surgeon can fail to adjust the moving operation amount or force, and damage living tissue of a patient.
Then, medical robot systems have been known that adopt bilateral control which present force generated in slave apparatuses to master apparatuses. In bilateral control, feedback control is performed such that the positions and force of surgical instruments and input interfaces agree with each other between a slave apparatus and a master apparatus. A medical robot system that adopts the bilateral control includes an apparatus configured to present haptic sensation in accordance with the force of an input operation of a user detected by a force sensor provided to a master apparatus.
For example, Patent Literature 1 discloses a master apparatus including three force sensors that detect the respective force components in the directions of three axes (x, y, and z) orthogonal to each other, three respective angle sensors that detect a roll angle, a pitch angle and a yaw angle, and three position sensors that detect the respective front end positions of a dental tool handle in the xyz coordinate system. The master apparatus is a haptic presentation apparatus including a parallel link structure with a multi-degree of freedom and a force sensor, and drive control over an actuator which controls the attitude of the parallel link structure is performed in accordance with the force of an input operation of a user detected by the force sensor.
In addition, as technology applicable to a medical apparatus, Patent Literature 2 discloses a pressure sensation/tactile sensation presenting apparatus that expresses pseudo pressure sensation/tactile sensation with vibration as an expression of an operation situation. The pressure sensation/tactile sensation presenting apparatus uses a pressure sensation/tactile sensation sensor to detect a situation in which a surgical instrument such as forceps comes into contact with a target object, drives a pressure sensation/tactile sensation presenting device such as a voice coil in accordance with an output of the pressure sensation/tactile sensation sensor, and transmits pressure sensation/tactile sensation to a fingertip of a user.


To provide a back-illuminated type solid-state imaging device capable of color separation of pixels without using a color filter, and a camera module and an electronic equipment module which incorporate the solid-state imaging device.

As solid-state imaging devices, a CMOS solid-state imaging device represented by a CMOS image sensor, and a CCD solid-state imaging device represented by a CCD image sensor are known. In solid-state imaging devices, a front-illuminated type solid-state imaging device in which light enters from the front surface side of a semiconductor substrate is widely accepted. On the other hand, a back-illuminated type solid-state imaging device in which sensitivity can be improved by making the region of a photoelectric conversion element larger than that in the front-illuminated type solid-state imaging device is disclosed.
FIG. 6 is an example of a back-illuminated type CMOS solid-state imaging device. A CMOS solid-state imaging device 1 includes: pixel-isolation regions 4 made of p type, that is a second conductive type, semiconductor regions formed in a first conductive type, for example n-type, silicon semiconductor substrate 2 such that unit pixel regions 3 are separated from each other; and a photodiode PD which serves as a photoelectric conversion element and a required number of MOS transistors Tr for reading out signal charges obtained through photoelectric conversion and accumulated in the photodiode PD, which are formed within each of the pixel regions 3 surrounded by the p-type pixel-isolation regions 4.
The p-type pixel-isolation regions 4 are formed in the direction of the depth of the substrate such that the region extends from the front surface to the back surface of the substrate 2. The MOS transistors Tr are formed in p-type semiconductor regions 5 which are connected to the p-type pixel-isolation regions 4 and extend, on the front surface side of the substrate 2. The photodiodes PD are formed extending to the back surface side of the substrate 2 such that the photodiode extends to the lower part of the p-type semiconductor regions where the MOS transistors Tr have been formed. Each photodiode PD includes an n-type semiconductor region 7, which is formed of the n-type substrate 2 surrounded by the p-type pixel-isolation regions 4, and a high concentration p+ semiconductor region 6 that is a lower layer of the p-type semiconductor region 5; and a pn junction j1 is mainly formed between the n-type semiconductor region 7 and the p+ semiconductor region 6.
A p+ accumulation layer 8 for restraining the occurrence of dark current, which is made of a high impurity concentration p-type semiconductor region is formed at the interface on the back surface of the n-type semiconductor region 7 which constitutes a photodiode PD, in common with each pixel. Further, a p+ accumulation layer 11 is formed at the interface on the front surface of the n-type semiconductor region 7 as well. On the other hand, a MOS transistor Tr has an n-type source drain region 9 formed in the p-type semiconductor region 5, and a gate electrode 10 formed above and between a pair of n-type source drain regions 9 with a gate insulating film in between. The MOS transistor Tr shown in the figure includes the photodiode PD, the n-type source drain region 9 and the gate electrode 10 to form a readout transistor.
On the front surface of the semiconductor substrate 2 is formed a multilayer wiring layer 14 in which multilayer wirings 13 are laminated with an interlayer insulating film 12 made, for example, of a silicon dioxide film or the like in between, and on this multilayer wiring layer 14 is formed a supporting substrate 15 for reinforcement that is made of a silicon substrate, for example. On the back surface of the semiconductor substrate 2, which is a light incidence surface, is formed a color filter 17 with an insulating layer 16 in between, and an on-chip microlens 18 is formed thereon.
In this back-illuminated type CMOS solid-state imaging device 1, light enters from the back surface side of the substrate through the on-chip microlens. The light is separated into light beams of red, green and blue by the color filter 17, which enter the photodiodes PD of corresponding pixels, respectively. Subsequently, signal charge of each pixel is read out through the MOS transistor Tr on the front surface side of the substrate, and so a color image is output. Since the back-illuminated type CMOS solid-state imaging device 1 has a large area so that the photodiode PD extending to the lower layer of the MOS transistor Tr, high sensitivity can be obtained.
In the above-described back-illuminated type solid-state imaging device, a pn junction j2 is formed by the p+ accumulation layer 8 and the n-type semiconductor regions 7 of the photodiodes PD which are formed on the light incidence surface side, with the same depth in each pixel; and a pn junction j1 of the photodiode PD is similarly formed with the same depth in each pixel. In order to obtain a color image, such back-illuminated type solid-state imaging device uses the color filter 17 and photoelectrically converts light of a specific wavelength to obtain a signal from each pixel. Accordingly, there has been a problem in which the formation process of a color filter causes the number of production processes to increase, the cost increase, and the yield rate deterioration.
In light of the above, the present invention provides a back-illuminated type solid-state imaging device in which color separation of a pixel is made possible without using a color filter, and a camera module and an electronic equipment module which incorporate this solid-state imaging device.

Solid-state imaging device, camera module and electronic equipment module

Abstract: A solid-state imaging device including: a photoelectric conversion element PD formed in a semiconductor substrate 22; a reading-out part which reads out signal charges from the photoelectric conversion element PD formed on one surface side of the semiconductor substrate 22; the other surface of the semiconductor substrate 22 made to a light incidence surface; and a pixel which exclusively makes light of a specific wavelength or longer photoelectrically converted, by adjusting pn junction depths h2 [h2 r, h2 g, h2 b] between the photoelectric conversion element PD and an accumulation layer 28 on the light incidence surface side. A camera module and an electronic equipment module which incorporate the solid-state imaging device.


Disclosed is a system for handling failures in a storage controller interfacing between a plurality of host systems and direct access storage devices (DASDs). The storage controller directs data from the host systems through a first and second data paths in the storage controller to a DASD. A first processor, first non-volatile memory unit (NVS), and a first cache are associated with the first data path and a second processor, a second NVS, and a second cache are associated with the second data path. A bridge provides communication between the first processor and the second NVS and the second processor and the first NVS. During normal operations prior to a failure in the storage controller, data directed to the first data path is written in the first cache and communicated with the first processor to the second NVS via the bridge for storage in the second NVS. Data directed to the second data path is written in the second cache and communicated with the second processor to the first NVS via the bridge for storage in the first NVS. A point of failure within at least one of the first processor, first cache, and first NVS is handled by routing the data directed to the first data path to the second processor and writing the routed data to the second cache and the second NVS. Upon repairing the point of failure, the data directed to the first data path is rerouted to the first processor, wherein the rerouted data is written in the first cache and communicated with the first processor to the second NVS via the bridge for storage therein.

1. Field of the Invention
The present invention relates to a storage controller for interfacing between a host system and a direct access storage device (DASD) system and, in preferred embodiments, a storage controller including a failback and failover system for handling a point of failure within the storage controller.
2. Description of the Related Art
In a large distributed computer system, a plurality of host computers and devices are typically connected to a number of direct access storage devices (DASDs) comprised of hard disk drives (HDDs). The DASDs may be organized in a redundant array of independent disks, i.e., a RAID array. A RAID array is comprised of multiple, independent disks organized into a large, high-performance logical disk. A controller stripes data across the multiple disks in the array and accesses the disks in parallel to achieve higher data transfer rates. However, utilizing multiple disks in an array increases the risk of failure. The solution in the art is to employ redundancy in the form of error-correcting codes to tolerate disk failures. The arrangement and organization of RAID arrays is described in Peter M. Chen, Edward K. Lee, Garth A. Gibson, Randy H. Katz, and David A. Patterson, "RAID: High-Performance, Reliable Secondary Storage," ACM Computing Surveys, Vol. 6, No. 2, June 1994, which is incorporated herein by reference in its entirety.
Not only is there a risk associated with the failure of a hard disk drive in a DASD system such as a RAID array, but there is also a risk of failure at a point within a storage controller which controls read and write operations between host computers and the DASDs. The conventional storage controller is typically designed to handle hardware failures. One such storage control designed to handle certain hardware failures is the storage controller utilized in the International Business Machines Corporation's (IBM) 3990 Model 3 system. This storage controller has two storage clusters, each of which provides for selective connection between a host computer and a DASD. Each cluster is on a separate power boundary. Further, a non-volatile storage unit (NVS) is associated with each cluster. The NVS is a memory array supported by a battery backup system. The NVS stores back-up copies of modified data in the event of a hardware failure within the storage controller while data is being written to a DASD. The NVS provides a storage back-up that is as secure as writing the data to a magnetic disk. Failback systems for storage controllers are described in U.S. Pat. Nos. 5,636,359, 5,437,022, 5,640,530, and 4,916,605, all of which are assigned to IBM, the assignee of the subject application, and all of which arc incorporated herein by reference in their entirety.
In U.S. Pat. Nos. 5,437,022 and 5,640,530, as with the IBM 3990, model 3, the storage controller is comprised of two clusters, wherein each cluster has a cache and a NVS. The cache buffers frequently used data. When a request is made to write data to a DASD attached to the storage controller, the storage controller may cache the data and delay writing the data to a DASD. Caching data can save time as writing operations involve time consuming mechanical operations. The cache and NVS in each cluster can intercommunicate, allowing for recovery and reconfiguration of the storage controller in the event that one of the memory elements is rendered unavailable. For instance, if one cluster and its cache fails, the NVS in the other cluster maintains a back-up of the cache in the failed cluster.
In one caching operation, referred to as DASD fast write, data buffered in the cache is backed-up in the NVS. Thus, two copies of data modifications are maintained, one in the cache and another in the NVS. DASD fast write is typically used for data that will be written to the DASD. If the data to be written to the DASD is present in the cache, instead of writing the data to the DASD, the controller copies the data into the cache and NVS without having to interrupt processing to immediately write to the DASD. If the data to be written is not present in the cache, then the data is written to the DASD and cache simultaneously and immediately. Another caching operation, referred to as cache fast write, involves writing data to the cache without using the NVS. Cache fast write is intended for data that is not needed for job completion or that can be easily reconstructed.
Notwithstanding, the storage controller disclosed in U.S. Pat. Nos. 5,437,022 and 5,640,530 comprises a complex and custom hardware structure, wherein each storage path in a cluster requires its own custom microcontroller and microcode. In fact, U.S. Pat. No. 5,640,530, at column 6, lines 50-57, makes note of the added complexity of the system which requires that each microcontroller maintains and updates information concerning the location of data for read, writes and other data transfers.
Moreover, data transfer rates in a storage controller are determined by the data-transfer rates at each connectivity point within the controller. The speed at which processed data travels between a host and DASDs, such as a RAID array, is restricted by the maximum data-transfer rate possible through each peripheral interface. In current systems, data transfer rates are significantly degraded when a cluster fails, because the remaining cluster must then handle all data transfers. In storage control systems which involve complex arrangements to handle failovers, such as the system disclosed in U.S. Pat. Nos. 5,437,022 and 5,640,530, the complexity of the system can further degrade data transfer rates when one cluster must take over data transfers previously handled by the failed clusters.
Yet further, in some prior art systems, the NVS and storage controller have single points of failure which can disable the entire cache and NVS, resulting in substantial performance degradation.

Failover and failback system for a direct access storage device


An electronic device comprising a connecting section; a first IF circuit that communicates through the connecting section with an external device connected via the connecting section, at a first communication speed; a second IF circuit that communicates through the connecting section with the external device, at a communication speed that is higher than the first communication speed; and a control section that, when one of the first IF circuit and the second IF circuit is selected as an IF circuit to be used for communication, limits a power supply to the other IF circuit.

1. Technical Field
The present invention relates to an electronic device and a computer readable medium.
2. Related Art
A peripheral device is known that includes an MCU block and a USB control block that operate based on a power supply voltage of a USB power supply bus, when the peripheral device is connected to a personal computer (PC) via a USB, such as shown in Patent Document 1, for example. When the peripheral device is disconnected from the PC, the power supply from the USB power supply bus to the USB block stops, and power supply voltage is supplied from a battery driving the peripheral device to the MCU block. Patent Document 1: Japanese Patent Application Publication No. 2010-231795
When a communication IF section corresponding to High-Speed USB 2.0 and a communication interface corresponding to SuperSpeed USB 3.0 are provided as communication IF sections compliant with the USB 3.0 standard, the power consumed by each IF section is increased. In this way, when a communication IF section corresponding to high-speed communication and a communication IF section corresponding to low-speed communication are both provided, the power consumption is increased.

Electronic device and computer readable medium


A method and system for enforcing host routing settings in a network device comprises network devices having enforcement logic for extracting host routing settings from a DHCP packet issued by a DHCP server to a DHCP client connecting to a network. The network devices generate enforcement rules based on the host routing settings and apply those rules to ports through which the DHCP client connects to the network. The enforcement rules include access control lists having one or more match conditions generated based on the host routing settings.

Because networks have come under an increasing number of malicious attacks that not only compromise the security of network resources, but also prevent access by legitimate users, enforcement mechanisms to limit access to the network, i.e., network access control (NAC) mechanisms, have become an increasingly important part of network security. NAC mechanisms include host-based approaches to enforcement that limit access to the network by an end point device, i.e., the host, using network configuration information stored in the host itself, as well as network-based approaches to enforcement that limit the host's network access using network configuration information stored in the network's connection points, such as the switches, hubs, and routers, collectively referred to as switches.
A commonly used host-based approach to enforcement is the Dynamic Host Control Protocol (DHCP) for enforcing end point access policies through Internet Protocol (IP) address configuration. Examples of NAC solutions that implement DHCP include a NAC platform product sold under the trademark "Sentriant AG" by Extreme Networks, Inc., of Santa Clara, Calif., the assignee of the present application, as well as Microsoft's Network Access Protection ("NAP") framework.
Using DHCP, a DHCP server automatically assigns a DHCP client, i.e., the end point or host device, an IP address from an available pool of addresses, including various routing parameters such as a default gateway and subnet mask. The IP address and other parameters are leased to the end point device to allow access to the network for a predetermined period of time, after which the address assignment expires.
Unfortunately, the DHCP and other host-based approaches to enforcement have traditionally been very weak from a security perspective since enforcement is performed entirely on the host. In the case of DHCP, this allows an attacker to bypass the enforcement mechanism and gain full network access by simply configuring static networking settings on their machine rather than using the DHCP-provided settings, a practice that is sometimes referred to as IP spoofing.
For example, under normal circumstances, the DHCP server limits a non-compliant computer's access to the network by purposely not configuring a default gateway and/or setting the subnet mask to 255.255.255.255 so that there is no route to the attached subnet. The non-compliant computer may legitimately gain limited access to a domain name server (DNS) and remediation servers on the network only when the DHCP server assigns a limited set of host routes to those computers using the Classless Static Routes DHCP option. However, an attacker can bypass this entire mechanism by simply statically configuring a valid default gateway and IP subnet.
In order to thwart an attacker attempting to bypass the DHCP routing settings, some NAC solutions have implemented a network-based enforcement mechanism that locks down a suspect source IP address that does not appear to have been assigned by a DHCP server. Network-based approaches to enforcement are generally considered to be far more secure than host-based approaches such as DHCP since they are far more difficult for an attacker to bypass. This is because it is generally much harder for an attacker to reconfigure the network settings on a switch or other type of connection point than to reconfigure their own device.
One example of such a network-based enforcement mechanism is an IP security feature of the switch operating system sold under the trademark "Extreme XOS" by Extreme Networks, Inc., of Santa Clara, Calif., the assignee of the present application. The Source IP Lockdown feature automatically places source IP address filters on specified ports of a switch such that only traffic from a valid DHCP-assigned source IP address or an authenticated static source IP address is allowed to enter the network. In this way, the network is protected from attacks that use random source IP addresses for their traffic. However, because this feature is limited to filtering traffic based on the source IP address alone, it does not protect the network from attacks that bypass the other routing settings that are provided by DHCP, such as the default gateway and IP subnet settings.

Enforcing host routing settings on a network device


A color prediction system includes: database storing absorption/scattering coefficients of each primary color ink; sections for: selecting a spot color ink as a combination of primary color inks that reproduce a colorimetric value of a color sample, reading absorption and scattering coefficients of the primary color inks of a reference spot color from the database, obtaining absorption and scattering coefficients of the spot color ink of a specified formulation ratio, and calculating a spectral reflectance of the spot color ink to be reproduced; obtaining a reproduced color from the spectral reflectance; obtaining a difference from the colorimetric value of the color sample and correcting the formulation ratio to calculate a formulation ratio with an allowable difference; and calculating a Neugebauer primary color of overprinted spot color inks from the absorption and scattering coefficients of the spot color inks calculated at formulation ratios determined by the formulation ratio determination section.

1. Technical Field of the Invention
The present invention relates to a color prediction system and a color prediction method for predicting a reproduced color in performing color matching of a reproduced color printed by a printer.
2. Related Art
In color matching, for example, a reproduced color can be adjusted by area modulation (area modulation gradation). Such color matching is performed by predicting a color of a portion in which each color is printed with a given dot area ratio. There are some known techniques of such color prediction, including a method using Yule-Nielsen spectral Neugebauer model (e.g., see JP-A-2007-516663) and a method using a spectrally expanded Neugebauer model (e.g., see Journal of Japanese Society of Printing Science and Technology, Vol. 42, No. 5 (2005)).
The "spectrally expanded Neugebauer model" herein refers to a model in which Neugebauer primary colors and dot area ratios are expanded to the spectral model so as to serve as functions of wavelengths.
The models mentioned above are based on the precondition that, when dots are different in size, the dots are printed on a surface of a print medium with a solid single primary color ink of an even thickness. With this kind of model, the components ascribed to the scattering of light at an edge of each dot cannot be precisely expressed.
As a measure against this, there is a model in which the "spectrally expanded Neugebauer model" is expanded to more precisely take account of the components ascribed to the scattering of light at an edge of each dot (e.g., see JP-A-2006-329753).
The conventional art mentioned above predicts color reproduced on a surface of a print medium as a result of overprinting primary color inks.
On the other hand, a spot color ink is produced each time it is used, by formulating a plurality of primary color inks at an arbitrary formulation ratio. Therefore, an actually measured spectral reflectance is not available for such a spot color ink, unlike in the case of a primary color ink. Thus, the spectral reflectance cannot be calculated for each gradation of the spot color ink and thus color calculation cannot be performed using the above-mentioned model that is an expansion of the "spectrally extended Neugebauer model".
Further, in the conventional art mentioned above, it is difficult to predict a color which is reproduced by overprinting spot color inks, each being a mixture of primary color inks, on a surface of a print medium.

Color prediction system and color prediction method


Methods and/or systems are disclosed herein for use in imaging an object with microwave tomography using a plurality of different boundary conditions.

The disclosure herein relates generally to microwave tomography. More particularly, the disclosure herein pertains to methods and systems of microwave tomography (MWT) for use in, e.g., imaging applications (e.g., tumor detection in human tissue, etc.).
Tomography is imaging by sections or sectioning to convey internal structures of an object, for example, the human body or the earth. Microwave tomography (MWT) systems irradiate an object of interest, or object to be imaged, with electromagnetic energy, measure or sample the resultant scattered electromagnetic energy, and generate or reconstruct an image of the object based on the resultant scattered electromagnetic energy. "Scattering" is a general physical process whereby some forms of radiation, such as light, sound, or moving particles, for example, are forced to deviate from a straight trajectory by one or more non-uniformities in a medium through which it passes. The "inverse problem" may be used to determine the characteristics of an object of interest such as its shape and internal constitution from the resultant scattered electromagnetic energy.
An exemplary tomography system, e.g., a microwave tomography system, is described in Patent Cooperation Treaty Patent Application Pub No. WO 2009/066186 A2 filed on Nov. 21, 2008 and entitled "System and Methods of Improved Tomography Imaging," which is incorporated herein by reference in its entirety.
Contributions to MWT have been made in all aspects of the technology, especially the development of improved inversion algorithms (see, e.g., T. Rubaek, P. M. Meaney, P. Meincke, and K. D. Paulsen, "Nonlinear microwave imaging for breast-cancer screening using Gauss-Newton's method and the CGLS inversion algorithm," IEEE Trans. Antennas Propag., vol. 55, no. 8, pp. 2320-2331, August 2007; A. Abubakar, P. M. van den Berg, and J. J. Mallorqui, "Imaging of biomedical data using a multiplicative regularized contrast source inversion method," IEEE Trans. Microwave Theory Tech., vol. 50, no. 7, pp. 1761-1777, July 2002; J. D. Zaeytijd, A. Franchois, C. Eyraud, and J.-M. Geffrin, "Full-wave three-dimensional microwave imaging with a regularized Gauss-Newton method-theory and experiment," IEEE Trans. Antennas Propag., vol. 55, no. 11, pp. 3279-3292, November 2007; and W. C. Chew and Y. M. Wang, "Reconstruction of two-dimensional permittivity distribution using the distorted Born iterative method," IEEE Trans. Med. Imaging, vol. 9, no. 2, pp. 218-225, 1990).
Further, diverse antenna or transducer systems have been utilized in the actual physical setups used to collect electromagnetic scattering data in MWT systems (see, e.g., P. Meaney, M. Fanning, D. Li, S. Poplack, and K. Paulsen, "A clinical prototype for active microwave imaging of the breast," IEEE Trans. Microwave Theory Tech., vol. 48, no. 11, pp. 1841-1853, November 2000; A. Franchois, A. Joisel, C. Pichot, and J.-C. Bolomey, "Quantitative microwave imaging with a 2.45-GHz planar microwave camera," IEEE Trans. Med. Imag., vol. 17, no. 4, pp. 550-561, August 1998; A. Broquetas, J. Romeu, J. Rius, A. Elias-Fuste, A. Cardama, and L. Jofre, "Cylindrical geometry: a further step in active microwave tomography," IEEE Trans. Microwave Theory Tech., vol. 39, no. 5, pp. 836-844, May 1991; S. Y. Semenov, R. H. Svenson, A. E. Bulyshev, A. E. Souvorov, A. G. Nazarov, Y. E. Sizov, V. G. Posukh, A. Pavlovsky, P. N. Repin, A. N. Starostin, B. A. Voinov, M. Taran, G. P. Tastis, and V. Y. Baranov, "Three-dimensional microwave tomography: Initial experimental imaging of animals," IEEE Trans. Biomed. Eng., vol. 49, no. 1, pp. 55-63, January 2002; A. Fhager, P. Hashemzadeh, and M. Persson, "Reconstruction quality and spectral content of an electromagnetic time-domain inversion algorithm," IEEE Trans. Biomed. Eng., vol. 53, no. 8, pp. 1594-1604, August 2006; C. Yu, M. Yuan, J. Stang, E. Bresslour, R. George, G. Ybarra, W. Joines, and Q. H. Liu, "Active microwave imaging II: 3-D system prototype and image reconstruction from experimental data," IEEE Trans. Microwave Theory Tech., vol. 56, no. 4, pp. 991-1000, April 2008; T. Rubaek, O. Kim, and P. Meincke, "Computational validation of a 3D microwave imaging system for breast-cancer screening," IEEE Trans. Antennas Propag., vol. 57, no. 7, pp. 2105-2115, July 2009; and A. E. Bulyshev, A. E. Souvorov, S. Y. Semenov, R. H. Svenson, A. G. Nazarov, Y. E. Sizov, and G. P. Tastis, "Three dimensional microwave tomography theory and computer experiments in scalar approximation," Inverse Probl., vol. 16, pp. 863-875, 2000).
In many previous MWT systems, the object of interest and the antennas are contained within a chamber, usually made from a dielectric material, such as plexiglass. The dielectric chamber is usually filled with a lossy matching fluid, e.g., a 87:13 glycerin:water solution (see, e.g., T. Rubaek, P. M. Meaney, P. Meincke, and K. D. Paulsen, "Nonlinear microwave imaging for breast-cancer screening using Gauss-Newton's method and the CGLS inversion algorithm," IEEE Trans. Antennas Propag., vol. 55, no. 8, pp. 2320-2331, August 2007; and P. M. Meaney, M. W. Fanning, T. Raynolds, C. J. Fox., Q. Fang, C. A. Kogel, S. P. Poplack, and K. D. Paulsen, "Initial clinical experience with microwave breast imaging in women with normal mammography," Acad Radiol., March 2007).
Further, in one or more previous MWT systems, the object of interest and the antennas have been enclosed by a circular metallic enclosure (see, e.g., L. Crocco and A. Litman, "On embedded microwave imaging systems: retrievable information and design guidelines," Inverse Problems, vol. 25, no. 6, 2009, 065001 (17 pp); C. Gilmore and J. LoVetri, "Enhancement of microwave tomography through the use of electrically conducting enclosures," Inverse Problems, vol. 24, no. 3, 2008, 035008 (21 pp); A. Franchois and A. G. Tijhuis, "A quasi-Newton reconstruction algorithm for a complex microwave imaging scanner environment," Radio Sci., vol. 38, no. 2, 2003; R. Lencrerot, A. Litman, H. Tortel, and J.-M. Geffrin, "Measurement strategies for a confined microwave circular scanner," Inverse Problems in Science and Engineering, pp. 1-16, January 2009; "Imposing Zernike representation for imaging two-dimensional targets," Inverse Problems, vol. 25, no. 3, 2009, 035012 (21 pp); and P. Mojabi and J. LoVetri, "Eigenfunction contrast source inversion for circular metallic enclosures," Inverse Problems, vol. 26, no. 2, February 2010, 025010 (23 pp)). Still further, in previous MWT systems, the object of interest and the antennas have been enclosed in conducting cylinders of arbitrary shapes (see, e.g., P. Mojabi, C. Gilmore, A. Zakaria, and J. LoVetri, "Biomedical microwave inversion in conducting cylinders of arbitrary shapes," in 13th International Symposium on Antenna Technology and Applied Electromagnetics and the Canadian Radio Science Meeting (ANTEM/URSI), February 2009, pp. 1-4).
Obtaining quality images using MWT may require accurate collection of a substantial amount of electromagnetic scattering data, which may often be performed using a relatively large number of co-resident antennas. For example, many present MWT systems include antenna arrays that range from 16 to 32 elements in which small monopoles or Vivaldi antennas have been used. These large antenna arrays may facilitate gathering of bistatic scattering data at many angles without mechanically repositioning the antennas. The antenna elements themselves are not typically taken fully into account in the electromagnetic system model of the associated nonlinear optimization problem, although it may be a consideration in achieving good images (compare, e.g., the antenna compensation schemes in the following: K. Paulsen and P. Meaney, "Nonactive antenna compensation for fixed-array microwave imaging. I. Model development," IEEE Trans. Med. Imag., vol. 18, no. 6, pp. 496-507, June 1999; P. Meaney, K. Paulsen, J. Chang, M. Fanning, and A. Hartov, "Nonactive antenna compensation for fixed-array microwave imaging. II. Imaging results," IEEE Trans. Med. Imag., vol. 18, no. 6, pp. 508-518, June 1999; and O. Franza, N. Joachimowicz, and J.-C. Bolomey, "SICS: A sensor interaction compensation scheme for microwave imaging," IEEE Trans. Antennas Propag., vol. 50, no. 2, pp. 211-216, February 2002).
Including the antennas in the MWT system model may be one way of reducing modeling error that exists between a numerical system model, used in an inversion algorithm, and the actual system, from which data is collected. Modeling error may also occur when assuming a homogeneous unbounded domain for the numerical system model (i.e., assuming that the matching fluid extends to infinity) because the boundary conditions for the dielectric discontinuity, e.g., at a MWT system's dielectric casing (e.g., a plexiglass casing), may actually be required to properly account for the finite extent of the matching-fluid region. Both the antenna and the boundary condition modeling errors may be reduced by using lossy matching fluid of sufficiently high loss such that electromagnetic energy returning from the boundary, or any passive antenna, to any receiving antenna is not appreciable. Although the use of a lossy matching fluid may reduce modeling errors, the net effect of using a lossy matching fluid in MWT systems may also be to reduce the accuracy of the complex permittivity profile reconstructions because the addition of any loss reduces the dynamic range and achievable signal-to-noise ratio of the system.
A MWT system that uses a rotating metallic hexagonal-shaped container where the object of interest is illuminated by waveguides (e.g., each of the waveguides acts as both a transmitter and a receiver) connected, or fixedly attached, to each side of the metallic container has been previously described (see, e.g., E. Wadbro and M. Berggren, "Microwave tomography using topology optimization techniques," SIAM J. Sci. Comput., vol. 30, no. 3, pp. 1613-1633, 2008). In this system, a container, along with the attached waveguides, may be rotated about the object of interest to collect additional scattering data, and topology optimization techniques may be used to invert the data. At each rotation, however, this system produces an identical incident field with respect to the boundary (i.e., the boundary condition) of the enclosure because the microwave sources (i.e., the waveguides) remain fixed with respect to the boundary. In other words, this system produces identical boundary conditions with respect to its waveguides (i.e., its transmitters and receivers) because the waveguides are fixedly attached to the enclosure, and therefore, rotate with the enclosure.

Microwave tomography systems and methods


The present disclosure provides optimal network performance and network illumination in a wireless, autonomous communications network with a dynamic network topology achieved by auto-configuration. Functional alogorthemic enhancements of the communications network are used, enabling the communications network to automatically determine the current network configuration and the accessibility of the transceivers that are associated with the communications network by using measurements and to determine the optimal position of a master station at any one time from the data obtained from the measurements.

In wireless communications networks, e.g. computer networks functioning in conformance with the IEEE standard 802.11a/b/g (WLAN standard) which are set up from a base station which can for its part also forward data traffic, the accessibility of all the transceivers that are associated with the communications network (e.g. fixed or mobile stations for wireless telecommunications)—in other words of the subscribers—depends on the respective position of the device concerned, which can be configured as a mobile or fixed device, in relation to a master station or base station preferably configured as an access point.
The devices which are not located within visual range of the master station or base station will be unable to be associated with the network. Since the master station or base station is capable of forwarding data traffic, two devices which cannot see one another directly can nevertheless communicate with one another via the master station or base station.
Accordingly, an optimal placement of the master station or base station can, in turn, optimize the performance and the illumination of a communications network.

Method for establishing a wireless, autonomous communications network, transceiver and base station of a wireless, autonomous communications network and corresponding wireless, autonomous communications network


Storing text samples in a manner that the text samples may be quickly searched. The text samples are assigned a text sample identifier and are each parsed to thereby extract text components from the text samples. Text components that have the same content are assigned the same text component identifier. For each parsed text component, a text component entry is created that includes the assigned text component identifier as well as the text sample identifier for the text sample from which the text component was parsed. A text sample entry group is created for each text sample that contains the text component entries in sequence for the text components found within the text sample. The text sample entry groups are stored so as to be scannable during a future search.

Computers and computing systems have affected nearly every aspect of modern living. Computing systems are providing ever more complex and sophisticated functionality. Such functionality is often primarily driven by underlying software, which itself is becoming ever more complex. Some of the more sophisticated functionality involves computing systems communicating one with another using a network. For instance, the Internet is a world-wide consortium of constituent computing networks that allow computing systems to complete communication world-wide.
Such improved capability in communication has allowed information to be more easily shared, and is a large reason why this modern era has often been referred to as the "information age". The improved ease of communication has contributed to the development of data centers, buildings which contain large arrays of data processing and storage power. The volume of information thus available to a user on a computing system is no longer limited to the local storage of the computing system, but extends to the almost infinite variety of information that the computing system may access from other computing systems and data centers throughout the world.
Human beings are, however, only interested in some information, and the interest of a human being varies from person to person and moment to moment. Accordingly, there are mechanisms for sorting through large quantities of information and providing information of higher interest to a user. Conventional mechanisms for doing so including web browsers, search engines, social networks, and so forth.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.


A prefabricated cover board has a high-density polymer or predominantly polymer material core layer having a density between 6 lbs/ft3 and 25 lbs/ft3. A prefabricated roofing panel composite includes the cover board and an insulation board that has a low-density polymer or predominantly polymer material foam core layer having a density less than 6 lbs/ft3. The cover board may have a waterproofing membrane forming the top major surface of the cover board. When making the roofing panel composite, the low-density foam core layer of the insulation board may be formed with the high-density core layer of the cover board being currently or subsequently formed over and bonded to a top major surface of the low-density foam core layer in the same operation or preformed insulation boards may be fed into a production line with the high-density core layer of the cover board being formed over and bonded to top major surfaces of the low-density foam core layers of the insulation boards.

The subject invention relates to low-slope roofs that are typically found on commercial and industrial buildings and in particular to a prefabricated high-density polymer or predominantly polymer material cover board and a prefabricated roofing panel composite, which includes the high-density polymer or predominantly polymer material cover board and a low-density polymer or predominantly polymer material foam insulation board, for use on such low-slope roofs and to a method of making the cover board and the roofing panel composite.
Commercial and industrial buildings typically have roofs with low-slope roof decks. The roofing systems for these roofs with low-slope roof decks typically include one or more layers of a low-density roofing insulation, a layer of roofing cover boards that overlie the low-density roofing insulation layer(s), and a waterproofing membrane that overlies the layer of cover boards. The layer(s) of low-density insulation, such as a low-density polymer-based foam insulation, if not protected, can be partially crushed or otherwise damaged from worker traffic over the insulation, the placement of heaving objects on the insulation, the weather, and other causes commonly encountered in roofing construction. The layer of roofing cover boards that overlies the one or more layers of low-density insulation, protects the more fragile low density insulation from damage, acts as a fire barrier, provides a suitable substrate for the attachment of the overlying waterproofing membrane, and augments the insulating function of the low-density insulation. The uppermost waterproofing membrane layer overlying the cover board layer protects the underlying cover board and insulation layers from moisture and other adverse climatic conditions. Normally, these three components (the low-density insulation boards, the roofing cover boards, and the waterproofing membrane) of the roofing system are separately manufactured and separately and successively applied to the low-slope roof deck. While these roofing systems function very well, there has remained a need to provide an improved roofing cover board and to provide prefabricated roofing panel composites that combine at least an insulation board and the improved roofing cover board layer, and that, preferably, combine an insulation board, the improved roofing cover board layer and a waterproofing membrane. With the use of such an improved roofing cover board and prefabricated roofing panel composites, roofing systems for low-slope roof decks can be improved and/or the time, labor and costs associated with the installation of roofing systems on low-slope roof decks can be reduced. The subject invention provides an improved roofing cover board, an improved prefabricated roofing cover board and waterproofing membrane composite, an improved prefabricated roofing panel cover board and insulation board composite, and an improved prefabricated roofing panel cover board, insulation board, and waterproofing membrane composite. The subject invention also provides a method for making the improved roofing cover board and the prefabricated roofing panel composites including the improved roofing cover board that is highly productive, relatively economical, and efficient.

This patent is subject to a terminal disclaimer.

Roofing cover board, roofing panel composite, and method


A cargo handling truck bed that includes a material handling device having a base and two longitudinally extending conveyors. Each of the conveyors includes a longitudinally extending belt having a first end and a second end. A first drum is rotatably secured to the base and secured to the first end of the belt. A second drum is rotatably secured to the base and secured to the second end of the belt. The first drum is longitudinally spaced apart from the second drum. A first drive arrangement for rotating the first drum and a second drive arrangement for rotating the second drum for winding the belts around the respective drums are provided. A control is provided for driving the respective first drums and second drums. A guide and guide track are provided to keep the belts in alignment. Polyethylene bearings are provided to engage with the drums and limit switches are provided for stopping winding of the belts around the drums.

1. Field of the Invention
The present invention relates to a material handling device, and more particularly, to a cargo handling truck bed.
2. Description of the Prior Art
Manually moving and removing materials, such as boxes from truck beds, particularly from trailer beds, is time consuming. Material moving devices, such as single conveyors, have been developed to assist in moving materials from the truck beds. See, for example, U.S. Pat. No. 4,760,971, which is hereby incorporated by reference. Alternatively, rollers (either driven or undriven) have been utilized to roll the material from the truck bed.
A problem with the prior art conveyors is that all of the material or cargo, say boxes, must be moved simultaneously by the conveyor. In some instances, when only a portion of the cargo must be delivered, all of the cargo may have to be removed from the trailer and then the undelivered portion must be returned to the trailer.
To overcome this problem, the prior art roller arrangement has been modified to provide two separately driven roller sections extending along the length of the truck bed. The two sections of rollers are independently driven by separate chain and sprocket arrangements. The driven roller arrangement is expensive to manufacture and maintain due to the number of parts required, namely, rollers, chains and sprockets. Further, an inherent flaw of the driven roller arrangement is that cargo, such as boxes, may roll in the trailer bed when the rollers are not being driven and the trailer bed is inclined. This can pose a safety problem when unloading the trailer bed.
Therefore, it is an object of the present invention to provide a two-sectioned cargo handling truck bed that utilizes less parts than the prior art driven roller arrangement.


An optical fiber assembly of the present invention is configured such that an optical fiber fixing section (i) is fixed to an SUS tube and (ii) sandwiches an optical fiber between a first member and a second member at an end part of the SUS tube, so that the optical fiber is fixed while being spaced from the SUS tube. This makes it possible to provide an optical fiber assembly having a structure that prevents an optical fiber from coming into contact with an edge part of a metal tube on the premise that the optical fiber is covered with the metal tube.

An optical fiber(s) is covered with a protection material for prevention of breakage and damage. A resin material is generally used as an optical fiber protection material.
However, in a case where an optical fiber(s) is used in an electronic device, there arises a problem that outgassing of, for example, siloxane occurs from resin which is a protection material, and consequently brings about an adverse effect on an electronic component in the electronic device.
Under the circumstances, in order to prevent the occurrence of outgassing, covering of an optical fiber(s) with a metal tube such as an SUS tube has been considered. Patent Literatures 1 and 2, for example, each disclose an example of covering an optical fiber(s) with a metal tube such as an SUS tube.


A multi-unit welding apparatus has a row of electric welding units all of which are connected in parallel with a single welding transformer through an electric conductor assembly. The electric conduction assembly includes a single strip of electric conductor and a double-folded strip of electrode conductor which are connected at one end to positive and negative terminals of a secondary winding of the welding transformer and are arranged along and connected to the welding units of the welding unit row so that the combined length of conductor between secondary winding and each welding unit is the same for all welding units.

1. Field of the Invention
This invention relates to a multi-unit electric welding apparatus, and, more particularly to an electric welding apparatus having a plurality of electric welding units, arranged in a row, which are supplied with welding current from a power source through a single welding transformer.
2. Description of Related Art
For space saving and low manufacturing cost, a plurality of welders, or electric welding units, are connected in parallel to a single welding transformer by means of electric conductors, or welding cables. If a plurality of electric welding units are arranged in a straight line, the welding cable must be longer as the distance of the electric welding unit from the welding transformer is. Accordingly, the welding cables have different electric resistances from one another and, hence, supply different welding work currents to the electric welding units. This results in non-uniform welding quality of works.


An object is to provide an inverter device capable of realizing exact protection of the winding of a motor. An inverter device for generating a pseudo alternating current by switching a direct current to drive a motor, comprises a controller that executes vector control on the basis of a secondary current applied to the motor. The controller calculates a current density from the secondary current to execute a predetermined protection operation on the basis of the calculated current density. The controller imposes a restriction on the operation frequency of the motor on the basis of the current density.

1. Field of the Invention
The present invention relates to an inverter device for generating a pseudo alternating current by switching a direct current to drive a motor.
2. Description of the Related Art
Conventionally, for example, in an air conditioner for a vehicle, a refrigerant is circulated in a refrigerant circuit by an engine-driven compressor to cool the interior of a compartment. However, attendant upon recent conspicuousness of environmental problems, cars using electric motors, such as electric cars, fuel cell powered cars, and hybrid powered automobiles, have been heartily developed. In such a car, because electric power is supplied from a battery to a main electric motor to run, an air conditioner uses a battery-driven electromotive compressor.
In that case, actually, a direct current from a battery is converted into a three-phase pseudo alternating current by an inverter including a plurality of switching element groups and then applied to a motor of an electromotive compressor to drive. However, if a surplus current flows in the winding of the motor, inconvenience such as burnout may arise. Thus, protection of the motor must be intended. For this reason, in a conventional general air conditioner for a home, the primary current flowing from a power source before entering an inverter is measured to make protection (for example, see Japanese Patent No. 2629664).
Here, in case of making motor protection using the primary current as described above, the secondary current flowing in the motor was calculated from the primary current as follows. That is, the power consumption is represented byW=√{square root over (3)}×Vrs×Ir×cos θ1in case of a three-phase alternating current power source andW=Vdc×Idc in case of a direct current power source, and the power consumption obtained from the secondary side is represented byW=√{square root over (3)}×Vuv×Iu×cos θ2(W: power consumption, Vrs: primary voltage, Ir: primary current, Vuv: secondary voltage, Iu: secondary current, and cos θ: power factor). Therefore, the secondary current Iu is represented byIu=(Vrs×Ir×cos θ1)/(Vuv×cos θ2)orIu=(Vdc×Idc)/(√{square root over (3)}×Vuv×cos θ2).Therefore, for obtaining the secondary current, the values of the power factor, Vrs, Vuv, and Vdc are necessary. If those values include errors, it is difficult to accurately estimate the secondary current.


A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

1. Field of the Invention
The present invention relates to either discrete devices or integrated power semiconductor devices including MOS-gated power devices such as, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices. In particular, the invention relates to a MOS-gated power device having a smaller minimum dimension Lp that is a function of a single feature size and that yields an increased density of MOS-gated power devices per unit area.
2. Discussion of the Related Art
MOS technology power devices as known in the related art are composed of a plurality of elementary functional units integrated in a semiconductor chip. Each elementary functional unit is a vertical MOSFET, and all the elementary functional units are connected in parallel. With this arrangement, each elementary vertical MOSFET contributes a fraction of an overall current capacity of the power device.
A MOS technology power device chip typically includes a lightly doped semiconductor layer of a first conductivity type forming a common drain layer for all the elementary vertical MOSFETS. The lightly doped layer is superimposed over a heavily doped semiconductor substrate. Each elementary functional unit includes a body region of a second conductivity type formed in the common drain layer. U.S. Pat. No. 4,593,302 (Lidow et al.) discloses a so called "cellular" power device, wherein the body region of the elementary functional units has a polygonal layout, such as for example a square or hexagonal shape. For this reason, the elementary functional units are also called "elementary cells". In addition, MOS technology power devices are also known in the related art wherein the body region of each elementary functional units is an elongated stripe.
For any of the above power MOS devices, a typical vertical structure of the elementary functional units (i.e. a cross-section view) of the MOS technology power device is as shown in FIG. 1. In FIG. 1, the heavily doped semiconductor substrate is indicated by reference numeral 1 and the lightly doped semiconductor layer is indicated by reference numeral 2. The body region 3 of the elementary functional unit includes a central heavily doped portion 4, called a "deep body region", and a lateral lightly doped portion 5, having a lower dopant concentration than the heavily doped deep body region, which forms a channel region of the elementary vertical MOSFET. A doping level of the lateral portions 5 of the body region determines a threshold voltage of the power device. Inside the body region 3, a source region 6 of the same conductivity type as the common drain layer 2 is formed. A thin oxide layer 7 (a gate oxide layer) and a polysilicon layer 8 (a gate electrode of the power device) cover a surface of the semiconductor layer 2 between the body regions 3, and the layers also extend over the lightly doped lateral portion of the body regions. The polysilicon layer 8 is covered by a dielectric layer 9 in which contact windows 11 are opened over each body region to allow a superimposed metal layer 10 (a source electrode of the power device) to be deposited through the contact window and to contact the source regions 6 and the deep body region 4.
In the structure of FIG. 1, a short-circuit is defined between the source region and the deep body region to prevent a parasitic bipolar junction transistor having an emitter, a base and a collector respectively formed by the source region 6, the deep body region 4 and the heavily doped semiconductor substrate 1, from triggering on. The parasitic bipolar transistor will trigger "on" if the lateral current flow in the body below the source produces a voltage drop greater than approximately 0.7 V, forward biasing the emitter-to-base (EB) junction. The deep body region 4 increases the ruggedness of the power device because it reduces the base resistance of such a parasitic transistor.
The structure of FIG. 1 is manufactured by forming the common drain layer 2 over the heavily doped substrate 1, generally by means of an epitaxial growth. The thin oxide layer 7 is thermally grown over an active area of the common drain layer 2, wherein the elementary functional units of the MOS technology power device will be formed, and the polysilicon layer 8 is deposited on the thin oxide layer. The deep body regions 4 are formed by selective introduction of a high dose of a dopant to form the central heavily doped deep body regions 4. Windows 12 are formed in the gate oxide layer and the polysilicon layer by a selective etching of the polysilicon and gate oxide layers via a second mask to open the windows 12 where the elementary functional units will be formed. The lateral lightly doped portions of the body regions are then formed by selective introduction of a low dose of dopants into the common drain layer through the windows to form the lightly doped portions of the body regions. Next, the source regions 6 are formed as will be described in more detail below, followed by deposition of the dielectric layer 9 and selective etching thereof to open the contact windows 11. The metal layer 10 is then deposited and patterned.
This process involves the use of a minimum of four photolithographic masks: a first mask is used for the formation of the deep body regions 4; a second mask is used to selectively etch the polysilicon 8 and gate oxide 7 layers; a third mask is used to form the source regions 6 and a fourth mask is used to open the contact windows 11 in the dielectric layer 9. The mask for the introduction of the dopants forming the source regions is provided partially by the polysilicon and oxide layers, and partially by photoresist isles over a middle portion of the deep body regions 4. The photoresist isles are formed by depositing a photoresist layer over the common drain layer, selectively exposing the photoresist layer to a light source, and selectively removing the photoresist layer to provide the photoresist isles.
Referring again to FIG. 1, a dimension Lp of each window 12 in the polysilicon 8 and gate oxide 7 layers is given by equation (1): EQU Lp=a+2t (1)
where "a" is the width of the contact window 11 in the dielectric layer 9 and "t" is the distance between an edge of the polysilicon 8 and gate oxide 7 layers and an edge of the window 11 in the dielectric layer 9. The dimension "a" of the contact window is given by equation (2): EQU a=c+2b (2)
where "b" is a distance between an edge of the contact window 11 and an inner edge of the source region 6, or in other words the length of the source region available to be contacted by the metal layer 10, and "c" is the dimension of a surface of the deep body region wherein the source regions are absent or in other words the distance between the inner edges of the source regions, corresponding to the length of the surface of the deep body region available to be contacted by the metal layer. The dimension Lp is therefore given by equation (3): EQU Lp=c+2b+2t (3)
Accordingly, the elementary functional units of the related art have the dimension Lp determined by "three feature sizes", in particular the dimension Lp depends on the parameters "c", "b" and "t".
In MOS technology power devices, the electrical parameters to be optimized are the output resistance in the "on" condition Ron, a gate-to-drain capacitance (feedback capacitance) and a gate-to-source capacitance (input capacitance) of the MOS technology power device for a specific die size and breakdown voltage. The output resistance Ron is the sum of several components, each of which is associated with a particular physical region of the device. More specifically, Ron is made up of the components as shown in equation (4): EQU Ron=Rc+Racc+Rjfet+Repi (4)
where Rc is a channel resistance associated with the channel region, Racc is an accumulation region resistance associated with a surface portion of the common drain layer between the body regions, Rjfet is a resistance associated with a portion of the common drain layer between depletion regions of the body regions 5, and Repi is a resistance associated with a portion of the drain layer beneath the body regions.
The channel resistance Rc depends on process parameters such as the dopant concentration of the channel region. In other words Rc is proportional to the threshold voltage of the MOS technology power device, and to the channel length. The accumulation region resistance Racc depends on the distance "d" between two adjacent body regions, and decreases as such distance decreases. The Rjfet resistance depends on a resistivity of the common drain layer and on the distance "d" between the body regions, and increases as such a distance decreases. The Repi resistance depends on the resistivity and a thickness of the common drain layer, two parameters which also determine a maximum voltage (Bvmax) that can be sustained by the MOS technology power device. Bvmax increases as the resistivity increases, as long as the epi layer is thick enough. The resistivity and the thickness are optimized for the lowest value of Repi. Further, the output resistance Ron is inversely proportional to an overall channel length of the MOS technology power device. In other words Ron is inversely proportional to a sum of the channel of the individual elementary functional units that make up the MOS technology power device. The longer the channel length per unit area of the MOS technology power device, the lower the output resistant Ron per unit area.
Thus, in order to reduce the Ron it is desirable to scale down the dimensions of the elementary functional units and in particular the distance "d" between the body regions as long as Rjfet is not significantly increased, or in other words to increase a density of elementary functional units per unit area. A reduction of the distance "d" between the body regions has a further advantage of lowering the input and feedback capacitances of the MOS technology power device, thus improving its dynamic performance. Also, in high-voltage MOS technology power devices, reducing the distance "d" between the body regions increases the device's ruggedness under switching conditions. A recent technological trend has therefore been toward increasing the density of elementary functional units per unit area, and MOS technology power devices with a density of up to six million elementary cells per square inch can be fabricated.
The structure of the related art however poses some limitations to the further reduction of the dimensions thereof. These limitations are essentially determined by a resolution and alignment characteristics of the photolithographic apparatus used in the process to manufacture the MOS technology power device. Referring again to FIG. 1, it is known that the dimension "c" must be sufficiently large enough to guarantee that the metal layer 10 contacts the body region, and can only be scaled down to the resolution limit of the photolithographic apparatus used to provide the region "c". In addition, the dimension "b" must be sufficiently large enough to guarantee that the metal layer contacts the source region 6, and must also allow for any alignment errors between the mask defining the contact window 11 in the dielectric layer 9 and the mask for the formation of the source regions. Further, the dimension "t" must be sufficiently large enough to guarantee that the polysilicon layer 8 is electrically insulated from the metal layer and must also take into account any alignment errors between the masks for the definition of the windows 12 in the polysilicon layer and the mask for forming the contact windows in the dielectric layer.
In addition, the structure of the elementary functional units according to the related art does not allow reduction of the distance "d" between the elementary functional units below certain values that depend on a voltage rating of the MOS technology power device. For example, the distance "d" is approximately 5.mu.m for low-voltage devices and in a range from 10.mu.m to 30.mu.m for medium- to high-voltage devices. A reduction of the distance "d" below the specified values would in fact cause a rapid increase in the Rjfet component of the Ron of the MOS technology power device, thereby increasing the value of Ron.
In view of the state of the art described, it is an object of the present invention to provide a new MOS technology power device structure which provides an improvement to the MOS technology power devices of the related art.

Single feature size MOS technology power device

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno


A process for producing metals in the reduced state from their oxides using a simple and less expensive facility with lower running cost. A metal oxide in the form of particles is supplied into a high temperature flame from an oxygen burner in a reactor furnace to heat and melt the metal oxide. A reducing agent is also supplied into the flame to cause a reducing reaction of the molten metal oxide with the reducing agent. The resulting metal is recovered.

1. Field in the Industry
This invention concerns a process for obtaining a metal from a metal oxide as a reduced form. More specifically, the invention concerns a process in which a metal oxide is pulverized and the resulting particles are heated by high temperature flame and melted to carry out reducing reactions.
2. State of the Art
In conventional steel making using an electric furnace dust waste from the furnace is collected by a dust collector for the purpose of preventing air pollution.
The dust as a waste from steel making is very fine powder, and because of difficulty in utilization thereof, even though it contains FeO and Fe.sub.2 O.sub.3, the dust has been disposed as it is.
The steelmaking using an electric furnace also exhausts as wastes oxidation slag and reduction slag depending on the steps of refining.
Of the wastes, the oxidation slag is used as a roadbed material for constructing asphalt-paved roads. On the other hand, the reduction slag has no particular use, and thus, it is unavoidable to dispose.
The reduction slag contains, as one of the components, much free CaO, which absorbs water to be Ca(OH).sub.2. Volume expansion occurring at the time of this hydration makes it difficult to use the reduction slag as it is even for the roadbed material.
Disposing these dusts of course requires much cost, and the cost for disposing increases the costs for steel making.
The applicant proposed in a previous patent application (Japanese Patent Application No.6-11208) a method of mixing the steel making dust and the reduction slag by injecting them from nozzles of a burner into high temperature flame to melt.
This method gives the reduction slag physical and chemical properties similar to those of the oxidation slag, and thus, makes it possible to use the waste as the roadbed material.

Process for obtaining metal from metal oxide


There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

This invention relates to semiconductor devices and a method of making the devices, and, more particularly, to a semiconductor memory device having a static random access memory and a method of making the same.
A conventional highly-integrated static random access memory (SRAM) using insulated gate field effect transistors (IGFET's: hereinafter referred to as MOS transistors which are most typical) has a construction as shown in an equivalent circuit of FIG. 2A. This SRAM comprises a flip-flop circuit having two driver MOS transistors T1 and T2 coupled with each other in cross connection, highly resistive elements R1 and R2 for supplying extremely small currents to two store nodes N1 and N2 of the flip-flop circuit so as to store data connected to the store nodes N1 and N2, and transfer MOS transistors T3 and T4 for "write" and "read" of data which is to be connected to or which has been connected to the store nodes N1 and N2.
The flip-flop circuit is supplied with standard voltages such as power supply voltage Vcc and grounded potential GND, and the transfer MOS transistors are connected with data lines 1 and 1', having their gates connected in common to a word line 2.
As well known in the art, such a SRAM cell operates as follows More particularly, when the word line 2 is activated to, typically, higher potential, "high" or "low" data from the data lines are stored at the store nodes N1 and N2 through the transfer MOS transistors or conversely, statuses of the store nodes are read out to the data lines.
At present, the above type of memory cell having four MOS transistors and two highly resistive elements is used as a highly-integrated SRAM cell of the most general type. Recently, however, to ensure low-power consumption operations at low voltage, MOS transistors formed on a polycrystalline silicon layer have been used in place of the highly resistive load.
FIG. 2B diagrammatically shows a planar configuration of the conventional memory cell comprised of the four MOS transistors and two highly resistive elements. In the figure, gate electrodes 5b and 5c correspond to the gate electrodes of the driver MOS transistors T1 and T2 shown in FIG. 2A and a gate electrode 5a corresponds to the common gate, serving as the word line, of the transfer MOS transistors T3 and T4 shown in FIG. 2A. A highly concentrated n-type impurity region 3d serving as the drain of the driver MOS transistor T1 is in common to an n-type impurity region of the transfer MOS transistor T3.
A highly concentrated n-type impurity region 3e serving as the drain of the driver MOS transistor T2 is electrically connected, at the bottom of a contact hole 8a, to an n-type impurity region 3c of the transfer MOS transistor T4 by the gate electrode 5b. The contact hole 8a intervenes between the gate electrode 5b and a low resistivity polycrystalline silicon layer 9a.
The gate electrode 5c of the driver MOS transistor T2 is connected to the n-type impurity region 3d common to the transfer MOS transistor T3 and driver MOS transistor T1 to establish the cross connection in the flip-flop circuit of the static random access memory cell.
Contact holes 6a and 6b are respectively opened through highly concentrated n-type impurity regions 3f and 3g serving as the sources of the driver MOS transistors T1 and T2 to ensure electrical connection of the sources to a second layer in the form of a conductive layer 7.
Standard voltage is supplied to the sources of the driver MOS transistors T1 and T2 through this conductive layer 7. In order to prevent grounded potential from being raised by current flowing in the memory cell, the second layer acting as the conductive layer 7 is formed of a composite film (polycide film) having a low resistive polycrystalline silicon layer and a refractory silicide layer.
Contact holes 8a and 8b are respectively opened through the gate electrodes 5b and 5c, and highly resistive polycrystalline silicon layers 9c and 9d are connected to the gate electrodes 5b and 5c through low resistivity polycrystalline silicon layers 9a and 9b. A low resistivity polycrystalline silicon layer 9e serves as a common power supply electrode for feeding power supply voltage to the highly resistive polycrystalline silicon layers.
Aluminum electrodes 11a and 11b correspond to the two data lines in the memory cell, and they are electrically connected to highly concentrated n-type impurity regions 3a and 3b of the transfer MOS transistors T4 and T3 through contact holes 10a and 10b.
The prior art as discribed above is disclosed in, for example, JP-A-63-29576 which corresponds to an anterior application by the present applicant, and it features that the area of an electrode in a cell for standard potential supply connected to the memory cell can be reduced and the degree of integration of SRAM can be improved.
U.S. patent application Ser. No. 07/503,928 by some of the present inventors pertains to a SRAM.

Semiconductor memory device having static random access memory


The present disclosure provides improved systems and methods for automated cell identification/classification. More particularly, the present disclosure provides advantageous systems and methods for automated cell identification/classification using shearing interferometry with a digital holographic microscope. The present disclosure provides for a compact, low-cost, and field-portable 3D printed system for automatic cell identification/classification using a common path shearing interferometry with digital holographic microscopy. This system has demonstrated good results for sickle cell disease identification with human blood cells. The present disclosure provides that a robust, low cost cell identification/classification system based on shearing interferometry can be used for accurate cell identification. For example, by combining both the static features of the cell along with information on the cell motility, classification can be performed to determine the type of cell present in addition to the state of the cell (e.g., diseased vs. healthy).

Currently, biomolecular analysis is typically used in order to diagnose sickle cell disease. However, such analysis can be expensive and cumbersome, particularly for developing countries.
An interest exists for improved systems and methods for cell identification. These and other inefficiencies and opportunities for improvement are addressed and/or overcome by the assemblies, systems and methods of the present disclosure.

Automated cell identification using shearing interferometry