The present disclosure envisages a process for pelletizing carbon black by mixing carbon black powder and water in a proportion in the range of 0.1:2 to 2:1 with a binding agent and a dispersing agent. The dispersing agent is an amine-based surfactant and is added in a proportion in the range of 0.005-0.1% of the total mixture. The mixture is pelletized in a pelletizer and subsequently the raw pellets are dried for 20-60 minutes at a temperature between 150-250° C., to obtain the carbon black pellets. The process of the present disclosure provides uniform distribution of water on the surface of the pellets giving a uniform pellet quality, reduced water consumption, energy savings and an increased production rate.

In industry, loose carbon black is commonly formed as carbon black pellets by a pelletization process, since carbon black in the pellet form provides an increased density and easy handling and transportation. Also, carbon black in the pellet form is easier to use in the various processing equipments. Therefore, most of the industrial applications involving carbon black demand pelletization. Conventionally, a pelletization process involves adding a solution of water and a binding agent to carbon black powder to obtain a mixture, the mixture is pelletized in a drum pelletizer or a pin pelletizer. Later, thermal processing is provided to dry the pellets obtained from the pelletizer so as to remove the moisture.
One major drawback of the conventional pelletization method is the improper distribution of water and binding agent in the mixture with carbon black. To overcome this drawback and meet the pellet quality requirements, excessive water is added. Later, during thermal processing, the water is removed by application of heat, typically in a rotary drum dryer. Excess water results in an increased load on the dryer and a resultant drop in the production output of the process. Also, the energy required for drying and the time taken in drying is increased due to the excess water. Therefore, the uniform distribution of water and the binding agent in the mixture with carbon black is crucial in the pelletization process. Further, due to improper distribution of the pelletization components, the quality of the carbon black pellets so produced is not uniform.
The use of dispersing agents has been studied in the past, so as to effect a more uniform dispersion of the carbon black in an end-use application, for example: in rubber or plastic. However, there is still felt a need to provide an improved pelletization process which ensures uniform distribution of water and the binding agent in the mixture with carbon black, so as to obtain carbon pellets having uniform quality.
Several attempts have been made to provide a pelletization process for carbon black that overcomes one or more of the drawbacks listed above. Some of the disclosures are listed in the prior art below:
U.S. Pat. No. 3,776,750 discloses a two-stage process for pelletizing carbon black. The first stage comprises forming a first mixture of carbon black and an oil-water emulsion and the second stage involves adding water to the first mixture to obtain a second mixture. The second mixture is then agitated to form carbon black pellets. The process as disclosed in U.S. Pat. No. 3,776,750 aims at providing soft pellets which can be disintegrated easily and dispersed in rubber.
U.S. Pat. No. 3,956,445 discloses an improved carbon black pelleting method which produces layered pellets having relatively high density. The method comprises the steps of combining an aqueous pelleting liquid and loose carbon black in a weight ratio of about ⅔ to 2, and agitating the resultant mixture in a pellet mill to form pellets. Additional carbon black is added in a series of increments and additional water is finally added. By controlling the relative amounts of carbon black, pelleting liquid, and the time of addition of incremental carbon black, the layered pellets are formed.
U.S. Pat. No. 4,102,967 discloses a method for pelleting carbon black to produce layered carbon black pellets having a hardened outer shell. The method comprises the steps of: introducing an aqueous pelleting liquid and loose carbon black in a weight ratio of about 2:3 to about 2:1, agitating the mixture in a pellet mill to form pellets, introducing additional carbon black into the mill, and finally introducing an additional liquid containing ammonium lignin sulfonate or hydrocarbon oil into the mill to obtain layered pellets. The layered pellets so obtained reduce dispersion related problems and dusting problems while handling.
The present disclosure aims at providing an improved process for pelletizing carbon black, the process primarily aims at providing a uniform distribution of water and the binding agent on the surface of the carbon black pellets, thereby, providing uniform dispersion of carbon black in end-use applications. Also, the present disclosure aims at reducing the water consumption and conserving energy while increasing the productivity and enhancing the pellet quality.

Process for the preparation of carbon black pellets

Aditya Birla Science & Technology Company Limited


A computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded in each component of the computer for which the ability to detect faults and isolate failed devices is disclosed. The computer system comprises one or more CPU""s, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU""s, memory modules, and master control device. The master control device also connects to the CPU""s and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices. After a device is determined to be non-functional, one of the CPU""s stores that device""s unique ID code in the failed device log. Using the list of physical devices from the failed device log, the CPU creates a logical resource map which includes a list of logical addresses of all available (i.e., fully functional) devices. The logical resource map is provided to the computer""s operating system which isolates failed devices by only permitting access to those logical devices listed as available in the logical resource map.

1. Field of the Invention
The present invention generally relates to fault detection in computer systems. More particularly, the invention relates to the use of unique device identification codes stored in non-volatile memory to track failed devices in a computer system. Still more particularly, the present invention relates to a system in which failed components may be tracked physically through the use of stored or embedded identification codes.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modem computer systems. These components typically include one or more central processing units (CPU""s), an array of random access memory (RAM) modules, and certain peripheral devices such as a floppy drive, a keyboard, and a display. The components generally are interconnected by one or more xe2x80x9cbusses.xe2x80x9d A bus is a collection of digital signal lines over which data, address, and control signals are conveyed between devices connected to the bus according to a predetermined protocol. Examples of industry standard bus protocols include the Peripheral Component Interconnect (PCI) bus, the Industry Standard Architecture (ISA) bus, and Universal Serial Bus (USB).
For a computer system to operate successfully and efficiently, its components must function correctly. To ensure proper operation in the event of a failed component, the computer system must be capable of (1) detecting the failure, and (2) isolating the failed component so it is no longer accessed. Accordingly, many computer systems include logic for detecting when a device has failed and isolating the failed device to prevent its subsequent use by other devices (such as the CPU) in the computer system. Although the sophistication of personal computer systems continues to increase, there continues to be a concern that components may fail during operation. To protect against this eventuality, fault detection systems continue to play an important role in the operation of computer systems. The present invention relates to an improved fault detection and isolation technique.
To understand conventional fault detection and isolation schemes, it is important to understand the interaction between the computer""s hardware components and the operating system (e.g., Windows(copyright) 95). Application software, such as a word processor or game, uses the operating system to access the computer""s hardware components to manipulate data. For example, a particular application program may require access to data on a hard disk drive. The operating system translates a data access request from the application program into one or more device level operations to obtain the requested data for the application program. The application program need not access the hard disk directly, but does so indirectly via the operating system.
Many devices, such as system memory and the CPU are assigned a xe2x80x9clogicalxe2x80x9d address during system initialization (xe2x80x9cboot-upxe2x80x9d). As such, it is common to refer to a xe2x80x9cphysicalxe2x80x9d device or a xe2x80x9clogicalxe2x80x9d device; the physical device refers to the actual hardware device, and the logical device and refers to the device as it is mapped into the logical address space. For example, system memory may comprise 4 megabyte (MB) dual in-line memory modules (DIMM""s). Each physical DIMM, therefore is a 4 MB xe2x80x9cphysicalxe2x80x9d DIMM. During boot-up, each physical DIMM is assigned a 4 MB logical address range. One physical DIMM might be assigned the 0-4 MB address range, while another DIMM might be assigned the 4-8 MB address range. The operating system accesses a particular memory location in each DIMM typically by using its starting logical address (0, 4 MB, etc.), and also an offset from the starting logical address to the targeted memory location.
Assigning logical addresses to physical devices permits efficient use of the computer""s physical resources by the operating system and applications software. Software can then be developed to run on computers with different hardware configurations; the software need only be aware of the logical addresses of the various devices. Further, if a user moves a physical device from one location in the computer to a new location, the logical address assignment may change (during boot-up) and the computer""s software and operating system will be unaffected other than being made aware of the device""s new logical address.
Most computer systems run various tests during boot-up in a process generally referred to as xe2x80x9cpower on self testxe2x80x9d(POST). The POST routines are part of the Basic Input Output System (BIOS) code that is stored in read-only memory (ROM) and executed by the CPU. During execution of the POST routines, the various devices in the computer system, such as the CPU and memory, are tested to ascertain whether each device is working properly. Different types of devices are tested in different ways. Memory, for example, is tested by writing (i.e., storing) a known test data value to the memory device to be tested, and then reading (i.e., retrieving) the data value from the memory device to ensure the value read matches the value written. If a match does not exist, the memory is deemed defective; otherwise, the device is assumed to be functional. A CPU typically includes logic to test itself. The operational state of a CPU can be ascertained by the BIOS code reading the contents of various status registers internal to the CPU that indicate the CPU""s functional states. Device testing also occurs to a certain extent after POST while the computer system is undergoing normal operation.
After the computer""s hardware devices are tested, the BIOS code provides the operating system with a Logical Resource Map (LRM) which includes the logical addresses of only those devices that are fully functional. The operating system will not permit access to those logical devices not listed in the LRM, thereby isolating those devices from use in the computer. Further, if a device fails during operation of the computer and the failure is detected, the logical resource map is changed to indicate to the operating system that the failed device is no longer available.
The CPU also uses the BIOS code to maintain a list of failed logical devices in a xe2x80x9cfailed device logxe2x80x9d (FDL) stored in non-volatile memory (i.e., memory whose contents are not erased when power is removed from the device). During boot-up, the BIOS code reads the failed device log to determine which logical devices were previously reported as failed. As the BIOS code creates the logical resource map to be provided to the operating system, the BIOS code will not include those logical devices that have been reported previously as failed. Accordingly, fault detection and isolation involves determining that one or more of the computer devices is defective, and prohibiting further access to that device by the operating system even after the computer has been turned off and then re-started.
The user, however, may wish to take remedial actions when the computer reports the presence of a failed device. For example, if the BIOS code determines that a CPU is defective, the user may replace the defective CPU with a new CPU. If a memory device has failed, the user may wish to replace the defective memory device or simply add additional memory modules without removing the defective device. In some situations, only a portion of the memory device has failed and most of the memory locations in the memory device may still be fully functional. As such, the user may not wish to replace the memory device. Instead, the user may leave the partially defective memory device in the computer and add an additional memory device to make up for the loss of memory capacity resulting from the defective memory locations.
When repairs or alterations to the computer configuration are made, the possibility exists that the FDL will no longer match the physical configuration of the computer. The following examples illustrate this problem. If a user removes a defective device, such as a CPU, and replaces it with a new device, the new CPU likely will be assigned the same logical address as the defective CPU. The FDL identifies which logical devices had previously been reported as failed. Upon subsequent system initialization, the BIOS will read the FDL and erroneously determine that the device at that logical address is still defective. Further, the new logical CPU will not be included in the LRM. Unless the user tells the computer system that the defective CPU has been replaced, the operating system will not permit access to the new CPU simply because the logical address associated with that new device is still tagged as failed in the FDL, and accordingly is not included in the LRM. This erroneous result can be remedied by the user running a known utility program that resets the failed device log so that upon subsequent boot-up, the logical address associated with the replaced device is associated with a previously identified failed component. This solution, however, places a burden on the user to know that it is necessary to run such a utility program, to know which utility program to run, and how to run the program.
Another example of the mismatch that can occur between the physical configuration of a computer and the failed device log relates to the system memory. Most computer systems available today include system memory comprising one or more memory modules. The memory modules may be implemented as single in-line memory modules (SIMM""s), dual in-line memory modules (DIMM""s), or any other type of available memory technology. These memory modules typically include connectors that mate with corresponding connectors (commonly referred to as xe2x80x9cslotsxe2x80x9d) on the computer system xe2x80x9cmotherxe2x80x9d board. Many computers include connectors for eight or more memory modules, although not all of the available slots need be populated with memory modules.
The BIOS code assigns a logical memory address range to each memory module on the mother board. If one of the memory modules is found to be defective and, instead of replacing the defective memory module, the user simply adds a new module, it is possible for the newly inserted memory module to be assigned the logical address range previously assigned (i.e., assigned the last time the computer was turned on) to the defective memory module. Further, the defective memory module may be given a logical address range different than previously assigned to the defective module and not previously tagged as failed in the failed device log. During subsequent boot-up, the BIOS will read the FDL and, unless a suitable utility program is run by the user, the BIOS will report to the operating system via the logical resource map that the newly inserted memory module is defective. This erroneous result occurred because the new memory module was assigned the logical address range previously assigned to the defective module. Further, the BIOS will also erroneously report to the operating system that the defective memory module is available for use because its logical address range had not been previously tagged as failed in the failed device log. These problems can be remedied by the user running a utility program to inform the BIOS code of the new memory configuration. As noted above, however, running the utility program places an undesirable burden on the user.
Accordingly, a computer system that solves the problems noted above would be beneficial. Such a computer system preferably would be capable of accurately tracking failed devices even if those devices have been replaced or assigned to different logical addresses. Further, the new computer system preferably reduces or eliminates the necessity of the user running utility programs when a physical device is removed or replaced or a new device is added to the computer. Despite the advantages that such a system would offer, to date no such system has been introduced.
The deficiencies of the prior art described above are solved in large part by a computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded, or otherwise stored, in particular computer components. Examples of such devices in which ID codes could be embedded include, for example, the CPU (or CPU""s if multiple processors are included in the computer system) and memory modules comprising the computer""s main system memory. The use the embedded or storage ID codes enables the fault detection and isolation technique to track physical devices instead of logical devices.
In accordance with the preferred embodiment, the computer system comprises one or more CPU""s, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU, memory modules, and master control device. The master control device also connects to the CPU and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module, and any other device for which physical tracking is desired, includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory coupled to the CPU by way of the North bridge device. After a device is determined to be non-functional, either during POST or during normal system operation, a CPU stores that device""s unique ID code in a failed device log in the non-volatile memory. Using the list of failed physical devices, the CPU creates a logical resource map which includes a list of logical addresses of all available (i.e., fully functional) devices. The logical resource map is provided to the computer""s operating system which only permits access to those logical devices listed as available in the logical resource map.
During initialization, a CPU reads the list of ID codes from the failed device log, and the master control device retrieves the ID code from each physical device connected to the master control device. The master control device provides the retrieved ID codes from each device to the CPU, which then compares the list of ID codes from the failed device log with the list of ID codes retrieved from the devices by the master control device. If one of the device ID codes matches an entry in the failed device log, the CPU does not include the logical address associated with that physical device in the logical resource map. The operating system will not permit access to a logical device that is not listed in the logical resource map.
By tracking failed devices using an ID code unique to each device, the pitfalls described above regarding tracking logical devices can be avoided. The various characteristics described above, as well as other features, will be readily apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments of the invention, and by referring to the accompanying drawings.
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings, in which:
FIG. 1 is a block of a computer system constructed in accordance with the preferred embodiment hand including devices with embedded identification numbers; and
FIG. 2 is a flowchart representing a preferred method for determining which devices in the computer system of FIG. 1 are available for use and which devices are defective.

Computer system implementing fault detection and isolation using unique identification codes stored in non-volatile memory

Compaq Information Technologies Group, L.P.


A process and apparatus for highly efficient production of industrial gases by the cryogenic distillation of air, wherein a feed stream of compressed air, is supercharged to high pressure, cooled, and mixed with various recycle streams of supercharged air, to regulate the expander turbine operating temperature. The need for pre-cooling equipment downstream of the supercharger, which is widely employed in industry to manage the temperature of the incoming compressed air stream, is eliminated.

The present invention relates to a method of producing, in gaseous form and under high pressure, at least one fluid chosen from oxygen, argon and nitrogen, in which method air is distilled, the said fluid is brought in the liquid state to the high pressure, it is vaporized and warmed at this high pressure in the heat exchange line of the installation.
In the present specification, "high pressure" means a pressure greater than 10 bar in the case of oxygen, argon and nitrogen, and "blower" means a compressor having a single compression stage. Furthermore, the pressures in question are absolute pressures.
When producing oxygen, these methods, called "pumped" methods, have the advantage of dispensing with the oxygen compressor, which is a costly machine, poses serious reliability problems and has high maintenance costs.
EP-A-0 504 029 describes a method in which all the air is compressed to a high pressure in a blower, a portion of the high-pressure air is expanded in a Claude turbine (that is a Claude turbine which discharges into the medium-pressure column) and the rest of the air exchanges heat with the liquid oxygen in the process of vaporizing in the exchange line.
In this type of unit, it is desirable to have a means of preventing the inlet of the turbine becoming too cold, for example in the event of change of operation.
FR-A-2 688 052 describes a method in which:                air in the process of cooling in the heat exchange line is extracted from the latter at an intermediate temperature close to the vaporization temperature of the said fluid, or to its pseudo-vaporization temperature if the high pressure is supercritical;        this air is compressed in a blower;        it is reintroduced into the heat exchange line and at least one expansion of a cycle gas is effected in a turbine.
EP-A-0 644 388 describes a method in which a portion of the air is compressed to the medium pressure and sent into the medium-pressure column of a double column while the rest of the air is supercharged at ambient temperature. A portion of the supercharged air is then compressed in a cold supercharger.
During the start-up of the units according to EP-A-0 644 388 and FR-A-2 688 052, the air extracted from the heat exchange line is at the inlet of the blower at ambient temperature due to the fact that there are very few cold gases that warm up in the exchange line. Following compression, it returns to a temperature that may be as high as 120° C., compared with the temperature of approximately −120° C. when the unit is in stable operation. This may damage the exchange line, which is not designed to withstand such high temperatures.

Method and installation for producing, in gaseous form and under high pressure, at least one fluid chosen from oxygen, argon and nitrogen by cryogenic distillation of air

L'Air Liquide, Societe Anonyme A Directoire et Conseil de Surveillance pour l'Etude et l'Exploitation des Procedes Georges Claude


In response to an automatic baseline input, a default control template for a site in a telecommunications network is translated into monitoring and simulation templates. Current end-to-end application and component information are translated into operational modes for monitoring and simulation modules according to the monitoring and simulation templates. Operational controls are established for controlling the monitoring and simulation modules for controlling, in real time, the transmission of network management and simulation traffic.

1. Technical Field
The present invention relates to automatic control of monitoring and simulation within closed-loop control methodologies applied to the field of on-line business bandwidth management tools.
2. Discussion of Related Art
Simply stated, the current rate of change in business bandwidth management is getting out of control. IT business owners and service providers are struggling to manage business systems. Transport of data is exploding at unbelievable growth rates and some service providers are straining at full capacity. Even though data from multimedia networks is still a relatively small proportion of the whole, this is expected to change in the near future. The performance of these streaming protocols is not visible to network probes and sniffers. Service providers and business managers mistrust each other due to the stressful environment. Most service provider contracts are now mandating service level agreements (SLAs) to try to get a mechanism in place to enforce what is promised versus what is delivered. Business managers are contemplating increasing their outsourcing due to the need for outside assistance in managing their networks and therefore new dynamic services are needed. Furthermore, in view of the fact that dynamic routing and the impending internet to "virtual" services model will obsolete current modeling and planning tools new solutions are needed.

Auto control of network monitoring and simulation


In accordance with the invention a system is described for controllably varying the resolution of an image event to conserve data output by varying the size of the instantaneous IFOV of an array of detectors. The system comprises a multiplicity of individual detectors which produce an electrical signal in response to an image stimulus. The detectors are connected to busing circuitry by a circuit associated with each individual detector and which is in parallel with the circuits from the other detectors. Each parallel circuit includes a switch for making and breaking the parallel circuit to the busing circuit and control means are provided for opening and closing the switches in real time. As the switches are opened and closed the output signals of the detectors are combined into signals representing pixels having various size instantaneous fields of view depending on the number of detectors whose signals are combined. Combining detector output signals reduces the data output and conserves data processing capacity.

The operation of any scanning system requires that the successive radiation signals from a given pixel in the viewed scene be converted into an output signal representing that particular pixel. In a line array system, this may be accomplished by a direct, synchronized transfer and conversion of each pixel input signal to a corresponding output signal available to the observer.
This transfer may require integration of successive signals from a given pixel prior to electronic transfer of the pixel output. The common method used for such integration is the use of a semiconductor charge transfer device (CTD) array, such as a charge-coupled device (CCD) array, or a bucket-brigade (BB) array. Background noise is a substantial problem, however, when employing a two-dimensional focal plane as contrasted to a line scanner in which the signal is proportional to changes in intensity as the scene sweeps across the detector. Many of the prior art difficulties in providing adequate photo-detector signals from a two dimensioned focal plane have been solved by the "Z-technology" developed by the assignee of this application. The term "Z-technology" refers to the fact that a focal plane module, which has circuit carrying layers perpendicular to the focal plane, has a depth dimension Z in addition to the X and Y dimensions of the focal plane.
Maximum image enhancement, such as would be required to observe an image at maximum range, requires the smallest instantaneous field of view (IFOV). The minimum IFOV is equivalent to one pixel which is represented by the area of object space observed by one detector at a given time. Utilizing Z-technology a large number of detectors can be assembled to observe a large search volume comprising a plurality of focal planes, such as would be required in an aircraft scanning and tracking system. Such systems, however, require enormous data processing capabilities which are beyond the capabilities of most, if not all, data processing equipment currently available. Presently available scanning and tracking systems, particularly those using Z-technology, use various methods to compress or reduce the amount and rate of data output in order effect data processing. For example, one such method is the so-called "thresholding" technique in which only those pixels containing targets or target-like objects are passed to the data processor. However, if the thresholding is accomplished with high sensitivity, most of the background noise passes through the filter to the data processor. On the other hand, if threshold sensitivity is reduced small targets become lost in the background clutter.

Apparatus and system for controllably varying image resolution to reduce data output


The invention relates to a method to adhere a hard cellulose ester compound to a surface of a soft thermoplastic elastomer compound and shaped composite articles comprising said components.

1. Field of the Invention
The present invention relates to composite articles of a hard and a soft component having improved adhesion to each other and a method for improving the adhesion. In detail, the hard component is selected from cellulose esters and the soft component is selected from thermoplastic elastomers.
2. Background/Prior art
Cellulose esters are polymers made from renewable energy sources which become more and more popular because of their natural origin. Cellulose esters are transparent which makes them a candidate of choice for applications where transparency and clarity is needed. Furthermore, cellulose esters can be plastisized which increases their toughness at low temperatures. One representative cellulose ester is cellulose propionate.
There are many applications, for instance, in the automobile industry or for mechanical rubber goods, in which a combination of flexible and rigid materials is required. In most cases, a soft component is adhered onto the rigid cellulose propionate. Actually, this can be achieved by putting an adhesive system between the surface and the hard component of the article. These methods, however, are inherently expensive since they require extensive laboratory time. For details it is referred to A. Van Meesche and C. Radar, Adhesion of Elastomeric Alloy Thermoplastic Vulcanizates, in `Elastomerics`, September 1987, pages 21 to 24 and J. P. Vander Kooi and L. A. Goettler, Bonding Olefinic Thermoplastic Elastomers, in `Rubber World`, May 1985. EP-A-0 718 347 discloses a method to adhere thermoplastic elastomer blends to polyester substrates by treating the surface of the substrate with a blocked diisocyanate and optionally an epoxy resin.
One way to reduce the cost of the manufacture of the article is, for instance, to use sequential injection molding, a process during which the soft part is over-molded onto the rigid or hard material, and vice-versa. This technology gives outstanding adhesion between the soft and the hard polymers if they are miscible or at least compatible. If the two polymers are incompatible, they do not adhere together.
Cellulose esters and, as an example, cellulose propionate, are known to be incompatible with any other polymer (see Paul, Polymer Blends, Vol. 1 and 2, Academic Press, New York, 1977).
Therefore it was an object of the present invention to provide a method for adhering polymers, and in detail non-polar thermoplastic elastomers to cellulose esters providing an outstanding adhesion when over-molded, co-molded, co-blow molded or co-extruded.

Composite article of cellulose esters and thermoplastic elastomers


There are provided novel compounds of formula (I), wherein R1, R2, R3, T, U, X, Y, V and W are as defined in the specification, and pharmaceutically acceptable salts thereof, and enantiomers and racemates thereof; together with processes for their preparation, compositions containing them and their use in therapy. The compounds are inhibitors of nitric oxide synthase and are thereby particularly useful in the treatment or prophylaxis of inflammatory disease and pain

Nitric oxide is produced in mammalian cells from L-arginine by the action of specific nitric oxide synthases (NOSs). These enzymes fall into two distinct classes—constitutive NOS (cNOS) and inducible NOS (iNOS). At the present time, two constitutive NOSs and one inducible NOS have been identified. Of the constitutive NOSs, an endothelial enzyme (eNOS) is involved with smooth muscle relaxation and the regulation of blood pressure and blood flow, whereas the neuronal enzyme (nNOS) appears to be involved in the regulation of various biological functions. Inducible NOS has been particularly implicated in the pathogenesis of inflammatory diseases. Regulation of these enzymes should therefore offer considerable potential in the treatment of a wide variety of disease states (J. E. Macdonald, Ann. Rep. Med. Chem., 1996, 31, 221–230).
Considerable effort has been expended to identify compounds that act as specific inhibitors of one or more isoforms of the enzyme nitric oxide synthase. The use of such compounds in therapy has also been widely claimed.

Arylheteroalkylamine derivatives and their use as inhibitors of nitric oxide synthase


The present invention relates to a microwave cable and connector. The microwave cable includes a cable center conductor, a cable dielectric surrounding the cable center conductor and a cable outer conductor surrounding the cable dielectric. A connector body is provided that surrounds the cable outer connector. The connector body has a reduced diameter portion extending beyond the edges of the cable dielectric and the cable outer conductor, and the reduced diameter portion further extends radially inwardly to create a step. The diameter across the step is less than the diameter of the cable dielectric, and the step at the end of the connector body is able to block movement of the cable dielectric. The connector body includes at least one soldering hole that extends through the connector body in a circular recess formed in the connector body dimensioned for receipt of a snap ring.

SubMiniature version A ("SMA") shell connectors are defined in military and trade specifications. Some of these connectors use the center conductor of the cable as the connector center contact, and the cable dielectric as the connector dielectric. Most coaxial connectors have separate contacts and dielectric inserts that hold the center conductor centrally within the connector. This connector is used primarily on a cable having an outer diameter of 0.141 inches and provides a low cost, very short microwave connector. Assemblies using this cable and connector combination generally are used to interconnect microwave modules mounted on printed circuit boards or microwave sub-assemblies.
An example of a standard, commercial shell-only SMA connector according to the prior art is shown in FIG. 1. A cable 10 is provided with a center conductor 14 surrounded by a dielectric 16. An outer conductor 12 surrounds the dielectric 16. The connector 20 is soldered on the outer conductor 12 of the cable 10 by applying solder 18 to the rear of the connector 20. The solder 18 then flows internally in the connector 20, between the connector 20 and the outer conductor 12, to complete an electrical path. The disadvantage of this construction is that a ring of solder is formed at the joint of the cable 10 and connector 20 at the rear of the connector 20. This limits where the cable 10 can be bent, thus preventing a tight bend at the rear of the connector 20 from being formed when necessary.
Another way to attach the connector to the cable is to solder the connector from the front of the cable at the connector interface. While this eliminates the solder build-up at the rear of the connector, solder instead builds up on the connector interface. The interface therefore must be machined by a separate operation during manufacture to eliminate the solder build up at the connector interface, where the male SMA connector would mate with a female SMA connector. This operation removes the gold plating on the connector interface and also tends to easily damage the center conductor of the cable, which projects outwardly.
A further, significant problem exists with either of these connector designs. After assembly, when the cable is twisted or bent, the cable dielectric can move forward and extend beyond the connector mating face (reference plane 60), and thus prevent proper mating with another connector.
The present invention addresses these shortcomings in in the prior art by eliminating the solder at the rear of the connector, eliminating the need to machine the interface, eliminating cable dielectric protrusion, and compensating for the interface capacitance caused by the mating of connectors with different inner and outer conductor diameters.

Electrically compensated SMA shell connector with cable dielectric captivation


A fluid dispenser having a dispensing valve movable between open and closed positions for controlling the flow of the fluid from the fluid dispenser. A solenoid is operatively connected to the dispensing valve and is capable of moving the dispensing valve between the open and closed positions. The fluid dispenser further includes a power supply having a voltage and a driver circuit electrically connected to the solenoid and the power supply. The driver circuit provides an output signal to the solenoid having a time variable component, for example, a peak current duration, determined as a function of the voltage of the power supply. Thus, the driver circuit automatically adjusts to, and can be used with, power supplies of different voltages. The invention further includes a method by which the driver circuit provides the output signal as a function of the power supply voltage.

Pneumatic and electric fluid dispensers have been developed for dispensing applications requiring a precise placement of a fluid. Pneumatic dispensers have a significant advantage in that the pneumatic solenoid operating the dispensing valve provides a sufficient force so that the dispensing valve operation is essentially independent of the viscosity of the fluid being dispensed. However, pneumatic solenoids have disadvantages in that they generally have a shorter life than electric solenoids, and the operation of the pneumatic solenoid is subject to less precise control than the electric solenoid in an electric fluid dispenser. Therefore, in some applications, electrically operated fluid dispensers are preferred over pneumatic fluid dispensers.
Generally, electrically operated fluid dispensers include an electromagnetic coil surrounding an armature that is energized to produce an electromagnetic field with respect to a magnetic pole. The electromagnetic field is selectively controlled to open and close a dispensing valve by moving a valve stem connected to the armature. More specifically, the forces of magnetic attraction between the armature and the magnetic pole move the armature and valve stem toward the pole, thereby opening the dispensing valve. At the end of a dispensing cycle, the electromagnet is de-energized, and a return spring returns the armature and valve stem to their original positions, thereby closing the dispensing valve.
In the operation of an electric fluid dispensing gun, the coupling between the coil and the armature is not efficient; and therefore, in order to achieve the highest actuation speed, a current pulse or spike is typically provided to the coil during an initial turn on period in order to initiate the motion of the armature as quickly as possible. After the initial current pulse, the current through the coil is then reduced to approximately the minimum value required to hold the armature in its open position against the opposing force of the return spring. Such a stepped current waveform provides high performance while minimizing power dissipation in the coil.
The continued development and use of fluid electric dispensers has resulted in more demanding performance specifications. For example, the operational speed of the dispensing valve can be increased by increasing the electrical voltage applied to the electric coil operating the valve. However, simply doubling the applied voltage without other changes to the solenoid driver circuit would cause overheating and possibly degrade the performance of the fluid dispenser. For example, if a high voltage power supply is used with a low voltage solenoid driver circuit, the solenoid will switch proportionally faster. However, the low voltage solenoid driver provides an initial current pulse having more power than is required by the solenoid which results in an inefficient operation of the coil. Therefore, if it is desired to use a higher voltage to operate the fluid dispenser at a higher rate, not only must a new power supply be used; but a different solenoid driver circuit must be used. The requirement of replacing the whole driver circuit to upgrade the performance of the fluid dispenser is labor intensive, time consuming and expensive.
While the above problem has been described with respect to an electrically operated fluid dispenser, a similar problem exists with respect to pneumatically operated fluid dispensers. Therefore, there is a need to provide a fluid dispenser having a driver circuit which is operable with different power supplies.

Self adjusting solenoid driver and method


A semiconductor laser device includes a substrate which is made of, e.g., silicon and which has in its principal surface first and second recessed portions formed at a distance from each other. Disposed in the first recessed portion is a first semiconductor laser chip in the form of a function block, which emits an infrared laser beam. Disposed in the second recessed portion is a second semiconductor laser chip in the form of a function block, which emits a red laser beam.

The present invention relates to semiconductor laser devices and methods for fabricating the devices, and more particularly relates to semiconductor laser devices which are used as a light source for the reading or writing of data from or on optical storage mediums such as compact discs and digital versatile discs, and methods for fabricating the devices.
Typical digital-versatile-disc (hereinafter referred to as "DVD") players need to function to play back compact discs (hereinafter referred to as "CDs") in addition to DVDs, and also have to function to replay, and store data on, recordable CDs (CD-Rs) which have become widespread rapidly in recent years.
As a light for replaying DVDs, a red laser beam with a wavelength in the 650 nm band is employed, while an infrared laser beam with a wavelength in the 780 nm band is used as a light for playing back CDs and CD-R discs. In the currently available DVD players, therefore, two semiconductor laser diodes are incorporated: one is a red semiconductor laser diode for generating a red laser beam and the other is an infrared semiconductor laser diode for generating an infrared laser beam.
With an increasing demand for smaller personal computers and other information equipment, DVD players also need to be reduced further in size and thickness. To that end, it is indispensable to reduce the size and thickness of optical pickup. Methods for reducing optical pickup in size and thickness include optical system simplification.
As a method for simplifying an optical system, integration of a red semiconductor laser diode and an infrared semiconductor laser diode is available. The current DVD players include two optical systems: one for a red semiconductor laser diode and the other for an infrared semiconductor laser diode. Integration of the red semiconductor laser diode and the infrared semiconductor laser diode allows one optical system to be shared, thereby realizing an optical pickup system of smaller size and thickness.
For instance, as one example of the integration of a red semiconductor laser diode and an infrared semiconductor laser diode, a so-called monolithic semiconductor laser diode array which is integrated on a substrate is disclosed in Japanese Laid-Open Publication No. 11-186651.
Japanese Laid-Open Publication Nos. 11-144307 and 11-149652 disclose another example, in which hybrid integration of two semiconductor laser chips, one for a red laser and the other for an infrared laser, enables an optical system to be shared in an optical pickup system.
Nevertheless, in the conventional monolithic two-wavelength laser diode array, the respective active layers of the laser diodes have different compositions and thus have to be grown in different process steps, which results in the problem of low yields. In particular, when high-output laser diodes are monolithically integrated, yields decrease significantly.
Moreover, it is very difficult, in the viewpoint of crystal growth, to monolithically integrate a gallium nitride (GaN)-based blue laser diode, which is used in high density DVDs, and an aluminum gallium indium phosphide (AlGaInP)-based red laser diode, which is used in typical (conventional) DVDs.
The conventional hybrid optical pickup, on the other hand, have the problem that when the red semiconductor laser chip and the infrared semiconductor laser chip are assembled using assembly equipment, it is difficult to control and optimize the locations of active layers of the semiconductor laser chips and the distance between the light emitting points thereof.
In recent years, mounting methods in which a fluidic self-assembly (hereinafter referred to as "FSA") technique is used have been developed as one type of device-mounting method.
In the FSA technology, devices (hereinafter referred to as "function blocks") ranging in size from 10 μm to several hundred μm and having given shapes are suspended into a liquid to form a slurry. The liquid (suspension) in the form of slurry is poured over the surface of a substrate in which recessed portions have been formed. The recessed portions are substantially the same as the function blocks in size and shape. In this manner, the function blocks that have been spread in the liquid are settled into the recessed portions and thereby mounted onto the substrate.
The FSA technology is disclosed in U.S. Pat. No. 5,545,291, U.S. Pat. No. 5,783,856, U.S. Pat. No. 5,824,186 and U.S. Pat. No. 5,904,545, for example.

Semiconductor laser device and method for fabricating the same

Matsushita Electric Industrial Co., Ltd.


A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the invention relates to a latch circuit and a flip-flop circuit which are data holding circuits using MOS transistors. The present invention also relates to a buffer circuit for use to input a signal to the data holding circuits.
2. Description of the Background Art
FIG. 24 is a circuit diagram of a conventional latch circuit. The latch circuit is shown as comprising transmission gates TG1 to TG4, inverter gates INV1 and INV2, first and second data input terminals DI and DIB, first and second clock input terminals CK and CKB, and first and second data output terminals DO and DOB.
The elements constituting the latch circuit will be described below. Each of the transmission gates TG1 to TG4 includes a PMOS transistor and an NMOS transistor which are connected in parallel and which have commonly connected source electrodes and commonly connected drain electrodes to form two current electrodes. Gate electrodes of the PMOS transistors of the transmission gates TG1 and TG2, and gate electrodes of the NMOS transistors of the transmission gates TG3 and TG4 are commonly connected to the first clock input terminal CK. Gate electrodes of the NMOS transistors of the transmission gates TG1 and TG2, and gate electrodes of the PMOS transistors of the transmission gates TG3 and TG4 are commonly connected to the second clock input terminal CKB.
The first data input terminal DI is connected to a first current electrode of the transmission gate TG1. A second current electrode of the transmission gate TG1 is connected to an input terminal of the inverter gate INV2 and is also connected to an output terminal of the inverter gate INVL through the transmission gate TG3.
Likewise, the second data input terminal DIB is connected to a first current electrode of the transmission gate TG2. A second current electrode of the transmission gate TG2 is connected to an input terminal of the inverter gate INV1 and is also connected to an output terminal of the inverter gate INV2 through the transmission gate TG4. The output terminals of the inverter gates INV1 and INV2 are connected to the first and second data output terminals DO and DOB, respectively.
Signals to be inputted to the latch circuit are described below. A signal at H level (high level, voltage level of a first power supply VDD) and a signal at L level (low level, voltage level of a second power supply GND) are mutually exclusively applied to the first data input terminal DI and the second data input terminal DIB. The signals at H and L levels different from each other are those at voltage levels indicative of opposite binary logics.
A data combination wherein data signals to be applied to the first and second data input terminals DI and DIB are at H and L levels respectively is referred to as first data DATA1. Similarly, a data combination wherein the data signals to be applied to the first and second data input terminals DI and DIB are at L and H levels respectively is referred to as second data DATA2.
Likewise, a signal at H level and a signal at L level are mutually exclusively applied to the first and second clock input terminals CK and CKB.
A data combination wherein clock signals to be applied to the first and second clock input terminals CK and CKB are at H and L levels respectively is referred to as a first clock input state CLK1. Similarly, a data combination wherein the clock signals to be applied to the first and second clock input terminals CK and CKB are at L and H levels respectively is referred to as a second clock input state CLK2.
The latch circuit has the above described connection and arrangement. Thus, the transmission gates TG1 and TG2 form a pair, and the transmission gates TG3 and TG4 form a pair. The two pairs are mutually exclusively in and out of conduction.
A series of circuit operations of the latch circuit are discussed below. Signal setting for determining the circuit operations (1) to (4) of the latch circuit will be described below. Signal setting numbers correspond respectively to circuit operation numbers.
Signal setting (1)
The latch circuit is in the first clock input state CLK1, and receives the first data DATA1.
Signal setting (2)
The latch circuit is in the second clock input state CLK2, and receives the first data DATA1.
Signal setting (3)
The latch circuit is in the first clock input state CLK1, and receives the second data DATA2.
Signal setting (4)
The latch circuit is in the second clock input state CLK2, and receives the second data DATA2.
FIGS. 25A to 25C are waveform charts representing a timing chart of the circuit operations (1) to (4) of the latch circuit in response to the signal settings (1) to (4). FIG. 25A shows the signal levels at the first and second data input terminals DI and DIB, FIG. 25B shows the signal levels at the first and second clock input terminals CK and CKB, and FIG. 25C shows the signal levels at the first and second data output terminals DO and DOB. The latch circuit functions to receive the data signals at the first and second data input terminals DI and DIB in synchronism with the clock signals to output the data signals which are phase-shifted by a half cycle of the clock signals, as will be described below with reference to FIGS. 25A to 25C.
1. Circuit operation (1) of latch circuit
The transmission gates TG1 and TG2 are off whereas the transmission gates TG3 and TG4 are on. Thus, the signals at the H and L levels applied respectively to the first and second data input terminals DI and DIB are not provided to the interior of the latch circuit.
2. Circuit operation (2) of latch circuit
The transmission gates TG1 and TG2 are on whereas the transmission gates TG3 and TG4 are off.
The signal at H level applied to the first data input terminal DI is applied to the inverter gate INV2 through the transmission gate TG1. In response to this signal, the inverter gate INV2 outputs a signal at L level through the second data output terminal DOB. Likewise, the inverter gate INV1 receives the signal at L level at the second data input terminal DIB through the transmission gate TG2 to output a signal at H level through the first data output terminal DO. Therefore, the first and second data output terminals DO and DOB output the first data DATA1.
3. Circuit operation (3) of latch circuit
The transmission gates TG1 and TG2 are off whereas the transmission gates TG3 and TG4 are on. Thus, the first and second data input terminals DI and DIB and the input terminals of the inverter gates INV2 and INV1 are isolated from each other by the transmission gates TG1 and TG2 which are off, respectively. Specifically, although the data DATA2 are applied to the first and second data input terminals DI and DIB, the signals at L and H levels are continuously applied to the input terminals of the inverter gates INV1 and INV2 respectively in a loop formed by the inverter gates INV1, INV2 and the transmission gates TG3, TG4 which are on. Therefore, the first data DATA1 are outputted continuously.
4. Circuit operation (4) of latch circuit
The transmission gates TG1 and TG2 are on, and the inverter gates INV1 and INV2 are electrically connected to the second and first data input terminals DIB and DI, respectively. The inverter gates INV1 and INV2 receive the signals at H and L levels to output signals at L and H levels through the first and second data output terminals DO and DOB, respectively. Therefore, the first and second data output terminals DO and DOB output the second data DATA2.
Subsequently, the first and second clock states CLK1 and CLK2 are alternately repeated in similar manner, and third data DATA3 phase-shifted by a half clock cycle are transmitted through the latch circuit.
A conventional flip-flop circuit will be described below which is provided by connecting two latch circuits shown in FIG. 24. FIG. 26) is a circuit diagram of a flip-flop circuit disclosed in "IEICE TRANSACTIONS on Electronics, vol. E78-C, No. 12, Dec. 1995, pp.1746-1753".
The flip-flop circuit of FIG. 26 comprises transmission gates TG1 to TG8, inverter gates INV1 to INV4, first and second data input terminals DI and DIB, first and second clock input terminals CK and CKB, and first and second data output terminals DO and DOB.
A process for connecting two latch circuits together is discussed below. As illustrated in FIG. 26, a first latch circuit comprises the transmission gates TG1 to TG4 and the inverter gates INV1 and INV2, and has the same connections of the elements as the latch circuit of FIG. 24. A second latch circuit comprises the transmission gates TG5 to TG8 and the inverter gates INV3 and INV4 which are connected in corresponding relation to the transmission gates TG1 to TG4 and the inverter gates INV1 and INV2, respectively.
The first and second data output terminals of the first latch circuit are connected to the first and second data input terminals of the second latch circuit, respectively. The first and second data input terminals DI and DIB of the first latch circuit serve as the first and second data input terminals DI and DIB of the flip-flop circuit, respectively.
Similarly, the first and second data output terminals DO and DOB of the second latch circuit serve as the first and second data output terminals DO and DOB of the flip-flop circuit, respectively.
The first clock input terminal of the first latch circuit and the second clock input terminal of the second latch circuit are commonly connected to serve as the first clock input terminal CK of the flip-flop circuit. The second clock input terminal of the first latch circuit and the first clock input terminal of the second latch circuit are commonly connected to serve as the second clock input terminal CKB of the flip-flop circuit.
The flip-flop circuit is constructed as above described. Thus, the transmission gates TG1, TG2, TG7, TG8 simultaneously turn on and off, and the transmission gates TG3 to TG6 simultaneously turn on and off in exclusive relation to the transmission gates TG1, TG2, TG7, TG8.
The operation of the flip-flop circuit will be described on the basis of the above-mentioned signal settings (1) to (4). FIGS. 27A to 27C are waveform charts representing a timing chart of the flip-flop circuit and illustrate the same signals as those of FIGS. 25A to 25C.
The clock input states and corresponding data input states in the latch circuit are identical for each signal setting with those in the flip-flop circuit. Thus, the circuit operation of the first latch circuit is identical with that of the above described latch circuit. Accordingly, the second latch circuit and the flip-flop circuit including the first and second latch circuits are mainly described below, with the description of unnecessary portions of the first latch circuit dispensed with.
1. Circuit operation (1) of flip-flop circuit: Signal setting (1)
The transmission gates TG1, TG2, TG7, TG8 are off whereas the transmission gates TG3 to TG6 are on. Since the transmission gates TG1 and TG2 are off, the signals at the first and second data input terminals DI and DIB are not transmitted to the second latch circuit.
2. Circuit operation (2) of flip-flop circuit: Signal setting (2)
The transmission gates TG1, TG2, TG7, TG8 are on whereas the transmission gates TG3 to TG6 are off.
The signal at H level applied to the first data input terminal DI is fed to the inverter gate INV2 through the transmission gate TG1. In response to this signal, the inverter gate INV2 outputs a signal at L level to the second latch circuit. However, since the transmission gate TG6 is off, the output signal from the inverter gate INV2 is not applied to the input terminal of the inverter gate INV3.
Similarly, the inverter gate INV1 receives the signal at L, level at the second data input terminal DIB through the transmission gate TG2 to output a signal at H level. However, since the transmission gate TG5 is off, the output signal from the inverter gate INV1 is not applied to the inverter gate INV4.
3. Circuit operation (3) of flip-flop circuit: Signal setting (3) The transmission gates TG1, TG2, TG7, TG8 are off whereas the transmission gates TG3 to TG6 are on. Specifically, the second latch circuit is in the state of the circuit operation (2) of the latch circuit. The transmission gates TG5 and TG6 are on to permit the signals at H and L levels from the inverter gates INV1 and INV2 to be applied to the inverter gates INV4 and INV3, respectively. Thus, the first and second data output terminals DO and DOB output the first data DATA1.
In the latch circuit, the first and second data output terminals DO and DOB thereof output the first data DATA1 in the circuit operation (2) of the latch circuit. It is hence appreciated that the output from the flip-flop circuit further lags by a half clock cycle behind the output from the latch circuit.
4. Circuit operation (4) of flip-flop circuit: Signal setting (4)
The transmission gates TG1, TG2, TG7, TG8 are on whereas the transmission gates TG3 to TG6 are off. The second latch circuit is in the state of the circuit operation (3) of latch circuit.
In the second latch circuit, the transmission gates TG5 and TG6 are off and the transmission gates TG7 and TG8 are on. Thus, the output terminals of the inverter gates INV2 and INV1 are isolated from the input terminals of the inverter gates INV3 and INV4 by the transmission gates TG6 and TG5, respectively.
The inverter gates INV3 and INV4 and the transmission gates TG7 and TG8 which are on form a loop wherein the signals at L and H levels are continuously applied to the input terminals of the inverter gates INV3 and INV4, respectively. Thus, the first and second data output terminals DO and DOB continuously output the first data DATA1.
Subsequently, the first and second clock states CLK1 and CLK2 arc alternately repeated in similar manner, and the third data DATA3 phase-shifted by one clock cycle are transmitted through the flip-flop circuit. It will be understood from the comparison between FIGS. 27C and 25C that the flip-flop circuit functions to receive the data signals at the data input terminals in synchronism with the clock signals, to temporarily hold the data signals, and to output the data signals phase-shifted by 2 operations of the latch circuit.
In other words, the flip-flop circuit and the latch circuit have the same function of receiving the data signal in synchronism with the clock signal and outputting the phase-shifted data signal. However, a phase difference of one operation of the latch circuit exists between the flip-flop circuit and the latch circuit.
FIG. 28 illustrates a buffer circuit for applying a clock signal or a data signal to the flip-flop circuit or the latch circuit. The buffer circuit is shown as comprising a signal input terminal CIN, an inverter gate INV5 having an input terminal connected to the signal input terminal CIN, a first signal output terminal CKO connected to an output terminal of the inverter gate INV5 through an inverter gate INV6, and a second signal output terminal CKOB connected to the output terminal of the inverter gate INV5.
The circuit operation of the buffer circuit is described below. When a signal at H level is applied to the signal input terminal CIN, the first signal output terminal CKO outputs a signal at H level through the two inverter gates INV5 and INV6, and the second signal output terminal CKOB outputs a signal at L level through the one inverter gate INV5. Likewise, when a signal at L level is applied to the signal input terminal CIN, the first signal output terminal CKO outputs a signal at L level, and the second signal output terminal CKOB outputs a signal at H level. In this manner, the buffer circuit produces two signals which are logically opposite with each other in response to the input signal.
In the above described flip-flop circuit or the latch circuit, signals are applied through the buffer circuit to the first and second data input terminals DI and DIB or the first and second clock input terminals CK and CKB. To use the buffer circuit for the flip-flop circuit as a clock buffer circuit for a clock signal, four PMOS transistors and four NMOS transistors are connected to the output terminals of the clock buffer circuit, respectively. To use the buffer circuit for the latch circuit as the clock buffer circuit for the clock signal, two PMOS transistors and two NMOS transistors are connected to the output terminals of the clock buffer circuit, respectively.
FIGS. 29A to 29C are waveform charts representing a timing chart of the buffer circuit, and illustrate signal levels at the signal input terminal CIN, the second signal output terminal CKOB, and the first signal output terminal CKO, respectively. A switching delay d5 of the inverter gate INV5 and a switching delay d6 of the inverter gate INV6 are shown in FIGS. 29B and 29C.
As depicted in FIGS. 29A to 29C, after the input signal was applied to the signal input terminal CIN, the second signal output terminal CKOB provides the output signal with the switching delay d5 and the first signal output terminal CKO provides the output signal with a switching delay d5+d6.
As above stated, the conventional latch circuit includes the four PMOS and NMOS transistor pairs constituting the respective transmission gates. Similarly, the conventional flip-flop circuit includes the eight PMOS and NMOS transistor pairs constituting the respective transmission gates.
Such arrangements are disadvantageous because of increased areas of the conventional latch and flip-flop circuits.
When the clock buffer circuit is connected to the flip-flop circuit, the four PMOS transistors and four NMOS transistors are connected to the first and second signal output terminals CKO and CKOB of the clock buffer circuit, respectively. When the clock buffer circuit is connected to the latch circuit, the two PMOS transistors and two NMOS transistors are connected to the first and second signal output terminals CKO and CKOB of the clock buffer circuit, respectively.
This excessively increases the load capacitance of the output terminals of the clock buffer circuit, causing the clock buffer circuit to consume a large amount of power during charging and discharging of the load capacitance.
Further, the conventional buffer circuit, wherein the number of inverter gates connected between the signal input terminal CIN and the first signal output terminal CKO is different from the number of inverter gates connected between the signal input terminal CIN and the second signal output terminal CKOB, causes a time delay between the signals outputted from the first and second signal output terminals CKO and CKOB. Additionally, two inverter gates between the first signal output terminal CKO and the signal input terminal CIN have a delay causing a corresponding signal output delay, resulting in low operating speed of the flip-flop circuit or latch circuit.


A micro switch for detecting forces in two orthogonal directions, rather than one, useable, for example, to detect out of size parts in one plane in a multiple spindle screw machine, and disengaged parts in an orthogonal plane. This is accomplished through the provision of a ramp that is slidably engaged by the switch's actuation rod as the rod moves in a first plane to translate sideway movement of the rod into perpendicular linear movement of the switch's plunger. The ramp has a recess that captures the rod as it moves in the orthogonal plane, which is coincident with the axis of the plunger, thereby causing switch actuation with plunger movement in two planes.

In multiple spindle screw machines, there are two distinct conditions that require machine shut-down. The first is a failure to properly turn the workpiece at any station and the second is the inadvertent disengagement of a part at any station. An automatic shut-down system for these conditions is desirable because it is difficult for a single operator to immediately view both of these conditions at all stations, frequently six or eight in number. It is possible to have two systems at each station to accomplish these tasks, such as a gauge to measure part diameter and a separate sensing barrier to detect part disengagement, but such systems are costly and hence tool buyers do not usually select these systems, particularly in cases where great precision is not required.
However, they both remain significant problems because they result in a high number of damaged parts if not detected immediately, and also broken tools.
Thus, it is a primary object of the present invention to ameliorate the problems noted above in systems for detecting conditions in two directions.


The invention relates to a method for the treatment of a surface of a silicon carbide (SiC) substrate, said substrate being used in semiconductor manufacturing processes. The invention also relates to a SiC substrate for use in semiconductor manufacturing processes treated with the method according to the invention. According to the invention, said method comprising the steps of selective etching the surface of said SiC substrate using a reactive gas mixture, thereby creating a carbon surface layer on said substrate, and removing said carbon surface layer being created on said substrate. Thus, with the method steps according to the invention, SiC substrates can be obtained with a surface structure that complies with the highest standards as regard to dimensions and purity as required in semiconductor manufacturing processes. In particular, SiC substrates treated according to the steps of the invention are highly suitable for use as wafer boats for handling and containing semiconductor wafers on which subsequent treatment process steps of the semiconductor manufacturing processes (such as semiconductor layer deposition or temperature annealing) are performed under accurate, well controlled working conditions (temperature, pressure and vacuum).

Silicon carbide (SiC) substrates are known for their use in semiconductor manufacturing processes. More particularly, SiC is used as starting material from which, for example, wafer boats or support rings are constructed. Such constructions serve as a holder and positioning means for multiple wafers, which wafers are subjected to several treatment steps during semiconductor fabrication. Such treatment process steps are performed under specific, well controlled conditions as regards to temperature, pressure and vacuum and can be the deposition of several semiconductor material layers on said wafers, for example using chemical vapor deposition techniques (CVD) or other process steps, such as temperature annealing.
It should be noted in this patent application that the term "silicon carbide substrates" includes not only wafer boat holders, but also other constructions or components made from a SIC material, which are used in semiconductor manufacturing processes, for example, in reactor vessels.
As the subsequent treatment process steps of the semiconductor manufacturing processes (such as semiconductor layer deposition) takes place under accurately controlled circumstances as regard as temperature, pressure and vacuum and also require so-called clean room environments needs to fulfill the highest standard as regard to purity and lack of contaminations, also the SiC substrates need to fulfill to the highest standard as regard to dimensions and thermal behavior.
To this end, the several SiC substrate components which form, for example, a wafer boat holder, are subjected to a mechanical machining operation in order to treat the substrate surface. However the surface treatment by means of a mechanical machining operation results in small, nearly invisible microcracks or holes in the surface of the SiC substrates. These microcracks or subsurface damage adversely affects the different subsequent semiconductor manufacturing processes (e.g., the semiconductor layer deposition or high temperature anneal) as all kinds of contaminations may accumulate in said microcracks, which contaminations can be freed from said micro cracks during the semiconductor process, thereby contaminate the semiconductor layer deposition on the wafers. The latter will result in significantly reduced quality or rejection of products.
A further drawback of the presence of subsurface damage on the SiC substrate is the risk of particle generation and emission during the semiconductor manufacturing processes. Due to the changing thermal conditions during the several semiconductor layer depositions, small SiC particles will come loose from the substrate and hence, contaminate the semiconductor manufacturing process.
It is an object of the invention to provide a method and a silicon carbide substrate as mentioned above which obviates the above-identified drawbacks. According to the invention, said method comprising the steps of selective etching the surface of said SiC substrate using a reactive gas mixture, thereby creating a carbon surface layer on said substrate, and removing said carbon surface layer created on said substrate.
Thus, with the method steps according to the invention, SiC substrates can be obtained with a surface structure that complies with the highest standards as regard to dimensions and purity as required in semiconductor manufacturing processes. Especially, SiC substrates treated according to the steps of the invention are highly suitable for use as wafer boats for handling and containing semiconductor wafers on which subsequent treatment process steps of the semiconductor manufacturing processes (such as semiconductor layer deposition or temperature annealing) are performed under accurate, well controlled working conditions (temperature, pressure and vacuum).
As all subsurface damage in the form of microcracks is removed with the removal of the carbon surface layer, a smooth and clean SIC surface is obtained having an extremely high purity, as also all impurities are removed. Furthermore, due to the removal of the subsurface damaged surface, the generation and emission of particles from the SiC surface, which particles may adversely affect the semiconductor manufacturing process, is herewith avoided.
Hence, with a SiC substrate treated with the method according to the invention, a higher degree of purity can be obtained during semiconductor manufacturing processes with a higher level of accuracy and lesser rejection of products.
In a specific embodiment of the method according the invention is the step of removing said carbon surface layer performed by means of an oxidation treatment technique.
In another embodiment of the method according to the invention is the step of removing said carbon surface layer performed by means of a hydrogenation treatment technique. In another embodiment, the step of removing said carbon surface layer is performed by means of a hydrothermical treatment technique.
Moreover, in an advantageous embodiment of the invention, a functional etching technique the reactive gas mixture being used during the step of etching the surface of said SiC substrate is a halogen-containing gas mixture, wherein the halogen-containing gas concentration of said reactive gas mixture can be 100%.
In another embodiment according to the invention, the halogen-containing gas is chlorine (Cl2), for example, in an Argon-environment.
Furthermore, in another advantageous embodiment with an excellent etching performance, the reactive gas mixture also contains hydrogen (H2).
In an example, the flow rate of said reactive gas mixture is 0.5-5 liters per minute, whereas, the working pressure of said reactive gas mixture may lie between 100 mbar and the ambient pressure, and wherein the working temperature of said reactive gas mixture may lie between 1000° C. and 1200° C.
The SiC substrate for use in semiconductor manufacturing processes is, according to the invention, characterized in that said SiC substrate comprising a surface, wherein on said surface a carbon surface layer is formed by means of an etching technique using a reactive gas mixture, which carbon surface layer is subsequently removed from said substrate.
Likewise is in an specific embodiment of the SiC substrate according to the invention, said carbon surface layer removed by means of an oxidation treatment technique. Or said carbon surface layer can be removed by means of a hydrogenation treatment technique.
Likewise said carbon surface layer can be removed by means of a hydrothermical treatment technique.
In a specific embodiment of the SiC substrate according to the invention, said SiC substrate surface is subjected to a reactive gas mixture consisting of a reactive gas mixture containing a halogen-containing gas mixture.
Furthermore, in a more specific embodiment, said halogen-containing gas concentration of said reactive gas mixture is 100%, and more in particular, said halogen-containing gas is chlorine (Cl2) in an Ar-environment. Furthermore, the reactive gas mixture may also contain hydrogen (H2).
Likewise the flow rate of said reactive gas mixture may lie between 0.5-5 liters per minute, whereas said SiC substrate surface may be subjected to a working pressure of said reactive gas mixture between 100 mbar and the ambient pressure, or whereas said SiC substrate surface is subjected to a working temperature of said reactive gas mixture between 1000° C. and 1200° C.

Method for the treatment of a surface of a metal-carbide substrate for use in semiconductor manufacturing processes as well as such a metal-carbide substrate


A night light having a lamp socket for holding a lamp and a lamp shade around the lamp such that when the lamp shade is removed from the lamp socket, power to the lamp is automatically interrupted.

1. Field of the Invention
This invention relates generally to a night light and, more particularly, to a lamp holder having a safety switch which automatically interrupts the flow of electricity to the lamp when a detachable lamp shade is removed from the lamp holder.
2. Description of the Related Art
Night lights for residential use are well known in the art. They are used primarily to dimly illuminate corridors and rooms. Night lights include a lamp socket for holding a lamp and a switch which serves to control the flow of electricity or power to the lamp. Night lights may include a lampshade for partially blocking light from a lamp to prevent glare. However, a night light may pose a danger to a person when the lamp is removed from the lamp socket because electricity may still be flowing to the lamp socket. What is needed is a night light that reduces such a danger.


The present invention relates to a digital-to-analog converter providing two complementary output signals varying inversely with respect to each other and by steps according to a digital datum to be converted, including circuitry for offsetting by one step the variation characteristic of one of the output signals.

1. Field of the Invention
The present invention relates to digital-to-analog converters providing two complementary outputs, and more specifically, to a digital-to-analog converter of R-2R type.
2. Discussion of the Related Art
FIG. 1 schematically shows a conventional digital-to-analog converter of R-2R type. In this type of converter, currents I/2, I/4, I/8 . . . stepped according to a geometric series of ratio 1/2 are generated. The series of currents includes as many currents as there are bits in a digital datum D to be converted (4 in the example of FIG. 1). Each of these currents is directed by a respective switch K to one or the other of two complementary outputs Io, Io* according to a respective bit of datum D. The currents of the series are provided by a network of resistors 10 of R-2R type. A current source 12 draws a current I of network 10 to a low supply potential Vee.
The first current I/2 of the series is provided by a resistor of value 2R connected to current source 12. The second current I/4 of the series is provided by two resistors of values R and 2R connected in series to current source 12. Each of the following currents of the series is provided by two resistors of values R and 2R connected in series to the connection node of the two resistors providing the preceding current.
The last current of the series is provided by a single resistor 13 of value 2R. This last resistor 13 provides a current equal to the penultimate current of the series (I/8 in the example), and must thus be divided by 2 to effectively provide the last current I/16 of the series. In the example shown in FIG. 1, resistor 13 is connected to the emitters of both cascode transistors Q1 and Q1' of identical characteristics, in which the current I/8 provided by resistor 13 is distributed. The bases of transistors Q1 and Q1' are biased by a same voltage Vb1. The last current I/16 of the series is taken from the collector of transistor Q1 while the collector of transistor Q1' is connected to a high supply potential Vcc. To ensure that network 10 and current source 12 operate in proper conditions, switches K are connected to the corresponding resistors of network 10 via respective cascode transistors Q2, the last transistor Q2 being connected between network 10 and cascode transistors Q1 and Q1'. The bases of transistors Q2 are biased by a same voltage Vb2, the collectors are connected to the respective switches K, and the emitters are connected to the corresponding resistors of network 10. The emitter surface areas of transistors Q2 are preferably chosen to be proportional to the currents flowing in these transistors.
With such a converter, each of outputs Io and Io* can take 2.sup.n discrete values, corresponding to the possible combinations of the n bits of datum D. In the example, n=4 and the amplitude of the steps is I/16. Outputs Io and Io* vary in inverse directions with respect to each other.
In some applications, it is desired to generate an analog bipolar signal, that is, a signal which varies between a positive and a negative value, based on digital datum D. This is, for example, the case for a circuit the offset voltage of an amplifier.
By means of a converter of the type of FIG. 1, a bipolar current can be generated. Such a current is obtained by forming the difference Io-Io* of the complementary output currents of the converter.
As shown as an example in FIG. 1, current Io-Io* can be obtained by means of a current mirror 14, the input of which receives current Io. The complementary current Io* is taken from the output of current mirror 14 and the residual current on this output forms the desired current Io-Io*.
Current mirror 14 includes, for example, two PNP transistors Q3 and Q4, the emitters of which are connected to high supply potential Vcc, and the bases of which are interconnected. The collector of transistor Q3 is connected to the base of transistors Q3 and Q4 and receives current Io. The collector of transistor Q4 receives current Io* and supplies current Io-Io*.
FIG. 2 illustrates the variation of signal Io-Io* according to the successive values of datum D. In the example of FIG. 1, datum D varies from 0 to 15. Current Io-Io* varies from -15I/16 to +15I/16 by steps of 2I/16. For example, when datum D is equal to 6 (decimal) or 0110 (binary), the switches K associated with currents I/2 and I/16 are positioned towards output Io*, while the remaining switches K are positioned towards output Io. Thus, current Io* is I/2+I/16=9I/16, while current Io is I/4+I/8=6I/16, whereby current Io-Io* is equal to -3I/16.
There appears to be no value of D for which current Io-Io* is zero. This is a disadvantage in some applications. For example, if such a converter is used to perform an offset setting, a zero offset cannot be obtained.

Digital-to-analog converter with complementary outputs


A system and method for performing videophone operations over a television. The system includes a television system, a transceiver and a personal computer that is coupled to a communications network and the transceiver. The television system includes a camera, a microphone, a wireless receiver for wirelessly receiving audio and video signals, a signal processor for processing the received audio and video signals for presentation on a television. The transceiver includes a receiver for wirelessly receiving audio and video signals from the television system, and a transmitter for wirelessly sending audio and video signals to the television system. The personal computer includes a memory and a processor for executing program instructions stored in memory for receiving audio and video data over the communications network, for receiving audio and video data from the personal computer transceiver, and for sending the audio and video data received from the personal computer transceiver to a recipient system over the communications network.

This invention relates to the art of videophones, and more particularly, a method and system for an improved videophone user interface.
The concept of integrating video communication with audio communication traditionally provided by the telephone is old. Back in the 1960s a xe2x80x9cpicture phonexe2x80x9d by which both audio and video were bidirectionally communicated between local and remote stations was introduced. These early picture phones added a television camera, a television transmitter and receiver, and a television monitor to the existing telephone assembly. In order to transceive (that is, both transmit and receive) audio and video, a dedicated high-capacity telephone line having a bandwidth adequate for bidirectional communication between the local and remote stations was required. In fact, a dedicated telephone line not generally available to the public, known as a T-3, was used. Hence, this picture phone was futuristic and considered cost prohibitive for widespread commercial deployment. Some time later, audio and video communication between local and remote stations appeared in the form of xe2x80x9cvideo teleconferencing.xe2x80x9d Video teleconferencing systems typically require dedicated local and remote rooms. Generally, these video teleconferencing systems have evolved to comprise a video camera connected to a video processor which digitizes the video data, in turn connected to a communication controller for transmitting video over a high-capacity data communications link (a high-capacity digital telephone line, such as a T-1) leased from a common carrier. The video portion of the video teleconferencing system also comprises one or more television monitors connected to the video processor for displaying video. Recently, data compression techniques have been employed to render video transmission more efficient. For optimum audio quality and apparent synchronization between audio and video, audio is provided over another leased telephone line. Audio can be communicated over a standard telephone line, but audio quality is compromised (e.g., cross-talk, etc.). Also, synchronization between audio and video suffers not only because audio and video are being transceived by two different subsystems, but also due to propagation delay. Propagation delay is evident in visible loss of synchronization between audio and video, such as lip movement not synchronized with speech, especially if long distances are involved. In any event, audio and video are transceived over different telephone lines. Such video teleconferencing systems are commercially available from PictureTel Corporation of Peabody, Mass., and Compression Labs Inc. of San Jose, Calif., for example, but are priced at tens of thousands of dollars and are therefore affordable generally only by businesses, beyond the reach of the home consumer budget. Consequently, widespread deployment of these video teleconferencing systems has not occurred.
As an alternative to video teleconferencing, Matsushita Electric Ltd. introduced a still-image, black-and-white visual telephone in 1987. This visual telephone integrated a small video camera, video digitizer, communication controller, and cathode ray tube (CRT) display into a housing connected to either the same standard telephone line as the telephone assembly at each of the local and remote stations or to a second standard telephone line if the stations were equipped with two-line service. However, the system could not simultaneously exchange video snapshots between the local and remote stations, so the users at each end were required to coordinate video communication to avoid access conflicts. In any event, not only were audio and video non-simultaneous over the same telephone line, but only still video snapshots could be transceived, whereas true video teleconferencing provides motion video.
In recent years, a few Internet-based videophone systems, such as CU-Seeme, have appeared. These videophone systems require a user to have a camera and a personal computer (PC) coupled to the Internet. In order for the user to make or receive calls over the videophone system, the user must be located in the vicinity of the camera at the PC. Although this appears to be an attractive Internet-based application, it still requires the user to be located at the PC when making or receiving a call. Because most people place their PCs in separate rooms or in less frequently traveled locations in their house, it is inconvenient to make and receive calls, especially if they are not arranged in advance. Also, due to many people""s fears of PCs, these systems are not attractive products to many consumer.
Therefore, there exists a need for making a more user-friendly videophone system. The present invention is directed to overcoming the foregoing and other disadvantages. More specifically, the present invention is directed to providing a system and method, for improving videophone interaction.
A system and method for using a television as a videophone is provided. The present invention allows a user to experience videophone functions on any television in their house.
The system includes a television system, a personal computer transceiver and a personal computer that is coupled to a communications network. The television system includes a camera, a microphone, a wireless receiver for wirelessly receiving audio and video signals, a signal processor for processing the received audio and video signals for presentation on a television. The personal computer transceiver includes a receiver for wirelessly receiving audio and video signals from the television system, and a transmitter for wirelessly sending audio and video signals to the television system. The personal computer, which is coupled to the personal computer transceiver, includes a memory and a processor coupled to the memory and in communication with the communications network and the transceiver. The memory includes stored program instructions that are executed by the processor for receiving audio and video data over the communications network, for receiving audio and video data from the personal computer transceiver, and for sending the audio and video data received from the personal computer transceiver to a recipient system over the communications network.
In accordance with a further aspect of the invention, the camera, the microphone and the transmitter are included in a stand-alone unit.
In accordance with a still further aspect of the invention, the system includes a remote control device for generating control signals. The remote control device includes an input device and a transmitter. The remote control device transmits control signals as UHF or infrared signals.
In accordance with another aspect of the invention, the input device of the remote control includes a microphone for including a voice command in the control signal. The processor component comprises a voice recognition component for processing voice commands included in a control signal.
In accordance with yet another aspect of the invention, the television system includes a second transmitter for wirelessly transmitting the control signal to the television, if it is determined that the control signal is for the television. The second wireless transmitter is an infrared transmitter.
In accordance with still yet another aspect of the invention, the processor component includes a decompression component for decompressing compressed audio and video data received over the communications network and a compression component for compressing the audio and video data received from the television system through the personal computer transceiver before sending over the communications network.
In accordance with still yet another aspect of the invention, the wireless communication between the television system and the transceiver is in the 2.3 and 2.5 GHz range.
In accordance with still yet another aspect of the invention, the audio and video data is streamed in real-time.
As will be readily appreciated from the foregoing summary, the invention provides a system and method for allowing a user to experience videophone functions on any television in their house.


A system and method for verifying a digital signature on a certificate, which may be used in the processing of encoded messages. In one embodiment, when a digital signature is successfully verified in a signature verification operation, the public key used to verify that digital signature is cached. When a subsequent attempt to verify the digital signature is made, the public key to be used to verify the digital signature is compared to the cached key. If the keys match, the digital signature can be successfully verified without requiring that a signature verification operation in which some data is decoded using the public key be performed.

Electronic mail ("e-mail") messages may be encoded using one of a number of known protocols. Some of these protocols, such as Secure Multiple Internet Mail Extensions ("S/MIME") for example, rely on public and private encryption keys to provide confidentiality and integrity, and on a Public Key Infrastructure (PKI) to communicate information that provides authentication and authorization. Data encrypted using a private key of a private key/public key pair can only be decrypted using the corresponding public key of the pair, and vice-versa. The authenticity of public keys used in the encoding of messages is validated using certificates. In particular, if a user of a computing device wishes to encrypt a message before the message is sent to a particular individual, the user will require a certificate for that individual. That certificate will typically comprise the public key of the individual, as well as other identification-related information.
Certificates are digital documents that are typically issued by certification authorities. In order to trust a particular public key, the public key typically needs to be issued by a certification authority that is also trusted, or by an entity associated with the trusted certification authority. The relationship between a trusted certification authority and an issued public key can be represented by a series of related certificates, also referred to as a certificate chain. The certificate chain can be followed to determine the validity of a certificate.
Typically, a certification authority will digitally sign each certificate that it issues, to certify that a specific public key belongs to the purported owner as indicated on the respective certificate. In building certificate chains, the digital signatures on the certificates of the chain often need to be verified. Verification of a digital signature on a certificate is a process that requires the public key of the certification authority that issued the certificate.

System and method for verifying digital signatures on certificates