It is an object of the present invention to control damage of a phosphor caused by an etching solution. Disclosed is a method of manufacturing a phosphor having the steps of: (a) crushing phosphor particles via a crushing treatment process, and (b) surface-treating phosphor particles dispersed in a solvent by adding an etching solution via a surface treatment process, wherein an adding speed of the etching solution is in a range of 1.2×10−16-7.0×10−15 mol/min. per 1 m2 of specific surface area of the phosphor particles.

As a display device employing a novel image display method replacing CRT (Cathode Ray Tube), there have been recently developed a liquid crystal display using a liquid crystal panel (LCD: Liquid Crystal Display), an EL display using a phenomenon of electro luminescence (EL: Electro Luminescence) and a plasma display using a plasma display panel (hereinafter referred to as PDP: Plasma Display Panel).
In the plasma display among those stated above, it is possible to achieve slim lightweight panels, simplification of the structure and large screens, and it is possible to observe a sharp image at an angle in a wide range upward and downward and on all sides, because a visible range, the so-called view angle can cover 160° or more both in the horizontal and vertical directions, when compared with a liquid crystal panel. Further, the plasma display is of an image display system with a fixed pixel by means of a dot matrix printer, and therefore, out of color registration and a distortion of an image area are controlled, and an image with high image quality can be depicted even when it is a large image area.
The PDP used for the plasma display is provided with a large number of discharge cells each being formed by two glass base boards provided with electrodes and by a partition provided between the base boards, and a phosphor layer on which a phosphor is coated is formed inside each discharge cell. The PDP constructed in this way is arranged so that vacuum ultraviolet (hereinafter referred to as VUV: Vacuum Ultraviolet) caused by discharge gas filled in a discharge cell may be generated when impressing voltage between electrodes to discharge the discharge cell selectively, and thereby, a phosphor may be excited to emit visible light.
As a general manufacturing method for the phosphor stated above, there are two ways including a solid phase synthesis wherein compounds containing an element constituting a phosphor matrix and compounds containing an activating element, each being in a prescribed amount are mixed, and then, are baked, and a liquid phase synthesis wherein a phosphor material solution containing an element constituting a phosphor matrix and a phosphor material solution containing an element of activating agents are mixed, and baking is carried out after sediment of precursors of the phosphors thus obtained is subjected to liquid-solid separation.
For realizing images which are more clear and are of higher image quality, PDP is highly miniaturized recently, and a phosphor which is small in size and has high light-emission intensity is required by the highly miniaturized PDP. However, a phosphor particle obtained through a solid phase synthesis is large in size, and has a problem that emission efficiency and light-emission intensity are lowered as its particle size turns out to be smaller.
On the other hand, there has been developed a method to miniaturize phosphor particles by conducting a crushing treatment process after manufacturing a phosphor by and a liquid phase synthesis, and thereby to improve light-emission intensity by receiving VUV efficiently. However, there is also caused a problem that the light-emission intensity is lowered, because a surface layer of the phosphor is damaged by the crushing treatment process, and distribution of particle sizes is broadened.
There is also caused another problem that impurities such as nonreacted substances and by-products adhere to the surface of phosphor particle after baking, to absorb VUV generated by electric discharge, resulting in a decline of light-emission intensity.
With the foregoing as a background, there have been developed a phosphor capable of improving emission efficiency of the phosphor, and a manufacturing method of the phosphor wherein impurities such as nonreacted substances and by-products adhering to the surface layer of damaged phosphor particles and to the surface of the phosphor particle are removed by conducting chemical processing by etching solutions such as nitric acid or hydrochloric acid on the phosphor surface, after the phosphor is synthesized by the liquid phase synthesis (for example, Patent Documents 1, 2 and 3).
(Patent Documents 1) TOKKAI No. 2000-226577
(Patent Documents 2) TOKKAI No. 2001-172622
(Patent Documents 3) TOKKAI No. 2003-292950

Method for manufacturing phosphor, phosphor and plasma display panel


An asymmetric hetero-doped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.

This invention relates in general to lateral power transistors and in particular to a lateral Asymmetric Hetero-doped High-voltage MOSFET (AH2MOS) transistors for integrated circuits and for power semiconductor devices.
The operation and cost of an electronic system is improved by reducing the size of transistors and number of packaged devices that make up the system. Many electronic systems save space by forming devices of different types on the same substrate. For example, systems such as cell phones, personal digital assistants and mother boards of personal computers have used separately packaged parts for performing power supply and logic operation. To save space, manufacturers now try to reduce the size of the components in each package, use common process steps for power and logic devices and fabricate power and logic devices on a common semiconductor substrate.
The LDMOS device is a popular transistor for supplying power to electronic systems. It is characterized by a highly doped source disposed in a well or body region that is established by a double diffused implant. Over the source and well is an insulated gate. Spaced from the well is a drift region that holds a drain. The voltage on the gate controls current that flows laterally from the drain, through the drift region and into the source. The drift region is usually lightly doped, or at least less doped than either the source or drain.
Logic devices usually have very shallow source and drain regions. In contrast, LDMOS and other high voltage devices often have diffusion regions that extend deep by into the substrate. Such differences present obstacles to using common steps to form power on logic devices on the same substrate. As device features shrink laterally to submicron sizes, the LDMOS device must also scale its vertical dimensions. That presents a problem because many LDMOS and other power devices rely upon high temperatures and long duration diffusion times to establish deep diffusions that support high voltages. Such deep diffusion process steps are not compatible with smaller geometry, shallow junction logic devices. When high voltage devices are added a low voltage, shallow junction deep submicron logic process, the low voltage process limit all diffusion steps to lower temperatures and short cycle times. A conventional thermal diffusion for a power device would destroy the junctions in a deep-submicron CMOS process. One solution to this problem makes the LDMOS first, masks the LDMOS devices, and then makes the low voltage devices in accordance with their lower temperature requirements. However, this will limit LDMOS p-body self-align to gate poly. Therefore, LDMOS devices will have very long gate poly lengths and that feature induces large channel resistance and increases device size, despite using advanced process tools.
In order to solve this problem others have proposed forming power devices by using high dose implants that are made at large implant angles instead of conventional, small angle about ion implants and long thermal diffusions. While such high dose and high angle implants may support a long enough p-body channel for device punch-through, those processes add more steps to the manufacturing process and thus increase the cost of parts. In addition, such processes are often limited by their size of photoresist opening area. It is conventional to use photoresist as a mask to self-align a body implant to the gate polysilicion. However, the thickness of the photoresist will cast a shadow over the implant area when the angle of implant is high and the body opening is small. Others have used a P-well or a combined P-body and P-well instead of the conventional P-body only LDMOS. However, that solution increases the dimension because the P-well is not self-aligned to the gate polysilicon.

Asymmetric hetero-doped high-voltage MOSFET (AH


A method for detecting the occurrence of rare events in an executable logic code includes assigning a first probability of a chance of traversal of one or more decision paths, in which each path connects two decision points defined by execution of the logic code. As a result of execution of the logic code, the decision paths traversed are evaluated to determine whether said traversal conforms to a predefined performance function. The performance function defines a goal to be achieved pursuant to the execution of the logic code. A second probability is assigned to the chance of traversal of at least one of said one or more decision paths to increase the likelihood that the one or more decision paths are traversed in a subsequent execution of the logic code in a closer conformity with the predefined performance function.

Exhaustive testing of a commercially written program code that has thousands of lines of codes and multitudes of execution paths is very challenging, particularly when there are a large number of nested loops and conditional branches (i.e., interleavings) in the logic code.
Complex programs are commonly tested by way of non-exhaustive testing methods, such has simulation and verification. Simulation and verification techniques are generally based on a heuristic approach which is efficient in determining most errors in typical programs, but does not guarantee discovery of all errors (i.e., bugs). Simulation-based verification is traditionally used to verify the correctness of a program with respect to a set of input values. Different input values can induce a different execution path for the program under test.
Execution of a program in a certain path is considered to be correct, if the program behaves as required (i.e., produces the expected output) for all possible input values for that path. Ideally, a complete verification will test all execution paths in a program, using all possible input values for each path. Obviously, this approach is very time consuming and expensive, if not impractical.
A more practical testing option focuses on discovering bugs that manifest themselves when the computing system is subjected to a heavy computational load during runtime (i.e., stress-testing). Another practical approach involves creating random interference in an event scheduler which leads to randomized interleavings in execution paths.
The interference is created by injecting noise to the scheduler forcing the scheduler to create uncommon interleavings, which are rare during usual execution. However, a chance of finding a very rare bug or a defective program routine that is only very rarely initiated is small, since the random distribution created by injecting noise cannot be adjusted to a specific pattern.
The most commonly used method to maximize the exhaustiveness of testing is coverage estimation. There is an extensive simulation-based verification research on coverage metrics, which provides a measure for determining the exhaustiveness of a test. Coverage metrics are used in order to monitor progress of the verification process, estimate whether more input sequences are needed, and whether direct simulation towards unexplored areas of the program are required.
In the related art systems, the metrics measure the part of the design that has been activated by the input sequences. For example, code-based coverage metrics measure the number of code lines executed during the simulation. There is a variety of different metrics used in coverage estimation, and they play an important role in the design validation effort. Still, since there is no special effort directed to a possibly erroneous pattern in the code, rare bugs can remain undetected even after testing has reached a high degree of coverage.
Thus, software testing and verification methods and systems are needed that can overcome the aforementioned shortcomings by directing code testing according to performance measures that enhance identification of bugs, especially those of the rare event type.

Using cross-entropy to test executable logic code

International Business Machines Corporation


Distance d1 between the right edges of A1 and B2, and distance d2 between the right edges of A3 and B4 are calculated. If data to be embedded is 1, one or a combination of a process for increasing the size of B2 in the column direction or decreasing the size of B4 in the column and a process for moving the position of B2 toward B3 or moving the position of B4 toward B3 is executed to meet d1>d2. If data to be embedded is 0, one or a combination of a process for decreasing the size of B2 in the column direction or increasing the size of B4 in the column direction, and a process for moving the position of B2 toward B1 or moving the position of B4 toward B5 is executed to meet d1<d2.

As a copyright protection method upon distributing digital data such as image data, audio data, and the like on the Internet, digital watermarking attracts a lot of attention. Digital watermarking is a technique for embedding information so as to be imperceptible to a human being. For example, as a digital watermarking technique for a multi-valued image, various methods that exploit the redundancy of the density values of multi-valued pixels are known.
On the other hand, a binary image such as a document image has small redundancy, and it is difficult to apply the digital watermarking technique to such image. However, some digital watermarking methods that exploit unique features of document images are known. For example, a method of shifting the baseline of a line (e.g., see Japanese Patent No. 3,136,061), a method of manipulating an inter-word space length (e.g., see patent U.S. Pat. No. 6,086,706 and Japanese Patent Laid-Open No. 9-186603 (U.S. Pat. No. 5,861,619)), a method of manipulating an inter-character space length (e.g., see "Electronic document data hiding technique using inter-character space", The 1998 IEEE Asia-Pacific Conf. On Circuits and Systems, 1998, pp. 419-422), a method of rotating a character to change its inclination (e.g., see Yasuhiro Nakamura & Kineo Matsui, "Digital Watermarking onto Japanese Documents by Seal Image", IPSJ Journal Vol. 38, No. 11, November 1997), and the like are known.
However, since a document image has small redundancy, and the conventional methods proposed so far embed information by changing two variables, i.e., the baseline of a line, inter-word space, or rotation of a character, the changed points stand out (i.e., image quality deteriorates considerably). Thus, it is possible that third party may detect embedding of information in a document image.

Digital watermark embedding method, apparatus, digital watermark extraction method and apparatus


The invention provides a combination treatment for ischemia conditions in or otherwise affecting the CNS, such as stroke. The treatment involves administration of a PSD-95 inhibitor and performing reperfusion therapy (e.g., by administration of tPA). Administering a PSD-95 inhibitor in combination with reperfusion therapy increases the efficacy of the reperfusion therapy and/or slows the decline in efficacy of reperfusion therapy with time after onset of ischemia thus extending the window in which reperfusion therapy can be administered.

Ischemic stroke is a common cause of death and serious disability and is usually caused by a blockage in a blood vessel leading to or within the intracranial cavity and/or brain. Few effective treatments are available. One treatment consists of removing the blockage within the blood vessel in question. Other treatments consist of altering perfusion pressures within the brain by increasing blood pressure to the brain. Blockage of blood vessels can be removed using a range of mechanical devices, or using "clot busting agents" which are delivered intravenously or intra-arterially. Among such clot busting agents is Tissue plasminogen factor (tPA), a thrombolytic agent that is administered to some stroke subjects to dissolve emboli causing the ischemia and thus restore blood flow to the brain, and recombinant tPA's such as Alteplase, reteplase and tenecteplase. Other thrombolytic drugs that break down clots include streptokinase, urokinase and desmotaplase. Among mechanical reperfusion devices, there are intra-arterial catheters, balloons, stents, and various clot retrieval devices, such as the Penumbra System Reperfusion Cather. Among treatments that alter perfusion pressures in the brain are devices that increase the arterial pressure in the brain, such as balloons that can be inflated in the extra-cerebral arteries such as the aorta thereby diverting blood flow from other body areas and increasing brain arterial perfusion, such as the CoAxia NeuroFlo™ catheter device. Collectively, these strategies can be considered as medical and mechanical agents that enhance brain perfusion on or after the onset of cerebral ischemia (hereafter collectively "reperfusion therapies").
Although tPA and other reperfusion therapies administered soon after onset of ischemia are effective in reducing death or disability from ischemic stroke, less than about 3% of subjects presenting with stroke are treated with tPA or other reperfusion therapies. The low usage of tPA and other reperfusion therapies is due in part to the risk of death if administered to a patient who is having or who is at an elevated risk for sustaining a brain hemorrhage. Stroke can be the result of ischemia or hemorrhage. Too often, the time required to bring a subject to a hospital, reach an initial diagnosis and perform a brain scan to distinguish between ischemic and hemorrhagic stroke would place a subject outside the window in which tPA or other reperfusion therapies can be effective. Thus, many ischemic stroke subjects, who could benefit from tPA or other reperfusion therapies, do not receive such treatment.
A different form of treatment for stroke and related conditions is now in clinical trials (see WO 2010144721 and Aarts et al., Science 298, 846-850 (2002)). This treatment uses Tat-NR2B9c (NA-1), an agent that inhibits PSD-95, thus disrupting binding to N-methyl-D-aspartate receptors (NMDARs) and neuronal nitric oxide synthases (nNOS) and reducing excitoxicity induced by cerebral ischemia. Treatment reduces infarction size and functional deficits.

This patent is subject to a terminal disclaimer.


An amino-acid containing composition for inhibiting accumulation of fat, containing leucine in an amount of 33 to 67% by weight and threonine in an amount of 33 to 67% by weight, in terms of free amino acids thereof, based on whole amino acids.

Excessive accumulation of fat induces metabolic disorders. For example, when the fat is accumulated in the liver, muscles and blood to an excessive degree, fatty liver and insulin resistance will be induced. In addition, excessive fat accumulation in the fat cells will result in obesity. An increase in the number of obese people has constituted a serious social problem throughout the world. The accumulation of fat will thus cause various problems as mentioned above, so that it becomes the key to solving the problems to inhibit fat from being accumulated.
For preventing the accumulation of fat, to restrict the volume and kind of diet and to do exercise are found to be effective. However, the restriction of diet and the physical exercise need strong wills and efforts, so that those methods are not always practical for preventing the accumulation of fat. Accordingly, there has been an increasing demand for a method for preventing the accumulation of fat conveniently and effectively without any special exercise and restricted diet. Intake of supplements is now under consideration as one of the means for preventing the accumulation of fat. However, according to the reports about the currently used supplements, some have insufficient efficacy, and others have the potential for impairing the health, for example, impairing the liver function by the administration.
Amino acids are constituents of protein. The amino acids have been found to be highly safe from the long past experience of eating habits. In addition, it has become clear that the amino acids have a variety of physiological actions, in particular, an inhibitory effect on the fat accumulation. There are some reports regarding the mixtures of amino acids. For example, Japanese Patent Unexamined Publication (JP Kokai) Hei 6-24977 discloses that a mixture of thirteen kinds of amino acids can lower the body weight and the body fat; JP Kokai Hei 4-346770 discloses a mixture of eight kinds of essential amino acids can reduce the body fat; and JP Kokai Hei 9-157163 discloses an amino acid composition comprising nine kinds of essential amino acids, with arginine being contained in major proportions, can control obesity. The compositions of those amino-acid mixtures are shown in Table 2. There is also a report about the effect of an amino acid when used by itself, i.e., the promoting effect of leucine on the weight loss when leucine is taken during a period of restricted diet (Nutrition, 2006 May; 22 (5): 520-7). However, the methods disclosed in those documents require exercises or restriction of the food intake. Moreover, the above-mentioned methods are not compared and analyzed in the same manner, so that it has not been identified which composition has an action of sufficiently inhibiting the accumulation of fat. A more effective composition is desired.

Amino-acid containing composition for inhibiting accumulation of fat


A die casting machine 100 to fill by injecting molten metal into a die cavity 24 includes a variable displacement pump 16 driven by a servo motor 17 for discharging hydraulic fluid from a hydraulic fluid tank 40, an injection cylinder 11 with a slidable piston 12 assembled therein, hydraulic fluid pipes a and c for supplying hydraulic fluid discharged by the variable displacement pump 16 to the injection cylinder 11, hydraulic fluid pipes d, e1, g and a logic valve 14 connected to hydraulic fluid pipe c for supplying hydraulic fluid ejected from the injection cylinder 11 to hydraulic fluid pipe c with the piston 12 slid by the hydraulic fluid supplied to the injection cylinder 11.

1. Field of the Invention
This invention relates to a die casting machine to fabricate high-strength products by filling molten metal into a die cavity by injection and applying a predetermined pressure to the molten metal.
2. Description of the Related Art
A die casting machine capable of high-speed injection without using an accumulator is disclosed in Japanese Unexamined Patent Publication No. 2004-174502.
In the die casting machine disclosed in Japanese Unexamined Patent Publication No. 2004-174502, molten metal is filled by injection into a die cavity using a single two-way hydraulic pump in such a manner that the rotational speed of the drive motor of the two-way hydraulic pump is controlled at the time of filling the molten metal by injection and the torque of the drive motor of the two-way hydraulic pump is controlled to maintain pressure.


Disclosed is a method and apparatus for controlling automatic lifting and lowering type platform that can correct the inclination of a mobile power generator and that can always maintain the level while carrying out automatic lifting and lowering of the generator. The apparatus includes vertical outer cases which are extended or withdrawn in the horizontal directions from or into both sides at both ends of the chassis α; vertical inner cases which are inserted into the vertical outer cases and extended or withdrawn in the vertical directions; and an allotter which allots output to jacks so that inclination detected by an angle sensor can always be corrected.

1. Field of the Invention
The present invention relates to an automatic lifting and lowering controlling method that serves in installation of a heavy machine, such as a mobile power generating apparatus, or the like, on or removal thereof from a desired site, and an automatic lift/lower type platform controlling apparatus which is to be directly used for implementing the method.
2. Description of the Related Art
Conventionally, installation of a mobile power generating apparatus, or the like, on or removal thereof from a desired site has been performed by using a mobile large-sized crane, or the like, and the lashing crew therearound handling slings and other materials for load lashing.
However, loading and unloading of a mobile power generating apparatus, or the like, with a crane and by lashing work has presented a number of problems, such as that the operator of a crane is limited to the qualified personnel; that, if the crane used is large-sized, a wide working area is required to be secured, and that there is a hazard to the crew by a possible drop of load during operation of the crane, and the possibility of the load being damaged by dropping.
By the way, for the mobile power generating apparatus, it has been a general practice that the power generator is accommodated in a bonnet type (box type) container for reinforcement, and protection against outdoor weather, and minimization of the noise from the power generator; that the loading and unloading is performed by a crane to suspend the platform (also called chassis, bed, or base), on which the container is loaded, at the four side points thereof; and that, as the frame structural material on both sides of the platform, a channel steel material is used to provide a necessary strength.
In order to solve the above-mentioned problems, an automatic lifting/lowering platform apparatus A′, as shown in FIG. 10, which eliminates the need for lashing work, has been developed, allowing reduction of size of the mobile power generating apparatus; loading and unloading by a small number of crew members who are not limited to the qualified personnel, and thus reduction in the necessary numbers of working crew members; elimination of the hazard to the crew by a possible drop of load during operation of the crane, and the possibility of the load being damaged by dropping; and reduction of the working area required for transfer to or from the installation site.
Utilization of the automatic lifting/lowering platform apparatus A′ having the above-mentioned advantages has improved the safety and ease of the loading and unloading work, and reduced the cost.
Further, in the patent literature 1 as given below, the method for automatic lifting/lowering of a mobile power generating apparatus by utilizing the extending and contracting ability of the jacks in the automatic lifting/lowering platform apparatus A′, and the operator wirelessly operating a remote control operating apparatus for lifting/lowering the mobile power generating apparatus is disclosed.
Patent literature 1: Japanese Laid-Open Publication No. 2000-134729
However, the automatic lifting/lowering platform apparatus A′ as disclosed in the patent literature 1 has presented such problems as that, due to the difference in distance from the single pressure source to the respective jacks as automatic lifting and lowering means, the pressure loss and the pressure transfer rate vary, resulting in differences in operation timing and operation speed between jacks, and thus the vertical positions of the respective jacks vary, which can cause an inclination to be generated in automatic lifting or automatic lowering of the power generator, and thus a strain or a torsion to be produced, resulting in the joint waterproofing material on the outer plate panel being peeled off, which may lead to rainwater entering the interior and the door becoming impossible to be opened.
In addition, there has been a big problem that, if, as the frame structural material αa′ for the chassis α′ in the automatic lifting/lowering platform apparatus A′, the above-mentioned channel steel material is used, and for further reinforcement, an upper part structural material (a-H frame) and five-face outer plates and a bottom plate as shown in FIG. 8 (a), are provided, those materials may interfere with some component parts of the power generator, with the bottom plate having such a maintenability ill effect as that the oil pan cannot be removed, and in order to avoid these possible issues, the automatic lifting/lowering platform apparatus A′ has to be increased in size, which results in an increase in the weight as opposed to the lightweight which is required of the automatic lifting/lowering platform apparatus for mobile power generating apparatus.
The cause for the above-mentioned problems originate from that, as shown in FIG. 9 (a) and FIG. 9 (b), the form of stress has been changed from that for the four-point suspension by the crane (see FIG. 9 (a)) to that for the support by the four jacks in the outriggers β′ in the platform mechanism part of the automatic lifting/lowering platform apparatus A′ (see FIG. 9 (b)). Further, with the jacks in the automatic lifting/lowering platform apparatus A′, a phenomenon of two-point support on the diagonal line across the points X+ and X−, or Y+ and Y−, is occasionally caused. With the four-point suspension by the crane, the load imposed on one point by the suspension is approx. ¼ of the total weight, and the loading angle with respect to the vertical is equal for all the four. On the other hand, with the support by the four jacks, when the two-point support phenomenon is caused, the load supported by one jack is increased from ¼ to ½ of the total weight, i.e., doubled. In addition, the lifted sides of the structure hang down, and the direction of stress is alternately inverted. The member between Y+ and −X, and that between X+ and Y− are twisted to an extent which depends upon the load they bear. As a result of this torsion, a tension which has not been encountered in the suspension is applied to the top, bottom, and side outer plates. Such tension is transferred to the vibration absorbing rubber mounts and the outer plate panels, and the repetition of application of the tension has also caused the above-mentioned problems.
In addition, the hydraulic circuit open-close shock load occurring in the solenoid directional control valves for the jacks incorporated in the outriggers β′ in the automatic lifting/lowering platform apparatus A′ has further increased the above-mentioned torsion of the chassis α′, although this phenomenon was a transient one. Such hydraulic circuit open-close shock load was heavily generated when, in lowering, the contracting motion of the jack which caused the power generating apparatus to be greatly inclined was stopped.
Either the crane for loading and unloading or the automatic lifting/lowering platform apparatus A′ is driven on hydraulic power, but these differ from each other in the mechanism of occurrence and transfer of a shock caused by a hydraulic open-close valve. With the crane for loading and unloading, the shock is alleviated by the deflection of the long beams and the extension and contraction of the wires, but with the automatic lifting/lowering platform apparatus A′, there are no portions which can alleviate the shock, and thus the chassis is directly subjected to deflection and torsion, which can lead to occurrence of problems.
The inclination of the entire power generating apparatus can be easily verified at a location distant to some degree therefrom, however, the system with which the solenoid directional control valves are directly operated near the machine, the angle of the inclination cannot easily be recognized (the tardiness of angle recognition), which, in some cases, has led to an unnecessary inclination, and increased the shock load. The tardiness of angle recognition involved in the operation near the machine might cause overturning of the machine, resulting in the operator himself being injured by the overturned machine, thus with this system, the operator must have had to repeat a slight adjustment, and "a patrol around and inspection of the entire machine".

Method and apparatus for controlling automatic lifting and lowering type platform


A power foldback circuit to automatically control the power of an audio amplifier by using the volume inputs to a pre-amp source which drives the audio amplifier. In an embodiment, a Universal Serial Bus (USB) on a personal computer is used to drive the audio speakers. In this circuit an audio digital to analog converter (DAC) with a USB interface receives a digitally encoded audio signal from a personal computer (PC). The USB DAC outputs an analog audio signal to a audio amplifier circuit. A supervisory circuit monitors the power used by the audio amplifier and through a volume control circuit lowers the volume control into the USB DAC to prevent the entire circuit from drawing more than the allowed power supplied by the USB connection to the PC.

In some audio applications it is sometimes necessary to limit the amount of power used by an audio amplifier due to power constraints. In a particular application, an audio amplifier that drives the speakers for a computer sound system has a limited amount of power available to the amplifier. In this system, an audio power amplifier is powered directly from a personal computer's USB (Universal Serial Bus) port. This is desirable to reduce the audio speakers wiring to a single connection to the speakers from the USB port. The USB interface connection includes power as well as a data bus. Power limitations of the USB port are defined by an accepted bus interface standard. The power is typically limited to ½ amp at 5 volts.
Overdriving the audio without limiting the current drawn on the USB port could damage the PC's USB drive circuits or cause them to current limit and shut down. Some prior art circuits would cut the current to the audio amplifier if the current draw rose to high. This would case an undesirable pause or stop in the audio output.

Automatic power foldback for audio applications


A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.

1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a technique advantageously applied to a semiconductor device in which two semiconductor chips are stacked on one another and are encapsulated with a single resin encapsulant.
2. Description of the Related Art
For the purpose of increasing the capacity of a storage circuit system, stacked semiconductor devices have been proposed in which two semiconductor chips forming a memory circuit system are stacked on one another and are encapsulated with a single resin encapsulant. For example, Japanese unexamined patent publication No. H7(1995)-58281 discloses a stacked semiconductor device having a LOC (lead on chip) structure.
A stacked semiconductor device having a LOC structure is comprised of a first semiconductor chip and a second semiconductor chip having a plurality of electrode pads formed on a circuit forming surface thereof which is the top surface, i.e., one of principal surfaces opposite to each other, a plurality of first leads bonded and secured to the circuit forming surface of the first semiconductor chip with an insulating film interposed therebetween and electrically connected to the electrode pads on the circuit forming surface through conductive wires, a plurality of second leads bonded and secured to the circuit forming surface of the second semiconductor chip with an insulating film interposed therebetween and electrically connected to the electrode pads on the circuit forming surface through conductive wires and a resin encapsulant for encapsulating the first semiconductor chip, second semiconductor chip, inner portions of the first leads, inner portions of the second leads, the wires and the like. The first and second semiconductor chips are stacked with their circuit forming surfaces facing each other. The first and second leads are bonded with respective connecting portions overlapping each other.
The inventors have encountered the following problems in the course of the development of stacked semiconductor device.
The conventional LOC structure as described above results in an increase in manufacturing cost because the manufacture involves the use of two lead frames when this structure is adopted.
The above-described conventional technique necessitates two lead frames because two semiconductor chips are to be stacked.
Further, since two semiconductor chips are stacked, the electrode pads of the two semiconductor chips can not be provided in four directions on the semiconductor chips with a single lead frame.
It is therefore an object of the invention to provide a technique which makes it possible to reduce the thickness of a semiconductor device by stacking two semiconductor chips and encapsulating the two semiconductor chips with a single resin encapsulant.
It is another object of the invention to provide a technique that accommodates a structure of a semiconductor device having two semiconductor chips stacked and encapsulated with a single resin encapsulant in which a single lead frame serves electrode pads provided along four sides of the stack formed by the two semiconductor chips.
It is still another object of the invention to provide a technique to make it possible to provide a multi-chip package having a reduced mounting without changing the storage capacity.
It is still another object of the invention to provide a technique that makes it possible to prevent cracks in a structure of a semiconductor device having two semiconductor chips stacked and encapsulated with a single resin encapsulant.
The above and other objects and novel features of the invention will be clearly understood from the description of this specification and the accompanying drawings.
Typical aspects of the invention disclosed in this specification can be briefly summarized as follows.
(1) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the second semiconductor chip with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semiconductor chip and the circuit forming surface of the second semiconductor chip facing each other and wherein
the inner portion of the support lead is bonded and secured to the circuit forming surface of the second semiconductor chip.
(2) There is provided a semiconductor device according to the first aspect, wherein a part of the inner portions of the leads is provided on the circuit forming surface of the second semiconductor chip.
(3) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the second semiconductor chip with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semiconductor chip and the back surface of the second semiconductor chip facing each other and wherein
the inner portion of the support lead is bonded and secured to the back surface of the second semiconductor chip.
(4) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the first and second semiconductor chips with the inner portion; and a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semiconductor chip and the circuit forming surface of the second semiconductor chip facing each other and wherein
the inner portion of the support lead is bonded and secured to the circuit forming surfaces of the first and second semiconductor chips.
(5) There is provided a semiconductor device according to the fourth aspect, wherein a part of the inner portions of the leads is provided on the circuit forming surface of the second semiconductor chip.
(6) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the first and second semiconductor chips with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semiconductor chip and the back surface of the second semiconductor chip facing each other and wherein
the inner portion of the support lead is bonded and secured to the circuit forming surface of the first semiconductor chip and the back surface of the second semiconductor chip.
(7) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the first and second semiconductor chips with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is provided on the second semiconductor chip with the resin of the resin encapsulant interposed between the back surface of the first semiconductor chip and the circuit forming surface of the second semiconductor chip and wherein
the inner portion of the support lead is bonded and secured to the circuit forming surfaces of the first and second semiconductor chips.
(8) There is provided a semiconductor device according to the seventh aspect, wherein a part of the inner portions of the leads is provided on the circuit forming surface of the second semiconductor chip.
(9) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the first and second semiconductor chips with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is provided on the second semiconductor chip with the resin of the resin encapsulant interposed between the back surface of the first semiconductor chip and the back surface of the second semiconductor chip and wherein
the inner portion of the support lead is bonded and secured to the circuit forming surface of the first semiconductor chip and the back surface of the second semiconductor chip.
(10) There is provided a semiconductor device according any of the first through ninth aspects, wherein the support lead is configured to serve as both a power supply lead and a reference potential lead.
(11) There is provided a method of manufacturing a semiconductor device comprising the steps of:
providing a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and providing a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
forming a semiconductor chip stack by bonding and securing the back surface of the first semiconductor chip to the circuit forming surface of the second semiconductor chip;
bonding and securing an inner portion of a support lead to the circuit forming surface of the second semiconductor chip;
electrically connecting the electrode pads of the first and second semiconductor chips to inner portions of a plurality of leads respectively through conductive wires; and
encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires.
(12) There is provided a method of manufacturing a semiconductor device according to the eleventh aspect, comprising the step of providing a part of the inner portions of the leads on the circuit forming surface of the second semiconductor chip.
(13) There is provided a method of manufacturing a semiconductor device comprising the steps of:
providing a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and providing a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
forming a semiconductor chip stack by bonding and securing the back surface of the first semiconductor chip to the back surface of the second semiconductor chip;
bonding and securing an inner portion of a support lead to the back surface of the second semiconductor chip;
electrically connecting the electrode pads of the first and second semiconductor chips to inner portions of a plurality of leads respectively through conductive wires; and
encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires.
(14) There is provided a method of manufacturing a semiconductor device comprising the steps of:
providing a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and providing a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
disposing the back surface of the first semiconductor chip and the circuit forming surface of the second semiconductor chip in a face-to-face relationship with each other and securing and supporting them at an inner portion of a support lead to form a semiconductor chip stack with a gap between them;
electrically connecting the electrode pads of the first and second semiconductor chips to inner portions of a plurality of leads respectively through conductive wires; and
encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires.
(15) There is provided a method of manufacturing a semiconductor device according to the fourteenth aspect, comprising the step of providing a part of the inner portions of the leads on the circuit forming surface of the second semiconductor chip.
(16) There is provided a method of manufacturing a semiconductor device comprising the steps of:
providing a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and providing a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
disposing the back surface of the first semiconductor chip and back surface of the second semiconductor chip in a face-to-face relationship with each other and securing and supporting them at an inner portion of a support lead to form a semiconductor chip stack with a gap between them;
electrically connecting the electrode pads of the first and second semiconductor chips to inner portions of a plurality of leads respectively through conductive wires; and
encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires.

Semiconductor device and a method of manufacturing the same and an electronic device


A lithium secondary battery of the present invention includes: a positive electrode; a negative electrode; a nonaqueous electrolytic solution; and a separator. The positive active material contains a lithium-containing composite oxide containing nickel. A molar ratio of a total nickel amount with respect to a total lithium amount contained in the entire positive active material is 0.05 to 1.0. The nonaqueous electrolytic solution contains 0.5 to 5.0 mass % of a phosphonoacetate-based compound represented by the following General Formula (1). In the Formula, R1, R2, and R3 independently represent an alkyl group, an alkenyl group, or an alkynyl group having 1 to 12 carbon atoms, which may be substituted by a halogen atom, and “n” represents an integer of 0 to 6.

In recent years, along with the development of portable electronic equipment such as a mobile phone and a notebook personal computer, and the commercialization of electric automobiles, there is a demand for further enhancement of performance and stability of a secondary battery and a capacitor to be used as power sources for the above-mentioned equipment and electric automobiles. In particular, a lithium secondary battery is drawing attention as a battery having high energy density and is being improved from various viewpoints as a preferred power source for the above-mentioned equipment and electric automobiles.
In the above-mentioned lithium secondary battery, various improvements are still being made for the purpose of enhancing battery characteristics. For example, Patent Document 1 discloses a lithium secondary battery in which the gas generation amount is reduced and the storage characteristics at high temperature are rendered excellent by causing a nonaqueous electrolytic solution to contain a particular compound based on a phosphate ester.
Further, Patent Document 2 discloses a lithium secondary battery in which the swelling characteristics at high temperature are ameliorated by adding a phosphonate compound containing an unsaturated hydrocarbon radical to an electrolytic solution.
Further, lithium cobaltate (LiCoO2) is easy to produce and handle, and hence is used frequently as a preferred positive active material for a lithium secondary battery. However, LiCoO2 is produced using cobalt (Co) that is a rare metal as a raw material, and therefore, it is expected that resource shortage will become a serious problem. Further, the price of cobalt is high, and the price fluctuation thereof is large. Therefore, it is desired to develop a positive electrode material that can be supplied stably at low cost.
Under the above-mentioned circumstance, a positive active material replacing LiCoO2 is being developed, and for example, Patent Document 3 discloses a positive active material containing nickel (Ni), manganese (Mn), cobalt (Co), and another substitution element M, in which a containing ratio of each element is defined, and an atomic ratio "a" of the substituent element M with respect to Mn, Ni, and Co on the surface of a positive active material particle is set to be larger than an average atomic ratio of the substituent element M with respect to Mn, Ni, and Co in the entire positive active material particle. The above-mentioned positive active material has a capacity higher than that of LiCoO2, and in particular, the positive active material containing Ni has a high capacity in the vicinity of 3 to 4.2 V on the basis of a lithium metal. Thus, the positive active material containing Ni is a material capable of further increasing a battery capacity.


A light emitting device has a base comprising at least one pair of leads having a silver-containing layer on their surfaces and being secured by a resin molded body, a light emitting element mounted on said leads, a protective film made of an inorganic material that covers the upper surface of said base, and a sealing resin disposed on the base surface via said protective film. The sealing resin has a first resin that covers said light emitting element, and a second resin having a higher hardness than said first resin that covers the boundaries between said resin molded body and said leads.

1. Field of the Invention
The present disclosure relates to light emitting devices having a silver-containing layer on the surface thereof and lighting equipment using the same.
2. Background Art
Light emitting devices using semiconductor light emitting elements (hereinafter, also simply referred to as "light emitting elements") employ numerous types of resin packages that use leads as electrodes in which silver (Ag) having high reflectivity for the light emitted from light emitting elements is disposed at the outermost surfaces of the leads. However, Ag is highly reactive (sulfurized) in an environment where a corrosive gas, such as a sulfur-containing gas, is present, and thus is susceptible to discoloration and corrosion, reducing the reflectivity and considerably degrading the properties of light emitting devices. Accordingly, attempts have been made to cover the surface of Ag with inorganic materials such as glass. See, for example, Japanese Laid-Open Patent Application Publication No. 2007-324256 and Japanese Laid-Open Patent Application Publication No. 2009-224536

Light emitting device and lighting equipment


An electric heating system comprising at least two electric heating resistors, the heating power of which being adjusted by a control device comprising a plurality of controllers each one of which has one of the electric heating resistor associated with it, wherein the control range of the control means is distributed over the controllers and wherein a different control range is associated to each controller.

The present invention refers to an electric heating system, the heating power of which is adjustable by a control means.
Electric heatings or heating systems are, for example, required for different applications in motor vehicles, for example for heating the air within the vehicle, for pre-heating the cooling water in water-cooled engines, for pre-heating the spark plugs in self-igniting internal combustion engines, for heating the fuel (diesel) etc. Heating systems of that kind usually consist of a heating with at least one heating stage, each comprising at least one heating element (for example provided as a heating resistor) for generating a predetermined heating power, as wellas of a control unit for monitoring the chronological course and for defining the heating power; the heating and the control unit are provided as separate modules (functional units) and are arranged at different positions within the motor vehicle.
It is a disadvantage that on one hand a plurality of connection lines is required between the heating and the control unit (which is connection with space requirements, costs, electromagnetical compatibility problems) and that on the other hand the dissipation power has to be carried off separately.
The control unit can be realized so as to control the different controllers which cause different control responses upon occurrence of a control deviation or control difference; proportional controller, integral controller, differential controller, linear controller or switchable step controllers are for example conmmonly used. In order to reduce the load of the control means, said control means may be composed of a plurality of controllers that are generally formed as switchable step controllers and may be activated or deactived for example by switching operations. The problem that occurs in this case (in particular in step controllers) is the delimitation of the range of action of the different controllers, i.e. the transition between the control ranges of the controllers is not clearly defined; this will lead to interferences of the control or of the control response (occurrence of dead ranges, overlappings, hystereses, undefined conditions etc.) and electromagnetical compatibility interferences, the reduction of which requiring expensive components

System for controlling a plurality of resistive heating elements


A VPN servers request is transmitted from a user device to a central server. A first VPN server is received from the central server at the user device. Responsive to the user device failing to establish a first encrypted tunnel with the first VPN server, a request for another VPN server is transmitted from the user device to the central server. A second VPN server is received from the central server. A second encrypted tunnel is established with the second VPN server. An encrypted communication is obtained by encrypting a communication directed to a network server. The encrypted communication is transmitted from the user device to the VPN second server.

Global Internet users increasingly rely on virtual private network (VPN) services to preserve their privacy and access geo filtered content. Originally developed as a technology to privately send and receive data across public networks, VPNs are now used broadly as a privacy-preserving technology that allows Internet users to obscure their traffic and their personal information, such as their web browsing history, from third parties including Internet service providers (ISPs), Spywares, and other third parties. A VPN service provider offers a secure private networking environment within a shared public insecure infrastructure through encapsulation and encryption of all traffic from the VPN application within the VPN user's device to the remote access VPN server.
Most VPN providers rely on a tunneling protocol to create a private network to add a layer of security that protects each packet on its journey over the Internet. Tunneling is the process of placing the entire packet within another packet before it is transported over the internet. The outer packet protects the contents from public view and ensures that the packet moves within a virtual tunnel. This virtual tunnel is a point-to-point tunnel established between a user device and a VPN server. This layering of packets is called encapsulation. Computers or other network devices at both ends of the tunnel, called tunnel interfaces, can encapsulate outgoing packets and reopen incoming packets. Additionally, in a VPN network, devices at each end of the tunnel encrypt the data entering the tunnel and decrypt them at the destination.
Encryption is the process of changing the data from a transparently readable format to an encoded, unreadable format with the help of an encryption algorithm. This encoded format can only be decoded with the right decryption key. VPN encryption, as mentioned before, renders the user's online traffic indecipherable to any third-party monitoring them. At the fundamental level, when a user launches a VPN application and connects to a VPN server, at least some of the subsequent user's requests are encrypted before they are sent to the VPN server. These requests are decrypted by the VPN server and forwarded to the intended target on the Internet. The VPN server may receive reply data from the intended target. The VPN server encrypts the reply data and transmits the encrypted reply data to the user device. Once the encrypted reply data reaches the user device, the data is decrypted by the VPN application so that the user can, for example, view them.
VPNs generally use different types of encryption algorithms to encrypt and decrypt user's online traffic. Symmetric encryption is one of the algorithms that rely on the identical public key and private key. This form of encryption is considered relatively fast, and one example of symmetric encryption is the AES encryption cipher. Another type of encryption algorithm is the Asymmetric encryption, which may also be known as public key cryptography. This algorithm uses different keys for the encryption and decryption processes. An example of asymmetric encryption is the RSA (Rivest-Shamir-Adleman) protocol.
VPN encryption keys may be randomly generated strings of bits that are used to encrypt and decrypt data. Each encryption key may be generated in such a way that it is unique. The length (and strength) of an encryption key may be expressed in bits. Usually, the longer the key, the stronger the key encryption. Two types of encryption keys are being used: private keys and public keys. They are mathematically related, since any kind of information that is encrypted with a public key can only be decrypted with a private key associated with it. The public key is usually available through a public directory, while the private key remains confidential and is only accessible by the key owner.
When a user accesses a VPN client application on a user device associated with the user, the user may first be taken through a user authentication procedure. User authentication is the verification of credentials required for confirmation of a user's authenticity. In other words, authentication is used to prove a user is allowed access, and so provides a form of access control. A typical user authentication consists of verifying a simple ID and password combination. However, more authentication factors may be added to improve the security of the VPN user. The primary authentication factors are knowledge, possession and inherence. Knowledge factors include all things a user must know in order to log in to the VPN client application, e.g., usernames or ID, passwords and PINs. In the same way, possession factors consist of anything a user must have in their possession, such as one-time password (OTP) tokens. Finally, the inherence factors include any inherent trait the user has that are confirmed for accessing the VPN client application such as fingerprint scans, retina scans, iris scans, etc.
A typical VPN service consists of a network of VPN servers, typically spread across several geographical locations. A VPN server may be a physical or a virtual server that is configured to host and deliver VPN services to users (i.e., to user devices). A VPN server may be implemented as a combination of hardware and software and may have one or more logical and physical communication ports for receiving network traffic. In a typical scenario, an end user application (e.g., an internet web browser) may execute on a user device and may communicate with (e.g., transmit network traffic to and receive network traffic from) another application (e.g., a web server) executing at a network node that may be available on the internet. The VPN client executing on the user and a VPN server may facilitate and secure the exchanged network traffic between the user device and the network node. As such, an encrypted tunnel is said to be established between the user device and the VPN server.
The VPN client application may connect with the VPN server, encrypt network traffic that is to be delivered to the other application executing at the network node, and send the encrypted network traffic from the user device to the VPN server. After receiving the encrypted traffic, the VPN server decrypts the encrypted network traffic and forwards the network traffic to the network node. The network node may transmit back reply data, such as in response to the content of the network traffic. In response to receiving the reply data from the network node, the VPN server encrypts the reply data and transmits the encrypted reply data to the user device. The VPN client application of the user device decrypts the encrypted reply data and hands the reply data to the user application. In an example, the decrypted reply data can be presented to the user (such as in the form of an internet browser page).
To reiterate, the VPN client application may be a software-based and/or a hardware-based technology that establishes a secure connection between a user device and a VPN server. Some VPN client applications work in the background of the user device automatically, while others have front-end interfaces that allow users to interact with and configure them. VPN client applications may be installed on computers (e.g., user devices). However, some organizations provide a purpose-built VPN client application that is a hardware device pre-installed with VPN software. Generally, VPN client applications operate on more than one VPN protocol to encrypt and decrypt the data. Some of the commonly used VPN protocols are OpenVPN, SSTP, PPTP, L2TP/IPSec, IKEv2, SoftEther.
Most of the VPN services allow users to select or switch between different servers in the private network according to the user's choice of location or requirements. For instance, if a user wants to connect to a VPN server that is located in the USA, the user can simply choose the location through the graphical user interface and the connection (e.g., an encrypted tunnel) may be established with the USA-based server. The existence of multiple servers in a VPN service network makes it possible for users to choose the locations of VPN servers to connect to. Without this provision of choice, a user device may be assigned (e.g., connected to) a random VPN server without an ability for the user to choose an available VPN server that better satisfies certain parameters. The more VPN servers a VPN service provides, the better it is for the users. This is because the users will have more servers to choose from, and they can access even the remotest websites that are only available in certain countries.
However, most VPN services do not have an inbuilt system or a method to recommend or identify optimal VPN servers for a particular user device from the available VPN servers. Average users often do not have clarity for identifying and selecting the optimum server to serve their purposes. Therefore, users mostly tend to randomly choose a server in a VPN service provider without weighing the servers' various parameters and conditions. Without evaluating the server conditions, the user is left in ambiguity while choosing a random server. One cannot be assured that all servers in a VPN service can be ideal. As such, it is important for the VPN service provider to evaluate and recommend servers to users accessing their services. This ensures reliability, connectivity, and improves user experience significantly.

Identifying virtual private network servers for user devices


A method is described for providing improved seismic data to a driller to indicate position and spatial extent of a drilling target which may be up to several hundreds of feet ahead of a drill bit. In one embodiment, the method includes the steps of: survey design and data modeling, and definition of a drilling target point and a drilling interruption point; drilling down to a depth at which drilling will be interrupted; interruption of drilling; look-ahead borehole seismic survey (VSP); continuation of drilling; data processing and interpretation; coordinate update for optimum target intersection; and steering of drilling by borehole seismic data interpretation.

1. Field of the Invention
This invention relates to a method of conducting the drilling of a borehole such as is used for hydrocarbon exploration and production. The well trajectory is derived from a look-ahead and look-around borehole seismic survey. Such a survey can provide very valuable information in the case of small drilling targets. This method is applicable also to other applications requiring look-ahead and look-around borehole seismic information.
2. Description of the Related Art
Vertical seismic profiling or "VSP" is a well known technique for obtaining geophysical information around a borehole (Hardage B. A., 1983, Vertical Seismic Profiling, Handbook of Geophysical Exploration, Section I, Geophysical Press, London, Amsterdam.). One or more seismic sources are positioned near the borehole at the surface and a sonde having one or more seismic detectors is lowered into the borehole on a wireline cable. The sonde is then positioned at a number of depths in the well while the sources are activated and seismic readings are taken. Suitable tools for performing such services are Schlumberger's Array Seismic Imager (ASI) or Combinable Seismic Imager (CSI) tools.
Typically VSP surveys are conducted when drilling has reached target depth or at a convenient pause in drilling operations such as an intermediate casing point, and serve to provide a diagnosis of the formations through which the borehole has been drilled.
Pinnacle reefs are high potential gas-bearing reservoirs that can be lucrative drilling targets for the oil and gas industry. They usually have a limited circular size with a diameter that can be as small as 600' to 800'. Their size is very small compared to their distance from the surface that can be greater than 16,000'. Their vertical section can be as thick as 600' which makes them attractive and preferred drilling targets in a Reef Trend. An object of this invention is to provide a technique which assists in steering drilling into a target such as a reef structure.
3D seismic represents a valuable tool to locate prospective reef development. Reef tops generally mark the interface from shale to limestone that creates a high-reflectivity event in the seismic wavefield. Surface and borehole seismic methods can detect and image those reefs that show different patterns of structure and amplitude in seismic data. These two methods have fundamental differences:
First, surface seismic images generally have less resolution than the ones obtained by borehole seismic. VSP sensors are deployed in a borehole that is characterised by a low ambient noise level for better signal recording. Also, seismic waves of a VSP survey generally have to propagate shorter distances and are less attenuated than surface seismic waves.
Second, the precision of accurately mapping the location of a reef structure in space depends on the quality of seismic stacking and migration velocity analysis. For surface seismic data, velocity analysis is based on data acquired at the surface that usually have greater errors with increasing depth. Velocity errors result in a deteriorated surface seismic image. Thus the actual position of a small pinnacle reef can be skewed both vertically and laterally in such an image. Borehole seismic, in turn, calibrates seismic velocity since is measures velocities in a well.
Third, borehole seismic has contributed successfully to the evaluation of thickness and spatial extent of pinnacle reefs by running offset Vertical Seismic Profiles (VSPs). In conventional surveys, geophones are deployed down to the drilling target depth. However, the methods used to date are mainly of diagnostic character. These aim to calibrate images obtained from surface seismic data, to provide depth information of the top and the base of a reef, and to map structural detail within a reef.
The present invention aims to overcome some or all of these problems and limitations in the existing techniques.

Method of conducting drilling operations using vertical seismic profiles


In some embodiments, apparatus useful for providing tubing into an underwater well includes at least one surface injector and at least one underwater injector. The surface injector is adapted and arranged to control the movement of the tubing into and out of the underground well below the sea floor during normal operations. At least one surface injector and/or underwater injector is arranged and adapted to maintain the tubing in substantial tension between the surface and underwater injectors.

In various phases of hydrocarbon recovery operations, a tubing injector is commonly used to insert a tubing into the well for performing various downhole services. Conducting tubing intervention in underwater or subsea wells typically warrants the use of a tubing injector at the subsea wellhead. The underwater disposition of the injector and the significant distance that may exist to the sea floor pose unique challenges in conducting effective and efficient subsea tubing intervention operations.
Various presently known injector systems and techniques for subsea tubing intervention are believed to have one or more drawbacks. For example, in some known existing systems, the sea-floor injector is utilized as the primary injector for moving the tubing into and out of the well. In such instances, the operation of the sea-floor injector will need to be controlled from the surface. Accordingly, the submerged injector will typically require substantial valve and control components, instrumentation that can be monitored from the surface and significant umbilical support (communication/control lines) from the surface. As such, the submerged injector will likely be heavy and cumbersome, requiring special equipment for deployment and rendering retrieval difficult or impractical. Furthermore, a multitude of components that are subject to malfunction, failure and maintenance will be underwater or located on the injector at the sea floor. Remotely accessing, repairing or replacing these components will be time consuming, expensive and difficult or impossible.
It should be understood that the above-described discussion is provided for illustrative purposes only and is not intended to limit the scope or subject matter of this disclosure or any related patent application or patent. Thus, none of the appended claims or claims of any related patent application or patent should be limited by the above discussion or required to address, include or exclude the above-cited examples, features and/or disadvantages merely because of their mention above.
Accordingly, there exists a need for improved systems, apparatus and methods capable of providing a tubing into an underwater well having one or more of the attributes, capabilities or features described below or evident from the appended drawings.

Apparatus and methods for providing tubing into a subsea well


A method for the analysis of samples including one or more glycopeptides including the steps of separating one or more glycopeptides using a chromatography system to produce a chromatographic eluent, adding a supercharging reagent to the chromatographic eluent, providing the chromatographic eluent and supercharging reagent to a mass spectrometer, ionizing the chromatographic eluent and supercharging reagent in an ion source to produce glycopeptide ions, performing at least one ion ion reaction on at least some of the glycopeptides ions to produce fragment ions, mass analyzing the fragment ions to produce ion ion reaction mass spectral data, and interpreting the ion ion reaction mass spectral data to provide structural information relating to the glycopeptide.

Glycoproteins are key components in many different functions within the human and animal body. It is often desirable to analyse the structure and sequence of glycoproteins and glycopeptides, in order to get information about health problems including breast cancer in Humans.
The analysis of glycoproteins and glycopeptides can be difficult ordinarily by mass spectrometry. In order to get significant information about any particular glycoprotein or glycopeptide sequence, data based upon the fragmentation of the analyte is required. One method of getting fragmentation data is typically Collision Induced Dissociation (CID), However, CID merely tends to result in the removal of the Glycan related group, which does not provide as much useful data for the sequencing of the Glycoprotein. An alternative method of fragmentation is Electron Transfer Dissociation. (ETD). However, ETD, does not provide much efficient fragmentation under normal conditions, which may also prevent sequencing the glycoprotein.
There is therefore a need for an improved method of analyzing glycoproteins and glycopeptides by Mass spectrometry where more fragments are produced, which allows the generation of data which provides greater sequence detail from which more structural information relating to the glycoprotein or glycopeptides can be deduced.

Methods for the analysis of glycoproteins or glycopeptides by mass spectrometry


A method and apparatus for the rapid cooling of screen masks used in the fabrication of semiconductor components is provided. The method and apparatus use a specially designed cooling plate which is contacted with a mask frame holding the screening mask. After a heated cleaning step which cleans the mask frame and screening mask of metal paste used in the screening operation, the cooling plate having one or more concave lower surfaces contacts the upper surfaces of the mask frame and bends the mask frame in the shape of the concave surfaces. This ensures intimate contact between the cooling plate and mask frame and enhances the thermal efficiency of the cooling step.

1. Field of the Invention
The present invention generally relates to screen printing and more particularly to a method for minimizing the distortion of a screening mask used in the screen printing process by controlling the cooling of a screening mask frame holding the screening mask after the screening mask has been cleaned at an elevated temperature and which frame and screen is then to be returned to the screen printing step of the process.
2. Description of Related Art
Screen printing to form a desired pattern on a substrate is very well known in the art. In general, the lower surface of a mask having a desired pattern is placed in contact with a substrate and a fluid material applied to the upper surface of the mask. The fluid material is then forced through the mask pattern (openings) onto the substrate forming the desired pattern. For convenience, the following description will be directed to the manufacture of semiconductor electronic components although it will be appreciated by those skilled in the art that the invention may be used for other screen printing processes.
In the fabrication of multi-layer ceramic substrates (MLC) for making semiconductor devices, conductive metal patterns are screened on individual ceramic greensheets by screen printing. In this process a screening mask, such as a metal mask, is placed in contact with the greensheet and a metallic paste is squeegeed on the greensheet surface through the mask pattern openings. After screening, the greensheets are assembled, aligned and laminated followed by a sintering operation to form a MLC. Fabrication techniques for making semiconductor devices including design, screening equipment and post screening processes are well known in the art.
The ground rules for making semiconductor devices continues to shrink, however, and maintaining tight control of pattern feature size and locations and mask tension of the mask screen becomes increasingly important. One problem in the screening process is that after the screening operation, paste residue is entrapped in the mask features in addition to a surface residue which is left on the screen surface. This requires that the mask be cleaned after one or more screening passes to eliminate/minimize the possibility of defects in subsequently screened patterns. Any defects in the screened paste pattern replicates into the final product causing a defective pattern and rejection of the product.
Using automated screening and mask cleaning processes, mask cleaning is typically preferred after one or more screening passes depending on whether the paste is fast drying or slow drying, otherwise the paste residue on the mask can cause defects in subsequently screened conductive patterns. Screening masks are typically made of metal, such as etched Ni or Mo masks. The screening paste used for defining via and wiring metallurgy patterns on the ceramic greensheets are typically comprised of a metal such as molybdenum, copper, tungsten, nickel, gold, platinum and silver. Some pastes may also contain inorganic fillers such as glass or ceramic powder, dispersed in an organic polymer binder in a high boiling organic solvent vehicle. Other additives include surfactants/dispersants, coloring agents, thickening agents or viscosity modifiers and antioxidants, etc.
In one in-line screening process, the screening mask secured in a frame, usually square, is supported on spaced apart rails whereby the front side and rear side of the frame traverse the space between the rails and the opposed sides of the frame rest on the opposed rails. In this system, the screening mask is secured to the lower side of the frame and the mask is suspended between the spaces of the rails. A greensheet is then positioned adjacent the screening mask and a conductive paste is applied to the upper surface of the screen and squeegeed onto the greensheet surface. After the screening operation the greensheet is removed and the frame and screening mask, which is now coated with excess paste, must be cleaned and the frame and screening mask assembly is moved to the cleaning section.
One technique for cleaning screen masks is by pressure spray cleaning with chemical solutions such as a dilute solution of tetramethyl ammonium hydroxide (TMAH) and/or related quaternary ammonium hydroxides. It is preferred that the mask cleaning be performed using a high pressure spray with a heated TMAH solution since this provides a reduction in cleaning cycle time. In general, and as described in U.S. Pat. No. 6,280,527 to Sachdev et al., which patent is incorporated herein by reference, Mo metal masks carrying conductive paste residue from the screening step are spray cleaned with an aqueous TMAH solution comprising less than 1 weight % TMAH in water. In one process the screening mask is sprayed for about 30 to 45 seconds using a hand-held spray nozzle or with a multi-nozzle spray at between about 50 and 70 psi and between about 130° F. to about 150° F. solution temperature. The mask can also be cleaned in less than about 15 seconds to about 20 seconds using a high pressure spray wash employing a specially designed multi-nozzle system at between about 150 and 200 psi and 130° F. and 180° F. in an automated in-line screening and mask cleaning machine such as described in U.S. Pat. No. 4,483,040, the disclosure of which is incorporated herein by reference. Subsequent to cleaning with TMAH, the screen masks are typically immediately rinsed with water and dried, preferably with forced hot air or nitrogen.
It is at this point in the screen printing process that distortion of the screening mask can occur because of the difference in cooling between the screening mask, which is relatively thin, and the mask frame which holds the screening mask, and which is relatively thick. In general, a screening mask is about 3 to 4 mils and a mask frame is about ⅛ inch thick. During the cooling the screening mask cools faster than the mask frame and the difference in cooling may cause a distortion of the screening mask and screening mask pattern.
Thick-film silk-screen and metal mask printing is used in the microelectronics industry to produce personalized conductive features for microchip packaging and solder paste applications. As ground rules continue to shrink, maintaining tight control of feature location and mask tension becomes increasingly important. Several patents disclose methods for maintaining such control. Japanese Patent No. JP58102768 discloses a method for heating mask frames using resistive heating elements. Japanese Patent No. JP5154986 improves on this patent by enabling both heating and cooling of the frame using fluid heat exchangers embedded within the mask frame. The addition of cooling capability is especially useful because it enables the compensation for rise in ambient temperature or for process-related temperature increases such as mask cleaning operations. Inherent in both of these methods is the requirement for modification of existing mask frames to accommodate the corresponding methods. For the former disclosure, heating elements would need to be affixed to the outside of the mask frame. For the latter, internal coolant passages would need to be formed inside the frame. The latter method would require a frame of sufficient thickness to accommodate said passages. Neither of these methods lends itself to easy implementation on a large inventory of existing mask frames, especially if existing mask frames are relatively thin (less than 0.25 in. thick) mask resulting in oblong vias and other such distortions of the pattern.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of screen printing which minimizes distortion of the screening mask caused by cooling of the screening mask after an elevated temperature cleaning step.
It is another object of the present invention to provide an apparatus for screen printing which minimizes distortion of the screening mask caused by cooling of the screening mask after an elevated temperature cleaning step.
A further object of the present invention is to provide a cooling plate for cooling a mask frame which holds a screening mask.
Still other objects and advantages of the present invention will in part be obvious and will in part be apparent from the specification.

Method and apparatus for rapid cooling of metal screening masks


A comb-like insert having a body and plurality of tapered fingers is installed with its fingers disposed within respective minichannels. The fingers and their respective minichannels are so sized as to restrict the channels and frictionally hold the insert in place in one dimension while providing for gaps in another dimension such that the flow of refrigerant is somewhat obstructed but allowed to pass through the gaps between the insert fingers and the minichannel walls and then expand as it passes along the tapered fingers to thereby provide a more homogenous mixture to the individual minichannels. A provision is also made to hold the insert in its installed position by way of internal structure within the inlet manifold. In one embodiment, an internal plate is provided for that purpose, and the plate has openings formed therein for the equalization of pressure on either side thereof.

This invention relates generally to air conditioning and refrigeration systems and, more particularly, to parallel flow evaporators thereof.
A definition of a so-called parallel flow heat exchanger is widely used in the air conditioning and refrigeration industry now and designates a heat exchanger with a plurality of parallel passages, among which refrigerant is distributed and flown in the orientation generally substantially perpendicular to the refrigerant flow direction in the inlet and outlet manifolds. This definition is well adapted within the technical community and will be used throughout the text.
Refrigerant maldistribution in refrigerant system evaporators is a well-known phenomenon. It causes significant evaporator and overall system performance degradation over a wide range of operating conditions. Maldistribution of refrigerant may occur due to differences in flow impedances within evaporator channels, non-uniform airflow distribution over external heat transfer surfaces, improper heat exchanger orientation or poor manifold and distribution system design. Maldistribution is particularly pronounced in parallel flow evaporators due to their specific design with respect to refrigerant routing to each refrigerant circuit. Attempts to eliminate or reduce the effects of this phenomenon on the performance of parallel flow evaporators have been made with little or no success. The primary reasons for such failures have generally been related to complexity and inefficiency of the proposed technique or prohibitively high cost of the solution.
In recent years, parallel flow heat exchangers, and brazed aluminum heat exchangers in particular, have received much attention and interest, not just in the automotive field but also in the heating, ventilation, air conditioning and refrigeration (HVAC&R) industry. The primary reasons for the employment of the parallel flow technology are related to its superior performance, high degree of compactness and enhanced resistance to corrosion. Parallel flow heat exchangers are now utilized in both condenser and evaporator applications for multiple products and system designs and configurations. The evaporator applications, although promising greater benefits and rewards, are more challenging and problematic. Refrigerant maldistribution is one of the primary concerns and obstacles for the implementation of this technology in the evaporator applications.
As known, refrigerant maldistribution in parallel flow heat exchangers occurs because of unequal pressure drop inside the channels and in the inlet and outlet manifolds, as well as poor manifold and distribution system design. In the manifolds, the difference in length of refrigerant paths, phase separation and gravity are the primary factors responsible for maldistribution. Inside the heat exchanger channels, variations in the heat transfer rate, airflow distribution, manufacturing tolerances, and gravity are the dominant factors. Furthermore, the recent trend of the heat exchanger performance enhancement promoted miniaturization of its channels (so-called minichannels and microchannels), which in turn negatively impacted refrigerant distribution. Since it is extremely difficult to control all these factors, many of the previous attempts to manage refrigerant distribution, especially in parallel flow evaporators, have failed.
In the refrigerant systems utilizing parallel flow heat exchangers, the inlet and outlet manifolds or headers (these terms will be used interchangeably throughout the text) usually have a conventional cylindrical shape. When the two-phase flow enters the header, the vapor phase is usually separated from the liquid phase. Since both phases flow independently, refrigerant maldistribution tends to occur.
If the two-phase flow enters the inlet manifold at a relatively high velocity, the liquid phase (droplets of liquid) is carried by the momentum of the flow further away from the manifold entrance to the remote portion of the header. Hence, the channels closest to the manifold entrance receive predominantly the vapor phase and the channels remote from the manifold entrance receive mostly the liquid phase. If, on the other hand, the velocity of the two-phase flow entering the manifold is low, there is not enough momentum to carry the liquid phase along the header. As a result, the liquid phase enters the channels closest to the inlet and the vapor phase proceeds to the most remote ones. Also, the liquid and vapor phases in the inlet manifold can be separated by the gravity forces, causing similar maldistribution consequences. In either case, maldistribution phenomenon quickly surfaces and manifests itself in evaporator and overall system performance degradation.
In tube-and-fin type heat exchangers, it has been common practice to provide individual capillary tubes or other expansion devices leading to the respective tubes in order to get relatively uniform expansion of a refrigerant into the bank of tubes. Another approach has been to provide individual expansion devices such as so-called "dixie" cups at the entrance opening to the respective tubes, for the same purpose. Neither of these approaches are practical in minichannel or microchannel applications, wherein the channels are relatively small and closely spaced such that the individual restrictive devices could not, as a practical manner, be installed within the respective channels during the manufacturing process.
In the air conditioning and refrigeration industry, the terms "parallel flow" and "minichannel" (or "microchannel") are often used interchangeably in reference to the abovementioned heat exchangers, and we will follow similar practice. Furthermore, minichannel and microchannel heat exchangers differ only by a channel size (or so-called hydraulic diameter) and can equally benefit from the teachings of the invention. We will refer to the entire class of these heat exchangers (minichannel and microchannel) as minichannel heat exchangers throughout the text and claims.

Minichannel heat exchanger with restrictive inserts