A method to just-in-time (JIT) compile Java software methods, the method having the steps of: initializing a first counter for a first software method to a first value, the first value being adjusted each time the first software method is invoked; initializing a second counter for a second software method to a second value, the second value being different from the first value, and the second value being adjusted each time the second software method is invoked; responsive to a determination that the first value exceeds a particular value, JIT compiling the first software method; responsive to a determination that the second value exceeds the particular value, JIT compiling the second software method.

Java (a trademark of Sun Microsystems, Inc.) is an object oriented programming language and execution environment allowing programmers to define software classes as encapsulated software components comprising data and functionality. The functionality within a Java class is represented by software methods which are executed by a Java virtual machine (JVM). A JVM is a virtual computer implemented as software on a computer system. A JVM includes components necessary to load Java classes and execute software methods written in the Java programming language.
Java classes are written by programmers in the Java programming language using Java instructions. Java instructions are subsequently encoded as platform independent bytecodes by a Java compiler and stored in binary Java class files until they are executed. On execution, the JVM loads a Java class file into memory and executes the software methods it contains. To execute a software method the JVM decodes and executes the bytecode instructions for the software method using a Java interpreter. Decoding a bytecode instruction involves converting the byte code instruction into one or more appropriate machine code instructions for the computer platform. The machine code instructions are subsequently executed by the computer's processor. This model of operation ensures Java classes are stored in platform independent bytecode format until execution, and can be loaded and executed on many computer platforms given the presence of a JVM capable of interpreting bytecodes. Java interpretation takes place for a software method each time the software method is executed.
The need to decode Java bytecodes to machine code prior to execution reduces the rate of execution of Java instructions when compared with that of native compiled programs which are stored as machine code (such as a compiled "C" application). Additionally, repeated execution of the same Java software method requires repeated decoding of the software method's bytecodes by the Java interpreter. To improve the speed of execution of Java instructions and reduce duplication through repeatedly decoding the same bytecodes it is desirable to decode the Java bytecodes in advance of execution. Some JVMs facilitate this by decoding all bytecodes in a software method to machine code and storing the machine code in memory when the software method is first executed. Decoding bytecodes for an entire software method in this way also offers the opportunity to optimize the machine code (such as removing non-operations) to further improve the performance of the executing software method. Once all bytecodes are decoded, the machine code is executed. Subsequent execution of the software method results in further execution of the existing machine code in memory. This technique is known as just-in-time (JIT) compilation because decoding takes place "just in time" for the first execution of a software method. JIT compilers result in a higher rate of execution of Java instructions than Java interpreters, though an initial performance penalty is paid as program execution is delayed while bytecodes are decoded to machine code on first execution. The length of the delay caused by JIT compilation is related to the number of bytecodes comprising a software method, with more bytecodes requiring more time for JIT compilation and therefore a longer delay. Furthermore, where a software method is executed few times (e.g. only once) the use of a JIT compiler with optimization can result in slower overall execution than a Java interpreter.
In "Overview of the IBM Java Just-in-Time Compiler" (IBM Systems Journal 2000 Vol. 39, No. 1, pp 175–193) Suganuma et al. disclose a method for executing Java software methods using a combination of a Java interpreter and a JIT compiler. The method involves providing an invocation count for each software method initialized as a certain threshold value. Whenever the software method is executed by the Java interpreter the JVM decrements the invocation count. When the invocation count reaches zero it is determined that the method has been invoked frequently enough and JIT compilation is initiated for the software method. Once JIT compiled the software method is executed in machine code for the remainder of the execution of the program. This technique offers the benefits of JIT compilation to only those software methods whose invocation count exceeds a determined threshold. Before the threshold is exceeded, software methods are executed using a Java interpreter. The use of the threshold to determine appropriate JIT compilation ensures only software methods which are executed frequently will be JIT compiled to justify the investment of processor time in JIT compilation.
In a transactional environment where software methods are executed in a JVM on a computer system in response to transaction requests from one or more client computer systems, multiple software methods are executed in a repetitive fashion over many transactions. This results in the invocation count for multiple software methods meeting the JIT compilation threshold at the same time, and so multiple software methods are JIT compiled at the same time. JIT compilation of multiple software methods results in an increased performance penalty as program execution is delayed while bytecodes are decoded to machine code for each software method. The transaction that caused software methods to exceed the JIT compilation threshold will experience an unacceptably high delay in the JVM processing of the transaction request as multiple software methods are JIT compiled in the JVM.

Just in time compilation of java software methods

International Business Machines Corporation


Disclosed is a process for forming a normalized genomic DNA library from an environmental sample by (a) isolating a genomic DNA population from the environmental sample; (b) at least one of (i) amplifying the copy number of the DNA population so isolated and (ii) recovering a fraction of the isolated genomic DNA having a desired characteristic; and (c) normalizing the representation of various DNAs within the genomic DNA population so as to form a normalized library of genomic DNA from the environmental sample. Also disclosed is a normalized genomic DNA library formed from an environmental sample by the process.

There has been increasing demand in the research reagent, diagnostic reagent and chemical process industries for protein-based catalysts possessing novel capabilities. At present, this need is largely addressed using enzymes purified from a variety of cultivated bacteria or fungi. However, because less than 1% of naturally occurring microbes can be grown in pure culture (Amann, 1995), alternative techniques must be developed to exploit the full breadth of microbial diversity for potentially valuable new products.
Virtually all of the commercial enzymes now in use have come from cultured organisms. Most of these organisms are bacteria or fungi. Amann et al. (Amann, 1995) have estimated cultivated microorganisms in the environment as follows:
______________________________________ Habitat Culturability (%) ______________________________________ Seawater 0.001-0.1 Freshwater 0.25 Mesotrophic lake 0.01-1.0 Unpolluted esturine waters 0.1-3.0 Activated sludge 1.0-15.0 Sediments 0.25 Soil 0.3 ______________________________________
These data were determined from published information regarding the number of cultivated microorganisms derived from the various habitats indicated.
Other studies have also demonstrated that cultivated organisms comprise only a small fraction of the biomass present in the environment. For example, one group of workers recently reported the collection of water and sediment samples from the "Obsidian Pool" in Yellowstone National Park (Barns, 1994) where they found cells hybridizing to archaea-specific probes in 55% of 75 enrichment cultures. Amplification and cloning of 16S rRNA encoding sequences revealed mostly unique sequences with little or no representation of the organisms which had previously been cultured from this pool, suggesting the existence of substantial diversity of archaea with so far unknown morphological, physiological and biochemical features. Another group performed similar studies on the cyanobacterial mat of Octopus Spring in Yellowstone Park and came to the same conclusion; namely, tremendous uncultured diversity exists (Ward, 1990). Giovannoni et al. (1990) and Torsvik et al. (1990a) have reported similar results using bacterioplankton collected in the Sargasso Sea and in soil samples, respectively. These results indicate that the exclusive use of cultured organisms in screening for useful enzymatic or other bioactivities severely limits the sampling of the potential diversity in existence.
Screening of gene libraries from cultured samples has already proven valuable. It has recently been made clear, however, that the use of only cultured organisms for library generation limits access to the diversity of nature. The uncultivated organisms present in the environment, and/or enzymes or other bioactivities derived thereof, may be useful in industrial processes. The cultivation of each organism represented in any given environmental sample would require significant time and effort. It has been estimated that in a rich sample of soil, more than 10,000 different species can be present. It is apparent that attempting to individually cultivate each of these species would be a cumbersome task. Therefore, novel methods of efficiently accessing the diversity present in the environment are highly desirable.

Production and use of normalized DNA libraries


The present invention relates to a method of receiving available channel information on K (K≧2) numbers of locations by a first type station (STA) from a second type STA in a wireless communication system includes: receiving a channel availability query (CAQ) response message, wherein the CAQ response message includes a field of the numbers (K) of the locations and K numbers of available channel list fields configured with information on an available channel list for each of the K numbers of locations, from the second type STA, and performing a communication in a white space using an available channel included in an available channel list for a single location among the K numbers of locations, wherein the K numbers of available channel list fields are configured with a Map ID field and a field of N (N≧1) numbers of available channels are repeated K times.

A standard for a wireless local area network (WLAN) technology has been developed as IEEE (Institute of Electrical and Electronics Engineers) 802.11 standard. IEEE 802.11a and IEEE 802.11b use an unlicensed band in 2.4 GHz or 5 GHz, IEEE 802.11b provides transmission speed of 11 Mbps and IEEE 802.11a provides transmission speed of 54 Mbps. IEEE 802.11g provides transmission speed of 54 Mbps in a manner of applying Orthogonal Frequency Division Multiplexing (OFDM) in 2.4 GHz. IEEE 802.11n provides transmission speed of 300 Mbps for 4 spatial streams in a manner of applying Multiple Input Multiple Output-OFDM (MIMO-OFDM). IEEE802.11n supports a channel bandwidth up to 40 MHz. In this case, IEEE802.11n provides transmission speed of 600 Mbps.
Currently, ongoing effort to develop IEEE 802.11af standard has been performed. IEEE 802.11af standard is a standard set to regulate an operation of an unlicensed device in a TV whitespace (TVWS) band.
The TVWS is a frequency band assigned for a TV broadcast and includes a Very High Frequency (VHF) band (54˜60 MHz, 76˜88 MHz, 174˜216 MHz) and an Ultra High Frequency (UHF) band (470˜698 MHz). The TVWS means a frequency band permitted to an unlicensed device to use under a condition that the unlicensed device does not impede a communication of a licensed device operating in a corresponding frequency band. The licensed device may include a TV, a wireless microphone, and the like.
Although operations of all unlicensed devices are permitted on 512˜608 MHz and 614˜698 MHz except several special cases, a communication between fixed devices is only permitted on 54˜60 MHz, 76˜88 MHz, 174˜216 MHz, 470˜512 MHz. A fixed device indicates a device performing a transmission at a fixed position only. In the following description, a white space band includes the aforementioned TVWS, by which the present invention may be non-limited.
The unlicensed device wishing to use the TVWS should provide a protection function for a licensed device. Hence, the unlicensed device should check whether the licensed device occupies a corresponding band before starting a transmission in the TVWS. In particular, a use of the unlicensed device is permitted only when the licensed device is not used in the white space band.
To this end, the unlicensed device should obtain channel list information available in a corresponding region in a manner of accessing a geo-location database (GDB) via the internet or a dedicated network. The GDB is a database configured to store and manage channel usage information, which is dynamically changing in accordance with information on licensed devices registered to the GDB, geographical locations of the licensed devices, and hours of use. Moreover, such a signaling protocol as a common beacon frame and the like, a spectrum sensing mechanism, and the like may be used to solve a coexistence problem between the unlicensed devices using a white space.
In IEEE 802.11 system, a TVWS terminal may indicate an unlicensed device operating using IEEE 802.11 MAC (medium access control) layer and a PHY (physical) layer in a TVWS spectrum. Unless there is a separate explanation in the present specification, a station (STA) indicates the TVWS terminal operating in the TVWS spectrum.
The STA should provide a function of protecting an incumbent user, which corresponds to a user to which a preferential access is permitted, including a licensed user (TV, wireless microphone, and the like). In particular, if a TVWS is in use by the incumbent user, the STA should stop using a corresponding channel. Hence, the STA should operate in an available channel in a manner of searching for an available channel (i.e., a channel not used by a licensed device) capable of being used by an unlicensed device.
A method of searching for an available channel, which is searched by the STA, includes a scheme of performing a spectrum sensing mechanism, a scheme of finding out a TV channel schedule by accessing a GDB, and the like. An energy detection scheme (a scheme of judging a use of an incumbent user if a strength of a reception signal is greater than a prescribed value), a feature detection scheme (a scheme of judging a use of an incumbent user if a digital preamble is detected), and the like may be utilized as the spectrum sensing mechanism. Subsequently, the STA obtains GDB information based on location information of the STA in a manner of accessing the GDB and finds out whether a licensed device uses a channel in the corresponding location. Accessing the GDB and obtaining information should be performed with a frequency sufficient enough to protect the licensed device.
If it is judged that an incumbent user uses a channel immediately adjacent to a currently used channel, a user equipment (or STA) and a base station (or access point (AP)) may protect the incumbent user with a scheme of lowering a transmit power.
For instance, detail contents on an operation in a TVWS may refer to 'Second Memorandum Opinion and Order' (FCC, ET Docket No. 10-174, September 2010.) document, 'IEEE 802.22: The first cognitive radio wireless regional area network standard' (C. R. Stevenson, G. Chouinard, Z. Lei, W. Hu, S. J. Shellhammer, and W. Caldwell, IEEE Comm. Mag., pp. 130-138, January 2009) document, 'TVWS PAR and 5C' (IEEE 802.11-09/0934r05, September 2009.) document, and the like.

Method and apparatus for transceiving a contact verification signal regarding available channels in a plurality of locations in a wireless communication system

INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY


A computer housing is adapted for mounting an interface card, and includes a housing body and a positioning device. The housing body includes a mounting portion and a first fixing portion disposed adjacent to the mounting portion. The positioning device includes a positioning component having a second fixing portion. The positioning component is pivotable relative to the housing body between a card retaining position, where the second fixing portion engages the first fixing portion and the positioning component is disposed to be capable of blocking removal of the interface card from the mounting portion, and a card releasing position, where the second fixing portion is disengaged from the first fixing portion and the positioning component is disposed to permit removal of the interface card from the mounting portion.

1. Field of the Invention
The invention relates to a computer housing, more particularly to a computer housing that uses a pivotable positioning component instead of screws to fasten an interface card to a housing body.
2. Description of the Related Art
A computer housing is generally formed with a plurality of mounting hole portions for mounting various types of interface cards, such as a video card, an audio card, a network card, etc. As shown in FIG. 1, a conventional computer housing 1 has a panel 11 formed with a plurality of vertical mounting hole portions 12. As shown in FIG. 2, another conventional computer housing 2 has a panel 21 formed with a vertical mounting hole portion 211, and a frame 22 assembled to the panel 21 and formed with a plurality of horizontal mounting hole portions 221. The interface cards (not shown) are secured to the mounting hole portions 12, 211, 221 of the computer housings 1, 2 with the use of screws (not shown), which is inconvenient and time-consuming.

Silitek Electronic (Guangzhou) Co., Ltd.


A flexible circuit board includes: an insulative substrate having a first surface and a second surface opposite to the first surface; a microstrip line having a first signal line formed on the first surface and a first ground pattern formed on the second surface and located in an area opposite to the first signal line; a coplanar line having a second signal line formed on the first surface, and second ground patterns that are formed on the first surface and are spaced apart from both sides of the second signal line; a connection line that is formed on the first surface and connects the first signal line and the second signal line together, the connection line having an opening; and third ground patterns formed on the second surface and arranged in areas located at both sides of an area opposite to the connection line including the opening.

(i) Technical Field
The present invention relates to a flexible circuit board, and more particularly, to a flexible circuit board having a converter that interconnects a coplanar line and a microstrip line.
(ii) Related Art
A flexible printed circuit board (FPC) is used for interconnecting electronic circuits (see Japanese Patent Application Publication No. 2011-238883, for example). Pads to which lead pins of a package are connected are formed at opposite ends of the flexible printed circuit board. The pads are formed by coplanar lines, and a microstrip line is formed as a line for connecting the pads together.
In some cases, impedance matching between the coplanar line and the microstrip line may not be established in a position where a connection between these lines is made.

Sumitomo Electric Device Innovations, Inc.


A vehicle interior illumination lamp 11 for mounting in an opening formed in an interior member of a vehicle includes a function portion 12 having a bulb 22 serving as a light source and a switch lever 74 for effecting and interrupting the supply of electric power to the bulb 22, and a design portion 13 having a cover lens 42 covering the function portion 12 and a switch knob 47 for operating the switch lever 74. The switch lever 74 is pivotally mounted on the function portion 12, and the switch knob 47 is pivotally mounted on the design portion 13. When the function portion 12 and the design portion 13 are combined together, shaft portions 78, serving as an axis of pivotal movement of the switch lever 74, coincide with shaft portions 84 serving as an axis of pivotal movement of the switch knob 47.

1. Field of the Invention
This invention relates to an interior illumination lamp for a vehicle which is mounted within a room of the vehicle.
2. Related Art
Generally, a vehicle has an interior illumination lamp mounted on a ceiling thereof. As shown in FIG. 15, one known such interior illumination lamp includes a function portion 4 which is fixed to a ceiling 1 of a vehicle body, and is partially exposed through an opening 3 formed through a ceiling plate (interior member) 2, and a design portion (cover lens) 5 which is fitted into the opening 3 in the ceiling plate 2 from the inside of a vehicle room, and is attached to the function portion 4 (see, for example, Unexamined Japanese Patent Publication 2002-79879).
This interior illumination lamp includes a switch 6 provided at the function portion 4, and a slidable switch knob 7 provided at the design portion 5. When the design portion 5 is to be attached to the function portion 4, a slider 8 of the switch 6 is engaged in an engagement portion 9 (in the form of a recess) formed in the switch knob 7 as shown in FIG. 16, and by doing so, the switch 6 can be operated by sliding the switch knob 7.
In the interior illumination lamp of the above construction, if the slider 8 of the switch 6 is disposed out of registry with the engagement portion 9 of the switch knob 7 at the time of attaching the design portion 5 to the function portion 4, the slider 8 can not be engaged in the engagement portion 9, and interferes with other portion than the recess of the engagement portion 9, so that the lamp can not be smoothly assembled.
Therefore, it is necessary that the slider 8 of the switch 6 and the engagement portion 9 of the switch knob 7 should be disposed accurately in registry with each other at the time of attaching the design portion 5 to the function portion 4, and therefore the assembling operation has been cumbersome.


A method, system, and product are disclosed for indicating a power status of multiple devices using hierarchically encoded indicators. Multiple nodes are included within a data processing system. Each node includes a different implementation of the devices. Each one of a first level of power indicators are associated with a different one of the nodes. Each one of a second level of power indicators is associated with a different one of the devices. A power status of each node is indicated utilizing one of the first level of power indicators. A power status of each device is indicated utilizing the second level of power indicators.

1. Technical Field
The present invention relates generally to an improved data processing system, and in particular to a method, system, and product for indicating power status for field replaceable units (FRUs) where hierarchically encoded service indicators are used to indicate when service is needed.
2. Description of Related Art
Service indicators, such as LEDs, are typically used to help service technicians locate the correct component to be repaired on a computer system. On many small and mid-range computers, each field replaceable unit (FRU) has an unlabeled LED which represents the FRU that needs to be repaired. The LED is physically mounted on the FRU itself or the second level package that includes the FRU. Therefore, the LED does not need to be labeled since it is physically located on the FRU, or the FRU's outer package, that needs service. In these systems, there is a one-to-one correspondence between each FRU and the indicator that represents the FRU. Thus, in these systems, each FRU is associated with and represented by its own LED.
On high end systems, because of the density of the package and number of FRUs involved, a light strip is sometimes used to mount the LEDs in a visible location. Thus, instead of being mounted directly on the FRU or the second level package that includes the FRU, each LED is mounted on the light strip. The light strip includes an LED for each FRU in the system. In this example, there remains a one-to-one correspondence between FRUs and LEDs. Each individual FRU is associated with and represented by its own LED.
In some high end systems, all of these LEDs could total in the hundreds. This creates many problems. The light strip must be very large and located somewhere close to the central processing complex that includes the processing nodes, but not in the way of service technicians or airflow for cooling. There may be problems with lighting this large number of LEDs in standby mode of operation. And, it may be hard for the service technician to distinguish which LED is associated with which FRU because of the large number of LEDs. This then defeats the purpose of having LEDs.
In addition to the LED that indicates whether a particular FRU needs service, other indicators may be used to indicate whether a particular FRU is currently receiving power. Thus, each individual FRU will have one or more indicators that represent its status. When the power status of an FRU is to be indicated, the FRU will have two indicators associated with it, one to indicate service and one to indicate power status.
Some FRUs support concurrent replacement. Concurrent replacement means that an FRU may be replaced while the system is running. It is imperative that a service technician know the status of the power on the FRU before attempting to replace it. If the power is not in the correct state and the service technician attempts to replace the FRU, it could cause the system to checkstop and crash for what would otherwise have been a concurrent repair.
Therefore, a need exists for a method, system, and product indicating power status for field replaceable units (FRUs) where hierarchically encoded service indicators are used to indicate when service is needed.

Method, system, and product for indicating power status of field replaceable units


A third-harmonic conversion arrangement includes a second-harmonic generating crystal and a third-harmonic generating crystal arranged in a polarization loop. The polarization loop, which includes a plurality of mirrors, a polarization-selective reflector, and a polarization rotator, causes plane-polarized fundamental-wavelength radiation being converted to make two passes through the crystals in orthogonally-opposed polarization orientations.

In solid-state laser systems for providing ultraviolet (UV) wavelength radiation, it is usual to generate the UV radiation by harmonic conversion of visible-wavelength radiation in an optically nonlinear crystal. By way of example, in one common arrangement for providing UV radiation, fundamental-wavelength radiation is generated by an optically-pumped solid-state laser that has a near-infrared wavelength. The visible radiation is generated by second-harmonic conversion of the fundamental radiation in a first optically nonlinear crystal. The visible radiation has the second-harmonic wavelength of the fundamental radiation. This second-harmonic conversion is less than 100% efficient. Residual (unconverted) fundamental radiation from the second-harmonic conversion and the visible radiation generated by the second-harmonic conversion are then converted to UV radiation by sum-frequency mixing in a second optically nonlinear crystal. The UV radiation has the third-harmonic wavelength of the fundamental radiation.
A particular shortcoming of the above-described arrangement is that the power of the UV radiation is clamped with respect to scaling the power of the fundamental radiation. The reason for this clamping is that the optimum power ratio between the visible radiation and the fundamental radiation for sum-frequency mixing is about 2:1, due to energy conservation. As the power of the fundamental radiation is increased, the efficiency of second-harmonic conversion of the fundamental radiation to visible radiation initially increases quadratically and then asymptotically, until essentially all of the fundamental radiation is converted into visible radiation. Meanwhile, the efficiency of sum-frequency mixing increases to a peak efficiency at a fundamental radiation power corresponding to about 67% second-harmonic conversion efficiency, then declines. This decline due to energy conservation, which limits the overall conversion of the fundamental radiation to UV radiation.
Absolute values of the efficiencies for second-harmonic generation to produce visible radiation and third-harmonic generation to produce UV radiation are dependent, inter alia, on the material the optically nonlinear crystals are made of, the intensity of the radiation in the optically nonlinear crystals, and the wave-front planarity of the radiation in the optically nonlinear crystals.
There is a need for an optical arrangement that will allow a more progressive increase in third-harmonic generation efficiency with increasing power of fundamental radiation. Preferably, the arrangement should provide higher third-harmonic generation efficiencies that are more comparable with second-harmonic conversion efficiencies.

Third-harmonic generating apparatus for laser-radiation having polarization loop


A pressure regulator comprising a housing, a pivoting lever selectively covering a passage between an inlet port and an outlet port of the housing, a diaphragm interconnected to the lever to rotate the lever in reaction to pressure levels in the housing, and a closure member abutting the pivoting lever and covering the passage to prevent fluid flow through the passage. The pressure regulator can have the closure member not being directly connected to the lever, a stabilizer element frictionally abutting a pivot pin as the lever rotates to thereby stabilize movement of the lever, an adjustment member that translates rotational movement of an adjustment cap into compression or decompression of a biasing element without applying a rotational force to the biasing element, and/or the cap including a tab configured to be selectively inserted at least one slot on the housing to prevent rotation of the adjustment cap.

This invention is applicable to a wide range of gas pressure-regulating applications, but is designed for particularly advantageous use in propane outdoor cooking appliance applications.
Heretofore, the gas pressure output of a pressure regulator has been controlled by applying the inlet pressure against a flexible diaphragm surface area that is balanced with a spring force set at or adjusted to the desired output gas pressure. Most regulators using flexible diaphragms, however, have not had a direct-acting mechanism between the regulating valve and the diaphragm. Therefore, more parts are needed to control the flow of the gas, and regulation is often not as well controlled and accurate as desired. Also, the pressure regulators had to be large and expensive because of all of the elements needed to control the gas pressure. Furthermore, such pressure regulators typically require gas pressure in the outlet gas line to operate the regulating device and to shut off the flow of gas. If a positive shut-off is required as a safety measure, a separate shut-off valve had to be placed at the outlet of the regulator to prevent the flow of gas downstream. Such a separate shut-off valve adds further expense.
Accordingly, an apparatus which avoids the aforementioned disadvantages and has the aforementioned desired features has long been desired.

Pressure regulator with improved outlet pressure control


Fundamental interconnect systems for connecting high-speed electronics elements are provided. Interconnect system has the means, which could reduce the microwave loss by reducing the effective dielectric loss and dielectric constant of the interconnect system, and increase the bandwidth of the interconnects and also reduce the signal propagation delay, respectively. Ideally, the speed of the electrical signal on the signal line can be reached to speed of the light in the air, and the bandwidth can be reached to closer to the optical fiber. The interconnect systems consists of the signal line, dielectric system with opened trench or slot filled up with the air or lower dielectric loss material, and the ground plan. The signal line proposed in this invention could be made any type of signal line configuration for example, microstripline, strip line or coplanar line. The signal line can also be made as single ended or differential pairs of any configurations. The interconnect system based on the fundamental techniques provided in this invention, can be used for on-chip interconnects where the high speed electronics devices are connected by the signal line laid on the oxide or dielectric material. Again, the interconnect system based on the fundamental techniques provided in this invention, can also be used for off-chip interconnects (chip-to-chip interconnects), where the whole portion or portion of the PCB on which high speed chips are to be connected, are having the dielectric system with opened trench or slot to reduce the microwave loss. High scale chip-to-chip interconnection using of the multilayered PCB is possible. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables. The main advantages of this invention are to make high speed interconnects systems for on-chip and off-chip interconnects. More over, this fundamental technology is also used for the high sped die package, high speed connector, and high speed cables where conventional manufacturing technology can be used and yet to increase the bandwidth of the interconnects.

The increasing of higher level of integration within electrical integrated circuit (IC) leads to both higher data rates and larger number of IC interconnections. Today, the inherent signal speed of IC is increased to 3 GHz, and shortly it will be reached to 10 GHz and beyond. The number of pin connection is also increased, with single IC requiring close to 2000 interconnection (i.e. single processor), and shortly it will be increased to over 5000. Simultaneously achieving higher data rates and higher interconnect densities for both on-chip and also off-chip, will be increasingly difficult as the IC technologies continue to evolve increasing signal speed of electronic devices and interconnection number. In on-chip cases (intra chip), as the number of the electronic devices such as transistor are increasing with development of the fabrication technology, the interconnecting the electronic devices without sacrificing the signal speed is getting challenging. In off-chip case, high density interconnects, covering from die-level packaging to chip-to-chip (hereafter chip indicates the die with package) interconnection on the printed circuit board (PCB), will also be getting increasingly difficult as the IC technologies continue to evolve increasing the signal speed and interconnection number.
With increasing of the signal speed and interconnection number within and outside of the IC, low-cost high-level interconnect technique compatible to today's manufacturing process are highly desirable to make available in consumer level.
Generally, it is known that if the electronic devices (for both on-chip and off-chip) are connected with the help of the metal conductor, electrical signal can be flown and the electronic device can be communicated with each other. This is true for the low-speed signal, below few MHz. In high-speed interconnection for both on-chip and off-chip interconnects, all connected signals should be considered to be propagated through well impedance matched transmission line. Any discontinuities in the electrical signal line due to impedance impedance mismatch, or the VIA etc. cause the reflection, which degrades the signal waveform reaching to the other side of the electronics devices. At multi GHz frequencies, interconnect lengths become a significant fraction of the wavelength of the high frequency harmonics, and therefore interconnects must be design with proper concern of impedance, cross talk, and attenuation. Impedance mismatch must be minimized to reduce the reflections and prevent ringing, which can cause false decision (switching) in the receiver signal. Significant attenuation and rise-time degradation can be caused by losses in the transmission line. The transmission line loss is the sum of the conductor loss and dielectric loss, both of which are dependent on the frequency.
Today technology development pushes to reduce the size of the electronic device, resulting in utilization of number of the devices inside single chip. As the level of integration targeting for future 'system-on-a-chip' design, is increasing, the chip area is also increasing. Novel interconnection technique compatible to standard IC fabrication technology is necessary; yet preserve the signal speed while assuring the adequate isolation for high-speed data communication. With increasing of intrachip signal speed, the interchip (off-chip) signal speed also increases, which require also novel technique, which could be also compatible to today's PCB technology.
FIG. 1 and FIG. 2 are the schematic showing part of conventional on-chip (intra) and off-chip (inter-chip) interconnections. In on-chip interconnection as shown in FIG. 1, single substrate 100 comprises with many electronics devices 102, and are connected by the metal conductor 104. Dielectric layer 106 such as silicon oxide for Si device isolates each device. Metal conductor such as Al, Cu, W, and WSi etc. is used for connecting on-chip devices.
In off-chip interconnection, as shown in FIG. 2, the chip 120 (for example processor) is connected with chip 130 (for example 3) by multilayered electrical signal lines 110 in the PCB 105. FIGS. 3 and 4 show the schematic representing the conventional BGA (ball grid array) and CSP (chip-scaled package) based packaging for high-speed single chip package (for example processor). In both type of packaging, die 122 and die 132 are attached with the ceramic or polymer substrate 124 and 134, respectively, containing the matrix of pins 126 and 136. Outside pins 128 and 138, located at the bottom-side of chip package (in both packaging cases) connect with the PCB, whereas topside of the package is connected with the heat sink to dissipate heat from the die. Both types of packages provide closer proximity of signal as on-chip. The fidelity of signal occurred due to the conventional interchip electrical signal connections 110 and ground/power 112 through multiplayer PCB 108. It is highly desirable having the board-level electrical interconnects for high-speed interchip connection, which could be compatible with existing IC package such as BGA, CSP etc., and also could be employed conventional PCB technologies.
Today's interconnection technology for both on-chip (intra-chip) and off-chip (inter-chip) are mainly based on the microstrip line or strip-line transmission layout on the dielectric material. FIG. 5A shows a cross-sectional of a microstrip layout, which refers to a trace routed as the top or bottom layer for example of a PCB for the case of off-chip interconnection. The electrical conductor 140A with width W and thickness T are laid on the dielectric material 142A having height H. The ground or power line 144A is located opposite of the signal conductor 140A. FIG. 5B is the cross-sectional view of strip line layout, which uses a trace 140B routed on the inside layer 142B for example of a PCB and has two voltage-reference planes (i.e. power and/or ground) 144B and 144B′. The impedances of microstrip line and strip line are expressed by:Zmicrostrip=[(87/Sqrt.(∈r+1.41)]In[(5.98×H)/(0.8W+T)]Ω  (1)Zstrip=[(60/Sqrt.(∈r))]]]In[(4H)/(0.67 π(0.8W+T))]]]Ω  (2)
Equations (1) and (2) indicate that the impedance is directly proportional to the dielectric constant ∈r, trace height H, and the inversely proportional to the trace width W and trace thickness T. In stripline layout, the signal line is sandwiched by the dielectric layer, whereas a microstrip layout has one conductor open to air. In microstripline type traces, the field is in both dielectric layer and air whereas in strip line type traces, the filed is confined inside dielectric materials. This causes a higher, effective dielectric constant stripline layout compared to microstrip layouts. Besides, these also causes the less dielectric loss in microstripline as compared with stripline. Higher effective dielectric loss experiences much dispersion or signal loss as compared with that of the microstrip line layout. FIG. 6 shows the top view and cross-sectional view of the microstrip line transmission layout, showing the electrical field distribution. The electrical field 146A is spreading both side of the electrical signal line 140A. FIGS. 7A and 7B are the frequency response of the microstrip line and strip line layout. As the effective dielectric constant (using of the same material) of the strip line layout is higher than that of the microstrip line layout. The signal is attenuated more in strip line layout in compared with increasing of the frequency. This also suggests that effective dielectric loss should be kept low to increase the bandwidth of the interconnection.
High-speed signal while propagating through the transmission line experiences the signal propagation delay, and it is dependent on the dielectric constant of the material. The signal propagation delay for the strip line and microstrip lines are expressed by:tPD microstrip=85[Sqrt.(0.475∈r+0.67)]  (3)tPD strip=85[Sqrt.(∈r)]  (4)
Equations (3) and (4) indicate that as ∈r increases, the propagation delay also increases. Microstrip line has comparatively lower propagation delay than the strip line layout for the fixed dielectric constant ∈r.
As mentioned earlier, electrical field inside dielectric material having higher dielectric constant experiences more signal delay as compared with that of transmission line comprising with lower dielectric constant material. These causes signal skews for the different length signal lines. In this case also, lower dielectric constant material is necessary in the interconnection for high-speed signal interconnection. This is true for both on-chip and off-chip interconnection. Lower dielectric constant material with low dielectric loss offers following functions;
(1) Higher density interconnection is possible due to reduction of the cross-talk;
(2) reducing the capacitance of the interconnection, helping to transfer the signal longer distance;
(3) lower propagation delay; and
(4) reducing the microwave loss as the field is spread closer to the electrical conductor, and help to transmit the longer distance. In other words, help to transmit the higher speed signal as compared with the higher dielectric constant and with same loss tangent.
Besides the dielectric constant of the material or the type of the signal line, the microwave loss due to dielectric material and also the electrode structure also limits the bandwidth of the interconnection. Microwave-loss occurs due to the electrode structure mainly from skin-depth of the signal. As Cu's skin-depth at 100 GHz is 0.2 μm, the skin-depth due to the conductor structure is neglected. So, the bandwidth of the interconnection (for both on-chip and off-chip interconnection) is mainly dependent on the following factors:
(1) length of the interconnects; and
(2) microwave-loss, mainly originated from the (a) dielectric constant, (b) dielectric loss tangent, and (c) electrode structure.
As the length of the interconnections in on-chip and off-chip varies from the few micrometers to 10 to 30 cm, the length dependency can be neglected. Mainly, the interconnection bandwidth is dependent on the dielectric constant and the material loss tangent.
It is very straight forward that increasing the bandwidth can be possible using of the material having the lower loss tangent (dielectric loss). However, in this case, for both on-chip and off-chip interconnection new material development is necessary. Additionally, manufacturing technology development is needed to implement product-level devices.
Much work can be found in both on-chip and off-chip interconnection technology focusing on the material development. As for example, in on-chip interconnection, low-K (dielectric constant) material is under development stage, to achieve lower dielectric constant than non-doped silicon oxide. Lowering the dielectric constant than silicon oxide is possible in some extend from material characteristic point view, which is not long-term technique, and beyond that different materials are necessary. Besides, implementing new material in chip fabrication process will cost tremendously to make it mature. Having low-K material for on-chip interconnection is not only time consuming development, but also the costly short-term solution. On the other hands, in off-chip interconnection, especially for the chip-to-chip interconnection, more focused are being paid on shortening the length or on the interconnection layout. In both cases, implementing technology would need to pay high cost.
As explained above, the conventional electronics interconnect technology being used in on-chip and off-chip interconnection cannot be used as the need of the signal speed is increasing. And also exiting conventional electrical interconnects have the limitation of achieving the bandwidth in certain level, beyond that complete manufacturing technology is needed to be changed which is costly for IC and PCB industries. It is highly desirable to have lower dielectric constant and lower dielectric loss (loss tangent) by adopt a technique or method which can be easily implemented, and which can use the standard dielectric material and IC and PCB technology.

High speed electronics interconnect and method of manufacture


A zoom lens including subsequently from an object side of the zoom lens to an image side of the zoom lens: a first lens group with a positive focal length; a second lens group with a negative focal length, an aperture arranged on an object side of a third lens group; the third lens group with a positive focal length, a forth lens group with a positive focal length. By zooming from a short focal end to a long focal end, an interval between the first lens group and the second lens group increases, an interval between the second lens group and the third lens group decreases, an interval between the third lens group and the fourth lens group increases. The first lens group has sequentially from an object side of the first lens group: a negative meniscus lens L1 having a convex surface facing the object; a positive lens L2; satisfying a conditional expression: Nd11>1.96 (Nd11: a refractive index of the negative meniscus lens L1.

1. Field of the Invention
The present invention relates to a zoom lens capable of changing a focal length by moving lens groups along an optical axial direction back and forth and an image-taking device equipped with the zoom lens, more specifically to a zoom lens especially suitable for a digital camera, a portable terminal device, a video camera and or the like and an image-taking device equipped with the zoom lens.
In recent years, the digital camera having a changeable focus mechanism such as a zoom lens camera barrel or the like is commonly available. The changeable focus mechanism can change continuously between a wide angle state and a telescopic angle state. The wide-angle state is that a focal length of a photographing lens is short and an angle of field is wide. The telescopic angle state is that the focal length of the photographing lens is long and the angle of field is narrow.
As for the digital cameras in recent years, a better picture, miniaturizing, more of the wide angle, more of a large caliber, and or the like are desired in a market.
Moreover, the better picture, miniaturizing, more of the wide angle and more of the large caliber for corresponding to a light detecting element which exceeds three million pixels are requested. The miniaturization means reducing a storage length of the lens, a total length of the lens, and a maximum of an effective diameter or the like.
2. Description of the Related Art
So, as a technical document filed earlier than the present invention, for example, Japanese Patent Publication No. 2004-354870 discloses a zoom lens of rear focus type which includes as follows: a first lens group that has a positive refracting power; a second lens group that has a negative refracting power; a third lens group that has a positive refracting power; a fourth lens group that has a positive refracting power; a fifth lens group that has a negative refracting power. The zoom lens is configured to zoom by moving the second lens group and the fourth lens group. When a distance of object is infinity and an image formation magnification of the fifth lens group is set to be β5 simultaneously, the zoom lens satisfies a condition of 1.6<β5<2.2. An excellent optical performance is obtained if a zooming ratio is set about 3-5 times. An entire system of the lens is miniaturized.
Moreover, Japanese Patent Publication No. 2004-286811 discloses a zoom lens that includes as follows sequentially from an object side of the zoom lens to an image side of the zoom lens: a first lens group that has a positive refracting power and doesn't move along with a zooming; a second lens group which has a negative refracting power and moves from the object side of the zoom lens to the image side of the zoom lens along with the zooming from a wide angle end to a telephoto end; a third lens group that has a positive refracting power and moves from the image side of the zoom lens to the object side of the zoom lens from the wide angle end to the telephoto end along with the zooming; a fourth lens group that has a positive refracting power and doesn't move along with the zooming. The third lens group has a three piece cemented lens that consists of a negative lens, a positive lens and a negative lens. Even though the zoom lens is small enough with a wide angle of field, the zoom lens is efficient, and the lens enables it to obtain a resolving power corresponding to an image sensor of 3-5 million pixels.
Moreover, Japanese Patent Publication No. 2004-199000 discloses a zoom lens that includes as follows: from an object side of the zoom lens sequentially, a first lens group that has a positive refracting power; a second lens group that has a negative refracting power; a third lens group that has a positive refracting power; a fourth lens group that has a positive refracting power. The first lens group consists only of one positive lens. During zooming from a wide angle end to a telephoto end, all the lens groups are moved in such a way that an interval between the first lens group and the second lens group increases, an interval between the second lens group and the third lens group decreases and an interval between the third lens group and the fourth lens group increases. At the same time, the third lens group and the fourth lens group are moved in a direction to the object side of the zoom lens. The zoom lens satisfies following conditional expressions: 5.0<f1/fw<9.5, −2.2<f2/fw<−1.2 and 0.4<f3/f4<1.5 (fw: a focal length of all zoom lens groups in a state of the wide angle end. F1: a focal length of the first lens group. F2: a focal length of the second lens group. F3: a focal length of the third lens group. F4: a focal length of the fourth lens group.). The zoom lens is suitable for a video camera or the like using a solid state image sensor or the like. The zoom lens is small and has a zoom factor about three times. In the zoom lens, an angle of field in the state of the wide angle end is 60 degrees or more and F number is about F2-F2.8. So, the zoom lens has an excellent image formation performance.
Moreover, Japanese Patent Publication No. 2005-181556 discloses a large caliber zoom lens that includes from an object side of the zoom lens sequentially as follows: a first lens group with a positive refracting power; a second lens group with a negative refracting power; a third lens group with a positive refracting power; and a fourth lens group with a positive refracting power. By a zooming, an interval between the first lens group and the second lens group extends, an interval between the second lens group and the third lens group narrows, and an interval between the third lens group and the fourth lens group narrows. The second lens group is moved to the object side of the zoom lens in a focusing. The lens satisfies following conditional expressions: (1) 0.5<f2/fW<1.0; (2) 0.5<f3/fT<2.0; (3) 0.5<f4/fW<2.0; (fW: a focal length of all optical systems in a wide angle end side. fT: the focal length of all optical systems in a telephoto side. f2: a focal length of the second lens group. f3: a focal length of the third lens group. f4: a focal length of the fourth lens group).
It is possible for the zoom lens disclosed in patent document 1 to correspond to the wide angle of field where the half field angle is about 38 degrees, but not to 2.5 or less in F number in a short focal end, and the first lens group is a thick structure. The 38 degrees in the half field angle corresponds to 28 mm of a focal length in a 35 mm silver bromide film camera, so-called Leica seal camera.
The zoom lenses disclosed in the patent documents 2 and 4 can correspond to the wide angle of field where the half field angle is 38 degrees or more, but can not correspond to 2.5 or less in F number of the short focal ends.
The zoom lens disclosed in above-mentioned patent document 3 can correspond to 2.5 or less in F number of the wide angle ends, but can not correspond to the wide angle of field where the half field angle is 38 degrees or more.


In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.

An example of prior art semiconductor memory device of this type is shown in FIG. 1. Its configuration will now be described with reference to the drawings.
FIG. 1 shows the structure of the prior art semiconductor memory device, e.g., dynamic RAM.
This semiconductor memory device has a power supply pad 1 for the ground potential (Vss), and a power supply pad 2 for the power supply potential (Vcc). Connected to the Vss and Vcc power supply pads 1 and 2 are power supply lines 3 and 4. Connected between the power supply lines 3 and 4, respective are a plurality of memory cell arrays 10-1 to 10-N. The number of the memory cell arrays 10-1 to 10-N is 8, for example, in the case of a 4 Mbit dynamic RAM. Both supply lines 3 and 4 include line resistance r.
Each of the memory cell arrays 10-1 to 10-N comprises a memory cell matrix 10a of 512 Kbits, for example, a sense amplifier group 10b, and a control circuit 10c for controlling the sense amplifiers 106. Although not illustrated, peripheral circuits, such as an input circuit for inputting a signal from the outside of the chip, an output circuit for outputting information of the memory cell to the outside, and a writing circuit for writing data from the outside into the memory cells are also connected to the Vss pad 1 and the Vcc pad 2.
In this semiconductor memory device, when a power supply voltage is supplied from the Vss pad 1 and the Vcc pad 2, the power supply voltage is applied via the power supply lines 3 and 4 to the memory cell arrays 10-1 to 10-N. Then the memory cell arrays 10-1 to 10-N operate, and accessing, i.e., data reading or data writing, is performed.
In this type of the semiconductor memory device, as the memory capacity is increased, e.g., up to several Mbits, the length of the conductor of the power supply lines (wiring conductors) 3 and 4 may be as long as several tens of millimeters, and the line resistance of the power supply lines 3 and 4 can be no longer neglected. The power supply lines 3 and 4 disposed from the Vss pad 1 and the Vcc pad 2 and along the memory cell arrays 10-1 to 10-N are therefore formed of a material having a low sheet resistance (such as aluminum) and their width is enlarged in order to reduce the resistance from the Vss pad 1 and the Vcc pad 2.
A specific example of a semiconductor memory device is shown in FIG. 2, and an example of the memory cell array in FIG. 2 is shown in FIG. 3. Identically labelled elements appearing in the different Figures refer to one in the same element.
As illustrated in FIG. 2, a plurality of memory cell arrays 10-1 to 10-N are connected between the power supply line 3 connected to the Vss pad 1 and the power supply line 4 connected to the Vcc pad 2. The sense amplifiers in each memory cell array 10-1 to 10-N are connected to the power supply line 3 via common nodes N1 supplying a sense latch signal SLN and sense amplifier drive n-channel MOS transistors (NMOS transistors) 11-1 to 11-N that are turned on and off by a control signal SN. The sense amplifiers in each memory cell array 10-1 to 10-N are connected to the power supply line 4 via common nodes N2 supplying a sense latch signal SLP and sense amplifier drive p-channel MOS transistors (PMOS transistors) 12-1 to 12-N which are turned on and off by a control signal SP.
Also connected to the Vss pad 1 and the Vcc pad 2 are a plurality of peripheral circuits 13-1 to 13-4 for controlling input and output of the semiconductor memory device.
The memory cell arrays 10-1 to 10-N are identical to each other, and one of them, the memory cell array 10-1 is taken up for further explanation with reference to FIG. 3.
The memory cell array 10-1 comprises a memory cell matrix 10a, a sense amplifier group 10b comprising a plurality of sense amplifiers 10b.sub.1 to 10b.sub.P and a control circuit 10c. The control circuit 10c comprises a plurality of word line drive circuits 30.sub.1 to 30.sub.Q, precharge circuits 31.sub.1 to 31.sub.P, transfer gates 32.sub.1 to 32.sub.P, and the like.
The memory cell matrix 10a comprises a plurality of word lines WL.sub.1 to WL.sub.Q, and a plurality of pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P, and memory cells 20.sub.11 to 20.sub.PQ connected at the intersections of the word lines and the bit lines. Each memory cell 20.sub.11 -20.sub.PQ includes a transistor 20a and a capacitor 20b. Connected to the bit line pairs BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P are sense amplifiers 10b.sub.1 to 10b.sub.P. The sense amplifiers 10b.sub.1 to 10b.sub.P are activated by the sense latch signals SLN and SLP on the common nodes N1 and N2, respectively, to detect and amplify the potential difference between each pair of bit lines, and is formed of two NMOS transistors 21a and 21b, and two PMOS transistors 21c and 21d.
The word line drive circuits 30.sub.1 to 30.sub.Q are connected to the word lines WL.sub.1 to WL.sub.Q. The word line drive circuits 30.sub.1 to 30.sub.Q respectively are responsive to the row decode selection signals XD.sub.1 to XD.sub.Q to vary the word lines WL.sub.1 to WL.sub.Q to the high level (Vcc) or to the low level (Vss). The precharge circuits 31.sub.1 to 31.sub.P are connected to the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P for precharging the corresponding pairs of the bit lines to a reference voltage VR responsive to a precharge signal EQ. The transfer gates 32.sub.1 to 32.sub.P are connected to the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P and are turned on and off by a column decode selection signal YD.sub.1 to YD.sub.P to transfer data on the corresponding pairs of bit lines to complementary data lines DB and DB.
FIG. 4 is a waveform diagram for explaining the operation of the circuit of FIG. 3. The operation of FIG. 2 and FIG. 3 will now be described with reference to FIG. 4.
Let us consider the operation of reading data "1" that is stored in the memory cell 20.sub.11 in FIG. 3.
In FIG. 4, the precharge signal EQ of the precharge circuits 31.sub.1 and 31.sub.P precharging the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P to the reference voltage VR (=1/2.multidot.Vcc) is lowered from the high level ("H") to the low level to put an end to the precharge. Then, the word line WL.sub.1 is raised to the high level by the word line drive circuit 30.sub.1 to which the column decode select signal XD.sub.1 is input. Then the data "1" in the memory cell 20.sub.11 is output to the bit line BL.sub.1, creating a slight potential difference between the pair of bit lines BL.sub.1, BL.sub.1.
After the word line WL.sub.1 is raised, the control signal SN is raised to the high level and the control signal SP is lowered to the low level. The sense amplifier drive NMOS transistor 11-1 and PMOS transistor 12-1 are turned on, and the sense latch signals SLN and SLP on the common nodes N1 and N2 precharged to the reference voltage VR, through a path not illustrated, are varied to the Vss level and the Vcc level, respectively, so that the sense amplifiers 10b.sub.1 to 10b.sub.p operate. When the sense amplifiers 10b.sub.1 to 10b.sub.p operate, a discharging current I.sub.1 (see FIG. 3) flows from the bit line BL.sub.1 as well as other bit lines BL.sub.2 to BL.sub.p, via the NMOS transistors 21a of the respective sense amplifiers 10b.sub.1 to 10b.sub.p, the common node N1, and the NMOS transistor 11-1 to the power supply line 3, and a charging current I.sub.2 (see FIG. 3) flows via the common node N2, and the PMOS transistor 21d to the bit lines BL.sub.1 to BL.sub.P through the PMOS transistor 12-1 from power supply line 4. By the sensing action of the sense amplifiers 10b.sub.1 to 10b.sub.p, slight potential differences on the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.p, BL.sub.p are detected and amplified.
After adequate amplification by the sense amplifiers 10b.sub.1 to 10b.sub.p, the column decode select signal YD.sub.1 is raised from the low level to the high level and the transfer gate 32.sub.1 is turned on, and the potential on the pair of the bit lines BL.sub.1 and BL.sub.1 is transferred to the data bus lines DB and DB. Data is thus read from the desired memory cell 20.sub.11.
In this type of semiconductor memory device, the sense latch signals SLN and SLP are made to operate in a higher speed in order to perform the sensing operation at a higher speed. This can be achieved by increasing the size of the NMOS transistors 11-1 to 11-N and the PMOS transistors 12-1 to 12-N, or the power supply lines 3 and 4 shown in FIG. 2, and the conductors for the common nodes N1 and N2 shown in FIG. 2 are made of metal (e.g., aluminum) having a lower sheet resistance to decrease the resistance.
The above memory device however is associated with the following problems.
(a) In a semiconductor memory device of a large capacity on the order of megabits, the power supply lines 3 and 4 may be as long as 15 mm and the line resistance cannot be neglected. For instance, when the power supply lines 3 and 4 are made of aluminum having a low sheet resistance, the sheet resistance is 0.06 .OMEGA. when the film thickness is 600 angstroms. If the conductor-length/conductor-width from the Vss pad 1 or the Vcc pad 2 to the farthest memory cell array 10-N or 10-1 is 15 mm/100 .mu.m, the line resistance will be 0.06 .OMEGA..times.15000/100=9 .OMEGA..
With such a line resistance r, differences are created in the power supply resistance from the Vss pad 1 or the Vcc pad 2 to the respective memory cell arrays 10-1 to 10-N, and differences are created in the operation margin between the memory cell arrays 10-1 to 10-N, and access delays and the like are also created.
(b) With the prior art semiconductor memory devices, it is possible to increase the speed of the sensing operation by enlarging the size of the sense amplifier drive NMOS transistors 11-1 to 11-N and PMOS transistors 12-1 to 12-N, or by using metal of a smaller sheet resistance for the power supply lines 3 and 4 and the conductors for the common nodes N1 and N2. However, increase of the sensing operation may be accompanied with the increase in the charging current I.sub.2 and discharging current I.sub.1, and substantial drop in the Vcc level on the power supply lines 4 and 3 or substantial rise in the Vss level. (See FIG. 4.) When this drop or rise occurs, it acts as a noise giving an adverse effect on the operation after the sense latch, causing access delay or varying the circuit threshold value. Specifically, reduction in the TTL margin of the initial-stage circuit provided in the peripheral circuits 13-1 to 13-4 and operating responsive to TTL level (transistor-transistor logic level) or the like may occur.
(c) A further problem is associated with the differences between in the line resistances for the respective memory cell arrays.
As illustrated in FIG. 2, line resistance r is present on the power supply lines 3 and 4, so the power supply resistances at the junctions with the memory cell arrays 10-1 to 10-N differ from each other. For instance, with respect to the memory cell array 10-1, the resistance of the power supply line 3 at the junction with the NMOS transistor 11-1 is small, and the resistance of the power supply line 4 at the junction with the PMOS transistor 12-1 is large. A large Vss noise is created in the vicinity of the Vss pad 1, and the Vcc noise in the vicinity of the Vcc pad 4 is small. In contrast, when the memory cell array 10-N is made to operate the Vss noise in the vicinity of the Vss pad 1 is small, and the Vcc noise in the vicinity of the Vcc pad 2 is large. As a result, the noises in the vicinities of the power supply pads 1 and 2 differ depending on which of the memory cell arrays 10-1 to 10-N is made to operate.
The noises are transmitted via the power supply pads 1 and 2 to the power supply lines 112 and 122 adversely affecting the peripheral circuits connected thereto. In particular, in the input initial-stage circuits receiving RAS (row address strobe), CAS (column address strobe), and other control signals of the TTL level (not shown), and operating on the TTL level, when the memory cell array 10-1 is made to operate, the Vss noise is large, so the high-level-side margin in the input initial-stage circuits declines. When the memory cell array 10-N is made to operate, the Vcc noise is large, so the low-level-side margins declines. Thus, depending on which of the memory cell arrays 10-1 to 10-N operates, the operation margin of the input initial-stage circuits occur may differ and decline, and, as a result, malfunctions of the peripheral circuits including the input initial-stage circuits can occur.

Semiconductor memory device being coupled by auxiliary power lines to a main power line


A decking plate is arranged on a cover plate over the open top of a U shaped channel, such that a through hole of the decking plate is positioned aligned over a cutout portion of the cover plate. A fixture is inserted through the through hole and the cutout portion. The fixture includes a head, a screw, a tube like portion and a protrusion. The cover plate and the decking plate are pinched and fixed together between the head and the protrusion of the feature. Thus, a positioned displacement of a attached plurality of plates can be prevented.

1. Field of the Invention
The present invention relates to fixtures and methods for fixing a plurality of plates, and more specifically, to a fixture and a method for fixing a plurality of plates each having a through hole in a stack.
2. Description of the Background Art
Conventionally, a U shaped groove, trough or channel 3 shown in FIG. 6 has been widely known for example as a drainage channel. A cover or a lid 2 is generally placed on the to of the U shaped groove or channel 3. When such a U shaped groove or channel 3 is arranged for example on a construction site, and vehicles are intended to pass thereover, a decking 1 is preferably placed on cover 2 for protection, as shown in FIG. 6. The provision of decking 1 ensures safety as a vehicle passes over U shaped groove 3.
However, as shown in FIG. 6, the above mentioned, decking 1 is often displaced from its proper position on cover 2 because it is simply placed loosely onto cover 2. Thus, decking 1 cannot fully exhibit its function of protecting cover 2. In addition, when decking 1 is made for example of resin and light in weight, it may possibly be lifted or taken away.

Fixture and method for fixing a plurality of plates


Apparatus 10 for detecting inadequate maintenance of a system 12 of an aircraft or other vehicle is provided. The apparatus comprises: computer readable medium or media 14 configured to store data 18 relating to operation or non-operation of the system 12 over a period of time; and a data processing unit 16 configured to evaluate the data to identify at least one event indicative of the inadequate maintenance of the system.

Devices and methods for performance- and health-monitoring of many types of systems are known. Such devices usually monitor a system by collecting data during the operation of the system and reporting the data to an operator of the system. Some devices evaluate such operational data to detect trends in the performance of the system and/or monitor "vital signs" of the system while the systems are operating, and report any abnormal conditions or trends to the operator.
The execution of periodic and preventative maintenance procedures is crucial to the proper operation of aircraft systems and to the long term health of such systems. The incorrect execution, or omission, of such procedures may cause premature wear and lead to system failures, particularly where, for example, such systems sit idle for relatively long periods of time. Conventional health monitoring systems and methods may detect the consequences of inadequate maintenance only by monitoring degradation or failure in system performance. Since inadequate maintenance may not have an immediate, noticeable effect on the performance or vital signs of the system, and since regular or protracted idle periods may not be monitored, or may otherwise go undetected, the effects of inadequate maintenance on a system may only be detected long after the fact. Hence, by the time any sign can be detected, inadequate maintenance of a system may have already led to costly consequences.
Improvement in detection of inadequate maintenance, and including for example periodic maintenance, is therefore desirable.

Apparatus for detecting inadequate maintenance of a system


Microparticles comprising a combination of an anticholinergic, a beta2-adrenoceptor agonist, and an inhaled corticosteroid are useful for the prevention and/or treatment of respiratory diseases.

Field of the Invention
The present invention relates to particles comprising three active ingredients for administration by inhalation. In particular, the present invention relates to microparticles comprising a combination of an anticholinergic, a beta2-adrenoceptor agonist, and an inhaled corticosteroid, processes for the preparation of such particles, and the use of such particles for the prevention and/or treatment of respiratory diseases.
Discussion of the Background
Respiratory diseases are a common and important cause of illness and death around the world. In fact, many people are affected by inflammatory and/or obstructive lung diseases, a category characterized by inflamed and easily collapsible airways, obstruction to airflow, problems of exhaling and frequent medical clinic visits and hospitalizations. Types of inflammatory and/or obstructive lung disease include asthma, bronchiectasis, bronchitis and chronic obstructive pulmonary disease (COPD).
In particular, chronic obstructive pulmonary disease (COPD) is a multi-component disease characterized by airflow limitation and airway inflammation. Exacerbations of COPD have a considerable impact on the quality of life, daily activities and general well-being of patients and are a great burden on the health system. Thus, the aims of COPD management include not only relieving symptoms and preventing disease progression but also preventing and treating exacerbations.
While available therapies improve clinical symptoms and decrease airway inflammation, they do not unequivocally slow long-term progression or address all disease components. With the burden of COPD continuing to increase, research into new and improved treatment strategies to optimize pharmacotherapy is ongoing.
Currently, there are several recommended classes of therapy for COPD, of which bronchodilators such as β2-agonists and anticholinergics are the mainstay of symptom management in mild and moderate disease, prescribed on an as-needed basis for mild COPD and as a maintenance therapy for moderate COPD.
Said bronchodilators are efficiently administered by inhalation, thus increasing the therapeutic index and reducing side effects of the active material.
For the treatment of more severe COPD, guidelines recommend the addition of inhaled corticosteroids (ICSs) to long-acting bronchodilator therapy. Combinations of therapies have been investigated with a view to their complementary modes of action enabling multiple components of the disease to be addressed. Data from recent clinical trials indicate that triple therapy, combining an anticholinergic with an ICS and a long-acting β2-agonist (LABA), may provide additional clinical benefits to those associated with each treatment alone in patients with moderate to severe COPD.
Furthermore, there is evidence suggesting synergistic actions of the LABA and ICS as long as both active ingredients are present at the same site of action, for example the small peripheral airways of the pulmonary tree. Without being limited by the theory, this might also occur if the anti-muscarinic drug is delivered at said site of action.
An interesting triple combination, presently under investigation, includes:
(i) formoterol, particularly its dihydrate fumarate salt (hereinafter indicated as FF), a long acting beta-2 adrenergic receptor agonist, currently used clinically in the treatment of bronchial asthma, COPD and related disorders;
(ii) rac-glycopyrronium bromide (hereinafter indicated as GB), an antimuscarinic drug recently approved for the maintenance treatment of COPD; and
(iii) beclometasone dipropionate (hereinafter indicated as BDP) a potent anti-inflammatory corticosteroid, available under a wide number of brands for the prophylaxis and/or treatment of asthma and other respiratory disorders.
On the other hand, current combined inhalation products may be subjected to a great variability in the dose delivery of each active ingredient, which in turn may be perpetuated as a function of product storage conditions.
Hence, it would be advantageous to provide combination-particles for inhalation, and a process of preparation thereof, that will allow all the three active ingredients to be delivered without significant dose variations.
Furthermore, there is still a need of an improved therapeutic control of patients exhibiting respiratory diseases affecting the small peripheral airways.
Therefore, it would highly be advantageous to provide combination-particles, and a process of preparation thereof, whereby all the three active ingredients could simultaneously reach the distal tract of the respiratory tree, and hence improving small airways outcomes and associated control.
In the prior art, different approaches have been proposed for preparing particles incorporating a combination of two or more active ingredients. For example, WO 02/28377, WO 2010/097188, and WO 2013/021199, all of which are incorporated herein by reference in their entireties, disclose particles incorporating, inter alia, a LABA and an ICS. However, none of said documents disclose particles incorporating a combination of formoterol salts, beclometasone dipropionate and glycopyrronium salts. Furthermore, they are all silent about the problem of reaching the distal tract of the respiratory tree.

This patent is subject to a terminal disclaimer.

Inhalation particles comprising a combination of an anticholinergic, a corticosteroid and a beta-adrenergic


A switch for a door or window has inner and outer handles which are both axially fixed to withdraw the locking element of any type of lock. The switch has an actuating shaft which extends between the inner and outer handles for withdrawing the locking element. The actuating shaft has overall dimensions which represent the only dimensions allowing the switch to fit into the lock. An actuating element associated with the inner handle is used to selectively set at least two states of operation of the outer handle. A transmission element inwardly linked to the actuating element extends between the inner and outer handles at least in an area of the actuating shaft that extends through the lock and within the limits of its overall dimensions. A coupling device associated to the outer handle is integrated as a closed unit into the outer handle for putting the outer handle in its selected state of operation, and in particular for selectively coupling or uncoupling the outer handle and the actuating shaft, so that the outer handle may swivel into all of its states of operation.

1. Field of the Invention
The invention relates to a changeover device for a door or window fitting and to a door, gate or window fitting having such a changeover device.
2. Description of the Prior Art
Door or window fittings with means for changing over between various operating states are known.
For example, turn and tilt fittings for windows are in widespread use, making it possible to open the window both about a vertical and about a horizontal axis of rotation or else keeping the window locked.
DE-B-11 13 649 discloses a door fitting, in which the door handle can be uncoupled from the associated lever spindle by means of a coupling. This fitting makes it possible, in one position of a coupling, to rotate the lever spindle and consequently open (or close) the door, whilst, in a second position, the door handle can be rotated freely, without the lever spindle rotating and without the door being able to be opened (or closed).
DE 78 20 998 U discloses a window fitting for swinging casement windows, in which a handle, rotatable in an escutcheon or a rose and having a boltlike integrally formed portion for engagement into a striking plate, is assigned a pushbutton-actuated blocking part, by means of which the handle can be prevented from being actuated.
In these and other known fittings, a changeover between the operating states takes place on that side of the fitting (that is to say of the door or window) on which the changeover also takes effect.
There are also known possibilities for selectively allowing or preventing the opening of a door from one side (outside) or from the other side (inside).
Not only conventional locks for locking a door by means of a key actuated lock bolt are generally known here, but also the locking devices of bathroom or WC doors, in which a detent bolt provided in addition to the spring-actuated snap bolt (of the latch) is pushed behind an associated striking plate via an internally arranged rotary grip (handle, knob), after which actuation of the external lever causes the snap bolt to be drawn back, but does not cause the door to open.
When a door is barred by means of a key, any passage through the door whenever the latter is to be kept barred involves a double actuation of the lock. This is too complicated in many instances occurring in practice, for example for authorities where there is usually public access, but in which admittance has to be controlled, or for stores, after they have closed, when there are still customers in the store and it must be possible for them to leave it. The more employees work in a room or section of a building, the more difficult this solution becomes in terms of organization and cost. Furthermore, "self-confinement" must be regarded as unfavorable from the point of view of protection of labor (the presence of nonbarred escape routes) and from considerations of work psychology.
Moreover, door openers have been known for a long time, particularly from the entrance areas of companies, authorities, etc., the functioning of these door openers being based on an electromechanically remote-controlled drawback of the abutment for the snap bolt in the door frame. The greatest disadvantage of this solution is that its execution, particularly in the form of retrofitting, necessitates a high outlay for electrical installation and, particularly in the case of safety doors, the modification of the frame.
German Utility Model 1,683,917 discloses a door handle which can be locked on one side and in which the external lever handle is inactivated as a result of the axial displacement of a projecting lever on the internal lever handle and the external lever handle is fixed in the inactive state. It is no longer possible for the door to operate idly in this operating state. However, since the user recognizes that the external lever handle is a handle for moving the door, this principle entails the risk of accidents on two counts, on the one hand because the absence of movability of the external lever handle in the inactive state is contrary to its visual appearance, on the other hand due to the axial displaceability of the adjusting lever relative to the door leaf, which leads to the risk of jamming.
German Patent Specification 670,268 describes a handle arrangement with two handles independent of one another and having a displaceable coupling member which, however, in order to be fitted, requires a modification of the lock. This arrangement is therefore scarcely suitable for retrofits.
U.S. Pat. No. 1,090,772 discloses a door locking arrangement, in which the changeover between the active/inactive operating states of the external handle is carried out by means of an axially displaceable internal handle. The result of the absence of axial fixing of the internal handle is that, when the internal handle is actuated, a change of state of the external handle may take place unintentionally. Moreover, this design entails a distinct risk of jamming, so that the arrangement does not meet current requirements relating to the protection of labor.
German Utility Model 72 16 046 discloses a mortise lock having two rotary grips (external/internal lever handle), with means which ensure that it is easier to unlock the door from outside by means of a key belonging to the lock. Here too, the changeover in operating states takes place as a result of an axial displacement of the internal handle, with the corresponding risks of accidents. Moreover, in order to provide the square perforation, the follower must have a dimension differing from the conventional dimension, in particular be widened subsequently, so that this arrangement, too, is somewhat unsuitable for retrofits.

Changeover device for a door or window fitting


The invention relates to DNA polymorphisms in sterol regulator element binding proteins (SREBP) that are characteristic of a higher risk of genetic diseases in humans such as hyperchlolesterolemia. The corresponding polymorphisms, especially the polymorphisms on SREBP-1 and SREBP-2 are frequently observed in Alzheimer patients (SREBP-2). They are also characterized by a specific behavior in the therapy of HIV patients with proteas inhibitors and appear to have an influence on the mortality.

In the last decades, epidemiological long term studies have identified numerous factors accelerating formation of atherosclerosis and thereby promoting development of cardiac infarctions. Despite of avoiding risk factors and of behavior increasing the risk of atherosclerosis, the development of pronounced atherosclerotic changes culminating in heart infarction can even be observed in young adults. In such cases, genetic factors play a decisive role. It is for example known that defects of genes playing an important role in cholesterol metabolism require medication with cholesterol lowering drugs. The early detection of a genetic defect allows that counter measures can be taken in time.
Therefore, it is desirable both from a diagnostic point of view and from a therapeutical point of view to be able to recognize and to detect crucial genetic alterations (see A. R. Miserez, Die Bedeutung genetischer Faktoren bei der Entstehung des Herzinfarkts, uni nova, April 1998, S. 44–52).
Cholesterol, besides being the precursor of steroid hormones and bile acids, is an essential constituent of the cell membrane decisively enhancing its permeability-barrier properties. Human cells control their intracellular cholesterol concentration tightly by regulating the receptor-mediated uptake of extracellular cholesterol-containing low density lipoproteins (LDL) and the intracellular cholesterol biosynthesis. LDL particles bind to the LDL receptor (LDLR) by their apolipoprotein (apo) B moieties. The binding and subsequent internalization of these lipoprotein-receptor complexes can be partially or completely abolished if one of the proteins involved in this process is defective or missing. Mutations of the genes encoding the apolipoprotein E (causing familial dysbetalipoproteinemia (FDL)), the apo B-100 (causing familial defective apo B (FDB)), and the LDL receptor (causing familial hypercholesterolemia (FH)) lead to an accumulation of cholesterol-containing particles in the plasma, which is associated with an increased risk of coronary artery disease. In most of the tested populations, said mutations can only explain 4.2 to 7% of cases with hypercholesterolemia (defined as the 10% of persons of a population with LDLC concentrations above the ninetieth percentile). Thus, the casual gene defects for the majority of affected people with increased plasma LDLC are not yet identified.
The promoters of the LDLR gene and of the genes involved in the cholesterol biosynthesis including the hydroxymethylglutaryl (HMG) CoA synthase, farnesyl-pyrophosphate synthase, and squalene synthase genes, contain specific nucleotide sequences, so-called sterol regulatory elements (SREs).
It is already known that two proteins, SRE-binding protein-(SREBP-) 1 and SREBP-2, bind the SREs in the promoters of these genes and activate their transcription rates. When cells are deprived of sterols, both proteins are activated by two proteolytic steps, first by a sterol-sensitive, and then by a cholesterol-independent step. These cleavage events release 68 kDa peptides from the NH2-terminal region of the SREBP-1 and -2 precursor proteins in the cytoplasm. The NH2-terminal, mature form of the transcription factors enters the nucleus and binds the SREs in the promoters of cholesterol-regulating genes. As a consequence, these genes are activated, thus leading to an increase in the receptor-mediated uptake of LDL as well as to an enhanced intracellular cholesterol biosynthesis.
When cholesterol accumulates in the cell, the first, cholesterol-sensitive cleavage event is inhibited, the mature forms of the SREBPs disappear and transcription rates decline, thereby preventing excessive accumulation of cholesterol in the cell. SREBP-1 and SREBP-2 regulate numerous SRE-containing genes involved in cholesterol homeostasis. In addition, SREBP-1 activates the HMG CoA reductase and the squalene synthase. SREBP-1 and SREBP-2 are members of the so-called basic helix-loop-helix leucine zipper transcription factor family. The genes encoding these factors have been cloned recently, and their genetic structures have been characterized (20,21).
Despite of the available knowledge, the percentage—as mentioned above—of identifiable risk patients for e.g. hypercholesterolemia is below 7%.
Therefore, the present invention had the aim to improve the early diagnosis and therapy of risk patients.
Said aim is achieved by providing diagnostic methods as well as polymorphisms in the SREBP genes which are suitable for the use in said diagnostic methods, in particular polymorphisms which are found in a fraction of patients with altered lipid metabolism, in particular cholesterol metabolism, preferably in a big fraction of such patients.


A method for forming an optimized communication connection providing enhanced performance of at least one application utilizing the communication connection is provided, the communication connection including a plurality of individual communication networks. The method includes the steps of: obtaining a set of performance requirements corresponding to the application utilizing the communication connection; obtaining real-time capacity information for each of a plurality of available channels associated with the respective individual communication networks; applying at least one policy-based management criteria to the available channels for controlling, in real-time, one or more aspects of the available channels; dynamically aggregating the individual communication networks to form the optimized communication connection, the communication connection leveraging one or more features and capabilities of at least a subset of the communication networks; and controlling real-time traffic scheduling across at least a subset of the available channels so as to adapt the communication connection to changes in network conditions and/or policy-based management criteria.

The Internet provides a platform for rapid and timely information exchange among a disparate array of clients and servers. Transmission control protocol (TCP) and Internet protocol (IP) are well-known separately designed and closely tied protocols that define rules of communication between end hosts, and are presently the most commonly used protocol suite for transferring data via the Internet. The combination of TCP/IP dominates modern communications over various networks, from a wired backbone to a heterogeneous network, due primarily to its simplicity and reliability. TCP has become the de facto standard used in most applications ranging from interactive sessions, such as, for example, hypertext transfer protocol (HTTP), to bulk data transfer, such as, for example, file transfer protocol (FTP). User Datagram Protocol (UDP) is used by many other applications, particularly Internet applications, requiring timely delivery of data. However, due at least in part to the lack of implicit acknowledgments, UDP cannot guarantee reliability, ordering or integrity of the data. Most multimedia streaming applications, as well as Voice over IP (VoIP), use the UDP protocol.
TCP was originally designed primarily for wired networks. In a wired network, random bit error rate (BER), a characteristic usually more pronounced in a wireless network environment, is negligible, and congestion is a main cause of packet loss. Emerging wireless applications, especially high-speed multimedia services and the advent of wireless IP communications carried by the Internet, call for calibration and sophisticated enhancement or modifications of this protocol suite for improved performance.
Based on the assumption that packet losses are indicative of network congestion, an additive increase/multiplicative decrease (AIMD) algorithm, which is a feedback control mechanism used in TCP congestion avoidance, reaches a steady state which reflects the protocol's efficiency in terms of throughput and link utilization. However, this assumption does not necessarily hold true when the end-to-end path also includes wireless links. Factors including, for example, high BER, unstable channel characteristics, and user mobility, may all contribute to packet losses.
Many studies have shown that an unmodified standard TCP performs poorly in a wireless communications environment due, at least in part, to its inability to distinguish packet losses caused by network congestion from those losses attributed to transmission errors. This phenomenon gets exacerbated for very lossy wireless connections such as, for example, satellite. Numerous modifications to TCP have been proposed to resolve, or at least alleviate, some of the issues with its original design. Unfortunately, however, conventional methodologies for addressing these issues have been, thus far, ineffective.
To be effective, modifications to TCP should to be applied on both ends of the communications (e.g., on the client side and on the server side). In practice, however, it is very rare to control both endpoints. As such, the concept of Performance Enhancing Proxies (PEPs) has been introduced. PEPs are introduced on both ends of a particular wireless connection and implement numerous alterations to TCP to improve the performance over a wireless segment, without requiring modifications to the client applications or servers. However, PEPs have at least two major limitations: first, they can only optimize one wireless connection at a time; and second, they break the end-to-end semantics of ingress and egress TCP connections. UDP complements TCP in terms of reliability. However, UDP does not detect congestion in the networks, nor does it retransmit lost packets. As a consequence, UDP performance is further degraded compared to TCP when used with lossy wireless networks. Furthermore, PEPs fail to optimize UDP because, unlike TCP, UDP does not establish a connection before sending application datagrams. Consequently, conventional means of addressing such wireless data communications problems have been insufficient.

Transparent proxy architecture for multi-path data connections