A label printer includes a thermal head, a keyboard unit for inputting label data including issuing number data determining the number of labels to be issued, a RAM for storing label data input by the keyboard unit, and a printing control circuit. The RAM at least first and second label data, and the printing control circuit performs a first label issuing operation in which the thermal head is driven to continuously print a label or labels according to the first label data read out from the RAM, interrupts the operation of the thermal head in response to an interrupt command input from the keyboard unit during the first label issuing operation and then changes the label issuing number data of the first label data stored in the RAM to indicate the number of remaining labels to be issued. The printing control circuit then performs a second label issuing operation in which the thermal head is driven to continuously print a label or labels according to the second label data, and then performs the first label issuing operation again after the second label issuing operation is completed.

1. Field of the Invention
This invention relates to a label printer.
2. Description of the Related Art
In the prior art, a label printer for issuing labels having characters and a bar code printed thereon is known. In a case where such labels are issued, printing format data and batch data are previously input into the label printer. The batch data includes label issuing number data and printing speed data in addition to printing data of characters and a bar code to be printed on the label. The printing format data includes various data for determining the coordinate position of the characters and bar code, the types of the characters and bar code, the magnified factor of the characters, and the density of the bar code. At the time of label issuing, the label printer continuously effects the printing operation and issues labels of the number determined by the label issuing number data.
When it is required to change the type of label in the label issuing operation and issue a different type of label, the different type of label may be issued after all the former type of labels are issued, for example. When it will take a long time to issue all the former type labels, or when it is required to issue the different type of label at once, then the operation of the former type of labels is forcedly interrupted.
In order to issue the different type of label, it is necessary to change the format data and batch data. In this case, since the format data and batch data of the former type of label are cleared when new format data and batch data are input, the former type of label cannot be continuously issued after the issuance of the different type of label is completed. For this reason, it is necessary to input the format data and batch data for the former type of label in order to issue the former type of labels additionally so that the required number of labels of the former type can be obtained.
Thus, the conventional label printer has the disadvantage that the operation becomes troublesome after issuance of one type of label is interrupted and a different type of label is issued.


A thin brick panel system and method of forming a thin brick wall includes an expanded polystyrene foam panel having a plurality of laterally extending channels formed therein for receiving a plurality of thin brick units. The thin brick units are bonded to the channels in the foam panel and the seams between adjacent bricks are filled with a mortar that bonds to the foam panel. The foam panel may be attached to a substrate with an adhesive as well as fasteners. Strips of a mesh fabric may span several panels to bind the panels together to form a structurally sound thin brick wall.

Architectural thin face brick, commonly referred to as "thin brick," is typically kiln-dried brick units that have height and width dimensions similar to those dimensions of conventional brick, but have a relatively small thickness. Thin brick systems are typically used as a decorative element to a new or existing architectural structure. These systems give structures the appearance of having "full" brick walls, while avoiding the associated expense. Many of these systems use a quick drying glue to adhere thin bricks to a foam panel. Mortar is then placed between the thin bricks to give the bricks structural integrity and to give the thin brick system the appearance of a full brick wall.
Problems have arisen in this art due to poor adhesion between the thin bricks and the foam panels. Prior thin brick systems have used various methods to increase the adhesive strength between the thin bricks and the foam panels. Some of these systems use foam panels with raised spacing members that form channels on the surface of the foam panels. The channels formed by the raised spacing members serve not only to align the thin bricks in a row, but also to snap into place and temporarily secure the thin bricks to the foam panel until mortar can be applied and dried. The height of the raised spacing members is less that the thickness of the thin bricks so that a small groove is formed on top of the raised spacing members and between the thin bricks. Mortar is applied to this area to secure the thin bricks into place.
One of the problems identified early on with these "friction-fit" or "snap-fit" systems is the limited surface area of the foam panels available for mortar bonding. That is, the mortar only makes contact with the tops of each laterally extending spacing member separating the thin bricks. This area of the foam panel is very small, and does not provide a strong bond between bricks and the panel. Due to natural elements and weathering, thin bricks of such systems may become unstuck from the foam panels, causing an uneven, warped brick surface. Further, in these systems very little force need be applied to crack the mortar and remove the thin bricks completely.
Some have tried to solve this problem by applying an adhesive to the brick to hold the brick to the foam panel. However, many strong adhesives disintegrate the polystyrene foam panel which is normally used in thin brick systems.
Thus it would be an advantage to provide a thin brick panel system that allows bonding of the mortar to the panel system without the need for additional structural support.
It would also be advantageous to provide a thin brick panel system which utilizes conventional adhesives to attach the brick to the panel system.
It would be another advantage to provide a panel system that prevents the brick and mortar attached thereto from being easily dislodged.
Moreover, it would be advantageous to provide a panel system that can readily utilize irregular shaped and/or sized thin bricks.
These and other advantages will become apparent from a reading of the following summary of the invention and description of the preferred embodiments in accordance with the principles of the present invention.

Panel for thin bricks and related systems and methods of use


A traction control device and method for a four-wheel drive electric vehicle are disclosed. When the drive wheels of an electric vehicle spin, a drive force of the electric vehicle is controlled so as to restrain the spinning of the drive wheels and to secure the starting performance and acceleration performance of the electric vehicle.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
In general, as one of the systems for improving the stability of a vehicle while driving, there is a traction control system (TCS), which controls drive force when the vehicle starts or accelerates suddenly and thus prevents slippage or spinning of the wheels of the vehicle.
Specifically, the TCS is a system that prevents slippage or spinning of the drive wheels when a vehicle starts or accelerates, thereby preventing poor traction of the vehicle and improving the starting performance and acceleration performance of the vehicle.
When the drive wheels of a vehicle slip or spin due to excessive drive force of the vehicle during starting or acceleration thereof, a conventional TCS controls the speed of the drive wheels by reducing the drive force (drive torque) of the vehicle.
However, we have discovered that when the TCS operates during travel of the vehicle, the drive force of the vehicle may be reduced, and thus the starting performance and acceleration performance of the vehicle may be deteriorated. In particular, while the vehicle is traveling uphill, the reduction in the drive force of the vehicle due to the operation of the TCS and the resultant deterioration in the starting performance and acceleration performance of the vehicle may cause a serious problem such as an accident.

Traction control device and method for four-wheel drive electric vehicle


A method for displaying statements of a computer program during an animation of the program's execution, the display using multiple colors to identify statements based on their respective frequency of execution, is disclosed. As a program statement becomes the current executed statement during the animation, the statement's frequency of execution is calculated as the number of times the statement has been executed so far during the animation, divided by the total number of statement executions throughout the animation. A display color is assigned based on whether the statement's execution frequency has reached one of two or more thresholds. The multi-hued display of program statements based on thresholds of execution frequency assists the programmer in understanding the operation of the program.

1. Technical Field
This invention relates to computer programming, and more particularly to displaying an animation of a computer program's execution.
2. Description of the Prior Art
A major challenge facing software testers is that of understanding the effect that test data has on a subject program. Techniques such as program animation bridge the gulf between the abstractness of test data and the idiomatic logic of an application under test, greatly enhancing the programmer's understanding of his or her program's operation. The programmer can then use this understanding to change the program's design to improve its performance.
Animation graphically displays the effect of executing one or more test cases for a computer program. The prior art in program animation may be categorized into two general areas: interpretive animation including SMALLTALK, ACTOR, etc., and executive animation such as in IBM's INSPECT FOR PL/I AND C/370 and PLITEST products which animate in "real time."
An interpretive animator uses an execution trace of a previously execution of the program as the source of its information about the program's execution. Interpretive animators are in control at all times, making possible such functions as reverse execution and path tracing. Duisberg, U.S. Pat. No. 4,821,220, entitled "System for Animating Program Operation and Displaying Time-based Relationships," discloses an interpretive-type animator for software objects. Duisberg's system uses time-based triggers to control a replay of an execution. In operation, the system records the original execution, saving time stamps at critical moments during the execution. Later, during replay, these time stamps are used to regulate and characterize the original program execution.
The program debuggers PLITEST, COBTEST and INSPECT of the International Business Machines Corporation (IBM), all are examples of executive animators. These products operate in real-time, and use color to highlight only the current focus of execution (i.e., the current executed statement or module) as displayed on a user's screen.
Algorithm animation is a distant cousin of interpretive and executive animation. Algorithm animators provide a scripted animation depicting a variety of classical programming data structures. These structures are animated so as to show traversal and data manipulation. Brown et al., U.S. Pat. No. 4,736,321, entitled "Communication Method Between an Interactive Language Processor Workspace and External Processes" is an example of an algorithm animator. Brown et al. disclose the invocation of an external process without having to suspend a currently executing process, passing arguments to an external process and receiving results therefrom in a currently executing APL workspace.
Saito et al., U.S. Pat. No. 4,730,315, entitled "Diagrammatic Method of Testing Program," discloses a method for correlating FORTRAN source code and a directed acyclic graph ("digraph") thereof in a step, edit, and retry interactive debug facility. Synchronism is preserved between the source code and the digraph by use of FORTRAN reserved words as pointers.
Beckett, U.S. Pat. No. 4,080,650, entitled "Facilitating Return From an On-line Debugging Program to a Target Program Breakpoint," discloses an interactive debug utility in which control is selectively passed from within one process to an external process and returned via breakpoints.
There is a need for animating the execution of a computer program in a manner which visually illustrates how the parts of a program respond to various test cases by identifying parts which reach certain user-selected thresholds during their execution.

Multi-color animation of computer program execution


A lithium ion battery electrode formed by the pyrolysis of a polycarbosilane followed by introducing lithium ions. These electrodes can be used to form batteries with large capacities, low irreversible capacity, high density and good safety behavior.

The present invention relates to a method of forming electrodes for rechargeable lithium ion batteries and the electrodes formed thereby. These electrodes can be used to form batteries with high capacities.
Lithium ion batteries are known in the art and are widely used as electric sources for lap top computers, cellular phones, camcorders and the like. They are advantageous in that they can provide high voltage, high energy density, small self-discharge, excellent long-term reliability and the like.
Rechargeable lithium ion batteries have a simple mechanism. During discharge, lithium ions are extracted from the anode and inserted into the cathode. On recharge, the reverse process occurs. The electrodes used in these batteries are very important and can have dramatic effects on the batteries' performance.
Positive electrodes known in the art for use in these rechargeable lithium ion batteries include metal chalcogenides, metal oxides, conductive polymers and the like. Negative electrodes (anodes) known in the art for use in rechargeable lithium ion batteries include compounds in which the lithium ion is incorporated into a crystal structure of inorganic materials such as WO.sub.2, Fe.sub.2 O.sub.3 and the like, and carbonaceous materials such as graphite and conductive polymers.
Properties which are desirable in electrode materials include 1) chemical inertness towards the other battery components such as the lithium ions, the electrolyte salts and the electrolyte medium; 2) the ability to store high quantities of lithium; 3) the ability to reversibly store or bind the lithium; 4) lithium storage that minimizes formation of metallic lithium clusters or agglomerates and, thus, minimizes safety concerns; and 5) a high density which allows for volume efficiency.
The electrodes to date, however, have not maximized these properties. For instance, while lithium metal provides the best electrode potential, large batteries constructed therewith have poor safety behavior. Likewise, while lithium alloys have reasonable electrode potentials and safety profiles, they often crack and fragment with the constant cycling of the battery.
The most desirable anode materials to date have been carbonaceous compounds such as graphite. Graphite is chemically inert, can bind reasonable amounts of lithium (cells with capacities of about 330 mAh/g of anode) with little being irreversible (about 10%), and it has a high density (about 2.2 g/cc.sup.2, although in the electrode the density is about 1.2 g/cc.sup.2). Cells with larger capacities, however, are often desired. References which discuss the use of graphite anodes include Dahn et al.; Science, 270, 590-3 (1995), Zheng et al., Chemistry of Materials, 8, 389-93 (1996); Xue et al.; J. of Electrochem. Soc., 142, 3668 (1995), Wilson et al.; Solid State Ionics, 74, 249-54 (1994), Wilson et al.; J. of Electrochem. Soc., 142, 326-32 (1995) and Xue et al.; J. of Electrochem. Soc., 142, 2927 (1995).
It has recently been suggested that the addition of boron, phosphorous or metals such as silicon to carbonaceous anodes can increase the capacity of the resultant batteries. Such batteries, however, have not achieved optimal results.
For instance, Tahara et al. in European publication 582,173 teach the use of a silicon oxide or a silicate as the negative electrode in a lithium ion battery. Similarly, Dahn et al. in European publication 685,896 teach the use of SiC containing materials as anodes in lithium ion batteries. These references, however, do not teach the methods claimed herein.
The present inventors have now discovered that lithium ion batteries containing electrodes made from preceramic polycarbosilanes can have many desirable properties heretofore unobtainable. For instance, such batteries can have large capacities with low irreversible capacity. In addition, these anode materials are chemically inert towards the other battery components, they minimize the agglomeration of lithium and they have a high density. Finally, these materials can be designed to have low hysteresis or a larger hysteresis. The Applicants herein postulate that the hysteresis of these materials may be valuable since it may reduce reaction rates between intercalated lithium and electrolyte under thermal abuse.

Method of forming electrodes for lithium ion batteries using polycarbosilanes


An electrical drive includes a housing mounted on a crank axle for partially receiving the axle. A driven ratchet base is rotatably mounted on a first end portion of the crank axle and includes a first end portion fixedly engaged with a chain wheel and a second end portion formed with a driven bevel gear. A drive bevel gear meshes with the driven bevel gear for rotating the driven ratchet base. A drive ratchet base is rotatably mounted on a mediate portion of the crank axle and includes a first end portion engaged with the second end portion of the driven ratchet base for rotating the driven ratchet base along one direction only, and a second end portion formed with a first engaging bevel gear. A ring element is fixedly mounted on the mediate portion of the crank axle to rotate therewith, and two pivot axles each extend from an outer wall of the ring element and each have a second engaging bevel gear rotatably mounted and meshing with the first engaging bevel gear. A retaining bevel gear meshes with each of the two second engaging bevel gears and is fixedly retained by an inner wall of the housing.

A conventional electrical drive can output a determined amount of power supply to co-operate with physical pedaling of a rider so as to drive a bicycle synchronously, thereby providing an auxiliary function to displace the bicycle. However, the conventional electric drive cannot precisely control power and voltages required for moving the bicycle, thereby easily causing a waste of power supply.
The present invention has arisen to mitigate and/or obviate disadvantages of the conventional electrical drive.


A method of apparatus for automatic page orientation of a scanned image which compares the number of character ascending pixels to the number of character descending pixels in the image to determine if the image is properly aligned or is 90.degree. or 180.degree. out of orientation. The method and apparatus includes morphologically processing the bitmap of the scanned image using structuring elements for isolating the character ascenders and descenders. When page orientation is improper, the bitmap image of the scanned image is rotated to correct the misalignment.

1. Field of the Invention
The present invention relates to improvements in methods and apparatuses for image processing, and more particularly to an improved method and apparatus for automatically determining and correcting the orientation of an image for document processing, specifically for determining and correcting the orientation of an image of a document that is 90.degree. or 180.degree. out of alignment.
2. Background and References
The present invention has wide applications in document image processing, both in traditional optical character recognition processing, and in scanned image processing, as well. In optical character recognition (OCR) systems, typically a bitmap representation of an image is accepted as an input, generally created by an optical scanner. In the operation of such systems, a user usually feeds the page or pages to be scanned into the document scanner by hand. However, a serious and common problem often occurs when the user feeds the pages in the wrong orientation, for example, with the top of the image on the document rotated either 90.degree. (clockwise or counter-clockwise) or 180.degree. (upside down) with respect to the expected orientation of the characters on the page.
Present day commercial OCR systems do not typically check for such a misorientation condition. Instead, they proceed to process the document as normal, by segmenting the page and sending bitmaps of the individual characters to the character classifier module. As the bitmaps are rotated from the expected orientation, the results are poor. Few characters are usually identified at all, and the characters that are identified are generally incorrectly classified. In addition, a long time is required to determine the bad results, since the patterns are unfamiliar to the classifier, and the classifier typically tries several subroutines that are slow and not expected to be run often. Finally, no warning is given to the user that the results are bad.
U.S. Pat. No. 2,905,927 to Reed describes a method and apparatus for recognizing words that employs three scans to determine the characteristics or pattern of the word to be identified. The upper scan obtains information indicating the number and position of full-height symbols and the lower scan derives information indicative of symbols extending below the base line. The center scan acquires information relative to the number of symbols in the word and the symbol spacing.
U.S. Pat. No. 4,953,230 to Kurose describes a system for processing and correcting the skew of a document image that scans the document and determines the location of a first appearing black pixel. Thereafter in subsequent contiguous scans when no black pixels are detected in a scan, it is determined that the right-hand end of the character line has been found. A mathematical determination of the skew of the document is determined using the line numbers and widths of the character lines in order to find the skew or slope of the character lines in reference to the horizontal (or vertical) scanning.
U.S. Pat. No. 4,723,297 to Postl describes a method for automatic correction of character skew in the acquisition of a text original. The text original is in the form of digital scan results, and the method contains an "identification of skewed position" step and an "electronic rotation" step. The identification of skewed position can be determined by the search scan method or the search sweep method. The search scan method of skew determination involves summing and comparing the scan results between scanned search lines beginning with Y=O on an XY plane. The search sweep method of skew determination utilizes Fourier transforms for summation of scanned regions. An angle, .alpha., is established in either skew determination step and electronic rotation of the scanned image provides correct image alignment.
U.S. Pat. No. 4,926,490 to Mano describes a method and apparatus for recognizing characters on a document, even if the document is skewed or not aligned with the axis of a typical segmentation apparatus, such as a scanner. A plurality of rectangles are formed surrounding respective character images, with position data for each rectangle stored in a first table in which plural position data of the rectangles are arranged in order from the left-most rectangle to the right-most rectangle in the X direction of the XY coordinates of the image buffer. By determining the rectangles belonging to one character row in the first list and calculating the positions of the bottom left corners of the rectangles, skew of the document is calculated. Vertical positions of the rectangles compensated by the skew in the Y direction are calculated to transfer the position data of the rectangles belonging to the first character row to a second table. The image data surrounded by the rectangles specified by the position data in the second list are sequentially supplied to a character recognition unit.


It is an object of the present invention to provide an improved noise removal device having an improved noise removal precision. A second noise extracting unit extracts a noise of an IF signal, and outputs a second noise signal which is then smoothed by a second noise smoothing unit to produce a second noise-smoothed signal. A noise hold control signal generating unit compares the second noise-smoothed signal with the second noise signal to produce a noise hold control signal indicating an occurring position and an occurring period of the noise of the IF signal. A first noise extracting unit extracts a noise of an FM detection signal, and outputs a first noise signal. A noise hold unit holds the first noise signal in accordance with the noise hold control signal to produce a held noise signal which is then smoothed by a first noise smoothing unit to produce a first noise-smoothed signal. A hold control signal generating unit compares the first noise-smoothed signal with the first noise signal to produce a hold control signal indicating an occurring position and an occurring period of the noise of the FM detection signal. Subsequently, a hold unit operates to hold the FM detection signal in accordance with the hold control signal, thereby generating and thus outputting an FM detection signal not containing any noise.

The present invention relates to a noise removal device for removing a noise mixed in a signal.
The present application claims priority from Japanese Application No. 2005-091876, the disclosure of which is incorporated herein by reference.
Generally, when an electronic device processes a signal, it is important to remove a noise from the signal.
For example, in a conventional FM radio receiver disclosed in Japanese Unexamined Patent Application Publication No. 10-75190, as shown in FIG. 1 of the patent application, a noise removal device is used to remove a noise which occurs once an over-modulated FM wave is FM-detected, and a signal processing such as a stereo demodulation is performed based on an FM detection signal (a composite signal) aimed at noise reduction.
Further, in a conventional vehicle radio receiver mounted on an automobile, a noise removal device is used to remove a noise such as an ignition noise mixed in an FM detection signal generated from an electronic device, and a signal processing such as a stereo demodulation is performed based on an FM detection signal aimed at noise reduction.
Now, with reference to FIG. 1 which is a block diagram and FIG. 2 which is a waveform chart, description will be given to explain the composition of a conventional and commonly used noise removal device provided in a vehicle radio receiver, also to explain a noise removal method. As shown, the conventional noise removal device comprises: a main path including a delay circuit 1 and a hold circuit 2; and a control path including a high pass filter 3, a smoothing circuit 4, a comparator 5, and a hold period adjusting circuit 6.
Once there is an input of an FM detection signal Sin containing a pulse-like noise Nz shown in FIG. 2(a), the high pass filter 3 in the control path will operate to inhibit certain signal component of the FM detection signal Sin, but allow the passing of the Noise Nz therethrough. Then, as shown in FIG. 2(b), a noise component Snz passed therethrough is smoothed by the smoothing circuit 4 to produce a smoothed DC signal Sdc which is used as a threshold value by the comparator 5 when the comparator 5 compares the DC signal Sdc with a noise component Snz, thereby generating a period detection signal Spd indicating an occurring period of the noise Nz shown in FIG. 2(c). Afterwards, the hold period adjusting circuit 6 will operate to finely adjust a time width of the period detection signal Spd in accordance with a predetermined fixed time, thereby generating a hold control signal Sh which is supplied to the hold circuit 2. On the other hand, with regard to the main path of the noise removal device, the delay circuit 1 will operate to make the FM detection signal Sin synchronized with the delay time of the control path before the FM detection signal Sin is inputted into the hold circuit 2. Then, as shown in FIG. 2(d), the hold circuit 2 will operate in synchronism with the hold control signal Sh to hold the noise Nz mixed in the FM detection signal Sin, thereby generating and thus outputting a noise-reduced FM detection signal Sout.
Thus, the conventional noise removal device is used to detect an accruing period of the noise Nz mixed in the FM detection signal Sin shown in FIG. 2(a), so as to generate the hold control signal Sh, and then, as shown in FIG. 2(d), to hold the Noise Nz in synchronism with the hold control signal Sh, thereby generating an FM detection signal Sout whose noise Nz has been reduced.
Moreover, the conventional FM radio receiver disclosed in Japanese Unexamined Patent Application Publication No. 10-75190 is used to extract a noise from an FM detection signal and then smoothen the extracted noise so as to produce a smoothed signal. Meanwhile, the smoothed signal is compared with the foregoing noise so as to generate a hold control signal indicating a noise occurring period. Then, the noise is held in synchronism with the hold control signal to generate a noise-reduced FM detection signal.
However, with regard to the noise removal devices provided in the aforementioned vehicle radio receiver and the FM radio receiver disclosed in Japanese Unexamined Patent Application Publication No. 10-75190, as shown in FIG. 2(b), a smoothed signal Sdc containing a smoothed noise occurred during a relatively long period is compared with each noise component to generate a hold control signal Sh in a manner such that a period during which a noise component Snz having a larger amplitude than the smoothed signal Sdc occurs will serve as a hold period. However, since the level (amplitude) of the smoothed signal Sdc will change in response to a change in the occurring density and the amplitude of the noise Nz, it was difficult to precisely detect the occurring period of each noise Nz.
Namely, as far as its nature is concerned, a noise is not something that occurs at certain density in time (in other words, frequency). In fact, each noise also changes independently from time to time in its intensity (amplitude) and waveform. For this reason, when the comparator 5 operates to detect an occurring period of a pulse-like noise occurring at certain instant in time, since it detects such an occurring period using a smoothed signal having a constant amplitude as a threshold value while being affected by the intensity and density of other noises occurring in a relatively long period, a change in the threshold level due to an influence from other noises makes it difficult to precisely detect the occurring period of the pulse-like noise, resulting in a problem that once a noise signal is held by the hold circuit 2, the noise will still be mixed in the FM detection signal Sout and this can cause part of the detection signal missing.


A security system for software to be input to a closed internal network includes: a kiosk including a registration module configured to read the stored software of a connected portable storage medium, a vaccine module configured to detect malicious code in the software, and an authentication module configured to set inspection authentication for the portable storage medium whose software has been inspected for malicious code; and a client including a check module configured to check the portable storage medium for inspection authentication and authorize the execution of the stored software.

The present invention relates to a SECURITY SYSTEM AND METHOD FOR SOFTWARE TO BE INPUT TO A CLOSED INTERNAL NETWORK, which block the input and installation of software infected with malicious code to and in an internal network through an external network, thereby establishing a safe security environment for the internal network.
Government offices of government agencies, local governments, etc. and various enterprises and research institutes that require security (hereinafter referred to as the "security group") have built closed internal networks that are blocked from external networks such as the Internet in order to prevent the unauthorized leakage of their own data and to protect the constituent PCs and server of the security group.
Advanced security technology blocks direct penetration into an internal network through an external network, and thus existing malicious code technology has limitations in terms of the attack on the internal network. Due to this, unauthorized data leakage from internal networks and the infection rate of internal networks have significantly decreased.
However, with the development of security technology, hacking technology and infection routes are diversified, and thus attacks on software developers having relatively weak security have increased. Software developers develop software such as source codes and programs, update files, and patches to be installed in internal networks, and input the software to the internal networks according to designated paths.
In a communication environment between a software developer and an internal network, a hacker penetrates the network of the software developer, and modifies software to be transmitted to the internal network or inserts new software for malicious purposes, or a hacker accesses a separate server distributing software and changes software to be installed on the internal network. For reference, typical attack methods include the alteration of build/update infrastructure, alteration through the leakage of a certificate or development account, the alteration of hardware or firmware, and the sales of an online product infected with malicious code.
The software of the software developer infected and altered (hereinafter referred to as "infected") by the hacker is installed on the server and PCs of the internal network, and then leaks the data of the internal network without permission or damages the server so that it cannot perform its functions.
As a result, there is an urgent need for security technology that can completely block the online connection between an internal network and an external network and neutralize the malicious code of software to be input to the internal network, thereby establishing a safe software installation environment.
Prior art document 1: Korean Patent Application Publication No. 10-2002-0031500 (published on Feb. 5, 2002)

Security system and method for software to be input to a closed internal network


The present disclosure relates to crystalline solid forms of a stimulator of soluble guanylate cyclase (sGC), Compound I:

sGC is the primary receptor for NO in vivo. sGC can be activated via both NO-dependent and NO-independent mechanisms. In response to this activation, sGC converts Guanosine-5′-triphosphate (GTP) into the secondary messenger cGMP. The increased level of cGMP, in turn, modulates the activity of downstream effectors including protein kinases, phosphodiesterases (PDEs) and ion channels.
In the body, NO is synthesized from arginine and oxygen by various nitric oxide synthase (NOS) enzymes and by sequential reduction of inorganic nitrate. Three distinct isoforms of NOS have been identified: inducible NOS (iNOS or NOS II) found in activated macrophage cells; constitutive neuronal NOS (nNOS or NOS I), involved in neurotransmission and long term potentiation; and constitutive endothelial NOS (eNOS or NOS III) which regulates smooth muscle relaxation and blood pressure. Experimental and clinical evidence indicates that reduced concentrations or bioavailability of NO and/or diminished responsiveness to endogenously produced NO contributes to the development of disease.
NO-independent, heme-dependent sGC stimulators, have shown several important differentiating characteristics, when compared to sGC activators, including crucial dependency on the presence of the reduced prosthetic heme moiety for their activity, strong synergistic enzyme activation when combined with NO and stimulation of the synthesis of cGMP by direct stimulation of sGC, independent of NO. The benzylindazole compound YC-1 was the first sGC stimulator to be identified. Additional sGC stimulators with improved potency and specificity for sGC have since been developed.
Compounds that stimulate sGC in an NO-independent manner offer considerable advantages over other current alternative therapies that target the aberrant NO pathway. There is a need to develop novel, well-characterized stimulators of sGC. Compound I is an sGC stimulator that has demonstrated efficacy for the treatment of a number of NO related disorders in preclinical models. Compound I was previously described in WO2014144100, Example 1, as a light orange solid. Compound I may be present in various crystalline forms and may also form several pharmaceutically acceptable salts.
The properties of a solid relevant to its efficacy as a drug can be dependent on the form of the solid. For example, in a drug substance, variation in the solid form can lead to differences in properties such as solubility and dissolution rate, surface properties (e.g., wettability), powder properties (flow, cohesion, bulk density, mixing behavior, compressibility, static, etc.), tablet properties (hardness, homogeneity, friability, disintegration, stability to heat and humidity, etc.), oral absorption, bioavailability, storage properties (caking, hygroscopicity), toxicology results and clinical trial results.
Characterization of polymorphs is useful in preventing certain problems from arising during clinical trials and/or commercialization of drugs, for instance, to avoid inconsistency of drug substance and products (e.g. inconsistencies from lot to lot), hydration or dehydration of hydrates, chemical degradation, amorphization or polymorphic transformation in drug product. A polymorph might also be preferred if it improves the solubility and/or bioavailability compared to another polymorph of the compound or to its amorphous form. It might also be preferred because it imparts increased physical or chemical stability, it provides a higher melting point (leading to improved mechanical properties), it has more acceptable taste or smell, or more neutral pH, and so on.

This patent is subject to a terminal disclaimer.

Abstract: Also provided herein are methods for the preparation of these solid forms. The invention also relates to pharmaceutical formulations and dosage forms comprising these solid forms and their uses thereof, alone or in combination with one or more additional agents, for treating and/or preventing various diseases or disorders; these diseases or disorders are ones that may benefit from sGC stimulation or from an increase in the concentration of nitric oxide (NO) and/or cyclic guanosine monophosphate (cGMP).


Disclosed is a routing apparatus for obtaining routing data conforming to a destination address of a packet that arrives from a line, adding the routing data onto the packet, and switching the packet based upon the routing data to send the packet to a prescribed line. The routing apparatus has a main controller equipped with content addressable memories (CAMs) corresponding to respective ones of line speed. When search key data with an attached line identifier is received from a line card, routing data is generated by the content addressable memory (CAM) corresponding to the line speed and the routing data is sent to the line card. The line card adds routing data of which it has been notified by the main controller onto a packet and then outputs the packet. A switch to which a packet having attached routing data is input from a prescribed line card switches the packet based upon the routing data and sends the packet to another line card.

This invention relates to a routing apparatus that uses a CAM (Content Addressable Memory) when routing is performed in a network such as the Internet or ATM network. More particularly, the invention relates to a routing apparatus for obtaining routing data, which conforms to the destination address of a packet that arrives from a line, from a CAM, adding the routing data onto the packet, and switching the packet based upon this routing data to send the packet to a prescribed line.
The processing speeds of routers and ATM switches is increasing with the explosive spread of the Internet and ATM networks. Owing to lines packed in higher densities, tables for searching data (routing data) necessary for routing and switching are increasing in capacity.
Methods of searching routing data rely upon conventional processing technology using a CAM. However, an increase in the capacity CAMs is accompanied by the need for a large number of CAMs if the CAMs are of the usual capacity. It is difficult to package all the CAMs on an ordinary LSI chip. Therefore, a CAM of large capacity is recently available on the market as a special-purpose LSI chip.
FIG. 15 is a block diagram illustrating the general structure of a router according to the prior art. This will be used to describe an overview of a search method using a CAM in an ordinary router. The router has a main controller (CPU) 1, a switch 2 and line cards 31˜3n, 41˜4n provided between lines and the switch 2. Data transmission over a line generally is transmission using POS (Packet over SONET or Packet over SONET). With POS, an IP packet is mapped to an SDH or SONET payload and then transmitted. Line terminators (not shown) separate IP packets from the POS lines and input the IP packets to line cards 31˜3n. A packet processor 3a in each of the line cards 31˜3n extracts the destination address of the IP packet, acquires routing data conforming to the destination address from a CAM 3b, adds the routing address onto the packet and inputs the packet to the switch 2. On the basis of routing data attached to packets which enter from the line cards 31˜3n, the switch 2 switches these packets and inputs them to different line cards 41˜4n. Packet processors in the line cards 31˜3n remove the routing data from the packets, subsequently map the packets to the payloads of SDH or SONET frames and send the packets to POS lines.
FIG. 16 is a block diagram of a line card illustrating the CAM 3b as being separated into a CAM LSI chip 3b1 and an associative memory 3b2. FIG. 17 is a flowchart of a CAM search. A key-data memory (not shown) of the CAM LSI chip 3b1 stores key data conforming to a number of destination addresses, and the associative memory 3b2 stores routing data. The IP header of an IP packet has a destination address DA (destination address=IP address). When the IP packet enters the packet processor 3a of any of the line cards 31˜3n (step 101), therefore, the destination address DA is extracted (step 102) from the IP packet that has entered and the destination address is transferred as key data to the CAM 3b, which has a conversion table, in advance. The CAM LSI chip 3b1 of the CAM 3b checks to determine whether an IP address corresponding to this key data exists in the key-data memory. If the IP address exists, the CAM LSI chip 3b1 converts this key data to an address of the associative memory 3b2 and sends the latter to the associative memory 3b2 (step 103). The associative memory 3b2, which is constituted by a RAM, outputs preset associative data, e.g., a highway number HW-No. that is necessary for switching, based upon the entered address. Immediately before outputting the IP packet, the packet processor 3a adds this highway number HW-No. onto the packet and then inputs the packet to the switch 2. The latter performs routing (step 104) using the highway number HW-No.
FIG. 18 is a block diagram showing the details of the conventional router. Components in FIG. 18 identical with those shown in FIGS. 15 to 17 are designated by like reference characters. Main controllers 1, 1′ are redundant in order to improve reliability and are identically constructed. Specifically, the main controllers 1, 1′ respectively include: (1) main processors (MPU) 1a, 1a′; (2) main memories (MM) 1b, 1b′; (3) cache memories (not shown); (4) MPU bus conversion bridges 1c, 1c′ for connecting various devices such as input/output units and a CAM to the MPU; (5) output-port search CAMs 1d, 1d′ for when the main controller performs communication with the neighboring router; (6) Ethernet switching hubs 1e, 1e′ for transferring routing tables created by the main controller to each of the line cards 31˜3n via the switch 2 on separate lines; and (7) MPU bus conversion bridges 1f, 1f′ for sending the MPU packets addressed to this router that arrive from the line cards via the switch.
The line cards 31˜3n accommodate various lines such as SONET or SDH lines and are identically constructed. The speeds of the lines accommodated by each line card are the same but the line speeds differ from one card to another. The packet processor 3a (1) extracts the destination address DA of a packet that arrives via a POS line or the like and sends this destination address DA to the CAM as key data for searching routing data; (2) adds the routing data (highway number HW-No.) onto the packet and sends the packet to the switch; and (3) removes routing data from a switched packet and sends the packet to a line. The CAM 3b has the CAM LSI chip and associative memory (see FIG. 16) and obtains routing data (highway number HW-No.) from the destination address DA that has entered as key data. The CAM 3b executes the reverse of this operation as well. A LAN controller (LANC) 3c receives routing data by communicating with switching hubs 1e, 1e′ of the main controllers. A local MPU 3d controls the LAN controller 3c and controls the configuration internally of the line card.
The switch 2 controls the exchange of packets between the line cards and the main controllers 1, 1′ and controls the exchange of packets between the line cards.
FIG. 19 is an explanatory view illustrating the flow of packets in the conventional router.
1) A data packet that has entered from a POS line is separated into packets by the input section of a line card 3. It should be noted that PPP in FIG. 19 signifies Point-to-Point Protocol.
2) On the basis of the IP destination address DA in the packet header, the packet processor 3a searches the CAM 3b for a highway number HW-No. and other necessary information (QOS information, filtering information, etc.), adds the HW-No. and other information onto the packet (the payload portion thereof) and transfers the packet to the switch 2.
3) The switch 2 switches the packet based upon the routing data HW-No. and other information and inputs the packet to a line card 4 on the egress side. A packet processor 4a in the line card 4 removes the routing data HW-No. and other information from the packet that enters from the switch.
4) The packet processor 4a finally maps the packet to the payload of an SDH or SONET frame and sends the packet to a POS line. This completes routing processing in its entirety.
FIG. 20 is a diagram illustrating the internal structure of the CAM LSI chip. The CAM LSI 3b1 has an address decoder 5a, a memory array 5b, an index register 5c, a mask register 5d, a response register 5e and a priority encoder 5f.
The address decoder 5a decodes address data and stores separately input key data at a prescribed address of the memory array 5b or reads key data out of the memory array 5b and outputs the same. The memory array 5b stores key data conforming to the number of destination addresses, and the index register 5c stores key data desired to be searched (i.e., search key data), e.g., key data conforming to the destination address of a packet received from a POS line. The mask register 5d specifies the bit position to be masked in the search key data (masking is performed by logical "1"). The response register 5e stores (1) the result of performing matching (comparison) between key data, which has been stored in the memory array 5b, and search key data or (2) the result of performing matching between key data, which has been stored in the memory array 5b, and the non-masked portion of the search key data. The priority encoder 5f generates an address of the associative memory 3b2 based upon the result of matching from the response register 5e. The associative memory 3b2 outputs associative data (routing data and other information) from the entered address.
The key data shown in FIG. 20 is indicated as being 8-bit data for the sake of explanation; 32-bit data, etc., is employed in actuality. Further, the memory array 5b is illustrated as storing eight items of key data, though the memory array 5b actually has enough capacity to store a great many items of key data. Further, the memory array 5b within the CAM is so adapted that bit width can be varied in dependence upon the application of the CAM search, and the memory array has a register (not shown) for changing the configuration of the memory array. With regard to the associative memory 3b2, however, the bit width of the associative addresses and associative data is fixed at the hardware-design stage.
The following problems arise with the conventional routing apparatus (router) using the CAM:
1) High Cost of the CAM LSI Chip
The number of CAM entries is increasing as use of the Internet becomes more widespread. The number of entries that can be processed per CAM LSI chip is 64,000 at most if it is assumed that 36 bits per entry are required. Here 36 is the total of 32 bits required as the destination address in IP-V4 (IP Version 4) and four bits serving as control bits.
2) High Mounting Surface Occupancy of CMI LSI Chips
If it is assumed that 15 CAM LSI chips (4×4 cm in size) are required to be mounted, a high mounting surface occupancy is the result. This requires that the line card have a complicated structure, such as a two-tier structure.
3) Transfer Time of Routing Tables
It is necessary to transfer routing tables to each of the line cards from the main processor of the main controller that performs centralized administration of routing tables. For example, when the system is started up, it is necessary to transfer a routing table from the main processor of the main controller to the CAM mounted on each line card. As a consequence, system start-up takes considerable time and so does recovery at the time of failure.
4) Changing Bit Width of Associative Data
The construction of a CAM is such that the associative memory constituted by a RAM is externally mounted on the CAM LSI. Consequently, if key data is changed from IP-V4 to IP-V6 (4 bytes to 16 bytes), it becomes necessary to change the circuit configuration of the hardware and the line card must be redesigned.
5) Multiple Hits in Key Data
Since the conventional CAM does not possess a statistical processing function, the CAM cannot execute statistical processing at the time of multiple hits, namely when there are multiple items of entry key data for search key data. Consequently, it is required that the MPU of the main controller calculate statistical information by program processing using the main memory (MM), which results in a large head of the MPU.
6) Relationship Between Line Speed and CAM
In the conventional router, a CAM is mounted on a line card and the line card accommodates a plurality of lines of the same speed (an example of mounting is OC-12 lines×4). The reason for this is that in an arrangement in which a line card accommodates lines having different speeds, costs rise because all of the line cards will require a costly CAM of maximal speed. However, with the router of the conventional arrangement in which each card accommodates lines having the same speed, it is required to provide a line card that conforms to each line speed. Depending upon the network, there will be line cards that cannot be used and situations will arise in which the lines accommodated by line cards are too few in number. In other words, the conventional routing apparatus is such that the line cards have a poor line accommodating efficiency, and the apparatus is high is cost.


A communication control device for a user station. The communication control device controls a communication of the user station with at least one other user station of the bus system, and generates a transmission signal for transmission onto a bus and/or receives a signal from the bus. The communication control device generates the transmission signal according to a frame in which bits having a predetermined temporal length are provided. The communication control device generates the transmission signal so that its bits may be transmitted bus as a dominant state or a recessive state, so that the recessive state is overwritable by the dominant state. The communication control device shortens in the transmission signal at least one bit, which is to be transmitted as the dominant state, by a predetermined value in comparison to a bit that is to be transmitted onto the bus as the recessive state.

Bus systems for the communication between sensors and control units, for example in vehicles, are intended to allow the transfer of a large data volume, depending on the number of functions of a technical facility or a vehicle. In many applications, it is necessary to transfer the data from the sender to the receiver at the highest possible data transfer rate.
At the present time, in vehicles, a bus system is used in the introduction phase, in which data are transferred as messages under the ISO 11898-1:2015 standard, as a CAN protocol specification with CAN FD. The messages are transferred between the bus users of the bus system, such as the sensor, control unit, transducer, etc. For this purpose, the message is transmitted onto the bus in a frame, in which a switch is made between two communication phases. In the first communication phase (arbitration), it is negotiated which of the user stations of the bus system is allowed to transmit its frame onto the bus in the subsequent second communication phase (data phase or transmission of the useful data). With most manufacturers, CAN FD is used in the vehicle at a 500 kbit/s arbitration bit rate and a 2 Mbit/s data bit rate in the first step. During the transfer, a switch is thus to be made back and forth on the bus between a slow operating mode and a fast operating mode.
To allow even higher data rates in the second communication phase, at the present time a successor bus system for CAN FD (referred to as CAN XL) is being developed, which is presently standardized by the CAN in Automation (CiA) organization. In addition to the strict data transport, CAN XL is intended to also support other functions via the CAN bus, such as functional safety, data security, and quality of service (QoS). These are basic properties that are required in an autonomously traveling vehicle.
Errors may occur during the transfer of data in a frame via a channel (CAN bus). For example, a bit may be falsified or edges between bits may be shifted due to external influences, in particular irradiation or reflections at bus ends. In addition, as the result of nonideal clock sources, a phase error may occur in a user station, which for the present communication on the bus is not a sender, but instead, only a receiver of the message (reception node).
These frame conditions contribute to a reduction in the quantity of data that is effectively transferable per unit of time (the net data rate).

Communication control device for a user station for a serial bus system, and method for communicating in a serial bus system


A serial network interface unit which uses indirect addressing to access an exchange table. In one embodiment, the serial network interface unit comprises a serial communications transceiver, a transmit controller, a receive controller, and a register file for storing an exchange table and an index table. The exchange table has slots for storing information about data exchanges, and the index table has an entry for each ongoing exchange to indicate which of the slots is storing information about the exchange. The transmit and receive controllers are coupled to the register file to reference the index table to determine an exchange table slot corresponding to a current exchange and to thereafter update information in the current exchange table slot. A processor may be coupled to the register file via an i/o bus to store inactive (but ongoing) data exchange information to system memory and to replace the inactive data exchange information with information for active data exchanges. The processor also updates the index file to reflect these changes. When an inactive exchange becomes active again, it is placed back into the exchange table for access by the receive and transmit controllers.

1. Field of the Invention
This invention relates to the field of computer networking, and in particular to a low complexity information exchange management system.
2. Description of the Related Art
Internetworking of high-performance computers has become the focus of much attention in the data communications industry. Performance improvements in processors and peripherals, along with the move to distributed architectures such as client/server, have spawned increasingly data-intensive and high-speed networking applications, such as medical imaging, multimedia, and scientific visualization. However, the interconnections between the systems and their input/output devices cannot keep up with the blinding data rates, nor can they provide the distances needed for local area networks spanning campus-wide areas.
According to "Amdahl's Law", a megabit per second of input/output (I/O) capability is needed for every MIPS of processor performance. Current communications standards top out at just over 100 megabits per second, not nearly fast enough, as technical computing applications already demand processors exceeding 1,000 MIPS. The deficiencies in current transmission rates results in the communications channel becoming a bottleneck to system performance.
A new protocol known as Fibre Channel is 10 to 250 times faster than existing networks, transmitting at rates exceeding 1 Gbps in both directions simultaneously. It defines standard media and signaling conventions for transporting data in a serial fashion, it provides an error correcting channel code and a frame structure for transporting the data, it sets out a flow control methodology, creates some common services, and supports interfaces to existing higher level protocols such as SCSI (small computer system interface). The Fibre Channel protocol can be applied to various network topologies including point-to-point, ring, and switched. The Fibre Channel protocol is being proposed as an ANSI (American National Standards Institute, Inc.) standard, and a multitude of reference material is readily available at http://www.fibrechannel.com.
The higher level protocols supported by Fibre Channel perform "operations" such as: open, read, write, close, etc. Each of these operations corresponds to one or more data exchanges between the local node and a remote node. It is desirable to allow a large number of exchanges to be concurrently active on a given node, since this permits "multitasking" by a node. When a node is waiting on a resource (e.g. waiting for data on a disk to be read into memory) it could simultaneously be fulfilling other requests (e.g. buffering data to be written to disk, sending data already in cache memory to another remote node).
The high data rates require that a large part of the Fibre Channel protocol be handled by hardware. The hardware implementation may incur unwanted cost and complexity, particularly if a large number of concurrent data exchanges are to be supported. Each data exchange must be tracked by the network interface so that the interface can commence, conduct, and conclude each exchange in an orderly fashion, conforming to the specified exchange flow and verifying the validity of each received data frame. The tracking information for each exchange is stored in a corresponding entry in an exchange table. It would be desirable to provide a method for supporting a large number of concurrent data exchanges while maintaining a small exchange table.

System and method for managing information exchanges in a disk interface chip


A method creates semiconductor device in which a storage dielectric film and a storage electrode included in the capacitor is transferred from an inactive region of a semiconductor substrate to the active region thereof, i.e., into a device isolating trench such that the capacitor is prevented from unnecessarily occupying an active region of a semiconductor substrate while maintaining its proper function. In contrast to a conventional device where a capacitor is formed in the active region of the semiconductor substrate, to the capacitor is formed in the inactive region according to this process. Accordingly, the capacitor is able to maintain a trench structure without needing to perform a step of removal of a step height difference, and the active region is minimized in size. Therefore, without having a problem of a step height increase, a finished semiconductor device is able to accommodate modern demands for increased device interpretation.

1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device in which a storage dielectric film and a storage electrode included in the capacitor is transferred from an inactive region of a semiconductor substrate to the active region thereof, i.e., into a device isolating trench such that the capacitor is prevented from unnecessarily occupying an active region of a semiconductor substrate while maintaining its proper function, and a method for fabricating the same.
2. Discussion of the Related Art
Recently, the level of integration of a semiconductor device has rapidly progressed, a geometrical structure of each structural element of the semiconductor device has also been greatly reduced.
As illustrated in FIG. 1, in a semiconductor device in accordance with a related art, a semiconductor substrate 1 is divided and defined as an inactive region (FR) and an active region (AR) by a device separating film 2. In this case, in the active region (AR) of the semiconductor substrate 1, a transistor 10 for selectively switching a flow of electric charge, and a capacitor 20 for storing the electric charge switched by the transistor 10 are closely connected with each other.
In this case, the transistor 10 includes a gate insulating film pattern 11, a gate electrode patter 12, and a source/drain diffusion layer 14. The capacitor 20 includes a storage dielectric film 21 and a storage electrode 22.
In this case, the storage dielectric film 21 and the storage electrode 22 included in the capacitor 20 are formed in a trench 23 buried in the semiconductor substrate 1. In this instance, a portion 22a of the storage electrode 22 is exposed on a surface of the semiconductor substrate 1 and electrically connected with the source/drain diffusion layer 14 of the transistor 10.
As recognized by the present inventor, as semiconductor devices have become more highly integrated, a problem of reducing the active region (AR) acts as an important factor in determining a quality of a finished semiconductor device.
Nevertheless, as aforementioned, since the conventional capacitor 20 includes a trench structure and additionally occupies a portion of the active region (AR), if no separate measures are taken, the size of the active region (AR) of the semiconductor device largely increases as much as that of an occupied region of the capacitor 20. Therefore, it becomes more difficult to reduce the active region (AR) of the semiconductor device in accordance with the related art.
Of course, the size increase problem of the active region (AR) is somewhat assuaged when the structure of the capacitor 20 is changed from the abovementioned trench type structure to a stack type structure. However, as recognized by the present inventor in this case, a serious problem additionally occurs that an overall step height of the semiconductor device is unnecessarily increased as much as a height of the stacked capacitor 20.

Semiconductor device and method for fabricating the same


There is disclosed a method of preparing a vaccine suitable for administration to humans for the prevention or treatment of cancer. The vaccine is prepared by culturing human cancer cells in a serum-free medium and recovering from the culture medium the cell surface antigens shed from the human cancer cells during culturing. After purification, the collected or recovered shed antigens are employed to produce a vaccine consisting essentially of said antigens for the treatment or prevention of human cancer.

This invention relates to human vaccines, such as vaccines for protection against pathogenic microorganisms, e.g. bacterial infections and the like, and to human anti-cancer vaccines. More particularly, and in one special embodiment, this invention relates to the preparation of human anti-cancer vaccines useful for the prevention and/or treatment of cancer, such as melanoma, breast cancer, colon cancer, lung cancer and other such cancers.
For the treatment of cancer, it has been suggested to increase tumor protective immunity by active immunization to tumor antigens, see (1) the article by R. K. Oldham entitled "Biologicals and Biological Response Modifiers: Fourth Modality of Cancer Treatment", Cancer Treat Rep (1984):68:221-232, and (2) the article by M. J. Mastrangelo et al entitled "Current Condition and Prognosis of Tumor Immunotherapy: A Second Opinion", Cancer Treat Rep (1984):68:207-219. Unfortunately, this approach for the prevention and/or treatment of cancer has not been successful or completely satisfactory because of a number of problems, such as the absence in the vaccine of tumor antigens expressed by the tumor to be treated, poor characterization of the antigens in tumor vaccines, the contamination of vaccines by immunogenic but undesirable material, such as fetal calf serum (FCS) protein or transplantation antigens and additionally due to the antigenic heterogenicity of the cancer cells. Moreover, such tumor vaccines were often prepared from fresh tumor cells, the supply of which is limited so that the properties of the vaccines are not reproducible.
A clinical trial was conducted to evaluate the toxicity and immunogenicity in man of a partially purified, polyvalent, melanoma antigen vaccine and some success was indicated, see the abstract of the paper by J. C. Bystryn et al published by The Society for Investigative Dermatology, Inc. entitled "Phase 1 Trial of Specific Immunotherapy of Melanoma with a Polyvalent Melanoma Antigen Vaccine."
It is an object of this invention to provide an improved anti-cancer vaccine.
It is another object of this invention to provide a technique for the preparation of an improved anti-cancer vaccine.
It is another object of this invention to provide an immunotherapy for the prevention and/or treatment of human cancer.
Yet another object of this invention is to provide a technique for the production of reproducible anti-cancer vaccines.
Still another object of this invention is to provide a technique for the preparation of an anti-cancer vaccine useful when introduced into a patient to prevent and/or to treat cancer.
It is still another object of this invention to provide a technique for the preparation of vaccines for diseases caused by infectious cellular and/or subcellular organisms and/or viruses.
It is yet another object of this invention to provide a technique for the preparation of clinically or biologically important material shed from the surface of cells and the like.
How these and other objects of this invention are achieved will become apparent in the light of the accompanying disclosure. In at least one embodiment of the practices of this invention at least one of the foregoing objects will be achieved.


An antenna array with control circuitry placed at a front of the antenna array and between the antenna elements. By locating the azimuth beamforming network control circuitry on the front of the array and between antenna elements, the antenna elements and the other components can be coupled to the control circuitry without using cables. This leads to a reduction in the number of cable connections and to a reduction in size and weight of the resulting antenna array. The ABFN control circuitry is also used to control the beams formed from each row and not from each column as is usually done.

The communications revolution of the early 21st century has given rise to the ubiquity of the smartphone handset. With this comes a much higher demand for wireless communications coverage and, accordingly, more and better antenna arrays to provide such coverage. However, one problem with current antenna array technologies is their bulk—current arrays are large, bulky, and heavy.
The wideband multibeam planar antenna array consists of the wideband element, the wideband Elevation Beam Forming Network (EBFN), the wideband Azimuth Beam Forming Network (ABFN), and related antenna input connectors and cable connections. There are two kinds of multibeam planar antenna arrays: the fixed electrical down-tilt (EDT) array and the variable EDT array. Normally, due to the use of the simple T-splitter power splitter, the EBFN board can be integrated into the feed boards of the wideband elements in the fixed EDT array. For the variable EDT array, due to the phase shifter nature of the EBFN (using either a rotary phase shifter or a sliding phase shifter), it is very difficult to integrate the EBFN board into the feed boards of wideband elements. There is therefore a need to connect the EBFN board to the feed boards by way of cables. A consequence of this is that the number of cables increases dramatically as array size increases. For example, for a 3 beam dual polarization array with 7 columns and 5 rows, there are 84 cable connections: 70 (2 EBFN boards×7 colums×5 rows) between the wideband elements and the EBFN boards, and 14 (2 ABFN boards×7 BFN boards) between the ABFN boards and the EBFN boards.
In addition to the required cable attachments noted above, for such an array, in order to realize the EDT angle for each beam independently, the location of the ABFN and the EBFN boards in the array architecture must be exchanged. In other words, the ABFN boards (i.e. the Butler matrix) is between the antenna element and the EBFN board. Due to the nature of ABFN boards, both the connection between the wideband element and ABFN board and the connection between the ABFN board and EBFN board must be done through the use of cable connections. For the example given above (a 3 beam dual polarization array with 7 columns and 5 rows) there are 100 cable connections: 70 (2 ABFN boards×7 columns×5 rows) between each element and the ABFN boards and 30 (2 ABFN boards×3 EBFN boards×5 rows) between ABFN boards and EBFN boards. Because so many cable connections need to be used, the resulting multibeam array is bulky, heavy, complex, has poor electrical performance and poor passive inter-modulation (PIM), and the array cannot even be manufactured.
There is therefore a need for systems and devices that allow for the design and manufacture of such arrays.


A wheel bearing spindle is produced by an improved method which provides adequate structural clearance from the sharp edge of a wheel drum hub, while actually improving the effective yield strength of the spindle. The spindle is produced from a near net shape steel forging which has a cylindrical spindle and flat wheel flange radiating therefrom. The circular hub of a brake drum fits radially closely over the pilot, and abuts with the wheel flange. Therefore, the juncture of the pilot and flange needs to be relieved or cut away somehow, both radially and axially, in order to assure non interference with the circular edge of the hub, which could prevent the rest of the hub from intimately abutting the surface of the wheel flange. The radial component of the clearance is provided by conventionally machining a channel radially into the pilot. This can be done, since it does not weaken the flange. The axial clearance, which has to be provided into the surface of the flange, is provided not by machining, but by a coining operation. This creates an axial channel of a specific shape which not only provides clearance but which, by strain hardening the surface of the flange near its juncture with the pilot, shifts the stress zone radially inwardly. This actually effectively increases the yield strength of the flange, despite the axial thinning of the flange.

Known wheel bearings of the type shown in FIGS. 1 and 2, and indicated generally at 10, have a stationary outer hub 12, which is secured to a non illustrated vehicle suspension, and a rotatable spindle, indicated generally at 14. Spindle 14 rotates because it carries the vehicle wheel 16, as well as a brake drum 18. Brake drum 18 is mounted to spindle 14 through an open, central circular hub 20, which has a predetermined axial thickness as measured between a pair of circular edges. The inner edge, indicated at 22, appears to be a sharp comer in cross section, and is generally referred to as the "theoretical sharp comer." Adequate clearance from the comer is important to the proper installation of the brake drum 18 to spindle 14. Specifically, spindle 14 includes a cylindrical pilot 24 with an outer surface over which the brake drum hub 20 is inserted, with a very close radial clearance. A flat annular wheel flange 26 radiates outwardly from the pilot 24, perpendicular thereto, with a flat outboard outer surface 28 against which the brake drum hub 20 is abutted, and an axially opposed inboard outer surface 30. The brake drum hub 20 is firmly sandwiched between the outboard abutment surface 28 and the wheel 16 itself, which is bolted onto conventional studs 32, when the vehicle is operating. In addition, small clips on the studs 32 can be used, if desired, to retain the brake drum hub 20 flat against the flange abutment surface 28 when the vehicle is stationary and the wheel 16 is removed. There is little need for such retainers, however, because of the close fit of hub 20 over the pilot 24, and such clips would be primarily needed during shipping, when the bearing 10 and brake drum 18 would be handled as a unit.
The primary concern relative to brake drum 18 is not shipping retention, but rather the maintaining of a close, flat to flat contact of the hub 20 against the wheel flange abutment surface 28 during vehicle operation. This assures the clean and efficient translation of braking loads on drum 18 to the spindle 14 and, ultimately, to wheel 16. To that end, a relief channel 34 is machined into both the outer surface of pilot 24 and the wheel flange abutment surface 28 at their circular, perpendicular juncture. Relief channel 34 is machined when the other critical surfaces, such as the pilot 24, are machined to final dimension on the initial blank from which spindle 14 is manufactured, which itself is forged to near net shape. Other structural features of spindle 14, such as the holes for the studs 32, are cut through the blank with dies. The existence of relief channel 34 at the point where the "theoretical sharp corner" represented by the edge 22 lies assures that, regardless of any tolerance variations in the edge 22, there will not be any physical interference that could potentially hold the surface of brake drum hub 20 away from the wheel flange abutment surface 28. However, the juncture between pilot 24 and the wheel flange 26 is critical for another reason. The stress of wheel loads on flange 26 tend to bend and flex it about its juncture with pilot 24, although the spindle flange 26 is made more than thick enough not to actually bend or crack significantly in actual operation. Nevertheless, if deliberately stressed to failure in a test fixture, such stresses will naturally concentrate in a predictable zone that finds the "weakest link", which is the effectively least thickness between the pilot 24-abutment surface 28 juncture and the opposed, inboard wheel flange surface 30. Such deliberately caused high stress will cause a crack to form through this stress zone, which is shown as a diagonal dotted line in FIG. 2, but represents, in fact, a conical surface. The necessary relief channel 34 does round out the otherwise sharp juncture between pilot 24 and flange 26, which tends to avoid stress concentration. More significantly, however, machining out the steel that creates the relief channel 34 significantly thins the flange 26 at the very point where stresses will concentrate, and thereby necessitates that flange 26 be thicker and heavier than it would otherwise have to be. Heat treating the surface of channel 34, as by induction methods, would harden it, but represents an additional and expensive step which is generally not done, in preference to just making flange 26 thick enough that the thinning created by the channel 34 is not a problem. While spindles like 14 do and have operated very successfully, it is a constant goal to improve designs and methods of manufacture so as to save weight and cost.

Method for manufacturing a wheel bearing spindle


A method for imparting the multiple functions of water- and oil-repellency, soil-releasing properties and anti-bacterial properties to a mixed or blended fabric is provided including: (a) treating a mixed or blended fabric of polyester/rayon by dipping the mixed or blended fabric in a treating solution which includes, based on the weight of the mixed or blended fabric, 1 to 10 wt. % of phenolic antibacterial agent, 2.5 to 5.0 wt. % of a first fluoric compound, 3.0 to 6.0 wt. % of a second fluoric compound, different from the first fluoric compound, 0.3 to 0.5 wt. % of melamine resin as a cross-linking agent and a buffer, the rate of absorption of treating solution by the mixed or blended fabric being maintained at 50.+-.5%, (b) drying the treated fabric, and (c) thereafter heat treating the treated and dried fabric.

Generally, in a mixed or blended fabric of natural and synthetic fibers, there is often posed a problem that, when such a fabric is used for clothes, as a result of different fibrous characteristics of constituting fibers, microbes are incubated under the influence of sweat from human body and external pollutants, and a considerable quantity of ammonia is evolved to release an unpleasant odor or to inflict harm to the human body. Therefore there have been many attempts to impart an antibacterial function, as well as soil-releasing and water-repellent functions to fibrous materials.
However, the conventional art was restricted to a single function and thus, individual treating methods, for example, to impart the water-repellent and oil-repellent function, soil-releasing function or antibacterial and odor removing function were sought.
As a method to impart an antibacterial property to fibers, organic compounds based on silicon tertiary-ammonium are widely used in recent years, as disclosed in Japanese unexamined patent publication Sho 54-38951, wherein an ion exchange copolymer is produced and the product is treated with an aqueous solution of a copper or silver salt to deposit a metal ion on the surface of fibers whereby an antibacterial property is provided.
Further, in order to conduct a soil-releasing process on fabric cloth, there is disclosed a method in Japanese unexamined patent publication Hei 4-55491, wherein a silicon type agent for rendering soil-releasing function, incorporating a modified silicon compound, is coated on the fiber surface and another method in Japanese patent publication Hei 1-44837, wherein a film comprising a fluorine-containing compound and cationic surface active agent is coated on the fiber surface.
Still more, Japanese patent publication Hei 3-35432 discloses a water- and oil-repellency treating method for fabric cloth wherein dipping with a treating solution including a blocked polyisocyanate compound and a water-and oil-repellent agent based on silicon is conducted before drying and subsequently thermal treating is conducted.
The object of the present invention is to provide a multifunctional treating method wherein in order to bring forth multiple functions of water-repelling, oil-repelling, soil-releasing and bacteria resistance, a fluoric compound, a phenolic antibacterial agent and a buffer are minutely controlled through an adjustment of pH to create an excited state of a fluoric compound and a balanced coexistence of hydrophilicity and hydrophobicity whereby water-repellent and oil-repellent properties in the atmosphere and an antipolluting property in water are simultaneously exhibited, whereas the prior art failed to reveal the multiple functions because water-repelling and oil-repelling functions and a soil-releasing function were not in harmony, only a certain function being focussed on, which leads to a marked decrease in other functions.

Treating method for imparting water-and oil-repellent, soil-releasing and antibacterial properties to polyester/rayon mixed or blended fabric


The high-strength galvanized steel sheet having excellent formability has a component composition containing, on the basis of mass percent, 0.05 to 0.2% C, 0.5 to 2.5% Si, 1.5 to 3.0% Mn, 0.001 to 0.05% P, 0.0001 to 0.01% S, 0.001 to 0.1% Al, and 0.0005 to 0.01% N, the balance being Fe and incidental impurities; and the steel sheet has a microstructure including a ferritic phase and a martensitic phase including a tempered-martensitic phase, the ferritic phase having an area fraction of 30% or more relative to an entirety of the microstructure, the martensitic phase having an area fraction of 30 to 50% relative to the entirety of the microstructure, and the tempered-martensitic phase having an area fraction of 70% or more relative to an entirety of the martensitic phase.

In recent years, to provide crash safety of automobiles for the occupants and to improve the fuel efficiency of automobiles by decreasing the weight of automobile bodies, the application of high-strength steel sheets having a TS of 780 MPa or more and a small thickness to structural members of automobiles has been promoted. In particular, the application of steel sheets having a very high strength of 980-MPa-grade TS or 1180-MPa-grade TS has also been recently studied.
However, in general, an increase in the strength of steel sheets results in degradation of the ductility, stretch flangeability, and bendability of steel sheets and leads to degradation of the formability of steel sheets. Accordingly, galvanized steel sheets having a high strength, excellent formability, and excellent corrosion resistance are demanded.
To meet such a demand, for example, Patent Literature 1 proposes a high-strength galvannealed steel sheet having excellent formability and excellent adhesion of the coating. This steel sheet contains, on the basis of mass percent, 0.04 to 0.1% C, 0.4 to 2.0% Si, 1.5 to 3.0% Mn, 0.0005 to 0.005% B, 0.1% or less P, more than 4N and 0.05% or less Ti, and 0.1% or less Nb, the balance being Fe and incidental impurities; has galvannealing coatings on the surfaces of the steel sheet, the galvannealing coatings containing 5 to 25% Fe; has a multi-phase microstructure of a ferritic phase and a martensitic phase; and has a TS of 800 MPa or more. Patent Literature 2 proposes a high-strength galvannealed steel sheet having good formability that contains, on the basis of mass percent, 0.05 to 0.15% C, 0.3 to 1.5% Si, 1.5 to 2.8% Mn, 0.03% or less P, 0.02% or less S, 0.005 to 0.5% Al, and 0.0060% or less N, the balance being Fe and incidental impurities; satisfies (Mn %)/(C %)≧15 and (Si %)/(C %)≧4; and has a volume fraction of 3 to 20% in terms of a martensitic phase and a retained austenitic phase in a ferritic phase. Patent Literature 3 proposes a high-strength galvanized steel sheet with low yield ratio that has excellent stretch flangeability. This steel sheet contains, on the basis of mass percent, 0.04 to 0.14% C, 0.4 to 2.2% Si, 1.2 to 2.4% Mn, 0.02% or less P, 0.01% or less S, 0.002 to 0.5% Al, 0.005 to 0.1% Ti, and 0.006% or less N, satisfies (Ti %)/(S %)≧5, the balance being Fe and incidental impurities; has a volume fraction of 6% or more in terms of the total of a martensitic phase and a retained austenitic phase; and satisfies α≦50000×{(Ti %)/48+(Nb %)/93+(Mo %)/96+(V %)/51} where α% represents the volume fraction of a hard phase microstructure including the martensitic phase, the retained austenitic phase, and a bainitic phase. Patent Literature 4 proposes a high-strength galvanized steel sheet having excellent adhesion of the coating and excellent elongation during forming of the steel sheet. This steel sheet contains, on the basis of mass percent, 0.001 to 0.3% C, 0.01 to 2.5% Si, 0.01 to 3% Mn, and 0.001 to 4% Al, the balance being Fe and incidental impurities; has galvanization coatings on the surfaces of the steel sheet, the galvanization coatings containing, on the basis of mass percent, 0.001 to 0.5% Al and 0.001 to 2% Mn, the balance being Zn and incidental impurities; satisfies 0≦3−(X+Y/10+Z/3)−12.5×(A−B) where, on the basis of mass percent, X represents the content of Si of the steel, Y represents the content of Mn of the steel, Z represents the content of Al of the steel, A represents the content of Al of the galvanization coatings, and B represents the content of Mn of the galvanization coatings; and has a microstructure that is constituted by a primary ferritic phase (volume fraction: 70 to 97%) having an average grain size of 20 μm or less and a secondary phase (volume fraction: 3 to 30%) constituted by a austenitic phase and/or a martensitic phase, the secondary phase having an average grain size of 10 μm or less.

High-strength galvanized steel sheet having excellent formability and method for manufacturing the same


A driver circuit for driving one or more loads in a controlled manner includes multiple operational modes. In one mode, bypass switching may be used to adjust a drive signal applied to the one or more loads. In another mode, a DC-DC converter may be used to adjust the drive signal applied to the one or more loads. In at least one embodiment, the driver circuit is a light emitting diode driver circuit.

Electronic driver circuits are often called upon to drive electrical loads in a controlled manner in order to achieve a variable result. As one example, DC-DC switching converters (e.g., a buck converter, etc.) are often used to drive a light emitting diode (LED) load. The LED brightness is directly proportional to the current through the LED.
One type of converter sometimes used to drive an LED load is a current regulator that maintains a constant current output by using the output inductor as a current-regulating element. This regulator type eliminates the need for a large output capacitor as is generally required in voltage regulators, thereby reducing component cost and circuit board space requirements. However, one drawback of using the output inductor as a current-regulating element is that the inductor current cannot be turned on and off instantaneously.
A commonly used technique for adjusting LED brightness is the use of a pulse width modulation (PWM) signal. The LED current ramps up to a regulation target when the PWM signal is high and ramps down when the PWM signal goes low. Due to the finite current slope through the output inductor, the average current cannot be precisely controlled. The error gets larger as the PWM duty cycle gets lower. Therefore, another technique may be applied to achieve fast turn on and turn off of the LED current. One such, technique is to use a bypass switch in parallel with the LED string. The bypass switch acts as a current shunt to steer the inductor current away from the LED load such that the voltage across the LED string drops instantaneously from Vf (i.e., the forward voltage across the LED string) to nearly zero volts. The average inductor current remains unchanged, while the switch duty cycle is reduced to account for the lower output voltage.

Method and apparatus for driving loads using a DC-DC converter


A Method and System for Parallel Operation and Control of Legacy Computer Clusters is disclosed. Also disclosed is a system that permits the creation of a cluster computer using the legacy operating systems already existing on the computing devices. The system is further be able to seamlessly operate over a standard wide are network, such as the “Internet,” as well as over local area networks. The system further permits the individual computers to operate either as part of the cluster, or on local operations, without any need for modification to the other computers involved in the cluster. Still further, the system utilizes standard TCP/IP format for all internodal messaging. Finally, the system maintains performance “grades” for each cluster node, either by node self-grading, or by node reporting, such that the user can select which nodes to participate in a particular parallel application.

1. Field of the Invention
This invention relates generally to parallel computing systems and, more specifically, to a Method and System for Parallel Operation and Control of Legacy Computer Clusters
2. Description of Related Art
Parallel computation, the use of multiple processors (both within one computing device as well as between networked computing devices) to solve large computational tasks, has been an objective of the industry for quite some time. In seeking to serve these large computational tasks, scientists have often written their own software code—this code was historically written specifically for parallel computers (i.e. computers having multiple processors). While these "parallel applications" functioned adequately (when constructed well, of course), their utility was limited to the particular task (and many times hardware) for which they were specifically written; changes in hardware and/or software requirements typically would require substantial, costly, software revisions. Furthermore, these applications were typically unable to be used on other computing devices.
Large parallel computers are typically located at major supercomputing centers, the hardware consists of large parallel computers (e.g. Cray T3E, IBM SP, Fujitsu, etc.), the software is commonly proprietary vendor software (many time a Unix variant). These "supercomputers" are managed by large staffs of professional administrators, and the majority of their operations are not accessible directly by individual users (except through the administrators).
As personal computers led the hardware and software evolution to where substantial computing power became attainable by the individual, systems known as "Clusters" became prevalent. Computer clusters are a, type of parallel computation system where a network of computing devices' processors are tightly coupled to share computation tasks in parallel fashion. An early and fairly prevalent version of a cluster computer is the "Beowulf" system first assembled at a NASA site to solve Earth Sciences problems (NASA Goddard Space Flight Center). The Beowulf cluster is characterized by a set of personal computers connected by specialized network hardware and running a specialized version of the open-source Linux operating system.
A Beowulf class cluster computer is distinguished from a Network of Workstations by several subtle but significant characteristics. First, the nodes in the cluster are dedicated to the cluster in order to "ease load balancing problems," by removing any external factors from affecting the performance of individual nodes. A second characteristic of these systems is that the interconnection network is isolated from any external network such that the network load is determined only by the application being run on the cluster. Along with this architecture, all the nodes in the cluster are within the administrative jurisdiction of the cluster. Since there is no external network access or participation, there is no need (or provisions for) network security.1 1http://www.beowulf.org/intro.html2http://www.webopedia.com
While proponents of Beowulf systems (running on Linux operating systems) assert that they are extremely user-friendly to run parallel applications, it seems apparent that the clusters themselves are anything but simple to design and construct. In fact, it has been observed that at least two Beowulf clusters required approximately six months each to construct. Furthermore, the need for the computers to be captured (i.e. totally dedicated to use as a member of the cluster) in order to be a part of the cluster eliminates the possibility of making use of existing legacy networked computers.
If we turn to FIG. 1, we can review the general structure of a conventional (or legacy) computing device, such as a personal computer, so that we might next analyze how such a computing device might be modified in order to become part of a Beowulf cluster. FIG. 1 is a block diagram of pertinent functional components of a conventional computing device 10.
As shown, the computing device 10 comprises one or more processors 12 for performing the computations that are the essence of the function for which the computer 10 is used. The device 10 will also include a conventional operating system 14 for controlling the computer's operation. In communication with (or at least controlled by) the operating system are one or more input-output sub-systems, such as a video monitor, a keyboard, a network portal, etc. Another important module controlled by the operating system 14 is the memory 18. It is in the memory 18 (in this case random access memory, or RAM) that software applications reside while they are being executed; of course the memory 18 is closely coupled with the processor(s) 12.
To say that a software application such as any of 20A–20C is being executed on the computing device 10 is to actually say that the calculations that make up the applications are being operated upon by the processor(s) 12. In the case of the typical application 20, the operating system 14 is the "translator" between the application 20 written in a so-called high level language and the processor(s) 12, although in the case of applications written in "machine language," such as 20C, the application 20C interfaces directly with the processor(s). The operating system 14, although heretofore described generally, actually includes a critical component known as the "kernel."
The kernel is the central module of an operating system 14. It is the part of the operating system 14 that loads first, and it remains in main memory 18. Because it stays in memory 18, it is important for the kernel to be as small as possible while still providing all the essential services required by other parts of the operating system and applications. Typically, the kernel is responsible for memory management 26, process and task management 22, I/O management 24 and disk management.2 In order to better understand the nuances of the present invention, the kernel is represented here as being discrete components responsible for the various functional areas of the operating system 14; in fact, only a single kernel is run on a particular machine at a particular time. If we now turn to FIG. 2, we can examine one of the drawbacks of the prior methods and systems for creating cluster computers. 1http://www.beowulf.org/intro.html2http://www.webopedia.com
FIG. 2 is a block diagram of pertinent functional components of a conventional computing device 11 as it would be modified for operation as a node in a cluster computer under the prior art. In order for the cluster node control and interface software application 20D to be able to operate on the conventional computing device 11 to give control of its processor(s) 12 to another computing device (which is necessary to cluster compute), it has always been necessary, at the very minimum, to replace the original operating system with a modified operating system 15. The new operating system 15 is specifically designed to provide a kernel having the new functionality necessary to permit the cluster node control and interface application to offer the device's processor(s) up for control by an external computer (i.e. the control computer in the cluster).
This new kernel will typically require a revised CPU kernel 22A to provide the cpu-sharing capability, a revised I/O kernel 24A to exchange job messaging with the external computer(s), and a revised memory kernel 26A to provide control, monitoring and access to the device's memory 18 to external computers. There are at least two problems with replacing the original operating system with a special-purpose operating system: (1) there is a much higher likelihood of instability in the operating system due to conflicts and/or errors, and (2) the revised operating system is unlikely to maintain its original functionality—this means that the device 11 would not be suitable for general use any time the modified operating system is "booted." The result of this loss of original functionality is that the cluster will not be able to capitalize on existing (even idle) computer resources—the systems must be dedicated to the cluster and nothing else.
What is needed is a cluster node control software application that can operate with an existing, conventional or legacy operating system to provide shared processor resources to external computers in order to create a cluster computer without the need for computing resources dedicated to this task.

Method and system for parallel operation and control of legacy computer clusters