An antistatic optical film comprising an antistatic layer laminated on at least one side of an optical film, wherein the antistatic layer comprises a water soluble or a water dispersible conductive polymer, has excellent antistatic effect, optical characteristics and appearance.

1. Field of the Invention
The present invention relates to an antistatic optical film comprising an antistatic layer laminated on at least one side of an optical film, and a method for manufacturing the same. Furthermore, it relates to an image viewing display using the above-mentioned antistatic optical film, such as liquid crystal displays (LCDs), organic electroluminescence viewing displays, and PDPs. As the optical films, a polarizing plate, a retardation plate, an optical compensation film, a brightness enhancement film, etc., and furthermore optical films with the films laminated to each other may be mentioned.
2. Description of the Related Art
In liquid crystal displays etc., an image forming system necessarily requires polarizing elements disposed on both sides of a liquid crystal cell, and in general, polarizing plates are adhered thereto. Moreover, in liquid crystal panels, in order to improve display quality of displays, various optical elements in addition to the polarizing plates are increasingly used. For example, retardation plates for prevention of coloring, viewing-angle expansion films for improving viewing angle of liquid crystal displays, and furthermore, brightness enhancement films for increasing contrast of displays etc. are used. These films are generically named and called optical films.
In case of adhesion of the optical films to liquid crystal cells, pressure sensitive adhesives are usually used. Moreover, in adhesion between optical films and liquid crystal cells, and between optical films, each element usually is attached using pressure sensitive adhesives in order to reduce loss of light.
In these optical films, in order to prevent occurrence of damage and contamination to a surface of the optical film in transportation or manufacturing process until it is sent to consumers, surface protective films are usually attached on a surface thereof. The surface protective film is attached from a stage in which the optical film is in a state of single substance, and in some case it is peeled after being attached onto an LCD etc., and furthermore in other cases it is attached again after peeled to a same or another surface protective film. And there have been problems that static electricity generated in case of peeling of the surface protective film may destroy circuits, such as in LCD panels.
Although ITO treatment is usually performed on a cell substrate of one side of liquid crystal cell in case of LCD especially driven by IPS mode, antistatic treatment is not performed to an opposite side. For this reason, when a surface protective film is further removed from an optical film attached on a side without ITO treatment, separation electrification is generated, causing to occurrence of disorder of pictures. There are problems, also in a stage of completed panel finished products, that electrification is generated by wiping of pollution on a surface by cloths etc. in optical films of viewing side (upper side), or by contact with a diffusion film in the optical film of incidence side (lower side), resulting in disorder of pictures. Also in case of LCD driven by VA mode, when a cell substrate without ITO treatment given is used on one side of a liquid crystal cell, same problems occur.
In order to solve the above-mentioned problems, disclosed are a polarizing plate with an antistatic film having an antistatic film currently formed on a surface thereof (Japanese Patent Laid-Open No. 2-73307 official report), and a polarizing plate having a transparent conductive layer(s) prepared on one side or both sides thereof (Japanese Patent Laid-Open No. 4-124601 official report).

Antistatic optical film, method for manufacturing the same and image viewing display


A universal joint having a first yoke including a body portion and an overmold portion. The body portion includes a base and a pair of arms that extend from the base. A trunnion assembly is coupled to the first yoke and extends between the arms. A second yoke is coupled to the trunnion assembly.

The universal joint is well known in the art and commonly employed for use in the drivelines of automobiles and trucks. The universal joint transmits power, motion, or both, between two rotating shafts. The axes of the shafts are always intersecting while the bending angle between them is permitted to change during operation.
A typical universal joint includes a pair of opposed yokes that are axially aligned with one another. Each yoke has a pair of opposed axially extending arms that typically define diametrically opposed bores for receiving the bearing cups that support a spider or trunnion. The trunnion is typically cross-shaped, having bearing ends that are sized to be received into bearing cups.
The bearing cups are typically secured to the yokes by means of a circumferential groove formed in the surface of the bearing cup and a matching circumferential flange formed in the openings of the yokes. Due to the sizing of the bearing cups and openings, the bearings must be carefully aligned with the yokes in order to insert the bearings into the extending arms of the yokes. The difficulty of this operation is compounded since the trunnion must be aligned with the bearing cups in the opposing yoke. Therefore, even minor variances in the alignment between the bearing cups and the openings in the yokes can impede the assembly of the universal joint.
Accordingly, it is an object of the present invention to provide the art with a new universal joint yoke assembly and method of construction that eliminates the need for high precision machining and time consuming alignment between the opposing yokes and the trunnion while reducing fabrication costs.


A high-frequency quartz crystal unit includes a quartz crystal blank having a hole defined in at least one principal surface thereof, providing a resonating region in a portion of the crystal blank which is made thinner by the hole, excitation electrodes disposed respectively on opposite principal surfaces of the crystal blank in the resonating region, extension electrodes extending respectively from the excitation electrodes to respective first and second positions on an outer peripheral portion of the crystal blank, and a casing. The crystal blank has a fixed end electrically and mechanically connected to the casing by eutectic alloy in the first position. The crystal blank has a free end on which the extension electrodes are electrically connected to the casing by wire bonding in the second position.

1. Field of the Invention
The present invention relates to a quartz crystal unit having a high vibration frequency of 100 MHz or higher, and more particularly to a crystal unit having good aging characteristics and oscillating characteristics and a holding structure of such a crystal unit.
2. Description of the Related Art
Crystal units having a quartz crystal blank housed in a casing are incorporated as a frequency control device, particularly a reference source of a communication frequency, in oscillators. In recent years, with the advent of optical communication systems, there have been demands for crystal units having higher vibration frequencies. To meet such demands, a crystal unit has been developed which has a recess defined in a resonating region of a crystal blank to reduce the thickness of the crystal blank in the recess for increasing the resonant frequency, and holds the resonating region with a relatively thick portion around the recess to provide desired mechanical strength.
FIG. 1 shows a conventional crystal unit of such a design in exploded perspective. As shown in FIG. 1, the conventional crystal unit comprises casing 5 made of laminated ceramics and having a recess defined therein, and crystal blank 2 accommodated in the recess in casing 5. Casing 5 is in the form of a substantially rectangular parallelepiped, and crystal blank 2 is of a substantially rectangular shape. A step is formed on one of side surfaces of the recess in casing 5. A pair of connecting terminals 7 is disposed on the upper surface of the step at its opposite ends for electrically connecting to crystal blank 2. A pair of mounting terminals (not shown) is disposed on the outer surface of casing 5 and used to surface-mount the crystal unit on a wiring board. The mounting terminals are electrically connected to connecting terminals 7 through via holes or the like that are defined in casing 5.
Structural details of crystal blank 2 are shown in FIGS. 2A and 2B. Crystal blank 2 typically comprises an AT-cut quartz crystal blank. The AT-cut quartz crystal blank has its resonant frequency determined depending on the thickness thereof. The resonant frequency of the AT-cut quartz crystal blank is higher as the thickness thereof is smaller. To enable crystal blank 2 to have a resonant frequency in excess of 100 MHz, hole portion 1 is defined centrally in one principal surface of crystal blank 2, making crystal blank 2 thinner at the bottom of hole portion 1 than at a portion around hole portion 1 with the thinner region serving as a vibrating region. In the vibrating region, excitation electrodes 3 are disposed respectively on the principal surfaces of crystal blank 2. Extension electrodes 4 extend respectively from excitation electrodes 3 toward respective opposite areas of a shorter side of crystal blank 2. Extension electrodes 4 are associated respectively with connecting terminals 7 on the step of casing 5. Extension electrode 4 which is disposed on the upper surface of crystal blank 2 as shown has its tip end folded back over the lower surface of crystal blank 2 as shown across the shorter side of crystal blank 2. The both ends of the shorter side of crystal blank 2 is fixed to connecting terminals 7 by electrically conductive adhesive 6, thus holding crystal blank 2 horizontally in the recess in casing 5 and electrically connecting extension electrodes 4 to connecting terminals 7. Therefore, the mounting terminals disposed on the outer surface of casing 5 are electrically connected to excitation electrodes 3 of crystal blank 2.
After crystal blank 2 is fixed to the step in the recess in casing 5, a cover (not shown) is placed on casing 5 to seal the opening of the recess, thus hermetically sealing crystal blank 2 in casing 5.
The crystal unit of the above structure has suffered the following problems because of crystal blank 2 being fixed in position by electrically conductive adhesive 6: Electrically conductive adhesive 6 comprises a polymer resin such as silicone or epoxy resin mixed with metal particles. When electrically conductive adhesive 6 is hardened with heat, it bonds crystal blank 2 to casing 5. When electrically conductive adhesive 6 is thermoset, it emits an organic gas that is attached to crystal blank 2. An organic gas component that remains unremoved by cleaning or the like will subsequently be released and attached again to the vibrating region of crystal blank 2. When the assembly is exposed to a high temperature after crystal blank 2 is hermetically sealed in casing 5, electrically conductive adhesive 6 also emits an organic gas that will subsequently be attached to the vibrating region of crystal blank 2. If the organic gas component is attached to the vibrating region of crystal blank 2, the vibration frequency of crystal blank 2 or the like changes due to the mass addition effect or the like of the organic gas component, impairing the aging characteristics of the crystal unit. The higher the vibration frequency of crystal blank 2, the smaller the thickness of the vibrating region. Thus, if the vibration frequency of crystal blank 2 is higher, then the organic gas component that is attached to the vibrating region of crystal blank 2 is more detrimental to the aging characteristics of the crystal unit.
One solution would be to use a eutectic alloy having a low melting point, e.g., an inorganic material of AuSn (gold-tin) alloy, as a joining material for fixing crystal blank 2 to casing 5, instead of electrically conductive adhesive 6. However, since the joint made by a eutectic alloy has a high bonding strength, crystal blank 2 is strained due to the difference between the coefficients of thermal expansion of crystal blank 2 and casing 5. FIGS. 3A and 3B show the manner in which crystal blank 2 is strained due to the difference between the coefficients of thermal expansion of crystal blank 2 and casing 5. As shown in FIGS. 3A and 3B, crystal blank 2 is bent under stresses applied between two outer peripheral points on crystal blank 2. The strain is propagated to the vibrating region of crystal blank 2, impairing the vibrating characteristics of crystal blank 2, in particular, frequency vs. temperature characteristics that will be represented by a cubic function curve if crystal blank 2 comprises an AT-cut quartz crystal blank.
If crystal blank 2 is held at its opposite ends, then it will be strained to a greater extent because the vibrating region is positioned between the opposite ends than if crystal blank 2 were held at opposite sides at one end thereof. If the vibration frequency of crystal blank 2 is higher, then since the thickness of the vibrating region is smaller, crystal blank 2 will be strained more greatly. Though crystal blank 2 is also strained if it is fixed in position by electrically conductive adhesive 6, it is trained to a much larger extent if the eutectic alloy is used as the joining material.

Crystal unit and holding structure of crystal unit


An electronic circuit provided with a III/V semiconductor domain, and a method of operating such a circuit is presented. In particular, the present application relates to electronic circuit based on a Gallium Nitride (GaN) semiconductor. GaN components must be controlled in a way that ensures proper operation over a wide variation of GaN parameters. There is a circuit comprising a first domain coupled to a second domain, the first domain being based on a III/V semiconductor; wherein the first domain comprises a first component and a second component. The second component being representative of an electrical characteristic of the first component. The second domain contains a sensor adapted to sense an electrical quantity of the second component and an input generator coupled to the sensor. The input generator is adapted to provide at least one input, based on the electrical quantity, to the first domain.

Semiconductors components based on III/V semiconductors such as Gallium Nitride, GaN, diodes and GaN N-channel transistors, have a number of advantageous properties. For instance, GaN transistors have a relatively low on-resistance and can achieve higher switching speed compared to their silicon-based counterpart. As such, GaN components s are well suited for the design of switching converters and high-voltage power circuits.
However, the characteristics of GaN components, such as the forward voltage of a diode or the threshold voltage of a transistor, may vary significantly over a range of temperature and processes. For example, the characteristics of individual components obtained from different semiconductor wafers or from different dies may vary significantly. The characteristics of a GaN component, also referred to as GaN device, may vary by about 30% between two dies issued from a same wafer. This greatly complicates the implementation of accurate GaN voltage references.
As a result, GaN components must be controlled in a way that ensures proper operation over a wide variation of GaN parameters. In practice, this means that the gate voltage of a GaN transistor is over-driven to ensure operation in the saturation region of the transistor, typically in the region of 6V. Driving a GaN transistor with a high a gate voltage can cause severe degradation and over-stress to the GaN transistor. This also reduces operational efficiency and hinders linear mode operation of the device.

Circuit based on a III/V semiconductor and a method of operating the same


Systems, methods, and computer-readable storage devices to enable secured data access from a mobile device executing a native mobile application that operates in connection with a server executing a headless browser are disclosed.

As mobile devices become commonplace, users elect to perform more and more day-to-day tasks using mobile devices. For example, users may use mobile devices to work on projects that were typically reserved for desktop or laptop computers, such as editing documents and spreadsheets, creating drawings or graphic designs, generating multimedia content, etc. For a mobile device to perform certain tasks, the mobile device may need access to secured user data. However, due to security considerations and pre-existing back-end systems, providing mobile devices access to such secured user data may be challenging.
To illustrate, one day-to-day task in which mobile devices may be used is mobile banking. Increasingly, banking customers prefer to use a mobile device application to manage their money. As a result, banks are deploying mobile banking applications. For small and mid-size banks, it may be prohibitively expensive to develop a customized and full-featured mobile banking application (e.g., via in-house development or by hiring a third party development team), including setting up back-end security features and data integrations that enable such an application to access secured data, such as pre-existing account data, data stored in data warehouses, etc. To provide mobile banking for small and mid-size banks, some vendors use account aggregation, which involves storing user credentials for a bank on an intermediary server and then accessing the bank via the intermediary server. However, the account aggregation approach does not function properly if the bank blocks such accesses from third-party servers for security reasons. To illustrate, if the bank is able to identify multiple accesses coming from the same internet protocol address, the bank may block all accesses from the internet protocol address, thereby preventing the account aggregation technique from functioning. Storing user access credentials on intermediary servers (e.g., in the cloud) can also be a security risk. Additionally, processing power and battery life of some mobile devices can lead to challenges in creating mobile banking applications. For example, some devices, such as computerized watches, may lack sufficient processing resources and battery power to support a full-featured mobile banking application.

System architecture for accessing secure data from a mobile device in communication with a remote server


A solar cell module includes a plurality of solar cells each including a substrate, an emitter region positioned at a back surface of the substrate, first electrodes electrically connected to the emitter region, second electrodes electrically connected to the substrate, a first current collector positioned at ends of the first electrodes, and a second current collector at ends of the second electrodes, and a first connector connecting a first current collector of a first solar cell of the plurality of solar cells to a second current collector of a second solar cell adjacent to the first solar cell. The first current collector of the first solar cell and the second current collector of the second solar cell each have a different polarity.

Field of the Disclosure
Embodiments of the disclosure relate to a solar cell module.
Description of the Related Art
Recently, as existing energy sources such as petroleum and coal are expected to be depleted, interests in alternative energy sources for replacing the existing energy sources are increasing. Among the alternative energy sources, solar cells for generating electric energy from solar energy have been particularly spotlighted.
A solar cell generally includes a substrate and an emitter region, each of which is formed of a semiconductor, and electrodes respectively formed on the substrate and the emitter region. The semiconductors forming the substrate and the emitter region have different conductive types, for example, a p-type and an n-type. A p-n junction is formed at an interface between the substrate and the emitter region.
When light is incident on the solar cell, a plurality of electron-hole pairs are produced in the semiconductors. The electron-hole pairs are separated into electrons and holes by photovoltaic effect. The separated electrons move to the n-type semiconductor (e.g., the emitter region), and the separated holes move to the p-type semiconductor (e.g., the substrate). Then, the electrons and holes are collected by the electrodes electrically connected to the emitter region and the substrate, respectively. The electrodes are connected to each other using electric wires to thereby obtain electric power.


A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

The use of cache subsystems in microcomputer systems leads to a number of attractive operating advantages. A microcomputer system employing a cache subsystem is in effect a dual bus microcomputer. The CPU and cache subsystem are connected together via what can be referred to as a CPU local bus. Separate from the CPU local bus is a system bus to which other devices (I/O devices, additional memory, etc.) can be connected. The presence of the cache subsystem relieves the system bus from any read memory access to the extent that the information sought is found in the cache subsystem. Because not all desired information will be found in the cache subsystem, and write operations are usually directed to both the cache subsystem and to memory, there must of course be some connection between the system bus and the CPU local bus. When that connection is a latched buffer, additional advantages, specifically posted write operations, are possible.
More particularly, in any write operation, access will be necessary to memory (which is not on the CPU local bus). The information (data and address) for the write access is initially placed on the CPU local bus where it can be used for writing to the cache subsystem. Since the interface between the CPU local bus and the system bus is a latched buffer, the same data can be latched into the buffer. Once that information is latched onto the buffer, it need no longer be driven by the CPU. Thus a posted write cycle relies on the fact that the address and data information for a memory write operation is available from the latched buffer. Completion of that write cycle does not require the attention of the CPU. Thus in a "posted" write, the data and address for the write cycle is latched into the buffer interfacing the CPU local bus and system bus whereafter the CPU can go on to initiate a subsequent cycle. The cache control system (including the cache controller) can then monitor completion of the write to memory.
Microcomputer systems comprising an 80386 processor and an 82385 cache controller are arranged to take advantage of posted write operations in exactly this fashion.
The 80386, and the signals it generates, are described in "Introduction to the 80386 Including the 80386 Data Sheet" from Intel (April 1986). The 82385 cache controller, and the signals it generates, are described in "82385 High Performance 32-Bit Cache Controller", available from Intel (July 1987).
Another attractive feature of the 80386 is its capability for operating with what is referred to as dynamic bus sizing. The 80386 is nominally a 32-bit machine, i.e. its data bus is 32 bits wide. Dynamic bus sizing refers to the capability of the 80386 processor to cooperate with not only 32-bit devices (memory, I/O, etc.) but with devices which do not have 32-bit capability, i.e. devices that cannot transfer 32 bits of data in a single cycle. There are for example a wide variety of memory and/or I/O devices which are 16-bit devices, i.e. they can transfer no more than 16 bits of data on a given cycle. Moreover, there are 8-bit I/O, memory and other devices. Such devices can transfer only eight bits of data on a given cycle.
The 80386 includes provision for a BS16 signal. When that signal is asserted, it has the following effect. In the event the 80386 has generated a 32-bit cycle, i.e. it has generated and/or expects to accept 32 bits of data, the assertion of the BS16 signal indicates to the 80386 that it is not operating with a 32-bit device. Assertion of the BS16 signal will, during the 32-bit cycle, automatically initiate the generation of a second cycle. By convention, any 16-bit device is arranged to transfer a predetermined group of 16 bits from the 32-bit data bus. The 80386, on the second cycle generated by the presence of the BS16 signal will place that group of 16 data bits which in the first cycle was not in the predetermined group of data bits onto a predetermined group of data lines which is associated with the predetermined group of 16 bits. Accordingly, in the first of the two cycles, the 16-bit device will transfer a given set of 16 bits of the 32 bits data space. In the second cycle, the 16-bit device will transfer another 16 bits of data so that, taken together, the two 16-bit cycles transfer 32 bits.
There is, however, an incompatibility between posted write cycles and dynamic bus sizing. That incompatibility arises for the following reason. Assume that the 80386 initiates a posted write. The data and address for the posted write cycle are latched into the buffered interface between the CPU local bus and the system bus. Although the write cycle is not yet completed, a ready signal is returned to the 80386. This simulates completion of the cycle so that the 80386 can initiate a following operation. Since the BS16 signal (which is returned to the 80386 to indicate the size of the device with which it is operating) is generated by the device, that signal is not generated until the device has recognized its address. Continuing with the example, and assuming that the device for which the posted write cycle is destined is in fact a 16-bit device, by the time the BS16 signal is returned to the 80386, it has already gone beyond the given operation and is engaged in the following operation. The 80386 therefore cannot generate the second, necessary cycle for the 16-bit device.
Therefore it is an object of the invention to selectively post write cycles. Since a posted write cycle is identified with an early generation of a ready signal to the 80386, the invention provides logic to generate the ready signal to the 80386 only when a posted write is appropriate. In accordance with the invention, all devices with which the 80386 can interact (I/O, memory, etc.) are classified as either cacheable devices or non-cacheable devices. The address assigned to all the devices has a tag which indicates whether the device is cacheable or non-cacheable. In accordance with the invention, an address decoder is provided on the CPU local bus. The address decoder responds to the asserted address on the CPU local bus to assert a NCA signal when the access is to a non-cacheable device.
82385 High Performance 32-Bit Cache Controller provides, at Section 1.3.3 that: PA0 "The 82385 allows the system designer to define areas of main memory as non-cacheable. The 80386 address bus is decoded and the decode output is connected to the 82385's non-cacheable access (NCA#) input. This decoding is done in the first 80386 bus state in which the non-cacheable cycle address becomes available. Non-cacheable read cycles resemble cacheable read miscycles, except that the cache and cache directory are uneffected. Non-cacheable writes, like all writes, are posted." PA0 "NCA# allows the designer to set aside a portion of main memory as non-cacheable. Potential applications include memory-mapped I/O and systems where multiple masters access dual ported memory via different buses."
"Non-cacheable cycles fall into one of two categories: cycles decoded as non-cacheable, and cycles that are by default non-cacheable according to the 82385's design. All non-cacheable cycles are forwarded to the 82385 local bus. Non-cacheable cycles have no effect on the cache or cache directory.
And under Section 3.3.2, the document indicates:
Furthermore, while the 82385 cache controller is arranged to generate the ready signal, that signal is not coupled to the 80386. Rather, that signal is coupled to logic means in accordance with the present invention. That logic means, depending upon a variety of other asserted signals, will generate a CPUREADY signal (to replace the ready signal) only when appropriate. More particularly, the logic means of the present invention generates the CPUREADY signal to allow posted write cycles only when the access is to a cacheable device, i.e. in the absence of the NCA signal. On the other hand, in the presence of the NCA signal, the logic means withholds generation of the CPUREADY signal so that in effect posted write operations do not occur.
Accordingly, in accordance with one feature, the invention provides a microcomputer system having:
a CPU local bus connecting a CPU and a cache subsystem, said CPU having means for posted write operations in response to receipt of a CPU ready signal prior to completion of a write operation,
system bus means connecting a random access memory and a plurality of addressable functional units, said system bus means returning a ready signal at completion of a write operation,
means for bidirectionally coupling said system bus and said CPU local bus, and
logic means for selectively preventing posted write operations, said logic means comprising:
a) address decoder means coupled to an address bus component of said CPU local bus for generating a NCA signal indicating assertion of an address on said CPU local bus outside an address range associated with said cache subsystem, and
b) means responsive to said NCA signal for withholding said CPU ready signal until receipt of said unit ready signal from one of said addressable functional units.

Data processing apparatus for selectively posting write cycles using the 82385 cache controller

International Business Machines Corporation


A method of neutralizing a polysiloxane having acidic residuals is disclosed. The method involves contacting a polysiloxane having acidic residuals with a carbon solid, and separating the carbon solid from the polysiloxane. This invention is particularly useful to neutralize residual acid polymerization catalysts in organopolysiloxanes.

Polysiloxanes are prepared in large scale industrial production by several techniques. Two common techniques used in industry are 1. hydrolysis of chlorosilanes to produce polysiloxane hydrolyzates, and 2. acid catalyzed equilibration of low molecular weight siloxanes. In both instances, the resulting crude polysiloxane products contain acidic residuals that must be neutralized before further use or storage. Otherwise, the resulting crude polysiloxane products will further polymerize with time, causing undesirable increases in viscosities (i.e. viscosity drift). Conventional acid neutralization techniques are commonly used to treat the resulting crude polysiloxane products. For example, the polysiloxane crude product is often contacted with a basic material such as sodium bicarbonate, calcium carbonate, or other solid particulates that are basic. While such techniques are sufficiently efficient to neutralize the majority of acidic residuals, small amounts often remain which still can lead to a viscosity drift upon storage. Thus, neutralization techniques that are more efficient than those presently known and practiced are desired. The present inventors have unexpectedly discovered such a new neutralization technique.

This patent is subject to a terminal disclaimer.

Method of neutralizing polysiloxanes containing acidic residuals


A layer system and a method for producing the layer system are provided, the layer system having a silicon layer, on which at least regionally a passivating layer is superficially deposited, the passivating layer having a first, at least largely inorganic partial layer and a second, at least largely polymer partial layer. The method includes producing on the silicon layer, a first, inorganic partial layer, and producing on this first partial layer a second, polymer partial layer, which form the passivating layer. The production of the intermediate layer occurs in such a way that the intermediate layer in its surface area adjoining the first partial layer is composed as the first partial layer, and the intermediate layer in its surface area adjoining the second partial layer is composed as the second partial layer. The composition of the intermediate layer transitions, either continuously or in steps, from the composition corresponding to the first partial layer into the composition corresponding to the second partial layer.

According to a method described, e.g., in published German patent document DE 44 20 962, self-supporting MEMS structures in silicon (MEMS="microelectromechanical structures") are produced by a combination of anisotropic and isotropic etching techniques, and so-called trenches or deep structures having vertical side walls are initially anisotropically etched into a silicon substrate using a reactive plasma. Once the desired etching depth is achieved, then, following a longer passivating step for depositing a Teflon-like film, a longer etching step is performed, during which first a Teflon polymer that formed on the etching ground of the trench is removed by ionic bombardment and subsequently the self-supporting MEMS structures to be produced are isotropically undercut. During this isotropic undercutting, the vertical side walls of the trenches are protected from an etch attack by the previously applied Teflon-like film. According to published German patent document DE 44 20 962, the isotropic undercutting of the MEMS structures produced proceeds in the silicon substrate material on a purely time-controlled basis.
For depositing the Teflon-like film, a fluorohydrocarbon having a fluorine to carbon ratio that is as low as possible, e.g., 2:1, may be used, fluorohydrocarbons such as C4F6, C5F8, C4F8 or C3F6 being suitable for this purpose. A process gas that generally etches isotropically and that provides fluorine radicals, such as SF6, may be used for etching silicon.
Published German patent document DE 198 47 455 describes limiting isotropic undercutting vertically with the aid of buried oxide layers. Particularly, an etch attack on the MEMS structures is prevented by an intermediate oxide separating the MEMS structure from a sacrificial layer made of silicon. Moreover, it is also described that, instead of using fluorine radicals from a plasma discharge, isotropic undercutting can also be performed using spontaneously and plasmalessly silicon-etching fluorine compounds such as XeF2, CIF3 or BrF3. Following adsorption and chemisorption on a silicon surface, these compounds spontaneously split off fluorine radicals, which results in an isotropic etching removal of the silicon through the formation of silicon tetrafluoride. At the same time there is a very high selectivity vis-à-vis non-silicon materials such as Teflon-like passivating layers or passivating layers of other compositions. In particular, photo-resist is attacked by CIF3 in a way that is practically not measurable, so that on the one hand it is particularly easy to passivate parts of a silicon wafer that are not to be etched, while on the other hand very thin passivating layers are already sufficient to ensure complete protection against an etch attack. In many cases, the so-called "native" silicon oxide normally present anyway on silicon surfaces is already able to withstand a chlorine trifluoride attack for several minutes without the silicon underneath it being etched.
A further aspect in the use of CIF3 (and in a limited way also BrF3) is the generally low reactivity of these highly oxidizing fluorine compounds vis-à-vis silicon, which has the result that an etching performed with them proceeds in a reaction-controlled manner over a wider parameter range and is not limited by a mass transport. This being the case, large undercutting widths can be achieved without a reduction of the etch rate due to a growing aspect ratio of the undercutting channels. With the aid of these gases it is possible, for example, for the lateral extension of the undercutting channels to amount to a multiple, e.g., 100 to 1000, of their vertical extension.
Finally, isotropic etching using these gases occurs entirely without ion action, which is of great advantage with regard to the desired isotropy and selectivity vis-à-vis non-silicon materials.
On the whole, CIF3 is in many respects an ideal gas for the selective removal of silicon or porous silicon within the scope of a sacrificial layer technique in that it allows in a very simple manner for the creation of self-supporting membrane structures with minimal restrictions on the freedom of design. In many cases, even a single etch opening is sufficient in order to achieve a complete undercutting of a membrane area on porous silicon for example.
On the other hand, the disadvantage in the use of CIF3, and with qualifications also of BrF3, is the fact that it very easily spreads unchecked via microchannel structures or even nanochannel structures, so that there is a great danger of it creeping extremely quickly behind deposited passivating layers, for example Teflon-like side wall passivating layers described in published German patent document DE 42 41 045, via micro- or nanocracks in the interface area to the silicon.
Thus, a Teflon-like plasma passivating layer produced from C4F8 or C3F6 has sufficiently many microchannels or nanochannels in the interface area to the silicon below so as to expose, starting from a single opening, for example on the etching ground of the initially produced trench, the entire MEMS structure over a large area to a CIF3 etch attack in spite of the deposited Teflon-like passivation. A typical defect pattern in this regard is that structures, in which the etching ground was previously cleared of a passivating teflon polymer with the help of ions as described in published German patent document DE 42 41 045, are massively attacked by etching on the entire, generally passivated side wall surface, while structures, in which the etching ground had a remaining, few nanometers thick coating of a Teflon-like polymer, nowhere show signs of an etch attack, even after a long period. The cause of this problem are the microchannels or nanochannels, explained above, in the interface area between the Teflon passivation, which generally adheres poorly to silicon, and the silicon surface, which allow etching gas CIF3 access to the silicon at undesired places.
An object of the present invention is to provide a passivating layer on a silicon layer, as well as a method for producing such a passivating layer on a silicon layer, which achieves a reinforced passivation of the interface between the passivating layer and the silicon layer by preventing the formation of, or alternatively by closing, undesired microscale or nanoscale channels, through which otherwise an uncontrolled etch attack, particularly by an isotropically etching gas such as CIF3 or BrF3, would occur. In addition, it should be possible to integrate the method and the obtained layer system with the passivating layer into plasma etching methods using photo-resist masking for producing trenches and self-supporting structures.

Layer and system with a silicon layer and a passivation layer, method for production of a passivation layer on a silicon layer and use thereof


First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.

Circuits can be prone to defects introduced during a manufacturing process. To test for defects, a scan input may be applied to scan channels, and the result of the scan input that is applied to the scan channels may be analyzed. The test may include large numbers and variations of scan inputs being applied to scan channels of the circuit. The tests may take a great amount of time, produce large amounts of data for analysis, and require large amounts of resources for that analysis.

International Business Machines Corporation


In a microwave band-pass filter provided with a main line having an input terminal and an output terminal on both ends thereof, first, second, third and fourth open-ended stubs having lengths L1, L2, L3 and L4 connected electrically in parallel to the main line at intervals L0, L0' L0", respectively. The lengths of two of the four open-ended stubs are selected to be substantially equal to a quarter of the wavelength of the first stop-band frequency signal on the band lower than the pass-band, and the lengths of the others thereof are selected to be substantially equal to a quarter of the wavelength of the second stop-band frequency signal on the band higher than the pass-band. In this case, the insertion loss thereof steeply increases on a boundary band from one stop-band to the pass-band. In particular, there can be obtained the microwave band-pass filter having a simpler structure, in which the insertion loss steeply increases on the band higher or lower than the pass-band, and the insertion loss on the band lower or higher than the pass-band is relatively large over a relatively wide band, respectively.

1. Field of the Invention
The present invention relates to a microwave band-pass filter, and more particularly, to a microwave band-pass filter using a transmission line such as a strip line, a micro-strip line or the like, which has a frequency characteristic of an insertion loss steeply increasing on one outside of the pass-band thereof.
2. Description of the Related Art
Conventionally, there have been used filters in order to take out a desirable signal on a predetermined band, or to reject signals or noise other than a desirable signal. In particular, when a frequency of the desirable signal to be taken out is located between frequencies of signals to be rejected, or when a stop-band is located on both the outsides higher and lower than a pass-band, there is used a band-pass filter.
FIG. 1 shows a conventional microwave band-pass filter of this type, which comprises resonators, each resonator composed of a half-wavelength strip line having both the open ends. Referring to FIG. 1, between input and output terminals, there are formed between a dielectric substrate 500 and another dielectric substrate (not shown), an input strip line 3, three resonators 5 and an output strip line 4 so that the input strip line 3 is electrically connected through an electromagnetic coupling to the first resonator 5 over a quarter of the wavelength, the first resonator 5 is electrically connected through an electromagnetic coupling to the second resonator 5 over a quarter of the wavelength, the second resonator 5 is electrically connected through an electromagnetic coupling to the third resonator 5 over a quarter of the wavelength, and the third resonator 5 is electrically connected through an electromagnetic coupling to the output strip line 4 over a quarter of the wavelength.
In the conventional microwave band-pass filter shown in FIG. 1, when the number of stages of the resonators 5 is increased, the insertion loss on the band on the outside of the pass-band can be steeply increased. However, each of the resonators 5 has a relatively low unloaded Q such as about several hundreds at about 10 GHz. Therefore, when the number of stages thereof is increased, the microwave band-pass filter is increased in size, and also the insertion loss in the pass-band increases. Accordingly, it is extremely difficult to obtain a microwave band-pass filter having a relatively low insertion loss on the pass-band and having a frequency characteristic of the insertion loss steeply increasing on the outside of the pass-band.

Microwave band-pass filter having frequency characteristic of insertion loss steeply increasing on one outside of pass-band

Matsushita Electric Industrial Co., Ltd.


The present disclosure provides methods for detecting a high-risk phenotype of a mast cell tumor (MCT) in a biological sample from a mammal, preferably a dog. Kits, PCR probes and primers to detect high-risk MCT are also provided.

2.1. Introduction
Mast cell tumors (MCTs) are a common form of skin tumor in the domestic dog, accounting for up to 20% of all skin cancers in this species (Finnie and Bostock, 1979, Rothwell et al., 1987, Villamil et al., 2011). The clinical behavior of MCTs varies widely from benign tumors, which can be cured by surgical removal alone, to highly malignant tumors that exhibit aggressive biologic behavior and high rates of metastasis, even in dogs treated with a combination of surgery, radiation therapy and chemotherapy. This variable biological behavior of MCTs poses a clinical challenge to veterinary clinicians.
Treatment decisions are made based on the presence or absence of prognostic factors, such as histological grading, clinical stage, and expression of cell proliferation markers. Among many prognostic indicators, histopathological grading of tumors with Patnaik's 3-tier (grades 1-3, with grade 3 being the most malignant) and Kiupel's 2-tier grading (either low or high grade) schemes has been widely used for the prognostication and treatment decision (Patnaik et al., 1984, Kiupel et al., 2011). These schemes are based on consideration of histological features such as cellular morphology, mitotic index and extent of tissue involvement. These histological features, however, can be subjective, leading to inter-observer difference in grading. In addition, histopathological grading requires a tumor biopsy, which may involve general anesthesia and costly and potentially invasive surgical procedures. The need for a reliable, non-invasive prognostic test for canine MCTs remains paramount.
Numerical and structural chromosomal abnormalities are hallmarks of cancer. Such changes to the genome have been utilized widely as diagnostics and prognostics in a range of human cancers (Mitelman et al., 2007, Frohling and Dohner, 2008, Hanahan and Weinberg, 2011). Recent advancement in genomics technology now allows us to analyze the genetic abnormalities in the dog at a genome-wide level (Breen, 2009). DNA copy number changes correlated with prognosis have a potential to offer a molecular means of predicting outcome as well as identification of potential therapeutic targets. Genome-wide copy number analysis has thus far not been performed in canine MCTs, with the exception of a single MCT cell line (Lin et al., 2009).

Methods of mast cell tumor prognosis and uses thereof


A system and method for estimating optimal atrioventricular delay values for use in pacing the ventricles. Both the intrinsic inter-atrial conduction delay and the intrinsic atrioventricular conduction delay are determined for the patient and then the preferred atrioventricular pacing delay is derived therefrom. By taking into account intrinsic inter-atrial delay along with intrinsic atrioventricular delay, a more reliable estimate of the true optimal atrioventricular delay values for the patient can be achieved than with techniques that only take into account intrinsic atrioventricular delay values. In one example, the technique uses intracardiac electrogram (IEGM) signals and surface electrocardiogram (EKG) signals and hence can be performed by an external programmer without requiring Doppler echocardiography or other cardiac performance monitoring techniques. In another example, wherein the implanted device is equipped with a coronary sinus lead, the technique uses only IEGM signals and hence can be performed by the device itself.

Implantable cardiac stimulation devices, particularly pacemakers and implantable cardioverter defibrillators (ICDs), are usually configured to be used in conjunction with an external programmer that enables a physician to program the operation of an implanted device to, for example, control the specific parameters by which the pacemaker detects arrhythmia conditions and responds thereto. For instance, the physician may specify the sensitivity with which the pacemaker or ICD senses electrical signals within the heart and also specify the amount of electrical energy to be employed in pacing pulses or defibrillation shocks. Another common control parameter is the A-VP delay, which for dual chamber devices specifies the time delay between a paced or sensed (i.e. native) atrial event and a paced ventricular event. Additionally, the external programmer may be configured to receive and display a wide variety of diagnostic information detected by the implantable device, such as intracardiac electrogram (IEGM) signals sensed by the device, as well as diagnostic data from other sources, such as surface electrocardiogram (EKG) devices.
Herein, "A" is generally used to refer to atrial events, whether paced or sensed. "V" is used to generally refer to ventricular events, whether paced or sensed. In circumstances where it is necessary to distinguish between paced and sensed events, an "S" or "P" is appended. Hence, AS refers to a sensed atrial event, whereas AP refers to paced atrial event. VS refers to a sensed ventricular event, whereas VP refers to a paced ventricular event. A-VP represents the delay between either a paced or sensed atrial event, and a paced ventricular event. In addition, where appropriate, an "L" or "R" subscript is employed to distinguish between the left and right chambers of the heart. For example, APR refers to a paced event in the right atrium. VSR refers to a sensed event in the right ventricle. Hence, APR-VSR represents the delay between a paced event in the right atrium and a sensed event in the right ventricle. Sensed events are also referred to herein as depolarizations as they are representative of electrical depolarization of myocardial tissue. Paced events are also referred to herein as evoked responses. Paced events in the atria are triggered by A-pulses. Paced events in the ventricles are triggered by V-pulses. Finally, the term "intrinsic delay", as used herein, refers to the delay between a paced or sensed event in one chamber and a subsequent depolarization in another chamber. For example, an "intrinsic atrioventricular delay" refers to the delay between a paced or sensed atrial event and a subsequent sensed ventricular event, e.g. an AS-VS or AP-VS delay. An "intrinsic inter-atrial delay" refers to the delay between a paced or sensed event in one atrial chamber and a subsequent sensed event in the other atrial chamber, e.g. an ASR-ASL or APR-ASL.
For many patients, particularly those with congestive heart failure (CHF), it is desirable to identify a set of control parameters that will yield optimal cardiac performance (also referred to as hemodynamic performance). Cardiac performance is a measure of the overall effectiveness of the cardiac system of a patient and is typically represented in terms of stroke volume or cardiac output. Stroke volume is the amount of blood ejected from the left ventricle during systole in a forward direction. Cardiac output is the volume of blood pumped by the left ventricle per minute (or stroke volume times the heart rate). In view of the importance of maintaining optimal cardiac performance, especially for patients with compromised cardiac function, it would be desirable to provide improved techniques for use with pacemakers or ICDs for identifying pacing control parameters that optimize cardiac performance, particularly to reduce the degree of heart failure and valvular regurgitation. It is to this end that aspects of the invention are generally directed.
It is particularly desirable to identify A-VP delay values providing the best cardiac performance. In normal patients, the electrical conduction through the AV node is intact, and the body automatically adjusts the delay via the circulating hormones and the autonomic nervous system according to its physiologic state. It is well known, for example, that in normal patients the intrinsic AS-VS delay shortens with increasing heart rate associated with a physiologic stress such as exercise. For patients with abnormal AV node conduction or complete heart block, a pacemaker can control the A-VP pacing delay by delivering a ventricular pacing pulse at a software-controlled delay after an atrial pace or atrial sensed event. Since the optimum A-VP delay varies from person to person, this parameter should be optimized on an individual basis.
Conventionally, the physician attempts to program the A-VP delay (or other parameters) for a given patient by using an external programmer to control the device implanted within the patient to cycle through a set of different A-VP delay values. For each value, the implanted device paces the heart of the patient for at least a few minutes to permit hemodynamic equilibration, then the physician records a measure of the resulting cardiac performance, measured, for example, using Doppler echocardiography. The A-VP delay value that yields the best cardiac performance is then selected and programmed into the device. However, this is a time consuming and potentially expensive procedure. As a result, some physicians do not bother to optimize A-VP delay in many of their patients. Rather, A-VP delay is merely set to a default value and is adjusted only if the patient does not respond well to pacing therapy or complains that they do not feel well. Hence, many patients are not paced at their particular optimal A-VP delay value and thus do not obtain the maximal potential benefit from the improved cardiac performance that could be gained with the optimal A-VP delay. Moreover, even in circumstances wherein A-VP delay is optimized by the physician using, for example, Doppler echocardiography, the time and associated costs are significant. In addition, the optimal A-VP delay for a particular patient may change with time due to, for example, progression or regression in CHF, changes in medications, and/or changes in overall fitness. However, with conventional optimization techniques, the A-VP delay is re-optimized, if at all, only during specially scheduled follow-up sessions with the physician to allow access to the noninvasive testing equipment such as Doppler-echocardiography, which may be months or perhaps years apart.
Accordingly, it is would be highly desirable to provide improved techniques for more easily and reliably determining optimal or otherwise preferred A-VP delay values for a particular patient. At minimum, such techniques should be designed so as to be performed by an external programmer using only IEGM data received from the implanted device along with otherwise routine surface EKG data, so that Doppler echocardiography or other expensive and time consuming cardiac performance monitoring techniques are not required. Moreover, depending upon the implanted device and its leads, the improved techniques should be designed so as to be performed by the implanted device itself, without even surface EKG data. The latter technique would permit the optimal A-VP delay to be frequently and automatically updated so as to respond to changes within the patient. It is to these ends that aspects to the invention are more specifically directed.
Note that some techniques have been proposed for determining an optimal A-VP delay value based on IEGM data. For example, it has been proposed that the A-VP delay be set to A-VP=0.7 A−VSR−55 ms. Although this allows the A-VP pacing delay to be set automatically by the implanted device, it is not believed that the formula reliably provides the optimal delay value for many patients. In particular, the formula only takes into account the intrinsic delay from the atria to the right ventricle (A-VSR) but does not take into account the intrinsic inter-atrial delay or the intrinsic delay from the atria to the left ventricle, which the present inventors believe can significantly affect the optimal A-VP delay in at least some patients. In addition, it is desirable to separately determine optimal delay values for paced and sensed events, i.e. separate values for AS-VP and for AP-VP. Accordingly, still other aspects of the invention are directed to providing improved optimization techniques that take into account intrinsic inter-atrial delay, intrinsic delay times to both the left and right ventricles, and which provide separate optimal delay values based on paced and sensed atrial events.

System and method for determining optimal atrioventricular delay based on intrinsic conduction delays


A method for forming dual silicide regions includes forming semiconductor regions having a first thickness and a second thickness different from the first thickness and forming a dielectric layer over the semiconductor regions. Holes are opened up in the dielectric layer down to a first depth corresponding with the first or second thickness leaving a thickness of the dielectric layer over the other of the first or second thickness. A first silicide is formed at the first depth in the holes using a first deposited material. The holes are extended through the thickness of the dielectric layer to reach a second depth. A second silicide is formed at the second depth in the holes using a different material than the first deposited material.

1. Technical Field
The present invention relates to semiconductor devices, and more particularly to complementary metal oxide semiconductor devices having different silicide region materials depending on device dopant conductivity and employed in a single integration process.
2. Description of the Related Art
Silicides are often formed between contact metals and semiconductor materials, for example, for sources and drains of integrated circuit transistors. In many instances, complementary metal oxide semiconductor (CMOS) devices are employed in semiconductor devices and are processed side-by-side using the same materials and process parameters. Oftentimes, the process parameters and materials have different effects on performance between p-type field effect transistors (pFETs) versus n-type FETs (nFETs). For example, Ti silicide seems to improve nFET contact resistance due to its better thermal stability; however, Ti silicide degrades pFET contact resistance due to the contact interface resistivity as compared to other materials, like, NiSi.

Dual silicide regions and method for forming the same

INTERNATIONAL BUSINESS MACHINES CORPORATION


A downhole tool comprising a probe, wherein the probe comprises: a first inlet having an elongated cross-sectional shape, and a second inlet surrounding the first inlet. The downhole tool further comprises at least one pump configured to draw fluid from a subterranean formation through the first and second inlets.

1. Field of the Invention
The present invention relates to techniques for performing formation evaluation of a subterranean formation by a downhole tool positioned in a wellbore penetrating the subterranean formation. More particularly, the present invention relates to techniques for reducing the contamination of formation fluids drawn into and/or evaluated by the downhole tool.
2. Background of the Related Art
Wellbores are drilled to locate and produce hydrocarbons. A downhole drilling tool with a bit at and end thereof is advanced into the ground to form a wellbore. As the drilling tool is advanced, a drilling mud is pumped through the drilling tool and out the drill bit to cool the drilling tool and carry away cuttings. The fluid exits the drill bit and flows back up to the surface for recirculation through the tool. The drilling mud is also used to form a mudcake to line the wellbore.
During the drilling operation, it is desirable to perform various evaluations of the formations penetrated by the wellbore. In some cases, the drilling tool may be provided with devices to test and/or sample the surrounding formation. In some cases, the drilling tool may be removed and a wireline tool may be deployed into the wellbore to test and/or sample the formation. In other cases, the drilling tool may be used to perform the testing or sampling. These samples or tests may be used, for example, to locate valuable hydrocarbons.
Formation evaluation often requires that fluid from the formation be drawn into the downhole tool for testing and/or sampling. Various devices, such as probes, are extended from the downhole tool to establish fluid communication with the formation surrounding the wellbore and to draw fluid into the downhole tool. A typical probe is a circular element extended from the downhole tool and positioned against the sidewall of the wellbore. A rubber packer at the end of the probe is used to create a seal with the wellbore sidewall. Another device used to form a seal with the wellbore sidewall is referred to as a dual packer. With a dual packer, two elastomeric rings expand radially about the tool to isolate a portion of the wellbore therebetween. The rings form a seal with the wellbore wall and permit fluid to be drawn into the isolated portion of the wellbore and into an inlet in the downhole tool.
The mudcake lining the wellbore is often useful in assisting the probe and/or dual packers in making the seal with the wellbore wall. Once the seal is made, fluid from the formation is drawn into the downhole tool through an inlet by lowering the pressure in the downhole tool. Examples of probes and/or packers used in downhole tools are described in U.S. Pat. Nos. 6,301,959; 4,860,581; 4,936,139; 6,585,045; 6,609,568 and 6,719,049 and US Patent Application No. 2004/0000433.
The collection and sampling of underground fluids contained in subsurface formations is well known. In the petroleum exploration and recovery industries, for example, samples of formation fluids are collected and analyzed for various purposes, such as to determine the existence, composition and producibility of subsurface hydrocarbon fluid reservoirs. This aspect of the exploration and recovery process can be crucial in developing drilling strategies and impacts significant financial expenditures and savings.
To conduct valid fluid analysis, the fluid obtained from the subsurface formation should possess sufficient purity, or be virgin fluid, to adequately represent the fluid contained in the formation. As used herein, and in the other sections of this patent, the terms "virgin fluid", "acceptable virgin fluid" and variations thereof mean subsurface fluid that is pure, pristine, connate, uncontaminated or otherwise considered in the fluid sampling and analysis field to be sufficiently or acceptably representative of a given formation for valid hydrocarbon sampling and/or evaluation.
Various challenges may arise in the process of obtaining virgin fluid from subsurface formations. Again with reference to the petroleum-related industries, for example, the earth around the borehole from which fluid samples are sought typically contains contaminates, such as filtrate from the mud utilized in drilling the borehole. This material often contaminates the virgin fluid as it passes through the borehole, resulting in fluid that is generally unacceptable for hydrocarbon fluid sampling and/or evaluation. Such fluid is referred to herein as "contaminated fluid." Because fluid is sampled through the borehole, mudcake, cement and/or other layers, it is difficult to avoid contamination of the fluid sample as it flows from the formation and into a downhole tool during sampling. A challenge thus lies in minimizing the contamination of the virgin fluid during fluid extraction from the formation.
FIG. 1 depicts a subsurface formation 16 penetrated by a wellbore 14. A layer of mud cake 15 lines a sidewall 17 of the wellbore 14. Due to invasion of mud filtrate into the formation during drilling, the wellbore is surrounded by a cylindrical layer known as the invaded zone 19 containing contaminated fluid 20 that may or may not be mixed with virgin fluid. Beyond the sidewall of the wellbore and surrounding contaminated fluid, virgin fluid 22 is located in the formation 16. As shown in FIG. 1, contaminates tend to be located near the wellbore wall in the invaded zone 19.
FIG. 2 shows the typical flow patterns of the formation fluid as it passes from subsurface formation 16 into a downhole tool 1. The downhole tool 1 is positioned adjacent the formation and a probe 2 is extended from the downhole tool through the mudcake 15 to the sidewall 17 of the wellbore 14. The probe 2 is placed in fluid communication with the formation 16 so that formation fluid may be passed into the downhole tool 1. Initially, as shown in FIG. 1, the invaded zone 19 surrounds the sidewall 17 and contains contamination. As fluid initially passes into the probe 2, the contaminated fluid 20 from the invaded zone 19 is drawn into the probe with the fluid thereby generating fluid unsuitable for sampling. However, as shown in FIG. 2, after a certain amount of fluid passes through the probe 2, the virgin fluid 22 breaks through and begins entering the probe. In other words, a more central portion of the fluid flowing into the probe gives way to the virgin fluid, while the remaining portion of the fluid is contaminated fluid from the invasion zone. The challenge remains in adapting to the flow of the fluid so that the virgin fluid is collected in the downhole tool during sampling.
Formation evaluation is typically performed on fluids drawn into the downhole tool. Techniques currently exist for performing various measurements, pretests and/or sample collection of fluids that enter the downhole tool. Various methods and devices have been proposed for obtaining subsurface fluids for sampling and evaluation. For example, U.S. Pat. No. 6,230,557 to Ciglenec et al., U.S. Pat. No. 6,223,822 to Jones, U.S. Pat. No. 4,416,152 to Wilson, U.S. Pat. No. 3,611,799 to Davis and International Pat. App. Pub. No. WO 96/30628 have developed certain probes and related techniques to improve sampling. However, it has been discovered that when the formation fluid passes into the downhole tool, various contaminants, such as wellbore fluids and/or drilling mud, may enter the tool with the formation fluids. These contaminates may affect the quality of measurements and/or samples of the formation fluids. Moreover, contamination may cause costly delays in the wellbore operations by requiring additional time for more testing and/or sampling. Additionally, such problems may yield false results that are erroneous and/or unusable. Other techniques have been developed to separate virgin fluids during sampling. For example, U.S. Pat. No. 6,301,959 to Hrametz et al. and discloses a sampling probe with two hydraulic lines to recover formation fluids from two zones in the borehole. Borehole fluids are drawn into a guard zone separate from fluids drawn into a probe zone. Despite such advances in sampling, there remains a need to develop techniques for fluid sampling to optimize the quality of the sample and efficiency of the sampling process.
It is, therefore, desirable that the formation fluid entering into the downhole tool be sufficiently 'clean' or 'virgin' for valid testing. In other words, the formation fluid should have little or no contamination. Attempts have been made to eliminate contaminates from entering the downhole tool with the formation fluid. For example, as depicted in U.S. Pat. No. 4,951,749, filters have been positioned in probes to block contaminates from entering the downhole tool with the formation fluid. Additionally, as shown in U.S. Pat. No. 6,301,959 to Hrametz, a probe is provided with a guard ring to divert contaminated fluids away from clean fluid as it enters the probe.
Despite the existence of techniques for performing formation evaluation and for attempting to deal with contamination, there remains a need to manipulate the flow of fluids through the downhole tool to reduce contamination as it enters and/or passed through the downhole tool. It is desirable that such techniques are capable of diverting contaminants away from clean fluid. It is further desirable that such techniques be capable of one of more of the following, among others: analyzing the fluid passing through the flowlines, selectively manipulating the flow of fluid through the downhole tool, responding to detected contamination, removing contamination and/or providing flexibility in handling fluids in the downhole tool.
In considering existing technology for the collection of subsurface fluids for sampling and/or evaluation, there remains a need for techniques capable of providing one or more, among others, of the following attributes: the ability to selectively collect virgin fluid apart from contaminated fluid; the ability to separate virgin fluid from contaminated fluid; the ability to optimize the quantity and/or quality of virgin fluid extracted from the formation for sampling; the ability to adjust the flow of fluid according to the sampling needs; the ability to control the sampling operation manually and/or automatically and/or on a real-time basis.
Techniques have also been developed to evaluate fluid passing through the tool to determine contamination levels. In some cases, techniques and mathematical models have been developed for predicting contamination for a merged flowline. See, for example, Published PCT Application No. WO 2005065277 and PCT Application No. 00/50876, the entire contents of which are hereby incorporated by reference. Techniques for predicting contamination levels and determining cleanup times are described in P. S. Hammond, "One or Two Phased Flow During fluid Sampling by a Wireline Tool," Transport in Porous Media, Vol. 6, p. 299-330 (1991), the entire contents of which are hereby incorporated by reference. Hammond describes a semi-empirical technique for estimating contamination levels and cleanup time of fluid passing into a downhole tool through a single flowline.
While techniques have been developed for contamination monitoring, such techniques relate to single flowline applications. It is desirable to provide contamination monitoring techniques applicable to multi-flowline operations. It is further desirable that such techniques provide one or more of
the following capabilities: analyzing the fluid flow to detect contamination levels, estimate time to clean up contamination, calibrate flowline measurements, cross-check flowline measurements, selectively combine and/or separate flowlines, determining contamination levels and compare flowline data to known values. To this end, the present invention seeks to optimize the formation evaluation process.


A robot remote manipulation system is provided, including a bipedal walking robot and a remote manipulation device for remotely manipulating the bipedal walking robot. The robot is connected to the remote manipulation device via a communication network and controlled by controlling data from the remote manipulation device. In the system, the remote manipulation device comprises a pair of bilateral mechanical rotating elements providing a quantity of motion for each bilateral leg of the bipedal walking robot; and a controlling data transmitter for transmitting controlling data corresponding to the quantities of motion to the bipedal walking robot. The bipedal walking robot comprises a controlling data receiver for receiving the controlling data transmitted from the remote manipulation device; and a leg motion controller for processing the received controlling data and causing the bilateral legs to move forward or backward.

1. Field of the Invention
The present invention generally relates to a robot remote manipulation system and a robot remote manipulation device, and specifically relates to such systems and devices that remotely manipulate bipedal walking robots via communication networks.
2. Description of the Related Art
A variety of robot remote manipulation systems have been developed recently. As one prior art robot remote manipulation system, Tmsuk 04 (Robocon magazine No. 18, pp. 20–23, published by Ohm-sha in 2001) is known in which a robot can be remotely manipulated using a PHS line. In the Tmsuk 04 technology, an operator operates a master arm to control the motion of a robot as a slave. Another prior art manipulation system uses a joy stick. By moving the joy stick forward, backward, rightward or leftward, the moving direction, the length of a step and the walking speed of a robot can be controlled.
There is known one other prior bipedal walking robot remote manipulation system in which commands are inputted or a moving destination and route are inputted.
Such conventional bipedal walking robot remote manipulation systems, however, have comparatively large sizes. Further, while manipulating a robot in the conventional systems, it is not easy to be aware of forces applied to the legs of the robot and therefore it is not easy to control the robot.

Robot remote manipulation system and remote manipulation device


To create a backup of a live (running) virtual machine, a backup agent may take a snapshot of the virtual machine, backup the virtual machine from the snapshot disk, and delete the snapshot. Deleting the snapshot initiates a snapshot consolidation process where delta disks of the virtual machine are collapsed. A virtual disk layer sets up a mirror driver between a current virtual disk and a target virtual disk. Data sectors of the delta disk are copied over to the target virtual disk in a single pass, while the mirror driver mirrors write request for the current virtual disk to the target virtual disk.

Computer virtualization is a technique that involves encapsulating a physical computing machine platform into a virtual machine that is executed under the control of virtualization software on a hardware computing platform, or "host." A virtual machine has both virtual system hardware and guest operating system software. Virtual system hardware typically includes at least one "virtual disk," which is represented as a single file or a set of files in the host's file system, and appear as a typical storage drive to the guest operating system. The virtual disk may be stored on the host platform's local storage device (if any) or on a remote storage device. Typically, a virtual machine uses the virtual disk in the same manner that a physical storage drive is used, to store the guest operating system, application programs, and application data.
A snapshot of the virtual disk can be taken at a given point in time to preserve the content within the virtual disk at that point in time, referred to herein as a "point in time (PIT) copy of the virtual disk." Once a snapshot of a virtual disk is created, subsequent writes received from the guest operating system to the virtual disk are captured in a "delta disk" so that the preserved content, i.e., the base PIT copy, is not modified. The delta disk is an additional file associated with the virtual disk. At any given time, it represents the difference between the current state of the virtual disk and the state at the time of the previous snapshot. Thus, the base PIT copy remains intact and can be reverted back to or can be used as a base template to create writable virtual disk clones. Multiple PIT copies of the virtual disk can be created at various points in time by creating snapshots of snapshots. Each snapshot corresponds to a separate delta disk that is overlaid on a previous delta disk.
Creating multiple snapshots of a virtual disk results in a long chain of delta disks, each corresponding to a snapshot of the virtual disk. Every read I/O operation to the virtual disk has to traverse through each delta disk associated with the virtual disk to get the latest copy of the data from a delta disk. Therefore, an increased number of delta disks negatively impacts the performance of read I/O operations to the virtual disk. Performance of such I/O operations may be increased when redundant delta disks are consolidated to reduce the number of delta disk in a given chain. Redundant delta disks are associated with PIT copies of the virtual disk that are no longer needed. For example, a PIT copy of the virtual disk may be created for backing up or testing purposes and becomes redundant upon backup completion or when the testing is successful.
Delta disks are consolidated by merging PIT copies such that a particular delta disk can be deleted. Merging the PIT in copies typically involves copying out data from the delta disk to be deleted (the "source delta disk") to the main primary disk or an adjacent delta disk (either, referred to generally as the "destination delta disk"). Copying data in such a manner from the source delta disk to the destination delta disk involves data movement operations that cost a significant amount of I/O and CPU resources. As the size of data in the source delta disk increases, the data movement operations that are necessary to consolidate two delta disks become very I/O intensive. Thus, during consolidation, the I/O performance for the virtual disk as a whole degrades drastically when a delta disk consolidation operation is in process. In some cases, the consolidation process might fail altogether depending on the I/O workload of the virtual disk itself.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

Online snapshot consolidation using I/O mirroring


Adaptors and devices for displaying decorative finials. The adaptors and devices of the invention include devices for engaging various table lamps and utilitarian objects, including table lamps having clip-on lamp shades and European standard table lamps, to extend the visual benefits of decorative finials beyond the application of a single finial atop an American standard table lamp.

Finials are ornamental objects whose primary known use is to beautify table lamps. Finials include a decorative portion, which varies in design, and a bore having an internal thread for mating the finial with a finial receiver, also called a finial stud, of a table lamp. The decorative portion of finials is known to be designed and manufactured in many different sizes, shapes and styles, with each different design providing a unique visual appearance. In contrast, the bore of finials is generally of a common size so that the bore is compatible with most finial receivers, which typically have a size 1/4"-27 external thread. Thus, the table lamp user is usually able to select a finial of a preferred size, shape and style from among a wide variety of ornamental designs.
It has long been known to use a single finial to beautify the top of an American standard table lamp. The base of such lamps typically has a harp extending upward from a lamp socket. Projecting upward from the top of the harp is a screw for receiving the center ring of a lamp shade. When the center ring is placed on the harp screw, the lamp shade becomes loosely suspended on the harp. The shade is then secured to the lamp base by mating the threaded bore of a finial with the harp screw and tightening down the finial until the center ring becomes fixed in place between the finial and the screw. After mating, the decorative portion of the finial remains visible above the lamp shade, creating an aesthetically pleasing visual impression. The finial thus helps secure the lamp shade to the lamp base while at the same time beautifying the top of the lamp.
While the visual benefits of finials are well known in the above-described application, the advantageous use of finials has been limited primarily to a single finial at the top of an American standard table lamp. Finials are not known to have been used to beautify other parts of American standard table lamps, such as the lamp shade and the bottom of the lamp base, as there is no ready means at those locations to attach a finial. Further, multiple finials are not known to have been displayed atop an American standard table lamp for added beautification, as the top of such lamps generally has only one harp screw for receiving a finial.
Moreover, finials are not known to have been displayed on table lamps designed in accordance with the European standard, because of differences in how the lamp shade is secured to the lamp base. In such table lamps, there is no harp extending upward from the lamp socket for receiving the lamp shade and finial. Instead, the lamp shade has a sunken center ring which is secured to the lamp base at the lamp socket.
Moreover, while finials have been displayed on table lamps having clip-on lamp shades, known devices to adapt such table lamps to receive a finial have certain disadvantages. In such table lamps, the lamp shade is secured to the lamp base using flexible wire clips, which grasp the light bulb mounted in the lamp socket. Known devices to adapt the wires of such lamp shades to receive a finial have proven difficult to install and often unable to maintain the finial in the desired upright position.
Moreover, the visual benefits of finials are not known to have extended to other utilitarian devices such as bookends, desktop phones, picture frames, candles, bottle tops, door knobs and electrical outlets, and have not extended to aesthetic devices, such as flower arrangements.


A test handler is provided for testing electronic devices having light-emitting elements. Electronic devices are mounted at a loading position, optical measurements are conducted at a test contact position where a testing device is located for optical communication with the light-emitting elements and then tested electronic devices are removed at an unloading position. Multiple test contactors hold the electronic devices and move them to and through the loading position, test contact position and unloading position in sequence. Each test contactor comprises a device contact point including electrical conductors which are connected to electrical contacts of the electronic device when the electronic device is mounted at the device contact point, and a retaining mechanism grips the electronic device at the device contact point such that the retaining mechanism does not obstruct the optical communication between the testing device and the light-emitting element at the test contact position.

Test handlers are used in the semiconductor industry for testing electronic devices, such as integrated circuits, semiconductor chips and the like. There is a constant demand for such electronic devices to be produced at less cost and in smaller dimensions, increasing the challenges faced when designing apparatus to test such electronic devices.
Test contactors comprised in test handlers generally position the electronic device for testing by a tester. Contact pins of the test contactor are connected to the electronic device during testing to make electrical contact with the device under test ("DUT"). The test contactor is usually incorporated as part of or subsequently coupled to a tester depending on the type of device being tested.
In the case of light-emitting electronic or photonics devices, such as light-emitting diodes ("LEDs"), the tester typically includes sensors for measuring the intensity and/or quality of the light emitted. A challenge faced when testing LEDs is to be able to effectively observe the light emitted by the LED with sensors which are located at a certain distance from the LED. An unblocked line of sight should preferably be maintained between the LED and the sensors while the device is held securely and electrically connected at the testing position.
One traditional type of test contactor for LEDs comprises an insulation socket with a contact pin incorporated in the socket. An LED is inserted into the insulation socket to make electrical contact with the contact pin so as to illuminate the LED. An optical test is then conducted. Thus, the position of the test contactor is fixed at the testing position. Automation of the testing process may comprise the steps of using a pick arm to transfer the LED to the insulation socket, inserting the LED into the insulation socket with the pick arm to make contact with the contact pin in order to light up the LED for testing, and then removing the LED from the insulation socket. A disadvantage of this approach is that the pick arm typically has to be positioned over the insulation socket, and therefore blocks some of the light emitted from the LED. The resulting test is hence less accurate since some of the light is blocked. The movement of the pick arm to pick and position one LED at a time at the insulation socket is also relatively slow.

Test handler including gripper-type test contactor


The present invention refers to a dry firing prevention device, especially for use in a nail gun with a drawer type magazine, in which the main body of the nail gun is equipped with a safety apparatus and a dry firing prevention device near a trigger. The dry firing prevention device is disposed on the magazine. When a nail pusher pushes nails until where last few nails are left, the nail pusher will contact with one end of the dry firing prevention device and the other end of the dry firing prevention device blocks the safety apparatus, so that the safety apparatus retains in a safety status to prevent the nail gun from dry firing, so as to prolong the lifetime of the nail gun.

Conventional depth adjusting devices of nail guns are generally installed inside the safety devices, for example, U.S. Pat. No. 6,170,729, U.S. Pat. No. 6,427,896 and US 2003/0019901 disclose that the adjusting devices and the safety devices are disposed on the outside of the barrels. The addition of other adjusting devices makes the whole structures more complicated and limited in stabilization. Besides, it is more inconvenient to make adjustment because of its vicinity to the muzzle of the barrel.
Such structure has shortcomings, such as unstable structure, inconvenience for use and complicated manufacture. Because the safety device is assembled by pieces, an adjustment assembly is additionally attached in the middle thereof, which will cause the safety device to shake while the adjustment assembly acts, so as to make the structure unstable and unable to locate precisely. Besides, the adjustment assembly is near the muzzle, it is unable to make an adjustment by one hand that presses the trigger while use. If it needs to adjust the depth of nailing frequently, which is inconvenient for use. Moreover, the connection between the adjustment assembly, the safety device and the trigger uses corresponding connection structure, it needs to design the corresponding connection structure individually for application of different safety devices and triggers, which is complicate to manufacture.
As for the shortcomings mentioned above, the inventor has a TW Appl. No. 93133904 adjustable safety device approved, which discloses that a main body of a nail gun is equipped with an adjusting assembly and a moving assembly between a trigger and a magazine. One end of an acting piece of the adjusting assembly is connected with the trigger. The acting piece is connected with a supporting piece, and the acting piece and one end of the supporting piece are coupled with a moving piece of the moving assembly. Meanwhile, the moving piece is connected with one end of an interlocking assembly of a safety device via a compressing piece. When adjusting the supporting piece, the distance between the acting piece and the moving piece can be controlled precisely, so as to precisely adjust the depth between the actuation point of the safety device and the muzzle. However this case does not consider that the nail gun is still dry firing while the nail is insufficient, which causes the damage of the structure of the nail gun and the firing device.

Dry firing prevention device for nail gun


A waterproof zipper consisting of a first zipper tape, a second zipper tape, and a zipper slider consisting of slide, a pressure plate and a pull tab is disclosed. The first zipper tape and the second zipper tape are specially configured to enhance the tensile strength and waterproof characteristics of the zipper. The pressure plate defines with the topmost edges of the two second stop walls of the slider a constraint space for holding down the first zipper tape and the second zipper tape to prevent accidental displacement of the zipper slider relative to the first and second zipper tapes.

1. Field of the Invention
The present invention relates to zip fasteners and more particularly, to a waterproof zipper, which has good tensile strength and waterproof characteristics. Embodiments provide a constraint space between a bottom edge of a pressure plate and the topmost edges of two second stop walls of a slider of a zipper slider thereof for enabling the zipper slider to be positively locked to the zipper tapes.
2. Description of the Related Art
A conventional zipper generally comprises two zipper tapes, each having an interlocking series of teeth, and a zipper slider slidable to force the two series of teeth into engagement with each other or to cause separation of the two series of teeth. However, if the zipper is accidentally vibrated, the zipper slider can be forced to displace, causing separation of the two series of teeth. Therefore, when a zipper is used in an article that needs to protect against wind and water (such as a raincoat), a shielding strip and a fastener must be provided at an outer side of the zipper so that the shielding strip can be locked to shield the zipper.


A method of recycling post-consumer polyester to obtain recycled polyester of sufficiently high purity to meet food packaging requirements is disclosed. The method includes cleaning comminuted pieces of post-consumer polyester to remove surface contaminants; melting the surface-cleaned post-consumer polyester pieces; extruding the post-consumer melt; blending the melt of post-consumer polyester with a melt of virgin polyester prepolymer; solidifying and pelletizing the blended melt while the virgin polyester prepolymer remains as prepolymer; and polymerizing the solid blended pellets in the solid state.

The widespread use of polymer-based products ("plastics") in consumer goods has lead to a corresponding interest in suitable methods for reclaiming or recycling as much of these products as is practical. The interest in such recycling is driven by several considerations. These include: environmental factors, principally occupation of landfills and other disposal issues; preservation of limited resources, because polymers are a product in the chain of petrochemicals that begins with crude oil; and economic interests, because the cost of post-consumer plastic is less related to the cost of raw materials, and instead is more dependent upon the cost of physically collecting and transporting post-consumer plastic objects to an appropriate facility for recycling. Additionally, public policy is expected to continue to emphasize environmental issues, and thus legal requirements for recycling are already in force in some jurisdictions, and are expected in others in the future.
Interest in post-consumer recycling has increasingly focused upon polyester (i.e. polyethylene terephthalate, "PET," and related compounds). More specifically, for several decades polyester found its widest use as a synthetic material for textile products. Because polyester is typically blended and textured when incorporated into yarns and fabrics, the task of recycling textile materials is quite different from the task of recycling molded polyester objects.
In more recent years, however, polyester chemistry and the techniques for molding polyester have developed to the point at which polyester has become widely used as a material for "disposable" beverage bottles. Accordingly, these polyester bottles, once disposed of, present a significant opportunity for economical and efficient recycling, provided appropriate techniques can be developed.
In this regard, the term "recycling" often tends to be used relatively broadly, but actually covers a number of different ways to reuse any given material. Thus, in one sense, if a polyester bottle is used to contain a non-food product liquid rather than being directly disposed of, it has been "recycled", but the term "recycled" is rarely applied to such follow-up use of an empty container. Instead, recycling is typically identified as falling into one of three general categories, which are also recognized by the U.S. Environmental Protection Agency (EPA) and the U.S. Food and Drug Administration (FDA). The first is primary recycling; the use of pre-consumer industrial scrap and salvage. The second is secondary recycling, which refers to the physical reprocessing (e.g., grinding and re-extruding) of the polymer. The third is tertiary recycling in which a polymer is reprocessed to isolate chemical components and reuse them in manufacturing a new product.
Because the present invention deals with post-consumer recycling, primary recycling will not be addressed further herein. As used herein, the term "post-consumer" refers to polyester objects (e.g. food containers or bottles) that have been disposed of after their initial use. Because such containers or bottles are generally treated as household trash, or even re-used for non-food compositions, they may contain various contaminants or contaminant residues when submitted for recycling.
With respect to polyester, tertiary recycling generally falls into one of several chemical processes that reduce polyester (typically polyethylene terephthalate) back into its component monomers (terephthalic acid and ethylene glycol) in some sort of depolymerizing step. Typical depolymerizing steps include methanolysis as for example practiced by Eastman Chemical Company, and Hoechst. Shell practices another process referred to as "glycolysis," and which mixes post-consumer polyester with glycol (and potentially other compounds) to break it back down into its component precursors.
Other recycling techniques provide methods for removing companion materials often used with polyester in consumer products. In this regard, U.S. Pat. No. 5,523,329 to Moore et al. for "Recovery of Polyester From Spent Film," which is commonly assigned with the pending application, describes a method of removing polyvinylidene (PVDC) from a polyester substrate, a combination which is often used, for example, as a substrate for photographic film and their emulsions.
In order to be used to package food products, any polymer whether virgin or recycled must meet the appropriate standards for food contact. As used herein, the term "virgin" refers to polymers made directly from chemical precursors, and because of which their purity is generally considered to be acceptably high. Thus, in seeking to produce a food quality polyester from post-consumer polyester, the recycling process must not only produce a reconstituted polyester with appropriate physical and chemical characteristics, but must also be sufficiently pure to meet food quality standards.
In the United States the FDA has generally taken the position that the levels of recycle related contaminants present in food contact articles must be low enough to ensure that the resulting "dietary exposure" to those substances is less than one-half part per billion (ppb). According to FDA calculations, the residual concentration of possible contaminants in the food packaging material should be no more than about 215 ppb. At these levels, if a contaminant were present in a polyester container made from recycled material, and if the contaminant was assumed to migrate entirely (100%) into the food, the concentration of the contaminant in the daily diet would be on the desired order of less than 0.5 ppb based on a 5 percent PET consumption factor (i.e. the FDA assumes that 5 percent of food is packaged in polyester).
At levels greater than about 215 ppb, migration studies can also be used to demonstrate that the concentration in a daily diet would still fall to 0.5 ppb or less.
As noted above, if a polymer such as polyester is manufactured from pure precursor components such as terephthalic acid and ethylene glycol, it can generally be produced in the desired purity ranges. Similarly, and as would be expected, if post-consumer polyester is reduced by glycolysis or methanolysis to the equivalent of pure starting materials, which are then re-reacted to form monomer and re-polymerized to form polymer, a similar purity level can be achieved. The disadvantage, however, of such processes is that by the very nature of their extensive chemical treatment, they are more expensive and less efficient than the processes for producing polyester from virgin precursors. Because one of the objects of recycling is to promote its economic attractiveness, recycling processes that are so elaborate as to offer economic disincentives tend to be used sparingly, and occasionally only in the face of legal requirements, rather than for their marketplace advantages.