A miniature electrochemical cell having a total volume that is less than 0.5 cc is described. The casing enclosure consists of a lower plate supporting a cylindrically-shaped can having an open upper end closed with a cover. The can is selectively coated with a dielectric material to provide electrical isolation of the to-be-housed active materials from the can sidewall. A glass-to-metal seal electrically isolates the lower plate from the can. An electrode assembly comprising a sandwich of cathode active material/separator/anode active material is housed in the casing. That way, the lower plate contacting the cathode active material is the positive terminal and the closing cover connected to the can and contacted to the anode active material serves as the negative cell terminal. An electrolyte filled into the casing activates the electrode assembly and the fill opening is sealed with a plug. The cell can be of either a primary or a secondary chemistry.

1. Field of the Invention
This invention relates to the conversion of chemical energy to electrical energy. More particularly, the present invention relates to an electrochemical cell having a total size or volume that is less than 0.5 cc. Such so-called miniaturized electrochemical cells enable numerous new and improved medical device therapies. Miniature electrochemical cells are defined as those having a size or total volume that is less than 0.5 cc.
2. Prior Art
Electrochemical cells must have two opposite polarity terminals that are electrically isolated from each other. In use, the terminals are connected to a load, such as the circuitry in an implantable medical device to power the medical device. In that respect, an electrochemical cell which is sufficiently hermetic to prevent ingress of moisture and egress of electrolyte so that the cell can operate for 10 years or more requires robust sealing methodologies while still providing adequate electrical isolation between the opposite polarity terminals. However, conventional sealing techniques are often not practical when cell size drops below 0.5 cc. That is because the seals themselves take up a major portion of the overall cell volume.
A coin cell construction is a convenient configuration for the assembly of small cells. Conventional coin cells typically have a metal base and a metal lid, which are electrically isolated from each other by a plastic gasket. The cell is sealed by crimping the base around the plastic gasket. The gasket electrically isolates the base from the lid so that the base and lid serve as opposite polarity terminals for the cell. The problem is that a seal formed by crimping a plastic gasket is not easy to form consistently and, even when crimped according to design, is porous and not considered to be hermetic. The gasket becomes an escape path for electrolyte egress or ingress of atmospheric contaminants that can disrupt charging and discharging of the cell. For example, ingress of water is particularly problematic for lithium cells. Thus, crimped plastic seals may not provide the consistent longevity required for some applications.
Additionally, the plastic seal and crimp have a certain volume requirement at the cell periphery that reduces space which can otherwise be used for active materials such as the opposite polarity electrodes and activating electrolyte, thereby reducing cell capacity and volumetric efficiency. Reduced capacity means that the cell may not have sufficient energy per unit volume to power the associated electronic device. Further, there is a limit to how small a crimp seal can be made so that below a certain size, it may not be possible to construct the cell at all.
Moreover, since secondary electrochemical cells activated with a solid electrolyte typically undergo expansion and contraction during charging and discharging, they require hermetic encapsulation approaches that suitably accommodate this cycling induced dimensional change. Those types of hermetic enclosures for miniature electrochemical cells do not currently exist.
For that reason, the present invention provides encapsulation techniques that are suitable for use with hermetically sealed electrochemical cells of both primary and secondary chemistries. For rechargeable cells, the present enclosures have sufficient dimensional flexibility to accommodating the required dimensional changes during cycling. While useful with cells of virtually any size, the present encapsulation techniques are particularly well suited for cells having a total volume or size that is less than 0.5 cc.

Miniature electrochemical cells housed in a metallic casing having a glass-to-metal seal isolating the opposite polarity terminals


A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.

Many modern processors control various input/output ("I/O") devices using a memory-mapped I/O scheme, which enables a processor to communicate to an I/O device by reading and writing to one or more memory addresses reserved for that particular I/O device. A drawback of this approach, however, is that the memory addresses reserved for each I/O device reduces system memory available to the processor, such as when the reserved addresses coincide with physical addresses. Collectively, those reserved addresses constitute a "memory hole," which is a term commonly used to describe the linear address space of the memory that is unusable (or inaccessible) to a processor as system memory. As the number of I/O devices increases, the range of linear addresses reserved to service those I/O devices increases correspondingly. Consequently, the amount of memory useable as system memory decreases. To illustrate the effects of memory holes on system memory, consider a 36-bit processor having access greater than 4 GB of memory (i.e., an amount of memory including 236 addresses) and being a part of a computing system having two graphics processing units ("GPUs") as I/O devices. Usually, each of these GPUs can require 1024 megabytes (MB) of address space (i.e., an amount of memory including 230 addresses) in system memory to maintain frame buffers, which would then require reserving a total amount of 2 gigabytes ("GB") of address space to cover the two GPUs. Moreover, additional system memory must be dedicated for boot code and for other I/O devices, such as audio and visual devices. Consequently, the processor of this example would have less than one-half of its system memory available to perform its computational tasks. So if reserved memory were to expand without bound, processors would be left without much system memory with which to operate.
There are several memory addressing techniques known for redirecting accesses from one range of addresses of memory to another range of addresses. Some of these techniques are used for reducing the effects of memory holes, while others are directed toward other memory management functions.
FIG. 1A illustrates one memory addressing technique used for ameliorating the effects of memory holes. In this approach, system memory 100 is increased by adding extended memory 102 to the normal amount of memory available ("useable memory") 108 that is useable by a processor (not shown), which typically is about 680 kilobytes ("KB"). By adding extended memory 102, system memory 100 recovers the 340 KB of system memory usually lost to memory hole 104. In this memory addressing technique, an arithmetic operator 106 adds an amount, "delta," to a linear address ("LA") 101 to form adjusted address 103 (i.e., LA+delta), but only if address 101 is above 640 KB. The amount delta is a single quantity of addresses representing a displacement in linear address space. Arithmetic operator 106 therefore uses addition to redirect address 101 from a reserved address space in memory hole 104 to the supplemental address space in extended memory 102, thereby recovering memory that otherwise would not be available to the processor. While functional, adding an amount "delta" to an address is relatively cumbersome in execution and requires more hardware to implement adders than otherwise is necessary to reduce the effects of memory holes.
FIG. 1B shows another conventional memory addressing technique for managing memory. In this technique, system memory 150 contains three disparately sized dual in-line memory modules ("DIMMs"), such as DIMM ("1") 154, DIMM ("2") 152 and DIMM ("3") 156, that are collectively divided into ranges of linear addresses 162. Each range 162 corresponds to a range of physical addresses and has a range base 166 describing a base address for that range. For example, Range 1, which extends from linear address ("LA") 2 GB to LA 3 GB, has a range base ("1") 166b of 2 GB. As such, linear addresses from 0 GB to 2 GB map into physical addresses 0 GB to 1 GB−1 of DIMM ("1") 154, as translated from range base ("0") 166c, and linear addresses 2 GB to 3 GB map into physical addresses 1 GB to 2 GB−1 of DIMM ("1") 154, as translated from range base ("1") 166b. A DIMM base address ("DIMM Base") 170 is selected to relate a linear address, such as "LA 2 GB+1," to the physical addresses of system memory 150. Notably, linear addresses of a memory hole 168 also correspond to physical addresses in system memory, and specifically, to a group 164 of physical addresses that includes data for memory-mapped I/O devices. As such, a processor cannot use group 164 of physical addresses to process computations. While functional in addressing some system memories, this conventional memory technique does not ameliorate the effects of memory holes and is not readily adaptable to do so.
In view of the foregoing, it would be desirable to provide a system, an apparatus and a method for minimizing the drawbacks of the above-mentioned memory addressing techniques in the reclamation of memory in any number of arbitrarily-sized memory devices that otherwise would be lost to a memory hole.

System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices


A doctor unit in a paper machine includes a blade carrier having a blade holder fitted to the blade carrier. A doctor blade is mountable in the blade holder to doctor a roll or similar moving surface. The blade holder and/or doctor blade include one or more sensors installed inside the construction or on its surface. The sensors are arranged to measure the wear of and/or stress in the blade holder and/or doctor blade.

The rate of wear of the doctor blade in the various doctor units in a paper machine varies greatly. Depending on the doctor blade's position, its working life can vary from tens of hours to as much as tens of days. In terms of the operation of the paper machine and the doctor units, the degree of wear and general condition of the doctor blade would be valuable information. First of all, replacements could be predicted and, on the other hand, breakages could be noticed immediately. In the worst case, a worn-out or damaged doctor blade may be used, which will naturally lead to a poor doctoring result. At the same time, the doctor unit or even the surface being doctored can be damaged. If this results in the doctor dropping through, both the damage and the cost will be great. However, no effective method or device exists for determining the degree of wear of a doctor blade. Suggestions have been made for installing angle-sensors at the ends of the doctor unit. However, the change in the angle between the blade holder and the blade carrier does not indicate wear with sufficient accuracy. This is especially so, as the doctor blade usually wears least at the ends and generally most in the centre. In addition, the measurement of the angle will not show local faults or wear peaks in the doctor blade, which always lead to a poorer doctoring result. There is also no effective apparatus for monitoring the condition of the blade holder while the paper machine is running.
The wear of the blade and the doctoring result are particularly affected by the blade load and the blade angle being used at the time. Usually, the doctor blade is pressed against the surface being doctored by a load imposed on the blade holder by loading devices. In known doctor units, the loading devices are calibrated when the paper machine is stopped. The specific force, corresponding to the feed pressure of the loading devices, which is required to lift the doctor blade off the surface being doctored, is then generally measured. The results obtained can thus only be used to calculate the desired blade load approximately. The method can also be applied roughly to determine the blade load when running, but the method is complicated and inaccurate. The method also does not provide blade-load values over the width of the doctor unit, which would be important information for monitoring the doctoring result and the wear of the doctor blade.


Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

1. Field of the Invention
The present invention generally relates to integrated circuit structures that include multiple height devices and more particularly to an improved structure that reduces the height of the passivating layer to reduce the height of the contacts made to such devices.
2. Description of the Related Art
Fabrication of BiCMOS chips (integrated circuit chips having both bipolar transistors and complementary metal oxide semiconductor (CMOS) transistors) requires process integration of both bipolar and CMOS field effect transistors (FET) devices. One of the key challenges in process integration is to make contact connections to the differently sized devices. Reliable contact connection has always been one of the significant issues for base CMOS FET fabrication. Due to the significant vertical height difference between bipolar and CMOS FET devices, contact formation becomes even more difficult for BiCMOS chip fabrication. At present, the aspect ratio of contacts for BiCMOS is about 30% higher than base CMOS for 0.25 and 0.18 um SiGe technologies. This aspect ratio difference becomes unsustainable for future SiGe technologies (e.g., 0.13 um or below). The present invention described below provides a reliable solution to contact formation for future BiCMOS technologies.

Bipolar and CMOS integration with reduced contact height

International Business Machines Corporation


Nanoscale, pH-responsive polycationic networks useful for the delivery of anionic biologic therapeutics and associated methods.

Polymers have played an integral role in the advancement of drug delivery technology, providing controlled release of therapeutic agents in constant doses over long periods, cyclic dosage, and enabling tunable release of both hydrophilic and hydrophobic drugs. From early beginnings using off-the-shelf materials, the field has grown tremendously, driven in part by the innovations of chemical engineers. Modern advances in drug delivery are now predicated upon the rational design of polymers tailored for specific cargo and engineered to exert distinct biological functions. In particular, hydrogels have been instrumental in the development of polymeric systems for controlled release of therapeutic agents. These materials are attractive for transmucosal and intracellular drug delivery because of their facile synthesis, inherent biocompatibility, tunable physicochemical properties, and capacity to respond to various physiological stimuli.
The landmark discovery of RNA interference (RNAi) in 1998 has sparked a massive research effort in all fields of biological science and redefined our understanding of gene regulation mechanisms. Theoretically, RNAi mediated by small interfering RNA (siRNA) could be used as a powerful and versatile treatment modality to treat nearly any disease resulting from aberrant gene expression. Owing to its remarkable potency and low therapeutic dosage, siRNA holds extraordinary promise as a new biological therapeutic. However, efficient delivery has been implicated as the major hurdle to its widespread clinical application. Although much effort has been directed toward synthetic polymer carriers for siRNA, there remains a paucity of data on the development of oral delivery systems. Nearly all delivery systems undergoing clinical trials (no RNAi therapeutic has achieved FDA approval) rely on naked siRNA, conjugated polymers, or lipid carriers for topical and intravenous administration and do not posses attributes that render them useful delivery vectors for GI targets. It is desirable to develop a novel hydrogel platform for delivery of agents, such as agents for RNA interference, and capable of transporting therapeutic cargoes to their subcellular site of action.

Delivery of small interfering RNA and micro RNA through nanogels containing hydrophobic pseudo-peptides

Board of Regents, The University of Texas System


A device includes a member having an axis and a socket recess formed axially therein. The recess is polygonal in shape at its open outer end and has planar drive surfaces parallel to the axis alternating with retaining surfaces disposed at the corners of the polygonal shape and sloping inwardly of the recess toward the axis. Each of the retaining surfaces is substantially triangular in shape, having one apex at the adjacent corner at the outer end of the recess and having the other apices in adjacent drive surfaces at the inner end of the recess. The device may be a rotatably drivable device, wherein the axis is the axis of rotation.

1. Field of the Invention
The present invention relates to devices having female sockets adaptable for matably receiving a complementarily shaped male member. The invention has particular application to means for retaining the member in the socket.
2. Description of the Prior Art
Various types of rotatably drivable devices, such as drive sockets for wrenches and socket-head threaded fasteners, are provided with a female socket recess adapted for receiving a complementarily shaped male drive member. A typical form of such a drivable device has a polygonal socket recess formed in one end of the device coaxially with the axis of rotation. Various techniques have been used to facilitate retaining the drivable device on the associated driving tool or other drive member or, stated another way, to retain the driving tool or member in the socket recess. Various types of magnetic means have been used for this purpose.
Another technique is to so shape the socket recess and/or the drive member so as to provide an interference fit which will frictionally hold the parts together. Thus, for example, in my U.S. Pat. No. 4,970,922, there is disclosed a fluted driving tool which is adapted for engagement in a similarly shaped socket recess, the tool and socket recess having cooperating drive surfaces. The drive surfaces in the socket recess are substantially parallel to the axis of rotation while those on the drive member are given a slight helical twist about the axis of rotation so as to afford a wedge fit in the socket recess.
It has been considered desirable to provide a drivable device with a socket recess shaped such that, when used with a driving tool of standard shape, it will provide a retention fit. It is known to provide a socket-head screw with a hexagonal socket recess provided with a slight helical twist. Such an arrangement is disclosed in U.S. Pat. No. 2,538,350. However, that screw is specifically designed for use with a mating, helically twisted drive tool, and not with a standard drive tool. Furthermore, a helically twisted socket recess is very expensive to manufacture. Normally, female socket recesses are made by a forming or upsetting process wherein a forming tool is driven axially into the device to form the socket recess. In order to form a helically twisted socket recess, it is necessary to twist the forming tool during the forming operation, which requires the use of specialized tooling and equipment which is expensive to design and manufacture.

Device having socket with retention surfaces


A system for controlling gear (gear ratio) shifting in an automatic transmission mounted on a vehicle, including a shift control means for generating a shift command to upshift from one gear (gear ratio) currently established to a next gear (gear ratio) by determining a command to the solenoid valves to discharge the pressurized oil from the frictional engaging elements that establish the current gear (gear ratio) so as to slip-control the frictional engaging elements, and to charge the pressurized oil to the frictional engaging elements that establish the next gear (gear ratio) to be shifted to. The system includes a first step for determining the command such that an actual slip rate of the frictional engaging elements that establish the current gear (gear ratio) converges to a first desired slip rate, a second step for determining the command such that the actual slip rate of the frictional engaging elements that establish the current gear (gear ratio) converges to a second desired slip rate, maximum slip rate detecting means for detecting a maximum actual slip rate, slip rate difference calculating means for calculating a difference between the detected maximum actual slip rate and the second desired slip rate, command correcting means for correcting the command in response to the calculated difference, and command storing means for storing the corrected command to be used as the command in the first step in controlling a next upshift. This arrangement can avoid the clutches (and brakes) from being suffered excessive slippage, thereby improving the service life of the clutches and brakes and making the control to smooth shift to that for the next gear (gear ratio).

FIELD OF THE lNENTION
The present invention relates to a gear ratio shift control system for an automatic vehicle transmission, and in particular relates to a system for controlling the supply of oil pressure through shift solenoid valves to frictional engaging elements that establish the current gear (gear ratio) shifted from when upshifting.

Gear ratio shift control system for automatic vehicle transmission


A fluid delivery apparatus which embodies a stored energy source such as distendable elastomeric membrane which cooperates with a base and a conformable ullage to define a fluid reservoir and one which includes a unique fill assembly for use in controllably filling the fluid reservoir. The novel fill assembly of the invention enables the fluid reservoir of the fluid delivery portion of the apparatus to be aseptically filled in the field with a wide variety of selected medicinal fluids.

1. Field of the Invention
The present invention relates generally to fluid delivery devices for infusion of beneficial agents into a patient. More particularly, the invention concerns a fluid delivery apparatus which includes a conformable ullage and a novel fill assembly for filling the fluid reservoir of the apparatus in the field.
2. Discussion of the Invention
Many medicinal agents require an intravenous route for administration thus bypassing the digestive system and precluding degradation by the catalytic enzymes in the digestive tract and the liver. The use of more potent medications at elevated concentrations has also increased the need for accuracy in controlling the delivery of such drugs. The delivery device, while not an active pharmacologic agent, may enhance the activity of the drug by medicating its therapeutic effectiveness. Certain classes of new pharmacologic agents possess a very narrow range of therapeutic effectiveness, for instance, too small a dose results in no effect, while too great a dose results in toxic reaction.
In the past, prolonged infusion of fluids has generally been accomplished by gravity flow methods, which typically involve the use of intravenous administration sets and the familiar bottle suspended above the patient. such methods are cumbersome, imprecise and require bed confinement of the patient. Periodic monitoring of the apparatus by the nurse or doctor is required to detect malfunctions of the infusion apparatus.
One of the most versatile and unique fluid delivery apparatus developed in recent years is that developed by one of the present inventors and described in U.S. Pat. No. 5,205,820. The components of this novel fluid delivery apparatus generally include: a base assembly, an elastomeric membrane serving as a stored energy means, fluid flow channels for filling and delivery, flow control means, a cover, and an ullage which comprises a part of the base assembly. The ullage in these devices, that is the amount of the fluid reservoir or chamber that is not filled by fluid, is provided in the form of a semi-rigid structure having flow channels leading from the top of the structure through the base to inlet or outlet ports of the device. Since the inventions described herein represent improvements over those described in U.S. Pat. No. 5,205,820 this patent is hereby incorporated by reference as though fully set forth herein.
In the semi-rigid ullage configuration described in U.S. Pat. No. 5,205,820, wherein the ullage means is more fully described, the stored energy means of the device must be superimposed over the ullage to form the fluid-containing portion of the reservoir from which fluids are expelled at a controlled rate by the elastomeric membrane of the stored energy means tending to return to a less distended configuration in the direction toward the ullage. With these constructions, the stored energy membrane is typically used at higher extensions over a significantly large portion of the pressure-deformation curve.
For good performance, the elastomeric membrane materials selected for construction of the stored energy membrane must have good memory characteristics under conditions of high extension; good resistance to chemical and radiological degradation; and appropriate gas permeation characteristics depending upon the end application to be made of the device. Once an elastomeric membrane material is chosen that will optimally meet the desired performance requirements, there still remain certain limitations to the level of refinement of the delivery tolerances that can be achieved using the semi-rigid ullage configuration. These result primarily from the inability of the semi-rigid ullage to conform to the shape of the elastomeric membrane near the end of the delivery period. This nonconformity can lead to extended delivery rate tail-off and higher residual problems when extremely accurate delivery is required. For example, when larger volumes of fluid are to be delivered, the tail-off volume represents a smaller portion of the fluid amount delivered and therefore exhibits much less effect on the total fluid delivery profile, but in very small doses, the tail-off volume becomes a larger portion of the total volume. This sometimes places severe physical limits on the range of delivery profiles that may easily be accommodated using the semi-rigid ullage configuration.
As will be better appreciated from the discussion which follows, the apparatus of the present invention provides a unique, disposable fluid dispenser of simple but highly reliable construction that may be adapted to a wide variety of end use applications. A particularly important aspect of the improved apparatus is the incorporation of conformable ullages made of yieldable materials which uniquely conform to the shape of the stored energy membrane as the membrane distends and then returns to a less distended configuration. This novel construction, which permits the overall height of the device to be minimized, will satisfy even the most stringent delivery tolerance requirements and uniquely overcomes the limitation of materials selection. Further a plurality of subreservoirs can be associated with a single ullage thereby making it possible to incorporate a wide variety of delivery profiles within a single device.
The thrust of the present invention is to provide a novel fluid delivery apparatus that includes a conformable ullage of the character described in the preceding paragraph and also includes a unique fill assembly that can be used to controllably fill the fluid reservoir of the apparatus in the field. As will be better understood from the description which follows, the fill assembly of the present invention includes a fluid containing vial subassembly mounted within a unique adapter subassembly that functions to conveniently mate the vial subassembly with the conformable ullage type fluid delivery assembly.
In use, the adapter subassembly of the invention securely interconnects the fluid containing vial with the fluid delivery assembly so that the reservoir of the device can be controllably filled with the fluid contained within the vial assembly. After the reservoir is thus filled, the stored energy means of the fluid delivery device will cooperate with the conformable ullage to controllably expel the fluid from the device.

Fluid delivery device with conformable ullage and fill assembly


Systems and methods for providing multi-channel audio using a reduced amount of resources for the decoding process. A 5.1 channel audio stream is divided into three stereo streams. The packets from each of three stereo streams are multiplexed to create a pseudo-5.1 channel audio stream. The pseudo 5.1 channel audio stream is then decoded and demultiplexed at the output to create the output 5.1 channel audio sound. As such, the decoder resources only have decode a single pseudo 5.1 stream. This technique is equally applicable to 7.1 or other multi-channel formats.

Historically, multi-channel audio formats were developed for cinema applications. However, in recent years multi-channel audio, such as Dolby Digital and DTS has become prevalent in home theater systems. Typical formats include 4.0, 5.1 and more recently, 7.1. For instance, the 5.1 Dolby Digital format comprises two front speakers, two rear speakers, one center speaker and one low frequency effects (LFE) speaker (e.g., a sub-woofer). This provides a surround sound experience to the listener.
While multi-channel audio provides an improved listener experience, multi-channel audio streams require significantly more decoding resources than conventional stereo streams. This is because the information content of the multi-channel streams is much more than stereo streams. The additional decoding resources undesirably increase hardware requirements and cost.
Thus, there is a need for a decoder for use with multi-channel audio streams that can decode such streams while avoiding the hardware cost of conventional multi-channel audio decoders. The present invention provides such a solution.


High etch selectivity of both silicon nitride and silicon with respect to silicon oxide is obtained using an etch bath of phosphoric acid, hydrofluoric acid, and nitric acid. Minimal loading effects are observed and a long bath life is obtained by replenishing the hydroflouric and nitric acids.

Integrated circuit fabrications processes include steps in which materials must be selectively removed with respect to other materials. The removal process may use either wet or dry etching. Regardless of the method selected, the selectivity of the etch between the materials that are removed and those that are not removed should be high. However, selectivity is not the only consideration; the skilled artisan readily appreciates that consistent results over an extended period of time should be readily achieved.
Dielectric regions, termed field oxides, are formed in integrated circuit fabrication by depositing a dielectric mask layer over silicon (likely having a thin oxide, termed a pad oxide, on its surface), patterning the dielectric mask layer to expose the silicon or oxide, and then growing a thick oxide in the exposed region. The thick oxide is the field oxide. The patterned dielectric mask layer is then removed. A typical choice of dielectric for the mask layer is silicon nitride. This process is frequently referred to as LOCOS which is a well known acronym for Localized Oxidation of Silicon. In current practice, a polysilicon layer is frequently present underneath the nitride layer. The patterned structure is referred to as a Poly Buffered LOCOS (PBL) stack. Thus, both silicon nitride and polysilicon must be removed without significant attack on the silicon oxide after the field oxide has been grown.
Wet etching techniques are commonly used for blanket stripping of oxides, nitrides, and silicon. For example, silicon nitrides are etched in boiling phosphoric acid. Minor amounts of nitric acid may also be present in the etch bath. However, these baths are susceptible to aging effects and high particle counts because the silicate concentration in the bath increases with wafer throughput. PBL stacks may be removed with a phosphoric acid/nitric acid bath. However, this bath also suffers from bath aging, presumably due to silicate buildup. The process is also relatively slow with 140 minutes being a representative time for etching a typical PBL stack. Pitting of the oxide can be an additional problem as the polysilicon etches rapidly along its grain boundaries. Some pad oxide may be exposed to the etch bath and may etch (pit) the oxide as etch selectivity between polysilicon and the oxide does not prevent all etching of oxide. Yet another approach strips the nitride in one bath and the polysilicon in another bath. This method also yields some pitting as it is difficult to stop the nitride etch without pitting the polysilicon.
Of course, etching of these materials in other contexts is also contemplated. See, Solid State Technology, "Spin Etcher for Removal of Backside Depositions," by Ernst Gaulhofer, May 1991, for a description of etching apparatus and etchants. It is reported that nitric, hydrofluoric, and phosphoric acids are used in a 3:1:1 solution to etch silicon, apparently both single crystal and polycrystalline. No selectivity is reported nor is there any discussion of rejuvenating the etch solution which is important to minimize chemical usage.
Wet etching techniques with high selectivity of nitride and polysilicon with respect to oxide and long bath life are desirable. It will be appreciated that the high selectivity and long bath life should result in higher throughput and lower costs.

Method of integrated circuit fabrication including selective etching of silicon and silicon compounds


A voltage generation circuit including a capacitor, an n-channel MOS transistor, a p-channel MOS transistor and the like. The n-channel transistor has a source terminal connected to a node and a drain terminal employed as an output terminal for a negative voltage, the p-channel MOS transistor has a source terminal connected to the aforementioned node and a drain terminal employed as a ground terminal, gate terminals of the n-channel MOS transistor and the p-channel transistor are connected in common, and clock signals inverted in phase to each other are applied to the common node and a first terminal of the capacitor.

1. Field of the Invention
The present invention relates to a voltage generation circuit employing a capacitor and a display unit comprising this voltage generation circuit.
2. Description of the Related Art
FIG. 41 illustrates an exemplary conventional voltage generation circuit employing a capacitor. The voltage generation circuit shown in FIG. 41 comprises a capacitor (pumping capacitor) cp1, first and second p-channel MOS (metal oxide semiconductor) transistors pt1 and pt2, an inverter circuit inv1 and the like.
The first p-channel MOS transistor (driving transistor) pt1 has a drain terminal D and a gate terminal G connected to a node nd1 and a source terminal S defining a voltage output terminal 30 outputting a negative voltage VBB. The second p-channel transistor pt2 has a source terminal S connected to the node nd1, a gate terminal G connected to the inverter circuit inv1, and a drain terminal D defining a ground terminal.
The capacitor cp1 is formed by a p-channel transistor having a source terminal and a drain terminal connected in common with each other and a gate terminal G connected to the node nd1. A clock signal CLK is input in the capacitor cp1 and the inverter circuit inv1 through an input terminal 10.
The outline of operation of the voltage generation circuit having the aforementioned structure for generating the voltage (negative voltage) VBB is now described.
When the clock signal CLK goes low in logic (hereinafter simply referred to as xe2x80x9clowxe2x80x9d), the potential Vn1 of the node nd1 lowers to reach a negative voltage. When the potential Vn1 of the node nd1 lowers below the potential VBB of the source terminal S of the first p-channel MOS transistor pt1 in excess of the threshold voltage Vthp1 of the first p-channel MOS transistor pt1, the first p-channel transistor pt1 is turned on.
At this time, charges proportional to the capacitance of the capacitor cp1 flow from the source terminal S of the first p-channel MOS transistor pt1 toward the node nd1. These charges are stored in the capacitor cp1 since the second p-channel MOS transistor pt2 is in an OFF state, and the potential Vn1 of the node nd1 rises in response to these charges.
When the clock signal CLK goes high in logic (hereinafter simply referred to as xe2x80x9chighxe2x80x9d), the potential Vn1 of the node nd1 is pulled up by a level corresponding to the high level (VDD) of the clock signal CLK, to further rise.
When the clock signal CLK goes high, further, a low-level signal is input in the second p-channel MOS transistor pt2 through the inverter circuit inv1, to turn on the second p-channel MOS transistor pt2. At this time, the charges stored in the capacitor cp1 are extracted to the ground terminal (GND), and the potential Vn1 of the node nd1 lowers.
Thus, the charges are pumped from the source terminal S of the first p-channel MOS transistor pt1 to the ground terminal (GND) every cycle of the clock signal CLK, thereby rendering the voltage of the source terminal S of the first p-channel MOS transistor pt1 negative.
FIG. 42 shows a voltage generation circuit known as an example improving the pumping efficiency of the afore-mentioned conventional voltage generation circuit. This voltage generation circuit uses two conventional voltage generation circuits described above, and applies clock signals CLK and /CLK inverted in phase to each other to terminals of pumping capacitors cp1 and cp2 respectively thereby improving the pumping efficiency thereof and reducing the time for attaining a prescribed negative voltage.
While the aforementioned conventional voltage generation circuit effectively generates the voltage (negative voltage) VBB with a simple structure, the theoretical value of the achieved negative voltage (VBB) is (xe2x88x92VDD+Vthp1+Vthp2) in FIG. 41 and (xe2x88x92VDD+Vthp1) in FIG. 42, which is less than the maximum logical value (xe2x88x92VDD) by the threshold voltage (Vthp1, Vthp2) of the first and second p-channel MOS transistors pt1 and pt2.
As the output negative voltage VBB lowers, further, the potential difference between the source terminal S of the first p-channel MOS transistor pt1 and the node nd1, i.e., the gate-to-source voltage of the first p-channel MOS transistor pt1 reduces to lower the drivability of the first p-channel MOS transistor pt1.
In recent years, a voltage generation circuit having high current drivability is required in view of current drivability necessary for controlling word lines of a DRAM (dynamic random access memory) with a negative bias or in view of reduction in power consumption and attainment of operating margins of pixel transistors in a liquid crystal display unit or the like. However, the aforementioned conventional voltage generation circuit cannot sufficiently satisfy such requirements due to the low current drivability.
An object of the present invention is to provide a voltage generation circuit capable of obtaining a high voltage with high current drivability and a display unit comprising this voltage generator.
A voltage generation circuit according to an aspect of the present invention has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, and further comprises an n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a p-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while gate terminals of the n-channel transistor and the p-channel transistor are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to the gate terminals connected in common.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the n-channel transistor serving as a driving transistor. When generating a negative voltage, for example, the driving transistor is reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistor can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistor is employed as the driving transistor, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistor, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistor with the n-channel transistor, further, the element areas of the transistors can be reduced.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, the n-channel transistor preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the p-channel transistor preferably includes a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and the capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on an N-type semiconductor substrate having a double well structure, the n-channel transistor may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the p-channel transistor may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and the capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on a glass substrate, an active layer of each of the n-channel transistor and the p-channel transistor may be formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor may be formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the same go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistor, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal, and a delay circuit adjusting a period so that the two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A voltage generation circuit according to another aspect of the present invention has first and second capacitors and generates a prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, and further comprises a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a first p-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential terminal, and a second p-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor are connected in common and connected to the second node, a gate terminal of the second n-channel transistor and the gate terminal of second p-channel transistor are connected in common and connected to the first node, the output terminals of the first and second n-channel transistors are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the first and second n-channel transistors serving as driving transistors. When generating a negative voltage, for example, the driving transistors are reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistors can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistors are employed as the driving transistors, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistors, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistors with the n-channel transistors, further, the element areas of the transistors can be reduced.
In addition, pumping operation is performed every half cycle of the clock signals, whereby pumping can be more efficiently performed for increasing the speed for reaching the target output voltage.
The voltage generation circuit is preferably f formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors preferably includes a MOSFET formed on an N-type well to which the clock signal is applied for obtaining its back gate potential, the first capacitor preferably includes a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor preferably includes a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, the first capacitor may include a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, the first capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a double well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, the first capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on an insulator film formed on a silicon substrate, an active layer of each of the first and second n-channel transistors and the first and second p-channel transistors may be formed from a semiconductor layer formed on the insulator film, and at least one electrode of each of the first and second capacitors is formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The voltage generation circuit may be formed on a glass substrate, an active layer of each of the first and second n-channel transistors and the first and second p-channel transistors may be formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors may be formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the two clock signals go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistors, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal and a delay circuit adjusting a period so that the two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A voltage generation circuit according to still another aspect of the present invention has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, and further comprises a first n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a second n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor and the other one of the two clock signals is applied to a gate terminal of the first n-channel transistor.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the first n-channel transistor serving as a driving transistor. When generating a negative voltage, for example, the driving transistor is reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistor can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistor is employed as the driving transistor, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistor, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistor with the n-channel transistor, further, the element areas of the transistors can be reduced.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, the first n-channel transistor preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the second n-channel transistor preferably includes a MOSFET formed on a P-type well to which the node is connected for obtaining its back gate potential, and the capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on an N-type semiconductor substrate having a double well structure, the first n-channel transistor may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the second n-channel transistor may include a MOSFET formed on a P-type well to which the node is connected for obtaining its back gate potential, and the capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first and second n-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor is preferably formed from an n-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the two clock signals go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistors, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal and a delay circuit adjusting a period so that the two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A voltage generation circuit according to a further aspect of the present invention has first and second capacitors and generates a prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, and further comprises a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a third n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential terminal, and a fourth n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while the output terminals of the first and second n-channel transistors are connected in common, a gate terminal of the first n-channel transistor is connected to the second node, a gate terminal of the second n-channel transistor is connected to the first node, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the first and second n-channel transistors serving as driving transistors. When generating a negative voltage, for example, the driving transistors are reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistors can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistors are employed as the driving transistors, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistors, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistors with the n-channel transistors, further, the element areas of the transistors can be reduced.
In addition, pumping operation is performed every half cycle of the clock signals, whereby pumping can be more efficiently performed for increasing the speed for reaching the target output voltage.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the third n-channel transistor preferably includes a MOSFET formed on a P-type well to which the first node is connected for obtaining its back gate potential, the fourth n-channel transistor preferably includes a MOSFET formed on a P-type well to which the second node is connected for obtaining its back gate potential, the first capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a double well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the third n-channel transistor may include a MOSFET formed on a P-type well to which the first node is connected for obtaining its back gate potential, the fourth n-channel transistor may include a MOSFET formed on a P-type well to which the second node is connected for obtaining its back gate potential, the first capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a glass substrate, an active layer of each of the first to fourth n-channel transistors may be formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors may be formed from an n-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the two clock signals go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistors, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal and a delay circuit adjusting a period so that said two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has a capacitor and generates the prescribed voltage through a node connected to a first terminal of the capacitor, the voltage generation circuit further includes an n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a p-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, gate terminals of the n-channel transistor and the p-channel transistor are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to the gate terminals connected in common.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the n-channel transistor and the p-channel transistor is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor is preferably formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has first and second capacitors and generates the prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, the voltage generation circuit further includes a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a first p-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential terminal and a second p-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor are connected in common and connected to the second node, a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor are connected in common and connected to the first node, the output terminals of the first and second n-channel transistors are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first and second n-channel transistors and the first and second p-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors is formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, the voltage generation circuit further includes a first n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a second n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to a gate terminal of the first n-channel transistor.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first and second n-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor is preferably formed from an n-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has first and second capacitors and generates the prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, the voltage generation circuit further includes a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a third n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential, and a fourth n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, the output terminals of the first and second n-channel transistors are connected in common, a gate terminal of the first n-channel transistor is connected to the second node, a gate terminal of the second n-channel transistor is connected to the first node, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first to fourth n-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors is formed from an n-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage, such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Voltage generation circuit and display unit comprising voltage generation circuit


The present disclosure provides systems and methods for assembling a device while maintaining the aesthetic appearance and structural integrity of a visible surface of the device. In one or more implementations of the invention, a system includes a first assembly piece with an assembly region that comprises an opening defined by first and second connecting elements. The system further includes a second assembly piece and a fastening assembly, where a portion of the second assembly piece is shaped to fit within the assembly region opening and the fastening assembly spans the first and second connecting elements to secure the first assembly piece to the second assembly piece, and tightening of the fastening assembly causes the second connecting element to deform, pressing a surface of the second assembly piece against an adjacent surface of the first connecting element and retaining a substantially even visible surface of the device.

Advances in manufacturing and distribution have made it possible to create, package, and distribute high volumes of ready to assemble consumer goods. In some instances, the distributor or retailer assembles the consumer goods before the point of sale, but it is also common for ready to assemble consumer goods to be packaged with assembly instructions, making it possible for the consumer herself to assemble the packaged device at home or at another preferred location. Regardless of who assembles the device, it is often important that the finally assembled product functions as intended and that the assembly process does not significantly affect the overall structural integrity and aesthetic appearance of the device.
Aesthetics can play a significant role in the perceived quality and workmanship of a consumer device. If, for example, there is a crack, scratch, or dent on the device, some consumers—and even some distributors and retailers—may assume the product is constructed of a low quality material or is otherwise defective, even though the crack, scratch, or dent may not affect the device's designed functionality or its structural integrity. On the other hand, a device lacking aesthetic malformations may connote a high level of workmanship and product quality, which may, in turn, increase consumer confidence in and satisfaction with the product.
Unfortunately, some goods may include an aesthetically unpleasant malformation as a result of the post-manufacturing assembly process. Such malformations may not actually affect the quality or structural integrity of the device, but the device may nonetheless suffer from a consumer perception that it is in some way an aberrant device or that the device's structural integrity is somehow flawed.
Accordingly, there are a number of disadvantages with system and methods of assembling devices that can be addressed.


The present invention provides for data to be bilaterally transferred between general applications such as databases and task specific applications. The transfer maps and transports data between applications. The first application includes a data structure with a data structure identifier and a table. The second application includes a data grid. The mapping of data is performed by: associating a column in the grid to a table data field; associating a mapping icon with the column; and associating the table identifier with the column. The transporting of data between the applications include: identifying a transport function; identifying at least one of the mapping; and transporting data according to the selected mapping and the selected transport function.

The present invention relates to the transfer of data between software applications. More specifically, the present invention provides for data to be transferred between general applications such as databases and task specific applications such as decision support software.
The overhead associated with manually entering data into applications may be inefficient and error prone, especially when that data has already been entered in a different application. Writing specific data transfer utilities may also be inefficient because of the custom programming resources required. What is needed is a generalized method to allow general users of an application to efficiently set up repeatable data transfers between applications.

This patent is subject to a terminal disclaimer.


The present invention relates to a flexible semiaromatic polyamide composition with a low moisture uptake comprising, by weight, the total being 100:                60 to 99.5% (preferably 70 to 93%) of at least one copolyamide of formula X/Y,Ar in        which:                    Y denotes the residues of an aliphatic diamine having from 8 to 20 carbon atoms,            Ar denotes the residues of an aromatic dicarboxylic acid,            X denotes either the residues of aminoundecanoic acid NH2—(CH2)10—COOH, of lactam-12 or of the corresponding amino acid, or X denotes the unit Y,x, residue from the condensation of the diamine with an aliphatic diacid (x) having between 8 and 20 carbon atoms, or X denotes the unit Y,I, residue from the condensation of the diamine with isophthalic acid,            −0.5 to 40% (preferably 7 to 30%) of at least one product chosen from plasticizers, nanofillers, polyolefins, crosslinked polyolefins and additives.

There exist terephthalic copolyamides based on a 6 unit (for example, 6,6/6,T or 6/6,T or also 6,I/6,T, comprising predominantly 6,T) which have very high melting points, above 300° C. These products are very rigid and their elongation at break is less than 10%, which prevents them from being used in the field of extrusion of pipes. Patent EP 550 314 gives examples of copolyamides-12/6,T. U.S. Pat. No. 3,843,611 discloses copolyamides-12,12/12,T. U.S. Pat. No. 5,708,125 discloses copolyamides-10,6/10,T. None of these prior arts discloses a possible aptitude with regard to ageing. Furthermore, none of these prior arts discloses the need for flexible polyamides. The aim of the present invention is to find polyamides which have resistance to ageing when they are subjected to a high working temperature, while remaining flexible. Such compositions have now been found.

Flexible semiaromatic polyamides with a low moisture uptake


There is provided a wheel support bearing assembly (1) utilizing a dual row angular ball bearing. The bearing assembly (1) includes two ball retainers (5) for retaining corresponding rows of balls (4). One or both of the retainers (5) is so designed that the neighboring balls (4) can adjoin directly in a non-contact fashion relative to each other on a pitch circle PCD of the row of the balls (4). For example, the ball retainer (5) is of a generally comb-shape having a plurality of pillars (5b) each formed with a throughhole (13) aligned on the pitch circle PCD.

1. Field of the Invention
The present invention relates to a wheel support bearing assembly for rotatably supporting a wheel relative to a vehicle body structure in automotive vehicles such as automobiles and also relates to an angular ball bearing for use in various applications.
2. Description of the Prior Art
For the wheel support bearing assembly, a dual row angular ball bearing is largely employed, in which dual rows of balls are rollingly interposed between outer and inner members at a predetermined contact angle. In such a dual row angular ball bearing, the balls of each row are retained by a respective ball retainer in circumferentially equidistantly spaced relation to each other and are prevented by the ball retainer from contacting with each other.
In wheel support bearing assemblies available in recent years, from the perspective of increasing the freedom of design choice of the automotive vehicles and the mileage and of facilitating the maintenance and reduction of the cost, the needs have arisen to further increase the lifetime and the rigidity of the wheel support bearing assembly, to manufacture the wheel support bearing assembly in a compact size and light-weight feature.
In an attempt to satisfy those needs, the Japanese Laid-open Patent Publication No. 2002-195254, for example, discloses a wheel support bearing assembly, in which one of the dual rows of balls, for example, an inboard row of balls, which is positioned remote from a vehicle wheel supported by the wheel support bearing assembly, makes no use of a ball retainer, i.e., represents a full complement ball bearing. The full complement ball bearing with no ball retainer employed is particularly advantageous in that the number of the balls can be increased, reducing a bearing load imposed on each of those balls. For this reason, the wheel support bearing assembly can have an increased lifetime and can also be manufactured in a compact size having a light-weight feature.
Although in the full complement ball bearing the number of the balls can be increased as compared with the bearing assembly utilizing the ball retainers, it has been well recognized that the neighboring balls contact with each other. Considering that during the operation of the bearing assembly the balls rotate in the same direction about their own center axes, the respective surfaces of the neighboring balls move in opposite directions at a contact point where such surfaces contact, with the consequence that a sliding contact or friction takes place at the contact point at a velocity that is twice the peripheral velocity of each ball. In other words, a so-called "ball-to-ball competition (ball-to-ball sliding friction)" occurs.
Once the ball-to-ball competition occurs, the frictional resistance increases. Also, in the full complement ball bearing, separation and collision of the balls repeat during the operation of the bearing assembly, which would lead to generation of rattling sounds and heat.
While the bearing assembly with the balls retained by the ball retainers is known to be advantageous in that the occurrence of the ball-to-ball competition and collision can be avoided, it is preferred that pillars in the ball retainers, that define a pocket between the neighboring pillars for accommodating the corresponding ball, may be as thin as possible in order for the number of the balls employable in the bearing assembly to be increased. The thinnest portion of the pillar needs to be aligned with the pitch circle of the row of the balls. However, to render each pillar to be thin is limited in view of the strength and manufacturing difficulty. By way of example, if each pillar is made too thin, the ball retainer is susceptible to damage at such a thin portion of the pillar and debris resulting therefrom will hamper a smooth rotation of the bearing.
The problems discussed above can be equally found in the standard angular ball bearing, particularly where the angular ball bearing is desired to be manufactured in a compact size with an increased load bearing capacity.

Wheel support bearing assembly and angular ball bearing