The present invention provides a method of driving a main rotor (2) of a rotorcraft (1) in rotation. A regulation setpoint (C) for a power plant (3) used for driving the main rotor (2) at a variable speed of rotation is generated by a control unit (4) and is transmitted to a regulator unit (5) for regulating the operation of the power plant (3). The value of an initial setpoint (NRini) is generated progressively and continuously depending on variation in the current value of the density (D) of the ambient air outside the rotorcraft (1). The value of the initial setpoint (NRini) is potentially corrected depending on predefined flight conditions of the rotorcraft (1). Prior to being transmitted to the regulator unit (5), the value of the regulation setpoint (C) is preferably limited to a range of acceptable speeds for driving the main rotor (2) in rotation.

(1) Field of the Invention
The present invention relates to the field of rotorcraft fitted with at least one rotary wing rotor. The present invention relates more specifically to data processing methods and equipment adapted to a specific function of determining controlled variation in the speed at which at least one main rotor of substantially vertical axis of a rotorcraft is driven in rotation.
(2) Description of Related Art
Rotorcraft are rotary wing aircraft having at least one main rotor of substantially vertical axis that provides the rotorcraft with lift. If the rotorcraft is a helicopter, the main rotor provides not only lift, but also propulsion and/or control in pitching and in roll.
Compared with other powered aircraft, rotorcraft have the advantage of being able to hover and/or fly at low speed, including when close to the ground. As an indication, a rotorcraft is commonly said to be flying at low speeds when it is flying at less than about 50 knots (kt). Nevertheless, in cruising flight, rotorcraft are capable of flying at high speeds. As an indication, a rotorcraft is commonly said to be flying at high speed when flying at a speed lying in the range about 75 kt to 160 kt.
In this context, consideration should also be given to transitory flying speeds of the rotorcraft, i.e. flying speeds of the rotorcraft lying between low speeds and high speeds. Such transitory flying speeds of a rotorcraft are conventionally used for short periods only, between the rotorcraft flying at low speed and the rotorcraft flying at high speed.
In general, depending on the flying speed of a rotorcraft, its flight envelope is segmented into commonly accepted flying speed ranges of less than about 50 kt, transitory flying speeds, and greater than 75 kt. The values given for the ranges of rotorcraft flying speeds are given by way of indication and may be varied, in particular depending on the structure, the weight, and/or the performance of a particular rotorcraft, for example.
The lift of the rotorcraft is provided by the main rotor and it is controlled using flight controls operated by a pilot to vary the collective pitch of the blades making up the rotary wing of the main rotor. Such a pilot may be a human pilot or an autopilot. Driving rotation of the main rotor is considered as being a priority, given that it has the essential function of providing the rotorcraft with lift.
In the past, the rotary drive speed of the main rotor has long been established as being substantially constant. Nevertheless, proposals have been made to vary the drive speed of the main rotor voluntarily over a restricted range of speeds of rotation, in order to satisfy specific needs depending on various flight conditions of the rotorcraft.
For example, in order to improve the performance of a rotorcraft in a combat situation, it is known to vary the drive speed of the main rotor as a function of variation in the air speed of the rotorcraft. In this context, reference may be made to the publication "Enhanced energy maneuverability for attack helicopters using continuous variable rotor speed control" (C. G. Schaefer Jr.; F. H. Lutze Jr.); 47th Forum American Helicopter Society 1991, pp. 1293-1303.
Document US 2003/051461 (B. Certain) discloses regulating the speed of a rotorcraft engine used for driving rotors of the rotorcraft including a main rotor and a tail rotor of substantially horizontal axis, as a function of the position of the rudder control for varying the collective pitch of the blades of the tail rotor.
Nevertheless, it should be understood that multiple rotorcraft flight conditions can be taken into account in order to define a variable desired speed of rotation for the main rotor.
For example, concerning the performance of the rotorcraft, it is desirable for the pilot to have optimized ability to maneuver the rotorcraft, in particular at low flying speeds and/or in situations when the rotorcraft is close to the ground, including in the event of a possible failure of one of the rotorcraft engines used for driving rotation of the main rotor.
Also by way of example, it is also useful to take account of the noise produced by the rotorcraft in order to limit the sound nuisance that it generates while approaching or departing from a landing point.
In this context, reference may be made to Document U.S. Pat. No. 6,198,991 (Yamakawa et al.), which proposes reducing the sound nuisance generated by a rotorcraft approaching a landing point. In one possible implementation, it is proposed for that purpose to vary the speed of rotation of a main rotor of the rotorcraft in order to reduce the noise produced by the rotorcraft.
Also by way of example, reference may be made to Document WO 99/42360 (A. E. Karem), which proposes improving the performance obtained by a main rotor of a rotorcraft by causing its drive speed to vary depending on a load threshold supported by the blades of the main rotor.
Also by way of example, concerning the ambient outside medium in which the rotorcraft is flying, the physicochemical characteristics of the air have an influence on the lift of the rotorcraft for a given angle of incidence of the blades of the main rotor. The rotorcraft has various measuring and/or calculation instruments serving to identify the values of various parameters, such as the height of the rotorcraft above the ground, its pressure altitude, its density altitude, or the outside temperature, for example. On the basis of identifying the ambient outside medium or the flying speed of the rotorcraft, actions may be taken to modify the speed at which the main rotor is driven in rotation.
In this context, reference may be made to Document US 2007/118254 (G. W. Barnes, et al.), which proposes varying the speed of rotation of a main rotor of a rotorcraft depending on two values considered as being low and high under predefined threshold conditions for values of various parameters associated with previously-identified flight conditions of the rotorcraft.
Reference may also be made in this context to Document WO 2010/143051 (Agusta Spa et al.), which proposes varying the speed of rotation of a main rotor of a rotorcraft in compliance with a previously-established map depending on various flight conditions of the rotorcraft.

Method of driving a main rotor of a rotorcraft in rotation in compliance with a speed of rotation setpoint of variable value


An ultra-short channel device with an inverse-T gate lightly-doped drain (ITLDD) structure is disclosed. The present invention includes a semiconductor substrate, which includes a top surface; a source region formed in the semiconductor substrate; and a drain region formed in the semiconductor substrate spaced from the source region by a channel region. Further, the present invention also includes an inverse-T shaped silicon region formed over the semiconductor substrate, wherein the inverse-T shaped silicon region is approximately disposed within the area of the channel region; and a sidewall insulating region abutting to a sidewall of the inverse-T shaped silicon region. A first conductive region is formed on the top surface of the inverse-T shaped silicon region, and a second conductive region is formed on the top surface of the source region. Also, a third conductive region is formed on the top surface of the drain region.

1. Field of the Invention
The present invention relates to a semiconductor transistor, and particularly, to an ultra-short channel metal-oxide-semiconductor field effect transistor (MOSFET) with an inverse-T gate lightly-doped drain (ITLDD) structure.
2. Description of the Prior Art
Metal-oxide-semiconductor (MOS) devices with ultra-short (less than 0.1 .mu.m) channel are required for high frequency operation, for example, in a high-speed ring oscillator. The major constrains for 0.1 .mu.m (or less) gate length metal-oxide-semiconductor field effect transistor (MOSFET) device used, for example, in giga-bit dynamic random access memories (DRAMs) are short channel effect and hot carrier reliability problems. To solve these problem, some process techniques such as ultrashallow junction and ultra-thin gate oxide are used. For example, a device design window of process conditions such as oxide thickness, punch-through doses, and lightly-doped drain (LDD) doses is disclosed in Hyunsang Hwang et al., "Performance and Reliability Optimization of Ultra Short Channel CMOS Device for Giga-bit DRAM Applications," IEEE IEDM Tech. Dig., pages 435-438 (1995) which is hereby incorporated by reference.
However, it becomes difficult to define a gate length below 0.1 .mu.m due to some practical limitations, such as the resolution, under current optical photolithography technique. In order to circumscribe this situation, a resistor-thinning process based on an isotropic plasma resist ashing technique is applied in forming short channel MOSFETs with the gate length below 0.1 .mu.m as disclosed in Mizuki Ono et al., "Sub-50 nm Gate Length N-MOSFETs with 10 nm Phosphorus Source and Drain Junctions," IEEE IEDM Tech. Dig., pages 119-122 (1993) which is also hereby incorporated by reference.
When the MOSFET devices are operated at a low supply voltage, the parasitic resistance effect due to the lightly-doped drain (LDD) structure should be reduced to maintain their performance. Further, the peak field location under the gate should be properly controlled, so that the hot carrier effect germane to the LDD structure can be improved. An inverse-T lightly-doped drain (ITLDD) transistor structure is disclosed in Tiao-Yuan Huang et al., "A New LDD Transistor with Inverse-T Gate Structure," IEEE Electronic Device Letters, VOL. EDL-8. No. 4, pages 151-153 (1987) which is hereby incorporated by reference. Although this ITLDD structure can alleviate hot carrier effect, its process is still not suitable for high-density or high-speed circuit application, in which fabrication of ultra-short channel devices with gate length less than 0.1 .mu.m is required.

Semiconductor device with an inverse-T gate lightly-doped drain structure


The invention provides a system for modeling three-dimensional objects using hybrid geometric/volumetric representation, wherein sharp edges are created by a geometric representation that is connected to the volumetric representation. The system creates, maintains, and updates the hybrid representation according to user input. The system also provides for conversion of the hybrid representation into either a wholly geometric representation or a wholly volumetric representation, as may be needed for output to a given device, such as a display device, a printer, and/or a fabricating device.

Traditional modeling systems operate in either the geometric domain or in the volumetric (quantized) domain. Geometric models are generally built using lines, polygons, NURBS, and the like. FIG. 1 incorporated herein shows a geometric representation of a space shuttle 100 composed of polygons. Geometric representations are excellent for modeling objects that can be characterized with simple geometric forms. However, geometric representations are not as effective for modeling more organic, realistic, and/or complex shapes.
Voxel-based models offer advantages in both graphical and haptic representation of three-dimensional objects, particularly objects having complex shapes that cannot be easily characterized with simple geometric forms such as lines, polygons, spheres, cylinders, or the like. Voxel-based models offer significant speed and other processing advantages for production of realistic force-feedback to a user in a haptic virtual reality system. However, voxel-based models are not as effective as geometric models at representing objects with sharp edges.
Traditional modeling systems do not combine both volumetric and geometric representations, and do not have the ability to perform operations in one domain (volumetric or geometric) and have the results reflected in the other domain. This restricts the utility of such modeling systems in applications that require both industrial design (e.g., design of man-made, man-altered, and/or linear forms) and organic modeling (e.g., modeling non-linear, complex forms that appear in nature).

Systems for hybrid geometric/volumetric representation of 3D objects


Impedance, e.g. sub-threshold impedance, is measured across the heart at selected cardiac cycle times as a measure of chamber expansion or contraction. One embodiment measures impedance over a long AV interval to obtain the minimum impedance, indicative of maximum ventricular expansion, in order to set the AV interval. Another embodiment measures impedance change over a cycle and varies the AV pace interval in a binary search to converge on the AV interval causing maximum impedance change indicative of maximum ventricular output. Another method varies the right ventricle to left ventricle (VV) interval to converge on an impedance maximum indicative of minimum cardiac volume at end systole. Another embodiment varies the VV interval to maximize impedance change. Other methods vary the AA interval to maximize impedance change over the entire cardiac cycle or during the atrial cycle.

Congestive heart failure (CHF) is defined generally as the inability of the heart to deliver enough blood to the peripheral tissues to meet metabolic demands. Frequently CHF is associated with left heart dysfunction, but it can have a variety of other causes. For example, CHF patients may have any one of several different conduction defects. The natural electrical activation system through the heart involves sequential events starting with the sino-atrial (SA) node, and continuing through the preferred conduction pathways at the atrial level, followed by the atrio-ventricular (AV) node, Common Bundle of His, right and left bundle branches, and final distribution to the distal myocardial terminals via the Purkinje fiber network. A common type of intra-atrial conduction defect is known as intra-atrial block (IAB), a condition where the atrial activation is delayed in getting from the right atrium to the left atrium. In left bundle branch block and right bundle branch block, the activation signals are not conducted in a normal fashion along the left or right bundle branches respectively. Thus, in a patient with bundle branch block, the activation of the ventricle is slowed, and the QRS is seen to widen due to the increased time for the activation to traverse the conduction path.
CHF resulting from such conduction defects and/or other cardiomyopathies are the object of considerable research. It is known generally that four-chamber cardiac pacing and atrial synchronous bi-ventricular pacing can provide significant improvement for patients having atrial or ventricular mechanical dysynchrony resulting in dysfunction and symptoms of congestive heart failure.
The benefits of four-chamber pacing and atrial synchronous bi-ventricular pacing generally have been disclosed and published in the literature. Cazeau et al., PACE, Vol. 17, November. 1994, Part II, pp. 1974-1979, disclosed investigations leading to the conclusion that four-chamber pacing was feasible, and that in patients with evidence of interventricular dysynchrony, a better mechanical activation process can be obtained by resynchronizing depolarization of the right and left ventricles, and optimizing the AV sequence on both sides of the heart. In the patent literature, U.S. Pat. No. 4,928,688 is representative of a system for simultaneous left ventricular (LV) and right ventricular (RV) pacing; natural ventricular depolarizations are sensed in both chambers, if one chamber contracts but the other one does not within a window of up to 5-10 ms, then the non-contracting ventricular chamber is paced.
Further, similar to the advantages of substantially simultaneous or synchronous pacing of the two ventricles, there is an advantage to synchronous pacing of the left atrium and the right atrium for patients with IAB (inter-atrial block). In a normal heart, atrial activation initiates with the SA node. In a patient with IAB, the activation is slow being transferred over to the left atrium, and as a result the left atrium may be triggered to contract up to 90 ms later than the right atrium. It can be seen that if contractions in the left ventricle and the right ventricle are about the same time, then left AV synchrony is way off, with the left ventricle not having adequate time to fill up. The advantage of synchronous pacing of the two atria for patients with IAB is disclosed at AHA 1991, Abstract from 64th Scientific Sessions, "Simultaneous Dual Atrium Pacing in High Degree Inter-Atrial Blocks: Hemodynamic Results," Daubert et al., No. 1804
Further, it is known that patients with IAB are susceptible to retrograde activation of the left atrium, with resulting atrial tachycardia. Atrial resynchronization through pacing of the atria can be effective in treating the situation. PACE, Vol. 14, April 1991, Part II, p. 648, "Prevention of Atrial Tachyarrhythmias Related to Inter-Atrial Block By Permanent Atrial Resynchronization," Mabo et al., No. 122. For patients with this condition, a criterion for pacing is to deliver a left atrial stimulus before the natural depolarization arrives in the left atrium.
In view of the published literature, it is observed that in CHF patients improved pump function can be achieved by increasing the filling time of the left ventricle, i.e., improving the left AV delay, and specifically the left heart mechanical AV delay (MAVD); decreasing mitral valve regurgitation, (back flow of blood into the atrium through the nearly closed valve) by triggering contraction of the left ventricle when it is maximally filled. More specifically, for a cardiac pacing system used for treating a CHF patient, the aim is to synchronize atrial and ventricular contractions through optimization of the left and right AV delays so as to properly fill the ventricles and provide maximal filling; and to activate the left ventricle as much as possible to contract in synchrony with the right ventricle. Correct programming of the AV interval is key for optimizing the filling of the ventricles, and optimizing ejection fraction, or cardiac output (CO). Particularly, the AV delay should be set to produce maximal filling of both ventricles during diastole and maximal emptying during systole.
Exact timing of left and right ventricular contraction is important for properly controlling pacing so as to optimize left ventricular output. Specifically, it is known that actual contraction of one ventricular chamber before the other has the effect of moving the septum so as to impair full contraction in the later activated chamber. Thus, while concurrent or simultaneous pacing of the left and right ventricle may achieve a significant improvement for CHF patients, pacing both left and right ventricles at the same time may not always be optimal. For example, if conduction paths in the left ventricle are impaired, delivering a pacing stimulus to the left ventricle at precisely the same time as to the right ventricle may nonetheless result in left ventricular contraction being slightly delayed with respect to the right ventricular contraction. Electrodes are now being positioned adjacent the left ventricle, and can be activated with sequential or simultaneous timing with respect to the right ventricle, resulting in varied timing and activation patterns. If the right and left ventricle are paced simultaneously this may not result in maximized pumping action, with the optimal pacing lead or lag between the ventricles being patient specific.
Echocardiography is sometimes used to set the AV interval in pacing devices. In this procedure, ultrasound is used to produce an echo cardiogram, followed by observation of the E and A waves. The AV interval can be clinically varied to optimize the E and A waves, so that the atrium is allowed to contract and fill the ventricles before the ventricle contracts. If the AV interval is too long, the valves are closed at ventricular contraction. If the AV interval is too short, LV filling does not receive the benefit of the atrial kick. Echocardiography is quite expensive, and can only be done infrequently, in a clinical setting. Quite frequently, the AV pacing intervals are set to a nominal AV interval, without echocardiography.
It is known to use impedance sensors in pacing systems, for obtaining information concerning cardiac function. For example, reference is made to U.S. Pat. No. 5,501,702, incorporated herein by reference, which discloses making impedance measurements from different electrode combinations. In such system, a plurality of pace/sense electrodes are disposed at respective locations, and different impedance measurements are made on a time/multiplexing basis. As set forth in the referenced patent, the measurement of the impedance present between two or more sensing locations is referred to "rheography." A rheographic, or impedance measurement involves delivering a constant current pulse between two "source" electrodes, such that the current is conducted through some region of the patient's tissue, and then measuring the voltage differential between two "recording" electrodes to determine the impedance therebetween, the voltage differential arising from the conduction of the current pulse through the tissue or fluid between the two recording electrodes. The referenced patent discloses using rheography for measuring changes in the patient's thoracic cavity; respiration rate; pre-ejection interval; stroke volume; and heart tissue contractility. It is also known to use this technique of four point impedance measurements, applied thoracically, for measuring small impedance changes during the cardiac cycle, and extracting the first time derivative of the impedance change, dZ/dt. It has been found that a substantially linear relation exists between peak dZ/dt and peak cardiac ejection rate, providing the basis for obtaining a measure of cardiac output. See also U.S. Pat. No. 4,303,075, disclosing a system for measuring impedance between a pair of electrodes connected to or in proximity with the heart, and processing the variations of sensed impedance to develop a measure of stroke volume. The AV delay is then adjusted in an effort to maximize the stroke volume.
Given the demonstrated desirability of cardiac resynchronization therapy (CRT), or bi-ventricular pacing, and the availability of techniques for sensing natural cardiac signals and mechanical events, there nonetheless remains a need to provide pacing intervals which are tuned for improving cardiac output, and in particular for improving left heart function. What would be particularly desirable is a method for also determining the optimal right side to left side pacing delay between the ventricles to obtain maximum cardiac output.

Algorithm for the automatic determination of optimal pacing intervals


Herein described is at least a method and system for improving the performance of a disk drive. A cache work queue and a disk work queue operate together as a dual work queue to facilitate efficient processing of one or more read/write operations performed by the disk drive. In a representative embodiment, the disk drive controller comprises a host interface, a cache buffer, and a disk drive media interface. The disk drive controller comprises the necessary circuitry to execute one or more host commands provided by a host computer. Further, the disk drive controller may facilitate the generation of the cache work queue and the disk work queue. The disk drive controller executes one or more host commands that are received through the host interface such that the cache work queue and disk work queue are employed when a read or write operation is performed.

When performing a read or write operation on a disk drive, a variety of methods have been employed to reduce total data access time. One method, known as command queue reordering, reorders a command sequence that is received from a host computer into an execution sequence for a disk drive. Commands may be temporarily held in a command queue, where they may be reordered. Each command in the command queue contains an instruction for the disk drive that facilitates a read or write operation starting from a particular logical block address (LBA) on the disk. These commands may be uniquely identified by a label or tag, allowing them to be executed in a sequence different from that in which they arrive at the host computer. The idea behind reordering such commands is to minimize the path length that the read/write mechanical actuator or transducer must travel.
Another method to perform command queue reordering utilizes what is known as a rotational positioning optimization (RPO) algorithm. The RPO algorithm may utilize seek time and rotational latency when reordering the command queue. The total access time for a read or write command in the current command queue is computed with respect to the ending LBA of the last executed command, and the command having the shortest access time is moved to the front of the queue.
Yet another more advanced RPO algorithm may be used that considers the state of cache memory, in addition to the command queue. The more advanced RPO algorithm utilizes a cost function for not storing the block in the cache memory and an analogous cost function for storing the new data block into the cache memory. The above referenced RPO schemes try to optimize disk performance for queued commands, utilizing a host-centric approach.
Unfortunately, each of the previous schemes relies on a host-command oriented approach that employs a single work queue. This approach limits the effectiveness for tracking non-host-command work that occurs between the cache memory and the disk drive.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.


A photoconductor, which contains an electrically conductive support, and at least a photoconductive layer provided over the electrically conductive support, wherein the photoconductive layer contains a compound represented by the following general formula (1):

1. Field of the Invention
The present invention relates to a photoconductor, an image forming apparatus, a process cartridge, a compound, and a composition.
2. Description of the Related Art
As for a photoconductor for use in an electrophotographic system, an organic photoconductor has been conventionally known. The electrophotographic system is an image forming process, which is a so-called Carlson process.
There have recently been significant developments with image processing system devices using an electrophotographic system. Especially a digital recording system, where information is recorded with light by converting information into digital signals, has been applied not only printers, but also photocopiers. So-called digital photocopiers have been developed.
As for a light source for use in a digital recording system, a semiconductor laser (LD) or a light-emitting diode (LED) is often used. The emission wavelength range of the LD is in the near infrared region, and the emission wavelength of the LED is longer than 650 nm. Therefore, desired is a photoconductor having high sensitivity in the near infrared region.
In Japanese Patent Application Laid-Open (JP-A) No. 2004-352916, disclosed is a method for producing a pigment containing a butanediol adduct of titanyl phthalocyanine, by allowing 0.6 mol to 1.0 mol of (2R,3R)-2,3-butanediol and/or (2S,3S)-2,3-butanediol to react with 1 mol of titanyl phthalocyanine, followed by treating the reaction product in a solvent in the presence of water. In the X-ray powder diffraction spectrum with the Bragg angle 2θ (±0.2°, the butanediol adduct of titanyl phthalocyanine has a distinct peak at 8.3°.

Abstract: where R1, R2, R3, R4, R5 and R6 are each independently a hydrogen atom, a halogen atom, an alkyl group, an aralkyl group, an alkoxy group, or an aralkyloxy group; n, a, b, c, and d are each independently an integer of 1 to 4 and m is 1 or 2; and a plurality of R1, R2, R3, R4, R5 or R6 may be the same or different when n, m, a, b, c, or d is an integer of 2 or greater.


A data region is provided to a non-effective pixel region, which is not used in generating an image, that constitutes a photosensitive surface of a solid-state image sensor. On a micro lens in predetermined pixels of the data region, a black film is selectively formed. Pixels having the black film are recognized as “0”, and other pixels are recognized as “1”. Individual information of the image sensor is stored in the data region, as digital information. The image sensor outputs an imaging signal including the individual information under a predetermined condition. By determining the value of each pixel in the data region based on the imaging signal, the individual information is read. The read individual information is stored to a predetermined memory. In this way, the individual information can be obtained from the solid-state image sensor built into an imaging device, and set to the imaging device.

1. Field of the Invention
The present invention relates to a method for setting individual information of solid-state image sensor, solid-state image sensor, and imaging device suitable for a digital camera.
2. Description of the Related Art
Conventionally, in an imaging device such as a digital camera, etc., a CCD (Charge Coupled Device) is generally used as a solid-state image sensor. To adequately function the CCD of the imaging device, various setting parameters are necessary. Various setting parameters are generally pre-stored to a predetermined memory in a digital camera, etc. When the digital camera, etc., is operating, the setting parameters are read from the memory. Activation of the CCD and various signal processing are performed based on the read setting parameters. This kind of imaging device is disclosed in for example, Unexamined Japanese Patent Application KOKAI Publication No. 2003-46871.
The above described setting parameter includes common information and individual information. Common information is information which differs according to the type of the CCD, i.e., information that is common among the same types of CCDs. Individual information is information which differs according to each CCD, i.e., information that is unique to each CCD. Concretely, individual information indicates for example, flaw defects, sensitivity of RGB (Red, Green, Blue), and substrate voltage (or the adjustment data thereof). Conventionally, because an average DC bias is generated in the CCD, it is not necessary to provide an adjustment voltage to each CCD, externally. Recently, the number of pixels of the CCD is increasing, and the size of the CCD is becoming smaller. Namely, the size of 1 pixel is becoming smaller. Therefore, there is not enough voltage generated in the CCD, and it is necessary to provide an adjustment voltage individually.
Of the aforementioned individual information, information concerning flaw defects and sensitivity of RGB can be obtained relatively in a short time and easily, even if the CCD is in a state where it is built into the product. For example, information concerning flaw defects can be obtained in about several dozen seconds to one minute. On the other hand, it is hard to obtain the adequate value of the substrate voltage, unless it is before the CCD is built into the product, and it takes a lot of time to obtain it. Therefore, ordinarily, a serial number is printed to the surface of the CCD (generally, to the back side surface), at the manufacturing time of the CCD. Data of the substrate voltage that corresponds to each serial number is provided to the manufacturing factory of a digital camera, etc., in a state where the data is stored in a recording medium, or in the form of a document. The provided data is written into the above described predetermined memory of each product, at the time when the CCD is built into the product, in the manufacturing factory.
However, in a case where the individual information of the CCD is stored to a digital camera, etc. and used as above, there are problems in that it takes time to store the setting parameter, and a cost occurs to manage the setting parameter. Especially, when storing data of the above described substrate voltage, there is a possibility of an input mistake occurring. Furthermore, when re-adjusting the substrate and product that the CCD is built in, there is a problem that the serial number can not be confirmed without dismantling the substrate and product.
The content of the above document, is incorporate herein by reference in their entirety.

Method for setting individual information of solid-state image sensor, solid-state image sensor, and imaging device


For exactly determining the switchover point when producing plastic injection mouldings, two pressure sensors are arranged successively at intervals in the flow direction of the inflowing material, so that the material reaches them at different points in time, and pressure curves (p.sub.1, p.sub.2) are recorded inside the mould cavity. From the measured pressures, the differential pressure is derived. When passing from volumetric filing to compression, the pressures in the mould cavity (p.sub.1, p.sub.2) undergo an abrupt rise (U1, U2). This is reflected in a steep drop of the differential pressure formed, its gradient experiencing a change of sign (V). This indicates that the switchover point has been reached, at which the filling phase must give way to the holding pressure phase.

The invention concerns a process for determining the switchover point when producing a die casting or plastic injection moulding.
When producing metal die castings or injection mouldings of plastic or ceramics, plastic material is injected into the cavity of a die or mould by a suitable injection device, after which it is solidified or cured by cooling. The mould is then opened and the moulding ejected. In injection moulding there are two successive phases. During a filling phase, the mould is filled by an injection device usually being controlled according to a filling program so that the delivery rate obeys certain setpoints on a time scale. As soon as the mould is filled, the injection device is usually controlled during a holding pressure phase so that, according to a holding pressure program, the pressure in the cavity reaches certain setpoints, which may likewise be time-dependent.
It is very important that the switchover point, i.e. the instant of changing from the filling program to the holding pressure program, is determined correctly and coincides as exactly as possible with the instant at which the cavity is just filled completely and volumetrically, i.e. without compression. If the switchover is too soon, there will be a danger of the cavity not being completely filled yet, followed by uncontrolled filling under holding pressure. If switchover is too late, excessive pressure will be reached in the cavity, resulting in a moulding that is brittle and liable to fracture due to internal stresses.
It is therefore decisive that the complete filling of the cavity should be detected as exactly as possible before the onset of a drastic pressure rise. One familiar process DE-A-41 40392 attempts to solve this problem by determining approximately the second derivation of the pressure versus time from measured values of the pressure in the cavity at fixed time intervals, deducing that the switchover point has been reached when this value exceeds a fixed threshold and switching over to the holding pressure program.
This solution has, however, proved to be insufficiently reliable, for considerable pressure variations may occur before the mould cavity is completely filled too, causing the second derivative to exceed the threshold briefly and trigger premature switchover. Within the limits of this known process, this shortcoming can be countered only by raising the threshold, which however poses a danger of the complete mould filling being detected too late, so that switchover is delayed.
Furthermore from EP-A-07 07 936, corresponding to U.S. Pat. No. 5,665,283 a process is known whereby the switchover point is determined by the fuzzy logic method. Since in the fuzzy logic system the measured values are processed in successive stages, this approach again gives a switchover point significantly delayed in relation to the instant at which the mould is actually filled volumetrically.
The object of the invention is to further reduce the lag of the indicated switchover point behind the instant of volumetric mould filling, in order to enhance the quality of the mouldings additionally.
This aim is achieved by the invention. At the end of the volumetric filling process, it is known that the mould cavity pressure undergoes an abrupt rise, which is propagated as a compression front throughout the mould cavity within a few milliseconds. Now if the pressures are measured at two points reached by the material and later the compression front at different times, a differential pressure can be calculated from the two measurements. After the abrupt pressure rise mentioned, this differential pressure drops steeply, reflected in an abrupt sign reversal of its gradient. When this drop exceeds an adjustable threshold, this is interpreted as reaching the switchover point, whereby the threshold ensures that chance fluctuations of the pressures and/or their difference are not misinterpreted by the arrangement as reaching the switchover point.
The new process thus reduces the processing of the measured values to a simple differential pressure formation. This takes place very quickly, so that the new process responds much faster to reaching the volumetric filling than that based on fuzzy logic. Moreover the new process demands far less apparatus than the known processes.
In general, a large number of familiar force or pressure measuring elements, such as strain gauges, are suitable for the pressure measurements to be made, but piezoelectric crystals have proved particularly suited. If these have like polarity, the difference is formed in familiar manner from their measured values, possibly after appropriate amplification, whereas with unlike crystal polarity the measured values are added.
The devices for amplifying, subtracting or adding, and the differential pressure falling below the threshold, and for controlling the switchover to the holding pressure phase, are state of the art and available commercially.
The invention will now be explained in more detail with the aid of figures representing a typical embodiment.

Process for determining the switchover point in the production of a die casting


A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, xcex1-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an SRAM (Static Random Access Memory) and a method for manufacturing the same.
2. Description of the Related Art
FIG. 27 shows an equivalent circuit diagram of an SRAM memory cell. A load transistor Q5 and a driver transistor Q3 form an inverter. A load transistor Q6 and a driver transistor Q4 form an inverter. The inverters are electrically connected to each other to form a flip-flop.
A transfer transistor Q2 connects an output cell node 1000 of the inverter that is formed by the load transistor Q6 and the driver transistor Q4 and a bit line (BL). A gate electrode of the transfer transistor Q2 is electrically connected to a word line.
Source regions of the load transistors Q5 and Q6 electrically connect to a power supply line VDD. Source regions of the driver transistors Q3 and Q4 electrically connect to a ground line Vss.
A transfer transistor Q1 connects an output cell node 1002 of the inverter that is formed by the load transistor Q5 and the driver transistor Q3 and a bit line (/BL). A gate electrode of the transfer transistor Q1 is electrically connected to a word line.
The flip-flop retains a state in which the cell node 1000 is at a voltage of 3V, for example, and the cell node 1002 is at a voltage of 0V, for example, as xe2x80x9c1xe2x80x9d, for example. Also, the flip-flop retains a state in which the cell node 1000 is at a voltage of 0V, for example, and the cell node 1002 is at a voltage of 3V, for example, as xe2x80x9c0xe2x80x9d, for example.
An SRAM may suffer a problem of an xcex1-ray soft error. Materials for wiring layers, molding resin, and the like contain a very small amount of radioactive substances. The radioactive substances generate xcex1-rays. The xcex1-ray soft error is a phenomenon in which retained data is destroyed due to the xcex1-ray. The destruction of retained data by the xcex1-ray soft error will be described below in detail, with reference to the accompanying figure.
FIG. 25 is a cross-sectional view of a silicon substrate 200 in which the load transistor Q6 and the driver transistor Q4 are formed. The silicon substrate 200 is of a p-type. An n-well 202 and a p-well 204 are formed adjacent to each other. A source 212 and a drain 214 of the driver transistor Q4 are formed in the p-well 204. A p-type well contact region 216 is formed in the p-well 204. The well contact region 216 is isolated from the source 212 by a field oxide film 206. The well contact region 216 and the source 212 are electrically connected to the ground line Vss.
A source 218 and a drain 220 of the load transistor Q6 are formed in the n-well 202. An n-type well contact region 222 is formed in the n-well 202. The well contact region 222 is isolated from the source 218 by a field oxide film 210. The well contact region 222 and the source 218 are electrically connected to the power supply line VDD. The drain 220 is isolated from the drain 214 by a filed oxide film 208.
Next, the destruction of retained data by the xcex1-ray soft error will be described with reference to FIGS. 25 and 26. As shown in FIG. 25, when the cell node 1000 is at 3V, for example, the drain 214 is at 3V, and the p-well 204 is biased to the ground line Vss. Therefore, because a diode formed by the drain 214 and the p-well 204 is inversely biased, a depletion layer is formed.
In this state, if an xcex1-ray passes through the drain 214 and the p-well 204 and reaches the silicon substrate 200, the depletion layer of the diode is warped by the xcex1-ray. As a result, electron-hole pairs are cut along the pass of the xcex1-ray. As shown in FIG. 26, the holes flow into the well contact region 216 and into the ground line Vss. The electrons flow into the drain 214 that is at a high voltage. The flows of the holes and the electrons lower the drain voltage. As a result, the retained data is destroyed. In other words, in this example, the state of the cell node 1000 changes from 3V to 0V, and therefore the state xe2x80x9c1xe2x80x9d changes to xe2x80x9c0xe2x80x9d.
It is an object of the present invention to provide a semiconductor memory device with a structure that is difficult to cause harmful effects on the memory function and a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate defining a main surface, and a peripheral circuit region and an SRAM memory cell region in the main surface. The semiconductor memory device comprises a first well, a second well of a first conductivity type, a third well of a second conductivity type, a device element isolation structure, an embedded layer of the second conductivity type, a driver transistor, a load transistor, and an impurity region of the second conductivity type. The first well is formed in the peripheral circuit region, and the second well is formed in the memory cell region. The second well is shallower than the first well. The driver transistor is formed in the second well. The impurity region is formed in the second well. The impurity region is a drain of the driver transistor. The impurity region is an element that composes a cell node. The third well is formed in the memory cell region. The third well is shallower than the first well. The load transistor is formed in the third well. The device element isolation structure is formed in the memory cell region. The device element isolation structure isolates the driver transistor from the load transistor. The second well and the third well are formed to extend to a location under the device element isolation structure. The embedded layer is formed under the second well and under an area where at least the impurity region is located. The embedded layer forms a junction with the second well. The embedded layer is fixed at a potential that prevents carriers of the second conductivity type in the embedded layer from flowing into the second well.
The semiconductor memory device in accordance with the embodiment achieves the following advantages.
The miniaturization of a memory cell must address two conflicting issues. The length of the device element isolation structure (such as a semi-recessed LOCOS oxidation layer) of the memory cell area needs to be shortened in order to miniaturize the memory cell. On the other hand, to prevent the generation of a parasitic MOS leak current that causes latch-up, the spacing between one well and source/drain of another well formed adjacent to the one well needs to be longer than a certain distance. Accordingly, when the length of the device element isolation structure is shortened to miniaturize the memory cell, the spacing between one well and the source/drain of another well formed adjacent to the one well may become too short to an extent that a parasitic MOS leak current may be readily generated. However, in accordance with the embodiment of the present invention, the length of the device element isolation structure can be reduced for the miniaturization of the memory cell, while the distance between one well and the source/drain of another well formed next to the one well can be prevented from becoming too short.
In a semiconductor memory device in accordance with one embodiment of the present invention, the wells in the peripheral circuit region and the wells in the memory cell region may be different in depth. In other words, the second and third wells formed in the memory cell region are shallower than the first well formed in the peripheral circuit region. Accordingly, this structure can reduce an overlapped area between the second well and the third well beneath the device element isolation structure. The reason for this will be described below in conjunction with the discussion of the embodiments. Accordingly, in a semiconductor memory device in accordance with the present invention, the length of the device element isolation structure can be reduced, while the distance between one well and the source/drain of another well formed next to the one well can be prevented from becoming too short.
In accordance with another embodiment of the present invention, the semiconductor memory device of the present invention further includes an embedded layer. The embedded layer is formed in an area under the second well where at least the impurity region is located. The embedded layer forms a junction with the second well. The embedded layer is fixed at a potential that prevents carriers of the second conductivity type in the embedded layer from flowing into the second well.
In the semiconductor memory device in accordance with the present invention, the embedded layer can prevent the generation of an xcex1-ray soft error that may occur in the impurity region of the driver transistor (an element that forms a cell node). For example, when the semiconductor substrate is of a p-type, the embedded layer is an n-type, the second well is of a p-type, and the impurity region is of an n-type, the following phenomenon occurs.
Let us consider a situation when the impurity region of the driver transistor (an element that forms a cell node) is, for example, at a voltage of 3V, and an xcex1-ray passes through the impurity region of the driver transistor, the second well, the embedded layer, and the semiconductor substrate. As a result, the electron-hole pairs are cut. It is believed that only electrons in the second well are drawn to the impurity region (element that forms a cell node) because of the presence of the p-n junction between the second well and the embedded layer. Electrons in the embedded layer and in the semiconductor substrate do not flow into the second well, because the embedded layer is fixed at a positive potential (a potential that prevents the electrons from flowing into the second well).
In the manner described above, only the electrons in the second well are drawn to the impurity region (element that forms a cell node). Accordingly, the voltage at the impurity region (element that forms a cell node) is difficult to become unstable, and, therefore, this makes the retained data difficult to be destroyed.
When a first embedded layer is an n-type, the impurity concentration of the first embedded layer is preferably 5E12-5E13 cmxe2x88x922. This impurity concentration is the same as the impurity concentration of a low resistance layer of the n-type first well.
In the embodiments of the present invention, the cell node refers to a node at which a transfer transistor and an output of an inverter that is formed by a load transistor and a driver transistor are connected to each other.
In accordance with the present invention, examples of the device element isolation structure include a LOCOS oxide film, a semi-recessed LOCOS oxide film, or a shallow trench (the depth ranging between about 0.4 and 0.8 xcexcm).
In accordance with the present invention, the xe2x80x9csource/drainxe2x80x9d refers to at least one of a source and a drain.
In a semiconductor memory device in accordance with another embodiment of the present invention, the following structure may be added. For example, the semiconductor memory device of the present invention includes another impurity region of the first conductivity type. The another impurity region is formed in the third well. The another impurity region is a drain of the load transistor. The another impurity region is an element that forms the cell node. The embedded layer is not formed in an area under the third well where the another impurity region is located. The semiconductor substrate is the first conductivity type.
As a result of the addition of the above-described structure, the generation of an xcex1-ray soft error that may occur in the another impurity region of the load transistor (an element that forms a cell node) can be prevented. For example, when the semiconductor substrate is of a p-type, the embedded layer is n-type, the third well is of an n-type, and the another impurity region is of a p-type, the following phenomenon occurs.
Let us consider a situation where the another impurity region of the load transistor (an element that forms a cell node) is, for example, at a voltage of 0V, and an xcex1-ray passes through the another impurity region of the load transistor, the third well, and the semiconductor substrate, with the result that the electron-hole pairs are cut. As a result, it is believed that only holes in the third well are drawn to the another impurity region (element that forms a cell node) because of the presence of the p-n junction between the third well and the semiconductor substrate.
In this manner, since the embedded layer is not formed in an area under the third well where the another impurity region is located, only the holes generated in the third well among the holes generated by the xcex1-ray result in a soft error. Because the third well is relatively shallow, relatively few holes are generated therein. As a result, the voltage of the another impurity region is difficult to become unstable, and this makes the retained data difficult to be destroyed.
In the semiconductor memory device in accordance with the present invention, the following structure may be added. The semiconductor memory device of the present invention further includes a well contact region of the second conductivity type. The well contact region is formed in the third well, the well contact region is a contact region that fixes a well potential of the third well, and the embedded layer contacts the third well.
As a result of the addition of the above-described structure, the potential of the embedded layer can be fixed at a potential that can prevent the carriers of the second conductivity type in the embedded layer from flowing into the second well. For example, when a positive voltage is applied to the well contact region, electrons generated in the embedded layer in the example described above are drawn from the embedded layer through the third well to the well contact region.
In the semiconductor memory device in accordance with the present invention, the following structure may be added. For example, the semiconductor memory device in accordance with the present invention includes another embedded layer of the first conductivity type. The another embedded layer is formed under the second well, and the another embedded layer contacts the second well.
As a result of the addition of the structure described above, the generation of latch-up can be prevented. More specifically, the conductivity type of the another embedded layer is the same as the conductivity type of the second well, and, therefore, the resistance of the second well is lowered. This contributes to the prevention of the generation of latch-up. In one embodiment, when the another embedded layer is a p-type, the another embedded layer may have an impurity concentration of 5E12-5E13 cmxe2x88x922.
In the semiconductor memory device in accordance with the present invention, the first well, the second well, and the third well may be retrograded wells. The retrograded well is a well that is formed by a high-energy ion implantation without using a thermal diffusion.
Each of the first well, the second well, and the third well, that are retrograded wells, has a first concentration layer, a second concentration layer, and a third concentration layer in the order from a top layer. The first well further has a fourth concentration layer under the third concentration layer. The first concentration layer may be, for example, a channel dope layer that adjusts the threshold voltage (Vth) of the transistor. The second concentration layer may be, for example, a punch-through stopper layer that suppresses the short channel effect of the transistor. The third concentration layer may be, for example, a channel-cut layer that prevents the operation of a parasitic transistor. The fourth concentration layer may be, for example, a low resistance layer that lowers the well resistance. In one embodiment, in the second and third wells, the first concentration layer may be a channel dope layer, the second concentration layer may be a channel stopper layer, and the third concentration layer may be a channel cut layer, for example.
In the semiconductor memory device in accordance with the present invention, the length of the device element isolation region that isolates the wells in the memory cell region may fall within a range of about 0.2 xcexcm-1.6 xcexcm. The border between the second well and the third well needs to be located below the device element isolation structure. When the resist is patterned, a positional alignment error may occur. Accordingly, the device element isolation structure requires a certain minimum length. The minimum length of the structure may be about 0.2 xcexcm. Also, when the device element isolation structure has a length longer than about 1.6 xcexcm, the size of the memory cell becomes too large.
In the semiconductor memory device in accordance with the present invention, the second well and the third well may have a depth of about 0.5-1.2 xcexcm. When the second and third wells are shallower than about 0.5 xcexcm, the device element isolation structure becomes deeper than the wells. This presents a problem in designing as to how a well contact region for fixing the potential of the well is formed. When the second and third wells are deeper than about 1.2 xcexcm, the overlapped area between the second well and the third well, beneath the device element isolation structure, becomes greater.
In the semiconductor memory device in accordance with the present invention, the semiconductor substrate may be of a p-type. As a result, the p-type wells in the memory cell region are connected to one another through the semiconductor substrate, and, therefore, the resistance of the wells is lowered. As a result, this suppresses an increase in the substrate potential of a region, where the n-channel transistor (having a relatively large substrate current compared to the p-channel transistor) is formed.
In accordance with another embodiment of the present invention, a method is provided for manufacturing a semiconductor memory device having a semiconductor substrate defining a main surface, and a peripheral circuit region and an SRAM memory cell region in the main surface. The method includes the following steps. (a) A device element isolation structure is formed in the main surface. (b) A first well is formed by ion-implanting an impurity in the peripheral circuit region. (c) An embedded layer of a second conductivity type is formed by ion-implanting an impurity in the memory cell region. (d) A third well of the second conductivity is formed by ion-implanting an impurity in the memory cell region, wherein the third well is shallower than the first well, formed to extend to a location under the device element isolation structure, and in contact with the embedded layer. (e) A second well of the first conductivity type is formed by ion-implanting an impurity in the memory cell region. The second well is in contact with the third well in an area lower than the device element isolation structure, and is formed over the embedded layer. Also, the second well forms a junction with the embedded layer. (f) A driver transistor is formed in the second well. Among the impurity regions of the driver transistor, an impurity region that forms an element composing a cell node is formed in a manner that the embedded layer is located under the impurity region. (g) A load transistor is formed in the third well.
In the above-described embodiment of the present invention, a method is provided for manufacturing a semiconductor memory device that can prevent the distance between one well and source/drain of another well adjacent to the one well from becoming too short without excessively elongating the device element isolation structure.
In accordance with the present invention, an embedded layer is further formed, as described below. The embedded layer is formed in an area under the second well, under a region where the impurity region of the driver transistor (element that forms a cell node) is located, and forms a junction with the second well. Also, the embedded layer contacts the third well.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, in step (b) and step (c), a resist pattern having a thickness of about 3.0 xcexcm-8.0 xcexcm is used as a mask, and in step (d) and step (e), a resist pattern having a thickness of about 1.2 xcexcm-2.5 xcexcm is used as a mask.
If the thickness of the resist pattern is thinner than about 3.0 xcexcm in steps (b) and (c), the impurity penetrates the resist pattern when the ion implantation is performed to form a retrograded well. If the thickness of the resist pattern is thicker than about 8.0 xcexcm, control of the configuration of the end portion of the resist pattern is difficult. As a result, a problem arises in which the length of the device element isolation structure needs to be increased.
If the thickness of the resist pattern is smaller than about 1.2 xcexcm in steps (d) and (e), the impurity penetrates the resist pattern when the ion implantation is conducted to form a retrograded well. If the thickness of the resist pattern is greater than about 2.5 xcexcm, the control of the configuration of the end portion of the resist pattern is difficult. As a result, a problem arises in which the overlapped area between the second well and the third well below the device element isolation structure becomes greater.
Either a positive resist or a negative resist works as the resist pattern in steps (b) and (c). Also, a positive resist or a negative resist works as the resist pattern in steps (d) and (e). However, more preferably, a positive resist may be used. This is because the positive resist outperforms the negative resist in the control of the vertical configuration of the end portion of the resist pattern and the dimensional control of the resist pattern.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, the step of implanting ions in step (b) includes the step of implanting ions in step (c).
In the method for manufacturing the semiconductor memory device in accordance with another embodiment of the present invention, the following features may be added where the first well is a twin-well having a well of a first conductivity type and a well of a second conductivity type. Step (b) includes implanting ions in a region where the well of the first conductivity type is formed and implanting ions in a region where the well of the second conductivity type is formed, and step (d) includes implanting ions three times in a region where the third well is formed and in a region where the well of the second conductivity type in the peripheral circuit region is formed. The step of implanting ions three times forms the third well having a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the memory cell region. Step (b) and the step of implanting ions three times form the well of the second conductivity type having a fourth concentration layer, a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the peripheral circuit region. Furthermore, step (e) includes implanting ions three times in a region where the second well is formed and a region where the well of the first conductivity type in the peripheral circuit region is formed. The step of implanting ions three times forms the second well having a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the memory cell region; and step (b) and the step of implanting ions three times form the well of the first conductivity type having a fourth concentration layer, a third concentration layer, a second concentration layer and a first concentration layer, in the order from a bottom layer, in the peripheral circuit region.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, the following step (h) may be added. For example, step (h) includes forming another embedded layer of the first conductivity type under a region where the second well is formed.
According to this manufacturing method, the semiconductor memory device has another embedded layer of the first conductivity type, wherein the another embedded layer is formed under the second well, and the another embedded layer contacts the second well.
In the method for manufacturing the semiconductor memory device in accordance with the present invention, the step of implanting ions in step (b) includes implanting ions in step (h).

Semiconductor memory device and method of manufacturing the same


An apparatus for coupling a heat-generating device to a heat-removing device. The apparatus includes a thermally-conductive plate having a first side and a second side. The apparatus also includes a plurality of first channels that intersect with a plurality of second channels formed on at least one of the first side and the second side. The formation of the first channels and the second channels weaken the thermally-conductive plate. The apparatus further includes a plurality of protrusions formed by the intersection of the first channels and the second channels. The protrusions are deformable by coupling the thermally-conductive plate between the heat-generating device and the heat-removing device.

Electronic and mechanical devices generate heat due to inefficiencies. The heat may be removed from the device to prevent possible damage due to overheating. For example, a heat sink may be mounted to the device. A surface on the heat sink may abut a surface on the device to form a thermal connection therebetween. The respective surfaces, however, are typically imperfect, which may provide less actual contact between the respective surfaces (e.g., metal-to-metal contact). Moreover, the imperfections may create a void and thus a volume of air between the respective surfaces. When there is less actual contact between the respective surfaces (e.g., air gaps due to surface imperfections), there may be less heat transfer therebetween.
Traditionally, a thermally-conductive paste and/or grease is added between the device and the heat sink. Thermal conductivity of the paste and/or grease may be low relative to a metal surface of the heat sink. Notwithstanding the low thermal conductivity, the paste and/or grease may fill the volume between the respective surfaces, which may relatively increase the area of contact and the heat transfer between the heat sink and the device. The paste and/or grease, however, may dry and crack over time, which may once again introduce air pockets. The air pockets may reduce the actual contact between the device and the heat sink, thus reducing the heat transfer therebetween and diminishing the benefit of the paste and/or grease. Moreover, use of the paste and/or the grease in mass production may be undesirable because of handling and/or assembly issues.


In a storage system having a plurality of control units each connected with a plurality of disk units, it is provided that a replication is created in the volume of the disk units connected to different control units. The replication creation unit of a given control unit creates a replication in the volume of the disk unit connected to other control units in such a manner that the original volume information, the replication volume information in the control unit and information on the other control units are registered as volume pair information. Based on this volume pair information, a replication creation request is transmitted to the other control units.

The present invention relates to a storage system comprising a plurality of control units each connected with a plurality of disk units.
In recent years, demand has risen to shorten the time required for the process (hereinafter referred to as the backup process) to replicate the data stored in a given storage unit to another storage unit held by a business organization. On the background of this demand is the increase in the information amount held by each organization, and the time consumed for backup is ever on the increase, while the increase in the business hours of each organization has decreased the relative length of time that can be assigned to the backup process.
A "snapshot" has been proposed in JP-A-7-210439 and JP-A-2001-318833 as a technique for backing up the data stored in a storage device without suspending the routine work of organizations. The snapshot is defined as a function of producing a copy of a storage area of a storage device at a specific time point without the intermediary of the computer connected with the storage device. Taking advantage of the function, the user uses the original storage area for business, and the data stored in the copy storage area for backup.

Cluster storage system and replication creation method thereof


A method for receiving up-to-date transportation information at a user entity (120) in a wireless communication system (100) includes requesting up-to-date transportation information (502), determining which up-to-date transportation information is desired (506), requesting access to the desired up-to-date transportation information (510), and obtaining the desired up-to-date transportation information and providing the desired up-to-date transportation information (516, 518) to the user entity (120) for presentation to the user.

While commuting, it can be very helpful to a driver to have up-to-date transportation information to help him make commute-related decisions such as taking an earlier or later bus or train, or traveling a different route when traffic is stopped on a highway. For years, commuters could receive current traffic conditions from other drivers who request and receive current traffic conditions at their locations on a citizen band radio (CB). CB radio's channel 19 is an open channel which allows a CB user to identify their location to other CB users within transmission range, identify their location, and request current traffic conditions near that location. Updating traffic conditions by CB radio, however, is dependent upon having a CB radio user at a location useful to the commuter. In addition, CB radio is generally deployed in vehicles such as automobiles and trucks, and, therefore, is ineffective in providing up-to-date information on bus and train schedules.
Today's wireless communication devices, such as cellular telephones, have a multitude of functions in addition to the traditional point-to-point audio communications. Modern portable communication devices can receive and transmit multimedia signals, such as photos or videos, with or without accompanying audio and, in addition, can access internet sites and information therein. The internet has a multitude of sites, some of which provide transportation information which is updated regularly to keep the information current. For example, train and bus schedules are maintained at internet sites and daily statuses on train or bus delays, possibly providing up-to-the-minute departure and arrival information, can be accessed through such internet sites. In addition, many internet sites provide access to video images from highway cameras placed at various locations on the highways or bridges. To access these internet sites and the current information provided thereon, however, is problematic for a commuter with a cellular telephone or even with a cellular enabled computing device. All cellular access to the internet and surfing thereof is subject to the limitations of the user interface. and the limitations of the cellular system's connectivity to the internet. In addition, surfing the internet from a car while driving along a highway would take attention away from the task of driving. Also, surfing the internet takes time and by the time a commuter has located the appropriate traffic information, it may already be either out-of-date or no longer of interest to the commuter.
Thus, what is needed is a method and apparatus for an up-to-date transportation notification system which provides up-to-date transportation information to a commuter in a timely manner to allow the commuter to utilize the transportation information to for commute-related decisions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

Method and apparatus for an up-to-date transportation notification system


There is disclosed a thermosetting metal oxide-containing film-forming composition for forming a metal oxide-containing film to be formed in a multilayer resist process used in lithography, the thermosetting metal oxide-containing film-forming composition comprising, at least: (A) a metal oxide-containing compound obtained by hydrolytic condensation of a hydrolyzable silicon compound and a hydrolyzable metal compound; (B) a thermal crosslinking accelerator; (C) a monovalent, divalent, or higher organic acid having 1 to 30 carbon atoms; (D) a trivalent or higher alcohol; and (E) an organic solvent. There can be provided a metal oxide-containing film-forming composition in a multi-layer resist process, in a manner that a film made of the composition allows for formation of an excellent pattern of a photoresist film, the composition is capable of forming a metal oxide-containing film as an etching mask having an excellent dry etching resistance, the composition is excellent in storage stability, and the film made of the composition is removable by a solution used in a removal process; a metal oxide-containing film-formed substrate; and a pattern forming process.

1. Field of the Invention
The present invention relates to a metal oxide-containing film-forming composition for forming a metal oxide-containing film to be used in a multi-layer resist process used for fine processing in a manufacturing process of semiconductor devices and the like; a metal oxide-containing film-formed substrate; and a patterning process using the composition.
2. Description of the Related Art
With highly integrated LSI's providing highly increased speeds, finer pattern rules are being rapidly promoted. Commensurately with the fineness, the lithography technique has attained formation of fine patterns, by virtue of light sources of shorter wavelengths and resist compositions appropriately selected therefor. The main role thereof was played by positive photoresist compositions to be each used as a monolayer. The monolayer positive photoresist composition is configured to possess, in a resist resin, a frame having an etching resistance against dry etching by chlorine-based or fluorine-based gas plasma, and to possess such a resist mechanism that an exposed portion is made dissolvable, so that the exposed portion is dissolved to thereby form a pattern, and the remaining resist pattern is used as an etching mask to dry etch a processing substrate coated with the resist composition.
However, when a pattern is made finer, i.e., pattern rules are further narrowed while keeping a thickness of a used photoresist film as it is, the photoresist film is deteriorated in resolution performance. Further, when the resist film is to be developed by a developer to form a pattern, a so-called aspect ratio thereof is made excessively large, thereby resultingly causing a pattern collapse. Thus, the fineness has been accompanied by decrease in photoresist film thickness.
Meanwhile, although for processing of a processing substrate, there is typically used a method for processing the processing substrate by dry etching by adopting a patterned photoresist film as an etching mask, practically no dry etching methods exist to exhibit a complete etching selectivity between a photoresist film and a processing substrate, so that the resist film is also damaged during processing of the processing substrate and the resist film is collapsed, thereby failing to accurately transfer a resist pattern onto the processing substrate. Thus, with finer patterns, resist compositions have been required to have higher dry etching resistances.
Further, since shortened wavelengths of exposure have demanded that resins having lower light absorption at exposure wavelengths are used for resist compositions, such resins have been subjected to a transitional history from a novolak resin, through polyhydroxystyrene, and to a resin having an aliphatic polycyclic frame, commensurately with a transitional history from i-beam, through KrF, and to ArF. However, etching speeds under the dry etching condition have been practically made higher, so that recent photoresist compositions having higher resolutions practically tend to be rather lowered in etching resistance.
This obliges a processing substrate to be dry etched by a photoresist film which is inevitably thinner and weaker in etching resistance, thereby making it urgent to ensure a material and a process in this processing state.
As one method to solve such a problem, multi-layer resist process have been used. The methods are configured to: interpose a resist intermediate film having an etching selectivity different from that of a photoresist film, i.e., a resist upper layer film, between the resist upper layer film and a processing substrate; obtain a pattern in the resist upper layer film; thereafter transfer the pattern to the resist intermediate film by dry etching by using the obtained resist upper layer film pattern as a dry etching mask; and further transfer the pattern onto the processing substrate by dry etching by using the obtained pattern of the intermediate film as a dry etching mask.
In a bilayer resist process as one of the multi-layer resist processes, a silicon-containing resin is used as a resist composition of a upper layer film, and a novolak resin is used as an intermediate film (Japanese Patent Laid-Open (kokai) No. H6-95385, for example). The silicon resin exhibits an excellent etching resistance against reactive dry etching by oxygen plasma, but is easily etched and removed by using fluorine-based gas plasma. In turn, the novolak resin is easily etched and removed by reactive dry etching by oxygen gas plasma, but exhibits an excellent etching resistance against dry etching by fluorine-based gas plasma, chlorine-based gas plasma, or the like. Thus, a novolak resin film as a resist intermediate film is formed on a processing substrate, and a resist upper layer film adopting a silicon-containing resin is formed thereon. Next, the silicon-containing resist film is subjected to pattern formation by a post treatment such as irradiation of energy beam, development, and the like, and the formed pattern is used as a dry etching mask in a manner to remove a novolak resin by reactive dry etching based on oxygen plasma at those portions of the novolak resin where the resist pattern material has been developedly removed, to thereby transfer the pattern to the novolak film. Further, the pattern transferred to the novolak film is used as a dry etching mask, thereby enabling pattern transference to the processing substrate by etching based on fluorine-based gas plasma, chlorine-based gas plasma, or the like.
Since such a pattern transference based on dry etching leads to obtainment of a transferred pattern in a relatively excellent profile when an etching resistance of the etching mask is sufficient, problems are scarcely caused such as pattern collapse due to friction or the like by a developer upon development of a resist, thereby allowing for obtainment of a pattern having a relatively large aspect ratio. Thus, even for a fine pattern which has not been directly formed due to pattern collapse upon development or the like due to a problem of aspect ratio when a resist film exemplarily adopting a novolak resin has been made to have a thickness corresponding to that of the aforementioned intermediate film, the above-described bilayer resist process allows for obtainment of such a novolak resin pattern having a sufficient thickness as a dry etching mask of a processing substrate.
The multi-layer resist process further include a three-layer resist process which can be performed by using a typical resist composition used in a monolayered resist process. For example, this method is configured to form: an organic film as a resist lower layer film based on novolak or the like on a processing substrate; a silicon-containing film as a resist intermediate film, thereon; and a typical organic photoresist film as a resist upper layer film, thereon. Since the organic resist upper layer film exhibits an excellent etching selectivity ratio relative to the silicon-containing resist intermediate film for dry etching by fluorine-based gas plasma, the resist pattern is transferred to the silicon-containing resist intermediate film by means of dry etching based on fluorine-based gas plasma. According to this method, patterns of novolak films having sufficient dry etching resistances for processing can be obtained similarly to the bilayer resist process insofar as patterns can be transferred to silicon-containing films, even by adopting: a resist composition which is difficult to be formed with a pattern having a sufficient film thickness for direct processing of a processing substrate; and a resist composition having an insufficient dry etching resistance for processing of a substrate.
Examples of silicon-containing resist intermediate films to be used in the above-described three-layer resist process include silicon-containing inorganic films by CVD, such as SiO2 films (Japanese Patent Laid-Open (kokai) No. H7-183194, for example) and SiON films (Japanese Patent Laid-Open (kokai) No. H7-181688, for example); and films obtained by spin coating, such as SOG (spin-on-glass) films (Japanese Patent Laid-Open (kokai) No. H5-291208, J. Appl. Polym. Sci., Vol. 88, 636-640 (2003), for example), and crosslinkable silsesquioxane films (Japanese translation of PCT international application No. 2005-520354, for example); and polysilane films (Japanese Patent Laid-Open (kokai) No. H11-60735, for example) would also be usable. Although the SiO2 films and SiON films have excellent performances as a dry etching mask upon dry etching of an underlying organic film, a specific equipment is required for film-formation. Contrary, the SOG films, crosslinkable silsesquioxane films, and polysilane films can be formed by only spin coating and heating, and are thus considered to be high in process efficiency.
The applicability of the multi-layer resist process is not restricted to an attempt to enhance a resolution limit of resist film. In a via-first method which is one of substrate processing methods where a processing intermediate substrate has large height differences, an attempt to form a pattern with a single resist film encounters a problem such as inaccurate focusing during resist exposure due to a substantial difference in resist film thickness. In such a case, the height differences are filled by a sacrificial film and flattened thereby, then a resist film is formed thereon and a resist pattern is formed, and this situation inevitably entails usage of the aforementioned multi-layer resist process (Japanese Patent Laid-Open (kokai) No. 2004-349572, for example).
Silicon-containing films having been conventionally used in such a multi-layer resist process have several problems. For example, it is well known that when a resist pattern is intended be formed by photolithography, exposure light is reflected by a substrate and interferes with incident light, to cause a problem of so-called standing waves, and it is required to interposingly provide an antireflective film as an intermediate film so as to obtain a fine pattern which is free of edge roughness of photoresist film. Particularly, reflection control is indispensable, under the most-advanced high NA exposure conditions.
Then, it becomes necessary to interpose an organic antireflective film between a silicon-containing film and a photoresist film to be formed on the silicon-containing film, in a process for forming the silicon-containing film as a resist intermediate film, particularly by CVD in a multi-layer resist process. However, when such an organic antireflective film is to be additionally interposed, it becomes necessary to pattern the organic antireflective film by using the photoresist film as a dry etching mask, such that transference to processing of the silicon-containing film is allowed after dry etching of the organic antireflective film by using the photoresist film as the mask upon dry etching. As such, the overlying photoresist film is subjected to an additional burden of dry etching to an extent the processing of the organic antireflective film. Particularly, most-advanced photoresist films have been made small in thickness, so that such dry etching burden is not negligible. Thus, attention has been directed to a three-layer resist process utilizing a light-absorbing silicon-containing film as a resist intermediate film which is free of occurrence of the aforementioned etching burden.
Known as such a light-absorbing silicon-containing film to be utilized as a resist intermediate film, is a spin coating type of light-absorbing silicon-containing film. Exemplarily disclosed is a technique for causing the film to have an aromatic structure as a light-absorbing structure (Japanese Patent Laid-Open (kokai) No. 2005-15779).
However, since the aromatic ring structure for effective light absorption has a function to lower a dry etching speed in case of dry etching by fluorine-based gas plasma, this is a disadvantageous way to conduct dry etching of a resist intermediate film without burdening a photoresist film. Then, since addition of a large amount of such light-absorbing substitutional groups is undesirable, it is required to restrict the addition amount to a minimum.
Further, the dry etching speed for reactive dry etching by typically used oxygen gas plasma upon processing of a resist lower layer film while using a resist intermediate film as a dry etching mask, is to be preferably low so as to increase an etching selectivity ratio between the resist intermediate film and the resist lower layer film, so that such a resist intermediate film is desired which has a possibly higher silicon content exhibiting a higher reactivity with a fluorine-based etching gas so as to obtain such a dry etching characteristic. As noted above, those films are preferable having higher contents of silicon which is a component having a higher reactivity with a fluorine gas, in view of the requirement from the processing conditions of both the overlying photoresist film and the underlying organic film.
Actual silicon-containing intermediate film-forming compositions of spin coating type contain organic substitutional groups so that a silicon-containing compound is made dissolvable in an organic solvent. There is disclosed a composition for forming a SOG film among known silicon-containing films as resist intermediate films in lithography using KrF excimer laser light in the J. Appl. Polym. Sci., Vol. 88, 636-640 (2003).
However, since no descriptions are found concerning a light-absorbing group for the disclosed composition, it is supposed that a silicon-containing film to be obtained from the composition fails to have an antireflective function.
This fails to prevent reflection upon exposure in lithography using a most-advanced high-NA exposure system, thereby possibly failing to obtain a finer resist pattern profile.
Moreover, since photoresist films have been further decreased in thickness in a most-advanced semiconductor process using the above-described high-NA exposure system, it is predicted that a pattern transference to a silicon-containing intermediate film is made difficult in case of etching the intermediate film by using a photoresist film as an etching mask, when a silicon content of the silicon-containing intermediate film is merely increased while possessing an antireflective function. As such, materials having faster etching speeds are expected.
As described above, resist intermediate films to be used in multi-layer resist process are required to realize: excellent dry etching characteristics relative to resist upper layer films and resist lower layer films; and highly fine resist pattern profile.
Particular concern in a composition for forming a resist intermediate film having a higher silicon content rate, is a storage stability of the composition. Silanol groups present in silicon-containing compounds included in the compositions sometimes condense, so that molecular weights of silicon-containing film-forming compositions are changed.
Typically, when a hydrolyzable silicon compound is affected by water in the presence of an acid catalyst, a hydrolyzable substitutional group(s) is/are subjected to hydrolysis, to form a silanol group(s). The silanol group is further subjected to a condensation reaction with another silanol group or an unreacted hydrolyzable group, to form a siloxane bond. This reaction is successively and repetitively caused, to resultingly form a silicon-containing compound, so-called an oligomer, polymer, or a sol as the case may be. At this time, the condensation reaction is progressed sequentially from the silanol group having the highest reactivity among those silanol groups derived from monomers, oligomers, polymers, and the like produced by hydrolysis reaction in the system, in a manner to consume silanol groups belonging to the monomers, oligomers, polymers, and the like, thereby forming a silicon-containing compound. Moreover, such a condensation reaction occasionally progresses endlessly, to an extent that the silicon-containing compound solution is eventually gelated. In such a condition, film thickness fluctuation, lithography performance fluctuation, and the like are observed. Since fluctuation of lithography performance is particularly delicate, such a fluctuation is inevitably observed as a change of finer pattern profile even when condensation of silanol groups in molecules is not observable as a film thickness increase or a molecular weight change.
It has been conventionally described that such a highly reactivity silanol group can be relatively stabilized when the same is preserved in an acidic state, in a C. J. Brinker and G. W. Scherer, "Sol-Gel Science: The Physics and Chemistry of Sol-Gel Processing", Academic Press, San Diego, p. 120 (1990) and the like.
Further, there has been disclosed addition of water so as to improve a storage stability, in the J. Appl. Polym. Sci., Vol. 88, 636-640 (2003), Japanese Patent Laid-Open (kokai) No. 2004-157469, Japanese Patent Laid-Open (kokai) No. 2004-191386, and the like.
However, even when such countermeasures are taken for silicon-containing compounds in silicon-containing film-forming compositions produced in the above methods, it is actually impossible to completely stop condensation reactions of silanol groups, so that the silicon-containing compounds slowly change over time, and natures of silicon-containing films to be obtained from the thus changed silicon-containing film-forming compositions are also changed. As such, it has been necessary to preserve them by refrigerating or freezing until just before usage thereof, and to bring them back to a service temperature (typically 23° C.) upon usage in a manner to swiftly use them up.
Meanwhile, in an actual manufacturing process of a semiconductor device, defects are occasionally caused in coated films formed on the substrate, and re-processing is thus to be performed. Conventional SOG films have compositions substantially equivalent to SiO2. Thus, to remove the films, dry delamination or the like based on hydrofluoric acid or fluorine gas has been conducted, but such a removal technique has brought about a serious damage against the substrate.
Against such a problem, there has been sought for a silicon-containing film-forming composition which can be subjected to wet delamination for utilizing a sulfuric acid-hydrogen peroxide-water mixture or ammonia-hydrogen peroxide-water mixture typically used in a conventional semiconductor device production process.

This patent is subject to a terminal disclaimer.

Metal oxide-containing film-forming composition, metal oxide-containing film-formed substrate, and patterning process