Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.

When data is transmitted over a transmission medium to a receiving location, the data may be received in error due to a myriad of causes. Amongst the causes of error are random noise in the channel, bursts of strong noise, drift and nonlinearities in the demodulator. or the like. A broad field of mathematics, which has been embodied in at least one of hardware, firmware, or software has arisen in an effort to overcome the errors introduced in the transmission of data, so that the received data as corrected by an error correcting code (ECC) does not differ from the transmitted data, at least with a certain probability. Such codes are characterized by a code rate, being the ratio of its information content to the overall size of the codeword. For example, for a codeword that contains k data bits and r redundancy bits, that rate is defined by k(k+r).
As first theoretically shown by Shannon, and applied and extended by others, a channel may be characterized by a maximum information rate that may be related to the energy-to-noise ratio of the received signal. Practical error correcting code types do not achieve the theoretical performance predicted by Shannon; however, recent work with low density parity codes (LDPC) shows substantial improvement over Bose-Chaudhuri-Hocquenghem (BCH) and similar cyclic codes. Yet the selection of a coding scheme for a channel is determined not only by the theoretical properties of the code, but of the complexity in computation time, instruction code space, memory or hardware needed to implement the selected coding method as well as the model of the channel itself. This remains true whether the operations are performed in, for example, a FPGA, DSP or a general purpose processor, although the detailed considerations may be somewhat different.
Data storage has been modeled by considering the storage medium to be the conceptual equivalent of the transmission channel, and coding schemes designed for communications channels has been adapted to provide error correcting capabilities for RAM memory, magnetic disk memories, CR ROMs and the like. The behavior of a storage medium may not be characterized as having the same noise statistics as a communications channel having, for example, additive white Gaussian noise (AWGN), and other channel models may be used in order to evaluate and select the appropriate error correcting code.
An evolving form of data memory is NAND FLASH, which is now being used in large-scale data memory systems. Apart from having substantially asymmetrical write and read times, FLASH memory may exhibit technology-related error characteristics, amongst which are wear out, read-disturb, write-disturb, data decay, and the like. Read-disturb and write disturb errors may be considered to be a form of data dependent error. Wear our and data decay are forms of data retention error, and the effect of data decay, generally, is to increase the rate at which the voltage values representing the stored data decay with time. At present, although there is some published data and theoretical work on the characteristics of such FLASH memories, the situation has not stabilized, as the manufacturing technology of the various vendors is still evolving. A variety of techniques are being developed to compensate for and mitigate these characteristics, however residual errors remain.
There are two generic types of NAND FLASH, single level cell (SLC) and multi-level cell (MLC), characterized as storing one bit, or more than one bit, per memory cell, respectively. Today, the MLC FLASH products are favored as they provide the storage at a lower unit cost than the SLC FLASH products, even though the number of erase operations before wear-out is considerably greater for SLC FLASH than for MLC FLASH. Herein, the term MLC may be used to refer to any data storage format having more than one bit per memory cell.
Many other characteristics of the MLC product are less satisfactory than that of a corresponding SLC product, such as read, write and erase performance times. Here, we address only the error characteristics. There is some indication that these disadvantages of MLC are increasing as the manufacturers strive for increases in device density and lower product cost.
Apart from initial manufacturing defects, which are screened by the manufacturer, and which may result in some blocks of a FLASH memory chip not being made available to the user, all of the blocks of memory of a new FLASH memory device exhibit a very low and consistent error rate. The error correction capability under these circumstances need not be very strong. As the FLASH block is programmed (written), erased, and read, over a period of time, errors begin to occur and, after some number of erase operations or storage time, the error rate begins to markedly increase. At some error rate, the device becomes unusable, as whatever error correcting codes are used have insufficient capability to correct, or even to detect, errors.
A higher level operating system may be operable to extend the life of the device by ensuring a reasonable distribution of use across all of the blocks (wear leveling), but when the error rate exceeds some threshold, error-free recovery of the data is not possible. Before such time, a system policy may be executed that declares the FLASH to be worn out, and may migrate the data to an operable FLASH device so that the worn out device may be replaced, or at least not used. The details of such a policy may vary, but the policy generally has at least some relationship to the observed error rate for recovered data.
In another aspect, the operating parameters of a particular FLASH device may be adjusted over a lifetime so as to mitigate the wear on the device, and some manufacturers of solid state disks (SSD) using FLASH have developed procedures to perform these adjustments, sometimes working in concert with the manufacturer of the FLASH devices. While extending the lifetime of a particular version of a FLASH device using vendor specific characteristics and controls may be useful, the manufacturing processes may change, particularly with respect to feature size, and such management of FLASH parameters may lead to inconsistent results.

System and method for correcting errors in data using a compound code


A system and machine-implemented method for processing data associated with an application running on an electronic device. A server receives an HTTP header from the electronic device. The HTTP header is associated with an application running on the electronic device and specifies a content mode for the application. The content mode identifies a type of server content for a user of the application, and corresponds to at least one of plural modes including a child mode in which the type of server content is for a child user. The server receives a request for content from the electronic device, the request being associated with the application, and accesses content for the application based on the received request. The accessed content is provided for the application running on the electronic device. At least one of the accessing or the providing is based on the identified type of server content.

The present disclosure generally relates to client-server applications and, in particular, to providing a cross-platform child mode for applications.
An end user of an electronic device can access content from a server, for example, via a web browser or other application on the electronic device. In some cases, content or functionality provided by the server is not appropriate or suitable for the end user.

Cross-platform child mode for applications


A text completion system that automatically displays a list of completion suggestions for a partial data entry in response to a pause in receipt of the data entry. To avoid annoying the user by displaying an excessive number of wrong suggestions, the text completion system applies search criteria to the partial data entry. If the partial data entry satisfies the search criteria, the text completion system obtains a prioritized list of word predictions for the partial data entry from a word prediction system. To further avoid annoying the user by displaying very short completion suggestions, the text completion system applies display criteria to the word predictions to obtain a prioritized list of completion suggestions that satisfy the display criteria. This prioritized list of completion suggestions is then displayed in a pop-up list box, typically immediately under and to the right of the partial data entry. The completion suggestions are positioned in the list based on a computed indication of likelihood of being correct. The user may accept a completion suggestion from the list by touching a stylus to the display screen over the position of the desired completion suggestion, or by using traditional selection and acceptance keystrokes, such as the "arrow" keys to select a completion suggestion and the "enter" key to accept the selected completion suggestion. Thus, the text completion system allows the user to complete the partial data entry without having to type the remaining letters of the complete data entry.

Miniature computers, commonly known as "hand-held computers" and "personal digital assistants," are becoming increasingly powerful and popular. The user interface included with one of these miniature computers typically includes a small "QWERTY" keyboard, a stylus, and a small touch-sensitive display screen, such as a liquid-crystal display (LCD). The size and speed of basic computer components has improved to the point where miniature computers can now perform many of the text-based functions, such as word processing, e-mail, spreadsheets, personal calendars, and the like that previously required a full-size desktop or laptop computer.
To use a miniature computer for one of these text-based functions, a user typically types on a keyboard to enter text and commands into an active data file, which is open within a host application program running on the computer. Other text input devices may include a voice recognition interface, a touch-sensitive screen that displays a graphical image of a keyboard, and a system that detects the motion of a stylus in combination with handwriting recognition software. The text and commands are then interpreted and manipulated by the host application program in accordance with the syntax and functionality implemented by the host application program.
For many users, the most time consuming computer activity is the entry of large amounts of text into various data files, such as word processing files, personal calendar files, e-mail files, and so forth. Regardless of the input method used, the speed at which the text can be entered into the computer is a major factor governing the user's efficiency. Entering text into a miniature computer can be particularly cumbersome using the small keyboards included with miniature computers. This is because the key size on this type of keyboard is so small that using one's finger to select a key runs a substantial risk of contacting one or more unintended keys. This sort of text entry error can slow text entry and frustrate the user.
Accordingly, effective text-input aids are important attributes for miniature computers. Due to space limitations, however, miniature computers typically carry significantly less computer storage, random-access memory, and processing capacity than their desktop and laptop cousins. In general, because processing speed and memory storage are more restricted for miniature computers, special attention must be given to these aspects of program design. As a result, text-input aids that are feasible to deploy on desktop and laptop computers may not be feasible to deploy on miniature computers. Text-input aids for miniature computers must therefore be designed in light of these relatively severe processing speed and memory-use constraints.
The designers of text-intensive application programs for conventional desktop and laptop computers have developed text-input aids to assist users in entering text into these computers. Although these text-input aids may not be directly applicable to miniature computers, they are generally instructive of the design techniques and considerations often associated with text-input aids. More specifically, the text-input aids developed for conventional desktop and laptop computers may be adapted for use in a miniature computer by modifying the text-input aids to operate with acceptable performance characteristics in view of the relatively severe processing speed and memory-use constraints encountered with the miniature computer.
A text completion system is a type of text-input aid that has been successfully deployed for conventional desktop and laptop computers. Generally stated, a text completion system predicts and suggests complete data entries based on partial data entries. This allows the user to type in a partial data entry and then accept a predicted text completion with a single keystroke, thus avoiding the keystrokes that would have been required to type the complete data entry. For example, a text prediction system may be configured to recognize a user's name so that the user's complete name, "Jossef Goldberg" for instance, may be predicted after the user types the first few letters, "Jos" in this example.
Because there are a limited number of words available in any given language, many of the words forming the vocabulary of the language are used frequently. This is particularly true for data files that include structured fields for certain data entries, such as the "from" and "to" fields of an e-mail message, and the "payee" and "amount" fields of a bank check. A structured field supplies a context for data to be entered into the field. This context can be used to limit the choice of text predictions for the field, and increase the likelihood that a suggested text completion will be correct. Text prediction systems therefore work well for structured data fields because the choice of words used in a particular structured field can often be sufficiently limited so that the word prediction system can offer reasonably likely suggestions within acceptable memory-use and performance characteristics.
Most-recently-used (MRU) text completion methods have also been deployed in connection with structured data fields to speed text entry and also serve as a memory aid for repetitive data entries. These text completion methods use an MRU data list for each structured field to provide a list of predicted text completion choices for the field. That is, a list of the most recent items entered into the structured field is used to predict text completions for partial data entries entered into the field. For example, a personal finance program may maintain a record of a person's previous bank checks. In order to speed entry of the check payee on a new check, the program keeps an MRU list of prior check payees. This MRU list is used to automatically predict a completion for the payee name after the first few letters of the payee have been typed by the user. For instance, if a user has previously written checks to "Georgia Power," the complete data entry "Georgia Power" may be predicted after the letters "Ge" have been typed into the check payee field.
In MRU text completion systems, an input character may be analyzed with respect to the prior history of text entered to predict the text likely to follow the input character or string of characters. Because MRU text prediction systems are based on a prior history of text entered, the search time and amount of storage required for the systems are important parameters. Either a linear or a binary search is typically used to scan the text history in order to predict a text completion. A linear search operates by sequentially examining each element in a list until the target element is found or the list has been completely processed. Because every entry must be analyzed, linear searches are primarily used with very short lists.
A binary search, on the other hand, locates an item by repeatedly dividing an ordered list in half and searching the half that it is known to contain the item. This requires a value for the input that can be compared against values in a list of items arranged in a known sequence, such as ascending numerical order corresponding to lexicographic placement. The binary search begins by comparing the input value against the value in the middle of the list. If the input value is greater than the middle value, the lower half of the list is discarded and the search continues on the upper half. The input value is again compared with a value in the middle of the new list and again half of the list is discarded. The process continues, with the input value being compared against the middle of each succeeding smaller list, until the desired item is found.
Although binary searches can generally be completed relatively quickly if the data to be searched is stored in a format allowing fast random access, both linear and binary searches can require substantial time to complete. This can lead to unacceptable performance when very large search lists must be analyzed. MRU text completion systems therefore tend to be costly in terms of computation resources and performance. Also, without a mechanism for increasing the likelihood of making a correct prediction, such as structured fields in the input data file, the text completion system may make wrong predictions so often that the system may be perceived as more annoying than useful. For this reason, MRU text completion systems have typically been deployed in connection with structured fields.
Restricting the search field using a limited text prediction data space, such as a known data range or naming syntax, is another approach to improving the performance of a text completion system. For example, a spreadsheet program may use the data entries in adjacent rows and columns as a limited data space list for predicting text completion choices when the user is entering a new heading into the spreadsheet. Similarly, an editing program for software development may use a predefined list of valid function and command names as a limited data space for predicting text completion choices when the user is writing a software program. Or a filing system may use the list of previously-created file names as a limited data space for predicting text completion choices when the user is selecting a file. Of course, these limited-data-space text prediction systems only work well when there is a limited and well-defined data space to use for selecting text predictions. They are not well suited to automatic application for all data entries in an unstructured portion of a data file because, in this situation, there is not a readily apparent limited and well-defined data space to use for selecting text prediction choices.
Prior text completion systems have additional shortcomings when deployed in the multiple-application-program environment that exists on most computers systems, including recent generations of miniature computers. These computers allow multiple application programs, such as a word processing program, an e-mail program, and a personal calendar program, to run simultaneously on the computer. User interfaces for the various application programs typically appear in different windows. The user selects one window at a time to receive input, and then inputs text and commands into the selected window using the keyboard or another text input device.
The text completion systems described above are usually deployed on an individual application program basis. That is, each text completion system is typically customized to work only with one particular application program. For example, the check writing text prediction system discussed previously works only with the check writing application program, and not with other application programs, such as a word processing program or e-mail program running on the same computer system. This causes wasteful duplication of software when similar text completion systems are implemented by several different application programs. Duplication of items stored in memory can also result. For example, duplicate items may be stored in memory when several different applications keep separate MRU histories or dictionaries. Another problem is that repetitive data entries cannot be identified across several application programs. As a result, the user may have to "teach" several text completion systems the same set of commonly-used data entries, such as the user's name, address, business name, etc.
As noted previously, all of the difficulties encountered with text completion systems in general are exacerbated in a text completion system for a miniature computer. Thus, there is a general need in the art for a text completion system for use with a miniature computer system having a touch-sensitive display screen and a reduced-size keyboard as primary data entry devices. There is a further need in the art for a text completion system that operates effectively within the restricted processing speed and memory-use characteristics of a miniature computer. There is a further need for an application-independent text completion system that may operate with multiple application programs running on a miniature computer.

Text completion system for a miniature computer


A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits. Each ASP is configurable to generate an ASP interrupt request signal when the value of the last of the multiple data bits is equal to a predetermined value, preferably when the last data bit is set to 1 as commonly used to signal the beginning or end of a data packet. Each ASP includes at least one configuration register, the contents of which determine the operation of the ASP. Generation of the ASP interrupt request signal and the internal DMA request signal is determined by the contents of at least one bit position within the configuration register.

1. Field of the Invention
This invention relates to the manufacture of integrated circuits and more particularly to the manufacture of microcontrollers.
2. Description of the Relevant Art
A typical computer system includes a microprocessor secured within its own semiconductor device package and connected to several separately-packaged support circuits. The support circuits perform support functions such as communication functions and memory interface functions. A microcontroller is an integrated circuit which incorporates a microprocessor core along with one or more support circuits on the same monolithic semiconductor substrate (i.e., chip). Computer systems which employ microcontrollers may thus be formed using fewer semiconductor devices. Advantages of such systems include lower fabrication costs and higher reliabilities. Microcontrollers find applications in industrial and commercial products including control systems, computer terminals, hand-held communications devices (e.g., cellular telephones), photocopier machines, facsimile machines, and hard disk drives.
Asynchronous serial communication is the standard means of transmitting data over distances greater than about 25 feet. In serial data communication, each unit of data (e.g., an 8-bit byte representing a character) is transmitted one bit at a time over a transmission medium (e.g., a pair of wires, a coaxial cable, etc.). FIG. 1a is a diagram of a data "frame" used in asynchronous serial communication. The data frame includes multiple data bits 2 transmitted between a "start" bit 4 and one or more "stop" bits 6. Data bits 2 include n bits of a data unit, D.sub.0 through D.sub.n-1 where n is typically 7 or 8, and an optional parity bit 8 which may be added to facilitate error detection. Start bit 4 is always a 0 and signals the beginning of the frame. The one or more stop bits 6 are always a 1 and signal the end of the frame. Start bit 4 and the one or more stop bits 6 are used to synchronize a transmitter and a receiver during asynchronous serial communication. The transmitter and receiver must both use the same set of rules designating how many bits are transmitted per second (i.e., the baud rate), how many bits are included in a data unit, whether a parity bit is included, and how many stop bits are added after the data bits.
Due to the prevalence of serial data communication, many microcontrollers include one or more asynchronous serial ports (ASPS) which can transmit and/or receive data one bit at a time. Such microcontrollers typically employ interrupt signals to notify the microprocessor core that an ASP requires service. An ASP typically issues an interrupt request signal when a data unit has been received by the ASP and needs to be transferred from the ASP to an external memory unit, or when the ASP has finished transmitting a data unit and the next data unit to be transmitted must be transferred from the external memory unit to the ASP.
The microprocessor core executes instructions of software programs. Upon receiving an interrupt request signal from the ASP, the microprocessor core stops program execution, saves the contents of certain critical registers (i.e., saves its internal state), and begins executing instructions of an appropriate interrupt service routine (i.e., an interrupt handler) associated with the ASP. When execution of the interrupt service routine is completed, the microprocessor core restores the saved contents of the critical registers (i.e., restores the internal state) and resumes execution of the interrupted program at the point where the interruption occurred.
When interrupts are used to service an ASP, the microprocessor core must first save its internal state and execute a portion of the instructions of the interrupt service routine. The amount of time required to perform these actions places an upper bound on the number of bits the ASP may transmit or receive each second (i.e., the maximum operational baud rate of the ASP). In addition, the microprocessor core must interrupt program execution in order to service the ASP, negatively impacting the performance of the microprocessor core.
Direct memory access (DMA) is a well known technique which allows data transfers without involving the microprocessor core. In addition, many microcontrollers include a DMA unit which controls DMA data transfer operations. The microprocessor core simply initializes control registers within the DMA unit with transfer control information. The transfer control information typically includes the first address of the source of the block of data to be transferred (i.e., the source address), the first address of the destination of the block of data to be transferred (i.e., the destination address), and the number of bytes or words to be transferred (i.e., the byte/word count).
When a device needs to transfer data, the device generates a DMA request signal. The DMA unit responds to the DMA request signal by gaining control of the common bus interconnecting the involved devices and initiating the data transfer operation. The DMA unit generates address and control signals needed to read a byte or word of data from the source address and to write the data to the destination address. After each read/write operation, the source and destination addresses and the byte/word count are either incremented or decrement. This process is continued until the data transfer operation is complete. When the data transfer operation is complete, the DMA unit relinquishes control of the common bus.
9-bit serial protocols are increasingly being used to transfer data using asynchronous serial communication. FIG. 1b is a diagram of a data frame used by 9-bit serial protocols. The data frame includes multiple data bits 2 transmitted between a "start" bit 4 and one or more "stop" bits 6. Data bits 2 include 8 bits of a data unit, D.sub.0 through D.sub.7, and a ninth data bit D.sub.8, labeled 9 in FIG. 1b, in place of optional parity bit 8 (FIG. 1a). Ninth data bit 9 (bit D.sub.8) is set to 1 to indicate the beginning and/or end of a message spanning multiple data units (i.e., the beginning and/or end of a data packet). 9-bit serial protocols are commonly used to manage communications between multiple microcontrollers coupled to a common transmission medium. In this case, each data packet typically includes one or more "header" frames at the beginning of the data packet. Each data packet may also include one or more "trailer" frames at the end of the data packet. One of the header frames typically includes a unique device identification (ID) number assigned to the intended receiver. The trailer frames may include, for example, the last data units of the data packet or a cyclic redundancy check (CRC) value for error detection. Ninth data bit 9 is set to 1 in the header and trailer frames and is set to 0 in other data packet frames.
It would thus be desirable to have a microcontroller which is configurable to transfer data to and from one or more ASPs using DMA, and having hardware features which notify the microprocessor core when complete data packets transmitted using a 9-bit serial protocol are received. DMA data transfers increase the maximum baud rate of each ASP and improve the performance of the microprocessor core during ASP operation. When the microprocessor core is involved in the transfer of serial communication data, the microprocessor core is able to determine the beginning and end of data packets transmitted using a 9-bit serial protocol. The use of DMA to accomplish such data transfers does not allow for such a determination. When DMA is used to transfer serial communication data transmitted using a 9-bit serial protocol, additional hardware features are needed to notify the microprocessor core when complete data packets are received.

System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted


A beam scanner is disclosed for confocal microscopes. The beam scanner is provided with a disc-shaped, rotary-driven base unit which largely prevents disruptive optical scattering. The beam scanner is so designed that at least one main surface of the base unit is provided with a reflecting grid; light is reflected only by those regions of the main surface which correspond to the meshes of the reflecting grid, or only by those regions which correspond to the lattice of the reflecting grid.

The invention involves a beam scanner for confocal microscopes with a rotary-drive disk as a base.
Beam scanners with disk-shaped, rotary-drive bases so-called disk scanners, have been used for several years in confocal microscopy. In the confocal microscopic imaging procedure only the structures of an object that are directly in the focal plane of the microscope objective are displayed. In a confocal optical arrangement the object is illuminated in the focal plane by a point light source. The light coming from the object is reflected by a beam splitter in the direction of a point light detector and detected. In this regard the point light source, point light detector, and the limited- diffraction light point on the object in the focal plane lie exactly in the optically conjugate points. Light that comes from outside the focal plane is not focussed sharply on the point light detector and hence is also not registered by the detector. For this reason there are no inputs from unfocussed parts of the object. Object parts that lie outside the focal plane are thus almost faded out. In practice very small pinhole apertures are used for the light source and point light detector. In order now to produce a three-dimensional image of an object, the light point must be guided relative to the object in an appropriate manner. One possibility for this is to use a multipoint scanner in the form of a Nipkow disk. This is a disk driven with an electric motor and having a grid of tiny apertures, so-called pinholes. A problem that occurs in practice in using the known disk scanner involves the light reflected back from the upper surface of the disk that falls on the eyepiece and irradiates or at least affects adversely the image of the object. Avoiding this kind of scattered light effects often requires substantial expenditure on apparatus. In addition, the use of a Nipkow disk as a beam scanner requires relatively expensive auxiliary optics because of the diffraction phenomena that occur at the pinhole apertures.


Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.

An electronic circuit arrangement can include a semiconductor chip and a chip carrier, which are at least partly packaged in a housing (so-called packaging). The chip carrier for the at least one semiconductor chip has a plurality of functions in a finished package. It serves as a stable bearing and holding area to which the semiconductor chip is fixedly connected, dissipates heat that arises, and provides the electrical connections for the semiconductor chip. That is to say that it forms the contact elements for the electronic circuit arrangement which are connected to printed circuit boards, for example, in a further processing step.
The semiconductor chip is usually connected to a chip contact location of the chip carrier (so-called die pad). There are various methods for producing the necessary electrical contacts between the chip carrier and the semiconductor chip. In the case of wire bonding, the semiconductor chip is fixed on the chip contact location and connected to the contact elements of the chip carrier by means of fine wires. The chip contact location then often only forms an electrical conducting line for the semiconductor chip. Such wire bonding to a chip carrier is known for example from German patent application DE 100 31 204.
In the case of the flip-chip method, the unhoused semiconductor chip is applied directly to the contact elements of the chip carrier without further wiring. The chip contact location provides a plurality of contact elements with which the chip comes into electrical contact upon application to the chip carrier. The method is more efficient since all the connections are produced in one method step. In the case of very complex circuits, this technology often affords the only practical possibility for connection because hundreds of contacts can be realized. With the flip-chip method, it is possible here to utilize the entire area of the chip contact location for the connections. This is not possible, or is possible only to a very limited extent, in the case of wire bonding because wires would then cross one another and very probably make contact with one another.
In both cases it is important to produce a stable connection having high electrical and thermal conductivity between the chip carrier, specifically between the chip contact location, and the semiconductor chip.
The chip carrier has a substrate that forms its basic framework and is produced from metal, in particular copper, copper alloys, iron-nickel alloys, and other alloys.
For better further processing of the electronic circuit arrangement, the substrate is preferably provided with at least one soldering layer. Tin or SnPb alloys have been customary for this. Both variants have disadvantages, however. Thus, as is known, lead-containing alloys are avoided on account of the high toxicity. Tin-plated chip carriers tend to form so-called whiskers, acicular elongate crystals, which can lead to short circuits when the circuit arrangement is mounted on printed circuit boards. In order to avoid these problems, it is known from Korean patent application KR 2002 094965, for example, to use palladium-containing soldering layers composed of NiPd or NiPdAu alloys.
These soldering layers have the disadvantage, however, that eutectic bonding with metalized chips, for example, by means of an AuSn or AuAs alloy, is not possible. This is particularly problematic since stringent requirements with regard to reliability, stability and also thermal and electrical conductivity are made of the connection of the chip to the chip carrier.
U.S. Pat. No. 6,376,901 B1 discloses a chip carrier (a so-called leadframe) for integrated semiconductor circuits wherein a nickel layer is plated onto the metallic carrier over the whole area and a palladium layer is plated onto the nickel layer, selectively covering bonding locations of the leadframe. Soldering agent is applied to the nickel layer where parts of the circuit arrangement are intended to be applied to the carrier.


A composition for cleaning water using an electrolytic chlorine generator includes an oxidizer, a pH reducer, a flocculent, a chelator, and a borate compound. A method of cleaning water treated with an electrolytic chlorine generator includes adding, to a body of water treated with an electrolytic chlorine generator, the composition.

Electrolytic chlorine generators or "ECGs" treat water by producing chlorine from sodium chloride using an electrolytic process in which NaCl is converted into hypochlorous acid and sodium hydroxide. ECGs are very effective, but they suffer from several drawbacks. One of the drawbacks is that the generated sodium hydroxide raises the pH of the water. Another drawback is that chlorine generation results in the formation of a lot of calcium, carbonate, sulfate, and phosphate scale on the ECG electrodes and pool surfaces. These drawbacks, when combined, decrease the useful lifetime of the ECG's electrolytic cells and add undesirable impurities to the water.

Water cleaning composition and related methods


A downhole tool for forming a seal in a wellbore includes a housing configured for attachment to a string usable to transport the tool in the wellbore to a target depth; a holding chamber disposed within the housing, the holding chamber configured to receive a combination of a metal, a metal oxide, and a negative thermal expansion material in the holding chamber; an initiator operable to initiate a chemical reaction; a pressure applicator configured to apply pressure to seal material in the holding chamber; and an opening in a surface of the housing through which the seal material is expellable from the holding chamber.

In the resource recovery industry it is common for a wellbore to contain multiple zones that have differing properties. Due to such properties and potentially different actions to enhance production of target fluids from the various zones, it is often desirable to create barriers downhole. Many kinds of barriers exist in the art such as packers, bridge plugs, etc. but they do not meet all of the varying needs of operators in some situations. Accordingly the art would well receive new barrier systems and methods.

Wellbore isolation barrier including negative thermal expansion material


Techniques for tracking dynamically negotiated port connections in a network include collecting statistical information on packets that are sent between nodes on a network, inspecting packets of control connections to detect payload fragments that denote ephemeral port negotiation and producing a mapping from a ephemeral connection flow_id to a control connection flow_id. The techniques also include checking the flow_id to see whether a flow record maps to a control connection.

This invention relates to techniques to detect network anomalies.
Networks allow computers to communicate with each other whether via a public network, e.g., the Internet or private networks. Managing networks is increasingly costly, while the business cost of network problems becomes increasingly high. Managing an enterprise network involves a number of inter-related activities including establishing a topology, establishing policies for the network and monitoring network performance. Another task for managing a network is detecting and dealing with security violations, such as denial of service attacks, worm propagation and so forth.
When collecting data on network traffic it is often necessary to determine the protocol/port used. Most traffic on the Internet uses well-known transport level port numbers. For example, the Hyper-Text Transfer Protocol (HTTP) usually uses port 80/Transmission Control Protocol (tcp); Domain Naming Service (DNS) protocol usually uses port 53/User datagram protocol (udp) and so forth. Some protocols, however, use short-lived (ephemeral), dynamically negotiated port numbers; each connection or transaction might use a different ephemeral port number.

Port tracking on dynamically negotiated ports


An apparatus for sealing the central opening in a conventional closet flange extending perpendicular to a drain pipe. A generally disk-shaped sealing member is connected to the lower end of a threaded shaft screwed through an intermediate hub in a diametrically extending mounting body. A pair of L-shaped retaining arms are pivotally connected to corresponding ends of the mounting body. Heads on the lower ends of the retaining arms may be inserted through diametrically spaced key-shaped slots in the closet flange and engaged with the underside of the flange. A handle connected to the upper end of the shaft may be turned to screw the shaft downwardly. This firmly presses an elastomeric boot on a convex underside of the sealing member against an inner edge of the central opening in the closet flange. This seals the opening in the closet flange to permit pressure testing of the drain and its associates sewer system.

The present invention relates to tools used by plumbers in residential and commercial building construction, and more particularly, to a device which may be readily mounted over the closet flange of a drain pipe normally used to support a toilet bowl flange in order to seal the pipe for pressure testing.
The use of mounting or closet flanges for toilet bowls on drain or discharge sewer pipes in both residential and both commercial construction is well known. See for example U.S. Pat. Nos. 3,181,585; 3,339,215; and 4,090,267. For many years, the closet flange and drain pipe were manufactured as one integral unit made of cast iron. More recently, so-called "drain/waste/vent" (DWV) pipe made of ABS (Trademark) plastic has been extensively utilized. A standard plastic DWV vent pipe is available with an integral closet flange.
The typical closet flange includes two opposed semi-circular slots on the flat receiving surface of the flange, which allow for insertion and then tightening of bolts perpendicular to the surface. Some closet flanges are also provided with diametrically opposed outwardly opening slots in the flange for receiving bolts. This was the typical configuration of the earlier cast-iron closet flanges.
A continual problem which has been faced by plumbers is the proper installation and mounting of drain pipe early in construction, long before the toilet bowl is mounted in place. Some plumbers cover the closet flange opening with duct tape, paper, burlap or anything handy which is easily dislodgable. As a result, debris from construction frequently goes through the opening in the closet flange and into the drain pipe, causing plugging. Since the closet flange is on the floor of the building, debris almost always accumulates in the pipe. The flange openings and the face of the closet flange can become encrusted with tile grout. Cleaning is time consuming and expensive and the closet flange can be broken or damaged.
U.S. Pat. No. 3,846,851 describes a closet flange which incorporates an integral knockout plug. However, there is a chance that the flange can be damaged in the removal of the plug. Also, the knockout plug can fall down into the drain pipe causing plugging. The flange is still subject to damage before the toilet bowl is mounted thereon.
Another problem continually faced by plumbers relates to pressure testing of the sewer system in a building. Most municipalities have a plumbing code, such as the Uniform Plumbing Code (UPC), which requires that the sewer pipe system in a residence or commercial building be capable of withstanding a predetermined internal pressure, between about five pounds per square inch and fifteen pounds per square inch, without any apparent leaks. In order to accomplish such a pressure test, it is necessary for each drain pipe terminating in a closet flange to be sealed. Standards set by the International Association of Plumbing and Manufacturing Offices (IAPMO) prohibit internal threading of the drain pipe portion adjacent the closet flange. Therefore, it is not possible to seal the hole in the closet flange with an externally threaded plug.
There have been several approaches for sealing a closet flange in order to accomplish a pressure test, but each of these approaches is expensive and, in some cases, time consuming. One approach is to insert an elastomeric ball into the drain pipe and to inflate the same to accomplish a seal. These inflatable plugs are expensive and the inflation thereof is both time consuming and dangerous. Over-inflation can lead to explosions, which can injure the plumber. An inflatable seal only seals the inside of the pipe, and does not test the joint between the pipe and the closet flange. An alternate approach is to glue a seal into the hole in the closet flange leading to the drain pipe. However, once the pressure test is complete, this seal must be broken out, and frequently lodges in the drain pipe, causing plugging. Furthermore, the knocking out of a plug which has been glued into place can damage the closet flange.
Another approach to pressure testing of a drain pipe connected to a closet flange is to manufacture a closet flange with an integral breakout seal as indicated above. However, these seals often become lodged in the drain pipe when they are broken out. Therefore, many municipalities are considering banning closet flanges with breakout seals. Yet another approach to sealing the hole in the closet flange is to utilize a so-called "dollar plug". This plug has a large wing nut which is turned by the plumber in order to expand an elastomeric sleeve against the internal walls of the drain pipe adjacent the closet flange. These dollar plugs frequently fail to provide an effective seal, and they are time consuming to install and remove. Also, repeated use of dollar plugs is sometimes impaired because they rust and become encrusted with grout and other debris. The dollar plug frequently does not allow the seal between the pipe and the closet flange to be tested.
U.S. Pat. No. 4,233,697 of Cornwall discloses a protective cover or cap 10 for toilet mounting flange 14 which is installed on a drain pipe 21. The cover 10 is comprised of a disk-shaped plate 11 with tubes 12 that extend upwardly from plate 11 which has a lower surface 11a to mate with the flat toilet bowl surface 13a. A flat elastomeric disk-shaped ring seal 15 is provided to seat between surfaces 11a and 13a and can be either separate or attached to the flange 14 or the cover 11. The bolts 18 which are ultimately used to attach the toilet bowl to the mounting flange 14 are protected in the tubes 12. Cornwall's device is designed to hydrostatically test the toilet bowl mounting flanges to determine if there are any leaks in the flange or in the drain pipe. The preferred embodiment in shown in FIGS. 2 and 3, which discloses the cover 100 having two tubes 118 with rectangular cross-section holes 119. The problem with Cornwall's device is that it is very difficult to attain a true seal when securing a flat disk with only two bolts. Tightening of the two bolts tends to cause the center of the disk to bulge, leaving gaps for leaks.
U.S. Pat. No. 2,559,210 of Bradley discloses a device, including a U-shaped strap 14 for holding a closet flange ring 10 firmly in place over the upper end of the drain pipe 11 during the pouring of concrete 12 around the drain pipe. Bolt and nut assemblies 22 and 23 extend through elongated slots 19 and 20 in the ring 10 and attach to opposite sides of the U-shaped strap 14. A generally cylindrical elastomeric member 32 may be radially expanded against the inner walls of the drain pipe 11 by rotating a wing nut 27 mounted above the center of the U-shaped strap 14. A threaded pipe 31 extends through a slotted portion in the center segment of the U-shaped strap 14 and through the center of the elastomeric member 32. The elastomeric member 32 is squeezed radially against the inner wall of the pipe 11 by turning the wing nut 27 in order to squeeze the elastomeric member 32 between bearing members 28 and 35. When the elastomeric member 32 is squeezed against the inner wall of the pipe 11, the device forms a test plug. The U-shaped strap 14 is not an anchor for the test plug, but rather is held in place by the test plug. The device Bradley is thus very similar to the conventional dollar plug described above. It is difficult and time consuming to install. Significant torque or tightening on wing nut 27 is required. This device may be difficult to repeatedly use because of the build up of debris on the threaded pipe, and because the mechanical components of this device may rust over a long period of time.


A junction device for administering nebulizer treatments directly to a supply of oxygen supplied to a patient mask includes a supply conduit being couplable to an oxygen supply and a patient mask to allow oxygen from the oxygen supply to be supplied to the patient mask. A side conduit is coupled to and is in fluid communication with the supply conduit. An elbow conduit is rotatably coupled to the side conduit opposite the supply conduit. The elbow conduit is couplable to a nebulizer to permit treatments from the nebulizer to flow through the elbow conduit and the side conduit into the oxygen being supplied to the patient mask. A valve assembly is positioned in the elbow conduit between the side conduit and the nebulizer. The valve assembly opens and closes to control the treatments from the nebulizer to flowing into the elbow conduit.

1. Field of the Invention
The present invention relates to patient mask supply junctions and more particularly pertains to a new patient mask supply junction for administering nebulizer treatments directly to a supply of oxygen supplied to a patient mask.
2. Description of the Prior Art
The use of patient mask supply junctions is known in the prior art. The prior art commonly teaches a patient mask having several connections to allow multiple treatment machines to be coupled to the patient mask and thus uses the patient mask to mix treatments provided from the treatment machines.
While these devices fulfill their respective, particular objectives and requirements, the need remains for a device that has certain improved features that allow treatments from a nebulizer to be provided directly to a supply of oxygen supplied to a patient mask prior to the oxygen supply reaching the patient mask. Additionally, the nebulizer may be positioned at a variety of angles to enhance the comfort of a patient wearing the patient mask.


Exemplary embodiments include a method, system, and storage medium for implementing voice-initiated computer functions. The method includes translating a voice command into a machine-readable format. The voice command requests implementation of a function. The method also includes executing the function requested in the voice command, and acknowledging whether the function was successfully completed.

The present invention relates generally to communications services, and more particularly, to methods, systems, and storage mediums for implementing voice-initiated computer functions.
Computer-based systems and applications are becoming more sophisticated over time as advancements are made in the associated hardware/software technologies such as communications protocols, systems standardization, and networks. As the costs of computers and processor-enabled devices decrease, more consumers are acquiring a number of these devices and creating home networks for their personal and/or business use. Additionally, a significant portion of the day may be spent in front of these devices performing, for example, tasks such as word processing, web surfing, messaging, etc. Studies have shown that the more time an individual spends at a computer, particularly without taking regular breaks, the greater the likelihood that this individual will develop muscle strains, poor circulation, eye strain, and similar types of injuries that can lead to more serious health issues and result in diminished productivity. Unfortunately, however, it is often the case that such individuals have little recourse in that their jobs or businesses require that many hours be spent on the computer.
What is needed, therefore, is way to perform the various computer functions needed or desired without requiring that individuals maintain a stationary position.

Methods, systems, and storage mediums for implementing voice-commanded computer functions

AT&T Delaware Intellectual Property, Inc.,


The invention relates to a cosmetic container. According to one aspect of the invention, there is provided a cosmetic container, including: a storing unit providing a first storing space which can store fluid; a discharging unit which discharges the fluid stored in the storing unit to the outside; and a fluid supporting unit which can support from a lower direction fluid which has been discharged to the outside.

With the growing interest of people in skin care, more cream type or gel type of cosmetics having a high viscosity are launched.
In a case where a dip tube type pump is applied to a conventional cosmetic container in which a cosmetic having a high viscosity is stored, it is difficult for the cosmetic to flow into the dip tube, since the cosmetic having a high viscosity is attached to an inner wall of the container. In this case, there is a problem that cosmetic is not discharged to the outside and remained in the cosmetic container. Because of this problem, it is difficult for the conventional cosmetic container for storing a high viscosity cosmetic to employ a pump and a dip tube, and thus the high viscosity cosmetic is stored in a container having a shape of a jar and a user takes some cosmetic out of the jar-shaped container at the time of use.
However, there is a problem that the cosmetic container from which a user takes some cosmetic may cause inconvenience. Further, there is a problem that foreign matters may be entered into the cosmetic container, since a device for taking some cosmetic out of the container should be inserted into the cosmetic container.
Further, there is a problem that in a case where the cosmetic taken out of the cosmetic container needs to be mixed with other cosmetics, a separate container for mixing cosmetics is necessary.
Meanwhile, as the demand for functional cosmetic, customized cosmetic or the like increases, various cosmetic containers are suggested, which can mix cosmetics having different properties, or cosmetics having different dosage form at the time of use. For this, Korean Registered Utility Model No. 20-0464645 suggests a container which can mix cosmetic by rotating a plurality of agitating blades around a rotational axis, which are spaced apart from each other in an up and down direction.
However, as the agitating blades are spaced apart from each other in an up and down direction, there exists a region in which cosmetic is not collided with the agitating blades and thus indirectly agitated by an influence of surrounding flows. Further, it is difficult to form an agitating blade at an upper end part and a lower end part of the rotational axis, and thus these regions would also become a region where cosmetic is indirectly agitated. Accordingly, there is a problem that it is difficult to sufficiently agitate cosmetic in the entire interior of a container, or that the agitating blades should rotate more times to achieve the sufficient agitation.
Further, there exists a problem that the cosmetic attached to an inner wall surface of the container is remained thereon without being agitated not only since the agitating blades are arranged as described above, but also since radial ends of the agitating blades are spaced apart from the inner wall surface of the container. These containers, which have such function of mixing fluid therein, are usually made of a transparent material to make the function of mixing fluid therein appeal to customers. However, it will become a negative point for the design due to the fact that cosmetic is attached to the inner wall surface without being mixed. Particularly, if the cosmetic has a high viscosity, such negative point becomes more noticeable.
Further, it is also a problem that it is difficult to employ a pump to the conventional cosmetic container having a rotating blade, since the agitating blade is fixed to a rotational axle disposed at the center of the cosmetic container. Particularly, there is a problem that it is difficult to employ a dip tube, which extends to or near the bottom of the container, to the conventional cosmetic container having a rotating blade.


The present invention provides an odor discriminating apparatus capable of determining the similarities or differences between plural odors with respect to the odor quality and the odor intensity, and showing the measurement result in such a manner that helps the user to correctly understand the result. According to the present invention, plural samples of a reference odor gas, each sample having a different concentration, are measured with m pieces of odor sensors. Based on the measurement result, a calibration curve is created in an m-dimensional space formed by the detection signals of the m pieces of odor sensors (Steps S1–S3). Next, a measurement point U0 representing the measurement result of a subject odor is plotted in the m-dimensional space. Based on the spatial relation between the measurement point U0 and the calibration curve, an index θ indicating the difference in the quality between the two odors and another index In indicating the difference in the intensity between the two odors are calculated (Steps S4–S9). Then, using a predetermined conversion rule, θ and In are converted into an odor quality difference index and an odor intensity difference index, and the measurement result is plotted on an odor similarity evaluation graph whose abscissa and ordinate correspond to the two indices, respectively (Step S10).

Most of the conventional methods for the instrumental analysis of odors use the component analysis with gas chromatographs or gas chromatograph mass spectrometers. The component analysis, however, is affected by various problems. For example, the measurement takes a long time and requires considerable skill. Furthermore, a large number of measurement signals is obtained for each sample, so that the analysis and interpretation of the signals are difficult and take a long time. Also, the measurement result has no correlation with the organoleptic evaluation by the olfactory sense of a human being.
To solve such problems, some odor measuring apparatuses use odor sensors responsive to odorous substances. Examples of such apparatuses are disclosed in the Japanese Unexamined Patent Publication Nos. H11-352088 and 2002-22692, and "Development of Odor Discriminating Apparatus," KITA, Junichi et al., Shimadzu Review, Vol. 59, No. 1–2 (November 2002), Shimadzu Corp., pp. 77–85. These apparatuses are capable of processing the detection signals produced by plural odor sensors and determining the distances between the odors of plural samples (i.e. whether or not these odors belong to the same or similar categories) by the cluster analysis, principal component analysis or other type of multivariate analysis, or by the non-linear analysis using neural networks.
For example, in the principal component analysis, a graph representing a space formed by plural axes corresponding to different principal components is created, and the results of the measurements of a large number of samples are plotted in the space as measurement points. The spatial relation between the measurement points enables the determination of the similarity or difference between the odors. However, in principle, the principal component analysis allows only a relative comparison of the sensor outputs. In this analysis, the selection of the samples to be simultaneously measured may influence the measurement result. For example, two relatively similar odors might be located very far from each other on the graph, or inversely, two odors having little similarity might be located close to each other on the graph. In such cases, the user often misunderstands the measurement result. Therefore, it is necessary to considerably limit the kinds of odors to be simultaneously measured.
According to another analysis method, the Euclidean distance between the measurement result of a reference odor and that of a subject odor is calculated, and the similarity or difference between the two odors is determined from the Euclidean distance. This method provides the absolute difference between the two odors, but it is impossible to determine whether the difference results from the quantitative difference or the qualitative difference between the odors. For example, in the evaluation of the odors of food, drinks, cosmetics, medicines or other products, it is impossible to determine whether the difference is due to a mixture of an unexpected odor in the subject odor or an excessive addition of the perfumes concerned. Therefore, the evaluation or examination result cannot always be satisfactory.
In view of the above-described problems, the present invention intends to provide an odor discriminating apparatus capable of determining the similarities or differences between plural odors with respect to the odor quality and the odor intensity. The present invention also intends to provide an odor discriminating apparatus capable of visually representing the measurement result in such a manner that helps the user to correctly understand the result and prevents the user from making a wrong determination.


The present invention relates to a motor vehicle control device data transfer system and process. In particular, it relates to such a system and process for the transfer of data, subject to the risk of tampering, from a central data-processing device (12) at the motor vehicle manufacturer's to a motor vehicle data-processing device (5), such as an electronic drive engine control device, in which tamper-free data transfer is guaranteed. In this connection, an authentication enquiry value is generated by the vehicle data-processing device (5) and transferred to the central data-processing device (12) by means of a mobile data-processing device (9). This generates an authentication response value, which is transferred back by the same route with release data.

1. Field of Invention
The present invention relates to a motor vehicle control device data transfer system and process. In particular, it relates to such a system and process for the transfer of data, subject to the risk of tampering, from a central data-processing unit at the motor vehicle manufacturer's to a motor vehicle data-processing unit, such as an electronic vehicle drive engine control device, in which tamper-free data transfer is guaranteed.
2. Description of Related Art
From the prior art, motor vehicles are known, in particular agricultural utility vehicles, such as agricultural tractors, with combustion engines, in particular Diesel engines. The individual component parts of these, such as the drive engine or immobilizer, are controlled by electronic control devices. With such vehicles it is necessary for these control devices to be programmed with data on completion of manufacture, in order to bring the vehicle into an operational state. With the example of a drive engine control device and an immobilizer control device, this means on the one hand that the immobilizer control device is programmed with features of permitted ignition keys. On the other, it means that the drive engine control device is programmed with a communication code for communicating with that immobilizer control device from which it will exclusively accept a start instruction. In order to prevent unauthorized use of the vehicle, it is necessary that this data transfer satisfies high security requirements and cannot be tampered with or compromised.
In addition to this, the drive engine control device is programmed with control data which in particular represents situation-dependent maximum torque values. These are, for example, functions which, depending on the present engine speed, impose a restriction on the maximum selectable desired torque of the drive engine in respect of different aspects, such as overheating protection, overload protection, emission, or performance class of the drive engine. In addition to this, drive engines of a model series are restricted differently in their performance, in order in this way to obtain models of drive engines which may be of the same structural design but are of different performance output. In order to prevent tampering with performance output or erroneous function of the drive engine by changing the programming of the drive engine control device, during operation of the vehicle a comparison is made between the control data and the reference data stored in the immobilizer control device. In order to prevent an unauthorized or illegal increase in performance output by tampering with the control data, it is necessary that this data transfer satisfies high security requirements and cannot be tampered with or compromised.
Such a secure transfer of this security-relevant data can be carried out relatively easily within a supervised area, such as the manufacturer's factory where the vehicle is made, in particular by organizational measures. However, if reprogramming of the electronic control devices of the vehicle becomes necessary due to a vehicle defect or error function, the vehicle has hitherto had to be taken to such a supervised area if the risk was to be excluded of third parties acquiring unauthorized access to the data to be transferred, or of unauthorized persons being able to tamper with the data transfer. This is the case, for example, if the immobilizer becomes blocked and prevents the operation of the vehicle. With agricultural utility vehicles in particular, which can only be transported with considerable effort, this leads to considerable trouble and costs.
The object of the present invention is to resolve this problem. In particular, it is the object of the present invention to provide a motor vehicle control device data transfer system and process which will allow control data to be transferred to control devices secure against tampering, even if the control devices are not taken to a supervised area.
The object is resolved by a system according to Claim 1 and a process according to Claim 16. Advantageous further embodiments are the subject matter of the sub-claims.

Motor vehicle control device data transfer system and process


A radially projecting member (e.g., a paddle assembly) including a pin having a head; a paddle pivotally engaged to the head; and a shear member engaged to the head and to the paddle, the shear member being constructed and arranged to fracture to permit pivotal rotation of the paddle relative to the head.

This invention relates to the field of paddle assemblies, for example, paddle assemblies used in separating, grinding, comminuting, breaking, and otherwise processing a material. For example, paddle assemblies may be used in continuous flow material processing equipment, which may grind and/or otherwise refine a material to be processed.
It is desirable in a wide variety of industries to process materials (e.g., organic materials, inorganic materials, mixtures thereof, etc.). For example, it may be desirable to separate and/or grind a particular material to prepare the material for a downstream application and/or subsequent processing. In some instances, the processing may include contacting a material to be processed with one or more paddles for the purpose of separating, grinding, comminuting, breaking, and otherwise processing a material.
For example, grinding and comminuting apparatus are used for reducing the size of materials, such as food products, chemicals, rubbers, resins, garbage (e.g., food waste), waste-paper, wood chips, waste fiber (e.g., cloth, gypsum), plastics, glass, metal chips, or the like. Conventional grinding/comminuting apparatus, such as that disclosed in U.S. Pat. No. 4,129,260, issued Dec. 12, 1978 to Baker, entitled Garbage Disposal, and U.S. Pat. No. 3,973,735, issued Aug. 10, 1976 to Ito et al., entitled Apparatus For Pulverizing And Sorting Municipal Waste, typically include a grinding chamber with high speed rotating beaters/hammers that tear, shred, slash, cut, and/or grind one or more desired products to a desired size.
However, depending on the material contacted by the paddles, the processing conditions, and the construction of the paddle assemblies (e.g., including the engagement thereof to a rotating drive shaft), obstructions that contact the paddles have been known to damage (e.g., breaking, bending, plastically deforming, etc.) rotating paddle assemblies and/or other portions of the processing equipment (e.g., drive shaft, drive source, etc.). Repairing or replacing paddle assemblies and other portions of the processing equipment can be costly, due to, for example, increased capital and labor expense, as well as increased downtime.
In some processing equipment, the failure of a single paddle assembly has been known to cause damage to one or more additional paddle assemblies or may otherwise reduce the processing efficiency of the processing equipment to an undesirable level. The reduced processing efficiency may require prematurely shutting down the processing equipment to repair the single damaged paddle assembly, resulting in decreased processing time and increased downtime.
Thus, improved paddle assemblies and processing equipment are desired to, for example, reduce maintenance time, maintenance expense, and/or processing equipment downtime.

This patent is subject to a terminal disclaimer.


A method for computing a decimation-in-time Fast Fourier Transform of a sample is provided, the method including inputting first 2B-bit values representing the sample into a radix-4 first section of the decimation-in-time Fast Fourier Transform and performing first complex 2B-bit integer additions and subtractions on the first 2B-bit values to form second 2B-bit values, without performing a multiplication. The method also includes rounding the second 2B-bit values to form B-bit values output from the radix-4 first section of the decimation-in-time Fast Fourier Transform.

1. Field of the Invention
This invention relates generally to digital signal processing, and in particular to methods for carrying out an inverse Fast Fourier Transform.
2. Description of the Related Art
Quantization noise in an Inverse Fast Fourier Transform (IFFT) used, for example, in digital signal processing (DSP), can result in an output that contains errors having relatively large spectral peaks, when analyzed in the spectral domain. Such quantization noise in the IFFT used in DSP is especially noticeable for low-level signals. For example, for audio signals, the quantization noise can result in an audible tonal noise that can be objectionable.
Typically, the IFFT used in DSP is performed using the same data type throughout, for example, B-bit data. When the IFFT used in DSP is implemented using either dedicated digital signal processors or general purpose digital computer processors with a finite word length, quantization noise will appear in the output. If the quantization noise is too large, typical corrective actions include: 1) increasing the word length or size, for example, to accommodate 2B-bit data, thus reducing the quantization error and/or 2) using floating-point representations instead of using fixed point representations. However, increasing word length and/or using floating-point representations can significantly increase circuit size and complexity and/or program execution time and/or required data storage.
The Fast Fourier Transform (FFT) is a well known algorithm used in DSP for transforming a set of N time-domain sample points into a corresponding set of N frequency-domain sample points. The FFT processes find utility in a variety of applications, including machine-implemented speech recognition, image enhancement or video or tomography signals, adaptive filtering of digitized waveforms, audio compression and so forth.
The basic FFT equations are: ##EQU1##
where j=.sqroot.(-1) so that j.sup.2 =-1, j.sup.3 =-j and j.sup.4 =+1. The time-domain samples are represented as x(0) through x(N-1). The frequency-domain samples are represented as X(0) through X(N-1).
The basic FFT equations show that each frequency-domain component X(p) is a weighted sum of all N time-domain components x(n), for n=0, 1, 2, . . . , N-1. The weights W.sub.N.sup.np are referred to as twiddle factors.
The basic IFFT equations are: ##EQU2## where z*=x-jy is the complex conjugate of z=x+jy. The basic IFFT equations show that each time-domain component x(n) is a weighted average of all N frequency-domain components X(p), for p=0, 1, 2, . . . , N-1. The weights W.sub.N.sup.-np =[W.sub.N.sup.np ]* for the IFFT are the complex conjugates of the twiddle factors W.sub.N.sup.np for the FFT. The expression in the brackets in the second equation for each time-domain component x(n) is recognizable as the FFT of the sequence {X*(p)}(for p=0, 1, 2, . . . , N-1), the complex conjugate of the frequency-domain component sequence {X(p)}(for p=0, 1, 2, . . . , N-1). Thus, the IFFT for each time-domain component x(n) can be computed by taking the complex conjugate of the FFT of the sequence {X*(p)}(for p=0, 1, 2, . . . , N-1), and dividing by the number of points N.
The basic FFT equation ##EQU3## for p=0, 1, 2, . . . , N-1, can be inserted into the basic IFFT equation ##EQU4## for n=0, 1, 2, . . . , N-1, to give: ##EQU5##
where ##EQU6## where .delta..sub.kn is the Kronecker delta.
Similarly, the basic IFFT equation ##EQU7## for n=0, 1, 2, . . . , N-1, can be inserted into the basic FFT equation ##EQU8## for p=0, 1, 2, . . . , N-1, to give: ##EQU9## Thus, the FFT and IFFT are, indeed, an invertible transform pair.
Machine-implemented computation of an FFT is often simplified by cascading together a series of simple multiply-and-add sections. When a recursive process is used, data circulates through a single section and the computational structure of the section is made variable for each circulation. Each circulation through the section is referred to as a "pass". When the number N of time-domain and frequency-domain sample points satisfies the relation N=2.sup.M, where M is a positive integer, then the number M is typically referred to as the number of "stages" of the FFT.
A plurality of computational elements, each known as a radix-r butterfly, may be assembled to define a single section of the FFT for carrying out a particular pass. A radix-r butterfly receives r input signals and produces a corresponding number of r output signals, where each output signal is the weighted sum of the r input signals. The radix number, r, in essence, defines the number of input components that contribute to each output component.
By way of example, as shown in FIG. 1, a radix-2 butterfly for a decimation-in-time (DIT) FFT receives two input signals A and B and produces two output signals X and Y so that X=A+W.sub.N.sup.k B and Y=A-W.sub.N.sup.k B, where ##EQU10## and the k on the arrow heading into the open circle shown in FIG. 1 represents the exponent of the twiddle factor W.sub.N.sup.k. Each output signal X=A+W.sub.N.sup.k B and Y=A-W.sub.N.sup.k B is the weighted sum of the two input signals A and B.
As shown in FIG. 2, a radix-4 butterfly for a DIT FFT receives four input signals A, B, C and D and produces four output signals X, Y, Z and V so that X=A+W.sub.N.sup.k B+W.sub.N.sup.l C+W.sub.N.sup.m D, Y=A-jW.sub.N.sup.k B-W.sub.N.sup.l C+jW.sub.N.sup.m D, Z=A-W.sub.N.sup.k B+W.sub.N.sup.l C-W.sub.N.sup.m D and V=A+jW.sub.N.sup.k B-W.sub.N.sup.l C-jW.sub.N.sup.m D, where ##EQU11## and the k, l
and m on the arrows heading into the open circle shown in FIG. 2 represent the exponents of the twiddle factors W.sub.N.sup.k, W.sub.N.sup.l and W.sub.N.sup.m. Each output signal X=A+W.sub.N.sup.k B+W.sub.N.sup.l C+W.sub.N.sup.m D, Y=A-jW.sub.N.sup.k B-W.sub.N.sup.l C+jW.sub.N.sup.m D, Z=A-W.sub.N.sup.k B+W.sub.N.sup.l C-W.sub.N.sup.m D and V=A+jW.sub.N.sup.k B-W.sub.N.sup.l C-jW.sub.N.sup.m D is the weighted sum of the four input signals A, B, C and D.
Completion of an N-point FFT requires that the product of the butterfly radix values, taken over the total number of sections or passes, equals the total point count, N. Thus, a 64-point FFT (constituting 6 stages since 64=2.sup.6) can be performed by one section (constituting all 6 stages at once) having 1 radix-64 butterfly or two cascaded sections (each constituting 3 stages) where each section has 8 radix-8 butterflies (the product of the radix values for section-1 and section-2 is 8.times.8=64) or three cascaded sections (each constituting 2 stages) where each section has 16 radix-4 butterflies (the product of the radix values for section-1, section-2 and section-3 is 4.times.4.times.4=64) or six cascaded sections (each constituting 1 stage) where each section (or stage) has 32 radix-2 butterflies (the product of the radix values for section-1 through section-6 is 2.times.2.times.2.times.2.times.2.times.2=64).
It has been shown that multi-section or multi-pass FFT processes can be correctly carried out under conditions where the number of butterfly elements changes from one pass or section to the next and the corresponding radix value r.sub.i (of the butterfly elements of section-i) also changes accordingly from one pass or section to the next. A mixed-radix system is one where the radix value r.sub.i (of the butterfly elements of section-i) is different from at least one radix value r.sub.k (of the butterfly elements of section-k) for i.noteq.k.
An advantage of a mixed-radix computing system is that it can be "tuned" to optimize the signal-to-noise ratio of the FFT and/or to minimize the accumulated round-off error of the total FFT for each particular set of circumstances. By way of example, it may be advantageous in one environment to perform a 64-point FFT using the mixed-radix sequence: 2, 4, 4, 2. In a different environment, it may be more advantageous to use the mixed-radix sequence: 4, 2, 4, 2. Round-off error varies within a machine of finite precision as a function of radix value and the peak signal magnitudes that develop in each section or pass.
The Cooley-Tukey algorithm, as described in E. Oran Brigham, The Fast Fourier Transform, Prentice-Hall, Englewood Cliffs, N.J., 1974, pp. 188-190, provides an N-point DIT FFT for arbitrary radix where N=r.sub.1 r.sub.2 . . . r.sub.m, where r.sub.1, r.sub.2, . . . , r.sub.m are all integer valued. Expressing the indices n and p in a variable radix representation: EQU p=p.sub.m-1 (r.sub.1 r.sub.2 . . . r.sub.m-1)+p.sub.m-2 (r.sub.1 r.sub.2 . . . r.sub.m-2)+ . . . +p.sub.2 r.sub.1 .sub.2 +p.sub.1 r.sub.1 +p.sub.0 EQU n=n.sub.m-1 (r.sub.2 r.sub.3 . . . r.sub.m)+n.sub.m-2 (r.sub.3 r.sub.4 . . . r.sub.m)+ . . . +n.sub.2 r.sub.m-1 r.sub.m +n.sub.1 r.sub.m +n.sub.0 where
p.sub.i-1 =0,1,2, . . . r.sub.i -1;1.ltoreq.i.ltoreq.m and n.sub.i =0,1,2, . . . , r.sub.m-i -1;0.ltoreq.i.ltoreq.m-1, the basic FFT equation ##EQU12## for p=0, 1, 2, . . . , N-1, becomes: ##EQU13## where the time-domain samples x(n) are presented in digit-reversed order so that the resulting frequency-domain samples X(p) will be in natural digit order. Since ##EQU14## using ##EQU15## for any integer s, then ##EQU16## where the brackets define the first section of the N-point DIT FFT: ##EQU17## Similarly, since ##EQU18##
again using ##EQU19## for any integer s, then ##EQU20## where the brackets define the second section of the N-point DIT FFT: ##EQU21## Generally the kth section of the N-point DIT FFT is defined, for 2.ltoreq.k.ltoreq.m-1, as follows: ##EQU22## so that, for example, the third section of the N-point DIT FFT is: ##EQU23## is the mth and final section of the N-point DIT FFT.
For example, the N-point DIT FFT for N=r.sub.1, where r.sub.1 is integer valued, becomes: ##EQU24## which, for r.sub.1 =2 is just the radix-2 butterfly for a DIT FFT, as shown in FIG. 1, with k=0, A=x(0), B=x(1), X=X(0) and Y=X(1). Similarly, for r.sub.1 =4, ##EQU25## is just the radix-4 butterfly for a DIT FFT, as shown in FIG. 2, with k=l=m=0, A=x(0), B=x(1), C=x(2), D=x(3), X=X(0), Y=X(1), Z=X(2) and V=X(3).
Likewise, the N-point DIT FFT for N=r.sub.1 r.sub.2, where r.sub.1 and r.sub.2 are integer valued, becomes: ##EQU26## which, for r.sub.1 =2=r.sub.2, is given by just two stages of 2 radix-2 butterflies each, as shown in FIG. 3. Expanded out, the 4-point DIT FFT, for N=2.sup.2, is given by:
X(00)=x.sub.2 (00)=x.sub.1 (00)+x.sub.1 (10)=[x(00)+x(10)]+[x(01)+x(11)],
X(01)=x.sub.2 (01)=x.sub.1 (01)+(W.sub.4).sup.1 x.sub.1 (11)=[x(00)-x(10)]+(W.sub.4).sup.1 [x(01)-x(11)],
X(10)=x.sub.2 (10)=x.sub.1 (00)-x.sub.1 (10)=[x(00)+x(10)]-[x(01)+x(11)],
X(11)=x.sub.2 (11)=x.sub.1 (01)-(W.sub.4).sup.1 x.sub.1 (11)=[x(00)-x(10)]-(W.sub.4).sup.1 [x(01)-x(11)], where the arguments of the time-domain samples x(n) and the frequency-domain samples X(p) are presented in binary form, n.sub.1 n.sub.0 and p.sub.1 p.sub.0. As shown in FIG. 3, the time-domain samples x(n) are input to the radix-2 first stage in (binary) digit-reversed order (reversed-binary order), {00,10,01,11}, while the frequency-domain samples X(p) are output from the final radix-2 stage (the second stage, in this example) in natural (binary) digit order, {00,01,10,11}. A correspondence with the radix-4 butterfly for a DIT FFT, as shown in FIG. 2, with k=l=m=0, may be made with the identifications: A=x(00), B=x(01), C=x(10), D=x(11), X=X(00), Y=X(01), Z=X(10) and V=X(11).
The N-point DIT FFT for N=r.sub.1 r.sub.2 r.sub.3, where r.sub.1, r.sub.2 and r.sub.3 are integer valued, becomes: ##EQU27## which, for r.sub.1 =2=r.sub.2 =r.sub.3 is given by three stages of 4 radix-2 butterflies each, as shown in FIG. 4. Expanded out, the 8-point DIT FFT, for N=2.sup.3, is given by:
X(000)=x.sub.3 (000)=x.sub.2 (000)+x.sub.2 (100)=[x.sub.1 (000)+x.sub.1 (010)]+[x.sub.1 (100)+x.sub.1 (110)]=[[x(000)+x(100)]+[x(010)+x(110)]]+[[x(001)+x(101)]+[x(011)+x(111)]]
X(001)=x.sub.3 (001)=x.sub.2 (001)+(W.sub.8).sup.1 x.sub.2 (101)=[x.sub.1 (001)-jx.sub.1 (011)]+(W.sub.8).sup.1 [x.sub.1 (101)-jx.sub.1 (111)]=[[x(000)-x(100)]-j[x(010)-x(110)]]+(W.sub.8).sup.1 [[x(001)-x(101)]-j[x(011)-x(111)]],
X(010)=x.sub.3 (010)=x.sub.2 (010)+(W.sub.8).sup.2 x.sub.2 (110)=[x.sub.1 (000)-x.sub.1 (010)]+(W.sub.8).sup.2 [x.sub.1 (100)-x.sub.1 (110)]=[[x(000)+x(100)]-[x(010)+x(110)]]+(W.sub.8).sup.2 [[x(001)+x(101)]-[x(011)+x(111)]],
X(011)=x.sub.3 (011)=x.sub.2 (011)+(W.sub.8).sup.3 x.sub.2 (111)=[x.sub.1 (001)+jx.sub.1 (011)]+(W.sub.8).sup.3 [x.sub.1 (101)+jx.sub.1 (111)]=[[x(000)-x(100)]+j[x(010)-x(110)]]+(W.sub.8).sup.3 [[x(001)-x(101)]+j[x(011)-x(111)]],
X(100)=x.sub.3 (100)=x.sub.2 (000)-x.sub.2 (100)=[x.sub.1 (000)+x.sub.1 (010)]-[x.sub.1 (100)+x.sub.1 (110)]=[[x(000)+x(100)]+[x(010)+x(110)]]-[[x(001)+x(101)]+[x(011)+x(111)]]
X(101)=x.sub.3 (101)=x.sub.2 (001)-(W.sub.8).sup.1 x.sub.2 (101)=[x.sub.1 (001)-jx.sub.1 (011)]-(W.sub.8).sup.1 [x.sub.1 (101)-jx.sub.1 (111)]=[[x(000)-x(100)]-j[x(010)-x(110)]]-(W.sub.8).sup.1 [[x(001)-x(101)]-j[x(011)-x(111)]],
X(110)=x.sub.3 (110)=x.sub.2 (010)-(W.sub.8).sup.2 x.sub.2 (110)=[x.sub.1 (000)-x.sub.1 (010)]-(W.sub.8).sup.2 [x.sub.1 (100)-x.sub.1 (110)]=[[x(000)+x(100)]-[x(010)+x(110)]]-(W.sub.8).sup.2 [[x(001)+x(101)]-[x(011)+x(111)]],
X(111)=x.sub.3 (111)=x.sub.2 (011)-(W.sub.8).sup.3 x.sub.2 (111)=[x.sub.1 (001)+jx.sub.1 (011)]-(W.sub.8).sup.3 [x.sub.1 (101)+jx.sub.1 (111)]=[[x(000)-x(100)]+j[x(010)-x(110)]]-(W.sub.8).sup.3 [[x(001)-x(101)]+j[x(011)-x(111)]],
where the arguments of the time-domain samples x(n) and the frequency-domain samples X(p) are presented in binary form, p.sub.2 p.sub.1 p.sub.0 and n.sub.2 n.sub.1 n.sub.0. As shown in FIG. 4, the time-domain samples x(n) are input to the radix-2 first stage in (binary) digit-reversed order (reversed-binary order), {000,100,010,110,001,101,011,111}, while the frequency-domain samples X(p) are output from the final radix-2 stage (the third stage, in this example) in natural (binary) digit order, {000,001,010,011,100,101,110,111}.
The 8-point DIT FFT for N=r.sub.1 r.sub.2, where r.sub.1 =2 and r.sub.2 =4, becomes: ##EQU28## which is given by a first section (one stage) of 4 radix-2 butterflies followed by a second section of 2 radix-4 butterflies, as shown in FIG. 5. Expanded, the 8-point DIT FFT, for N=r.sub.1 r.sub.2, where r.sub.1 =2 and r.sub.2 =4, is given by:
X(00)=x.sub.2 (00)=x.sub.1 (00)+x.sub.1 (10)+x.sub.1 (20)+x.sub.1 (30) =[x(00)+x(10)]+[x(01)+x(11)]+[x(02)+x(12)]+[x(03)+x(13)],
X(01)=x.sub.2 (01)=x.sub.1 (01)+(W.sub.8).sup.1 x.sub.1 (11)+(W.sub.8).sup.2 x.sub.1 (21)+(W.sub.8).sup.3 x.sub.1 (31) =[x(00)-x(10)]+(W.sub.8).sup.1 [x(01)-x(11)]+(W.sub.8).sup.2 [x(02)-x(12)]+(W.sub.8).sup.3 [x(03)-x(13)],
X(10)=x.sub.2 (10)=x.sub.1 (00)-jx.sub.1 (10)-x.sub.1 (20)+jx.sub.1 (30) =[x(00)+x(10)]-j[x(01)+x(11)]-[x(02)+x(12)]+j[x(03)+x(13)],
X(11)=x.sub.2 (11)=x.sub.1 (01)-j(W.sub.8).sup.1 x.sub.1 (11)-(W.sub.8).sup.2 x.sub.1 (21)+j(W.sub.8).sup.3 x.sub.1 (31) =[x(00)-x(10)]-j(W.sub.8).sup.1 [x(01)-x(11)]-(W.sub.8).sup.2 [x(02)-x(12)]+j(W.sub.8).sup.3 [x(03)-x(13)],
X(20)=x.sub.2 (20)=x.sub.1 (00)-x.sub.1 (10)+x.sub.1 (20)-x.sub.1 (30) =[x(00)+x(10)]-[x(01)+x(11)]+[x(02)+x(12)]-[x(03)+x(13)],
X(21)=x.sub.2 (21)=x.sub.1 (01)-(W.sub.8).sup.1 x.sub.1 (11)+(W.sub.8).sup.2 x.sub.1 (21)-(W.sub.8).sup.3 x.sub.1 (31) =[x(00)-x(10)]-(W.sub.8).sup.1 [x(01 )-x(11)]+(W.sub.8).sup.2 [x(02)-x(12)]-(W.sub.8).sup.3 [x(03)-x(13)],
X(30)=x.sub.2 (30)=x.sub.1 (00)+jx.sub.1 (10)-x.sub.1 (20)-jx.sub.1 (30) =[x(00)+x(10)]+j[x(01)+x(11)]-[x(02)+x(12)]-j[x(03)+x(13)],
X(31)=x.sub.2 (31)=x.sub.1 (01)+j(W.sub.8).sup.1 x.sub.1 (11)-(W.sub.8).sup.2 x.sub.1 (21)-j(W.sub.8).sup.3 x.sub.1 (31) =[x(00)-x(10)]+j(W.sub.8).sup.1 [x(01)-x(11)]-(W.sub.8).sup.2 [x(02)-x(12)]-j(W.sub.8).sup.3 [x(03)-x(13)], where the arguments of the time-domain samples x(n) are presented in binary/ternary form, n.sub.1 n.sub.0, with n=4n.sub.1 +n.sub.0, for n.sub.1 =0, 1, and n.sub.0 =0, 1, 2, 3, and the frequency-domain samples X(p) are presented in ternary/binary form, p.sub.1 p.sub.0, with p=2p.sub.1 +p.sub.0, for p.sub.1 =0, 1, 2, 3, and p.sub.0 =0, 1. As shown in FIG. 5, the time-domain samples x(n) are input to the radix-2 first section (first stage) in (ternary/binary) digit-reversed order, {00,10,01,11,02,12,03,13}, while the frequency-domain samples X(p) are output from the radix-4 second section in natural (ternary/binary) digit order, {00,01,10,11,20,21,30,31}. The (ternary/binary) digit-reversed order, {00,10,01,11,02,12,03,13}, may be obtained simply by reversing the order of the digits in the natural (ternary/binary) digit order, {00,01,10,11,20,21,30,31}.
Similarly, the 8-point DIT FFT for N=r.sub.1 r.sub.2, where r.sub.1 =4 and r.sub.2 =2, becomes: ##EQU29## which is given by a first section of 2 radix-4 butterflies followed by a second section of 4 radix-2 butterflies, as shown in FIG. 6. Expanded, the 8-point DIT FFT, for N=r.sub.1 r.sub.2, where r.sub.1 =4 and r.sub.2 =2, is given by:
X(00)=x.sub.2 (00)=x.sub.1 (00)+x.sub.1 (10) =[x(00)+x(10)+x(20)+x(30)]+[x(01)+x(11)+x(21)+x(31)],
X(01)=x.sub.2 (01)=x.sub.1 (01)+(W.sub.8).sup.1 x.sub.1 (11) =[x(00)-jx(10)-x(20)+jx(30)]+(W.sub.8).sup.1 [x(01)-jx(11)-x(21)+jx(31)],
X(02)=x.sub.2 (02)=x.sub.1 (02)+(W.sub.8).sup.2 x.sub.1 (12) =[x(00)-x(10)+x(20)-x(30)]+(W.sub.8).sup.2 [x(01)-x(11)+x(21)-x(31)],
X(03)=x.sub.2 (03)=x.sub.1 (03)+(W.sub.8).sup.3 x.sub.1 (13) =[x(00)+jx(10)-x(20)-jx(30)]+(W.sub.8).sup.3 [x(01)+jx(11)-x(21)-jx(31)],
X(10)=x.sub.2 (10)=x.sub.1 (00)-x.sub.1 (10) =[x(00)+x(10)+x(20)+x(30)]-[x(01)+x(11)+x(21)+x(31)],
X(11)=x.sub.2 (11)=x.sub.1 (01)-(W.sub.8).sup.1 x.sub.1 (11) =[x(00)-jx(10)-x(20)+jx(30)]-(W.sub.8).sup.1 [x(01)-jx(11)-x(21)+jx(31)],
X(12)=x.sub.2 (12)=x.sub.1 (02)-(W.sub.8).sup.2 x.sub.1 (12) =[x(00)-x(10)+x(20)-x(30)]-(W.sub.8).sup.2 [x(01)-x(11)+x(21)-x(31)],
X(13)=x.sub.2 (13)=x.sub.1 (03)-(W.sub.8).sup.3 x.sub.1 (13) =[x(00)+jx(10)-x(20)-jx(30)]-(W.sub.8).sup.3 [x(01)+jx(11)-x(21)-jx(31)], where the arguments of the time-domain samples x(n) are presented in ternary/binary form, n.sub.1 n.sub.0, with n=2n.sub.1 +n.sub.0, for n.sub.1 =0, 1, 2, 3, and n.sub.0 =0, 1, and the frequency-domain samples X(p) are presented in binary/ternary form, p.sub.1 p.sub.0, with p=4p.sub.1 +p.sub.0, for p.sub.1 =0, 1, and p.sub.0 =0, 1, 2, 3. As shown in FIG. 6, the time-domain samples x(n) are input to the radix-4 first section in (binary/ternary) digit-reversed order, {00,10,20,30,01,11,21,31}, while the frequency-domain samples X(p) are output from the radix-2 second section in natural (binary/ternary) digit order, {00,01,02,03,10,11,12,13}. The (binary/ternary) digit-reversed order, {00,10,20,30,01,11,21,31}, may be obtained simply by reversing the order of the digits in the natural (binary/ternary) digit order, {00,01,02,03,10,11,12,13}.
The foregoing examples suffice to demonstrate that the machine-implemented cascaded DIT FFT (and IFFT) may be readily generalized and extended to larger values for N, the number of sample points, as is well known in the art. Such large-N DIT FFTs and IFFTs are useful in digital signal processing (DSP) applications.
For example, a transform-based audio coding algorithm, such as Dolby.RTM. Digital, is designed to provide data-rate reduction for wide-band signals while maintaining the high quality of the original content, as described in L. Fielder et al. "AC-2 and AC-3: Low-Complexity Transform-Based Audio Coding," Collected Papers on Digital Audio Bit-Rate Reduction, Audio Engineering Society, New York, N.Y., pp. 54-72. Dolby.RTM. Digital is a high-quality audio compression format widely used in feature films and also with Digital Versatile Disks (DVDs), also known as Digital Video Disks. Many PC's offer DVD drives, and providing a Dolby.RTM. Digital decoder implemented in software, performing an IFFT as part of the implementation, allows decoding of Dolby.RTM. Digital to become a baseline capability on the PC.
Such a transform-based audio coding algorithm may be implemented on a PC based, for example, on an Intel Pentium.RTM. processor. It is important to maintain high audio quality, and Dolby.RTM. Laboratories has developed a stringent test suite to ensure that a certified decoder indeed provides high quality. In addition, trained listeners evaluate prospective decoders using both test and program material. Only after a decoder has passed both the analytical and subjective tests is the decoder certified.
An Intel Pentium.RTM. processor with Intel's MMX.TM. technology, for example, has MMX.TM. instructions that operate on 8, 16, and 32 bits. The human ear has an overall dynamic range of 120 dB and an instantaneous dynamic range of 85 dB, as described in S. Harris, "Understanding, enhancing, and measuring PC-audio quality," EDN, Vol. 42, Number 8, Apr. 10, 1997, p. 173. The dynamic range of a binary value is 6.0206 dB per bit. Eight bits (about 48 dB of dynamic range, approximately the dynamic range of AM radio) is not sufficient for high-quality audio. Sixteen bits (about 96 dB of dynamic range, the dynamic range of Compact Disks) is usually considered high-quality audio.
Due to quantization noise produced by rounding errors during the intermediate calculations, however, the accuracy at the output of a Dolby.RTM. Digital decoder, for example, is significantly less than the accuracy of the intermediate values (assuming a uniform accuracy throughout the transform-based audio coding algorithm). This is typical with DSP algorithms For example, using 16 bits of accuracy uniformly through a Dolby.RTM. Digital decoder is not sufficient to pass the Dolby.RTM. Laboratories test suite. The quantization noise produced using 16 bits of accuracy uniformly through a Dolby.RTM. Digital decoder, for example, can be both noticeable and tonal, making such an implementation unsatisfactory for high-quality audio. Tonal noise tends to be more objectionable than wideband or "white" noise.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.

Reducing peak spectral error in inverse Fast Fourier Transform using MMX.TM. technology


A measurement arrangement for measuring process and structure parameters of a fiber composite material along a measuring path includes a fiber material, a matrix material which surrounds the fiber material at least in regions, and an electrical sensor element that includes at least two signal transmission lines twisted together and aligned along the measuring path in and/or at the fiber material such that the signal transmission lines are surrounded at least in portions by the matrix material, wherein the electrical sensor element is configured to measure the process and structure parameters on the basis of the behavior of electromagnetic signals that are fed into the signal transmission lines.

Even though it is employable in various applications, the disclosure herein and its underlying problem are explained in more detail in relation to fiber composite components for aircraft. However, the described methods and apparatus can likewise be used for general fiber composite components for very different applications.
Fiber composite materials, such as carbon fiber reinforced plastic (CFRP), for example, are increasingly used in modern aircraft construction. In order to guarantee a quality standard within the scope of the production of components made of such materials, it is advantageous to monitor process and structure parameters of the production method as accurately as possible, without this impacting the quality of the components and/or without this driving up the production costs. By way of example, important process and structure parameters comprise a degree of curing or a cross-linkage of a matrix material, a current position of the flow front of a liquefied matrix material, potential damage to a semi-finished product and/or a pre-mold, etc. A method for determining such properties in spatially resolved fashion, e.g., along a line-shaped sensor, in particular, is the electrical time-domain reflectometry (TDR); see, e.g., the article Buchmann et al., "Investigation of Electrical Time Domain Reflectometry for infusion and cure monitoring in combination with electrically conductive fibers and tooling materials," Composites Part B: Engineering, 94:389-398, 2016 (referred to below as Buchmann).
In general, TDR is a method for analyzing run lengths and reflection characteristics of electromagnetic signals on transmission lines. TDR is based on the physical principle according to which an electromagnetic signal, e.g., a voltage pulse, is partly or completely reflected if the latter comes across regions in a medium that have different physical properties, for example changes in impedance along a transmission line. Specifically, one or more transmission lines in the aforementioned TDR method serve as line-shaped sensors at and/or in a fiber composite semi-finished product for the purposes of monitoring an infusion or injection process of a matrix material. Here, the introduced matrix material changes the dielectric properties along the transmission line, which in turn become noticeable as changes in the impedance of the line. If a voltage pulse is now fed into the line, it is possible to determine and analyze the reflection behavior and, building thereon, it is possible to obtain spatially resolved and/or time-resolved deductions about the infusion process.
However, electrically conductive fiber and/or tool materials may lead to relevant loss effects, which in turn can impair the measurement. The use of shielded sensors is sometimes proposed for compensation purposes; by way of example, use can be made of a braided shield about a transmission line, see, for example, documents EP 3 035 041 A1, EP 3 035 042 A1 and EP 3 035 043 A1. However, this increases the cross section of the sensors, leading to restrictions in respect of possible applications since, inter alia, the sensors require a greater installation volume.

Measurement arrangement for measuring process and structure parameters of a fiber composite material along a measuring path