A plurality of electron-emitting devices carried on a device substrate are arranged vis-a-vis an acceleration electrode carried on a face plate. The device substrate and the face plate, together with side walls disposed therebetween, constitute an envelope the inner space of which is kept under vacuum. A number of spacers are also disposed between the device substrate and the face plate within the inner space. The electric potential V.sub.a applied to the acceleration electrode, the distance l between the electron-emitting devices and the corresponding respective spacers, and the distance d between the electron-emitting devices and the acceleration electrode satisfy the relationship, V.sub.a .multidot.l.sup.2 /d.sup.2 >.vertline..DELTA.V.sub.sat .vertline./(2.multidot..alpha..multidot..beta.), where .alpha. and .beta. are constants determined from several factors and .DELTA.V.sub.sat is the potential deviation of the spacer surface under charged conditions from that under uncharged conditions.

1. Field of the Invention
This invention relates to an image-forming apparatus such as a display apparatus using electron beams and, more particularly, it relates to an image-forming apparatus comprising spacers arranged within the envelope of the apparatus to internally support the envelope against the atmospheric pressure.
2. Related Background Art
There have been known two types of electron-emitting devices, which are the thermionic electron source and the cold cathode electron source. Cold cathode electron sources refer to the field emission type (hereinafter referred to as the FE type), the metal/insulation layer/metal type (hereinafter referred to as the MIM type) and the surface conduction electron-emitting type (hereinafter referred to as the SCE type).
Examples of SCE type device include the one proposed in M. I. Elinson, Radio Eng. Electron Pys., 10 (1965).
An SCE type device is realized by utilizing the phenomenon that electrons are emitted out of a thin film with a small area formed on a substrate when an electric current is forced to flow in parallel with the film surface. While Elinson proposes the use of SnO.sub.2 thin film for a device of this type, the use of Au thin film is proposed in G. Dittmer: "Thin Solid Films", 9, 317 (1972) whereas the use of In.sub.2 O.sub.3 /SnO.sub.2 thin film and that of carbon thin film are also discussed respectively in M. Hartwell and C. G. Fonstad: "IEEE Trans. ED Conf.", 519 (1975) and H. Araki et al.: "Vacuum", Vol. 26, No. 1, p. 22 (1983).
FIG. 30 of the accompanying drawings schematically illustrates a typical surface conduction electron-emitting device proposed by M. Hartwell. In FIG. 30, reference numeral 3001 denotes an insulating substrate. Reference numeral 3004 denotes an electron-emitting region-forming thin film, which is a thin metal oxide film prepared by sputtering, using an H-shaped pattern, in which an electron-emitting region 3005 is produced when it is subjected to an electrically energizing process referred to as "energization forming" as will be described hereinafter. In FIG. 30, a pair of device electrodes are separated by a length L of 0.5 to 1[mm] and have a width W of 1.0[mm].
Conventionally, an electron emitting region 3005 is produced in a surface conduction electron-emitting device by subjecting the electron-emitting region-forming thin film 3004 of the device to an electrically energizing process, which is referred to as energization forming. In the energization forming process, a constant DC voltage or a slowly rising DC voltage that rises typically at a very slow rate of 1 V/min. is applied to given opposite ends of the electron-emitting region-forming thin film 3004 to partly destroy, deform or transform the film and produce an electron-emitting region 3005 which is electrically highly resistive. Thus, the electron-emitting region 3005 is part of the electron-emitting region-forming thin film 3004 that typically contains a fissure or fissures therein so that electrons may be emitted from the fissure and its vicinity. The electron-emitting region-forming thin film 3004 including the electron-emitting region produced by energization forming will be referred to as the electron-emitting region-containing thin film. Note that, once subjected to an energization forming process, a surface conduction electron-emitting device comes to emit electrons from its electron emitting region 3005 whenever an appropriate voltage is applied to the electron-emitting region-containing thin film 3004 to make an electric current run through the device.
Examples of FE type device include those proposed by W. P. Dyke & W. W. Dolan, "Field emission", Advance in Electron Physics, 8, 89 (1956) and C. A. Spindt, "PHYSICAL Properties of thin-film field emission cathodes with molybdenum cones", J. Appl. Phys., 47, 5284 (1976). FIG. 31 of the accompanying drawings shows a schematic cross sectional view of a device proposed by C. A. Spindt et al., which is a typical FE type device. Referring to FIG. 31, it comprises a substrate 3010, an emitter wiring layer 3011 made of a conductive material, a conical emitter 3012, an insulation layer 3013 and a gate electrode 3014. The device emits electrons from the tip of the conical emitter 3012 as an appropriate voltage is applied to the conical emitter 3012 and the gate electrode 3014.
While the FE type device illustrated and described above has a multilayer structure, the emitter and the gate electrode may alternatively be arranged on the substrate substantially in parallel with the plane of the substrate.
Examples of MIM type device are disclosed in papers including C. A. Mead, "The tunnel-emission amplifier", J. Appl. Phys., 32, 646 (1961). FIG. 32 of the accompanying drawings shows a schematic cross sectional view of a typical MIM type device. Referring to FIG. 32, it comprises a substrate 3020, a lower metal electrode 3021, a thin insulation layer 3022 having a thickness of about 10[nm] and an upper metal electrode having a thickness of about 30[nm].
The MIM type device emits electrons from the surface of the upper electrode 3023 as an appropriate voltage is applied between the upper electrode 3023 and the lower electrode 3021.
Contrary to a thermionic device, a cold cathode device is adapted to emit electrons at low temperature and hence does not need a heater. Consequently, the former has a simplified structure if compared with the latter and, therefore, it is possible to prepare very small cold cathode devices, which are relatively free from problems such as a thermally molten substrate if they are densely arranged on a substrate.
Additionally, while the responsiveness of a thermionic device is defined by that of the heater used for it, a cold cathode device is free from such a problem and hence a highly responsive cold cathode device can be realized without difficulty.
In view of the above listed advantages and other advantages, efforts have been paid to develop electron beam apparatus, image-forming apparatus in particularly, comprising cold cathode devices.
Particularly, the surface conduction electron-emitting device provides a remarkable advantage that a large number of devices can be arranged over a large area because of the structural simplicity they have. Studies have been made to exploit this advantage for various applications. Applications of surface conduction electron-emitting devices include electrically charged beam sources and display apparatus.
Applications of surface conduction electron-emitting devices arranged in numbers include electron sources realized by arranging surface conduction electron-emitting devices in parallel rows and connecting them through the opposite ends of each of the devices by means of wires to form a matrix of devices (see, inter alia, Japanese Patent Application Laid-Open No. 1-031332 filed by the applicant of the present patent application). While flat panel type display apparatus utilizing liquid crystal have been replacing CRTs in the field of image-forming apparatus including display apparatus, they have a drawback that they are not of the emission type and hence required to be provided with a back light. Therefore, there has been a strong demand for emission type display apparatus. Emission type display apparatus capable of displaying high quality images include image-forming apparatus having a large display screen that can be realized with relative ease by combining an electron source comprising a large number of surface conduction electron-emitting devices and fluorescent bodies adapted to emit visible light by electrons emitted from the devices (see, inter alia, U.S. Pat. No. 5,066,883 issued to the applicant of the present patent application).
An electron beam appratus that can be used for image-forming apparatus as described above typically comprises an envelope for maintaining vacuum within the apparatus, an electron source arranged in the envelope, targets to be irradiated with respective electron beams emitted from the electron source and an acceleration electrode for accelerating the electron beams directed to the respective targets. In addition to the above components, it may additionally comprise spacers for supporting the envelope from the inside against the atmospheric pressure.
The arrangement of such spacers within the envelope is indispensable for an image-forming apparatus of the above described type particularly when a large display screen is used and/or when the apparatus has to be made very thin.
When spacers are used within the envelope, there arise problems including (1) that electric discharges occur when electron beams are accelerated by a high voltage and (2) that electron beams are deviated from the intended respective routes to miss the respective targets (a phenomenon referred to as "beam deviation" hereinafter). The latter problem can result in a displaced and/or deformed light emitting spot produced on the target of each fluorescent body of the image-forming apparatus that can significantly degrade the quality of the display image. Particularly, when the image-forming member of the image-forming apparatus comprises fluorescent bodies for red, green and blue for displaying color images, the problem (2) as identified above can entail a deteriorated brightness and a phenomenon of color breakup. These problems are particularly remarkable at locations close to the spacers arranged between the electron source and the image-forming member presumably because electron beams and charged particles generated within the envelope under the effect of emitted electron beams can collide, at least partly, with the surfaces of the spacers to produce secondary electrons which by turn electrically charge the surfaces of the spacers and disturb the electric fields on and near the spacers so that consequently the electron beams in the envelope are deviated from there intended respective routes.
In an attempt to bypass this problem, there have been proposed a number of techniques for removing the electric charge of the spacers by using an electrically conductive material for the spacers.
For example, Japanese Patent Application Laid-Open No. 57-118355 describes a method of coating the surfaces of the plate-shaped spacers having holes at locations respectively corresponding to the thermionic cathodes with tin oxide in order to remove electrons adhering to the wall surfaces of the holes in an image-forming apparatus comprising thermionic devices. It also described that the electric conductivity of the spacers is such that an electric current between 10 pA and 0.001 .mu.A flows when a voltage of 10 V is applied between the electrodes arranged oppositely with the spacers interposed therebetween.
PCT/US94/00602 described the use of electrically conductive spacers having a secondary electron emitting efficiency close to 1 in order to minimize fluctuations in the potential of the spacers. Such electrically conductive spacers have a sheet resistance of 10.sup.9 to 10.sup.14 .OMEGA./.quadrature. and a film thickness of 0.05 to 20 .mu.m and are made of chromium oxide, copper oxide, carbon or the like. The inventor presumes that fluctuations in the potential of the spacers are caused by emitted secondary electrons and defines the potential deviation .DELTA.V at a position separated from distance x on a spacer held in contact with the substrate of the image-forming apparatus by formula (1) below; EQU .DELTA.V=.rho..sub.s .multidot.[x.multidot.(x-d)/2].multidot.j.multidot.(1-.delta.)(1),
where d is the height of the spacer (distance between the device substrate and the acceleration electrode), .rho..sub.s is the surface resistance of the spacer, j is the current density colliding with the spacer surface and .delta. is the secondary electron emission efficiency of the surface of the spacer.
Japanese Patent Application Laid-Open No. 57-118355 as cited above uses plate-shaped spacers having holes and defines the electric conductivity of the spacers in terms of the electric current (between 10 .mu.A and 0.001 .mu.A) that flows through the spacer when a voltage is applied between the oppositely disposed electrodes with the spacers interposed therebetween. Thus, the current flowing region of each of the spacers varies depending on its profile and the above definition cannot be applied to spacers having a profile other than the one described there.
As for the technique of PCT/US94/00602, if the presumption that secondary electrons are mainly responsible to the electric charge of the spacers is correct, the potential of the spacer surface varies from the ground to the acceleration voltage that is typically several kV depending on the position on the surface and hence it is practically impossible to select a material and a set of conditions with which the secondary electron emission efficiency is substantially equal to 1 over such a wide energy range. In other words, a potential deviation inevitably appears at least on part of the spacer surface. Additionally, while the electric charge of the spacers can be reduced by using a highly conductive material for the spacers, the use of such a material is not practically feasible in terms of power consumption rate of the image-forming apparatus.
As a result, positional deviations and electric discharges occur when the electron-emitting devices are on for driving such an image-forming apparatus.

Image-forming apparatus and method of driving the same


A diffuser sheet which compensates for chromatic dispersion generated in a hologram light guide plate, and an illumination apparatus employing the diffuser sheet are provided. The diffuser sheet includes a plate type light-transmissive substrate and a light diffusion layer disposed on a light emission surface of the light-emission substrate. A light-incident surface of the light-transmissive substrate has declined surfaces and flat surfaces which are alternatively and repeatedly formed thereon. The declined surfaces are declined at a predetermined angle.

1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a diffuser sheet and an illumination apparatus, and more particularly, to a diffuser sheet that can compensate for chromatic dispersion generated in a hologram light guide plate, and an illumination apparatus for a display employing the diffuser sheet.
2. Description of the Related Art
Non-emissive displays, such as liquid crystal displays (LCDs), typically require a separate illumination apparatus, such as a backlight unit. FIG. 1 shows an exemplary conventional illumination apparatus for a display provided with a light guide plate using a hologram. Referring to FIG. 1, the conventional illumination apparatus 10 includes a light guide plate 12 having a fine hologram pattern 13 formed on an upper surface thereof, a light source 11 disposed adjacent to one sidewall of the light guide plate 12, and a diffuser sheet 15 which uniformly diffuses the light emitted from the upper surface of the light guide plate 12.
The light source 11 of the illumination apparatus may be, for example, a white light emitting diode (LED). White light emitted from the light source 11 is incident obliquely through one sidewall surface of the light guide plate 12. The light guide plate 12 is made of poly methyl meth Acrylate (PMMA) which is a plastic material with a superior transmittance. The white light within the light guide plate is totally internally reflected by the upper and lower surfaces of the light guide plate. As shown in FIG. 1, since the light guide plate 12 has a hologram pattern 13 formed on the upper surface thereof, some of the light incident on the upper surface of the light guide plate 12 is diffracted by the hologram pattern 13 and is emitted through the upper surface of the light guide plate 12. For example, the hologram pattern 13 may have a sinusoidal form with a predetermined period. The light emitted through the upper surface of the light guide plate 12 is uniformly diffused through the diffuser sheet 15 to illuminate a non-emissive display, such as an LCD.
Refractive indices and transmittance vary depending on the wavelength of the light. Thus, when white light is emitted through the upper surface of the light guide plate 12 and through the hologram pattern 13, chromatic dispersion takes place. FIGS. 2A through 2C illustrate this chromatic dispersion and show measurement results of brightness distributions for red(R), green (G) and blue (B) light emitted from the hologram pattern 13. In the illustrated examples, the hologram pattern 13 has a period of 420 nm and a thickness of 250 nm. Also, the blue light has a wavelength of 600 nm, the green light has a wavelength of 555 nm and the blue light has a wavelength of 450 nm. FIG. 2A illustrates a brightness distribution of red light. As shown in FIG. 2A, most of the red light is distributed near incident center. FIG. 2B illustrates a brightness distribution of green light. As shown in FIG. 2A, the green light is distributed near the incident center, but the brightest portion slightly deviates from the incident center. FIG. 2C illustrates a brightness distribution of blue light. As shown in FIG. 2C, the brightest portion greatly deviates from the incident center. As shown, the brightness distribution is different according to the color of light.
As shown in FIG. 3, chromatic dispersion can be clearly seen from the brightness distributions of red (R), green (G) and blue (B) light. The angles shown in FIG. 3 are value measured with respect to the normal line perpendicular to the light guide plate 12. As shown in FIG. 3, the blue light is distributed centering on the angle of 22°, which is called a peak angle. In other words, the blue light is emitted from the light guide plate 12 at a peak angle of 22°. The green light is emitted from the light guide plate 12 at a peak angle of 8°. The red light is emitted from the light guide plate 12 at a peak angle of 4°.
Thus, the angle of the light emitted from the light guide plate 12 is different depending on wavelength causing the problem that the white light emitted from the light source 11 is divided into respective colors by the light guide plate 12. In the conventional art, the diffuser sheet 15 serves to uniformly diffuse the incident light, but it is limited in its ability to completely reproduce the divided color lights to white light. Therefore, display performance of the display is lowered.

Diffuser sheet for compensating for chromatic dispersion and illumination apparatus employing the same


A portable electronic device. The portable electronic device includes a body, a cover, a button, a movable pin and a battery. The button is movably disposed on the body to move between a first position and a second position. The movable pin is disposed in the body. The battery is disposed on the body. When the button is in the first position, the cover is separated from the button. When the button moves from the first position to the second position, the movable pin pushes the battery, allowing the battery to be separated from the body.

1. Field of the Invention
The invention relates to a portable electronic device, and in particular, to a button mechanism for a portable electronic device.
2. Description of the Related Art
FIG. 1 and FIG. 2 depict a conventional mobile phone, comprising a body 2, a battery 3, a battery cover 4 and a button 5. The battery cover 4 has a opening 41. When the battery 3 is disposed in the body 2, the battery cover 4 covers the battery 3 and the button 5 engages with the battery cover 4 through the opening 41, preventing separation of the battery 3 from the body 2.
To remove the battery 3 from the body 2, the button 5 is pressed to release the battery cover 4 from the body 2. The battery 3 can then be removed from the mobile phone 1 by hand. Users with larger fingers or short finger nails, however, may experience difficulty in removing the battery 3 form the mobile phone 1.


A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

The present invention relates to a semiconductor integrated circuit device and a semiconductor memory for such uses as a memory device with logic function constituting a buffer storage device (buffer memory device) for computers.
In the related art, there exists a prior art memory device with logic function having a plurality of RAM (random access memory) macrocells and gate arrays. There are digital processors such as a computer having a buffer storage that comprises the above memory device with logic function.
The memory device with logic function having multiple RAM macrocells and gate arrays is illustratively discussed in such publications as U.S. patent application Ser. No. 07/198,311, filed and assigned to Hitachi, Ltd. by Isomura et al. on May 25, 1988. The gate arrays of this prior art memory device comprise ECL (emitter coupled logic) circuits based on bipolar transistors for high-speed operation. The inventors found that this construction hampered efforts to reduce the power dissipation of the memory device and to enlarge the scale of circuit integration thereof. This has resulted in long delay times required for signal transmission and hence relatively low speeds of operation. The inventors' investigation further revealed that constraints on the circuit integration of the memory device with logic function kept the sharing of functions between the memory device and other devices from being optimized. The resultant long critical path of computers has imposed limitations on the cycle time thereof.


A connector for circuit board has a guide case provided on the base wall thereof, which has openings for exposing terminal conductors of a circuit board inserted therein and guide ribs for leading insertion of spring terminal of another connector and of which the edge portion is tapered. Thereby the terminal connecting portion of the circuit board may be assembled without a shift in position and it is possible to keep a secure electrical connection of the two connectors.

1. Field of the Invention
The present invention relates to connectors for circuit board and, more particularly, relates to a connector for circuit board capable of assembling the terminal connecting portion of a circuit board in a stable manner without a shift in position thereof and also capable of being securely connected to spring terminal with which it is to be mated.
2. Description of the Prior Art
A conventional connector for circuit board is formed into a box-like shape and a slit-like opening is provided on the base wall thereof, so that a flat plate-like terminal connecting portion continued from a circuit board is inserted into such an opening. Provided in parallel on the terminal connecting portion are a plurality of conductor terminals which are continued from a circuit conductor printed on the surface of the circuit board. A slit-like notch corresponding to the flat plate-like terminal connecting portion is provided on a connector with which the circuit board connector is to be mated and, in the notch portion, a spring terminal having resilient contacting pieces which are to contact the conductor terminals of the terminal connecting portion. By fitting these two connectors together, the terminal connecting portion on the circuit board side and the spring terminal are brought into contact with each other to be electrically connected. Such connector for circuit board has been disclosed in Japanese Utility Model Laid-Open Publication No.JP-U-1-161583(1989).
In the conventional circuit board connector, however, the terminal connecting portion tends to be easily shifted vertically and/or horizontally in position within the connector housing, causing such disadvantages as the occurrence of a bad contact with the spring terminal to be mated therewith or, in worst case, a short circuit. Further, there is also another problem that a large inserting force is necessary when the edge at the distal end of the terminal connecting portion and the spring terminal are abutted against each other, whereby the conductor terminals on the terminal connecting portion may be turned over.


A backlight system providing enhanced uniform brightness and a liquid crystal display (LCD) employing the same are provided. The backlight system includes: a light guide panel which forms a surface light source by guiding light; and a plurality of light emitting units arranged on at least one side of the light guide panel in the form of an array, wherein when the light emitting units in the array are divided into a first region, a second region and a third region and at least one of light emitting units is included in an edge of the first region and an edge of the third region, a quantity of current applied to the first region and the third region is controlled to be larger than a quantity of current applied to the second region in order to control the light guide panel to provide uniform brightness.

1. Field of the Invention
The present invention relates to a backlight system and a liquid crystal display employing the same and, more particularly, to a backlight system providing enhanced uniform brightness, and a liquid crystal display (LCD) employing the same.
2. Description of the Related Art
A liquid crystal display (LCD), which is a type of flat panel display, is a light receiving type display that is not self-luminescent but forms an image using incident light from an outside light source. A backlight system is disposed at a rear of the LCD to irradiate light toward a liquid crystal panel.
According to the arrangement of the light source, the backlight systems are classified into either direct light type backlight systems in which light emitted from a plurality of light sources disposed right below a liquid crystal panel is irradiated toward the liquid crystal panel, or edge light type backlight systems in which light emitted from a light source disposed on a sidewall of a light guide panel is transmitted to a liquid crystal panel.
The edge light type backlight systems using a cold cathode fluorescence lamp (CCFL) have generally been used up to now, and one of the edge light type backlight systems is shown in FIG. 1.
FIG. 1 is a perspective view of a conventional edge light type backlight system.
Referring to FIG. 1, the backlight system includes a light guide panel 1, a plurality of fluorescent lamps 3 arranged at edges of the light guide panel 1, and a plurality of reflectors 5 surrounding each of the fluorescent lamps 3 to reflect light emitted from the fluorescent lamp 3 to the light guide panel 1. The light guide panel 1 propagates the incident light emitted from the fluorescent lamps 3 to form a surface light source. A geometric pattern is printed or formed on a bottom surface of the light guide panel 1 to uniformly diffuse the incident light through the light guide panel 1 for illuminating a liquid crystal panel with uniform brightness.
Since the fluorescent lamps 3 are used in the conventional backlight system, color reproducibility is seriously degraded. In order to overcome such a drawback of the conventional backlight system, there are various studies in progress to develop a backlight system using a light emitting diode (LED) instead of the fluorescence lamp.
However, in the conventional backlight system, dark portions appear in the backlight systems using the fluorescent lamps 3 or the LED because a smaller quantity of light is emitted from the four corners of the backlight system. These dark portions cause the entire uniformity of the backlight system to be degraded.

Backlight system and liquid crystal display employing the same


A system and method provides communications to processes, handles transmissions of communications received from processes, and allows other manipulations of transmissions upon request by processes without an operating system call.

Computers may receive communications from, and/or provide communications to, other devices. For example, computers that operate as servers for the World Wide Web may receive communications from other computer systems requesting web pages. Other computers may operate as file or storage servers for a local-area, or metropolitan, network, receiving requests for files from a computer system, retrieving the file from a storage subsystem and providing the file to the requesting computer system.
Computer systems process each communication via one or more processes running on the computer system. On many computer systems, several processes capable of processing communications may be running at any given time. Some of these simultaneously operating processes may handle certain types of communications, while other processes on the same computer system handle other types of communications.
When a conventional computer system receives a new communication of a certain type, it provides it to a process that handles that type of communications. Subsequent communications received from the same source for the same destination may be provided to the process via operating system calls made by the process to allow the same process to handle messages that are part of the same thread of communications.
However, there are several problems with this approach. One problem is that new communication threads are assigned to a process that can handle communications of that type whether the process is in the best position to receive a new communication thread. Because the process does not control the manner in which communications are assigned, one process may receive a new communication at a time that it should not, even though another process may be in a better position to receive the new communication. Additionally, the use of operating system calls to receive communications is processor intensive, which can limit the overall capacity of the computer system to process communications and perform other operations.
Some communications may be processed by one process, potentially altering the communication as a result. The resulting communications may then be processed by another process. The interprocess transfer of these communications may also require operating system calls, adding additional load to the processors on which the processes run, further limiting the capacity of the system to process communications and perform other operations. Furthermore, the process that first handles the communications may be required to identify the process that should subsequently process the communication, which adds complexity to the process, complexity that must be duplicated in each such process.
Some processes can erroneously overwrite communications provided by other processes. It can be desirable to restrict access by one process to communications written by another process.
It can be desirable to implement any solution to the problems described above in a cost-effective manner. The costs of communication interfaces such as gigabit Ethernet interfaces can be enormously sensitive to volume. Thus, it is preferable to incorporate high volume communication interfaces into any solution, than to use more expensive custom communication interfaces, which would reduce the desirability of any solution incorporating a custom communication interface.
What is needed is a system and method that can route new communications to processes under control of each process, provides communications to processes without the use of operating system calls, allows communications to be easily reassigned to other processes, restricts access by one process to communications written by another process, and uses conventional communication interfaces.

This patent is subject to a terminal disclaimer.

System and method for providing communications to processes


A method for manufacturing a silicon carbide single crystal includes the steps of: preparing a seed crystal with a screw dislocation generation region; and growing the single crystal on a growth surface of the seed crystal. The generation region occupies equal to or smaller than 50% of the growth surface, which has an offset angle equal to or smaller than 60 degrees. The screw dislocation density in the single crystal generated from the generation region is higher than that in the other region. The single crystal includes a flat C-surface facet disposed on a growing surface of the single crystal. The C-surface facet overlaps at least one of parts of the growing surface provided by projecting the generation region in a direction perpendicular to the growth surface and in a direction parallel to a <0001> axis, respectively.

A semiconductor device formed from silicon carbide (i.e., SiC) single crystal is expected as a power device to replace a silicon device. To form a SiC power device having high performance, it is required to reduce leak current in the SiC substrate. The leak current in the SiC substrate is caused by a defect such as a screw dislocation in the SiC single crystal.
A conventional method for forming the SiC single crystal is a C-surface crystal growth method. In the C-surface crystal growth method, a SiC seed crystal has a growth surface, which is the C-surface or a surface having an offset angle in a range of 10 degrees (i.e., 10°) from the C-surface. The offset angle of the growth surface is determined from the C-surface. The growth surface of the SiC seed crystal exposes outside so that the SiC single crystal is grown on the growth surface by a sublimation recrystallization method or the like. However, when the C-surface is used for the growth surface of the seed crystal, and the SiC single crystal is grown along with a <0001> direction, many micro pipe defects or screw dislocations are generated along with the <0001> direction in the SiC single crystal.
To reduce the defect in the SiC single crystal, a method for manufacturing the SiC single crystal is disclosed in Japanese Patent Application Publication No. H5-262599. In this method, the seed crystal has the growth surface, which tilts by 60° to 120° from the C-surface. The SiC single crystal is grown along with an A-surface orientation direction so that the method provides an A-surface crystal growth method. In the SiC single crystal grown by the A-surface crystal growth method, a small amount of micro pipe defects and screw dislocations are generated. However, as shown in FIG. 17, the SiC single crystal 9 formed by the above method includes many stacking faults 95 parallel to the C-surface. The stacking faults 95 have high density in the SiC single crystal 9. Therefore, electric resistance of the SiC single crystal 9 perpendicular to the C-surface (i.e., parallel to a C-axis of a <0001> direction) becomes larger. Specifically, when electrons cross the stacking fault 95, the resistance becomes larger. Thus, the SiC single crystal 9 having high-density stacking fault 95 can not be used for the SiC power device.
To remove the stacking fault, in a process for manufacturing the SiC single crystal, it is required to use a seed crystal having a growth surface of the C-surface. Specifically, the A-surface grown seed crystal having no screw dislocation substantially is prepared firstly. Then, the A-surface grown seed crystal is cut so that the seed crystal having the growth surface of the C-surface is obtained. Here, the C-surface is exposed outside. Next, this seed crystal is used for the C-surface crystal growth so that the SiC single crystal having no screw dislocation nor stacking fault is obtained. However, in this method, as shown in FIG. 18, since the A-surface grown seed crystal 8 having the C-surface growth surface 81 has no screw dislocation substantially, there is no source for supplying steps when the C-surface crystal growth is performed using the A-surface grown seed crystal 8. The source supplies steps so that the A-surface grown seed crystal 8 is transcribed to a growing crystal 80. Specifically, the source supplies steps so that polymorphism of the A-surface grown seed crystal 8 is transferred to the growing crystal 80. However, there is no source so that the growing crystal 80 includes a heterogeneous polymorphous crystal 87 or a different surface orientation crystal 88, partially. If the heterogeneous polymorphous crystal 87 or the different surface orientation crystal 88 is grown, the SiC single crystal 80 includes many screw dislocation 89 at random. The SiC single crystal 80 having the different surface orientation crystal 88 or the screw dislocation 89 is not used for the device because of leak current.
In view of the above problem, another method for forming the SIC single crystal is disclosed in Japanese Patent Application Publication No. H8-59389. The method is such that the growth surface of the seed crystal includes an artificial convexity or concavity as a singular point. The singular point generates a screw dislocation as the source for supplying steps. Thus, the SiC single crystal is grown. However, the simple convexity or concavity has no screw component so that they may not work as the source for supplying steps for transferring the polymorphism of the A-surface grown seed crystal to the growing crystal. Specifically, when the SiC single crystal is grown by a certain amount, the convexity and concavity changes to the screw dislocation so that the convexity and concavity works as the source for supplying steps. However, in the beginning of the crystal growth, the heterogeneous polymorphous crystal 87 may be generated so that the heterogeneous polymorphous crystal 87 expands whole growing crystal 80. Then, the SiC single crystal may have inferior quality.

Method for manufacturing silicon carbide single crystal from dislocation control seed crystal


A musical jewelry apparatus is disclosed. The musical jewelry apparatus comprises a front member, a rear member, a hinge member, a musical and a power source. The hinge member is partially disposed on a portion of the front member and a portion of the rear member; and is adapted to hingedly connect the front member and the rear member. The musical member, which is powered by the power source, is disposed in either the front member or the rear member.

It has often been said regarding gifts that "it's the thought that counts." By this statement, it is meant that the more personal a gift is, the more rewarding it is, as such a gift acts as a constant reminder of the gift-giver.
One such gift is a photograph, or other item of a personal nature, that can be conveyed to a recipient. Such gifts, because they are not an attempt to buy affection—in addition to its obvious personal nature, immediately ascend to sentimental or heirloom status.
Currently, there are a number of devices which provide for donors to give loved recipients personal mementos. A locket is disclosed in U.S. Pat. No. 5,586,452, issued on 24 Dec. 1996 to Schmid. Schmid discloses an item of jewelry and, more specifically, lockets. See Schmid, Abstract.
However, although the invention disclosed in Schmid does allow for the placement of a photograph, other heirloom or keepsake memento therein, the invention does not provide for the ability to include a movement-activated musical device installed therein. Given the fact that music touches a sense different from the sight of the memento, coupling music to a personalized jewelry device, such as that disclosed in Schmid, can add even more sentimental value to such a gift.
Thus, the need exists for a musical jewelry apparatus that overcomes the above-stated disadvantages. Further, it should be noted that any description of any reference in this, or any other, Section is not intended to constitute an admission that the reference described herein is "Prior Art" with respect to the Present Invention, unless explicitly designated as such.


A process for manufacturing an exhaust system for an internal combustion engine includes the steps: a) providing at least one exhaust gas-carrying component (12, 18) for the exhaust system (10); b) applying a basic material layer (24, 26) to at least one area of a surface of at least one of the exhaust gas-carrying components (12, 16) in a high-temperature application process; and c) applying a catalytically active material layer (28, 30) to the basic material layer (24, 26) in a low-temperature application process.

To reduce the pollutant emission of internal combustion engines, especially diesel internal combustion engines, which are used as drive units in vehicles, it is known that a reactant, generally a urea/water solution, is added to the exhaust gas stream, and that the percentage of nitrogen oxides in the exhaust gas is lowered in a selective catalytic reduction (SCR). The ammonia needed for carrying out a selective catalytic reduction in an SCR catalytic converter is provided by adding the reactant. Due to the contact with the hot exhaust gas or with the surface of exhaust gas-carrying components of an exhaust system, at least part of the water contained in the reactant injected into the exhaust gas stream, i.e., for example, a urea/water solution, evaporates first in the reactant Ammonia and isocyanic acid are formed from the urea during the thermal decomposition Ammonia is formed from the isocyanic acid and the previously evaporated water in a hydrolytic reaction carried out on a hydrolysis catalyst. Such a hydrolysis catalytic converter may be provided, for example, by coating a substrate formed generally from a ceramic material in a partial area of an SCR catalytic converter with a material that is catalytically active for hydrolysis, for example, titanium dioxide (TiO2).

Process for manufacturing an exhaust system and exhaust system

Eberspächer Exhaust Technology GmbH & Co. KG


A method is described which includes receiving a point cloud having a plurality of data points each representing a 3D location in a 3D space, the point cloud being obtained using a detection and ranging (DAR) sensor. For each data point, associating the data point with a 3D volume containing the 3D location of the data point, the 3D volume being defined using a 3D lattice that partitions the 3D space based on spherical coordinates. For at least one 3D volume, the data points are sorted within the 3D volume based on at least one dimension of the 3D lattice; and the sorted data points are stored as a set of ordered data points. The method also includes performing feature extraction on the set of ordered data points to generate a set of ordered feature vectors and providing the set of ordered feature vectors to perform a machine learning inference task.

Autonomous vehicles generally include different types of sensors that may be used to sense an environment the vehicle operates in, to capture information about the environment, and produce sensor data representative of the captured information. One type of sensor that is becoming prevalent on autonomous vehicles is a LiDAR sensor. A LiDAR sensor captures three-dimensional (3D) information about objects in the environment the vehicle operates in, and produces sets of data points in space that are representative of the objects. Each set of data points in three-dimensional (3D) space is generally referred to in the art as a point cloud. However, the set of data points in a point cloud are typically unordered data points, with irregular formation and reflecting a non-uniform sampling density in 3D space.
Autonomous vehicles generally include a machine learning-based system that can perform a feature extraction procedure to extract features from point clouds obtained by LiDAR sensors which are used by downstream inference procedure(s) of the machine-learning based system to perform pattern recognition tasks, such as 3D object recognition and semantic segmentation. However, conventional feature extraction procedures may not account for the ray-scanning or ranging procedure that a LiDAR sensor uses to produce point clouds. In particular, point clouds received from a LiDAR sensor are not natural 3D surfaces that have been sampled as if the LiDAR sensor can be placed looking from every direction. Rather, the LiDAR sensor is typically affixed to the vehicle and scans only a limited field of view producing as many data points as it can scan from such direction. Furthermore, the point cloud produced by the LiDAR sensor from each scan conforms to a spatial ordering that is typically custom to the LiDAR sensor and not properly accounted for in downstream inference procedure(s) used to perform downstream pattern recognition tasks.

System and method for ordered representation and feature extraction for point clouds obtained by detection and ranging sensor


An embodiment of the present invention is directed to a riving knife assembly for a dual bevel table saw, comprising: a first armature configured for coupling with a beveling member; a second armature adjustably and rotatably coupled with the first armature; a first mounting member coupled with the second armature; a first riving bracket coupled with the second armature and configured for adjustably coupling with a bearing retaining nut of a dual arbor assembly; a second riving bracket coupled with the first mounting member and configured for adjustably coupling with the inside of a first bore of a first height bracket; a quick release handle disposed upon the first mounting member; an eccentric shaft coupled with the quick release handle; and a riving knife configured with an engaging assembly for engaging with a locking pin or a guard assembly or a kickback finger system.

Saw blades beveling is an advantageous capability to be included with power saw assemblies, such as table saw assemblies which include a saw assembly comprising a saw blade, extending through a planar surface (table), coupled with a motor by a mounting assembly. Beveling assemblies, provide the operator of a table saw with the ability to adjust the angular presentation of the saw blade relative to the planar surface of the table. Unfortunately, many beveling assemblies included with table saw assemblies, and the like, are limited in the capabilities they may provide to the operator.
A typical limitation of many beveling assemblies is the enablement of beveling in a single tilt orientation. For instance, a beveling assembly may provide the operator with the ability to adjust the angular presentation of the saw blade relative to the planar surface of the table in a right tilt orientation or a left tilt orientation. Other beveling assemblies have limited beveling capabilities resulting from unwanted contact between the component features of the saw assembly or beveling assembly and other structural impediments of the table saw assembly, such as the unwanted contact between the motor, which drives the saw blade of the table saw assembly, and the underside of the planar surface of the table or structural support features of the table saw assembly. Additionally, unwanted contact may result from contact between the mounting assembly of the saw blade and the table. For instance, when the blade is beveled, the mounting assembly may contact the underside of the table because of the mounting assembly's proximate location to the table.
Unfortunately, attempts to resolve these problems have resulted in assemblies which may require a user to accept limited capabilities. For example, unwanted contact is decreased, but only by limiting the depth of cut capabilities of the saw blade of the table saw assembly. Therefore, it would be desirable to provide a table saw assembly which enables the saw blade with bi-directional beveling capabilities (right and left tilt orientation) without reducing the capabilities of the saw blade due to factors, such as unwanted structural impedance.
Additional limitations may be a result of design limitations. For instance, the assembly, which couples the saw blade with the motor of the table saw, typically, statically fixes the position of the motor relative to the saw blade. Such a situation may result in decreased performance of the saw assembly during beveling due to changes in tolerances resulting from changes in the positions of these features due to beveling.
Therefore, it would be desirable to provide a beveling assembly which increased the ability of the component features of the table saw assembly to remain near optimal tolerances during the beveling of the saw blade. Another design limitation is the typical arbor assembly is enabled as a single axle, which may be limited to coupling with the saw blade to impart angular momentum on a single end of the axle. This may result in the beveling assembly enabled with the single axle arbor assembly limiting its capabilities to a single tilt orientation, as described previously. Still further, this may result in increased time spent attempting to properly re-align the single axle arbor assembly when transitioning between beveling in a first tilt orientation to beveling in a second tilt orientation, such as from right to left. This may significantly decrease productivity accomplished through use of the table saw employing such a single axle arbor assembly. Further, due to such drastic re-positioning required by the single axle arbor assembly there may be an increase in tolerance misalignments resulting in increases in non-production time spent by the power tool. Therefore, it would be desirable to provide an arbor assembly which decreased time spent re-aligning the arbor assembly and increased the ease of employing the saw blade on the arbor assembly for beveling in both tilt orientations.
Further, it is common practice in the field of power tools, particularly arbor assemblies for table saws, to take steps to "true" the assembly after it has been assembled. This truing may assist in increasing the productivity and life span of the power tool by assisting in reducing wear to the component features of the power tool. Steps, such as machining the flange may true the arbor assembly and may decrease the amount of "wobble" introduced into the saw blade during operation of the table saw. Unfortunately, after the truing of the arbor assembly is complete the parts of the arbor assembly, such as the bearing for example, may wear out due to use, requiring replacement. It is known to allow for the operator to disassemble the arbor assembly in order to replace the bearing. This often requires removal of the flange in order to access the bearing. It is typically the case that when the operator re-assembles the arbor assembly the flange and possibly other component features are no longer in the trued position, as originally provided by the manufacturer. Thus, "wobble" may be introduced into the spinning blade of the table saw. Therefore, it would be further desirable to provide an arbor assembly which assists the operator in maintaining its trued position even after replacement of component features of the arbor assembly.
Therefore, it would be further desirable to provide an arbor assembly which assists the operator in maintaining its trued position even after replacement of component features of the arbor assembly.

Riving knife assembly for a dual bevel table saw


An electro-magnetic storage device and method are disclosed. In one embodiment, a memory device includes a first magnetic material to attract a movable structure (e.g., a ferromagnetic material) when a first voltage is applied between the first magnetic material and the movable structure, and a second magnetic material to release the movable structure when a second voltage is applied between the second magnetic material and the movable structure. The movable arm may create a closed circuit when the second voltage is applied between the second magnetic material and the movable structure. There may be a vacuum-gap between the movable structure and at least one of the first magnetic material and/or the second magnetic material. The memory device may be stackable on other memory devices having similar properties, and/or electrically coupled with other memory devices having similar properties in a memory array.

A storage device is a hardware device that holds data. There are two types of the storage device, a non-volatile storage device and a volatile storage device. The non-volatile storage device (e.g., a hard drive) may hold data even when power is turned off. The volatile storage device (e.g., a static random access memory (a SRAM), a dynamic random access memory (a DRAM), etc.) may lose data when power is turned off.
A transistor (e.g., a simple electronic switch, either preventing or allowing current to flow through) is a solid state semiconductor device which may be used in the storage device. A storage cell (e.g., a physical unit of the storage device that may store exactly one bit) may be created from a number of transistors arranged in such a way as to allow data to be at least temporarily stored. For example, each bit in the SRAM may be stored on four transistors that form two cross-coupled inverters. The storage cell in the SRAM may have two stable states which may used to denote 0 and 1. Two additional access transistors may serve to control access to the storage cell during read and write operations. Thus, it may take six transistors (e.g., CMOS SRAM) to store one memory bit in the storage device.
As application programs demand more storage space and as computing power becomes faster, there is an increasing demand for denser and quicker versions of the storage device. In addition, widespread acceptance and adoption of portable computing devices (e.g., laptop computers, personal digital assistants, etc.) have created a demand for versions of the storage device that use less power.
In order to meet this demand, engineers have reduced physical size of the storage cell to be able to achieve desired properties of lower power, faster speed, and/or higher density of the storage device. In recent years, it has become increasingly difficult to achieve higher densities in the storage device because of leakage (e.g., thinner gate oxides of the transistor may create larger interference between a source and a drain), geometry constraints (e.g., patterning smaller features of the storage cell on a wafer is increasingly difficult and may be expensive), mask step complexity (e.g., it may take nineteen or more mask steps to make each storage cell), and photolithography challenges (e.g., shorter wavelengths are difficult to achieve and may be needed to define smaller features of the storage cell).

Electro-magnetic storage device and method


A hearing aid system (500) with active noise cancelling and a method for operating such a hearing aid system.

Generally a hearing aid system according to the invention is understood as meaning any device which provides an output signal that can be perceived as an acoustic signal by a user or contributes to providing such an output signal, and which has means which are customized to compensate for an individual hearing loss of the user or contribute to compensating for the hearing loss of the user. They are, in particular, hearing aids which can be worn on the body or by the ear, in particular on or in the ear, and which can be fully or partially implanted. However, some devices whose main aim is not to compensate for a hearing loss, may also be regarded as hearing aid systems, for example consumer electronic devices (televisions, hi-fi systems, mobile phones, MP3 players etc.) provided they have, however, measures for compensating for an individual hearing loss.
Within the present context a traditional hearing aid can be understood as a small, battery-powered, microelectronic device designed to be worn behind or in the human ear by a hearing-impaired user. Prior to use, the hearing aid is adjusted by a hearing aid fitter according to a prescription. The prescription is based on a hearing test, resulting in a so-called audiogram, of the performance of the hearing-impaired user's unaided hearing. The prescription is developed to reach a setting where the hearing aid will alleviate a hearing loss by amplifying sound at frequencies in those parts of the audible frequency range where the user suffers a hearing deficit. A hearing aid comprises one or more microphones, a battery, a microelectronic circuit comprising a signal processor, and an acoustic output transducer. The signal processor is preferably a digital signal processor. The hearing aid is enclosed in a casing suitable for fitting behind or in a human ear.
Within the present context a hearing aid system may comprise a single hearing aid (a so called monaural hearing aid system) or comprise two hearing aids, one for each ear of the hearing aid user (a so called binaural hearing aid system). Furthermore, the hearing aid system may comprise an external device, such as a smart phone having software applications adapted to interact with other devices of the hearing aid system. Thus within the present context the term "hearing aid system device" may denote a hearing aid or an external device.
The mechanical design has developed into a number of general categories. As the name suggests, Behind-The-Ear (BTE) hearing aids are worn behind the ear. To be more precise, an electronics unit comprising a housing containing the major electronics parts thereof is worn behind the ear. An earpiece for emitting sound to the hearing aid user is worn in the ear, e.g. in the concha or the ear canal. In a traditional BTE hearing aid, a sound tube is used to convey sound from the output transducer, which in hearing aid terminology is normally referred to as the receiver, located in the housing of the electronics unit and to the ear canal. In some modern types of hearing aids, a conducting member comprising electrical conductors conveys an electric signal from the housing and to a receiver placed in the earpiece in the ear. Such hearing aids are commonly referred to as Receiver-In-The-Ear (RITE) hearing aids. In a specific type of RITE hearing aids the receiver is placed inside the ear canal. This category is sometimes referred to as Receiver-In-Canal (RIC) hearing aids.
In-The-Ear (ITE) hearing aids are designed for arrangement in the ear, normally in the funnel-shaped outer part of the ear canal. In a specific type of ITE hearing aids the hearing aid is placed substantially inside the ear canal. This category is sometimes referred to as Completely-In-Canal (CIC) hearing aids. This type of hearing aid requires an especially compact design in order to allow it to be arranged in the ear canal, while accommodating the components necessary for operation of the hearing aid.
Hearing loss of a hearing impaired person is quite often frequency-dependent. This means that the hearing loss of the person varies depending on the frequency. Therefore, when compensating for hearing losses, it can be advantageous to utilize frequency-dependent amplification. Hearing aids therefore often provide to split an input sound signal received by an input transducer of the hearing aid, into various frequency intervals, also called frequency bands, which are independently processed. In this way, it is possible to adjust the input sound signal of each frequency band individually to account for the hearing loss in respective frequency bands.
In order to achieve optimum sound quality the hearing aid system needs to be adapted to suppress noise. This is, however, not always possible to do effectively by adjusting the frequency dependent gain provided by the hearing aid system.
External sound arrives at the eardrum of the hearing aid user through two main paths, directly through the vent and through the main signal processing of the in-situ hearing aid, which is adapted to alleviate an individual hearing deficit by applying a frequency dependent gain. The direct and the amplified sounds adds in an absolute manor, meaning that the total sound at the eardrum depends not only on the relative amplitudes of the two sound sources but also on the relative phase. E.g. if two harmonic signals are equal in amplitude but opposite in phase, the two signals will cancel each other completely. This is called destructive interference. On the other hand, if they are equal in phase they will interfere constructively and give a total signal which is 6 dB louder than each signal.
It has therefore been suggested to cancel out noise by adapting the hearing aid system to provide a cancelling signal that has the same magnitude and opposite phase of the noise and therefore cancels the noise in the ear canal through destructive interference.
U.S. Pat. No. 8,229,127B2 discloses a hearing aid system with an Active Noise Cancelling (ANC) unit that may be operated as an analogue feed-forward ANC systems, analogue feed-back ANC systems, digital feed-forward ANC systems, or digital feed-back ANC systems. However, the analogue systems appear to be preferred because they have a low delay which is an advantage for achieving a well-functioning ANC system. In an embodiment a digital feedback cancellation unit is adapted to adjust the filter characteristics of the ANC filter.
U.S. Pat. No. 8,867,766B2 discloses a method of operating a hearing aid system, wherein an audible signal is provided by processing in first and second controlled signal processing paths and by transmission through an uncontrolled signal transmission path and wherein the processing in the second controlled signal processing path is adapted to provide a signal that compensate the signal provided by the uncontrolled signal transmission path and wherein only one sample rate is used in the second controlled path as opposed to several sample rates in the first controlled path, whereby the delay in the second controlled path may be kept low because the delay introduced as a consequence of changing a sample rate is avoided.
U.S. Pat. No. 9,319,814B2 discloses a hearing aid system with active occlusion control that is based on an ear canal microphone sensing a sound pressure in the residual ear canal space between the hearing aid system in the ear part and ear drum of the user and wherein the ear canal microphone signal is provided to an occlusion control compensator filter arranged in a feedback loop between the ear canal microphone and the hearing aid system receiver.
It is therefore a feature of the present invention to provide a method of operating a hearing aid system that provides improved active noise cancelling.
It is another feature of the present invention to provide a hearing aid system adapted to provide such a method of operating a hearing aid system.

Method of operating a hearing aid system and a hearing aid system


Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.

Technological innovations in semiconductor fabrication technologies are driving market demands for semiconductor memory devices providing higher storage capacity, higher speed, higher integration density, and lower power consumption. The downscaling of semiconductor memory devices to submicron design rules and beyond, however, coupled with increased storage capacity poses technological challenges with respect to maintaining performance and reliability. For instance, as memory capacity increases and the pitch between adjacent patterns are made narrower, the layout of the memory arrays and peripheral devices become more problematic, especially with regard to memory core layout. When designing memory circuits, it is desirable to minimize the length and loading of word lines. Indeed, if word lines are too long/narrow and/or have too many memory cells connected to each word line (i.e., a large load), word line enable driver circuits will consume more power to drive the word lines, and the speed of driving word lines can decrease. To mitigate the impact on device performance with line rule downscaling and increased memory density, various memory circuit architectures have been employed including, for example, hierarchical memory bank architectures and hierarchical word line driver structures with sub word line architectures.
For instance, FIGS. 1A˜1C are schematic illustrations of a semiconductor memory device having a conventional hierarchical memory bank architectures and hierarchical word line driver framework. FIG. 1A illustrates a semiconductor integrated circuit memory chip (10) having a memory cell array with a memory capacity of 1 Gb, which is divided into a plurality of memory banks, Bank A, B, C and D (or more generally, Bank-i) (e.g., 4 memory banks of 256 Mb). Each memory bank Bank-i can be independently operated with associated peripheral circuits including column decoders (11) and row decoders (12), as well as other I/O circuitry for outputting/inputting data via peripheral data I/O pads (13). Each memory bank Bank-i comprises decoder circuits and core circuits that are arranged in "unit blocks," as depicted in FIG. 1B. In particular, FIG. 1B schematically illustrates a conventional layout of each memory bank (Bank_i) in FIG. 1A, wherein each memory bank (Bank-i) comprises a plurality of 256 unit blocks BL(i) including 16 unit blocks along an x-direction (bitline/column direction) and 16 unit blocks along a y-direction (word line/row direction).
FIG. 1C schematically illustrates a conventional layout pattern for each unit block BL-i in the memory bank Bank-i for a memory device utilizing a hierarchical sub-word line driver scheme. Each unit block BL-i includes a cell array (20), sub-word line driver (SWD) arrays (21), bit line sense amplifier (BSLA) arrays (23) and conjunction circuit blocks including PXiD driver blocks (22) and LA driver (LADRV) blocks (24). The unit block pattern BL-i depicted in FIG. 1C is repeated in both x and y directions over the memory bank Bank-i such that each memory cell array block (20) is disposed between two BLSA blocks (23) in the x (column) direction of bit lines and such that each memory cell array block (20) is disposed between two sub-word line drivers (21) in the y (word line) direction. In one conventional hierarchical word line framework, each block sense amplifier (23) is shared by two memory cell array blocks (20) to the left and right of the BLSA (23) and each sub-word line driver (21) is shared by two memory cell array blocks (20) above and below the SWD block (21) using an interleaved layout framework, as is known in the art.
By way of specific example, FIG. 2 is a schematic illustration of one conventional framework of a unit block BL-i such as depicted in FIG. 1C in a semiconductor device having a hierarchical divided word line scheme. As shown in FIG. 2, a memory cell array (20) includes an array of memory cells MC (each having a cell transistor and cell capacitor in a DRAM memory) located at the intersection of a bit line BL or BLB and a sub-word line WL. The bit lines are connected to the memory cells MC and to corresponding sense amplifiers SA in BLSA blocks (23) using an open bitline architecture, for example, as is known in the art. The BSLA blocks (23) are driven by control signals generated by drivers in respective LADRV blocks (24). In the hierarchical divided word line scheme, a word line is divided into a plurality of sub-word lines WL that are driven using corresponding sub-word line driver blocks (21) located above and below the memory cell array (20).
FIGS. 3, 4 and 5 are schematic diagrams to illustrate a conventional I/O architecture of for a multi-bank semiconductor memory device. In general, FIG. 3 is a schematic block diagram illustrating I/O circuitry for data read/write data paths for a conventional DRAM core comprising a plurality of banks. FIG. 4 schematically illustrates a layout arrangement of local and global data I/O bus lines providing a core data path from the memory cells and global bus lines for a multi-bank semiconductor device. FIG. 5 schematically illustrates a layout of the I/O circuitry and bus lines within the memory cell array regions and in peripheral regions of the memory arrays. FIGS. 3, 4, and 5 illustrate a typical device having an open bit line structure where bit lines BL and inverted bit lines BLB extend to both sides of a sense amplifier (23i) and where memory cells (MC) are formed at intersection region of the bit lines and word lines. Bit line pairs BL, BLB are respectively placed at both sides of each sense amplifier (23i) in a given array.
As shown in FIG. 3, each sense amplifier (23i) is shared by two memory cell arrays and is connected to local data lines LIO and /LIO by pass gates M1, M2 which are gated by the column select line CSL. As explained below, each column select line (CSL) may control multiple sense amplifiers per sense amplifier array, where each sense amplifier serves one data line pair. An LGIO multiplexer circuit (30) connects local data I/O line pairs LIO, /LIO to global data I/O line pairs GIO, /GIO. A GIO multiplexer circuit (31) connects the global data I/O line pars GIO, /GIO to data I/O line pairs DIO, /DIO at the input to a data read path and at the output of a data write path. The data read path includes IO sense amplifiers (32), a data bus multiplexer (33) and data output buffer (34) to output data to the appropriate output pads 13 upon memory read access operations. The data write path receives data input via the pads (13) at a data input buffer (35), a multiplexer circuit (36) and a data driver (37) to drive respective DIO line pairs.
To read out one or a plurality of data from the memory cells of the semiconductor memory device, the data stored in the cells are amplified in the bitline sense amplifier (23i). The data amplified in the bitline sense amplifier (23i) are transferred to the local data I/O lines LIO and /LIO) via a column selection line (CSL) switch, amplified in an LIO sense amplifier connected to the LIO bus, and then transferred to the global I/O buss. Data read from a selected memory block is transmitted to data line pairs DIO, /DIO via the GIO multiplexer (31). Data line sense amplifiers (32) sense data transferred via the data lines DIO and /DIO. The data line multiplexer (33) selects from among the output signals of the data line sense amplifiers (32), and transmits the selected output data signals to pads (13) via the data output buffer (34).
FIG. 4 schematically illustrates a layout structure of data lines from a memory cell to global I/O lines. As shown in FIG. 4, the semiconductor memory device includes alternating odd and even numbered memory cell blocks (101, 102, 103) with array of sense amplifiers interposed between the arrays. The LIO bus lines include two pairs (110) and (111) local I/O lines LIO, LIOB that extends over the sense amplifiers (i.e., parallel to the word lines) between the arrays and service the bit line sense amplifiers located within an array. The global I/O lines extend parallel to the bit lines over the full length of the memory array. The LIO bus lines may be formed from a first metallization level whereas the GIO bus lines are formed using a second metallization level. In the exemplary embodiment of FIG. 4, each CSL (column select line) is connected to the column switch circuit for 2 sense amplifiers on each side of the cell arrays and one CSL signal output form a column decoder (13) will activate the two pairs of sense amplifiers on each side of the cell arrays. This allows for DDR (dual data rate) memory access operations where 4 sets of LIO data can be transferred to the GIO lines for each CSL activation.
FIG. 5A illustrates an exemplary layout of the I/O circuitry and bus lines. As shown, the GIO bus lines extends over the entire memory bank towards a peripheral regions between the column decoders (130) of adjacent memory banks. The peripheral regions includes the GIO multiplexer circuit (31), the I/O sense amplifier circuit (32) and the DB multiplexer circuitry. Moreover, data I/O bus lines DIOB extend over substantially the entire length of the peripheral region between the top and bottom side of the memory banks and then extend across the top regions of the memory banks towards DOUT buffers and the DQ pads disposed at the peripheral edge regions of the semiconductor memory chip. Due to long lengths, repeater circuit (40) may be included along the DOIB bus lines. The repeaters (40) operate to buffer and transmit data on the DOIB lines between data pad and the DB multiplexer circuit (33) and thereby reduces the load and decreases the delay of the data signals of the DOIB lines.
When current sensing is used on the data lines, the transmission distances from the memory blocks to the data line sense amplifier vary. Accordingly, current from a memory block close to the data line sense amplifier travels a shorter length of the data lines and experiences less resistance on the data lines between the memory block and the data lines sense amplifier. Current from a memory block far away from the data line sense amplifier experiences more resistance on the data lines between that memory block and the data lines sense amplifier. Accordingly, the data line sense amplifier often has different sensing efficiency for different memory blocks. For instance, as shown in FIG. 5B, memory access operation to the upper left side of the memory bank (e.g., BANK A) must travel a long path along the GIO lines toward the column decoder (13) for the bank, and then up and down the FDIO and DOIB bus lines in the peripheral regions and then back towards the output pads over the top side of the memory bank A from between the column decoders (130). This can lead to differences in access times for read operations, which is particularly undesirable for a memory device such as a synchronous DRAM (SDRAM) where timing of data signals is critical. The problem becomes more significant for larger capacity memories because the relative differences in transmission lengths typically increase with an increase in the memory capacity and the integration density. Accordingly, a need exists for a semiconductor memory device capable of keeping the sensing efficiency of a data line sense amplifier uniform.

Semiconductor memory devices having optimized memory block organization and data line routing for reducing chip size and increasing speed


The present invention is produced by a composite with an Eu (II) compound nanoparticle and a metal nanoparticle. Such production generates quantum size effects of the Eu (II) compound nanoparticle, while the surface plasmon of the metal nanoparticle can be used. Thus, the magnetooptical property can be improved. In addition, a thin film may be produced by a composite with an Eu (II) compound nanoparticle and a metal nanoparticle.

Conventionally, high-speed communication with large capacity has been achieved by attaching a micro-optical isolator to a semiconductor laser. As a material for the micro-optical isolator corresponding to optical communication wavebands (1.3 μm, 1.55 μm), a Bi-substituted garnet is known (for example, see Patent Document 1). In Patent Document 1, composite film is produced by containing nanoparticles of Au, Al, Ag or the like within Bi-substituted garnet thin film, thus electric polarization induced by the metal nanoparticles is increased by surface plasmon resonance of the metal nanoparticles, and thereby magnetooptic effects of the Bi-substituted garnet are increased.
Meanwhile, in relation to the Eu (II) compound (Europium chalcogenide) represented by EuO, since Eu (II) having 7 unpaired f electrons shows intense light absorption and light emission resulting from f-d transition as well as ferromagnetic property, the compound has received attention for its magnetooptical property and is expected to be available as an optical isolator material. Among the properties, particularly the Faraday effect that a polarization plane is rotated by applying a magnetic field has been the focus of attention (for example, see Patent Documents 2 and 3). Patent Documents 2 and 3 suggest that nanocrystals of EuO express magnetooptical properties by quantum size effects at room temperature.

Composite thin film and composite nanocrystals containing europium (II) compound and metal

National University Corporation Hokkaido University