The present invention is a sorter for products conveyed successively and continuously. The sorter components include a main screw rotated continuously by a drive shaft to arrange in order and convey products to be sorted. The main screw has helical grooves for engagement with the products and an annular groove portion for stopping therein each of the to-be-sorted products. The annular groove portion is positioned between helical grooves of the main screw. A rotatable sub-screw with helical grooves is located near the main screw at the annular groove portion for engagement with the products to be sorted. The sorter further includes a delivery means disposed at the annular groove to deliver the products from the main screw to the sub-screw and an interlocking mechanism rotating off the drive shaft which synchronizes the delivery means with the sub-screw. This sorter is a high speed, reliable system for sorting products undamaged.

In an automated manufacturing equipment for mass-producing products, the quality of the products is checked to distinguish between non-defective products and defective products, thereby preventing defective products from being distributed to a commodity distribution channel. In particular, with recent mass production of medical supplies and electronic components, there has been a demand not only for the improvement in performance of inspection devices for inspection of those products but also for higher accuracy and higher efficiency of sorters for sorting the products after inspection. Defective medical products affect the human life and this is a serious problem, and defective electronic components if incorporated in an electronic device prevents the electronic device to exhibit its performance to a satisfactory extent. Therefore, it has come to be required that the sorter is capable of sorting mass-produced products efficiently and with strict correctness and reliability to completely prevent inclusion of defective products among non-defective products.
Heretofore, as methods for sorting products after inspection into non-defective products and defective products, there have been known such a method using star wheels as shown in FIG. 9 and such a method using a pendulum as shown in FIG. 10.
In the former method using star wheels, as shown in FIG. 9, there are used a product conveying star wheel 3 which rotates while receiving products 1 in recesses 3a formed in its outer periphery, the products 1 being fed through a product inlet guide 2, and a product sorting star wheel 4 which is disposed adjacent the star wheel 3 and which is rotated so that recesses 4a formed in the outer periphery thereof come into alignment with the recesses 3a of the star wheel 3. Further, the recesses 4a of the product sorting star wheel 4 are contiguous to slits 4b for communication with a vacuum passage 5. When a defective product passes the star wheel 4, a negative pressure is generated in the vacuum passage 5 to attract the defective product to the star wheel 4 from the star wheel 3, whereby the defective product is discharged through a defective product discharge guide 6. On the other hand, in the case of a non-defective product, a negative pressure is not generated in the vacuum passage 5, so that the product 1 is conveyed as it is by the star wheel 3 and is sent out through a product outlet guide 6a.
On the other hand, in the latter method using a pendulum, there is used a pendulum 7 which is reciprocated pivotally about a pivot center O. The pendulum 7 is formed with first and second bifurcated passages 7a and 7b centered at the pivot center O. A pair of first and second discharge passages 9a and 9b is formed in a discharge guide 9. The discharge passages 9a and 9b each come into communication with either of the passage 7a or 7b in accordance with a swing motion of the pendulum 7. The pendulum 7 is allowed to swing according to whether each product 1 fed through a feed guide 8 is non-defective or defective, whereby the product 1 is introduced selectively into one of the first and second passages 7a and 7b and is then discharged through the first discharge passage 9a or the second discharge passage 9b.
However, in the conventional sorter using star wheels shown in FIG. 9, since the sorting of products 1 is performed by suction using a negative pressure, there exists an unstable factor relating to the generation and control of a required negative pressure, thus leading to the problem that the sorting operation is less reliable. moreover, the recesses 3a and 4a formed respectively in the outer periphery of the product conveying star-wheel 3 and in the outer periphery of the product sorting star wheel 4 are for receiving and sending out products 1, but since both of the recesses 3a and 4a are spaced a large distance at a certain pitch, it has been likely that at the time of sending out the products 1 through the defective product discharge guide 6 and the product outlet guide 6a and arranging them in order, the products 1 will suddenly approach each other into collision and that the resulting great impact on the products will cause damage to the products.
In the conventional method using a pendulum, which is shown in FIG. 10, since the pendulum 7 swings repeatedly with products 1 contained in its first and second passages 7a and 7b, the products 1 on the pendulum 7 may repeat mutual collision due to the action of repeated centrifugal forces. Also in this point there has been a fear of damage to the products 1. Besides, in the case where the number of products 1 contained in the first and second passages 7a and 7b changes, there is a fear that unevenness may occur in the swing motion of the pendulum 7 due to a change in inertia force associated with the swing motion. Thus, it has been difficult to ensure the stability in high-speed operation.

Single drive, multi-screw sorter with pusher means


An apparatus and method for testing a dielectric layer. The apparatus includes a first conductive plate and a second conductive plate. The first conductive plate and the second conductive plate are in direct contact with a dielectric layer. Additionally, the apparatus includes a first conductive wire connected to the first conductive plate and biased to a first predetermined voltage, and a second conductive wire connected to the second conductive plate and a voltage detector. Moreover, the apparatus includes a fuse connected to the second conductive wire, and a third conductive wire connected to the fuse and a device capable of providing a second predetermined voltage and measuring a current.

The present invention is directed to integrated circuits. More particularly, the invention provides a method and apparatus for testing an oxide layer with fuse. Merely by way of example, the invention has been applied to testing a gate oxide layer. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or "ICs" have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device "geometry", has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as a given process, device layout, and/or system design often work down to only a certain feature size.
An example of such a limit is testing of a gate oxide layer. FIG. 1 is a simplified diagram showing conventional method and apparatus for testing gate oxide layer. The tested gate oxide layer is sandwiched between two conductive plates 110 and 112. The plate 110 is biased to a ground voltage level by a metal wire 120. The plate 112 is coupled to a source-measure unit (SMU) 130 via a metal wire 122. The source-measure unit 130 can provide a predetermined voltage and measure the resulting current by a probe card 132. During test, a predetermined voltage is provided to the conductive wire 122 by the source-measure unit 130. The resulting current that flows through the conductive wire 122 is measured by the source-measure unit 130. Based on the measured current, whether the gate oxide layer has broken down is determined. If the measured current becomes much higher, the gate oxide layer is determined to have broken down. If the gate oxide layer is determined to have not broken down, another voltage is provided to the conductive wire 122 for further testing. But this conventional method and apparatus for breakdown detection has limited reliability and sensitivity.
From the above, it is seen that an improved technique for testing oxide layer is desired.

Method and apparatus for testing gate oxide with fuse

Semiconductor Manufacturing International (Shanghai) Corporation


A generator assembly for an airbag module of a motor vehicle is provided. The generator assembly comprising a gas generator for inflating an airbag of an airbag module with gas, wherein the gas generator defines with its generator housing a lateral surface that extends between a first and a second frontal cover surface of the gas generator, and means for electrically insulating the gas generator with respect to adjacent parts. For electrical insulation of the gas generator a flexible material layer is provided that completely covers the lateral surface of the gas generator. A systematic, defined grounding of the gas generator via a grounding conductor is carried out which is connected to an electrical connection of the gas generator that is integrated into a connector area of the gas generator.

The invention relates to a generator assembly of an airbag module of a motor vehicle.
Such a generator assembly comprises a gas generator for inflating an airbag comprising an airbag covering of the airbag module with gas and means for electrically insulating the gas generator (comprising a metallic housing) with respect to adjacent (metallic) parts of the airbag module.
An airbag module for which the mentioned generator assembly can be used, serves for protection of occupants in case of a crash. For this, the gas generator of the airbag module is coupled to one or several crash and/or pre-crash sensors which upon a strong deceleration caused by a crash or rather upon an imminent crash detected by means of sensor data cause an ignition of the gas generator so that the latter discharges gas for inflating the airbag. The airbag that is initially provided in a folded or rather gathered state in the airbag module deploys upon inflation and forms a gas cushion in the inflated state that shall protect one or several occupants from a collision with the vehicle body.
In order to activate the gas generator in case of a crash detected by sensors provided therefor, the gas generator is usually electrically, i.e., via electrical conductors, connected to a control device that causes an ignition of the gas generator due to corresponding sensor signals.
In many applications one thereby seeks to electrically insulate the gas generator, i.e., particularly a metallic housing of the gas generator, with respect to adjacent (metallic) parts, so that a necessary grounding of the gas generator takes place exclusively systematically. Regarding insulating a gas generator with respect to surrounding parts it is known to form mounting parts and fastening elements that are in contact with the gas generator and particularly its (metallic) housing in an electrically insulating manner and to provide them for instance with molded plastic areas. This however causes an increased effort concerning production and necessitates the use of complicated mounting parts and fastening elements.

Generator assembly for an airbag module of a motor vehicle


The present invention relates to methods and systems for providing reliable power to a storage device, such as a network attached storage. In one embodiment, the storage device employs a redundant power backplane design using a DC-to-DC converter per drive in the backplane. Each drive is thus provided its own independent power interface to the power backplane. One embodiment may employ DC-to-DC converters having integrated N-channel MOSFETs to provide overcurrent and thermal protection. In addition, an embodiment may employ a staggered startup procedure to manage peak power draw.

Conventional multi-drive network attached storage (NAS) devices use an internal an advanced technology extended ("ATX") power supply and power backplane to interconnect and deliver power to its components. Typically, the power backplane distribute DC power, such as 5V and 12V power, from the power supply via power supply buses on the backplane. Unfortunately, these components can be susceptible to failure.
For example, ATX power supplies are subject to wear and tear due to power fluctuations, power surges, etc. Thus, ATX power supplies can be prone to failure. A failure in the ATX power supply may impact other sensitive components of the NAS device, such as the drives.
Power sequencing is one approach to reducing wear and tear on the power supply. Power sequencing is where the startup of individual drives of the NAS is staggered to reduce peak power draw and prevent overloading of the power supply. Typically, the individual drives of the NAS are connected to the power supply buses through switches, such as P-channel MOSFETs. Unfortunately, these switches in conventional backplanes are also known to be susceptible to failure and have poor performance, especially in isolating short circuit faults. Thus, even with the use of power sequencing, known NAS devices must use a higher rated ATX power supply than what would otherwise be necessary. This dramatically increases the cost of the NAS device and still does not address the underlying problems of conventional NAS devices and their backplanes.
As an alternative to power sequencing, some known NAS devices may employ fuses for protection. However, fuses still require an oversized power supply. Furthermore, fuses preclude the use of power sequencing.

Redundant power backplane for NAS storage device


The subject invention pertains to a method and apparatus for producing sensitivity maps with respect to medical imaging. The subject invention relates to a method for applying an inpainting model to correct images in parallel imaging. Some images, such as coil sensitivity maps and intensity correction maps, have no signal at some places and may have noise. Advantageously, the subject invention allows an accurate method to fill in holes in sensitivity maps, where holes can arise when, for example, the pixel intensity magnitudes for two images being used to create the sensitivity map are zero. A specific embodiment of the subject invention can accomplish de-noise, interpolation, and extrapolation simultaneously for these types of maps such that the local texture can be carefully protected.

Techniques for map correction in the parallel imaging field have been used, such as the polynomial fit procedure (Pruessmann K P W M, Scheidegger M B, Boesiger P. SENSE: Sensivity encoding for fast MRI. Magn Reson Med 1999; 42: 952-962), thin-plate splines (Miguel Angel Gonzalez Ballester Y M, Yoshimori Kassai, Yoshinori Hamamura, Hiroshi Sugimoto, Robust Estimation of Coil Sensitivities for RF Subencoding Acquisition Techniques. 2001. p 799), wavelets (F. H. Lin Y-JC, and J. W. Belliveau, L. L. Wald, Estimation of coil sensitivity map and correction of surface coil magnetic resonance images using wavelet decomposition. 2001; Brighton, UK), and Gaussian kernel smoothing (M. S. Cohen R M D, and M. M. Zeineh. Rapid and effective correction of RF inhomogeneity for high field magnetic resonance imaging. Hum Brain Mapp 2000; 10: 204-211). There are references that disclose inpainting techniques (G. Aubert L V. A variational method in image recovery. SIAM J Numer Anal 1997; 34(5): 1948-1979; Shen TFCaJ. Non-texture inpainting by curvature driven diffusions. J Visual Comm Image Rep 2001; 12(4): 436-449; Tony F Chan J S, Luminita Vese. Variational PDE models in image processing. Amer Math Soc Notice 2003; 50: 14-26; Tony F Chan J S. Mathematical model for local non-texture inpaintings. SIAM J Appl Math 2001; 62(3): 1019-1043; V. Caselles J-MM, and C. Sbert. An axiomatic approach to image interpolation. IEEE Trans Image Processing 1998; 7(3): 376-386). There are also references that teach sensitivity map correction (Pruessmann K P W M, Scheidegger M B, Boesiger P. SENSE: Sensitivity encoding for fast MRI. Magn Reson Med 1999; 42:952-962; Miguel Angel Gonzalez Ballester Y M, Yoshinori Kassai, Yoshinori Hamamura, Hiroshi Sugimoto. Robust Estimation of Coil Sensitivities for RF Subencoding Acquisition Techniques. 2001, p. 799; F.-H. Lin Y-JC, and J. W. Belliveau, L. L. Wald. Estimation of coil sensitivity map and correction of surface coil magnetic resonance images using wavelet decomposition. 2001; Brighton, UK.; M. S. Cohen RMD, and M. M. Zeineh. Rapid and effective correction of RF inhomogeneity for high field magnetic resonance imaging. Hum Brain Mapp 2000; 10:204-211, U.S. Published Application No. U.S. 2004/0000906 A1, King et al., published Jan. 1, 2004). However, these existing techniques for use in parallel imaging do not protect the local texture.
The existing methods referred to are based on the assumption that the map is sufficiently smooth (i.e., contains no sharp variations). However, the map that needs correction is typically piece-wise smooth. Hence, the map corrected by these methods is often over-smoothed and the local texture is often destroyed.
Image inpainting was originally an artistic phrase referring to an artist's restoration of a picture's missing pieces. Computer techniques could significantly reduce the time and effort required for fixing digital images, not only to fill in blank regions but also to correct for noise. Digital inpainting techniques (C. Ballester M B, V. Caselles, G. Sapiro, and J. Verdera. Filling-in by joint interpolation of vector fields and grey levels. IEEE Trans Image Process 2001; 10(8): 1200-1211; Tony F Chan J S, Luminita Vese. Variational PDE models in image processing. Amer Math Soc Notice 2003; 50:14-26; Tony F Chan J S. Mathematical model for local non-texture inpaintings. SIAM J Appl Math 2001; 62(3): 1019-1043; Shen TFCaJ. Non-texture inpainting by curvature driven diffusions. J Visual Comm Image Rep 2001; 12(4): 436-449; V. Caselles J-MM, and C. Sbert. An axiomatic approach to image interpolation. IEEE Trans Image Processing 1998; 7(3): 376-386) are finding broad applications such as, image restoration, dis-occlusion, perceptual image coding, zooming and image super-resolution, and error concealment in wireless image transmission. Due to its broad range of applications, various methods for inpainting have been developed, ranging from nonlinear filtering methods, wavelets and spectral methods, and statistical methods (especially for textures). The most recent approach to non-texture inpainting is based on the PDE method and the Calculus of Variations. According to Chan and Shen (Tony F Chan J S, Luminita Vese. Variational PDE models in image processing. Amer Math Soc Notice 2003; 50: 14-26) PDE based TV models and the Mumford-Shah model work very well for inpainting problems with a more local nature such as hole filling (holes being regions of low signal in magnetic resonance (MR) images). Hole filling is an important issue in the correction of MR sensitivity maps, which are generally derived from MR images.
In magnetic resonance imaging (MRI) systems, sensitivity maps are meant to contain the sensitivity information of radio frequency (RF) probe coils. Highly accurate knowledge of the spatial receiver sensitivity is required by both SMASH (Simultaneous Acquisition of Spatial Harmonics (Sodickson D. Spatial Encoding Using Multiple RF Coils: SMASH Imaging and Parallel MRI. I Y, editor: John Wiley & Sons Ltd; 2000.)) and SENSE (Sensitivity Encoding (Pruessmann K P W M, Scheidegger M B, Boesiger P. Coil sensitivity encoding for fast MRI. 1998; Sixth Scientific Meeting of ISMRM, Sydney, Australia. P. 579.; Pruessmann K P W M, Scheidegger M B, Boesiger P. SENSE: Sensitivity encoding for fast MRI. Magn Reson Med 1999; 42: 952-962.)). Sensitivity maps are also important to correcting the inhomogeneities of MRI surface coils. Accurate sensitivity information can only be obtained where signal is present. However, some data sets have large areas contributing little or no signal. Such dark regions (i.e. holes) are common, for example, in pulmonary MRI using Fresh Blood Imaging (FBI). In this case, sensitivity map interpolation techniques are often used to fix the holes. To deal with slightly varying tissue configurations and motion, extrapolation over a limited range can be utilized. Therefore, there is a need for technique that is capable of simultaneously interpolating and extrapolating. There are some existing techniques for this purpose, such as the polynomial fit procedure (Sodickson D. Spatial Encoding Using Multiple RF Coils: SMASH Imaging and Parallel MRI. I Y, editor: John Wiley & Sons Ltd; 2000.), thin-plate splines (Miguel Angel Gonzalez Ballester Y M, Yoshimori Kassai, Yoshinori Hamamura, Hiroshi Sugimoto, Robust Estimation of Coil Sensitivities for RF Subencoding Acquisition Techniques. 2001. p 799.), wavelets (F. H. Lin Y-JC, and J. W. Belliveau, L. L. Wald. Estimation of coil sensitivity map and correction of surface coil magnetic resonance images using wavelet decomposition. 2001; Brighton, U K.), and Gaussian kernel smoothing (M. S. Cohen RMD, and M. M. Zeineh. Rapid and effective correction of RF inhomogeneity for high field magnetic resonance imaging. Hum Brain Mapp 2000; 10: 204-2). These methods are based on the assumption that the sensitivity map is sufficiently smooth (i.e., containing no sharp variations). However, this assumption is not always true. If the sensitivity map is piecewise smooth, which is usually true for non-uniform loading, the existing methods are not sufficient. Accordingly, there is a need for an inpainting model that can apply a technique to handle interpolation and extrapolation for piecewise smooth maps simultaneously.

Method for applying an in-painting technique to correct images in parallel imaging


A color charge-coupled device is disclosed including plural light detectors corresponding to first to third colors and plural charge transmission regions on a semiconductor substrate; a pad on one side of the substrate excluding a portion where the light detectors and charge transmission regions are formed; a planarizing film on the substrate excluding the pad; microlenses on the planarizing film above the light detectors; and first to third color filter layers on each microlens excluding the edge portion.

The present invention relates to a color charge-coupled device, and more particularly, to a color charge-coupled device and a method of manufacturing the same, which is suited to improve sensitivity and to prevent color mixing.
FIGS. 1A to 1D are cross-sectional views for illustrating a method of manufacturing a conventional color charge-coupled device.
Referring to FIG. 1A, through a general process, a plurality of photodiodes 11 for generating a signal charge according to an intensity of light incident and a plurality of vertical charge-coupled devices (VCCDS) 12, i.e., charge transmission regions for transmitting the signal charge generated from photodiodes 11, are alternatley formed on a substrate 10. A pad 13 is formed on one side of the substrate excluding a portion where the photodiodes and VCCDs are formed, thereby forming a black/white charge-coupled device.
Of photodiodes 11, reference numeral 11-1 represents a photodiode corresponding to a first color. Reference numeral 11-2 represents a photodiode corresponding to a second color. Reference numeral 11-3 represents a photodiode corresponding to a third color.
A first planarizing film 14 is formed on the entire surface of substrate 10 in which the charge-coupled device is formed.
Thereafter, a color filter layer 15 is formed on first planarizing film 14. Specifically, after forming a resin layer on first planarizing film 14, the resin layer is dyed and adhered with the first color. The colored resin layer is photo-etched, thereby forming a first color filter layer 15-1. By repeating the above process, second and third color filter layers 15-2 and 15-3 are formed on first planarizing film 14, respectively. As a result, the color filter layers of three colors are sequentially formed on first planarizing film 14, thereby completing a process of forming color filter layer 15.
After completing a process of forming color filter layer 15, a second planarizing film 16 is formed on first planarizing film 14 including color filter layer 15, thereby planarizing the substrate again.
Referring to FIG. 1B, as a material 17 for microlens, a photoresist film is coated on second planarizing film 16. By performing a photo-etching process, material 17 for microlens is patterned so as to be left only on each photodiode region 11.
Referring to FIG. 1C, patterned material 17 for microlens is thermally flowed, thereby forming convex microlenses 18 on second planarizing film 16 above each photodiode 11.
Referring to FIG. 1D, a photoresist film 19 is coated on second planarizing film 16 on which microlenses 18 are formed. Then, photoresist film 19 above pad 13 is removed through a photo-etching process, thereby exposing second planarizing film 16.
Exposed second planarizing film 16 and first planarizing film 14 placed thereunder are sequentially etched by using photoresist film 19 as a mask, thereby exposing pad 13.
Finally, after exposing pad 13, remaining photoresist film 19 is removed, thereby producing the conventional color charge coupled device.
In case that the color charge coupled device manufactured according to the above-discussed method is applied to a camera, light incident through a camera lens is converged by microlens 18, and the light converged by microlens 18 is selectively permeated through color filter layer 15. That is, among color filter layers 15, first color filter layer 15-1 selectively permeates light only for the first color, of light converged by the microlens, and applies it to photodiode 11-1 corresponding to the first, color among plurality of photodiodes 11. Second color filter layer 15-2 selectively permeates light only for the second color and applies it to photodiode 11-2 corresponding to the second color. Third color filter layer 15-3 selectively permeates light only for the third color and applies it to photodiode 11-3 corresponding to the third color.
Accordingly, light incident upon each photodiode 11 is transformed photoelectrically, thereby generating a signal charge. The charge generated from photodiode 11 is transmitted to VCCD 12 by the signal transmission operation of a general charge-coupled device, and then, transmitted to a horizontal charge-coupled device (HCCD) (not shown). After sensing the signal charge transmitted to the HCCD due to a floating diffusion from the tip of device, the signal charge is amplified through an amplifier (not shown) and then, transmitted to a peripheral circuit.
However, the method of manufacturing the conventional color coupled device involves the following problems.
First, in order to form the color filter layer according to the conventional method, a photo-etching process is performed three times. During the photo-etching process of forming the color filter layer, a photoresist film is left on an undesired portion, thereby causing color mixing. Further, light is permeated between neighboring color filter layers. This also causes color mixing.
Secondly, since the second planarizing film exists between the microlens and color filter layer, light is likely to be scattered. Further, due to the distance offset between the microlens and color filter layer, it is difficult to adjust a depth of focus to the photodiode.
Thirdly, the second planarizing film is formed after forming the color filter layer, complicating the whole process. This also consumes a great amount of a manufacturing time. The thickness of the device is increased as well.


In the context of a machine-vision system for inspecting a part, a method and apparatus to provide high-speed high accuracy 3D (three-dimensional) inspection of manufactured parts by reducing vibration. One system includes a machine-base unit and a table-base portion supported by the base unit. At least two upright portions are connected to the table-base portion. A first scanner support is coupled to the upright portions. An imager head is coupled to the scanner support, wherein the scanner support moves the imager head in a linear motion to scan the object. A connecting member including at least one vibration-absorbing portion connects to the upright portions to absorb vibrations of the upright portions. Also described is a method of reducing vibration in a three-dimensional scanning apparatus used to determine a geometry of an object having at least one surface to be measured, the scanning apparatus having two or more upright portions and a scanning mechanism coupled the upright portions for moving an imaging head. The method includes supporting the scanning mechanism on the upright portions, dampening vibrations of the upright portions, scanning the imaging head relative to the object, receiving image signals representing a three-dimensional geometry of the object into a computer, and calculating with the computer object-geometry data representing three-dimensional geometry of the object.

This invention relates to the field of machine vision, and more specifically to a method and precision apparatus of obtaining three-dimensional inspection data for manufactured parts in a manufacturing environment.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright(copyright) 1998-2000, PPT Vision, Inc., All Rights Reserved.
There is a widespread need for inspection data for electronic parts in a manufacturing environment. One common inspection method uses a video camera to acquire two-dimensional images of a device-under-test.
Height distribution of a surface can be obtained by projecting a light-stripe pattern onto the surface and then re-imaging the light pattern that appears on the surface.
One technique for extracting this information based on taking multiple images (3 or more) of the light pattern that appears on the surface while shifting the position (phase) of the projected light stripe pattern is referred to as phase shifting interferometry, as disclosed in U.S. Pat. Nos. 4,641,972 and 4,212,073 (incorporated herein by reference).
The multiple images are usually taken using a CCD (charge-coupled device) video camera with the images being digitized and transferred to a computer where phase-shift analysis, based on images being used as xe2x80x9cbuckets,xe2x80x9d converts the information to a contour map (i.e., a three-dimensional representation) of the surface.
The techniques used to obtain the multiple images are based on methods that keep the camera and viewed surface stationary with respect to each other while moving the projected pattern.
One technique for capturing just one bucket image using a line scan camera is described in U.S. Pat. No. 4,965,665 (incorporated herein by reference).
U.S. Pat. No. 5,398,113 and 5,355,221 (incorporated herein by reference) disclose white-light interferometry systems which profile surfaces of objects.
In U.S. Pat. No. 5,636,025 (incorporated herein by reference), an optical measuring system is disclosed which includes a light source, gratings, lenses, and camera. A mechanical translation device moves one of the gratings in a plane parallel to a reference surface to effect a phase shift of a projected image of the grating on the contoured surface to be measured. A second mechanical translation device moves one of the lenses to effect a change in the contour interval. A first phase of the points on the contoured surface is taken, via a four-bucket algorithm, at a first contour interval. A second phase of the points is taken at a second contour interval. A control system, including a computer, determines a coarse measurement using the difference between the first and second phases. The control system further determines a fine measurement using either the first or second phase. The displacement or distance, relative to the reference plane, of each point is determined, via the control system, using the fine and coarse measurements.
Current vision inspection systems have many problems. Among the problems are assorted problems associated with the mechanical translation devices used with the vision inspection systems to handle the devices under inspection. One problem is that vision systems typically take up a large amount of linear space on a manufacturing line. Typically small devices, such as disk-drive suspensions, are placed in standard trays, to facilitate the handling of the small devices. In other cases, the disk-drive suspensions are manufactured from a continuous strip of thin metal, wherein at least a portion of the strip is maintained, with other portions cut away to form the suspensions, thus leaving the suspensions attached to the remaining strip. The suspensions can bend at various angles relative to the strip they are attached to. This strip is then used to facilitate the handling of the suspensions, such as positioning the suspensions under a machine-vision head at an inspection station. The exact positioning of the suspensions in their trays, or their relative orientation to the strip can vary, putting demands on the machine-vision system to determine the orientation and angle of the parts relative to the machine-vision head.
Conventional 3D imaging systems and methods have difficulty in obtaining both speed and accuracy. The support and motion control of the scanning head relative to the parts being scanned present substantial challenges. In particular, vibration problems as well as difficulty in maintaining tight tolerances of scan height across the length of the scan motion make it difficult to obtain accurate measurements of very small parts or parts having a requirement for extreme precision in 3 dimensional geometric measurements.
To overcome the problems stated above as well as other problems, there is a need for a method and precision apparatus of obtaining three-dimensional inspection data for manufactured parts in a manufacturing environment.
In the context of a machine-vision system for inspecting a part, this invention includes method and apparatus to provide high-speed 3D (three-dimensional) inspection of manufactured parts. In some embodiments, precision stamped, formed, and/or laser-cut metal parts are inspected to obtain dimensional and geometric information regarding such characteristics as sag or bow of subportions of the item, the angle of pitch, yaw, and or roll of one portion relative to another, heights of various formations on the part. In some embodiments, this invention includes method and apparatus to provide high-speed 3D inspection of manufactured parts.
One aspect of the present invention provides a machine-vision system for inspecting an object. The system includes a machine-base unit and a table-base portion supported by the base unit. At least two upright portions are connected to the table-base portion. A first scanner support is coupled to the upright portions. An imager head is coupled to the scanner support, wherein the scanner support moves the imager head in a linear motion to scan the object. A connecting member including at least one vibration-absorbing portion connects to the upright portions to absorb vibrations of the upright portions.
Another aspect of the present invention provides a method of reducing vibration in a three-dimensional scanning apparatus used to determine a geometry of an object having at least one surface to be measured, the scanning apparatus having two or more upright portions and a scanning mechanism coupled the upright portions for moving an imaging head. The method includes supporting the scanning mechanism on the upright portions, dampening vibrations of the upright portions, scanning the imaging head relative to the object, receiving image signals representing a three-dimensional geometry of the object into a computer, and calculating with the computer object-geometry data representing three-dimensional geometry of the object.

Precision 3D scanner base and method for measuring manufactured parts


A method of calibrating an interactive touch system includes moving a pointer along at least one path on a touch surface over a calibration image presented on the touch surface. Pointer coordinates are generated generally continuously during the tracing representing pointer contact locations on the touch surface. The coordinate system of the touch surface is mapped to the coordinate system of the calibration image using the pointer coordinates and the calibration image.

Interactive touch systems are well known in the art and typically include a touch screen having a touch surface on which contacts are made using a pointer in order to generate user input. Pointer contacts with the touch surface are detected and are used to generate corresponding output based on the locations of contact. There are basically two general types of touch systems available and they can be broadly classified as "active" touch systems and "passive" touch systems.
Interactive touch systems have a number of applications relating to computer operation and video display. For example, U.S. Pat. No. 5,448,263 to Martin, assigned to SMART Technologies Inc., assignee of the present invention, discloses a passive touch system including a touch screen coupled to a computer. The computer display is projected on to the touch surface of the touch screen via an imaging device such as a projector. The coordinates representing specific locations on the touch surface are mapped to the coordinate system of the computer display. When a user contacts the touch surface of the touch screen, coordinate data is generated by the touch screen and fed to the computer. The computer maps the received coordinate data to the computer display thereby allowing the user to operate the computer in a manner similar to using a computer mouse simply by contacting the touch surface. Furthermore, the coordinate data fed back to the computer can be recorded in an application and redisplayed at a later time. Recording the coordinate data generated in response to user contacts is typically done when it is desired to record information written or drawn on the touch surface by the user.
As the projector is separate from the touch surface of the touch screen, steps must be taken to calibrate the touch system thereby to align the projected image of the computer display with the coordinate system of the touch screen. During calibration, calibration marks are projected on to the touch surface and the user is prompted to contact the touch surface at the calibration mark locations resulting in coordinate data being generated. Since the coordinates of the calibration marks in the computer display coordinate system are known, the coordinate data generated by the touch screen in response to the user contacts at the calibration mark locations can be used to map the coordinate system of the touch screen to the computer display coordinate system. This calibration process corrects for projector/touch surface misalignment, and compensates for scale, skew, rotation and keystone distortion.
Contacting the touch surface at least at three calibration mark locations is required to accurately correct for scale, skew and rotational misalignment of a projected image with a planar touch surface. Contacting the touch surface at least at four discrete calibration mark locations is required to accurately correct for keystone distortion. Keystone distortion is generally the result of non-orthogonal axial misalignment between the imaging device used to project the image and the touch surface. Contacting the touch surface at more than four calibration mark locations during the calibration process provides for more robust calibration of the touch system.
It is common for interactive touch systems to have calibration processes requiring user input at up to eighty-one (81) calibration mark locations. Such a calibration process provides a high degree of accuracy but can be quite time consuming and laborious, since care must be taken to contact the touch surface at the exact location of each displayed calibration mark. If the imaging device or touch surface is bumped or moved, the entire calibration process may need to be repeated. As will be appreciated a calibration process for interactive touch systems that can be performed quickly and easily is desired.
Therefore, it is an object of the present invention to provide a novel method and apparatus for calibrating an interactive touch system.

Method and apparatus for calibrating an interactive touch system


The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.

1. Field of the Invention
The present invention relates to systolic arrays and, in particular, to a reassembly assist for a systolic array of a router used in a computer network.
2. Background Information
A class of data networking equipment, referred to as aggregation or edge routers, has emerged that aggregates thousands of physical or logical links from end users onto one or more higher speed "backbone" links (such as OC-12, Gigabit Ethernet, OC-48 and higher) of a computer network. As the name implies, these routers reside at the edge of the network and are "gatekeepers" for packets transmitted over the high-speed core of the network. As such, they are required to perform a list of advanced "high-touch" features on the packets to protect the network from unauthorized use and to deal with a wide range of unique link interfaces, protocols and encapsulation methods that the end user links require. In order to provide these complex features and to provide flexibility for newly defined features, these routers are normally implemented using specialized, programmable processors.
The sheer processing power and memory bandwidth required to access data structures (e.g., tables) in order to process packets dictates the use of multiple processors within an edge router. A common approach is to organize these processors into one or more parallel one-dimensional (1-D) systolic arrays wherein each array is assigned an incoming packet to process. Each processor within a single systolic array "pipeline" is assigned a piece of the task of processing the packet and therefore only needs access to a memory associated with that task. However, the corresponding processors in other parallel 1-D arrays that are performing the same tasks may also share that same memory. Furthermore, each processor has a limited amount of time (allotted phase) to process its packet without impacting the flow of packets through the system and negatively impacting packet throughput.
Aggregation routers of this class often provide support for multi-link protocols. A multi-link protocol is used to aggregate multiple physical links into a single logical link. Multi-link protocols enable parallel lower speed links to be combined such that they act together as one higher speed link. The combining of links is called bundling and the group of multiple physical links that are combined into a single logical link is called a bundle. Bundling provides the benefits of the combined bandwidth of the aggregated physical links, but with substantially less latency of any one individual physical link. In addition, greater service resilience is provided because the bundle continues to function even when individual links within the bundle fail. Two examples of multi-link protocols is are the multi-link point-to-point protocol (MLPPP) defined in RFC 1990, The PPP Multi-link Protocol, and the multi-link frame relay protocol (MFR) defined in FRF.15, the End-to-End Multi-link Frame Relay Implementation Agreement.
In a multi-link protocol, a packet waiting to be sent on a bundle is often sent on the next available physical link in the bundle. If the packet is large, the packet is typically broken up into a series of fragments (i.e., data fragments) then sent in parallel over different physical links in the bundle. On the receiving end, the fragments are reassembled to form the original packet. By fragmenting packets and sending them in this manner, greater bandwidth can be realized as large packets are sent in parallel and capable of utilizing the capacity of the bundle rather than an individual link. However, one drawback with this method is that fragments may arrive out of order on the receiving end, thereby complicating the process of reassembling the packet.
The reassembly process typically involves tracking fragments and temporarily storing them as necessary until all the fragments have been received. When all the fragments have been received, the packet is typically reassembled by moving each fragment into a packet buffer at a displacement in the buffer that correlates to the displacement of the fragment in the original packet.
The amount of time required to reassemble the packet varies based on the number of fragments that need to be reassembled. In a high throughput systolic array configuration, this variation in time is unacceptable because depending on the number of fragments that need to be reassembled, the processor may not be able to complete the reassembly process within its allotted time phase, thereby possibly stalling other processors in the array. Even if the time phase for the processor was extended to accommodate the worst case largest-sized packet, doing so introduces inefficiencies and wastes valuable processor resources. In addition, having to reassemble a packet when the last packet is received means the processor has to dedicate a greater amount of time to processing the last fragment than it dedicates to processing earlier fragments. Once again this could be remedied by extending the processor phase to accommodate the largest-sized packet, however, as indicated before, doing so wastes valuable resources. It is therefore highly desirable to have a mechanism that makes the packet reassembly process deterministic.

Multi-link protocol reassembly assist in a parallel 1-D systolic array system


In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.

The present invention relates to a simultaneous bidirectional transmission circuit for simultaneously transmitting and receiving signals by using a single transmission line. In particular, the present invention relates to a simultaneous bidirectional transmission circuit suitable for transmitting and receiving data between LSI (large-scale integrated circuit) chips even when the power supply voltage of LSIs is made low.
The simultaneous bidirectional transmission circuit has an input/output circuit at each of ends of a single transmission line, and transmits and receives signals simultaneously via the transmission line. As compared with a typical conventional transmission circuit using separate transmission lines respectively for the transmitting operation and the receiving operation, the number of lines is reduced to half. Therefore, the simultaneous bidirectional transmission circuit is especially useful, for example, in computers which transmit and receive several tens or more data. Typically in the computer application, a plurality of input/output circuits are contained in an LSI chip included in a computer. Between a pair of input/output circuits of LSI chips, a single transmission line is connected. In the case of a plurality of input/output circuits, a plurality of data are transmitted and received via a plurality of transmission lines. In some cases, the number of input/output circuits contained in a single LSI chip is one hundred or more.
In a conventional driver for sending a signal to a transmission line, the output resistance of a driver seen from a connection point of the driver with the transmission line should coincide with the impedance of the transmission line. The necessity of this impedance matching is described in the U.S. Pat. No. 4,719,369. In a driver disclosed in the U.S. Pat. No. 4,719,369, MOS transistors having different internal resistance values obtained by changing gate widths are connected in parallel. By selectively providing those MOS transistors with gate inputs, the output resistance of the driver is controlled so as to coincide with the characteristic impedance. Thus the impedance matching is accomplished.
On the other hand, a simultaneous bidirectional transmission circuit is disclosed in U.S. Pat. No. 5,514,983. A signal existing at the connection point of the simultaneous bidirectional transmission circuit with the input/output circuit contains a mixture of an output signal of the input/output circuit and a received signal which is sent from the other party and which should be received. In order to remove the output signal and extract the received signal from the mixed signal, a differential receiver is provided. By controlling the gate voltage of a reference circuit for outputting a part of the output signal to the differential receiver and the gate voltage of the final stage of the driver in an analog way, the output resistance is provided with a predetermined value.
As the gate voltage of nMOS transistors included in a transmission circuit and nMOS transistors included in the reference circuit described in the aforementioned U.S. Pat. No. 5,514,983, Vc1 outputted from a differential amplifier is supplied. Considering that the power supply voltage of current LSIs is typically 3.3 V, the Vc1 does not exceed 3.3 V, which is the power supply voltage VDD1 of the differential amplifier. Actually, since it is necessary to assure the control range of Vc1, the minimum value of Vc1 becomes approximately 2.5 V. Furthermore, for keeping the output resistance of each of nMOS transistors at a constant value, it is necessary to make the transistors operate in a triode region as described in the U.S. Pat. No. 5,514,983. It is thus necessary to set the power supply voltage VDD2 to be supplied to the drain terminal of each of these nMOS transistors to a voltage of (Vc1-Vth) or less, where Vth is the threshold voltage of an nMOS transistor activated in the source follower operation and Vth is typically at least 1 V. Furthermore, taking the dispersion of the power supply voltage into consideration, the practical value of the VDD2 is approximately 0.8 V. In this case, the (+) input of the differential amplifier based upon the ternary logic has a value of 0.8 V (=VDD2), 0.4 V (=VDD2/2), or 0 V, and the (-) input of the differential amplifier functioning as the reference signal has a value of 0.6 V (=3VDD2/4) or 0.2 V (=VDD2/4). The input amplitude between the (+) input and the (-) input of the differential amplifier becomes .+-.200 mV. It is significantly smaller than .+-.400 mV which is the operation amplitude of typical differential amplifiers. Thus, an amplitude large enough to withstand noise cannot be assured. When the method of controlling the output resistance by using the gate voltage of nMOS transistors as described in the U.S. Pat. No. 5,514,983 is employed, therefore, it is difficult to assure the input amplitude of the differential amplifier for the power supply voltage under the present situation, i.e., 3.3 V, or a lower power supply voltage value in the future. Furthermore, since the Vc1 is generated by an analog feedback loop, problems of noise and oscillation are also posed.

Simultaneous bidirectional transmission circuit


An apparatus eliminates a differential phase shift, Δθ(f), between a double sideband suppressed carrier modulated angular rate information signal and its sinusoidal demodulation reference signal in a gyroscope angular rate sensing circuit including a signal reference source. The apparatus includes a demodulator, a phase shifter in a demodulation reference signal path, the demodulation reference signal path being between the signal reference source and the demodulator. The phase shifter is configured to adjust a phase of the sinusoidal demodulation reference signal. A phase locked loop (PLL) includes a phase detector, a servo equalizer, and a dual-frequency, numerically controlled oscillator. The PLL is configured to provide a demodulation signal based on the phase shifted demodulation reference signal, and a phase shift command source is configured to provide an input to the phase shifter to command an appropriate phase adjustment.

This invention relates generally to digital signal processing (DSP) and, more specifically, to methods and apparatus for the demodulation of a digitized first information bearing signal by a digitized second demodulation reference signal.
A phase-locked loop (PLL) generates an output waveform, such as a sinusoid, that is intended to be locked in both frequency and phase to a reference waveform. The purpose of the PLL action is to synchronize the PLL output waveform with that of an input reference waveform. Depending upon the application, the requirement may be to lock on an input-reference source waveform, or a phase-modified received waveform. However, if the received waveform has been filtered or delayed subsequent to its generation, the PLL output signal will be synchronized with the received signal, but not with the source signal. If the phase difference between the source and received waveforms is small, there may be little consequence. Further, if the phase difference is constant, no matter what the size, it can be compensated by a fixed offset introduced at the phase detector.
However, in certain applications, the phase difference is frequency-sensitive and the frequency of operation is not exactly known, resulting in a phase error which can deleteriously effect the performance of the system in which the PLL is a component. Specifically, in digital gyroscope applications, a frequency sensitive error due both to delays and linear filtering is known to exist. More specifically, two signals are developed within a gyroscope. The first signal is an information signal which carries DSSC (double sideband suppressed carrier) modulated angular rate information of rotation about an input axis of the gyroscope. The second signal is a demodulation reference signal which approximates a sinusoid that is perfectly in phase with the suppressed carrier of the information signal. The two signals are routed along different paths within a gyroscope angular rate sensing system and therefore are subject to both intentional and unintentional filtering and propagation delays which introduce phase shift between the two signals.
If there is a non-zero differential phase shift, that is, if the phase shifts between the two signals are unequal, signal loss and significant errors can occur in a demodulator within the angular rate sensing system which receives both signals as input. The effects of differential phase shift can be mitigated by placing additional filtering in one or both signal paths to substantially eliminate the differential phase shift. Unfortunately, this solution has a potential disadvantage because such a solution can cause problems within the angular rate sensing system that arise due to the introduction of additional delay.
In one specific application, the demodulated angular rate information signal is applied to a flight control computer for navigation, flight control, and stability augmentation of an airborne vehicle. Since the above described digital signal processing operations occur within a closed loop system (the flight control system), critical servo stability issues are at stake, and delays in the two above described signal paths must be minimized.

Methods and apparatus for delay free phase shifting in correcting PLL phase offset


If the number of task attempts has not exceeded the maximum number of attempts, a server system transmits a regular job to cause tasks to execute a particular process, and if the number of task attempts has exceeded the maximum number of attempts, the server system transmits a failed job to cause the tasks to execute post-processing corresponding to the particular process.

Field of the Invention
The present invention relates to a server system for executing parallel distributed processing, a method for controlling the same, and a program.
Description of the Related Art
In recent years, as forms in which a server computer performs various processes, techniques such as cloud computing systems and software as a service (SaaS) have begun to be used. In cloud computing, the execution of data processing is distributed in parallel using many computing resources. This enables the simultaneous processing of requests from many clients. Cloud computing is also characterized in that the serial processing of a job to be executed by a server is broken down into units of task processes, and the tasks of executing the respective task processes are linked together to process the job in parallel, whereby many jobs can be processed in a scalable manner. In the present specification, such a system is referred to as a "cloud system".
The publication of Japanese Patent Application Laid-Open No. 2011-095835 discusses a form in which in a cloud system, to improve the scalability of computer resources and prevent a system down at the peak of requests from clients, a back-end process actively and asynchronously acquires and executes a job. In such a form, if an abnormality has occurred in the back-end process and processing is not completed, a retry function for executing the processing again is required. If a retry is performed, even a back-end process different from the back-end process in which the abnormality has occurred can process the job. The term "back-end process" refers to a program that is recognized and managed as a different process by an operating system (OS) but executes the same processing as that of the back-end process in which the abnormality has occurred. An abnormality occurs in a back-end process when a hardware failure has occurred in a computer, or when a bug has occurred in software implemented in the back-end process.
If tasks are achieved by implementing prescribed processes in a back-end process, a mechanism of executing post-processing may be introduced into the tasks so that a job is normally processed. Examples of the post-processing include the process of notifying by email that job processing has failed, the process of outputting an error log, and the process of changing a status. Each process is a process for notifying a user that a job has not been normally processed, thereby expecting that the job will be processed again and then normally processed.
In a cloud system, however, a retry mechanism asynchronously performs parallel processing, and therefore, the same task does not necessarily repeatedly execute the same job. Thus, tasks cannot determine how many times an acquired job has been processed, and therefore, the tasks cannot execute post-processing at appropriate timing.

Server system, method for controlling the same, and program for executing parallel distributed processing


A seating suspension assembly provides efficiency in the manufacture of upholstered furniture such as chairs, sofas or the like. The preferred form of the invention comprises a pair of flexible, durable fabric straps having coil springs fixedly positioned therebetween. The fabric can be attached to a rigid wooden chair seat frame and the suspension assembly stapled or tacked thereto. The coil springs are thus suspended between the front and back of the frame. Upon upholstering, the suspension assembly provides a comfortable, crowned seat for the user. A method of forming the seating suspension assembly is also disclosed.

1. Field of the Invention
The invention herein pertains to upholstered furniture seating assemblies and particularly to resilient assemblies which are suspended between rigid furniture components such as found on chair or sofa frames.
2. Description of the Prior Art and Objectives of the Invention
Furniture manufacturers have constantly improved their products and manufacturing techniques through the years in an attempt to provide consumers with comfortable, durable and reasonably priced upholstered furniture. Metal coil and sinuous springs have been used for many years in chair and sofa frames to the satisfaction of the purchasers. However, as labor costs have sharply risen, manufacturers are turning to a variety of constructions, some of which utilize fabric straps and webbings in place of the usual metal springs. Certain decking or suspension fabrics have been well accepted whereas others have been either too stiff or too resilient for widespread acceptance. Also, prior spring assemblies for furniture seating of the all metal type are extremely heavy and make handling and shipping difficult and expensive.
Thus, with the disadvantages and problems associated with prior art seating constructions and assemblies, the present invention was conceived and on of its objectives is to provide a seating suspension assembly which w ill provide the user with comfort and durability over a period of years.
It is another objective of the present invention to provide a seating suspension assembly which can be mass-produced in continuous form and delivered to the furniture assembly area in a convenient-to-handle roll.
It is yet another objective of the present invention to provide a seating suspension assembly which can be easily, quickly affixed to a furniture frame by a single worker.
It is still another objective of the present invention to provide a resilient seating suspension assembly and method which may include covered, pretensioned coil springs, fibrous batts or a polymeric foam.
It is also an objective of the present invention to provide a method for forming a suspension assembly utilizing a fabric top strap and a fabric base strap which are joined in parallel alignment to create a pocket therebetween for receiving a coil spring or other resilient member.
It is a further objective of the invention to provide a seating suspension assembly which provides a "crowned" seat.
It is also an objective to provide a seating suspension assembly which has a pre-loaded or tensioned center.
It is another objective of the invention to provide a seating suspension assembly with different tensions along the top, center and bottom.
Still another objective of the invention to provide a suspension assembly which is easy to install by not requiring extreme tensioning on the flexible straps.
Various other objectives and advantages of the present invention will become apparent to those skilled in the art as a more detailed description is set forth below.

Seating suspension assembly formation method


A valve assembly includes a first valve having a first valve stem configured for controlling operation of the first valve, and a second valve having a second valve stem configured for controlling operation of the second valve. A linkage is provided for interconnecting the first and second valve stems so that rotation of the first valve stem rotates the second valve stem, and thereby operates the first and second valves.

Equipment with moving parts, such as rotating or reciprocating compressors, are generally provided with lubrication systems. Such lubrication systems typically comprise a pump that circulates lubricant through the equipment, and a filter that removes impurities that accumulate in the lubricant. When such equipment is to be continuously operated, the lubrication system must be particularly reliable and, to that end, often includes dual filters. When dual filters are used, one is typically on-line while the other is off-line. The on-line filter provides service to the equipment by filtering lubricant for the equipment, while the off-line filter is available for service if needed, or may be cleaned or replaced as necessary.
Dual filters are typically interconnected between the equipment and the pump through a network of lines and valves which control which filter is on-line and which filter is off-line. As shown in FIG. 1, depicting the prior art, this may be achieved by a system 10 comprising conventional dual filters 12 and 14 interconnected via lines 16 and 18 to output ports 24a and 24b of a first three-way valve 24, and via lines 20 and 22 to input ports 26a and 26b of a second three-way valve 26. The valves 24 and 26 include input and output ports 24c and 26c, respectively, and valve stems 24d and 26d, respectively, operable for controlling flow through the respective output and input ports of the valves. A pump 30 and reciprocating compressor 32 are serially connected between the input port 24c and the output port 26c, and a rupture disc 34 is connected in parallel across the pump 30. The pump 30 circulates lubricant through the first valve 24, one of the filters 12 and 14, the second valve 26, and the compressor 32. In operation, the valves 24 and 26 must both be synchronized for directing fluid, such as a gas, liquid, slurry, or the like, to flow through either filter 12 or filter 14 as the on-line filter. It can be appreciated that when the filters 12 and 14 are switched between being on-line and off-line, the valves 24 and 26 must be turned simultaneously and synchronously or the system will be blocked ("dead-headed"). As a consequence, pressure will build up and pop the rupture disc 34, causing the system 10 to lose pressure. The compressor 32 would then not receive lubrication until the rupture disc 34 was replaced, thereby necessitating a shut down of the compressor 32 before it overheated and failed, resulting in substantial down-time costs.
Therefore, what is needed is a system and method wherein filters or subsystems thereof may switched between being on-line and off-line without incurring the risk that the system will be blocked and necessitate a shut-down of the system.


A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.

Error-correction coding, also called channel coding, is a type of digital signal processing that improves data reliability by introducing a known structure into a data sequence prior to transmission or storage. This structure enables a receiving system to detect and possibly correct errors caused by corruption during transmission or storage. This coding technique enables the decoder to correct errors without requesting retransmission of the original information or retrieving corrupt information from storage.
FIG. 1 is a block diagram illustrating an exemplary communication system. In communication channels that employ error-correction coding, a digital information source sends user data to an encoder 101. The encoder 101 inserts redundant bits, or parity bits, thereby outputting a longer sequence of code bits called a codeword. The codeword is sent through the transmission channel 102, where errors could occur due to noise or other factors. The codewords are received by a decoder 103, which extracts the original or recovered user data.
For many algebraic error correction codes, such as Reed-Solomon codes and BCH (Bose, Ray-Chaudhuri, Hocquenghem) codes, the complexity of the decoding scheme is determined by the desired error correction power and field size. Known communication systems use either erasure decoding or error decoding. When the locations of the errors are known, erasure decoding is used. For example, when a receiver detects the presence of jamming, fading, or some transient malfunction, it may choose to declare a bit or symbol erased. Attempts to correct the erasures can then be performed using the error correction codes and the erasure information. Here, the decoder receives erasure information, which indicates the location of zero or more suspected corrupt symbols within a codeword. Otherwise, error decoding is used. In error decoding, the decoder attempts to correct the errors by finding both the locations of the errors and by recovering the original symbols using the error correction codes. Reed-Solomon and BCH codes, as well as erasure and error decoding, are well known in the art and will not be described here in detail. Erasure decoding requires fewer operations than error decoding but requires erasure information, which is not always available. Error decoding does not require erasure information, however, in general, it is more complex, requiring more operations than erasure decoding.
Accordingly, there is a need for a method and system for reducing the complexity of error correction decoding while maintaining a desired error correction performance level.

Error correction decoding methods and apparatus


According to one embodiment, a storage control apparatus includes an interface and a controller. The interface transfers data or a command to or from a nonvolatile memory including a storage area for each of banks. The controller controls read operations for the banks in accordance with generation of access requests to the banks, respectively. The controller prioritizes performing read-command issuance processing included in each of the read operations.

Recently, as a data storage apparatus typically represented by a hard disk drive (HDD), a hybrid memory device which uses a nonvolatile memory such as a NAND flash memory (hereinafter simply referred to as a flash memory) together with a disk as storage media has been developed.
In such the hybrid storage apparatus, the flash memory comprises a storage area divided into a plurality of memory banks (hereinafter simply referred to as banks). A flash memory controller controls the flash memory in accordance with a so-called interleaving method which can simultaneously access to respective banks.
Here, an interface between the flash memory controller and the flash memory cannot transfer data simultaneously to the respective banks. Therefore, the flash memory controller has an arbitrator to arbitrate buses of the interface when a conflict occurs in access to a plurality of banks. By interleaving of the arbitrator, faster access is achieved.
However, in actual flash memory control, a series of processing including issuance of a read command needs to be performed for a read operation to read data from the flash memory. Therefore, simply performing arbitration with use of the interleaving method is not sufficient to reduce the time required for the read operation and to realize reading efficiency.

Prioritizing read-command issuance in a data storage apparatus


A method of preparing a non-conductive substrate to allow metal plating thereon. The method includes the steps of a) contacting the non-conductive substrate with a conditioner comprising a conditioning agent; b) applying a carbon-based dispersion to the conditioned substrate, wherein the carbon-based dispersion comprises carbon or graphite particles dispersed in a liquid solution; and c) etching the non-conductive substrate. The etching step is performed before the liquid carbon-based dispersion dries on the non-conductive substrate.

Printed wiring boards (also known as printed circuit boards or PWB's) are generally laminated materials comprising two or more plates of foils of copper, which are separated from each other by a layer of non-conducting material. Although copper is generally used as the electroplating metal in printed wiring boards, other metals such as nickel, gold, palladium, silver and the like can also be electroplated. The non-conducting layer(s) preferably comprise an organic material such as an epoxy resin impregnated with glass fibers, but may also comprise thermosetting resins, thermoplastic resin, and mixtures thereof, alone or in combination with reinforcing materials such as fiberglass and fillers.
In many printed wiring board designs, the electrical pathway or pattern requires a connection between the separated copper plates at certain points in the pattern. This is usually accomplished by drilling holes at the desired locations through the laminate of copper plates and the non-conducting layer(s) and connecting the separate metal plates. Subsequently, the through-hole walls of the printed wiring board are prepared for electroplating. These plated through-hole walls are necessary to achieve connections between two metal circuit patterns on each side of a printed wiring board, and/or between the inner layer circuit patterns of a multilayer board.
While electroplating is a desirable method of depositing copper and other conductive metals on a surface, electroplating cannot be used to coat a nonconductive surface, such as an untreated through hole. It is therefore necessary to treat the through hole with a conductive material to make it amenable to electroplating.
One process for making the through-hole bores electrically conductive involves physically coating them with a conductive film. The coated through-holes are conductive enough to electroplate, but typically are not conductive and sturdy enough to form the permanent electrical connection between the circuit layers at either end of the through-hole. The coated through-holes are then electroplated to provide a permanent connection. Electroplating lowers the resistance of the through-hole bore to a negligible level, which will not consume an appreciable amount of power or alter circuit characteristics.
One method of preparing through-hole walls for electroplating is a carbon-based process that utilizes a liquid carbon dispersion. The typical steps of this process are as follows:
1) Surfaces of the through-holes are drilled and deburred. In the case of multilayer printed circuit boards, the boards may also be subjected to a desmear or etchback operation to clean the inner copper interfacing surfaces of the through holes;
2) The printed wiring board is preferably subjected to a precleaning process to prepare the printed wiring board to receive the liquid carbon black dispersion thereon;
3) After the application of the cleaner, the PWB is rinsed in water to remove excess cleaner from the board and then contacted with a conditioner solution. The conditioner solution ensures that substantially all of the hole wall surfaces are prepared to accept a continuous layer of the subsequently applied carbon-based dispersion;
4) The liquid carbon-based dispersion is applied to or contacted with the conditioned PWB. The liquid carbon dispersion contains three critical ingredients, namely, carbon black, one or more surfactants capable of dispersing the carbon, and a liquid dispersing medium such as water. The preferred methods of applying the dispersion to the PCB include immersion, spraying or other methods of applying chemicals that are typically used in the printed circuit board industry. A single working bath is generally sufficient for applying the carbon dispersion; however, more than one bath may be used for rework or other purposes; and
5) The carbon-covered printed wiring board is subjected to a step wherein substantially all (i.e., more than about 95% by weight) of the water in the applied dispersion is removed and a dried deposit containing carbon is left in the holes and on other exposed surfaces of the nonconducting layer. This drying step may be accomplished by various methods, including, for example, evaporation at room temperature, heating the PWB for a period of time at an elevated temperature, an air knife, or other similar means generally known to those skilled in the art. To insure complete coverage of the hole walls, the procedure of immersing the board in the liquid carbon dispersion and then drying may be repeated.
Thereafter, the metal portions of the substrate are aggressively etched with high spray pressures and high total etch amounts to sufficiently remove the dried carbon coating from the metal portions of the substrate.
The microetch procedure performs two very desirable tasks at once: (1) the microetch step removes substantially all excess carbon black or graphite material adhering to the outer copper plates or foils and the exposed surfaces of copper inner plates or foils in a multilayer PWB; and (2) the microetch step chemically cleans and microetches slightly the outer copper surfaces, thereby making them good bases for either dry film application or the electrolytic deposition of copper when followed by mechanically scrubbing of the PWB.
The mechanism by which this microetch step works is not by attacking the carbon black material or the graphite material deposited on the copper foil directly, but rather by attacking exclusively the first few atomic layers of copper directly below which provides the adhesion for the coating. The fully coated board is then immersed in the microetch solution to "flake" off the carbon black or graphite from the copper surfaces in the form of micro-flakelets. These micro-flakelets may then be removed from the microetch bath either by filtration through a pump or via a weir type filter arrangement commonly used in the PWB industry.
The liquid carbon black dispersion or graphite dispersion, the microetch treatment, and the intermittent water rinses are preferably carried out by immersing the PWB in baths constructed of polypropylene or polyvinyl chloride (PVC) and kept agitated by a recirculation pump or pumped in air or by a conveyorized flood or spray machine. The carbon black or graphite coated PWB is immersed in or otherwise contacted with the microetch solution to "flake" off the carbon black or graphite from the copper surfaces which are then removed from the microetch bath by filtering or other similar means.
The steps of this process are described in more detail, for example, in U.S. Pat. No. 4,619,741, the subject matter of which is herein incorporated by reference in its entirety. Various modifications and refinements to this process are set forth in U.S. Pat. Nos. 4,622,107, 4,622,108, 4,631,117, 4,684,560, 4,718,993, 4,724,005, 4,874,477, 4,897,164, 4,964,959, 4,994,153, 5,015,339, 5,106,537, 5,110,355, 5,139,642, 5,143,592, and 7,128,820, the subject matter of each of which is herein incorporated by reference in its entirety.
U.S. Pat. No. 4,897,164 to Piano et al. describes a process in which after the drying step, the dried deposit of carbon black in the through-holes is contacted with an aqueous solution of an alkali metal borate prior to microetching to remove loose or easily removable carbon black particles from the areas of the through-holes.
U.S. Pat. No. 4,964,959 to Piano et al. describes the addition of a conductive polymer or combinations thereof to the carbon back dispersion.
U.S. Pat. No. 4,994,153 to Piano et al. describes a process for treating the tooling holes or slots which have been coated with a carbon black dispersion in a nonconductive material which comprises removing said carbon black with an aqueous solution containing: (a) an alkanolamine; (b) an anionic surfactant which is the neutralized addition product of maleic and/or fumaric acid and a poly(oxylated) alcohol; (c) a nonionic surfactant which is an aliphatic mono and/or diphosphate ester; and (d) an alkali or alkaline earth metal hydroxide.
U.S. Pat. No. 5,015,339 to Pendleton describes an electroplating pretreatment wherein nonconductive material is first contacted with an alkaline permanganate solution, then a neutralizer/conditioner solution and then a carbon black dispersion.
All of the processes described in these references contain a step in which the carbon-covered printed wiring board is subjected to a step wherein substantially all (i.e., more than about 95% by weight) of the water in the applied dispersion is removed and a dried deposit containing carbon is left in the holes and on other exposed surfaces of the nonconducting layer prior to the microetching step.
In a variation on this basic process, the carbon-coated wiring board may be subjected to a fixing step prior to drying in order to remove excess carbon dispersion from the surface of the printed wiring board and to make the carbon dispersion more workable as described, for example, in U.S. Pat. Pub. No. 2010/0034965 to Retallick et al., the subject matter of which is herein incorporated by reference in its entirety. Fixing may be accomplished by a chemical fixing method or by a mechanical fixing method.
In chemical fixing, a fixing solution is applied to the surfaces that have been wetted with the carbon dispersion and the fixing solution removes excess carbon composition deposits, smoothing the carbon coating on the recess surfaces by eliminating lumps and making the coating more uniform. In physical fixing, the recesses or other surfaces of the substrate which have been wetted with the carbon dispersion are subjected to a mechanical force to remove excess deposits of the carbon coating before it is dried. For example, a fluid jet may be used to contact the surfaces that have been coated with the carbon dispersion. The jet blows away any excess accumulation of the carbon deposit and smooths the carbon coating on the recess surfaces by elimination lumps and making the coating more uniform. Another fixing means involves the use of an air jet in the form of an air knife.
Once the carbon-coated printed wiring board has been microetched, the printed wiring board can be electroplated with a suitable conductive metal.
The microetch frequently causes problems, particularly in plating in the area of the copper dielectric interface. In particular, etching the copper frequently also strips the carbon coating from the dielectric area directly adjacent to the copper, thereby creating an insulating barrier for electrical continuity in the subsequent electroplating step. This barrier may then lead to poor plating and defects such as voids, knit lines, and plating folds. To avoid such kinds of defects, a lower microetch step is desirable.
To adequately remove the carbon black or graphite from the copper surfaces, large pumps, high pressures, large etch chambers, and/or aggressive etching chemistry must be employed to produce an acceptable result. In addition, it is also necessary that the equipment be cleaned often to reduce nodulation in the metal plating step for the carbon black or graphite that has been flaked off the copper surfaces.
Thus, it would be desirable to provide a direct plating process that offers reduced nodulation and that also does not require additional processing steps or conditions to produce a good result.


An external hard disk is connected to a personal computer (PC) through the parallel port. A parallel-port expansion card is installed on the AT bus in the PC for communicating with the external hard disk. The parallel-port expansion card has a ROM containing intercept code. The address of the ROM is automatically configured when the system BIOS scans for expansion ROMs during booting. When no other ROM drives the data bus when an address is scanned, the parallel-port card latches the address and has the ROM drive its data onto the bus. Future accesses to the latched address access the ROM. The ROM's code replaces the interrupt table's starting address of the hard-disk-controller routine with the address of an intercept routine. All hard-disk operations using the interrupt first execute the intercept routine. The intercept routine copies any data writes to the external disk. Thus the external disk has a redundant copy of the PC's internal hard disk. The external hard disk can be the boot disk by having the intercept routine route all disk reads and writes to the external disk any not pass any disk operations through to the PC's internal hard disk.

1. Field of the Invention
This invention relates to Personal Computers (PC's), and more particularly to adapters for connecting a redundant disk to the Parallel Port of a PC.
2. Description of the Related Art
Personal computers (PC's) are a vital part of most businesses today. While larger companies often use large mainframes for critical data, smaller firms often use inexpensive PC's even for critical data. The cost of PC's have fallen so much that the firm's data stored on the PC can be more valuable than the PC itself. Customer lists, work in progress, commercial and proprietary software are some examples.
The mantra of the expert's advice to these firms is "backup, backup, backup." Tape drives for backing up the PC's data are commonly used today to offer a degree of protection from data disaster. Unfortunately, these tape drives are slow in comparison to the hard-disk drives the primarily store the data, and users may perform a backup of their data only once a day, week, or month. The user often has to run specialized backup software, or a network administrator has to set up a backup schedule for networked PC's.
Redundant hard-disk drives are becoming increasingly popular, since data is backed up to the redundant hard disk immediately each time data is written to the primary hard disk. Thus no data is lost. However, these redundant disk arrays (RAID) are typically difficult to install, being mounted inside the PC's chassis. RAID disks installed inside the PC's chassis are not easily transportable. The complexities of installing a RAID disk in a PC can discourage many potential users.
Disks can also be installed outside of the PC's chassis. One desirable feature of PC's are the industry-standard busses and communication ports, allowing easy expansion by the end user. Early PC's had a serial port and a parallel port, usually located on the rear panel of the chassis. The serial port was used to communicate data in a serial fashion to external devices such as modems and mice, while the parallel port was used to communicate 8 bits of data in parallel to a printer. The connection of an external printer to the parallel port is so common that it is also known as the printer port.
The types and number of external devices that connect to the serial and parallel ports of a PC has grown over the years. While once just a printer was attached to the parallel port, now many users have two printers--a high-quality laser printer and a draft-mode dot-matrix printer. Other devices have also appeared that connect to the parallel port. These devices include external disk drives, tape drives, CD-ROM drives, and local-area network adapters. Data transfer to a portable PC such as a Laptop or Notebook can occur over a special cross-wired serial or parallel cable that connects a desktop PC to the portable PC.
Disks attached to the PC's parallel port are common today, but they operate as an additional disk drive rather than as a redundant disk drive. These disks do not mirror the writes to the PC's internal hard disk and thus do not provide redundancy. Standard PC software drivers and BIOS do not provide for redundancy. Configuring the parallel port and disk is complex because addresses and interrupts may have conflicts with other expansion devices on the PC. Often jumpers are used to select the addresses or interrupts for an expansion card.
When the primary disk fails, the PC must be re-started or booted from another disk. Often the removable diskette or floppy disk drive is used. When the data is backed up to the disk on the parallel port, the software driver for the parallel-port disk must also be loaded to memory, perhaps requiring that the boot diskette be swapped out for the parallel-port driver diskette. Swapping diskettes is undesirable, and the diskettes are easy to lose.
It is thus desirable to boot the computer from a hard disk on the parallel port. It is especially desirable to boot the PC from a redundant disk on the parallel port. It is desired to automatically mirror writes to the primary hard disk to the parallel-port disk so that the parallel-port disk is a fully redundant back-up disk. It is further desired to automatically configure the address of the parallel-port controller.

Bootable redundant hard disk attached to a PC's parallel port with rom-address auto-detect and configure during BIOS scan