An electronic program guide (EPG) having a variable indicator to focus a user's attention upon a corresponding field of a selectable program instance The EPG includes a user interface screen for providing a plurality of television program instances by time and channel in a grid menu. Each television program becomes selectable from the EPG based upon user interaction. The indicator is depicted in association with each television program when it becomes selectable as a result of user interaction. The indicator is configured based upon attributes of the currently selectable program instance.

Subscription television systems typically include an electronic program guide (EPG). With the development of interactive digital set-top boxes (STBs), a new type of advanced multimedia EPG was developed which may be referred to sometimes as interactive program guides (IPGs). Today, the acronyms EPG and IPG have been used interchangeably. The EPG provides an onscreen display of a program grid menu that includes a program lineup and episode information for every channel for the next several days. The program grid menu may be arranged in various ways. The program grid menu itself is a user interface where the user may navigate the program grid menu using arrow keys on a remote. For example, a typical EPG would have a program grid menu based on available channel and time. The user can navigate or scroll through the list of programs within a selected time slot until the desired program is highlighted. The boundaries of other fields associated with the highlighted field may also be highlighted such as the corresponding channel and time. The highlighted field may also sometimes be referred to either as a pill or as being active. Once the desired field is highlighted as a selectable item, the user may select the highlighted field using the select button on the remote.
Typically, a field in the EPG is shown as being highlighted by using a different color background relative to the background of any other field. Alternatively, a selectable field may be depicted as being enlarged or oversized. For the purposes of describing the present invention, the surrounding boundary or edge of the field corresponding with a selectable field is bolded to depict a field being highlighted. Although the present invention illustrates EPGs having a particular configuration or number of fields, today's EPGs include hundreds or even thousands of possibilities which the user may scroll through, highlight and select. Therefore, because of the increasing number of options within an EPG, as well as because of the difficulty some users have determining which item is selectable, there is a need to bring greater attention to the selectable item within the EPG.
The present invention will be described more fully hereinafter with reference to the accompanying drawings in which like numerals represent like elements throughout the several figures, and in which an exemplary embodiment of the invention is shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is described more fully hereinbelow.
FIG. 1 illustrates a screen-shot of a graphical user interface screen 10 of an EPG according to one embodiment of the present invention. The screen 10 may be presented in response to user input that may be provided via the activation of a guide key on a remote control, for example, the "Guide" key. In the top right of the screen 10, video corresponding to the channel to which a device is currently tuned may be displayed in the video area 12. Immediately below the video area 12 is an information banner 16 for displaying the channel number corresponding to the channel to which the device is currently tuned, the current day and date, and the current time. The method used to indicate time in the present invention is commonly referred to as military time. However, other methods of indicating time may be utilized.
The top left portion of the screen 10 is a detailed focus area 20 may include detailed information for a currently selectable instance of a program. The detailed focus area 20 may include channel number, channel description, presentation name, duration of the presentation, and/or any episode information or rating. The bottom area 24 of the screen 10 also indicates the current day for which presentation listing data is being displayed as well as information about the current functions of the optional "A" and "B" keys that may be on the remote controls and are used in conjunction with the EPG. Further information regarding an interactive program guide can be found in copending U.S. patent application Ser. No. 10/212,017 filed on Aug. 2, 2002, the disclosure and teachings of which are hereby incorporated by reference.
The user interface screen 10 of FIG. 1 includes a grid menu of television program instances in program instance fields 25 that can be identified by time and channel. In FIG. 1, the time corresponding to each of the program instances is provided in a time portion 26, that is arranged vertically in a column along the left of the grid menu in the example embodiment of FIG. 1. The channel corresponding to each instance is shown in a channel portion 28, depicted as a horizontal row along the top of the grid menu.
Each row of fields within the grid menu is scrollable up and down and to the left and right where each scroll highlights a different field. For example, as a user scrolls in time across the grid menu, different program instances corresponding with different program instance fields 25 are highlighted as selectable and information such as the day and date indications displayed in various areas of the screen 10 are updated. However, as explained above, the television programs may be arranged in any other manner. For example, the user interface screen of an EPG may be configured such that the EPG itself appears to move while a selectable field which is highlighted is maintained at the center of the grid menu. Preferably, the user interface screen 10 is created by utilizing images which may be tiled or stretched as background for drawn text. These background images may be tiled in either horizontal or vertical directions. Those skilled in the art appreciate that any tilable image carries with it information so that the image can morph itself when the image is displayed. For example, in FIG. 1, the user interface screen 10 includes one or more background images and accompanying text which correspond with the horizontal list of channels. One or more other background images may be utilized to correspond with the columns and rows of program instance fields 25 which make up the program grid of television programs. Text is then drawn over these background images to identify each instance of the programs presented from the EPG. Other background images may be utilized elsewhere in the user interface screen 10.
Still referring to FIG. 1, a television program instance titled "News", which corresponds with program channel 281 and has a start time of 1930 Hrs, is identified by reference number 30. The edge of the program instance field having the text for identifying the television program instance 30 is bolded to depict being highlighted as a result of user interaction such as scrolling through the program grid.
The screen 10 of the present invention also includes an indicator 40 according to one embodiment of the invention. The indicator 40 is preferably utilized as part of interactive television such as with an EPG/IPG to indicate position, start and end times, and/or duration of a selectable instance of a program. In FIG. 1, the indicator 40 corresponds with the position in the grid menu of the highlighted and selectable television program instance 30 titled "News". However, the indicator 40 may be utilized elsewhere as part of any graphical user interface that may be implemented as part of, for example, video games, interactive course ware, PDA's, cell phones, etc.
In one embodiment, the indicator 40 may be, but is not limited to, one or more graphic elements, separate or in combination with one another, which could be a graphic primitive such as a rectangle or oval or a complex image format such as GIF, JPEG, PNG or others, which may be configured in any number of ways. Preferably, the indicator 40 is variably sized depending on the attributes of the corresponding selectable program instance. Because of the variable size of the indicators of the present invention, the indicators of the present invention may be referred to as thermometers that measure the position, start and end times, and/or duration of a selectable program instance.
In FIGS. 1-3, the indicator 40 is depicted as being part of the vertical column indicating time in the grid menu and is, therefore, elongated in the vertical direction. Preferably, the indicator does not appear to fill the entire field of a time period. For example, the width of the indicator does not extend over the rest of the tile behind the text identifying the channel number of the program instance 30.
Indicators of the present invention may also indicate the start time as well as the duration of a program instance. Still referring to FIG. 1, one of the ends the indicator 40 corresponds with the start time of the corresponding selectable program instance 30, which is 1930 Hours, and the other end of the indicator 40 corresponds with the end time of the corresponding selectable program instance 30, which is 2000 Hours. Therefore, the indicator 40 not only conveys position, the length of the indicator 40 corresponds with the duration of the selectable program instance 30 which, in this example, is a half an hour long.
FIG. 2 illustrates an indicator 50 according to another embodiment of the present invention. In FIG. 2, the user has scrolled down in the grid menu of the screen 10 to a later time compared to the time of the selectable program instance 30 shown in FIG. 2. Indicator 50 corresponds with the program instance 52 which is shown to be a full hour in duration because one end of the indicator 50 corresponds with the start time of the corresponding selectable program instance 52, which is 2000 Hours, and the other end of the indicator 40 corresponds with the end time of the corresponding selectable program instance 30, which is 2100 Hours.
FIG. 3 illustrates an indicator 60 according to another embodiment of the present invention. In FIG. 3, the user has scrolled to the right in the grid menu of the screen 10 to a different channel than the channel of either of the selectable program instances 30, 50 of FIGS. 1 and 2. Indicator 60 corresponds with the program instance 62 which is shown to be two hours in length. One end of the indicator 60 corresponds with the start time of the selectable program instance 62, which is 1900 Hours, and the other end of the indicator 60 corresponds with the end tine of the selectable program instance 62, which is 2100 Hours.
FIG. 4 illustrates a screen-shot of an alternative graphical user interface screen 70 of an EPG according to another embodiment of the present invention. As does screen 10 described-above in regard to FIGS. 1-3, screen 70 includes a grid menu of television program instances identified by time and channel. However, the screen 70 is distinguishable from screen 10 because in FIG. 4 the channels corresponding to each of the program instances are arranged vertically in a column along the left of the grid menu and the time corresponding to each instance is shown in a horizontal row along the top of the grid menu.
In FIG. 4, an indicator 72 corresponds with the position in the grid menu of a highlighted and selectable television program instance 74 which is in the same time slot of the same program as program instance 62 is in FIG. 3. However, because time and channel in FIG. 4 is inverted to the time and channel of FIG. 3, the indicator 72 is horizontally oriented rather than vertically oriented. One end of the indicator 72 corresponds with the start time of the selectable program instance 74, which is 1900 Hours, and the other end of the indicator 72 corresponds with the end time of the selectable program instance 74, which is 2100 Hours.
In some embodiments, the attributes of the indicators of the present invention may be controlled by the user. For example, the colors of the indicators of the present invention may also be varied based upon the genre of the highlighted selectable program instance or be determined by user controlled preferences. The user may also control other attributes of the indicator, for example, such as the height, width, invisibility, brightness, or whether the indicator is on or off. Also, the indicators of the present invention may be intermittently displayed to the user. For example, the indicator may be made to appear to blink to gain the users attention to then help the user find the currently selectable field. In another embodiment, the indicator may no longer blink when the user is no longer scrolling and after a particular program instance has been highlighted for a particular period of time. In another embodiment, the rate at which the indicator blinks can be varied depending upon the length of time a particular program instance is highlighted. The rate at which the indicator blinks may also be based upon the duration of the currently selectable program. For example, program instances which are shorter in duration may have corresponding indicators which blink more frequently to gain the users attention than do program instances which are longer in duration.
The foregoing has broadly outlined some of the more pertinent aspects and features of the present invention. These should be construed to be merely illustrative of some of the more prominent features and applications of the invention. Other beneficial results can be obtained by applying the disclosed information in a different manner or by modifying the disclosed embodiments. Accordingly, other aspects and a more comprehensive understanding of the invention may be obtained by referring to the detailed description of the exemplary embodiments taken in conjunction with the accompanying drawings, in addition to the scope of the invention defined by the claims.

Graphical indication of selected cell within an interactive program guide


An operating system architecture that provides a high level of system functionality in a multimedia console through the use of concurrent system applications, while reducing the lack of control that multimedia applications have while running on the console. At power ON, a predetermined amount of system resources are reserved within which the concurrent system applications execute. The multimedia applications are afforded control over the unreserved system resources and do not need to support system functionalities as the concurrent system applications provide system functionalities to end users.

Multimedia devices, such as video game consoles, have traditionally provided an operating system that "gets out of the way" of the developer. In particular, in conventional video game consoles the game developers are provided with near total control of the hardware and the operating system is driven by the multimedia application. As game software is often developed for a particular platform, the available hardware resources (e.g., memory, processor speed, etc.) are well known. This architecture provides developers complete autonomy and insight into how every CPU cycle is used. Thus, software developers can manage and maximize the usage of the hardware resources and provide a high performance multimedia application. There is a significant drawback to this approach in that system services are severely constrained and require explicit direction by the application. This direction is necessary because there is only one application running on the system at any point in time (i.e., the multimedia application). Another drawback is because each application provides its own interface to system resources, the user's experience may differ significantly from application to application. Yet another drawback is that the operating system functionality cannot be updated over time in conventional multimedia devices.
The other end of the continuum of resource control is found in the conventional personal computer (PC), in which applications typically have limited control over the underlying functionality of the operating system. This approach provides a large amount of functionality in the operating system, without requiring that it be controlled by the application. Further, this provides for multiple applications to run simultaneously without requiring them to be aware of each other. The drawback of this approach is that an application has much less control over system resources, such as CPU cycles, RAM, network bandwidth, etc., and has to be architected to assume that it is not the only application running.
As multimedia devices grow in power there will be a greater demand to provide system services to applications while maintaining the benefits of existing multimedia console operating systems where developers have almost full control of system resources. Thus, there is a need for a system and method of providing system services in a multimedia device to enable more functionalities, while maintaining an application's high level of control over the operating system and hardware resources. The present invention provides such a solution.

Concurrent system applications in a multimedia console


A temperature controller for controlling a thermal module that raises or lowers the temperature of a thermal control platform that includes a reading interface and a control unit. The reading interface is used for reading parameters of the thermal control platform that are stored in a memory module. The control unit is connected to the reading interface for receiving the parameters read by the reading interface and for sending a control signal to the thermal module according to the corresponding parameters. The thermal module then raises or lowers the temperature according to the control signal. Accordingly, the temperature controller automatically adjusts the temperature control to different thermal control platforms.

General thermal control platforms can be used to test electronic components, material properties and even provide a condition for the growth of elements. For example, a thermal control platform can enable the electronic components to be heated to a proper temperature for an electrical test. Alternatively, a thermal control platform can also have a proper internal environment for semiconductor wafers growing epitaxial layers or carbon nanotubes. Therefore, accurate thermal control platforms have a very important impact on the scientific and technological progress.
In the prior art, the thermal control platform comprises a platform body and a thermal module. The platform body is used for carrying an analyte or other objects and can be in any form such as a stage or a cavity. The thermal module is used to raise or lower the temperature of the thermal control platform so as to reach a desired temperature condition. In addition, the thermal control platform can have a built-in temperature sensor to feedback the temperature of the analyte or the platform body to the temperature controller so as to have a more accurate temperature control.
In order to have accurate temperature control and to prevent the thermal module from burning when exceeding the temperature limit, the user must first input the parameters of the thermal control platform into the temperature controller so that the performance of the temperature control can be optimized. The above parameters of the thermal control platform depend on the design of the platform body. For example, the material of the surface of the thermal control platform, the operating temperature range, the PID parameters, the cooling capacity of the cooling structures, the maximum cooling power of the thermal module and the upper limit of the voltage or current of the thermal module are all included in the parameters. The temperature controller can control the input voltage or the input current of the thermal module according to the above parameters to have an accurate temperature control of the thermal control platform.
Because the designs of different thermal control platforms are not the same, it is necessary to input new parameters manually when the user uses a different thermal control platform. Furthermore, when the user uses an identical thermal control platform but with a different temperature controller, it is still necessary to input new parameters for the new temperature controller. The action of re-entering the parameters manually is not only making the operation inconvenient but also increasing the possibility of system errors.

Temperature controller and thermal control platform


A press-fitting device in which a terminal of a connector having a staggered arrangement section of the terminal of the connector is press-fitted into an insertion hole is provided. In the press-fitting device, a first terminal restricting member on which a guide section for restricting a vertical displacement of the terminals between the terminals along the lateral direction of the connector housing and a second terminal restricting member on which a guide section for restricting the lateral displacement of the terminals between the terminals along the vertical direction of the connector housing in an upper or lower part of the first terminal restricting member are provided. A guide groove to which terminals on an interior side of the connector housing are introduced is provided at a tip end portion of the guide portion positioned at the staggered arrangement section of the terminals.

1. Field of the Invention
The present invention relates to a terminal press-fitting device for which a tip end section of a terminal provided in a projected manner in a connector housing is press-fitted into an insertion hole formed on a substrate to connect the terminal and the substrate.
2. Description of the Related Art
A conventional structure is described in JP-A-7-65929, for example. In JP-A-7-65929, a for-substrate connector in which pin-like terminals (for-substrate connection pieces) are provided in a matrix form and are provided in a projected manner is mounted on a substrate such that the first comb teeth-like terminal arrangement plate in which guide grooves for guiding the pin-like terminals arranged in columns are formed at the same interval as the column space pitch and the number of columns is attached at a position in the vicinity of a face of the connector abutting against the substrate. Thereafter, the second comb teeth-like terminal arrangement plate in which guide grooves for guiding the terminals arranged in rows are formed at the same interval with the row space pitch and the number of rows is attached in the vicinity of the surface of the above-mentioned first comb teeth-like terminal arrangement plate. Then, the tip end of the above-mentioned terminal projecting out of the surface of the second comb teeth-like terminal arrangement plate and the insertion hole (through hole) of the substrate are used to temporarily mount the connector on the substrate to remove the first and the second comb teeth-like terminal arrangement plates. Thereafter, the above-mentioned connector is pressed toward the substrate side so that this connector is mounted on the substrate.
As described above, the above-mentioned structure is provided such that the above-mentioned tip end section of the terminal is press-fitted into the insertion hole formed in the substrate while the pin-like terminals provided in a projected manner in the connector housing are restricted by the above-mentioned first and the second comb teeth-like terminal arrangement plates. This structure has an advantage in that the above-mentioned connector can be mounted on the substrate without requiring special man-hours for modification even when these terminals have a thin shape and thus tend to be bent or to slant. However, this structure has a problem in that arrangements other than the matrix-like arrangement in which a plurality of terminals are provided on intersection points at which a plurality of lines extending column-wise of the connector and a plurality of lines extending row-wise intersect with one another prevent the comb teeth of the first and the second comb teeth-like terminal arrangement plates from providing the function for sufficiently positioning the terminals, thus failing to provide an effective prevention in the deformation of the terminals.
Specifically, this structure has a problem as shown below. When the terminals of the connector are arranged in a staggered manner due to a layout reason any of the comb teeth of the first comb teeth-like terminal arrangement plate and the comb teeth of the second comb teeth-like terminal arrangement plate cannot be straightly introduced to the area in which the above-mentioned terminals are provided As a result, when the above-mentioned tip end section of the terminal is press-fitted into the insertion hole of the substrate, the terminal cannot be positioned precisely, making it difficult to press-fit the tip end section of the terminal into the insertion hole of the substrate properly. In the case of a so-called press fit connector, in particular, by which the terminals and the substrate can be connected only by press-fitting the terminal into the insertion hole of the substrate without requiring soldering, when press-fitting the terminal into the above-mentioned insertion hole, an extremely large press-fitting force is required. Thus, an insufficiently-positioned terminal causes deformation of the terminal such as bending and slanting.


A microwave waveguide apparatus for generating plasma includes a waveguide which has first and second ends and propagates microwave from input end such that the microwave propagates from the first end to the second end, a circulator device having a first port, a second port coupled to the first end, and a third port coupled to the second end, the circulator device being structured such that the microwave is received at the first port, propagates from the second port to the first end, is received at the third port from the second end and is returned toward the input end, and a matching device which is interposed between the input end and the circulator device and reflects part of the microwave received at the third port and returned toward the input end to the first port. The waveguide has a slot-hole extending along the microwave propagation direction in the waveguide.

1. Field of the Invention
The present invention relates to a microwave waveguide apparatus, a plasma processing apparatus and a plasma processing method.
2. Description of Background Art
Regarding an apparatus that generates plasma from gas using a microwave supplied to a waveguide, Japanese translation of PCT Laid-Open Patent Application No. 2002-526903 describes a plasma generator having a linear waveguide in which a long, narrow slot penetrating a wall in the waveguide is formed, and a microwave power source connected to this waveguide. In such a plasma generator, a microwave power source supplies microwave power to the waveguide to generate plasma in a slot.
Also, Japanese Laid-Open Patent Application No. 2012-64444 describes a plasma-generating apparatus structured to have a rectangular waveguide that is connected to a microwave-generating device and is long in a transmission direction of a microwave; a gas-supply device that supplies a processing gas into the rectangular waveguide; and an antenna unit that has multiple rectangular slot holes formed on one surface of the rectangular waveguide and that discharges plasma generated in the slot holes to the outside. In such a device, a standing wave is formed in the rectangular waveguide, and the slot holes that discharge plasma to the outside of the rectangular waveguide are formed at positions of a microwave corresponding to antinode portions of a standing wave in the antenna unit.
Japanese Patent No. 4900768 describes a plasma-generating apparatus having an annular resonator that resonates a traveling wave, and multiple applicators coupled to multiple couplers that direct the microwave and guide the microwave to a plasma-generating chamber (FIG. 1). In such an apparatus, as FIG. 2 shows, a directional coupler that guides a reflected wave propagated into the annular resonator to a dummy load is provided between an introduction waveguide and the annular resonator. The entire contents of these publications are incorporated herein by reference.

Microwave waveguide apparatus, plasma processing apparatus and plasma processing method

NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY


An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for the bus has passed without participants. If there are no participants for arbitration, the SCSI initiator eliminates arbitration by asserting SEL and issuing initiator/target IDS. If any other device attempts to arbitrate at this time, the device sees SEL asserted and does not attempt to participate in arbitration.

1. Technical Field
The present invention is directed generally toward a method and apparatus for improving performance in a SCSI (small computer system interface) topology; more particularly, the present invention is directed toward improving performance by eliminating the arbitration phase in some circumstances.
2. Description of the Related Art
The need for faster data access in SCSI topologies has grown due to faster processors and enhanced PCI bus architectures that increase data transfer rates using wider data paths and improved clock rates. During the time when the system is running, the SCSI bus is generally either active or idle. If active, the bus is busy transmitting data from one device to another; if idle, it is available for a device to begin sending a command or data. When a device decides it wants to use the bus, it "bids" for control of the bus. It is also possible that other devices on the bus will want to use it at the same time, so they too may "bid" for control. A specific method is used to resolve these requests and decide which device gets to use the bus first; this is based to some extent on the devices' respective priority levels. This process is called arbitration.
While arbitration works fine in regular SCSI configurations, it introduces overhead. During the time that arbitration is going on, no data is being transferred on the bus, so it makes sense that doing this faster will allow improved performance of the entire SCSI subsystem. To this end, the SPI-3 standard defined a feature that reduces the overhead required for arbitration. This feature is called quick arbitration and selection or QAS.
QAS reduces bus overhead by reducing the time required to implement arbitration on the bus compared to normal arbitration. When the feature is used, a device waiting for the bus can grab it more quickly after the last device on the bus sends the signal that it is done, without having to begin a normal arbitration process. Provision is made in the specification to ensure that one device does not "dominate" the bus by "unfairly" blocking out other devices that may be of a lower priority or may not implement QAS.
In current SCSI systems, SCSI applications must create an initiator/target connection through arbitration and selection. The normal arbitration period on a SCSI bus can only occur after a bus clear condition. The term "bus clear" refers to a point in time on the SCSI bus when the signal BSY (busy) and SEL (select) are both deasserted for a period of time (e.g., 400 ns in some current systems) indicating the bus is "free," plus an additional time span (e.g., another 800 ns) indicating the bus is "clear." After waiting for the bus clear condition, the bus is idle and normal arbitration can start. After the normal arbitration period has completed (e.g., 2.4 microseconds later in many current systems), the selection phase begins. After the connection is established, the data transfer takes place and the drive either does a QAS disconnect or a normal disconnect followed by a bus free condition.
Unless another generation of SCSI topology is developed, performance of SCSI interfaces must be improved by increasing the efficiency and speed with which current topologies perform their duties. Therefore, current data processing systems would benefit from improved data transfer rates that deliver valid data sooner after a data request, and from the elimination of some time usage associated with arbitration after bus inactivity.

Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology


A system and method processes visual information including at least one object in motion. The visual information is processed by locating at least one spatial edge of the object, generating a plurality of spatio-temporal gradients for the at least one spatial edge over N frames, and then generating motion blur images from the spatio-temporal gradients. A regression analysis is performed on the motion blur images to determine direction of motion information of the object, and scene activity vectors are then generated for the N frames based on the direction of motion information. An event is detected in the visual information based on the scene activity vectors.

One or more embodiments relate to processing visual information.
Processing techniques have been developed to detect features in video using, for example, Mixture-of-Gaussian (MOG), Hierarchical Bayesian, and Hidden Markov models. The features are located in one frame and then an attempt is made to find matching features in a subsequent adjacent frame or by performing block matching between adjacent frames. These techniques have proven to be time-consuming because of computational complexity and also have been found to be prone to errors as a result of lighting changes, occlusion, rotation, scale difference and other effects.
Additionally, these techniques perform a bottom-up approach to feature finding. Such an approach locates features based on regions, which, for example, may be pre-chosen fixed blocks of n×n size. A bottom-up approach also detects, segments, and tracks one feature and then attempts to detect, segment, and track increasingly greater numbers of features. When the number of features becomes large, objects cannot be detected or tracked with any degree of accuracy. Bottom-up approaches, therefore, have proven unsuitable for many applications.

System and method for processing visual information for event detection


To provide a cleaning method for an etching apparatus for a metal film that efficiently removes an etching residue deposited in an etching process chamber, assures the reproducibility of the etching performance, and keeps the etching process chamber in a low-dust-emission condition.

1. Field of the Invention
The present invention relates to a method of cleaning a dry-etching apparatus. In particular, it relates to a cleaning method for an etching apparatus for a semiconductor device, the method being provided to assure that the etching rate of a film to be etched, the in-plane uniformity of etching rate of the film to be etched and the etching rate ratio (selectivity rate) between the film to be etched and a mask material or an underlying material are less variable and reproducible and to keep a stable apparatus condition by minimizing emission of foreign matters in the apparatus.
2. Description of the Related Art
In manufacturing processes of semiconductor devices, etching techniques are used for forming fine patterns. The etching techniques are classified into the dry etching type and the wet etching type, and the dry etching technique has recently become mainstream due to its high workability. Known dry etching techniques include microwave plasma etching and reactive ion etching, both of which involve introducing an etching gas to a vacuum vessel and exciting the etching gas into a plasma using cyclotron resonance or high-frequency electric field, thereby etching a film to be etched.
On the other hand, as an element wiring material for semiconductor devices, aluminum (Al) is used. With the recent increase of the packaging density of semiconductor devices, the elements are becoming smaller and smaller, and materials that are more chemically stable and have lower resistances are attracting more attention. For example, gold (Au) is considered as an alternative to aluminum. Besides, a film of platinum (Pt), silver (Ag), titanium (Ti), titanium nitride (TiN), titanium oxide (TiO) or an aluminum alloy or a stack of films of these materials may be used. In addition, the device structure is becoming thinner, and the photoresist (PR), the oxide (SiO2) film, the titanium (Ti) film, and the titanium nitride (TiN) film serving as a mask, and the oxide (SiO2) film and an organic film serving as a base material are required to have a high selectivity.
In order to achieve a high selectivity, etching may be conducted using, as an etching gas, a mixed gas produced by adding at least one of methane (CH4), ethane (C2H6), acetylene (C2H2), dichloromethane (CH2Cl2), dibromomethane (CH2Br2), chloromethane (CH3Cl), bromomethane (CH3Br) and fluoromethane (CH3F) to at least one of chlorine (Cl2), boron trichloride (BCl3) and hydrogen bromide (HBr).
However, since a hydrocarbon (CH)-based gas is used as the additive gas, a hydrocarbon (CH)-based product is deposited in the apparatus during etching of the film to be etched. In addition, an etching residue of the film to be etched and a reaction product as a result of reaction of the film to be etched and the etching gas are not discharged and are deposited in the apparatus. Such deposite piles all cause reduction of etching performance and occurrence of a foreign matter and, therefore, have to be removed as required.
In order to remove the deposite pile in the vacuum vessel, dry cleaning that involves plasma processing or wet cleaning that involves opening the vessel to the atmosphere may be utilized. Typically, from the viewpoint of the productivity of the semiconductor device, the dry cleaning, which can be done in a shorter time, is selected. For example, known conventional dry cleaning techniques are as follows:
(1) a method of removing a carbon-based deposite pile (see Japanese Patent Publication No. 6-53193 or Japanese Patent Publication No. 9-36085, for example); and
(2) a method of removing a deposite pile of aluminum (Al), titanium nitride (TiN) or an aluminum alloy (see Japanese Patent Publication No. 2000-12515, for example).
The methods described above are to remove the deposite pile in the vacuum chamber by plasma processing using a selected cleaning gas. There has not been disclosed any method for removing a deposite pile formed when a film of gold (Au), platinum (Pt), silver (Ag), titanium (Ti), titanium nitride (TiN), titanium oxide (TiO), aluminum (Al) or an aluminum alloy or a stack of the films is etched using a mixed gas produced by adding at least one of methane (CH4), ethane (C2H6), acetylene (C2H2), dichloromethane (CH2Cl2), dibromomethane (CH2Br2), chloromethane (CH3Cl), bromomethane (CH3Br) and fluoromethane (CH3F) to at least one of chlorine (Cl2), boron trichloride (BCl3) and hydrogen bromide (HBr).

Abstract: Each time one workpiece with a metal film is etched (S1), the interior of the vacuum chamber is cleaned by replacing the workpiece with a dummy substrate (S2), performing a first step of plasma processing using oxygen (O2) and carbon tetrafluoride (CF4) to remove a carbon-based deposit pile (S3), and performing a second step of plasma processing using boron trichloride (BCl3) and chlorine (Cl2) to remove a residue that could not be removed by the first step and an etching residue of the metal film (S4).


This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.

1. Field of the Invention
This invention relates generally to the structure and fabrication process of MOSFET transistors. More particularly, this invention relates to a novel and improved MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches.
2. Description of the Prior Art
In a conventional vertical power MOSFET fabrication process, the requirement to form a high concentration p-region with sufficient depth below the n.sup.+ source region in order to prevent an avalanche breakdown to occur at the junction directly underneath the n.sup.+ source region generates an intrinsic limitation in shrinking the cell size. This limitation can be well appreciated by referring to a standard trenched MOSFET transistor as that shown in FIG. 1A. This trenched power MOSFET has a built-in parasitic bipolar structure with the P-body, N.sup.+ source and drain regions formed as a base, emitter and collector respectively of the parasitic bipolar. During an avalanche breakdown, due to a high current and voltage of the MOSFET, the bipolar may be incidentally turned on. As an undesirable consequence of this incidental turning on of the parasitic bipolar, the drain voltage of the MOSFET may "snap back" to or below the open-base breakdown voltage of the bipolar transistor. Due to the incidental turning on of the bipolar, as that shown in FIG. 1B, a hole-current during avalanche flows laterally underneath the n.sup.+ source region which may cause permanent damages to the transistor. Therefore, an incidental turning on of the parasitic bipolar must be suppressed and the hole-current laterally flows underneath the n.sup.+ source region must be re-directed to protect the MOSFET under high current and high voltage conditions. A method to protect a MOSFET transistor from this type of damages is to form a high concentration deep-P region, e.g., a p-short region, below the n.sup.+ source region as that shown in FIG. 1C. The deep-P region serves to reduce the current gain of the parasitic bipolar and also provides a vertical path for the hole-current to flow to the source metal contact.
A high concentration deep-P region formed with greater depth under the source region imposes several restrictions on the structure and manufacture process of a MOSFET device due to a relative large depth and lateral diffusion of the deep-P region. First, an alignment step and long diffusion thermal cycle are required to form the deep-P region at the center of the cell as that shown in FIG. 1C. The requirements of alignment and the longer thermal cycles in forming the deep-P region increase the complexity and costs of the MOSFET manufacture. Secondly, the cell size cannot be easily reduced due to the lateral diffusion of the deep-P region when this region is formed with greater depth.
Therefore, there is still a need in the art of transistor fabrication, particularly in MOSFET design and fabrication, to provide a structure and fabrication process that would remove these limitations with improved device structure and fabrication processes.


Novel, binder-free compacted forms of 1,3-dihalo-5,5-dimethylhydantoins in which one halogen atom is chlorine and the other is a bromine or chlorine atom are produced and used for microbiological control in aqueous media and water.

This invention relates to the compacting of 1,3-dihalo-5,5-dimethylhydantoins other than 1,3-dibromo-5,5-dimethylhydantoin without use of binders, and to the novel compacted forms so produced, which, by virtue of their characteristics and physical properties, are superlative biocidal water-treating agents.
As used herein the terms xe2x80x9chalogenxe2x80x9d, xe2x80x9chalogenatedxe2x80x9d, and xe2x80x9chaloxe2x80x9d are with reference to bromine or chlorine, or both.
1,3-Dihalo-5,5-dialkylhydantoins, especially 1,3-dibromo-5,5-dimethylhydantoin, 1,3-dichloro-5,5-dimethylhydantoin, 1-bromo-3-chloro-5,5-dimethylhydantoin, and 1-chloro-3-bromo-5,5-dimethylhydantoin, or mixtures of two or more of them, are biocidal agents for use in water treatment. These compounds are, in general, sparingly soluble in water. Thus typically they are supplied in solid forms such as granules, tablets, or briquettes, and delivered into the water being treated by means of water flow through an erosion feeder.
Over the years considerable effort has been devoted to the search for improved methods for producing such compounds. In U.S. Pat. No. 2,971,960 N-brominated compounds such as N-brominated 5,5-di-lower-alkyl hydantoins are formed by treating the alkylhydantoin with bromine in an acidic aqueous solution containing hypochlorite, preferably at a pH between 1 and 4. However, the method of choice has been halogenation of the alkylhydantoin in a basic aqueous medium. Almost invariably the halogen has been introduced into, or formed in situ in, the aqueous medium containing the alkylhydantoin. See in this connection U.S. Pat. Nos. 2,398,598; 2,779,764; 2,868,787; 2,920,997; 2,971,959; 3,121,715; 3,147,259; 4,532,330; 4,560,766; 4,654,424; 4,677,130; 4,745,189; PCT Publication No. WO 97/43264, published 20 November 1997; Orazi and Meseri, Anales Assoc. Quim. Argentina, 1949, 37, 192-196; Orazi and Meseri, Anales Assoc. Quim. Argentina, 1950, 38, 5-11; Corral and Orazi, J. Org. Chem., 1963, 23, 1100-1104; Jolles, Bromine and its Compounds, Ernest Benn, London, 1966, p. 365; and Markish and Arrad, Ind. Eng. Chem. Res., 1995, 34, 2125-2127.
The N,Nxe2x80x2-dihalogenated dialkylhydantoin products formed by such processes are formed as powdery solids. For use in many applications the dry powders need to be converted into larger forms such as granules, tablets, or briquettes. This in turn has presented problems associated with providing densified or compacted products with sufficient strength to withstand the physical stresses encountered in packaging, conveying, handling, shipping, storage, and use. The nature of these problems have been described, for example, in U.S. Pat Nos. 4,532,330; 4,560,766; 4,654,424; 4,677,130; 4,745,189; and 5,565,576. The approaches described in these patents for alleviating one or more such problems involve use of additional or other materials. Thus in U.S. Pat. Nos. 4,532,330 and 4,621,096, halogenated dimethylhydantoins are mixed with calcium chloride and water, and the mixture is compacted by compression into the desired shape. In U.S. Pat. Nos. 4,560,766 and 4,654,424, halogenated ethylhydantoins are used instead of halogenated dimethylhydantoins and are compacted as such, or are melt blended with halogenated dimethylhydantoins. U.S. Pat. No. 4,677,130 describes forming dry blends of the halogenated dimethylhydantoin with particulate alkali metal or alkaline earth metal salt followed by compression to form a compacted product such as a tablet. PCT Publication No. WO 97/43264 describes the use of 1,3-bromochloro-5-methyl-5-propyl-hydantoin as a binder in making compacted forms of halogenated hydantoins.
U.S. Pat. No. 4,745,189 describes formation of halogenated dimethylhydantoinby halogenating the hydantoin in an aqueous mixture under alkaline conditions in the presence of a halogenated alicyclic organic compound such as dichloromethane. The Examples of the patent describe the formation of N,Nxe2x80x2-bromochloro-5,5-dimethylhydantoin products comprised of large particles.
U.S. Pat. No. 4,560,766 teaches that halogenated dimethylhydantoinper se cannot be used for making low-dust powders, granules, tablets, flakes, compacted forms, cast forms, and carrier-coated products without the aid of a binder.
It would be of great advantage to provide particulate 1,3-dihalo-5,5-dimethylhydantoins useful for making granules, tablets, flakes, compacted forms, cast forms, and carrier-coated products without the aid of a binder, and without use in the production process of any organic halogen compound such as dichloromethane.
This invention involves the discovery, inter alia, that 1,3-dihalo-5,5-dimethylhydantoins other than 1,3-dibromo-5,5-dimethylhydantoin can be compacted without need of a binder of any kind.
Accordingly, this invention provides, inter alia, novel, binder-free, pressure compacted articles of 1,3-dihalo-5,5-dimethylhydantoins other than 1,3-dibromo-5,5-dimethylhydantoin, and methods of producing such compacted articles from such binder-free 1,3-dihalo-5,5-dimethylhydantoins.
The 1,3-dihalo-5,5-dimethylhydantoins other than 1,3-dibromo-5,5-dimethylhydantoin are 1,3-dichloro-5,5-dimethylhydantoin, 1-bromo-3-chloro-5,5-dimethylhydantoin, and 1-chloro-3-bromo-5,5-dimethylhydantoin, and mixtures thereof. For ease of reference, such compounds (excluding 1,3-dibromo-5,5-dimethylhydantoin) are sometimes referred to hereinafter as xe2x80x9chalogenated hydantoinsxe2x80x9d. Even though devoid of a binder, pressure compacted articles formed from particulate halogenated hydantoins have remarkable crush strength. In contrast, so far as is known, all previously known particulate forms of virgin 1,3-dibromo-5,5-dimethylhydantoin cannot be pressure compacted into tablets When attempts were made to form such tablets, it was found that when released from a tableting die, the compacted shape would xe2x80x9cdelaminatexe2x80x9d, meaning that the compacted agglomerate would break apart into smaller pieces.
Moreover, when compacted without a binder, granules, tablets, briquettes, or other relatively small shapes formed from the halogenated hydantoins have excellent physical properties for use in water-treatment systems. The shapes erode at slow, but essentially constant, rates when maintained in a constant flow of water. They withstand the customary physical stresses encountered in packaging, conveying, handling, shipping, storage, and use. The compacted solid forms of this invention produced directly from the 1,3-dihalo-5,5-dimethylhydantoins other than 1,3-dibromo-5,5-dimethylhydantoin have excellent crush strength even when formed without a binder.
While many ways of producing halogenated hydantoins are known, the best way of producing them involves process technology fully described in commonly-owned copending application Ser. No. 09/484,844, referred to above.
In converting the halogenated hydantoins into granules, conventional processing equipment can be used under the usual operating conditions. Typically, the finely divided halogenated hydantoin is compressed into sheet form by means of a roll compactor. This sheet in turn is broken up into small granules by a mechanical device, such as a Chilsonator(copyright) breaker (The Fitzpatrick Company, Elmhurst, Ill.). The granules are then classified by screening into the desired size range. Undersized granules are typically recycled to the roll compactor, whereas oversized granules are recycled to the breaker device.
The formation of tablets and other compressed shapes such as briquettes from the halogenated hydantoins can also utilize known processing equipment and, for the most part, known procedures. However, in conducting compaction of the virgin halogenated hydantoins particulate solids in the absence of a binder, it is important that the compaction pressure be sufficient to induce plastic deformation and interparticulate binding of the particles. At the same time, the compaction pressure should not be so great as to produce a compacted product which delaminates on expulsion from the die. Typically, suitable compaction pressures in the practice of this invention will fall within the range of about 1000 to about 30,000 psi, and preferably in the range of about 5000 to about 25,000 psi. Such compaction can be conducted using, for example, a rotary tableting press operated at conventional rotational speeds, e.g., about 20 rpm. Another method for accomplishing the compaction is by means of pressure extrusion through a die orifice, while concurrently shearing the extrudate to produce compacted shapes of the desired size. In such operations, the compaction pressures within the die should be sufficient to induce plastic deformation and interparticulate binding of the particles, but insufficient to produce a compacted product which, when extruded, undergoes an elastic recovery of a magnitude that causes delamination of the compacted extrudate.
In operations conducted on a small scale using manually filled dies, 1,3-dichloro-5,5-dimethylhydantoin and N,Nxe2x80x2-bromochloro-5,5-dimethylhydantoin having an average particle sizes of about 108 microns and about 324 microns, respectively, have been successfully compacted into tablets without resorting to use of any binder. The tablets when released from the dies were intact and exhibited no visual surface imperfections.
The halogenated hydantoins can also be directly converted without use of a binder into whole briquettes utilizing conventional briquetting rolls operated under conventional conditions. In such operations, pressures in the range of about 1000 to about 30,000 psi are typical; more preferably, the pressures are in the range of from about 5000 to about 25,000 psi. As in the case of pressure compaction of tablets, the compaction pressure should be sufficient to induce plastic deformation and interparticulate binding of the particles, but insufficient to produce a compacted product which undergoes an elastic recovery of a magnitude causing delamination of the compacted article on exiting the rolls.
The compaction operations, whether performed in a die, by extrusion through an orifice of a die, or by roll compaction is typically conducted at ambient room temperatures. However, it is possible to either cool or warm the material being subjected to compaction. This can be accomplished either by refrigerating or directly heating the product before introducing it into the compaction apparatus, or by chilling or heating the apparatus itself such as, for example, by using rolls equipped with heating or cooling coils or other means for effecting temperature regulation. The compaction operation itself can, and in many cases does, result in generation of heat within the compacted shape. Generally speaking, the compaction operations pursuant to this invention can be performed at temperatures in the range of about 5 to about 80xc2x0 C.
It will be understood and appreciated that departures from the numerical ranges given herein for pressures and temperatures are permissible in the practice of this invention, whenever such departures are deemed necessary or desirable, provided only that such departures do not materially affect in an adverse manner the processing or the properties of the product being produced.
Typically, compacted products of this invention, such as tablets, briquettes, and pucks, formed without use of a binder, will have a crush strength in the range of from about 75 to about 200 pounds per inch of thickness. Thus, it is now possible to provide binder-free compacted products having the strength needed to withstand the physical stresses encountered in packaging, conveying, handling, shipping, storage, and use.
When converted into tablets, briquettes, pucks, and other compacted shapes with use of a suitable binder, the halogenated hydantoins form compacted articles of even greater crush strength. Markedly superior binding agents for use with the halogenated hydantoins are the micronized polyolefins waxes and the micronized polyfluorocarbon waxes described in commonly-owned co-pending application Ser. No. 09/487,816, filed Jan. 18, 2000.
Granules, tablets, and briquettes produced from halogenated hydantoins are of particular utility as biocidal agents for use in swimming pools, spas, toilet bowl cleaners, cooling towers, air washer systems, wastewater, pulp and paper processing operations, oil field applications, and decorative fountains.
In the practice of this invention, the halogenated hydantoin particulate solids used in compaction without a binder are pressure-compactible halogenated hydantoin particulate solids. By this is meant that upon application of pressure to the virgin material in a die, a shape is produced that can be removed from the die without breakage occurring. Experimental evidence to date indicates that 1,3-dichloro-5,5-dimethylhydantoin having an average particle size even as small as about 100 microns or perhaps even less can be successfully pressure compacted into shape-retentive articles. In the case of N,Nxe2x80x2-bromochloro-5,5-dimethylhydantoins the available experimental evidence indicates that somewhat larger average particle size product may possibly be required in order to produce shape-retentive articles without use of a binder. The particle size distributions of the halogenated hydantoin may also contribute to the efficacy with which such iparticulate solids can be compacted. Thus in any situation where the pressure compactibility of a given supply of halogenated hydantoin has not been established, it is desirable to perform a preliminary test to determine its suitability in forming a compacted article pursuant to this invention.
Thus, in a preferred group of 1,3-dichloro-5,5-dimethylhydantoin solids in which the average particle size is in the range of about 100 to about 300 microns, 50% of the particles have a particle size of at least about 70 microns.
In a particularly preferred group of 1,3-dichloro-5,5-dimethylhydantoin solids in which the average particle size is in the range of about 100 to about 300 microns, 10 percent of the particles have a particle size of at least about 180 microns, 25 percent of the particles have a particle size of at least about 120 microns, 50 percent of the particles have a particle size of at least about 70 microns, 75 percent of the particles have a particle size of at least about 35 microns, and 90 percent of the particles have a particle size of at least about 20 microns.
In a preferred group of N,Nxe2x80x2-bromochloro-5,5-dimethylhydantoin solids in which the average particle size is in the range of about 250 to about 350 microns, 50% of the particles have a particle size of at least about 170 microns.
In a particularly preferred group of N,Nxe2x80x2-bromochloro-5,5-dimethylhydantoin solids in which the average particle size is in the range of about 250 to about 350 microns, 10 percent of the particles have a particle size of at least about 800 microns, 25 percent of the particles have a particle size of at least about 400 microns, 50 percent of TA0 the particles have a particle size of at least about 170 microns, 75 percent of the particles have a particle size of at least about 60 microns, and 90 percent of the particles have a particle size of at least about 20 microns.
As also described above, this invention provides products in which one or more of the halogenated hydantoins are converted into granules, tablets, briquettes, pucks, or any other larger sized product, however produced. Typical operations of this type have been described above. Other procedures include, for example, mixing the solid halogenated hydantoin with other dialkylhydantoins and if desired, heat fusing the resultant mixtures, such as described in U.S. Pat. Nos. 4,560,766 and 4,654,424. Similarly, the halogenated hydantoins can be utilized in combination with 1,3-bromochloro-5-methyl-5-propylhydantoin as a binder as described in published PCT Application WO 97/43264.
While there are no hard and fast rules governing differentiation with respect to size among granules, tablets, briquettes, and pucks, typically granules are regarded as being particles ranging in size from about 80 to about 3 U.S. standard mesh size. Tablets typically fall in the range of from about 0.5 to about 1.0 inch in diameter and about 0.5 to about 1.0 inch in thickness. Briquettes will normally range in size from about 0.5 to about 4.0 inches in length, from about 0.5 to about 4.0 inches in width, and from about 0.5 to about 2.5 inches in thickness. Pucks are normally disc-shaped objects having a diameter up to about 3.0 inches and a thickness in the range of about 0.5 to about 1.0 inch. It will be understood and appreciated however, that these dimensions are not intended to unduly limit the scope of this invention.
If desired, the halogenated hydafitoins can be formulated with suitable excipients such as binders, lubricants, disintegrants, and mold release agents. Other optional ingredients which may be used in the formulation of compacted products from these halogenated hydantoins include fragrances, stabilizers, corrosion inhibitors, dyes, other biocidal agents, surfactants, effervescents, diluents, builders, chelating agents, and the like. Such ancillary materials should of course be compatible with the halogenated hydantoin and not interfere in any material way with the performance characteristics of the halogenated hydantoin. The amount(s) of such ancillary materials used should of course be sufficient to serve the purpose for which it is, or they are, being used. At the same time, the amount used should not materially detract from the physical, mechanical, or performance properties of the formulated product.
As indicated above, the halogenated hydantoins can be compacted with or without use of a binder. In the practice of this invention it is preferred to conduct the compaction in the absence of a binder. Commonly-owned co-pending application Ser. No. 09/487,816, filed Jan. 18, 2000, relates in part to the compaction of the halogenated hydantoins using novel binders described therein.
The following Examples are presented to illustrate the practice of, and advantages made possible by, this invention. These Examples are not intended to limit, and should not be construed as limiting, the scope of this invention to the particular operations or conditions described therein.
All particle size determinations referred to in the following Examples were determined by use of a Coulter(copyright) LS Particle Size Analyzer. The analyzer was equipped with an LS 230 small volume module and a Fraunhofer PIDS (Polarization Intensity Differential Scattering) detector switched to the xe2x80x9cOnxe2x80x9d position. The determinations were performed at room temperature with a run time of approximately 1 minute per sample. Prior to conducting the particle size determination, and whenever the sample appeared to contain particles adhering to each other, the sample was subjected for 15xc2x11 seconds to sonication using a Sonicor Model SC-100T apparatus to ensure that the particle size measurements were on individual particles of the product, rather than temporarily agglomerated particles.

Binder-free compacted forms of 1,3-dihalo-5,5-dimethylhydantoins


A nonvolatile semiconductor memory device includes memory cell, charge buildup damage reducer and damage reducer controller. The memory cell includes floating and control gates formed over a semiconductor substrate. The damage reducer is connected to the control gate. The controller is connected to the damage reducer. The damage reducer controls a potential level at the control gate so that the potential level falls within a predetermined voltage range even if charge buildup occurs in the control gate during a metallization process. And the controller allows no current to flow through the damage reducer while the memory cell is being written, read or erased.

The present invention relates to a nonvolatile semiconductor memory device, and more particularly relates to a non-volatile semiconductor memory device including gate electrodes in two layers, i.e., control and floating gates, and functioning as a flash memory.
Memories so constructed as to erase specified data electrically at a time, like a flash memory, have been in higher and higher demand these days.
As is well known in the art, various factors make it difficult for a flash memory to ensure high reliability. A so-called xe2x80x9ccharge buildup damagexe2x80x9d is one of those factors that decrease the reliability of a flash memory. The charge build-up damage is done on the tunnel insulating film of a flash memory during a metallization process to fabricate the memory. More specifically, when metal interconnects are formed by dry etching and patterning processes, positive or negative electric charges are likely accumulated in the interconnects. And if the quantity of those charges accumulated is huge, the control gate of the memory will have a potential with an outstandingly large absolute value, thus placing an excessively intense electric field on the tunnel insulating film. Should damage of that type be done on the tunnel insulating film, the reliability of a memory cell of the flash memory would decrease considerably.
For that reason, methods for reducing the charge buildup damage during a metallization process have been researched and developed vigorously in the pertinent art.
Hereinafter, one such method for reducing the charge buildup damage in a metallization process will be described.
FIG. 13 illustrates a memory cell for a flash memory (which will be herein called a xe2x80x9cflash memory cellxe2x80x9d simply) and a known charge buildup damage reducer. As shown in FIG. 13, a flash memory cell 101 has its control gate connected to a word line decoder 102 and to the cathode of a charge buildup damage reducer 103. The charge buildup damage reducer 103 is implemented as a backward diode with a grounded anode.
FIG. 14 illustrates a cross-sectional structure for the damage reducer 103. As shown in FIG. 14, a p-well 111 is defined in the upper part of a p-type semiconductor substrate 110. Over the p-well 111, n- and p-type doped regions 113 and 114 are defined and electrically isolated from each other by an isolation film 112. The n-type doped region 113 is connected to the control gate of the flash memory cell 101, while the p-well 111 and p-type substrate 110 are grounded by way of the p-type doped region 114.
FIG. 15 illustrates a current-voltage (I-V) characteristic of the damage reducer 103 (i.e., backward diode). In FIG. 15, the abscissa represents the voltage VCG applied to the control gate, while the ordinate represents the current Idiode flowing from the n-type doped region 113 into the p-well 111 in the backward diode 103. As shown in FIG. 15, if the voltage VCG applied to the control gate is V11 (e.g., about xe2x88x920.6 V) or less, a forward bias is applied to the backward diode 103. As a result, a current starts to flow through the backward diode 103. On the other hand, if the voltage VCG applied to the control gate is V12 (e.g., about 15 V) or more, breakdown occurs at the backward diode 103 and a current also starts to flow through the diode 103. That is to say, while the voltage VCG is between V11 (about xe2x88x920.6 V) and V12 (about 15 V), no current flows through the backward diode 103.
Next, it will be described how the known charge buildup damage reducer operates.
In a gate grounded erase method, in which electrons are removed from the floating gate by applying 0 V and 12 V to the control gate and source electrode, respectively, during erasing, the voltage applied to the control gate is always between 0 V and 12 V irrespective of the mode of operation the flash memory cell. No current flows through the backward diode within this voltage range, and the operation of the flash memory cell is not interfered with.
On the other hand, during the metallization process, positive or negative electric charges build up in the control gate of a flash memory cell. However, the known charge build-up damage reducer 103, or the backward diode 103, is connected to the control gate of the flash memory cell 101. Accordingly, if the voltage applied to the control gate is V11 or less or V12 or more, the charges built up flow out of the control gate. In this manner, the damage done on the tunnel insulating film can be reduced and the considerable decrease in reliability of the flash memory is avoidable.
The known method of reducing the charge buildup damage in a metallization process, however, has the following two drawbacks.
Firstly, a negative voltage with a large absolute value cannot be applied to the control gate. As a flash memory cell has been downsized recently, it becomes more and more necessary to reduce the positive high voltage (e.g., about 12 V) applied to the source electrode during an erase operation. Various techniques of reducing the source voltage have been proposed. One of those methods is a gate negative voltage erase method as represented in the following Table 1:
During a write operation, 12 V, 5 V, 0 V (i.e., ground potential) and 0 V are applied to the control gate, drain, source and p-well 111 of a selected flash memory cell, respectively. In this combination of applied voltages, channel hot electrons are created near the drain and are injected into the floating gate. After the write operation is over, the flash memory cell has a threshold voltage of about 6 V. As for non-selected flash memory cells on the other hand, 0 V is applied to the control gate thereof and the drain thereof is opened, thereby preventing those cells from being written erroneously.
During an erase operation, xe2x88x928 V, 5 V and 0 V are applied to the control gate, source and p-well 111 of the selected flash memory cell and the drain thereof is opened. In this combination of applied voltages, a Fowler-Nordheim (FN) tunneling current flows from the floating gate into the source and the electrons are removed from the floating gate. After the erase operation is over, the flash memory cell has a threshold voltage of about 2 V. As for the non-selected flash memory cells on the other hand, 0 V is applied to the control gate and source thereof, thereby preventing those cells from being erased erroneously.
During a read operation, 5 V, 1 V, 0 V and 0 V are applied to the control gate, drain, source and p-well 111 of the selected flash memory cell, respectively. In this combination of applied voltages, where the memory cell selected has been erased, a current flows from the drain toward the source thereof. On the other hand, if the selected cell has been written, no current flows through the cell. Accordingly, by sensing a difference in the amount of current flowing from the drain to the source thereof, it is possible to determine whether the memory cell has been erased or written. As for non-selected flash memory cells on the other hand, the ground potential is applied to the control gate thereof and the drain thereof is opened, thereby preventing those cells from being read erroneously.
However, the known charge buildup damage reducer for metallization process is not applicable to a flash memory cell to which this gate negative voltage erase method is supposed to be applied. This is because the negative voltage of xe2x88x928 V applied to the control gate thereof during the erase operation belongs to the voltage range in which the backward diode is forward biased, and cannot be applied to the control gate even when the damage reducer is used.
Secondly, the decrease in reliability of a flash memory cell is not completely avoidable because a positive high voltage of about 15 V might be applied to the control gate during a metallization process. Specifically, the known charge buildup damage reducer uses a backward diode, so a voltage between V11 (about xe2x88x920.6 V) and V12 (about 15 V) may be applied to the control gate. This voltage of about 15 V does not degrade the reliability of the flash memory so seriously but is so high as to allow a large FN tunneling current to flow through the tunnel insulating film thereof. Accordingly, the flash memory might have its reliability affected non-negligibly.
For these reasons, the known charge buildup damage reducing method for metallization process is not applicable to a flash memory utilizing the gate negative voltage erase method. Also, even if that damage reducing method is applied to a cell utilizing the erase method, the two problems mentioned above should occur and the charge buildup damage could not be reduced sufficiently during the metallization process.
It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device to which the gate negative voltage erase method and the charge buildup damage reducing method for metallization process are both applicable effectively.
To achieve this object, while a memory cell is operating, the damage reducer, which is a type of electrostatic discharge (ESD) shielding so to speak, is disabled according to the present invention.
Specifically, an inventive nonvolatile semiconductor memory device includes memory cell, charge buildup damage reducer and damage reducer control means. The memory cell includes floating and control gates formed over a semiconductor substrate. The damage reducer is connected to the control gate. And the control means is connected to the damage reducer. The damage reducer controls a potential level at the control gate so that the potential level falls within a predetermined voltage range even if charge buildup occurs in the control gate during a metallization process. And the control means allows no current to flow through the damage reducer while the memory cell is being written, read or erased.
The inventive memory device can adopt the gate negative voltage erase method and yet can reduce the charge buildup damage during a metallization process. Accordingly, the memory cell can operate at a reduced voltage.
In one embodiment of the present invention, the damage reducer is preferably a diode that includes first and second electrodes. The first electrode of the diode is preferably connected to the control gate. And the control means is preferably connected to the second electrode of the diode and preferably changes a voltage applied to the second electrode of the diode depending on whether the memory cell is being written, read or erased.
In this particular embodiment, the diode preferably includes: a well of a first conductivity type, which is formed in the substrate and used as the second electrode; and a doped region of a second conductivity type, which is defined in the well and used as the first electrode.
More particularly, the first and second conductivity types may be n- and p-types, respectively. And the control means may set the potential level at the n-well to a value equal to or greater than each voltage applied to the control gate while the memory cell is being written, read or erased.
In such an embodiment, the diode is connected in the forward direction. Accordingly, while the diode is reverse biased with respect to the control gate, no current flows through the diode and the device is compatible with the gate negative voltage erase method. Also, during a write operation, for example, a positive bias is applied to the control gate. However, since the control means sets the potential level at the n-well to a value equal to or greater than the positive bias, no forward current flows through the diode. Accordingly, the write operation can be performed just as intended.
Alternatively, the first and second conductivity types may also be p- and n-types, respectively. And the control means may set the potential level at the p-well to a value equal to or smaller than each voltage applied to the control gate while the memory cell is being written, read or erased.
In such an embodiment, the diode is connected in the backward direction. Accordingly, while the diode is forward biased with respect to the control gate, no current flows through the diode and the device can cope with the write and read operations as it is. Also, during an erase operation, a negative bias is applied to the control gate. However, since the control means sets the potential level at the p-well to a value equal to or smaller than the negative bias, no forward current flows through the diode. Accordingly, the erase operation can be performed just as intended.
In still another embodiment, the potential level at the control gate during the metallization process is preferably controlled to fall within a voltage range in which neither forward nor back current flows through the diode.
In yet another embodiment, the device preferably further includes a multi-level interconnect structure formed over the substrate to have two or more interconnect layers. The control gate and the diode are preferably connected together via one of the interconnect layers that is closer to the substrate than any other interconnect layer in the interconnect structure.
Then, the charge buildup damage can be reduced in every interconnect layer of the multi-level interconnect structure, as well as in the first-level interconnect layer.
In yet another embodiment, the damage reducer may include first and second diodes formed in the substrate. Each diode includes two electrodes with mutually opposite polarities. One of the two electrodes of the first diode and one of the two electrodes of the second diode may be both connected to the control gate. Then, the control means preferably changes a voltage applied to the other electrode of the first diode and the other electrode of the second diode depending on whether the memory cell is being written, read or erased.
In this particular embodiment, the first diode preferably includes a first well of a first conductivity type and a first doped region of a second conductivity type. The first well is formed in the substrate and used as the second electrode of the first diode. The first doped region is defined in the first well and used as the first electrode of the first diode. The second diode preferably includes a second well of the second conductivity type and a second doped region of the first conductivity type. The second well is formed in the substrate and used as the second electrode of the second diode. And the second doped region is defined in the second well and used as the first electrode of the second diode.
More particularly, the first and second conductivity types are preferably n- and p-types, respectively. The control means preferably sets the potential level at the n-well of the first diode to a value equal to or greater than each voltage applied to the control gate while the memory cell is being written, read or erased. Also, the control means preferably sets the potential level at the p-well of the second diode to a value equal to or smaller than each said voltage applied to the control gate while the memory cell is being written, read or erased.
In such an embodiment, the first and second diodes are connected in forward and backward directions, respectively. Accordingly, if positive charges build up during a metallization process, then the first diode is forward biased and the charges accumulated easily flow out therefrom. On the other hand, if negative charges build up during the metallization process, then the second diode is forward biased and the charges accumulated also flow out easily therefrom. Thus, the damage usually done on the tunnel insulating film can be eliminated almost completely. In addition, during a write or read operation in which the control gate is forward biased, the control means sets the potential level at the n-well of the first diode to a value equal to or greater than the positive bias. Accordingly, no forward current flows through the first diode. On the other hand, during an erase operation in which the control gate is reverse biased, the control means sets the potential level at the p-well of the second diode to a value equal to or smaller than the negative bias. Accordingly, no forward current flows through the second diode. In this manner, the memory cell can be written, read or erased just as intended.
In still another embodiment, the potential level at the control gate during the metallization process is preferably controlled to fall within a voltage range in which no forward current flows through the first or second diode.
In yet another embodiment, the inventive device preferably further includes a multi-level interconnect structure formed over the substrate to include two or more interconnect layers. The control gate is preferably connected to the first and second diodes via one of the interconnect layers that is closer to the substrate than any other interconnect layer in the interconnect structure.


A front-side type image sensor may include a substrate successively including: a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.

U.S. Patent Application Publication Number US 2016/0118431 describes a "front-side" type image sensor (also called a "front-side imager").
As illustrated in FIG. 1, the sensor comprises a Semiconductor-On-Insulator (SOI) type substrate comprising, from its back side to its front side, a support substrate 1 of P+ doped silicon, an electrically insulating layer 2 of silicon oxide, and an active layer 3 called an active layer of P− doped silicon, wherein a matrix array of photodiodes each defining a pixel is defined.
By convention, a P− doping corresponds to a concentration of P type dopants (for example, boron) in the order of 1014 to a few 1015 at/cm3.
A P+ doping corresponds to a concentration of P type dopants in the order of a few 1015 to 1019 at/cm3.
The choice of a P+ type doped support substrate aims at minimizing the migration of electrons from the support substrate to the active layer, which is likely to originate a dark current corresponding to the generation of carriers in the photodiodes even in the absence of light. On the other hand, the support substrate can be biased at an electric voltage lower than that of the active layer, for causing a build-up of majority carriers of the active layer at the interface between the active layer 3 and the electrically insulating layer 2 of silicon oxide. The electrically insulating layer 2 of silicon oxide is intended to electrically insulate the active layer 3 from the support substrate 1, for the purpose of preventing electrons from passing from the support substrate to the active layer.
However, the implementation of a P+ doped substrate on an industrial manufacturing line of SOI substrates is of concern.
Indeed, in some manufacturing stations, for example during cleaning or heat treatment steps, boron diffusion out of the support substrate and scattering into the environment of the manufacturing line are observed.
But, the manufacturing line is generally not dedicated to a single type of SOI substrates, and can in particular lead to treat little or undoped substrates. However, boron diffused into the environment can lead to contamination of the substrate, and this diffusion does not allow an accurate control of their doping level, which can alter their electrical properties.


We show that for any given muting fraction, a more constrained version of the problem of interest can be optimally solved in an efficient manner. In addition, the obtained solution is also a near-optimal solution for the original problem (for the given muting ratio). This allows us provide an algorithm that offers a good solution to the original problem with a tractable complexity. We also derive a lower complexity greedy that offers good performance and a certain worst-case performance guarantee. Simulations over an example LTE HetNet topology reveal the superior performance of the proposed algorithms and underscore the benefits of jointly exploiting partial muting of the macro and load balancing.

The present invention relates generally to wireless networks, and more particularly, to enhanced interference management in heterogeneous wireless networks.
The focus of this invention is on heterogeneous wireless networks (HetNets) that are expected to be fairly common and where the transmission points in the HetNet will be connected to each other by a non-ideal backhaul with a relatively high latency (ranging from 50 milliseconds to several dozens of milliseconds).
Over such HetNets, schemes that strive to obtain all coordinated resource management decisions within the fine slot-level granularity (typically a millisecond) are not suitable, since coordination (which involves exchange of messages and signaling over the backhaul) cannot be performed in such a fast manner. Instead, semi-static resource management schemes, where resource management over the set of transmission points TPs is performed at two time scales, are suitable since they are more robust towards backhaul latency.
The present invention considers one such semi-static resource management scheme. It focuses on a cluster of TPs that includes one high power macro TP and several low power pico TPs. The macro TP is the dominant interferer for all other pico TPs. The management scheme attempts to jointly exploit partial muting of the macro TP, wherein the macro TP can be made inactive for a fraction of the frame duration, and load balancing (a.k.a. user association), wherein users are associated to the TPs in that cluster, such that each user is associated to any one TP over the frame duration. The fraction for which the macro is muted can be chosen from a given finite set of fractions. This scheme requires limited coordination among TPs in the cluster which is possible under a non-ideal backhaul. The underlying coordination is performed periodically at a coarser frame-level granularity based on averaged (not instantaneous) slowly varying metrics that are relevant for a period longer than the backhaul latency. Examples of such metrics include estimates of average rates that the users can receive from those TPs under different configurations etc. On the other hand, the resource management that is done at a much finer sub-frame/slot level granularity involves no coordination among TPs and is done independently by each active TP based on fast changing information, such as instantaneous rate or SINR estimates, that is received directly by that TP from the users associated to it.
Together, partial muting of the macro transmission point TP and load balancing can lead to significant benefits.
The HetNet diagram of FIG. 1 shows 3 TPs and 3 users and associated frames. TP1 is the high power macro TP and TP2 and TP3 are the low power pico TPs. Dashed lines indicate potential association of users to TPs. TP1 is made inactive (is muted) for a fraction of the frame duration, whereas TP2 and TP3 are active throughout the frame.
Most existing works consider either exploiting only partial muting of the macro TP for a given user association or exploiting only user association for a given partial muting. Also, the prior art has adopted an approach which relaxes the underlying discrete variables, which can degrade performance.
Accordingly, there is a need for enhanced interference management in heterogeneous wireless networks.

Enhanced interference management in heterogeneous wireless networks


The present invention generally provides a terahertz (THz) imaging system that includes a source for generating radiation (e.g., a quantum cascade laser) having one or more frequencies in a range of about 0.1 THz to about 10 THz, and a two-dimensional detector array comprising a plurality of radiation detecting elements that are capable of detecting radiation in that frequency range. An optical system directs radiation from the source to an object to be imaged. The detector array detects at least a portion of the radiation transmitted through the object (or reflected by the object) so as to form a THz image of that object.

The present invention relates generally to terahertz (THz) imaging systems, and more particularly to such imaging systems that can acquire images in real-time at video rates, e.g., by utilizing a coherent narrow-band THz illumination source.
The transparency of materials to radiation having frequencies in a range of about 0.1 to about 10 terahertz (THz) can be quite different than their transparency to radiation having frequencies in the visible range. For example, germanium, silicon, polytetrafluoroethylene plastic (Teflon), high and low-density polyethylene plastics (HDPE and LDPE), teeth, leaves, clothing and envelopes typically become more transparent at these terahertz frequencies. The increased transparency of many materials at terahertz frequencies has prompted the development of a variety of terahertz imaging systems. However, conventional imaging systems often obtain an image of an object by linearly scanning the object through a tightly focused THz beam—a practice that limits the image acquisition time to the mechanical scan rate of the system. With upper limits of hundreds of pixels per second for acquiring an image by mechanical scanning, in this approach, a complete image requires minutes to be acquired.
Alternatively, conventional terahertz imaging systems suitable for acquiring real-time images (e.g., 20 frames per second or more) typically employ an electro-optic crystal for frequency upconversion of THz pulses to optical pulses so that a CCD focal-plane camera can be employed for detecting the radiation and generating images. This arrangement, however, requires precise timing of optical and THz pulses, thus necessitating a scanning delay mechanism that adds to system complexity. Moreover, such systems are inherently broad-band (typically short THz pulses (e.g., less than 1 ps) are utilized that result in a bandwidth larger that 1 THz), and hence not suitable for applications that require coherent narrow-band illuminating radiation for frequency-sensitive imaging.
Accordingly, there is a need for an enhanced terahertz imaging system that can provide real-time, high resolution images.

Real-time, continuous-wave terahertz imaging using a microbolometer focal-plane array


A medical device enables a user to bend it into a shape to suit a specific patient need or to orient efficiently the medical device for use. The medical device includes an elongate member, a mechanism, and an actuator. The mechanism is disposed at the distal portion of the elongate member. The actuator is at least partially disposed within the elongate member and coupled to the mechanism for actuating the mechanism relative to the elongate member. The elongate member is capable of being bent into a shape by the user and of retaining the shape during use. The shape may include multiple bends, in multiple directions, as needed for an application. Thereafter, the elongate member is capable of being bent into a second shape by the user and of maintaining the second shape during use.

For many surgical procedures, it is necessary to make a large opening in the human body to expose the area that requires surgical repair. There are instruments available that allow for viewing certain areas of the human body through, for example, a natural body opening or a small puncture wound, and thus avoid the need for making such large openings. These instruments, called endoscopes, can be used in conjunction with specialized surgical instruments to detect, diagnose, sample, and repair areas of the body that previously required open surgery to access.
Some surgical instruments used in endoscopic procedures are limited by the way they grasp tissue, cut tissue, apply a suture, or recapture the needle and suture. Furthermore, many surgical instruments are complicated and expensive to use due to the numerous parts and/or subassemblies required to make them function properly. Suturing, in particular, remains a delicate and time-consuming aspect of most surgeries, including those performed endoscopically.
In addition, many of the instruments used in endoscopic procedures are limited by the manner in which they access the areas of the human body in need of diagnosis, sampling, treatment, or repair. In particular, the instruments may not be able to access tissue or organs that are located deep within the body or that are in some way obstructed. The instruments used in endoscopic procedures typically have a rigid shaft, and do not allow the user to contour the shaft for a more efficient orientation to reach the location of diagnosis, sampling, treatment, or repair. Instruments with various shaft configurations have been introduced to accommodate specific applications. Thus, a user's inventory of instruments may include a number of rigid shaft instruments for various applications.

This patent is subject to a terminal disclaimer.


A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.

The present invention relates to semiconductor devices of multiple-chip configuration having capacitive insulation means for electrical separation and isolation between primary side circuitry and secondary side circuitry while permitting signal transmission therebetween and also relates to integrated circuits employing the devices and, in more particular, to communication terminal apparatus including an analog front end (AFE) and/or a modulator/demodulator, called "modem."
Traditionally, individual or "discrete" electronics components such as transformers or photo-couplers, also known as insulating couplers or isolators among those skilled in the art, are typically employed in cases where electrical insulation/isolation is to be established between a plurality of circuits while permitting signal transmission between them. For instance, in the field of communications technologies, higher dielectricity has been strictly required at boundaries between networks and terminals in order to provide enhanced protection for network facility with high publicities and also for terminal devices operatively associated therewith. To this end, isolators such as small-size communication-use transformers have been used. Alternatively in the fields of measurement technologies and medical industries, isolators have been used as means for providing electrical insulation and isolation between a signal detection unit and a signal processing unit, such as between a sensor module and its associative signal waveform processor circuitry, in a viewpoint of the safety for human bodies and measurement equipment with enhanced anti-noise performances.
In the case of using transformers to provide electrical insulation required, the quest for reduction in size and in weight is limited due to the presence of restrictions against materials and structures used, while accompanying a penalty as to unwanted cost/price increases. Isolators using a photo-coupler with a combination of light-emitting element and photosensitive element for detection of light received are generally small in size and less in weight and also low in price. Unfortunately such photocoupler can readily vary in electrical characteristics thereof with a change in temperature or other parameters. Compensating for such characteristic deviation does require the use of a correction circuit, which in turn requires highly accurate control techniques. Another problem faced with the photocoupler-based isolators is that extra fabrication processes for manufacturing the light emitting and receiving elements should be required in addition to standard or ordinary fabrication processes in the manufacture of a semiconductor device.
Discrete components for constitution of insulation barriers include a ceramic capacitor for electric power supply or for serge protection. A signal transmission circuit using capacitors of this type is called the capacitive insulation amplifier or, alternatively, capacitive insulation coupler among those skilled in the art to which the invention pertains. Known methodology for signal transmission via such capacitive insulation barriers includes pulse width modulation (PWM) schemes. One typical signal transfer technique using three separate capacitive insulation barriers has been disclosed in Published Japanese Patent Application No. 7-307708 (corresponding to U.S. Pat. No. 5,654,984), along with a model application circuit using the barriers.

Semiconductor device including primary and secondary side circuits on first and second substrates with capacitive insulation