A bit map display system has a frame buffer memory for storing image data in pixel blocks each composed of a plurality of dots or pixels. To transfer image data from a source address region to a destination address region, block addresses are generated from relative addresses of starting and ending pixel points in the source address region and relative addresses of starting and ending pixel points in the destination address region, and supplied to the frame buffer memory. A decision circuit generates a pre-reading signal and a non-reading signal from the relative addresses depending on the direction in which the image data are to be transferred. The pre-reading and non-reading signals are set according to certain predetermined conditions. The image data are transferred from the source address region to the destination address region in the frame buffer memory in various ways depending on whether the pre-reading and non-reading signals are set or not.

1. Field of the Invention
The present invention relates to an apparatus for transferring blocks of image data.
2. Description of the Prior Art
In usual bit map display systems, one frame of image data is written into a frame buffer (FB) memory which comprises a dynamic RAM, and the image data are successively read from the frame buffer memory and supplied to a display unit such as a CRT, which displays on its display screen an image represented by the image data. The displayed image is made up of a plurality of picture elements or pixels corresponding respectively to the image data which are stored at respective addresses of the frame buffer memory.
CRTs for use as graphic display terminals in CAD, CAM, and other similar applications have high resolutions, for example, of 1280.times.1024 dots. When such a CRT is scanned by the noninterlacing scanning process at a frequency of 60 Hz, a dot clock signal used to read one dot pixel from the frame buffer memory is required to have a frequency in excess of 100 MHz (i.e., a period in excess of 10 ns). However, since the dynamic RAM used as the frame buffer memory can be accessed at a speed which is much lower than the above frequency, it is customary practice to access a plurality of dynamic RAM chips simultaneously in one access cycle for reading image data representing plural dots at one time.
The image data of plural dots which have simultaneously been read are then supplied to a high-speed shift register. The image data stored in the shift register are successively read with the dot clock signal and supplied to the CRT. In this manner, the low access speed of the dynamic RAM is compensated for.
In view of recent microprocessors available with wider buses, it has become possible to write image data representing plural dots simultaneously into a frame buffer memory. The image data stored in the frame buffer memory are allotted addresses such that a group of image data representing plural dots corresponds to one address. It is customary to group a horizontal array of successive pixels, the number of which is represented by a power of 2. For example, one address is assigned to each horizontal array of successive pixels that represent 16 dots.
FIG. 1 of the accompanying drawings shows a structure of image data stored in a frame buffer memory, the image data being divided into groups of pixels representing 16 dots. In the frame buffer memory, a plurality of one-dot image data 1 are arranged in horizontal and vertical directions (indicated respectively by the arrows X and Y) which correspond to those on a display screen. The image data 1 are divided in the horizontal direction into pixel blocks 2A, 2B, 2C, . . . each composed of 16 pixels or dots. In each of the pixel blocks 2A, 2B, 2C, . . . , the image data which are 16 dots long in the horizontal direction and one dot long in the vertical direction are allotted one address. Therefore, the groups or units of image data which are 16 dots long in the horizontal direction and one dot long in the vertical direction are written into and read out of the frame buffer memory, one at a time.
It is assumed that image data representing a plurality of dots are to be transferred from one address region to another address region for translating a displayed image of an object on a display screen. If the address region from which the image data are to be transferred, i.e., the source address region, adjoins the boundaries of a pixel block composed of 16 pixels, and the address region to which the image data are to be transferred, the destination address region, adjoins the boundaries of another pixel block, then the image data can easily be transferred. Such a transfer of the image data can be carried out by reading one pixel block, writing one pixel block, reading one pixel block, . . . , reading one pixel block, and writing one pixel block.
More specifically, image data 3 (FIG. 1) corresponding to 16.times.2 dots can be transferred from an address region P1 adjoining the boundaries of the pixel block 2A to an address region P2 adjoining the boundaries of the pixel block 2B simply by reading and writing image data corresponding to 16 dots in two repetitive cycles.
However, if image data are to be transferred from or to an address region which does not adjoin a pixel block, then the process of transferring the image data is much more complex.
Specifically, as shown in in FIG. 1, it is assumed that image data 4 are to be transferred, from the righthand to the lefthand end of an address region P3, to an address region P4. Image data 5B in the source address region P3 within the pixel block 2B are three dots long in the horizontal direction, whereas image data 6A in the destination address region P4 within the pixel block 2C are nine dots long in the horizontal direction. The image data (including the image data 5B) in the pixel block 2B and the image data 5A in the pixel block 2A are pre-read from the source address region P3, and image data (including the image data 6A) produced by processing the two image data groups thus pre-read are written into the pixel block 2C in the destination address region P4.
Image data 6B at the lefthand end of the destination address region P4 are one dot long in the horizontal direction. Since the image data 6B have already been pre-read from the source address region P3, the step of reading the image data again may possibly be omitted. For the transfer of image data irrespective of the boundaries of the pixel blocks, as described above, the transfer procedure (transfer efficiency) may be optimized for an increased transfer rate by employing the pre-reading process or the like. Heretofore, no consideration has been given to optimization of the transfer efficiency.

Apparatus for transferring blocks of image data


The present invention relates to a flexible substrate. More particularly, the present invention relates to a flexible substrate for a display apparatus. A display apparatus according to an embodiment of the present invention comprises a display panel in which an electrode is formed, a heat sink plate formed on a rear side of the display panel, a driving board formed on a rear side of the heat sink plate, and a flexible substrate for connecting the electrode and the driving board, wherein the flexible substrate is directly grounded to the heat sink plate. Accordingly, the noise of pulses supplied from the flexible substrate can be prevented and damage to the flexible substrate can be prohibited.

1. Field of the Invention
The present document relates to a flexible substrate. More particularly, the present document relates to a flexible substrate for a display apparatus.
2. Description of the Related Art
A flexible substrate is used to reduce the cost price and the workability of display apparatuses such as a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP) and an Organic Electro Luminescent Display (OELD). For example, if a Tape Carrier Package (TCP) (i.e., one of the flexible substrates) is used as the package of the data driver Integrated Circuit (IC) chip of the display apparatus, the cost of the package itself can be saved and there are several advantages in terms of the process since the package supply and attachment processes can be automated.
The flexible substrate includes a Chip on Film (COF) and a TCP in which an IC chip is packaged, and a Flexible Printed Circuit (FPC) in which a circuit is simply patterned.
FIG. 1 is a drawing illustrating a display apparatus in the related art.
FIG. 1 shows an example of a flexible substrate used for a plasma display apparatus of the display apparatuses. As shown in FIG. 1, the plasma display apparatus has a control board 20, a data driving board 21, a flexible substrate 23, a plasma display panel 22 and a scan/sustain driving board 24. Each of the boards 20, 21 and 24 is directly grounded (GND) to a heat sink plate (not shown) formed on a rear side of the plasma display panel 22. There occurs a difference in the impedance between the grounds (GND) of the boards 20, 21 and 24 because of several causes.
Meanwhile, the flexible substrate 23 has a ground structure connected to the heat sink plate through the data driving board 21. Accordingly, problems arise because the flexible substrate 23 is influenced by pulses supplied from the driving boards 21 and 24 to the plasma display panel 22 and is vulnerable to electromagnetic interference. In other words, there are problems in that noise is generated in the pulses supplied through the flexible substrate and in even worse conditions, IC chips formed in the flexible substrate are failed.

Display apparatus and flexible substrate


Sigma-delta A/D converter having at least one analog signal input (1, 2) for applying an analog input signal, a subtraction element (3) having a plurality of capacitors (20) for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors (20) to reference voltage sources (7, 8, 9) depending on control signals, an integrator (10) for integrating the output signal of the subtraction element (3) during the integration phase, a quantizer (13) for analog-to-digital conversion of the output signal of the integrator (10) for outputting a digitized output signal to a digital signal output (14), and having a control logic element (16) for generating the control signals in such a way that the current load of the reference voltage sources (7, 8, 9) is minimized during the integration phase.

The invention relates to a sigma-delta A/D converter with minimal current load of the reference voltage sources.
FIG. 1 shows a block circuit diagram of a sigma-delta A/D converter according to the prior art. The sigma-delta A/D converter receives an analog input signal at the input E, which is fed to a subtraction element S. In the subtraction element S the output signal of a multi-bit D/A converter is subtracted from the analog input signal and is fed to an integrator. The integrator integrates the input signal and outputs the integrated signal to a quantizer. The quantizer is an analog-to-digital converter with a low resolution which outputs the digitized output signal to an output A of the sigma-delta A/D converter. The digitized output signal is connected via a feedback line to the input of the multi-bit D/A converter. The digitized output signal of the quantizer is converted by the multi-bit D/A converter into an analog signal and is subtracted in the subtraction element S from the input signal at the input E.
FIG. 2 shows an embodiment of a sigma-delta A/D converter employing SC circuitry (SC switched capacities: switchable capacitors). The prior art sigma-delta A/D converter shown in FIG. 2 is a fully differential sigma-delta A/D converter having two signal inputs VINA and VINB. Also provided are reference voltage sources VREFP and VREFN which can be connected by controllable switching devices to capacitors C1A, C2A, . . . CLA as well as capacitors C1B, C2B, . . . CLB. The capacitors may furthermore be connected by switching devices to the analog signal inputs VINA, VINB.
On the output side, the capacitors C1A, C2A, . . . CLA as well as C1B, C2B, . . . CLB can be connected by switching devices n and a common ground line to ground VGND or to an integrator.
In the sigma-delta A/D converter shown in FIG. 2, the integrator contains an operational amplifier with one inverting and one non-inverting input as well as two output lines, with integration capacitors CINT being connected between the signal inputs and signal outputs of the operational amplifier in each case. Connected downstream of the integrator is a quantizer for analog-to-digital conversion of the voltage between the two output lines of the operational amplifier. The digitized signal present at the output of the quantizer is fed via a feedback line to a control logic element which supplies control signals for controlling the switching devices.
During a sampling phase PHl1, the capacitors C1A, C2A, CLA are connected by switches on the one hand to the first analog input line VINA and on the other hand to ground VGND. During the sampling phase PHL1, the capacitors C1B, C2B, . . . CLB are connected by switching devices on the one hand to the second analog input signal VINB and on the other hand to ground VGND. During the sampling phase, all switches indicated by xe2x80x9cPHL1xe2x80x9d in FIG. 2 are closed.
Upon completion of the sampling phase PHL1, the switches indicated by PHl1 in FIG. 2 are opened and the capacitors C1A, C2A, . . . CLA are connected by the switches indicated by PHL2 to the non-inverting input (+) of the operational amplifier and to the first integration capacitor CintA for charge transfer. At the same time, the capacitors C1B, C2B, . . . CLB are switched by the switches indicated by PHL2 to the inverting input (xe2x88x92) of the operational amplifier and to the second integration capacitor CintB for charge transfer. At the same time, in each case the left capacitor plates of the capacitors C1A, C2A, . . . CLA and C1B, C2B, . . . CLB are connected to the reference voltage source VREFP or to the reference voltage source VREFN respectively in accordance with the control instructions generated by the control logic element.
Upon completion of the integration phase PHL2, an output voltage VOUTP(i) is present at the output of the integrator, i.e. between the two output lines of the operational amplifier, which output voltage depends on the preceding value VOUTP(ixe2x88x921), the analog input voltage VINA (ixe2x88x92xc2xd), the number of capacitors CjA whose left capacitor plate is connected to the positive reference voltage source VREFP during the integration phase, and the number n (i) of capacitors CjA whose left capacitor plate is connected to the negative reference voltage source VREFN during the integration phase.
The output voltage VOUTP(i) is obtained here using the following equation:                                                         V              OUTP                                                  (              i              )                                =                                                                                V                    OUTP                                                                          (                                          i                      -                      1                                        )                                                  +                                                                            V                      INA                                                                                (                                              i                        -                                                  1                          /                          2                                                                    )                                                        ·                                                            L                      ·                                              C                        jA                                                                                C                      int                                                                      -                                                      p                                                              (                      i                      )                                                        ·                                      "LeftBracketingBar"                                          V                      REFP                                        "RightBracketingBar"                                    ·                                                            C                      jA                                                              C                      int                                                                      +                                                      n                                                              (                      i                      )                                                        ·                                      "LeftBracketingBar"                                          V                      REFN                                        "RightBracketingBar"                                    ·                                                            C                      jA                                                              C                      int                                                                                ⩵                        =                                                                                V                    OUTP                                                                          (                                          i                      -                      1                                        )                                                  +                                                                            V                      INA                                                                                (                                              i                        -                                                  1                          /                          2                                                                    )                                                        ·                                                            L                      ·                                              C                        jA                                                                                C                      int                                                                      -                                                                            (                                                                        p                                                                                (                            i                            )                                                                          -                                                  n                                                                                (                            i                            )                                                                                )                                        ·                                          V                      REF                                        ·                                                                  C                        jA                                                                    C                        int                                                                                xe2x80x83                                                      with                                                        xe2x80x83                                                                          V                    REF                                                              =                                                "LeftBracketingBar"                                      V                    REFP                                    "RightBracketingBar"                                =                                  "LeftBracketingBar"                                      V                    REFN                                    "RightBracketingBar"                                                                    ;                            (        1        )
The number of capacitors CjA whose left capacitor plate is connected to the positive reference voltage source VREFP during the integration phase is obtained here using the following equation:                                           p                                      xe2x80x83                                                  (              i              )                                =                                    round                                            [                                                      L                    /                    2                                    ·                                      (                                          1                      +                                                                                V                            DIG                                                                                (                            i                            )                                                                                V                          REF                                                                                )                                                  ]                                       less than =                          L                                            xe2x80x83                                          for                                            xe2x80x83                                                                            V                  DIG                                                                  (                  i                  )                                                       greater than =            0                          ;                            (        2        )
where VDIG is the output signal of the quantizer.
The number of capacitances CjA whose capacitor plate is connected to the negative reference voltage source VREFN during the integration phase is obtained using the following equation:                                           n                                      (              i              )                                =                                    round                                            [                                                      L                    /                    2                                    ·                                      (                                          1                      -                                                                                V                            DIG                                                                                (                            i                            )                                                                                V                          REF                                                                                )                                                  ]                                       less than =                          L                                            xe2x80x83                                          for                                            xe2x80x83                                                                            V                  DIG                                                                  (                  i                  )                                                       less than =            0                          ;                            (        3        )
where VDIG is the output signal of the quantizer. The total number of capacitances whose left capacitor plate in each case is connected to the positive reference voltage source during the integration phase and of capacitances whose left capacitor plate is connected to the negative reference voltage source VREFN during the integration phase is constant here.
p(i)+n(i)=L=const.,xe2x80x83xe2x80x83(4)
where L is the total number of capacitors.
So that the total charge is fully integrated, all capacitors are connected to the input of the operational amplifier during the integration phase.
The load of the reference voltage sources VREFP, VREFN with the prior art sigma-delta A/D converter shown in FIG. 2 is greatly signal-dependent.
For VDIG(i)xcx9cVINA(i) and VINA(i) greater than 0, the charge transfer at the positive reference voltage source caused by the analog input signal VINA(i) is calculated using the following equation:                     "AutoLeftMatch"                                            "LeftBracketingBar"                                                dq_V                  REFP                                                                  (                  i                  )                                            "RightBracketingBar"                        =                                                            p                                                        (                    i                    )                                                  ·                                  (                                                            V                      REFP                                        -                                                                  V                        INA                                                                                (                        i                        )                                                                              )                                ·                                  C                  jA                                            =                                                round                  [                                                            L                      /                      2                                        +                                                                  L                        /                        2                                            ·                                                                                V                            DIG                                                                                (                            i                            )                                                                                V                          REF                                                                                ]                                ·                                  (                                                            V                      REFP                                        -                                                                  V                        INA                                                                                (                        i                        )                                                                              )                                ·                                                      C                    jA                                    ~                                      (                                                                                L                          /                          2                                                ·                                                  V                          REF                                                                    -                                                                        L                          /                          2                                                ·                                                                              V                            INA                                                                                (                            i                            )                                                                                +                                                                        L                          /                          2                                                ·                                                                              V                            DIG                                                                                (                            i                            )                                                                                -                                                                        L                          /                          2                                                ·                                                                                V                                INA                                                                                (                                i                                )                                                                                ·                                                                                V                                DIG                                                                                (                                i                                )                                                                                V                            REF                                                                                )                                                  ·                                                                            C                      jA                                        ~                    L                                    /                  2                                ·                                  C                  jA                                ·                                  V                  REF                                ·                                  (                                      1                    -                                                                                V                            INA                                                                                (                            i                            )                                                                          2                                                                    V                        REF                                                                              )                                                              ;                                    (        5        )
The charge transfer at the negative reference voltage source is obtained using the following equation:                     "AutoLeftMatch"                              "LeftBracketingBar"                                          dq_V                REFN                                                          (                i                )                                      "RightBracketingBar"                    =                                                    n                                                  (                  i                  )                                            ·                              (                                                      "LeftBracketingBar"                                          V                      REFP                                        "RightBracketingBar"                                    +                                                            V                      INA                                                                                (                      i                      )                                                                      )                            ·                              C                jA                                      =                                          (                                  L                  -                                      round                    [                                                                  L                        /                        2                                            +                                                                        L                          /                          2                                                ·                                                                                V                              DIG                                                                                (                              i                              )                                                                                V                            REF                                                                                ]                                                  )                            ·                              (                                                      "LeftBracketingBar"                                          V                      REFN                                        "RightBracketingBar"                                    +                                                            V                      INA                                                                                (                      i                      )                                                                      )                            ·                              (                                                                            ~                                              (                                                                                L                              /                              2                                                        ·                                                          V                              REF                                                                                +                                                                                L                              /                              2                                                        ·                                                                                V                                INA                                                                                (                                i                                )                                                                                -                                                                                L                              /                              2                                                        ·                                                                                V                                    DIG                                                                                (                                    i                                    )                                                                                ~                                L                                                            /                              2                                                        ·                                                                                V                                    INA                                                                                (                                    i                                    )                                                                                ·                                                                                V                                    DIG                                                                                (                                    i                                    )                                                                                V                                REF                                                                                )                                                              ·                                                                                C                          j                                                ~                        L                                            /                      2                                        ·                                          C                      jA                                        ·                                          V                      REF                                        ·                                          (                                              1                        -                                                                                V                                INA                                                                                (                                i                                )                                                                                2                                                                                V                            REF                            1                                                                                )                                                        ;                                                                                (        6        )
If both analog signal inputs VINA(i) and VINB(i) are included, the value and the effective current load of the reference voltage sources are doubled.
The effective current load of the reference voltage sources for the prior art sigma-delta A/D converter, as illustrated in FIG. 2, is then as follows:                                                         Ceff              VREF                                                  (              i              )                                =                      L            ·                          C              j                        ·                          (                              1                -                                                                            (                                                                        V                          INA                                                                                (                          i                          )                                                                    )                                        2                                                        V                    REF                    2                                                              )                                      ;                            (        7        )
The maximum effective load of the reference voltage sources is obtained with VINA(i) xcx9c0 and is:
Ceff_maxxe2x80x94VREF=Lxc2x7Cj;xe2x80x83xe2x80x83(8)
The minimum value of the effective load of the reference voltage sources is obtained for the value VINA(i)xcx9cVREF:
Ceff_minxe2x80x94VREF=0.xe2x80x83xe2x80x83(9)
As can be seen from the above equations, the current load of the reference voltage sources in the prior art sigma-delta A/D converter, as illustrated in FIG. 2, depends on the analog input signal. The signal-dependent load of the reference voltage sources leads to non-linear distortions and limits the resolution of the prior art sigma-delta A/D converter.
It is therefore the object of the present invention to create a sigma-delta A/D converter in which the current load of the reference voltage sources is minimal.
According to the invention, this object is achieved by a sigma-delta A/D converter having the features specified in Claim 1.
Further advantageous refinements of the sigma-delta A/D converter according to the invention emerge from the subclaims.
The invention creates a sigma-delta A/D converter having at least one analog signal input for applying an analog input signal, a subtraction element having a plurality of capacitors for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors to reference voltage sources depending on control signals, an integrator for integrating the output signal of the subtraction element during the integration phase, a quantizer for analog-to-digital conversion of the output signal of the integrator for outputting a digitized output signal to a digital signal output, and having a control logic element for generating the control signals in such a way that the current load of the reference voltage sources is minimized during the integration phase.
In an advantageous refinement of the sigma-delta A/D converter according to the invention, first switching devices are switched by control signals of the control logic element to connect the reference voltage sources to the capacitors during the integration phase.
In a further advantageous refinement of the sigma-delta A/D converter according to the invention, second switching devices are switched by control signals of the control logic element to connect the capacitors to the analog signal input during a sampling phase.
In a further advantageous refinement of the sigma-delta A/D converter according to the invention, third switching devices are switched by control signals of the control logic element to connect the capacitors to the integrator during the integration phase.
The control signals are preferably generated depending on the digitized output signal of the quantizer, the potential difference between the reference voltage sources and the number of capacitors.
In a preferred embodiment of the sigma-delta A/D converter according to the invention, the capacitors have the same capacitance.
Three reference voltage sources are preferably provided.
In a preferred embodiment of the sigma-delta A/D converter according to the invention, a first reference voltage source having a reference potential, a second reference voltage source having a positive potential and a third reference voltage source having a negative potential are provided.
The negative potential of the third reference voltage source and the positive potential of the second reference voltage source are preferably symmetrical to the reference potential of the first reference voltage source.
The sigma-delta A/D converter according to the invention is preferably of a differential design with two analog signal inputs.
A low-pass filter is preferably connected downstream of the digital signal output.
In a preferred embodiment of the sigma-delta A/D converter according to the invention, the integrator has an operational amplifier and at least one integration capacitor.
The quantizer preferably has a relatively low signal resolution in comparison with the signal resolution of the sigma-delta A/D converter according to the invention.
The operational amplifier within the integrator preferably has a very high-resistance signal input.


Isolated polynucleotides are disclosed which increase the efficiency of gene expression in a heterologous cell. The polynucleotide sequences which encode polypeptides are adapted such that the average rate of translation of the first at least about 30 amino acids is slower by at least two fold than the average rate of translation of the remaining amino acids of the polypeptide.

The present invention, in some embodiments thereof, relates to recombinant protein production in heterologous systems.
Advances in genetic engineering have made possible the production of therapeutics and vaccines for human and animals in the form of recombinant proteins. These biotechnology-derived recombinant proteins form a new class of drugs for many ailments like genetic disorders, cancer, hypertension and AIDS for which there is no better treatment or cure. Unlike chemical drugs, biologicals are the body's own molecules and hence more compatible with biological systems. At present there are more than 100 biotechnology-derived therapeutics and vaccines approved by US FDA for medical use and over 1000 additional drugs and vaccines are in various phases of clinical trials. In addition, use of DNA, proteins and enzymes in diagnostics is increasing exponentially. Industrial uses of enzymes in food, textile, leather, detergent, medicinal chemistry sectors are also increasing rapidly.
The growing need of therapeutic and other applications of enzymes and proteins is presently met by heterologous synthesis of recombinant proteins.
Commonly used expression systems for heterologous protein production include E. coli, baculovirus, yeast, Chinese Hamster Ovary cells (CHO) and plants.
Efficiency of expression of recombinant proteins in heterologous systems depends on many factors, both on the transcriptional level and the translational level.
mRNA translation is controlled at multiple stages and by a diversity of mechanisms. A major part of the control is on the stage of initiation, where ribosomes are recruited and assembled on the mRNA, typically on the 5′ un-translated region (UTR) (1). The elongation phase is governed by the mRNA secondary structure (2), and by the extent of adaptation of the coding sequence to the cellular tRNA pool (3, 4). The abundance of tRNAs that correspond to the different codons in a gene was suggested to determine the speed (5, 6) and accuracy (7) of translation. Thus, codons that are recognized by abundant or rare tRNAs will be respectively referred to here as codons with high and low efficiency (or as codons that are respectively highly or lowly adapted to the tRNA pool). It may be hypothesized that ribosomes will spend less time on high efficiency codons, explore less mismatched tRNAs and thus waste less GTP molecules when translating them, will be less likely to introduce a translation error on such codons and in addition may have lower probability of pre-mature drop off when translating them.
Indeed transcripts whose codons are biased towards the more abundant tRNAs were found to be more highly expressed (5, 8). In addition protein expression levels can be artificially increased by designed mutations that increased their codon-tRNA adaptation (9-12), pointing to a causal relationship between codon usage and expression level. Accordingly, the extent of adaptation between genes to the tRNA pool in different species was found to vary in evolution according to organisms' life style needs (5, 13).

Recombinant protein production in heterologous systems


An independent dual-blade robot assembly is provided for use in semiconductor wafer processing. The robot assembly includes a rotatable stage located within a chamber, a linear track mounted on an upper surface of the rotatable stage, and article first and second motorized platens slidably mounted on the linear track and configured for movement along a longitudinal axis of the linear track. Each motorized platen is magnetically driven and carries an end effector which extends from a leading edge. The end effectors of the first and second motorized platens are preferably horizontally coplanar. The linear track may be a single track carrying both motorized platens, or two linear track sections may be provided where each carries a single motorized platen. The two track sections may be pivotally or rotatably connected to the rotatable stage.

The present invention relates to the transfer of articles, such as semiconductor wafers, and more particularly to a dual-blade robot for effecting independent linear transfer of two or more semiconductor wafers.
The use of robot arms is a well established manufacturing expedient in applications where human handling of the wafers is inefficient and/or undesired. For example, in the semiconductor arts robot arms are used to handle wafers during various process steps. Such process steps include those which occur in a process chamber, e.g. etching, deposition, passivation, etc., where a sealed environment must be maintained to limit the likelihood of contamination and to ensure that various specific processing conditions are provided.
Current practice includes the use of one or more robot arms to load semiconductor wafers from a wafer cassette into various processing ports within a multiple process chamber system. Such systems typically include a central chamber, to which the wafer cassette and process chambers are linked. The robot arm is then employed to retrieve the wafer from a particular port after processing within an associated process chamber. The wafer is then shuttled by the robot arm to a next port for additional processing. When all processing within the reaction system is complete, the robot arm returns the semiconductor wafer to the loading port. Typically, a stack of several semiconductor wafers is handled in this manner during each process run, and several wafers may be in process at any point in time.
In multiple process chamber systems, it is desirable to have more than one semiconductor wafer in process at a time. In this way, the process system is used to obtain maximum throughput. In the art, where a single robot arm is used in a process system to shuttle wafers between wafer cassettes and process chambers, the robot may require complex movement to simply switch two wafers in two single wafer process chambers.
One way to increase the efficiency of the robot is to provide a robot arm having the ability to handle two wafers at the same time. Thus, some equipment manufacturers have provided a robot arm in which the two robot blades are rotated about a pivot by a motor with a belt drive at the end of the arm. In this way, one wafer may be stored on one carrier while the other carrier is used to retrieve and place a second wafer. The carriers are then rotated and the stored wafer may be placed as desired. Such mechanism is rather complex and requires a massive arm assembly to support the weight of a carrier drive located at the end of an extendible robot arm. Furthermore, such a mechanism does not allow independent operation of the two carriers.

Independent linear dual-blade robot and method for transferring wafers


Provided is an operational status testing apparatus and method for an Ethernet-based APS process. A test command signal which contains a command to perform an operational test for the APS process of a first node and a second test response signal that indicates that the operation of the APS process of a second node is performed normally, from among far end request signals that are received from the second node connected to own first node via an Ethernet network, are filtered. When the far end request signals are test command signals, a first test response signal that indicates that the operation of the APS process of the first node is performed normally is generated, and a top priority local request signal is selected based on priorities of the first test response signal and at least one local request signal that indicates the status of the APS process of the first node, and an output signal to be transmitted to the second node is determined based on priorities of the top priority local request signal and the filtered the far end request signal. The function for testing the operational status for the APS process defined in ITU-T recommendation G.8031 is embodied, and when an operational status test request is received from another node, the APS process can be tested effectively without having to perform a complicated diagnosis operation for the APS process.

1. Field of the Invention
The present invention relates to an operational status testing apparatus and a method for an Ethernet-based automatic protection switching (APS) process, and more particularly, to an operational status testing apparatus and a method for an Ethernet-based APS process, in which an operational status testing function and a protection switching status maintaining function of an APS process stipulated by ITU-T recommendation G.8031 are made to complement each other and are improved.
This work was supported by the IT R&D program of MIC/IITA [2006-S-061-02, R&D on Router Technology for IPv6 based QoS Services and Host Mobility].
2. Description of the Related Art
Protection switching (PS) allows at least one reliable connection path to be formed between two nodes connected via a network and, when a failure occurs in the connection path, communication can be achieved by using a previously reserved protection connection path.
An Ethernet protection switching function is defined by ITU-T recommendations G.8031 and G.8032. Here, ITU-T recommendation G.8031 defines a protection switching method for an Ethernet point-to-point connection, and ITU-T recommendation G.8032 defines a protection switching method for an Ethernet ring connection. The present invention relates to a function for testing whether a protection switching function is performed normally between both nodes connected via an Ethernet regardless of a method for connecting both nodes connected via the Ethernet. However, since ITU-T recommendation G.8032 has not been recognized as an official recommendation yet, only Ethernet linear protection switching stipulated by ITU-T recommendation G.8031 will now be described.
ITU-T recommendation G.8031 stipulates a 1-phase APS process in a 1:1 or 1+1 configured linear connection network architecture. Nodes at both ends of a protection domain are connected to each other via two paths, which are called a working transmission path and a protection transmission path, respectively. The working transmission path is a path through which data is interchanged between both ends of the protection domain at normal times and the protection transmission path is a reserved path for the case where a failure occurs in the working transmission path. An APS process is used in nodes at both ends of the protection domain so as to interchange path status information and a protection switching command.
The APS process is very important when a function for managing a protection switching operation is performed. If the APS process is stopped or a malfunction occurs at either end of the protection domain, a transmission path between both ends of the protection domain may be intercepted.
In order to prevent this situation, ITU-T recommendation G.8031 defines a test command (hereinafter, referred to as an EXER request) to check whether another node's APS process is performed normally at both ends of the protection domain. In other words, two nodes are located at both ends of the protection domain and connected each other. One node transmits the EXER request to the other node if necessary, and the other node who has received the EXER request checks its own APS process. If it is checked whether the APS process is performed normally, the other node makes a previously defined response, thereby indicating the operational status of the other node's APS process.
ITU-T recommendation G.8031 which has been published in 2006 defines NR (No Request) or DNR (Do Not Revert) in response to the EXER request. However, since NR or DNR may be confused with a response that is normally received from another node, NR or DNR is being modified by defining a new response that is called RR (Reverse Request) so that RR can be distinguished from other responses.
However, such a modification conflicts with the operation of the conventional APS process because the priority of a response to the EXER request becomes high.
In the conventional APS process, the priority of a status or request of a node of APS process own (hereinafter, referred to as a local request) is compared with the priority of a status or request that is received from another node at a far end of the protection domain (hereinafter, referred to as a far end request) and whichever request has the higher priority is considered as a final request (hereinafter, referred to as a global request), as illustrated in FIG. 1.
For example, both ends of the protection domain are set in a non-revertive mode, and a failure occurs in the working transmission path, and the data transmission path is changed to the protection transmission path, and the failure in the working transmission path is being recovered. If the switched state is maintained, a DNR request is transmitted to another node at a far end of the protection domain, even though the working transmission path is being recovered. In this situation, if one node transmits the EXER request the other node at the far end of the protection domain, the other node checks its own APS process and sends a RR response. Then, the EXER request is revoked and the DNR request is returned, and the other node also revokes the RR response and must also send the DNR request.
However, as illustrated in FIG. 2 which relates to priorities of each request and status defined in ITU-T recommendation G.8031, since the priority of RR is higher than that of DNR, it is not possible that the RR response is revoked and returned to the DNR request.

Operational status testing apparatus and method for Ethernet-based automatic protection switching process

Electronics and Telecommunications Research Institute


A drive voltage supply circuit has a first wire line, a second wire line, a first drive circuit, a plurality of second drive circuits, a control circuit for driving the first drive circuit and the plurality of second drive circuits, and an impedance element connected between the first wire line and each of output terminals.

The present invention relates to a semiconductor integrated circuit and, more particularly, to a drive circuit used in a multi-channel semiconductor integrated circuit for driving a capacitive load such as a plasma display.
A conventional drive voltage supply circuit used in a multi-channel semiconductor integrated circuit will be described with reference to the drawings (see, e.g., Japanese Patent Application No. 2003-362063 (FIG. 4)).
FIG. 12 shows a structure of the conventional drive voltage supply circuit in a multi-channel semiconductor integrated circuit.
The drive voltage supply circuit shown in FIG. 12 comprises: a shift register 1 consisting of a plurality of latch circuits 1a; a gate circuit 2; a level shift circuit 4 connected to a power source terminal 9 and outputs a signal having the same polarity as an input thereto and a voltage obtained by shifting the voltage of the input; a high-side drive circuit 7 composed of a high-side transistor 3 controlled by the level shift circuit 4; low-side drive circuits 8 each connected between a common connection terminal 13 and a GND terminal 10 and composed of a low-side transistor 5 and a diode 6; and load capacitances 14 connected between the respective output terminals 11 of the low-side drive circuits 8 and a GND terminal. In FIG. 10, parasitic diodes 3a and 5a are shown individually for the high-side transistor 3 and the low-side transistors 5.
As shown in FIG. 12, it is assumed that, when a specified one of the plurality of low-side drive circuits 8 is mentioned, e.g., when the first one of the low-side drive circuits is mentioned, it will be hereinafter denoted as "low-side drive circuit 8(1)" and, when all or any of the low-side drive circuits are mentioned, they will be hereinafter denoted as the "low-side drive circuits 8". The same notation shall apply to the low-side transistors 5, the diodes 6, the output terminals 11, the load capacitances 14, latch circuits 1a, and the parasitic diodes 3a and 5a which are the components of the low-side drive circuits 8.
Outputs Q which are sequentially outputted from the latch circuits 1a(1) to 1a(4n−3) each composing the shift register 1 are supplied to the gate circuit 2. An output signal from the gate circuit 2 is supplied to the level shift circuit 4. An output signal from the level shift circuit 4 controls the high-side transistor 3. On the other hand, the outputs Q which are sequentially outputted from the latch circuits 1a(1) to 1a(4n−3) control the low-side transistors 5(1) to 5(4n−3). By thus controlling the high-side transistor 3 and the low-side transistors 5, the states of the output terminals 11 are sequentially switched.
The conventional drive voltage supply circuit used in a multi-channel semiconductor integrated circuit has the structure in which the high-side transistor is shared by the plurality of low-side transistors. Accordingly, when the low-side transistor connected to a given one of the output terminals is ON, even though the low-side transistors connected to the other output terminals are OFF, the high-side transistor is turned OFF for the purpose of preventing a through current from flowing between the power source terminal and the GND terminal. In this manner, a path along which charge propagates is cut off by producing a high impedance state (hereinafter referred to as HIZ) so that the H level is maintained as a signal level at each of the output terminals. However, there has been a problem that, because of the HIZ state, an incoming disturbance causes an oscillation in the potential at any of the output terminals and the H level cannot be maintained any more.
A description will be given herein below to the problem of the oscillation in the potential at the output terminal caused by the disturbance in the HIZ state by using a case with a plasma display panel (hereinafter referred to as the PDP) as an example.
As shown in FIG. 13, the PDP comprises three electrodes which are a scan electrode 200, a sustain electrode 201, and a data electrode 202. Because each of the electrodes 200 to 202 is covered with a dielectric material, when viewed equivalently, it follows that capacitances 203, 204, and 205 are connected respectively between the electrodes 200 and 201, between the electrodes 201 and 202, and between the electrodes 200 and 202, as shown in FIG. 13. Accordingly, the output load of each of the drivers of the PDP becomes a capacitive load.
As shown in FIG. 13, a high-side transistor 208 and a low-side transistor 209 are connected between a power source terminal 206 and a GND terminal 207. When the low-side transistor 209 is OFF, the high-side transistor 208 is turned ON, whereby a H-level voltage is outputted to the scan electrode 200. Conversely, when the low-side transistor 209 is ON, the high-side transistor 208 is turned OFF, whereby a L-level voltage is outputted to the scan electrode 200. To each of the sustain electrode 201 and the data electrode 202 also, the H-level or L-level voltage is outputted with the same structure (a high side transistor 211 and a low-side transistor 212 each provided between a power source terminal 210 and a GND terminal 217 are connected to the sustain electrode 201, while a high-side transistor 215 and a low-side transistor 216 each provided between a power-source terminal 213 and a GND terminal 214 are connected to the data electrode 202) and under the same conditions as used for the scan electrode 200. In FIG. 13, the respective parasitic diodes (208a, 209a, 211a, 212a, 215a, and 216a) of the high-side transistors (208, 211, and 215) and the low-side transistors (209, 212, and 216) are shown.
Next, as an example of a disturbance (noise) resulting from the operation of an output signal from the data electrode 202, an oscillation caused by the disturbance in the output potential at the scan electrode 200 will be described herein below.
As shown in FIG. 14, when a data waveform applied to the data electrode 202 shifts from the L level to the H level at the time t1 and shifts from the H level to the L level at the time t2, noise enters the scan electrode 200 via the capacitance 205 to cause an undesirable oscillation in the potential at the scan electrode 200. In this case, when the high-side transistor 201 is ON, there is no problem because the oscillated potential at the scan electrode 200 returns to the same H level as the potential at the power source terminal 206 in a very short period of time. However, when each of the high-side transistor 208 and the low-side transistor 209 is OFF, the scan electrode 200 is in the HIZ state so that a path along which charge propagates is cut off. As a result, the noise from the data electrode 200 that has entered the scan electrode 200 via the capacitance 205 causes the oscillation in the potential at the scan electrode 200.
For example, as shown in FIG. 14, when the potential of the scan waveform applied to the scan electrode 200 oscillates to the H side at the time t1, it oscillates only to the level of a voltage (VDDH+VD) obtained by adding a forward voltage VD equivalent to the parasitic diode 208a to the power source voltage at the power source terminal 206. However, when the potential at the scan electrode 200 oscillates to the L side at the time t2, it undesirably oscillates to the level of a voltage (−VD) obtained by subtracting a forward voltage VD equivalent to the parasitic diode 209a from the voltage (VGND=0) at the GND terminal 207. As a result, the potential at the scan electrode 200 cannot retain the H level (power source voltage) and shifts to the L level.


This invention relates to a cryogenless superconducting magnet system of the type that is attached to a utility grid at end-user site and is used to store electrical energy until such time that an electrical disruption occurs in the grid. Structures of this type, generally, allow the stored electrical energy to be released in such a manner that the disruption in the utility grid is negated before it reaches critical loads.

1. Field of the Invention
This invention relates to a cryogenless superconducting magnet system of the type that is attached to a utility grid at end-user site and is used to store electrical energy until such time that an electrical disruption occurs in the grid. Structures of this type, generally, allow the stored electrical energy to be released in such a manner that the disruption in the utility grid is negated before it reaches critical loads.
2. Description of the Related Art
Today, low power electronic systems are being used increasingly as controllers for much larger mechanical/electrical machinery. A wide variety of industries across the country are finding that these automated electronic equipment--including adjustable-speed drives, programmable logic controllers and power supplies in computers--are vulnerable to overvoltage, undervoltage, momentary interruptions and other disturbances that have always existed in the utility power line. Much of this advanced equipment also generates disturbances back onto the utility line. Therefore, a more advantageous system, then, would be presented if such amounts of these various electrical disturbances were reduced.
It is apparent from the above that there exists a need in the art for a superconducting magnet which is capable of negating various electrical disruptions before they reach critical load, and which at the same time at least equals the superconducting characteristics of known superconducting magnets. It is a purpose of this invention to fulfill this and other needs in the art in a manner more apparent to the skilled artisan once given the following disclosure.

Superconducting magnetic energy storage device


A system and methodology for parallel processing of continuous data streams. In one embodiment, a system for parallel processing of data streams comprises: a converter receiving input streams of data in a plurality of formats and transforming the streams into a standardized data stream format comprising rows and columns in which values in a given column are of a homogeneous type; a storage system that continuously maintains a finite interval of each stream subject to specified space limits for the stream; an interface enabling a user to construct parallel stream programs for processing streams in the standardized data stream format, wherein a parallel stream program comprises a linear sequence of program building blocks for performing operations on a data stream; and a runtime computing system running multiple parallel stream programs continuously on the streams as they flow through the storage system.

1. Field of the Invention
The present invention relates generally to replication of information in data processing environments and, more particularly, to systems and methodologies for analyzing, filtering, enhancing and processing streams of data.
2. Description of the Background Art
Stream processing is concerned with filtering, enriching and enhancing continuous data streams. In order to detect opportunities and threats as early as possible, stream processing systems often need to analyze complex, fast moving, heterogeneous streams of data in real-time. In many cases, they also need to be able to rapidly process historical streams. For example, the ability to rapidly process and analyze historical streams of data is useful in refining trading strategies in the financial services sector. Stream processing software and systems need to run continuously, providing analytics, statistics, filtering, inference, deduction, connection, pattern matching, tracking and tracing.
Stream processing is complementary to databases, data warehousing, data mining, and search engines. The emphasis in stream processing is on continuous time-based information, on time-critical analysis, and often on situations where most of the data is irrelevant to most people most of the time. In stream processing, one is often looking to pinpoint a rare and important opportunity or threat, without drowning in the relentless flow of data that is typically received by most users and organizations.
Processing of real-time and historical data streams is a critical component of information technology solutions in many application areas, including the following:
Applications in which continuous live data streams from people, sensors, systems and networks are automatically monitored, filtered, analyzed, enhanced and enriched in real-time.
Systems where continuous analytics on massive volumes of real-time data enable businesses and financial services organizations to intelligently discover and immediately respond to opportunities and threats, manage risk, ensure compliance, and deliver the best possible personalized customer experience at all times.
Solutions wherein continuous inference on semantic graphs allows intelligent real-time discovery of deep and important connections within live data streams.
Applications involving continuous real-time analysis of streams of data from networked wireless sensors, such as those that will enable a new intelligent, secure, optimized and highly energy-efficient infrastructure—a new generation of smart buildings, homes, factories, utilities, energy networks, IT systems, data centers, networks and other equipment, each with always-on energy saving, intrusion prevention, and predictive maintenance capabilities.
Solutions utilizing continuous real-time intelligent tracking and tracing (GPS, RFID) enabling powerful new location-based services to be launched, theft and counterfeiting to be reduced, and transportation and distribution to be optimized.
The following is a list of specific application areas that may involve stream processing, although it is by no means a complete list:
Business (Dynamic Pricing, Mobile Advertising, Customer Experience Management, Supply Chain, Logistics, Marketing Intelligence, Risk Management, Compliance, Counterfeit Prevention).
Web and Telecommunications (Marketplaces, Online Games, Social Networks, Personalized Newsfeeds, Semantic Web, Virtual Worlds, Location-Based Services, Fraud Prevention).
Government (Homeland Security, Intelligence, Defense, Compliance).
Financial Services, Banking and Insurance (Algorithmic Trading, Risk Management, Compliance Tracking, Live Oversight, Fraud Prevention, News Services).
Machine-to-Machine Computing (Sensors, Smart Buildings, Remote Monitoring, Predictive Maintenance, Intrusion Prevention, Location Tracking, RFID, Process Control and Optimization, System and Network Monitoring).
In areas such as financial services and government applications, a number of products have been developed which permit the application of rule-based systems (expert systems) to event streams. U.S. Pat. No. 6,782,381 (Method and apparatus for evaluating queries against received event information, Nelson, Giles John et al.), the description of which is hereby incorporated by reference, describes one such approach to rule-based stream processing. United States Patent Application 2004/0220921 (Time series monitoring system, Billock, Joseph Greg et al.), the description of which is hereby incorporated by reference, describes another rule-based approach to event processing. The various rule-based event processing products aim to provide complete applications for complex event processing by coordinating analysis across multiple simultaneous event streams, external databases and spreadsheets, by merging streams, triggering the addition of new compound events and so on. The general technical approach involves using open-ended rule-based expert systems that check against patterns for matches and applying logic such as "when pattern matches, do_action_a, do_action_b, etc.". However, these rule-based expert systems have a number of limitations in processing of data streams. For example, with such systems it can be complex to express even rather simple stream processing applications where the aim is to filter and enrich a stream by partitioning it into a large number of substreams, computing substream properties across various time-based windows, then interleaving the resulting substreams to produce a filtered and enriched output stream. For applications of this kind, it would be desirable to have a solution providing the functionality and structuring of a carefully designed domain-specific programming language, rather than an open-ended rule-based system. Another limitation of rule-based expert systems concerns parallelization. Handling large-scale stream processing applications requires the ability to easily and automatically parallelize stream processing algorithms and programs. In contrast to domain-specific programming languages, rule-based expert systems do not provide a framework in which automatic and efficient parallelization for large-scale implementation can be easily achieved.
In recent years, a number of database research teams in universities have been adapting database techniques in general, and the SQL query language in particular, in order to perform certain types of stream processing (e.g., merge, join, sort, select) across multiple streams of structured data. For a recent example, see, e.g., Yijian Bai et al. "A Data Stream Language and System Designed for Power and Flexibility" in Proceedings of the 15th ACM Conference on Information and Knowledge Management (November 2006), the disclosure of which is hereby incorporated by reference. Several of these research projects have led to commercial products. However, these commercial solutions rely on the use of a database query language (e.g., SQL), and provide for adapting the database query language for use in stream processing. This results in some tradeoffs and inefficiencies in the use of a language that was designed for a different purpose than stream processing.
Keyword-based publish-subscribe systems have also been used for many years to disseminate real-time news to users based on preset subscriptions. Recently, various academic projects have worked to extend the traditional publish-subscribe model in various ways, to give it more expressive power. For example, the Cayuga project combines publish-subscribe automata with a SQL style query language for stream processing on multiple streams (for further description of Cayuga, see e.g., Alan Demers et al. "Cayuga: A General Purpose Event Monitoring System" in Proceedings of the Third Biennial Conference on Innovative Data Systems Research, Asilomar, Calif. (January 2007), the disclosure of which is hereby incorporated by reference). In a similar manner, the SASE project combines database techniques and a rule-based approach to produce an event processing architecture (for further description of the SASE project, see e.g., Eugene Wu et al. "High-Performance Complex Event Processing over Streams", in Proceedings of the ACM SIGMOD Conference, pages 407-418 (June 2006), the disclosure of which is hereby incorporated by reference).
Since the 1970s, general-purpose dataflow programming languages have been used for stream processing of various kinds. Moreover, some dataflow languages are currently being used for certain kinds of real-time stream processing applications. For example, the real-time dataflow language Lustre (the kernel language of the SCADE (formerly SAO+/SAGA) industrial environment) from Esterel Technologies can be used for critical control software in aircraft, helicopters, and nuclear power plants (for further description of Lustre, see e.g., N. Halbwachs et al "The synchronous dataflow programming language Lustre", in Proceedings of the IEEE, 1991, pages 1305-1320 (1991), the disclosure of which is hereby incorporated by reference). To achieve the strict real-time requirements of such applications, the design of Lustre programs can be quite complex, involving detailed analysis of clock synchronization amongst multiple streams.
Batch stream processing architectures such as Hancock have been developed to provide offline (non-real-time) processing of huge repositories of historical stream data, such as phone call records (for further description of Hancock see, e.g., Corinna Cortes et al. "Hancock: A Language for Analyzing Transactional Data Streams" in ACM Transactions on Programming Languages and Systems, Vol. 26, No. 2, pages 301-338 (March 2004), 1-338, the disclosure of which is hereby incorporated by reference).
IBM's System S Research Project is developing a prototype aimed at providing the "middleware" required to coordinate a wide range of distributed stream processing applications. The System S research project aims to produce a stream processing framework that is general-purpose. System S assumes that there are many user-developed stream processing components in use across the Internet, and that the main goal of the System S Stream Processing Core is to provide middleware coordination software that can tie these numerous components together in useful ways. However, System S does not provide a system and method that can be used to build a scalable stream processing architecture.
GigaSpaces of New York, N.Y. offer a product allowing users to offload data from Microsoft Excel to the GigaSpaces in-memory data grid, in order to be able handle larger amounts of data within Excel spreadsheets. They also provide a means of offloading parts of an Excel spreadsheet calculation to an external grid of servers, increasing the computation power available to perform standard spreadsheet calculations. While useful in terms of increasing the computation power and storage available for spreadsheet computations, these products do not offer any capability to perform real-time stream processing on data streams. The Excel spreadsheet model does not provide that capability, nor does the GigaSpaces parallel implementation of Excel.
Mashup editors, such as Yahoo Pipes allow users to combine web data from various sources using sorting, filtering and translation modules, in a way that is similar to the way in which Unix pipes are used to connect primitive Unix library functions. Yahoo Pipes is a web application (available from Yahoo!, Inc. of Sunnyvale, Calif.) that provides a composition tool to aggregate, manipulate, and mashup content by letting users "pipe" information from different sources (e.g., web feeds, web pages, and other services) and set up rules for how that content should be manipulated (e.g. filtering). Like Unix pipes, Yahoo Pipes permits simple commands can be combined together to create output meeting user needs. However, mashup editors such as Yahoo Pipes are not well suited for stream processing, in that they do not handle continuous data streams. The Yahoo Pipes user interface is typical of most visual programming tools, in that much of the complexity of the interface stems from the need to show the often complex mesh of wires connecting the building blocks. This visual complexity presents a major obstacle to the scalability of the approach for complex applications. It would be preferable to have a solution that was "wire-less", offering a powerful and highly scalable interface for complex stream processing applications.
Many modern software systems require mechanisms for the transformation and querying of XML streams. In recent years, a large number of software tools have been developed for the processing of XML streams, based on languages such as XPath, XSLT and XQuery. United States Patent Application 2004/0205082 (System and method for Querying XML streams, Fontoura, Marcus et al.) describes one such approach to XML processing. Open source software tools such as the SAXON XSLT processor (authored by Michael Kay and available from Saxonia.com of Reading, United Kingdom) provide extensive support for handling XML data. However, they do not provide a general-purpose solution for handling data that is not in XML format.
What is needed is a solution that is specifically designed for general-purpose stream processing. The solution should have the ability to handle all kinds of streaming data, including tables, text, feeds and graphs. Ideally, the solution should facilitate real-time processing applications requiring complex combinations of analysis, statistical monitoring, filtering, tracking and tracing, inference, deduction and pattern matching. The present invention provides a solution for these and other needs.

System and methodology for parallel stream processing


A composite metallic cast article (A) includes a shell (28) having a predetermined solid phase density. A non removable insert (24) is at least partially embedded within the shell (28). The insert (24) is fabricated from a foamed metal substance having a substantially lower solid phase density than the shell (28). The foamed metal insert (24) may have a layer of skin (26) fused with the molten metal of the shell (28) during the casting process. Tapered locating pins (30) or other spacing elements position the insert (24) within the mold cavity (18) to prevent shift during the casting operation. The foamed metal insert (24) reduces the time and expense involved in removing a traditional casting core after the casting operation is complete. Also, the insert (24) can be completely enclosed within the shell (28) of the article (A), thereby expanding the design capabilities of such cast articles (A). Furthermore, the foamed metal insert (24) provides better stiffness and energy absorbsion to the cast article (A) when compared with a hollow cavity section formed by a core of the prior art.

Metal casting processes, and in particular aluminum and magnesium casting processes, are often used to create a finished object having a hollow interior cavity. This is done primarily to reduce the weight of the finished article and to reduce cost by conserving casting material.
Hollow interior cavities are formed by placing a core in a casting mold prior to introducing the molten metal. After the molding operation, the core is removed by either disintegration (in the case of resin bonded sand cores), melt-down (in the case of metallic cores) or other techniques known to those skilled in the art. This core removal process is time consuming and sometimes expensive depending upon the type of core material used and the removal process employed.
Another drawback of this metal casting process is that the interior cavity must be partially exposed or else a passage must be provided for removal of the core after the casting process is complete. Therefore, the design of the interior cavity shape and placement of the cavity are often dictated more by considerations of core removal than of application and performance of the article in use. Furthermore, while the prior art hollow interior cavity is effective in reducing weight and material costs, it provides no structural support to the article.

Method of making a casting having a low density insert


A vacuum modulating air control valve includes a valve body with air intake ports, an output port, and a valve throat. A valve member is slidably mounted within the valve body between open positions relative to the valve throat and a closed position, to which the valve member is urged by a valve spring. A pneumatic cylinder has a piston forming a vacuum chamber and has a piston rod connected to the valve member. The output port is connected to a feedpoint of a vacuum conveying system, and the vacuum chamber is connected to a vacuum line communicating with the vacuum conveying system. A vacuum level within the vacuum chamber retracts the valve member from the throat, thereby admitting ambient air into the vacuum conveying system to control a material-to-air ratio within the system.

The present invention relates to pneumatic conveying systems and, more particularly, to a vacuum modulating air control apparatus which controls aspects of operation of a vacuum pneumatic conveying system.
Pneumatic conveying systems are frequently used for conveying bulk particulate materials for processing such materials or for feeding such materials into processes which use the materials. So-called dense phase pneumatic conveying systems operate below the minimum suspension velocity for a given material and are characterized by the product moving along the bottom of a pipe in "slugs" or a moving bed. The product is conveyed at high differential pressures below its saltation velocity, that is, the gas flow velocity below which the material begins to settle out of the gas flow. Conveying velocities are typically less than 2600 FPM (feet per minute), and material-to-air ratios of up to 100 to 1 are possible. Interaction of the particles in a dense phase system is greater than in a dilute phase conveying systems. Common applications for dense phase conveying systems include products with heavy bulk-densities, abrasive products, friable products, blended products, and, in some instances, products that do not require continuous delivery to their destinations.
Vacuum dense phase pneumatic conveying systems employ high vacuum pumps and special feeding mechanisms to form moving slugs of material which are conveyed at sub-atmospheric pressures. The result is minimized pipe friction and maximum protection of the product for multiple applications. Products commonly conveyed in vacuum dense phase systems include: friable products, blended products, and abrasive materials. These products may include sugar, pet food products, carbon black prills, plastic pellets, detergents, and the like. Depending on the product to be conveyed, variations in the configuration of the conveying system may be necessary with respect to such features as size and material characteristics of conveying conduits, structural support of the conduits, vacuum levels, conveying velocities, and the like.
There are two conventionally used methods for feeding products to be conveyed into a vacuum conveying system. In one method, an impulse valve alternates between drawing material and air into the conduit on a timed basis to create the desired material-to-air ratio. In a second method, a series of static bleed valves is used to balance the ratio of material and air.

Vacuum modulating air control valve apparatus


A manufacturing assembly is disclosed for manufacturing a disk drive. The manufacturing assembly comprises a pre-merge arm having a contact surface for contacting an actuator arm of the disk drive, and an actuator operable to actuate the pre-merge arm. When installing the actuator arm into the base of the disk drive, the actuator is operable to actuate the pre-merge arm in a first direction so that the contact surface biases the actuator arm rotationally about a pivot to bias the lift tab away from the ramp. After installing the actuator arm into the base of the disk drive, the actuator is operable to actuate the pre-merge arm in a second direction opposite the first direction so that the lift tab moves towards and contacts a ramp near an outer periphery of a disk.

1. Field
The present invention relates to manufacturing disk drives for computer systems. In particular, the present invention relates to a manufacturing assembly for manufacturing a disk drive.
2. Description of the Related Art
Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. When the disk drive is powered down or idled, the head is typically parked either on a landing zone of the disk, or on a ramp near an outer periphery of the disk. In disk drives that employ ramp loading/unloading, the actuator arm comprises a "lift tab" that extends out over the head which contacts and slides along the ramp. During manufacturing, a head stack assembly (HSA) comprising an actuator arm is installed into the base of the disk drive, and then rotated so that the lift tab makes initial contact with an outer edge of the ramp during a "pre-merge" operation. Thereafter a "merge" operation is performed to further rotate the actuator arm so that the lift tab slides further onto the ramp and into a parked position on the ramp.
In a prior art technique for manufacturing the disk drive, a "gripper" tool grips the HSA, removes the HSA from a tray, and then inserts the HSA into the base of the disk drive. A screw is then driven through the bottom of the base into the pivot of the HSA in order to secure the HSA to the machined, level surface of the base. Once the HSA is secured to the base, the gripper releases the HSA allowing it to rotate about the pivot until the lift tab contacts the outer surface of the ramp. Screwing the HSA to the base before releasing the gripper helps ensure the HSA rotates in a near perfect horizontal plane which prevents damage to the head as the lift tab contacts the outer edge of the ramp. However, driving a screw through the bottom of the base to secure the HSA increases the cost and complexity of manufacturing the disk drive.
There is, therefore, a need to reduce the cost and complexity of manufacturing a disk drive while maintaining adequate yield.

Manufacturing assembly for manufacturing a disk drive


A cable assembly includes a pair of cover halves which are mated with each other, and together define a receiving space, and a rib inwardly extending from inner surface of the cover halves, a cable with a stress relief integrally molded thereon, each cover half includes at least a hollow column extending toward the receiving space, and the stress relief includes a slot fitly engaged with the rib, and a securing head ahead of the annular slot, the securing head defines a through hole, a hollow column in one cover half extends through the through hole and engages with the other column of the other cover half by an exterior element.

1. Field of the Invention
The present invention is directed to a cable assembly, and more specifically, to a cable assembly with improved stress relief that is suitable for use in data or audio communication applications.
2. Description of Related Arts
In the past, flexible cable is commonly used in date transmission and integrally attached to a plug to form a cable assembly, for achieving interconnection between two electrical applications when the plug is engaged with a mating plug. However, practice has shown that a signification portion of the data or signal loss and/or distortion occurs at the areas with the highest stress, due to flexing, tension or torsional twisting, on the flexible cable. And, such stress also can lead to misalignment of the wires contained in the cable.
One transitional method to minimize the stress associated with such cable is to incorporate some form of stress relief into the cable assembly. And, traditional stress relief members, often acting only as a cover or protective plate, are incorporated with the cable by an injection molding process or assembly. However, this incorporation may be loose and departed from each other, when the cable suffers from excessively torsional twisting or tension. Further, even through a stress relief is provided, a distortion also can happen in joint between the cable and the plug, for the cable driving the stress relief to turn excessively.
Hence, a cable assembly having improved stress relief is desired.

Cable assembly with improved stress relief


An ATM network is coupled to a data warehouse. Information about transactions, the timing of transactions and advertisements displayed on or near ATM terminals in the network are stored in the data warehouse. Complex queries performed on the data warehouse are then used to provide information about the effectiveness of advertisements displayed on or near the ATM terminals and also to enable choices of subsets of the terminals to be made to provide information about suitable subsets for advertising placement.

This invention relates to methods of analyzing a self-service network, selecting advertisements for self-service terminals, to a data warehouse and to a self-service terminal.
As self-service terminals such as automated teller machines (ATM) become more sophisticated, an opportunity is provided for displaying increasingly sophisticated advertisements on (or adjacent) the ATM. For example, self-service ATMs increasingly are able to display fill motion video and Internet content in addition to being able to print information. Thus, during the time taken to authorize a transaction (which is typically of the order of a few and maybe several tens of seconds) advertisements may be displayed on the terminal display means or printed during and/or after a transaction. Such advertisements may generate revenue to support the cost of providing the ATM network.
In common with other advertising media such as radio and television, it is necessary to survey the effect of the advertisement in order to select appropriate advertisements and also to provide potential advertisers with information on which to make their placement decisions.
Presently, a few organizations collect information from ATM deployers about their ATM fleets, aggregate it and produce anonymized reports outlining trends and statistics in the use of self-service ATM terminals. However, this type of report is prepared manually and thus there is a time lapse of weeks or months between data gathering and report finalization and furthermore, there is no possibility of re-defining the way the report is presented such as by performing personalized queries on the data. Also, the reports are prepared based on a plurality of deployer's ATM fleets and thus do not relate to a particular fleet. Thus such reports are not suitable for selecting advertising content to be displayed on ATM self-service terminals.

Self-service terminals and self-service networks


Disclosed is a process for making an aromatic nitrile by reacting a benzotrichloride with an ammonium halide in the presence of an oxygen-donating initiator at a temperature of about 150.degree. to about 250.degree. C. An optional catalyst of a metal oxide or a metal salt can be used if desired.

This invention relates to a process for making an aromatic nitriles from a benzotrihalide and an ammonium halide. In particular, it relates to such a process in which a small amount of an oxygen-donating initiator is used.
Aromatic nitriles are important intermediates in the dye and pharmaceutical industries. At the present time, benzonitrile and chlorinated benzonitriles are made on an industrial scale by reacting benzotrichloride or a chlorinated benzotrichloride, respectively, with ammonia gas, ammonium hydroxide, or ammonium chloride in the presence of a catalyst such as ferric chloride, zinc chloride, copper chloride, or copper oxide. While these reactions produce the desired product, they also produce unwanted byproducts, such as tar residues, resulting in a significant amount of solid waste. Also, some of the reactions have been found to selectively form triazine in the presence of catalysts such as ferric chloride.


An image forming apparatus for forming a toner image on a peripheral surface of an image carrying drum and transferring the toner image onto a recording paper. The image forming apparatus comprises a conveyor to convey the recording paper, a register roller to feed the same to the conveyor, transfer unit for transfering the toner image and a pre-charging unit for charging the recording paper before the transferring. A controller of the image forming apparatus controls operation timings of the above units of the image forming apparatus and forms a blank area in the leading portion of the recording paper where no image is formed and no transfer operation is performed to the recording paper by the transfer unit.

The present invention relates to an image forming apparatus such as an electrostatic copier provided with a transfer belt unit which supports and conveys a transfer sheet electrostatically, transfers a toner image formed on an image carrier onto the transfer sheet, and conveys the transfer sheet to a fixing means.