Mobile units within an area are located using a wireless local area network. Reference signal transmitters are provided at selected fixed locations within the area. Reference signals are transmitted using the reference signal transmitters using a first selected channel of the wireless local area network. A computer is provided having a database relating signal characteristics of signals transmitted by the reference signal transmitters to location within the area At least one access point is coupled to the computer and provides wireless data communications between the computer and the mobile unit using one or more channels of the wireless data communications system that are different from the first data communications channel. A selected plurality of the reference signals are received at the mobile unit, signal characteristics of the received reference signals are determined and data representing the received reference signal characteristics is transmitted to the computer via the access point using the one or more data communications channels. The data representing reference signal characteristics is received at the computer and position of the mobile unit is determined using the database.

This invention relates to wireless data communications systems and particularly to wireless data communications systems which include arrangements for locating mobile units within the area serviced by the system.
The use of mobile data communications systems to perform location functions for locating mobile units is described in articles entitled Enhancements to the User Location and Tracking System, by Paramvir Bahl and Venkata N. Padmanabhan, and User Location and Tracking in an In-Building Radio Network, Microsoft Technical Report MSR-TR-99-12, dated February 1999, by the same authors, both published by Microsoft Research. As described therein signal strength of signals of the wireless data communications system, such as a system using the protocol of IEEE Standard 802.11, are used for locating mobile units within an area serviced by the system. Other techniques for locating mobile units using the wireless data communications systems or other location system are possible.
In co-pending application Ser. No. 09/528,697, filed Mar. 17, 2000, which is owned by the assignee of the present application and incorporated herein by reference, there is described a system which follows the protocol of IEEE Standard 802.11, but which uses a combination of RF Ports and Cell Controllers to perform the functions of Access Points of a classical 802.11 data communications system. Lower level MAC functions are performed by the RF Ports and higher level MAC functions, including association and roaming functions, are performed by the cell controller. The term "access point" as used herein is intended to include conventional access points, such as those which follow the protocol of IEEE Standard 802.11 and perform all MAC functions, as well as RF Ports operating with cell controllers, as described in the incorporated co-pending application.
One problem associated with locating mobile units using a wireless local area network system is the comunication burden the location function can put on the system. In a passive system wherein mobile units periodically listen for beacon signals from access points or other beacon transmitters for location determination, the mobile units must monitor beacon signals on a plurality of channels, such as 11 channels for IEEE Standard 802.11 (b) systems. Considerable operating time for a mobile unit can therefore be spent for passive monitoring of 11 channels for signals, such as beacon signals, to be used for location determination. Further, such passive monitoring can reduce the amount of time a mobile unit can operate in power save mode, therefore shortening battery life. The larger number of beacon signals that are required for the location function can also increase radio interference with data communications functions. Likewise, in arrangements wherein location signals are transmitted by reference signal transmitters or access points in response to request signals transmitted by mobile units, the request signal adds to the radio background and can further burden the media and the battery requirements of mobile units.
It is an object of the present invention to provide an improved method and system for locating mobile units using a wireless data communications system.

Method and system for improved wlan location


A predriver circuit that is capable of reducing the size of a drive transistor while preventing a drive transistor's gate from being destroyed, thereby reducing power consumption. The predriver circuit includes a current mirror circuit, which has a pair of transistors that are connected to a predriver power supply voltage; a level shifter circuit, which is connected to a first transistor via a self-bias circuit; and a discharge transistor, which is connected to a second transistor. A terminal connecting the second transistor to the discharge transistor is connected to a top gate of a high-side MOS transistor for a half-bridge connected drive circuit.

A full-bridge connection, half-bridge connection, or other similar drive circuit is known as a drive circuit for driving a motor or the like (refer, for instance, to JP-A No. 82946/2000 (FIG. 3) hereafter "patent document 1"). A full-bridge connection drive circuit, which is effectively available over a wide power supply voltage range, is disclosed by Patent Document 1.
Conventionally, a half-bridge connection drive circuit 500 shown in FIG. 4 was used. The drive circuit 500 uses a connection node between a high-side MOS transistor Q1 and low-side MOS transistor Q2, for which a drain terminal is connected to the drive circuit power supply voltage VM, as an output terminal OP. These MOS transistors Q1, Q2 are power MOS transistors and have switching functions. A predriver circuit is connected to each gate in order to drive the MOS transistors Q1, Q2.
The low-side MOS transistor Q2 for the drive circuit 500 is grounded. Therefore, when a voltage of 10 V is to be applied to the gate of MOS transistor Q2 during a normal operation, a voltage Vls between 0 V and 10 V is applied to the gate of MOS transistor Q2.
Meanwhile, a source terminal of the high-side MOS transistor Q1 for the drive circuit 500 is the output terminal OP of the drive circuit 500. Therefore, the voltage Vhs to be applied to a gate of MOS transistor Q2 needs to be applied until the sum of the voltage of the output terminal OP (output voltage Vout) and the gate-to-source voltage VGS of MOS transistor Q1 is reached. The output voltage Vout varies from 0 V to the drive circuit power supply voltage VM. Therefore, when gate-to-source voltage VGS having a potential difference of 10 V is required for MOS transistor Q1 during a normal operation, a voltage between 0 V and 25 V needs to be applied to the gate of high-side MOS transistor Q1 if the drive circuit power supply voltage VM is 15 V. If, in this instance, a voltage of 25 V is applied to the gate of MOS transistor Q1 for rapid charging purposes, the gate voltage of MOS transistor Q1 may become instantaneously excessive, thereby damaging the gate.
Further, the predriver circuit shown in FIG. 4 was provided with a circuit that adjusts the voltage of top gate TG while detecting the output voltage Vout of the source terminal of the high-side MOS transistor, that is, the output terminal OP. More specifically, a source reference circuit 505, a protection circuit 506, a clamp circuit 507, and other circuits were provided between the source terminal and gate terminal of MOS transistor Q1. The source reference circuit 505 controls the voltage of the gate terminal with reference to the voltage of the source terminal. The protection circuit 506 is an ESD protection circuit that protects the predriver circuit when static electricity or the like is discharged from the output terminal OP, which is connected to an external device. The clamp circuit 507 protects the source reference circuit 505 and gate terminal when an excessive electrical stress is generated at the output terminal OP. More specifically, the clamp circuit 507 generates a current flow to decrease the potential difference, thereby reducing the electrical stress. In other words, the conventional circuitry was configured to statically provide an operating state.
However, the source reference circuit, protection circuit, and clamp circuit need to be constantly operated to protect the circuitry against a circuit stress generated during operation of the conventional predriver circuit. Thus, electrical power is constantly supplied to the source reference circuit, protection circuit, and clamp circuit. As a result, the power consumption of the conventional predriver circuit is quite high. Therefore, the conventional predriver circuit cannot be used in portable products, which have a limited power supply capacity.
The present invention has been made in view of the above circumstances and provides a predriver circuit so that achieves downsizing and power consumption minimization while preventing a drive's transistor gate from being damaged.


A driver block for a differential pin driver that supports out-of-band signaling. The driver block includes a main enable switch that is controlled by a high speed driver inhibit (DINH) signal. The main enable switch controls coupling between a main current source and a differential pin driver output stage. The main enable switch is coupled in series with an output select switch that selects between a positive output and a negative output. The driver block also includes a positive enable switch for controlling coupling between the positive output and a positive level shifter that shifts voltages of the positive output. The driver block also includes a negative enable switch for controlling coupling between the negative output and a negative level shifter that shifts voltages of the negative output.

Mixed signal integrated chips are driving increasingly higher performing applicants. Testing the chips that drive the computer systems require a wide range of escalating speeds, pin counts, analog bandwidth, resolution and timing requirements. Automated Test Equipment (ATE) ideally provides the accuracy and test coverage required for design verification while delivering high throughput and low cost for testing required in high volume manufacturing.
With the availability of more advanced chip design processes the sophistication of mixed-signal devices continues to evolve rapidly toward increased functionality and higher bandwidth. In conjunction, testing requirements are pushed toward higher speeds and greater precision in order to meet the new and evolving device test requirements.
In particular, differential signaling is used for high speed data transfer such as 3.2 Gbps or more. Differential signals can use lower voltage swings than single-ended signals. This is possible because the differential threshold in a differential receiver is better controlled than the threshold of a single transistor. The lower swing leads to faster circuits and can reduce power consumption. Differential signaling also reduces electromagnetic interference (EMI) since the opposite current carried on the two traces leads to cancellation of the electric and magnetic fields at larger distances. Similarly, differential signals are less sensitive to crosstalk.
In order to drive a differential signal, an output stage of a conventional differential pin driver 100 employs a class-A configuration with a constant current source 110, a switch 120, and two 50 ohm source resistances, as shown in PRIOR ART FIG. 1. A high voltage level signal (VIH) determines the driver output high level, and a voltage swing signal (VIS) determines the driver output swing (i.e. the current source provides a current equal to VIS/50 ohms).
However, in the configuration of FIG. 1, the driver 100 can only provide two levels: drive-high level=VIH; or drive-low level=VIH-VIS. A high speed signal DHI controls the output logic to be either high or low for each output pin (IO_P or IO_N). The configuration of FIG. 1 is inadequate for testing mixed signal devices having multi-band instrumentation at higher speeds.
As such, what is needed is a differential pin driver capable of testing mixed signal devices with advanced analog instrumentation, including multi-band analog instrumentation.

High speed, out-of-band differential pin driver


A flash EEPROM with each memory cell including a single transistor, structured, to erase only the data of a desired memory cell, such that a high voltage of 10V is applied to one of all the bit lines in each block, a ground potential of 0V is applied to one of all the word lines in a memory array and a positive potential is applied to the other word lines in a data erasing to cause a tunnel phenomenon between a floating gate and a drain of one memory cell in each of blocks constituting the memory array.

1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices, and more particularly, to non-volatile semiconductor memory devices allowing exclusive erasing of storage data of a desired memory cell.
2. Description of the Background Art
Non-volatile semiconductor memory devices, differently from volatile semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Type Random Access Memory), are characterized in that storage data is maintained after power is lost. PROM (Programmable Read Only Memory) is a representative of such non-volatile semiconductor memory devices. PROM is a non-volatile semiconductor memory device allowing users to write information therein. Typical of such PROM which have been already in the market are EPROM (Erasable and Electrically Programmable Read Only Memory) which data is written electrically and erased by ultra-violet light and EEPROM (Electrically Erasable and Programmable Read Only Memory) which data is erased and written electrically. FIG. 12 is a sectional view showing the structure of a memory cell in an EPROM. FIG. 13 is a sectional view showing the structure of a memory cell in an EEPROM.
With reference to FIG. 12, each memory cell in the EPROM includes a single FAMOS (Floating-gate Avalanche Injection MOS) transistor. The FAMOS transistor includes N type impurity regions 2 and 3 as a drain and a source formed at a P type substrate 1, a conductor layer 5 of polysilicon formed on P type substrate 1, with an oxide film 6 provided therebetween, to extend between N type impurity regions 2 and 3, and a conductor layer 4 formed on conductor layer 5 with an oxide film 7 provided therebetween. Conductor layers 4 and 5 are a control gate and a floating gate of the FAMOS transistor, respectively.
A high voltage is applied to drain 2 and control gate 4 in a data writing. As a result, a large channel current flows between drain 2 and source 3. The electric field in the channel between drain 2 and source 3 is so strong in the proximity of drain 2 that electrons in the channel are sufficiently accelerated to obtain high energy. Part of the high energy electrons (hot electrons) has higher energy than barrier energy of oxide film 6 provided between floating gate 5 and semiconductor substrate 1 in the direction of floating gate 5 due to the high potential of control gate 4. The part of the hot electrons reaching floating gate 5 are captured by the gate 5. Stop of the application of a high voltage to drain 2 and control gate 4 prevents the hot electrons from flowing to floating gate 5. With floating gate 5 being electrically insulated from control gate 4 and P type substrate 1 by insulation films 7 and 6, respectively, the potential energy of the hot electrons captured by floating gate 5 is lower than the potential energy of oxide films 6 and 7. As a result, the electrons once captured by floating gate 5 will stay there for a long time period.
Data "0" and "1" correspond to the capture of electrons by floating gate 5 and non-capture thereof, respectively.
The capture of the electrons by floating gate 5 impedes formation of an inversion layer to be generated between drain 2 and source 3. As a result, a threshold voltage of the memory cell after a data writing becomes higher than that before the data writing. Reading of the data, therefore, is executed by applying an appropriate positive voltage to control gate 4, thereby determining as to whether current flows between drain 2 and source 3. The appropriate voltage is set to be higher than a threshold voltage of an FAMOS transistor with no data written, that is, with no electron injected to floating gate 5 and lower than a threshold voltage of an FAMOS transistor with data written, that is, with electrons injected to floating gate 5. The FAMOS transistor constituting the memory cell conducts only when no electron is injected to floating gate 5, resulting in producing current flowing between drain 2 and source 3. Whether the storage data of the memory cell is "0" or "1" is determined by detecting the presence of a current flowing between source 3 and drain 2.
Such high energy ray as ultra-violet light is directed to the FAMOS transistor in a data erasing. The photoenergy of the ray excites the electrons captured by floating gate 5 to attain higher energy than the potential energies of oxide films 6 and 7. As a result, the electrons captured by floating gate 5 are discharged to control gate 4 or substrate 1.
A memory cell array of an EPROM includes FAMOS transistors each structured as shown in FIG. 12, these transistors are arranged in a matrix of rows and columns. Respective control gates 4 of all the FAMOS transistors arranged in the same row are connected to the same word line. Respective drains of all the FAMOS transistors arranged in the same column are connected to the same bit line. Voltages are applied to drains 2 and control gates 4 through the bit line and the word line. An application of a high voltage to one word line and one bit line selectively writes data "0" in a single memory cell having control gate 4 and drain 2 connected to the one word line and the one bit line, respectively. In a data erasing, the entire memory cell array is irradiated with ultra-violet ray, resulting in a total erasing made for the storage data of the whole message in the memory cell array.
With reference to FIG. 13, each memory cell of an EEPROM includes a single stacked gate transistor 10 and a single MOS transistor 11 formed on the same substrate. FAMOS transistor 10 includes N type impurity diffusion layers 2 and 3 as a source and a drain formed at a P type substrate 1, a control gate 4 and a floating gate 5. Floating gate 5 is formed on P type substrate 1 with an oxide film 6 provided therebetween to extend between drains 2 and 3. Control gate 4 is formed on floating gate 5 with an oxide film 7 provided therebetween. In this stacked gate transistor 10, oxide film 6 provided between floating gate 5 and substrate 1 has a thickness (200.ANG. or more in general) in the portion corresponding a portion between source 2 and drain 3 to prevent the tunnel phenomenon and formed to be thin (about 100.ANG. in general) in the portion corresponding to the end portion of drain 2 to cause the tunnel phenomenon. The thin portion 6b of oxide film 6 is referred to as a tunnel oxide film. On the other hand, in an stacked gate transistor (FIG. 12) for use as a memory cell in an EPROM, oxide film 6 provided between substrate 1 and floating gate 5 has an even thickness extensively (200.ANG. or more in general) to prevent the tunnel phenomenon. Data writing and erasing of the EEPROM is carried out by using the tunnel oxide film 6b.
In a data writing, a high voltage, with drain 2 as a potential side higher, is applied to the region between drain 2 and control gate 4. As a result, a high electric field of the reverse direction to that in the data writing is generated in oxide film 6b, so that the electrons of floating gate 5 tunnel through oxide film 6b to be discharged to drain 2. The electrons captured by floating gate 5 are removed therefrom. A threshold voltage of stacked gate transistor 10 with a floating gate 5 capturing electrons is higher than that of a stacked gate transistor 10 with a floating gate 5 capturing no electron as a matter of course. Data writing and data erasing for an EEPROM is also performed by changing a threshold voltage of stacked gate transistor 10 constituting each memory. Conversely, a high voltage is applied between drain 2 and control gate 4 to make control gate 4 have a higher potential in a data writing. As a result, a high electric field with floating gate 5 as a potential side higher, is generated in tunnel oxide film 6b to cause the tunnel phenomenon. That is, hot electrons generated in the proximity of drain 2 and tunnelling through oxide film 6b are injected to floating gate 5. With no high voltage applied to the region between drain 2 and control gate 4, the electrons injected to floating gate 5 will stay in floating gate 5 for a long time period as in the case of the EPROM.
Whether the storage data of the memory cell is "0" or "1" can be determined by detecting the presence of a current flowing between drain 2 and source 3 of a memory cell having control gate 4 supplied with an appropriate potential (lower than the threshold voltage of FAMOS transistor 10 having a floating gate capturing electrons and higher than the threshold voltage of FAMOS transistor 10 having a floating gate 5 not capturing electrons).
For such data erase, data write and data read done on a memory cell basis, each memory cell is provided with an MOS transistor 11. MOS transistor 11 includes an impurity diffusion layer 2 as a source which layer is formed, together with the drain of stacked gate transistor 10, at P type substrate 1, an N type impurity diffusion layer 8 as a drain formed at P type substrate 1 and a gate electrode 9 formed on P type substrate 1 to extend between impurity diffusion layers 2 and 8. Gate electrode 9 is electrically insulated from P type substrate 1 by oxide film 6.
A memory cell array of an EEPROM includes memory cells structured as shown in FIG. 13 disposed in a matrix of rows and columns, gates 9 of MOS transistors 11 constituting all of memory cells arranged in the same row being connected to the same word line and drains 8 of MOS transistors 11 constituting all of memory cells arranged in the same column being connected to the same bit line. In a data writing, a high potential is applied to control gate 4 of each of stacked gate transistors 10 and a potential equal to or higher than a threshold voltage of MOS transistor 11 and a ground potential are applied to the one word line and the one bit line, respectively. As a result, data is written only the memory cell having gate 9 and drain 8 connected to the one word line and the one bit line, respectively. In a data erasing, control gates 4 of all the stacked gate transistors 10 are grounded and a potential equal to or higher than the threshold voltage of MOS transistor 11 and a high potential are applied to one word line and one bit line, respectively. As a result, only the data of the memory cell having gate 9 and drain 8 connected to the one word line and the one bit line, respectively, is erased. In a data reading, with said appropriate potential being applied to control gates 4 of all the stacked gate transistors 10 and a potential equal to or higher than the threshold voltage of MOS transistor 11 being applied to one word line, the presence of current flowing through one bit line is detected. As a result, only the storage data is read of the memory cell having gate 9 and drain 8 respectively connected to the one word line and the one bit line.
As described above, each memory cell of an EPROM is structured by a single transistor, while each memory cell of an EEPROM is structured by two transistors. The EPROM requiring low bit cost achieves high integration density with ease, while the EEPROM requiring high bit cost does not as a result. In operation, data erasing of the EPROM is carried out by using an ultra-violet ray, while data of the EEPROM is erased electrically. As a result, the EPROM allows the total erasing of the data of all the memory cells, while the EEPROM enables selective data erasing, for example, on a byte basis.
A flash EEPROM enabling total electrical erasing of storage data of all memory cells has drawn much attention as a non-volatile semiconductor memory device other than such EPROM and EEPROM. FIG. 14 is a diagram showing the sectional structure of each memory cell in a flash EEPROM. With reference to FIG. 14, each memory cell, similar to EPROM, is structured by a single FAMOS transistor. Unlike the FAMOS transistor constituting each memory cell of the EPROM, the present FAMOS transistor, however, generally has the thickness of an oxide film 6 provided between a floating gate 5 and a P type substrate 1 set to be as small as about 100.ANG. to cause the tunnel phenomenon. In a data writing, a high voltage is applied to a control gate 4 and a drain 2 to generate hot electrons which will be injected to floating gate 5. In a data erasing, control gate 4 is grounded and source 3 is supplied with a high voltage. This causes the tunnel phenomenon between floating gate 5 and source 3 and thus electrons stored in floating gate 5 tunnel through oxide film 6 to be discharged to source 3. The film thickness of an oxide film 7 between control gate 4 and floating gate 5 is 200.ANG. or more in general to prevent tunneling.
The flash EEPROM also includes a plurality of memory cells arranged in a matrix of rows and columns, with control gates 4 of FAMOS transistors constituting the respective memory cells arranged in the same row being connected to the same word line and drains 2 of FAMOS transistors constituting the memory cells arranged in the same column being connected to the same bit line. A voltage is applied to control gate 4 and drain 2 through a word line and a bit line, respectively, in the data writing and the data erasing. In the flash EEPROM, sources 3 of the FAMOS transistors each constituting each of all the memory cells are connected to a common signal line (hereinafter referred to as a source line). In the data erasing, a high voltage is applied to the source line and all the word lines are grounded. Data erasing of the flash EEPROM is simultaneously made for all the bits as a result.
FIG. 9 is a conceptual circuit diagram showing the structure of a memory array in a flash EEPROM. For the purpose of simplicity, FIG. 9 shows a memory array including memory cells arranged in a matrix of 3 rows and 3 columns. FIGS. 10A-10D are tables showing one example of the potentials on a word line, a bit line and a source line at the time of writing data in the flash EEPROM and FIG. 11A is a table showing one example of the potentials on the word line, the bit line and the source line at the time of erasing data of the flash EEPROM. FIG. 11B is a table showing one example of the potentials on the word line, the bit line and the source line at the time of reading data of the flash EERPOM.
With reference to FIG. 9, memory cells M11, M12 and M13 in the first row each have a control gate connected to a word line WL1, memory cells M21, M22 and M23 in the second row each have a control gate connected to a word line WL2 and memory cells M31, M32 and M33 in the third row each have a control gate connected to a word line WL3. Each drain of memory cells M11, M21 and M31 in the first column is connected to a bit line BL1, each drain of memory cells M12, M22 and M32 in the second column is connected to a bit line BL2 and each drain of memory cells M13, M23 and M33 in the third column is connected to a bit line BL3. Bit lines BL1, BL2 and BL3 are connected to a node D through N channel MOS transistors Q1, Q2 and Q3, respectively. Each source of all the memory cells Mij (i=1, 2, 3:j=1, 2, 3) is connected to the same node S. Node D is supplied with a high potential and a ground potential in a data writing and a data erasing, respectively. Node S is supplied with the ground potential and a high potential in the data writing and the data erasing, respectively. Transistors Q1-Q3 are provided for selecting one of bit lines BL1-BL3 supplied with the potential of node D. Transistors Q1, Q2 and Q3 is controlled by control signals C1, C2 and C3, respectively.
For writing data in memory cell M22, for example, a logical level of control signal C2 is brought to high, while the other control signals C1 and C3 are brought to a logical low level. At the same time, a high voltage of about 12V is applied to word line WL2, while the potentials on the other word lines WL1 and WL3 are set to 0V. In other words, bit line BL2 and word line WL2 are selected. As a result, the potentials of the control gate, the drain and the source of memory cell (hereinafter referred to as a selected memory cell) M22 located at the cross-over point of the selected bit line BL2 and the selected word line WL2 become 12V, 7V and 0V, respectively, as shown in FIG. 10(A). The hot electrons generated in the proximity of the drain are injected to the floating gate, in the selected memory cell M22. The potentials of the control gate, the drain and the source of each of the other memory cells M21 and M23 connected to the selected word line WL become 12V, 0V and 0V, respectively. As a result, no hot electron to be injected to the floating gate is generated in these memory cells M21 and M23 (see FIG. 10(B)).
The potentials of the control gate, the drain and the source of each of the other memory cells M12 and M32 connected to the selected bit line BL2 become 0V, 7V and 0V, respectively, as shown in FIG. 10(C). No hot electron to be injected to the floating gate is generated in these memory cells M12 and M32. The potentials of the control gate, the drain and the source of each of memory cells M11, M13, M31 and M33 having the control gate and the drain connected to non-selected word lines and non-selected bit lines become 0V, 0V and 7V, respectively as shown in FIG. 10(D). No hot electron is generated and no hot electron is injected to the floating gate in any of memory cells M11, M13, M31 and M33. As a result, data "0" is written only in the selected memory cell M22 but not in other memory cells.
In a data erasing, all of control signals C1-C3 attain a logical high level to pull the potentials on all the bit lines BL1-BL3 to approximately 0V. As a result, the potentials of the control gate, the drain and the source of each of all the memory cells Mij become 0V, 0V and 10V, respectively, as shown in FIG. 11A. The electrons are extracted from the floating gate to the source of each of all the memory cells Mij. Although non-selected bit lines can be at a floating state, they should have a potential equal to or lower than a voltage (read voltage) to be applied to the control gate for data reading, it is set approximately 0V in practice.
In a data reading, the potential of one of control signals C1-C3 and the potential of one of word lines WL1-WL3 are brought to an ordinary potential corresponding to a high level, that is, to 5V and a lower potential of about 2V, respectively, and a ground potential are applied to nodes D and S.
For reading the data from memory cell M22, for example, a logic level of control signal C2 is brought to high, while both of the logic levels of the other control signals C1 and C3 are brought to low. At the same time, 5V is applied to word line WL2. As a result, 5V, 2V and 0V are applied to the control gate, the drain and the source of the selected memory cell M22 as shown in FIG. 11B. When the selected memory cell M22 stores data of "1", memory cell M22 is turned on to cause a current to flow from node D to node S through transistor Q2, bit line BL2 and memory cell M22. With the memory cell M22 storing data of "0", memory cell M22 remains off to cause no such current.
Out of memory cells M11-M13 and M31-M33 respectively connected to 0V word lines WL1 and WL3, the potentials of the control gate, the drain and the source of each of the two memory cells M12 and M32 connected to bit line BL2 are 5V, 2V and 0V, respectively, as show in FIG. 11C. These two memory cells M12 and M32 therefore remain OFF irrespective of their storage data. No current flows from node D to node S through either of memory cells M12 and M32.
Out of the memory cells connected to word lines WL1 and WL3, all the drains of 6 memory cells M11, M13, M21, M23, M31 and M33 connected to bit lines BL1 and BL3 are in a floating state (see FIG. 11D and 11E). Therefore, no current is generated which flows from bit line BL1 to node S irrespective of the states of memory cells M11, M21 and M31 (either in an ON state or an OFF state). Similarly, no current is generated which flows from bit line BL3 to node S irrespective of the states of the memory cells M13, M23 and M33.
Whether the current is drawn out from node D or not is determined by whether a current flowing to bit line BL2 is generated or not, that is, by the storage data of the selected memory cell M22.
A sense amplifier (not shown) detects the presence of a current extracted from node D. The detection result of the sense amplifier is taken as the storage data of memory cell M22.
As described in the foregoing, a flash EEPROM including a memory cell structured by a single transistor requires low bit cost and advantageously achieve high integration. In operation, the flash EEPROM is structured to allow the total electrical erasing to be made for the storage data of all the memory cells.
As shown in FIG. 9, a memory cell array of a flash EEPROM is constituted by a plurality of blocks in general, not by a single block. FIG. 8 is a schematic block diagram showing a typical entire structure of a flash EEPROM With reference to FIG. 8, the flash EEPROM includes, for example, a memory array 100 divided into eight blocks 101-108, source/erase circuits 110, X decoder 120, Y decoders 130 and Y gates 140, each corresponding to each of 8 blocks 101-108. The flash EEPROM further includes sense amplifier and write circuits 150 provided corresponding to 8 blocks 101-108 and input/output buffers 160 provided corresponding to sense amplifier and write circuits 150. X decoder 120 is connected to terminals A0-Am for receiving external row address signals. Y decoder 130 is connected to terminals B0-Bn for receiving external column address signals. Input/output buffers 160 are respectively connected to terminals D0-D7 for receiving write data to memory array 100 and read data from the same. In memory array 100, word lines are provided each in common for 8 blocks 101-108, while bit lines BL are provided in the same number for each of 8 blocks 101-108. Each memory cell (not shown) is provided at a cross-over point of a word line WL and a bit line BL. In memory array 100, each of 8 blocks 101-108 corresponds to one bit.
X decoder 120, in response to external row address signals from address terminals A0-Am, selects one of the word lines WL and applies a high voltage (in a data writing) of about 12V or a power source voltage of 5V (in a data reading) to the selected word line WL. X decoder 120 also applies 0V to all the word lines WL in a data erasing. Y decoder 130, in response to external column address signals from address terminals B0-Bn, outputs a signal for selecting one of the bit lines BL in each block of memory array 100. More specifically, each Y gate 140 includes one MOS transistor 180 equivalent to transistors Q1-Q3 shown in FIG. 9, for each of all the bit lines BL included in the corresponding block (one of 101-108).
Y decoder 130 supplies a gate voltage to these MOS transistors 180 in response to the external column address signals to render one of the MOS transistors 180 which are included in the respective Y gates 140 conductive and the others non-conductive. MOS transistors 180 included in each Y gate 140 are provided between the respective bit line BL included in the corresponding block in memory array 100 and the corresponding sense amplifier and write circuit 150. As a result, one of the bit lines BL in each of 8 blocks 101-108 constituting memory array 100 is electrically connected to the corresponding sense amplifier and write circuit 150 through the corresponding Y gate 140. All bit lines BL in each of blocks 101-108 are connected to source/erase circuit 110 through the same source line 170. Source/erase circuit 110 applies 0V (in a data writing and a data reading) or a high voltage of about 10V (in a data erasing) to all the source lines 170.
In a data writing, 8-bit external data is applied to data input/output terminals D0-D7. Each of data input/output terminals D0-D7 receives a data signal of any one bit of the 8-bit data. Each input/output buffer 160 buffers the data signal from the corresponding data input/output terminal (one of D0-D7) and applies the same to the corresponding sense amplifier and write circuit 150. Each sense amplifier and write circuit 150 applies a high voltage of about 7V to the corresponding Y gate 140 when the data signal from the corresponding input/output buffer 160 corresponds to the logical value of "0" and applies a low voltage of about 0V to the corresponding Y gate 140 when the data signal from the corresponding input/output buffer 160 corresponds to the logical value of "1". As a result, the external data is written only in a single memory cell in each of 8 blocks 101-108 having a control gate and a drain connected to the word line WL supplied with a high voltage by X decoder 120 and the bit line BL supplied with a high voltage by Y gate 140.
In a data reading, each sense amplifier and write circuit 150 detects the presence of a current flowing through one bit line BL electrically connected to the circuit through the corresponding Y gate 140. Each sense amplifier and write circuit 150, when it detects the current flowing through said one bit line BL, outputs a data signal equivalent to the logical value "1" to the corresponding input/output buffer 160 and when no current flowing through said one bit line BL is detected, the circuit outputs a data signal equivalent to the logical value "0" to the corresponding input/output buffer 160. Each input/output buffer 160 buffers the data signal from the corresponding sense amplifier and write circuit 150 and outputs the same to the corresponding one of data input/output terminals D0-D7.
One-bit data is simultaneously written in each of 8 blocks 101-108 constituting memory array 100 in a single data writing and 1-bit data is simultaneously read from each of the 8 blocks 101-108 in a single data reading. That is, the data writing and the data reading are carried out on a byte basis.
In a data erasing, each sense amplifier and write circuit 150 applies a low voltage of about 0V to the corresponding Y gate 140. At the same time, Y decoder 130 renders conductive all the MOS transistors 180 included in the respective Y gates 140. As a result, the storage data of all the memory cells included in all the blocks 101-108 or storage data of one block included in memory array 100 is erased in a single data erasing.
In the data writing and the data erasing, the high voltage (equal to or larger than 5V) and a normal power source voltage (5V) to be applied to the word lines, the bit lines and the source line are externally supplied to power source terminals Vpp and Vcc, respectively. In practice, a switch circuit 190 selectively supplies either of the voltages applied to power source terminals Vpp and Vcc to source/erase circuit 110, X decoder 120 and Y decoder 130. Each function portion of the flash EEPROM operates as described above in response to such external control signals as a write enable signal WE for designating a data writing mode and an erase enable signal EE for designating a data erasing mode. The external control signals are supplied to a control terminal 192.
As described in the foregoing, the storage data of all the memory cells in each block in memory array 100 is erased in a single data erasing. That is, unlike the data writing and the data reading, the data erasing is not performed on a byte basis but simultaneously for all the bits or for each of the blocks constituting memory array 100.
While the flash EEPROM with one memory cell comprising one transistor requires low bit cost and achieves high integration density, in operation, data is erased on a block basis constituting a memory array, which makes selective erase of storage data of the memory array impossible.
Conventional non-volatile semiconductor memory devices, as described above, roughly fall into an EPROM and a flash EEPROM which require low bit cost and can be highly integrated, and an EEPROM which requires high bit cost and cannot be highly integrated with ease. With a recent increase in storage capacity of a semiconductor memory device, that is, an increase in the number of memory cells included in one semiconductor memory device, there is an increasing demand for a memory cell structure requiring low bit cost and achieving higher integration with ease. The non-volatile semiconductor memory devices which are previously described have the advantage in meeting such demands. In conventional EPROM and flash EEPROM, however, data erasing is performed for all the bits at the same time or on a block basis constituting a memory array. It is therefore impossible to selectively erase storage data of one or some memory cell(s) in the memory array and rewrite the memory cells. In this respect, the EPROM and the flash EEPROM are not highly functional. On the other hand, the latter non-volatile semiconductor memory devices (EEPROM) requiring high bit cost cannot achieve higher integration with ease, while the devices are highly functional because of the data erase made on a byte basis. As described in the foregoing, none of the conventional non-volatile semiconductor memory devices has a structure which allows an increase in storage capacity and is highly functional to selectively erase storage data of an arbitrary memory cell.

Non-volatile semiconductor memory device allowing erase of storage data of an arbitrary memory cell and method of erasing data in non-volatile semiconductor memory device


An (S)-1-phenyl-2-substituted propane derivative shown by the following formula (I) ##STR1## wherein R.sup.1 and R.sup.2 represent a lower alkyl group, etc., or R.sup.1 and R.sup.2 may form together an alkylene group, etc.; R.sup.3, R.sup.4 and R.sup.5 represent a hydrogen atom, etc.; and X represents a hydroxyl group which may be protected with a protective group, or a halogen atom etc., can readily be produced (i) by permitting a microorganism belonging to the genus Torulaspora, the genus Candida, the genus Pichia or the like to act on a phenylacetone derivative and asymmetrically reducing the compound, or (ii) by sterically inverting an (R)-enantiomer. (R,R)-1-phenyl-2-(2-phenyl-1-methylethyl)amino!ethanol derivative having a high optical purity can easily be obtained from the compound of the formula (I). The ethanol derivative is useful as an anti-obesity agent and the like.

As anti-obesity agents or anti-diabetic agents belonging to a new category of agents without using insulin, 1-phenyl-2-(2-phenyl-1-methylethyl)amino!ethanol derivatives are noted since the derivatives act selectively on a .beta..sub.3 -receptor in vivo, thus having extremely low side effects. Pharmacological studies on the 1-phenyl-2-(2-phenyl-1-methylethyl)amino!ethanol derivatives have revealed that the .beta..sub.3 -action substantially depends on (R,R)-enantiomers thereof (see J. Med. Chem., 35, 3081 (1992), and U.S. Pat. No. 5,061,727). For example, the above-mentioned U.S. Patent discloses that an (R,R)-5-2-2-(3-chlorophenyl)-2-hydroxyethyl!amino!propyl!-1,3-benzodiox ole-2,2-dicarboxylic acid disodium salt has a higher activity than the corresponding (S,S)-enantiomer by a factor of 47.
For the production of an optically active 1-phenyl-2-(2-phenyl-1-methylethyl)amino!ethanol derivative, there is known an optical resolution of a racemic form or a racemate, or an asymmetric synthesis.
For example, the above mentioned U.S. Pat. No. 5,061,727 discloses a method of producing an (R,R)-1-phenyl-2-(2-phenyl-1-methylethyl)amino!ethanol derivative which comprises (1) allowing a racemic 2-amino-1-phenylethanol derivative to react with a phenylacetone derivative and sodium cyanoborohydride to produce a mixture of four species of optical isomers of a 1-phenyl-2-(2-phenyl-1-methylethyl)amino!ethanol derivative, (2) isolating and removing an (R,S)-isomer and an (S,R)-isomer from the mixture, and (3) optically resoluting an (R,R)-isomer and an (S,S)-isomer by a diastereomer method. According to this method, however, it is necessary to isolate and purify only the (R,R)-isomer from the mixture of the four species of optical isomers, therefore, the processes are complicated and the yield is decreased. Further, since large quantities of raw materials are required, the method is also disadvantageous in economical factor.
The U.S. Patent and the Journal of Medicinal Chemistry as mentioned above disclose a method allowing an (R)-3-chlorostyrene oxide derivative to react with an (R)-1-methyl-2-phenylethylamine derivative. The (R)-1-methyl-2-phenylethylamine derivative used as a raw material or reactant in the method, however, has a strong antihypnotic or arousal action and it requires a particular attention when handled, therefore is not suited for a use in commercial production. Further, a lot of steps or processes are required to obtain the above-mentioned two reactants. For instance, the (R)-3-chlorostyrene oxide derivative is prepared from an acetophenone derivative through three steps, that is, chlorination, asymmetric reduction and epoxidation, and the (R)-1-methyl-2-phenylethylamine derivative is prepared from L-DOPA through six steps, namely, introduction of a protective group into an amino group, esterification, reduction of the resulting ester, converting a hydroxyl group to a mesyloxy group, removal of the protective group and reduction.

Optically active 1-phenyl-2-substituted propane derivatives and methods of producing the same


A multi-channel power amplifier for driving a plurality of loads, each associated to a respective channel, each channel comprising a pair of operational amplifiers, first and second, one operational amplifier of each channel being connectable through switches either in a bridge configuration with the other operational amplifier or in single-ended configuration to a constant reference voltage for driving the load of the respective channel, the amplifier comprises circuit means for comparing the signal level of the channels with at least a threshold and outputting a logic control signal for the switches. A relative method of controlling a power amplifier that allows a sensible reduction of distortion at the price of a negligible increase of dissipated power is disclosed.

In many applications and primarily in audio reproduction systems, for example in car audios, HI-FI audio systems and similar apparatuses that are intrinsically compact because of stringent installation requirements, as well as in portable apparatuses, power dissipation in final power stages, often quadrupled in order to drive a pair of loudspeakers (front and rear) for each stereo channel, may create heat balance problems. For example, four 20 W amplifiers may have a power dissipation of about 4×12=48 W and because of the limited space available in certain apparatuses, such a relatively large power may be difficult to be dissipated without a significant increase of temperature within the apparatus.
On the other hand, a relatively high temperature of operation may degrade the magnetic tape of cassettes or optical disks (CD), the drives of which are often tightly fitted inside a single apparatus case.
The so-called D-type switching amplifiers are highly efficient and are considered the most appropriate type for these applications.
Unfortunately, switching amplifiers generate electromagnetic emissions that in compact apparatuses interfere with the correct functioning of other systems, reducing their performances. For these reasons, audio signals are frequently amplified using a pair of class AB power amplifiers, operating in single-ended or in bridge configuration depending on the level of the processed signal.
Class AB power amplifiers are less efficient than switching amplifiers and a common technique for reducing power consumption consists in configuring them in single-ended instead of in bridge configuration, whenever it is possible to do so. In fact, these amplifiers dissipate more power in bridge configuration than in single-ended configuration as long as the amplitude of the output signal remains smaller than the positive supply voltage. Unfortunately, it is not possible to use single-ended class AB amplifiers if the output surpasses this voltage because the output signal would be severely distorted by clipping.
Techniques for automatically switching from one configuration to the other in function of the monitored level of the signal are implemented in systems disclosed in U.S. Pat. No. 5,194,821, U.S. Pat. No. 5,365,188 and U.S. Pat. No. 5,654,688, all in the name of the same Applicant.
U.S. Pat. No. 5,194,821 discloses a bridge amplifier using a positive and a negative supply voltage sources. The amplifier may function in single-ended or in differential or bridge output configuration, depending on the level of the output signal. A comparator changes the output circuitry configuration of the amplifier from a bridge configuration to a single-ended configuration or vice versa by closing or opening configuring switches, when the output signal becomes smaller than or greater than a certain threshold voltage.
U.S. Pat. No. 5,365,188 and U.S. Pat. No. 5,654,688 disclose a single supply, dual bridge power amplifier employing a window comparator for sensing the level of input signals fed to the amplifier and driving switches that by coordinately changing state configure the amplifier in either a bridge or in a single-ended configuration.
Recently, power amplifiers with digital input and analog output have been proposed. As shown in FIG. 1, they are substantially composed of a digital block receiving digital input signals and generating corresponding output signals for driving the channels of the power stage. Even for these amplifiers it is possible to reduce power consumption, according to the techniques disclosed in the mentioned patents, using dedicated comparators contained in the power stage that configure the channels in single-ended or bridge configuration depending on the level of the output signals.
The above mentioned power amplifiers show good performances in terms of power consumption and low distortion of the output signals when they have a relatively low frequency, but it has been noticed that distortion increases progressively as the frequency of the processed signal increases.

Low distortion power amplifier and method of controlling a multi-channel power amplifier


A graphics processing unit (GPU) and a management method of the GPU are provided. The GPU includes at least one graphics engine and an engine manager. The graphics engine performs a video decoding function or a graphics rendering function according to a graphics command from a driver software. The engine manager records a workload index of each graphics engine. The engine manager also adjusts the work ability of one of or more of the at least one graphics engine according to an adjustment command from the driver software. The driver software provides the adjustment command according to the workload index.

1. Field of the Invention
The invention relates to a graphics processing unit (GPU), and more particularly to a management method of a GPU.
2. Description of Related Art
Most of electronic devices widely used today, such as smart phone, personal digital assistant (PDA), tablet computer, notebook computer, or desktop personal computer, are provided with power saving management function. In order to reduce power consumption or to reduce waste heat, these electronic devices are capable of performing power saving management to important elements such as processor, co-processor and chipset. There are currently several power saving management techniques based on a hardware mechanism, such as dynamical voltage/frequency scaling (DVFS) and clock gating. Since these power saving management techniques are based on a hardware mechanism, they are less flexible.

Graphics processing unit and management method thereof


Disclosed is a water and oil resistant agent comprising a fluorine-containing copolymer obtained by copolymerizing a (meth)acrylate monomer having a polyfluoroalkyl group having 1-6 carbon atoms, hydrophilic monomer, and monomer having an anion-donating group, which agent affords a superior water and oil resistance to a paper. The invention also discloses a process for treating a paper by the water and oil resistant agent and a treated paper thereby.

The copolymer composition comprising a long chain C6-C12 polyfluoroalkyl group (hereinafter called as "Rf group") has been utilized previously as the water and oil resistant agent for paper.
On the other hand, US EPA (United State Environment Protection Agency) pointed out that the long chain Rf group produces perfluoro-octanoic acid (hereinafter called as "PFOA") which might cause an influence on the environment.
Therefore, many efforts have been made to develop a water and oil resistant agent for paper by using a fluorine-containing copolymer having a short chain Rf group. The water resistance and the oil resistance, however, tend to decrease along with the decrease of the carbon number of the Rf group, and the water and oil resistance is not satisfactory. So, further improvements have to be made to provide a paper having an enough water and oil resistance.
Sugimoto et. al. (WO2009/057716), for example, proposed the water and oil resistant agent for paper comprising a fluorine-containing copolymer which contains, as essential polymer units, a fluorine-containing (meth)acrylate monomer having a C1-C6 Rf group, a polyalkylene glycol (meth)acrylate monomer and itaconic acid. The water and oil resistance of this agent has been improved fairy well. A further improvement, however, is still required to attain usual properties of the copolymer having a long chain Rf group.

Water and oil resistant agent for paper, treatment process and paper


Disclosed are materials and methods for performing multiplex assays for nucleic acids, in which a transponder is associated with the bead(s) forming the solid phase used in the assay, nucleic acid probes are bound to the surface of the particles, and data concerning the assay is encoded on the transponder. A dedicated read/write device is used to remotely encode or read the data.

This invention relates to materials and methods for detecting nucleic acids in samples and, more particularly, to solid phase assays wherein transponders are associated with the beads constituting the solid phase, nucleic acid probes are bound to the surface of the particles and data concerning the assay is encoded on the transponders.
Solid phase assays have been used to determine the presence of nucleic acids, including deoxyribonucleic acids (DNA), ribonucleic acids (RNA) and their modified forms. Solid-phase assays can be applied to nucleic acids either in simple buffers, or in biological fluids, such as blood, serum, plasma, saliva, urine, tissue homogenates, and many others.
In solid phase assays, small beads, or microparticles, are used as the solid phase to capture the analyte. Solid-phase microparticles can be made of different materials, such as glass, plastic, latex, depending on the particular application. Some beads are made of ferromagnetic materials to facilitate their separation from complex suspensions or mixtures.
In conventional solid-phase assays, the solid phase mainly aids in separating molecules that bind to the solid phase from molecules that do not bind to the solid phase. Separation can be facilitated by gravity, centrifugation, filtration, magnetism, immobilization of molecules onto the surface of the vessel, etc. The separation may be performed either in a single step in the assay or, more often, in multiple steps.
Often, there is a need to perform two or more different assays on the same sample, most of the time in a single vessel and at about the same time. Such assays are known in the art as multiplex assays. Multiplex assays are performed to determine simultaneously the presence or concentration of more than one molecule in the sample being analyzed, or alternatively, several characteristics of a single molecule, such as, the presence of several epitopes on a single protein molecule.
One problem with conventional multiplex assays is that they typically cannot detect more than about five analytes simultaneously, because of difficulties with simultaneous detection and differentiation of more than about five analytes. In other words, the number of different analytes that may be assayed in a single solid phase assay is limited by the solid phase.

Multiplex assay for nucleic acids employing transponders


The present invention provides a floor cleaner and a water sink structure thereof. In the present invention, a water sink is formed on a surface of a cleaning cylinder by a rotating roller, and a conventional water sink structure formed by a shell water sink and a filter screen is not required, so that the structure is simpler. Since a water outlet conduit and a water pumping conduit are arranged vertically to the surface of the cleaning cylinder, water is discharged and pumped on a surface of an outer sponge layer, the water supply and water pumping systems will not be blocked, and the water discharge effect and the water pumping effect are better.

The present invention relates to the technical field of cleaners, and in particular to a floor cleaner and a water sink structure thereof.
Floor cleaning tools used early are brooms, mops, floor wipers and the like. These tools complete the cleaning operation mainly by means of manual operations. With the progress of science and technology, people's requirements for the floor cleaning tools are also gradually increasing. Vacuum cleaners appear firstly which are energized by electric power and suck garbage, dust and the like on the floor by generating negative pressure. However, due to the limitation of their working principle, the vacuum cleaners cannot clean some garbage and dirt firmly attached to the floor, so new floor cleaners have appeared.
Automatic floor cleaning robots have gradually entered ordinary families. They not only undertake some housework, but also increase the joy of family life. A cleaning cylinder of the floor cleaner is driven to scrub the floor through the operation of the motor. The cleaning cylinder usually adopts a sponge cylinder structure. The cleaning capability of the floor cleaner is related to the thickness of the sponge cylinder. The thicker the sponge cylinder is, the stronger the cleaning ability is. Meanwhile, the floor cleaner is also equipped with a water supply system and a water sink to clean the cleaning cylinder, thus so as to clean the floor completely.
In order to clean the cleaning cylinder, a water sink communicated with the water supply system is generally provided, clean water is supplied to clean the cleaning cylinder, and waste water produced after cleaning the cleaning cylinder is pumped out. The existing floor cleaner generally uses a shell water sink, and a filter screen is provided on the water sink, thus forming a water sink structure. However, since the garbage on the cleaning cylinder enters the filter screen, the filter screen is easily blocked.

Floor cleaner and water sink structure thereof


An information handling system includes a method for executing instructions for a content sharing system having mixed operating system capabilities, detecting pre-paired wireless connectivity of remotely connected computing devices to a system hosting the content sharing system, determining remotely connected computing device authorization for access with the content sharing system, and implementing, via a processor, role-based policy settings to partially limit content sharing system operation based on a role classification for remotely connected computing devices.

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, or communicates information or data for business, personal, or other purposes. Technology and information handling needs and requirements can vary between different applications. Thus information handling systems can also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information can be processed, stored, or communicated. The variations in information handling systems allow information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems can include a variety of hardware and software resources that can be configured to process, store, and communicate information and can include one or more computer systems, graphics interface systems, data storage systems, networking systems, and mobile communication systems. Information handling systems can also implement various virtualized architectures. Data and voice communications among information handling systems may be via networks that are wired, wireless, or some combination. In some instances, users may operate via multiple computing devices. In other instances, multiple users on multiple computing devices may want to collaborate and share data. Coordination of a wide variety of content from a variety of devices that may have disparate hardware requirements, software architecture, or distinct operating systems (OS) may be challenging.
The use of the same reference symbols in different drawings indicates similar or identical items.

Policy setting for content sharing of a plurality of remotely connected computing devices in physical or virtualized space


A luminescent layer in an EL device composed of CaGa.sub.2 S.sub.4 :Ce includes a first luminescent layer and a second luminescent layer. The first luminescent layer has an atomic ratio of Ga to Ca being higher than that in the second luminescent layer, and directly disposed on a first insulating layer, whereby delamination can be prevented. The atomic ratio of Ga to Ca in the second luminescent layer is approximately equal to a stoichiometric ratio, so that the threshold voltage of the EL device can be kept low.

1. Field of the Invention
The present invention relates to electroluminescent (hereinafter referred to as EL) devices which are used in various instruments of, for example, emissive-type segment displays and matrix displays, and in displays in various information terminals. The present invention also relates to methods for producing the same.
2. Related Arts
An EL device is typically formed by laminating a first electrode, a first insulating layer, an luminescent layer, a second insulating layer, and a second electrode on an insulating glass substrate in this order, and the layers at least on one side of the luminescent layer are made of transparent materials.
The luminescent layer is composed of a host material doped with a luminescent center, and various luminous materials are previously proposed. Especially, a luminescent layer capable of emitting blue light, including an alkaline earth thiogallate (MGa2S4, M=Ca, Sr, Ba) as the host material doped with cerium (Ce) as the luminescent center, is known. The alkaline earth thiogallate luminescent layer is deposited by a sputtering method.
However, in the case that the alkaline earth thiogallate layer formed by the sputtering method is independently used as the luminescent layer in the EL device, there occurs a problem that the luminescent layer is liable to peel off during thermal annealing after the luminescent layer is deposited. The delamination results in a decline in the breakdown voltage of the EL device, and the breakdown of the EL device starts at some tens volts over a threshold voltage. Therefore, reliability of the EL device is lowered.
As opposed to this, an EL device including an alkaline earth thiogallate luminescent layer deposited by sputtering and interposed between a pair of zinc sulfide (ZnS) layers to prevent delamination is disclosed in JP-A-5-65478.
The ZnS layers, however, do not contribute to the luminescent process, and the threshold voltage of the EL devices is increased by the ZnS layers.

Electroluminescent device and method for producing the same


A system and method for the continuous fabrication of bichromal spheres by introducing continuous streams of differently colored, pigmented polymer melts to substantially opposite sides of a plurality of spinning disks. The system comprises a first and second extruder which melts a raw polymer material and mixes the melted polymer with a pigment and optionally a charge control agent. The first and second extruders are connected to substantially opposite sides of a plurality of spinning disks with optionally interconnected gear pumps and mixing devices. The instant system and method is useful in fabricating large quantities of bichromal spheres in a continuous manner with a higher degree of uniformity in their physical characteristics.

Rotating element display material has been disclosed in U.S. Pat. Nos. 4,126,854, 4,143,103 and 5,389,945, each herein incorporated by reference. The rotating element display material generally comprises a substrate, a dielectric fluid and a set of rotatable elements. The rotating element display material has found use as reusable "electric paper" since it has many of the attributes of paper documents when the display is in sheet form. The rotating elements are embedded in an elastomer material which is then cured and swelled to create cavities around the elements. The rotating element display material has many of the qualities of real paper, including being flexible and affordable, it can be written on like paper, it can be copied like paper, it can be easily viewed in high levels of ambient light, and it will retain images nearly as long as regular paper.
The rotating elements, also referred to as bichromal spheres or bichromal balls, are optically and electronically anisotropic. For example, a rotating element has two distinct hemispheres, one black and one white, with each hemisphere having a distinct electrical characteristic giving it a dipole moment with respect to a dielectric fluid. An image is formed on the electric paper by applying an external electric field which rotates the bichromal sphere differentiated by the contrasting charges of the two hemispheres of the rotating element. The difference in charges between the hemispheres of the ball causes the ball to act like a dipole in the presence of an electrical field, which in turn causes the ball to rotate until its dipole vector lines up in the direction of the externally applied electric field.
Varying methods have been developed for the fabrication of the rotating elements; however, these existing methods are not adaptable to either a continuous fabrication of the rotating elements or a large-scale fabrication process which is commercially acceptable. For example, U.S. Pat. No. 4,438,160 describes the fabrication of rotating elements using a vapor deposition method. Generally, the vapor deposition method entails fabrication of rotating elements of a single color. A contrasting pigment is then evaporated on to one side of the rotational element resulting in a bichromal sphere.
Alternately, fabrication of rotating elements, as described in U.S. Pat. No. 4,810,431 to Leidner, may be achieved by (a) co-extruding a fiber of a semi-circular layer of a polyethylene pigmented white and a semi-circular black layer of polyethylene containing magnetite; (b) chopping the resulting fiber into fine particles ranging from 10 microns to about 10 millimeters; (c) mixing the particles with clay or anti-agglomeration materials, and (d) heating the mixture with a liquid at about 120° C. to spheradize the particles, followed by cooling to allow of solidification.
U.S. Pat. No. 5,262,098 describes an apparatus useful for fabricating bichromal spheres which comprises a separator member, also called a spinning disk, having opposing first and second surfaces, an outer edge region in contact with both surfaces, and means for delivering a first and second pigmented polymer melt over the first and second surfaces, respectively. The respective liquid materials arrive at the edge at substantially the same flow rate and form a reservoir outboard of the edge region. The reservoir comprises side by side regions of different colors which do not intermix. The separator member is rotated and the centrifugal forces cause the first and second liquid materials to pull away from the separator member and out of the reservoir as a plurality of side-by-side bichromal streams. As a result of the centrifugal forces, the forward ends of the bichromal steams become unstable, break into droplets which form into spherical balls each comprising hemispheres of differently pigmented polymer melts.
The existing systems for fabricating bichromal spheres employ a batch process for the preparation of the pigmented polymer melt. Basically, polymer material forming the matrix of the sphere, such as polyethylene wax, is poured into mixing tanks and heated. A separate tank is used for making the white pigmented polymer and for making the black pigmented polymer. A white pigment, usually titanium dioxide, is added to the first tank of molten material, mixed for approximately two hours then moved to solidify. Similarly, a black pigment, such as ferrous oxide, and optionally a charge control agent is added to the second tank of molten material which is also mixed for approximately two hours and allowed to solidify. Next, the white pigmented polymer material and the black pigmented polymer material are placed into separate melters where a white pigmented melt and black pigmented melt are formed. The separate melts are then introduced to the spinning disk as described above.
The inefficiencies of the existing methods for fabricating the rotational elements make these methods ineffective for continuous or large-scale production processes. For example, the existing fabrication methods which utilize spinning disks require 3 to 4 hours, or more, depending on batch size, to prepare and produce a single batch of rotating elements. However, actual production of useable rotating elements occurs for as little as 20 minutes, with the remainder being spent on preparation of the material and stabilization of the system. In addition, during the stabilization of the system, the production of irregular and unusable rotational elements results in waste of raw materials. Finally, rotational elements produced by different batches may have inconsistencies in critical features of the sphere such as contrast ratio of the display sheet into which the spheres are incorporated, diameter, complimentarity, and sphere quality, where sphere quality is understood to be a measure of the roundness of the spheres.
Accordingly, it is an object of the present invention to provide for a continuous fabrication of anisotropic rotational elements, such as hemispherically bichromal spheres, wherein a high level of consistency and complimentarity of the rotational element is obtained.

Continuous combined pigmented wax compounding and bichromal sphere fabrication process


A method of analyzing a bundle of banknotes. The method includes the steps of providing a bundle of banknotes, which bundle comprises at least one surface defined by the edges of banknotes, illuminating the surface of said bundle, providing a two-dimensional image of the bundle by making use of an optical sensor, and providing an output signal that represents the result of the analysis.

1. Field of the Invention
The present invention relates to a method of analyzing a stack of flat objects as well as to a device for analyzing a stack of flat objects. The present invention in particular pertains to a device and a method of analyzing a bundle of banknotes, which method comprises the steps of providing a bundle of banknotes, which bundle comprises at least one surface defined by the edges of banknotes, illuminating the surface of said bundle, providing a two-dimensional image of the bundle by making use of an optical sensor, and providing an output signal that represents the result of the analysis.
2. Description of the Related Art
From International application WO01/50426 there is known a method of determining a characteristic of a banknote including a sheet-like substrate of plastics material and pacifying layers applied to the two outer surfaces of the substrate. The method that is known therefrom comprises die steps of irradiating the substrate, the opacifying layers acting to guide the radiation "within" the substrate, whereupon the emission at the "end" of the substrate is detected, after which one or more characteristics of the emission, such as the intensity or the wavelength, are analyzed. The method described in said International application is only suitable for so-called "polymer banknotes", because the light bean must be trapped in the substrate.
From U.S. Pat. No. 6,182,962 there is known a method of separating a single note from a stack of banknotes, wherein the thickness of the stack is determined by means of a density sensor. The density is claimed to be a measure of the pressure with which the stack of banknotes is pressed against a withdrawal means. The method that is known therefrom is aimed at removing a single banknote from a stack of banknotes; the stack of banknotes as a whole is not analysed as such, however.
The method referred to in the introduction is also known from U.S. Pat. No. 5,534,690 (corresponding European patent No. 0 805 992). The method of counting stacked banknotes that is known therefrom requires the use of at least one optical sensor, which images at least two separate columns simultaneously along at least one surface of the bundle of banknotes, said columns extending in a direction perpendicular to the surface of the banknotes. On the basis of the signal provided by the optical sensor, a perception of the number of banknotes in the stack is obtained, for example by comparing the two images. One drawback of such a method is the fact that the bundle of banknotes must be subjected to so-called column imaging at two different positions. If the bundle contains folded, torn or strongly creased banknotes, this will render the result inaccurate.
From U.S. Pat. No. 5,918,960 there is known a method wherein a single banknote is illuminated with ultraviolet light of two different wavelengths, wherein detectors are used for detecting reflected light from the banknote having a first wavelength within a first wavelength band and for detecting fluorescence light from the banknote having a second wavelength within a second wavelength band different from said first wavelength band, said second wavelength band including wavelengths at which counterfeit objects may fluoresce when exposed to said ultraviolet light. Such a method is only limited to verifying authenticity characteristics of a single banknote, which means that if a large amount of banknotes is to be verified, each banknote must be separately subjected to such a verification of authenticity characteristics.
Banknotes include authenticity characteristics which may vary with each individual country, region or zone from a few authenticity characteristics in some banknotes to more than twenty authenticity characteristics in the Euro banknotes, for example. Such authenticity characteristics enable the user, the commercial financial institutions and the Central Banks to determine the authenticity of a banknote at different levels. Authenticity verification generally takes place upon acceptance of banknotes. At Central Banks, the verification of the authenticity characteristics of banknotes is carried out by means of so-called banknote sorting machines, with so-called "single note" sorting taking place. This means that all banknotes, which are usually supplied in bundles of 100, 500 or 1000 units, must first be "unbundled", which is a cost-intensive operation. Subsequently, the unbundled banknotes are mechanically verified one by one, irrespective of their value or their physical condition, by means of so-called sorting machines which carry the banknotes past a series of detectors and sensors. The verification comprises a number of authenticity checks, which can be carried out by means of a machine, as well as all kinds of measurements for determining the present condition or the fitness for use of the banknotes.
Low-denomination banknotes constitute about 40% of the total volume of banknotes that is in circulation worldwide. The "single note" sorting process as described above does not provide a desirable solution for handling low-denomination banknotes, in view of the high sorting costs and the (frequently) poor condition of these banknotes. Moreover, the efficiency of the sorting machine will strongly decrease if the physical condition of the banknotes to be processed is poor. The quality of low-denomination banknotes is generally inferior to that of high-denomination banknotes. This means that the handling costs of lower denomination banknotes are disproportionately high in relation to the value that such banknotes represent. In addition, low-denomination banknotes are rarely counterfeited, so that the high sorting costs will outweigh the security risk.

Method of analysing a stack of flat objects


A new and distinct cultivar of hardy herbaceous perennial Hibiscus hybrid plant named ‘Plum Fantasy’ comprising an upright dense branching, numerous flowers over a prolonged season having vibrant magenta-red overlapping petals and a darker red lustrous eye. The petals have a unique three-dimensional dimpling or puckering which helps resist strong wind, bright sun and harsh rain conditions. The foliage is dark-green, primarily heavily-dissected and tri-lobed.

The present invention relates to the new and distinct hardy, herbaceous, hibiscus plant, Hibiscus 'Plum Fantasy' hybridized by Clarence H. Falstad, III in the summer of 2007 at a nursery in Zeeland, Mich. The new plant, originally labeled # F7-16-01, is from a cross between Hibiscus 'Summer Storm' U.S. Plant Pat. No. 20,443 (female pod parent) times the proprietary hybrid # 05-139-17 (not patented) (male pollen parent). Both parents have a complex mixture of species in them, most likely including the species: moscheutos, coccineus and laevis (formerly militaris). Hibiscus 'Plum Fantasy' was first asexually propagated in 2010 by both stem cuttings and sterile tissue culture at the same nursery in Zeeland, Mich. The resultant asexually propagated plants have been found to be stable and true to type in successive generations of asexual reproduction.


The present invention discloses a combined dry sorting bed, the sorting bed is arranged with an inclination, and the inclination between the longitudinal extending of said bed surface and horizontal plane is from −2° to +4°, and the inclination between the lateral extending of said bed surface and horizontal plane is from 0° to +15°. By reasonable setting of the angle of inclination, the material being separated spiral overturn continuously on the sorting bed under the influence of the rising air currents and the force of vibration, with the result that the light material in the upper layer is separated under the influence of weight. The material is sorted for many times during the circularly movements, the product with different content of ash can be obtained. This invention also relates to a combined dry sorting device that comprises frame, sorting bed, vibrator and air supply device. This invention further relates to an apparatus for separation that comprises a feeding device, an air supply and dedusting device and a separating device, the above mentioned sorting bed is used in the sorting device and apparatus, therefore different products with vary quantity of ash are generated according to the gravity of material, and the accuracy of separation is improved.

It is well known that the dry sorting apparatus used in industrial production at home and abroad are mainly pneumatic jig and air table. The method of using air to replace water as sorting medium has already been eliminated through selection gradually for its poor sorting effect, low production capacity and a large amount of wind power demand.
An adverse current sorting apparatus was disclosed by American Graham & Troman Co., Ltd in Volume one of the book Coal-beneficiation Technique published in 1988. It's a kind of air table, whose bed surface is rectangular and is provided with an inclination of 10°. The longitudinal vibration device makes the bed surface move longitudinally and the bed surface adopts a perforated plate. A blower fan sends wind under the plate at a constant wind speed and pressure. The upward flowing airflow makes the materials on the bed surface sorted in layers and then the heavier waste-rock falls onto the perforated plate through the table and move upward and slantways along the bed surface effected by eccentric to-and-fro movement. In this way, the lighter coal emerges at the upper layer on the table and is pushed by the fed-in materials to move along the downwards-slanting bed surface. In nature, it's a kind of air-fluidized bed. The sorting is completed on the bed surface at a time. The float coal is discharged at a time, but it is easy for fine grain waste-rocks to drop in the coal. Therefore, the sorting effect is very poor, the production rate is low and the demanded wind power is very large. There is also another kind of dry type shaking table, which needs no wind power and depends on the helical motion of the materials to make the materials sorted in layers. In this way, the coarse grains stay at the upper layer and the fine grains stay at the lower layer. So, the sorting effect is poor because it is made according to the density of the materials.
A combined type sorting method was published in 1990s, which adopts the self-born medium (i.e. the fine grain coal contained in the raw coal to be sorted) and air to form air-solid two-phase medium for sorting; which utilizes mechanical vibration to sort the materials time after time by making them roll spirally; and which makes the most of the buoyancy effect of the interaction between grains generated by the gradually increased density of the materials on the table to sort the materials. Under such a condition that the materials are made to roll spirally on the bed surface of the sorting apparatus, the combined action of the vibratory force and the ascending air is utilized to make the material layers on the table incompact and make the mineral grains layered according to density. Under the effect of gravity, the materials whose density on the surface layer is low are delaminated. While this action is repeated, the materials are sorted time after time. By delaminating layer upon layer, several kinds of products are produced whose ash contents are from low to high, until the waster rocks and iron pyrites are discharged. Then, sorting is made by making use of the fine grain materials in the fed-in raw coal (called self-born medium) and upward flowing gas to form air-solid two-phase medium. In this dispersion medium with a certain density, the low-density materials emerge upward and the high-density materials sink. Then, pure waste-rock product is obtained by making use of the buoyancy effect generated by the interaction of the heavier grains to make the coal grains mixed in the waste-rock layer emerge continuously.
CN2101532 and CN2314850 respectively disclosed the above combined type of dry sorting apparatus, which are applicable to sorting material of solid particle admixture, in which the density of the solid particles is different. The sorting apparatus consist of a vibrator and a sorting bed hung from the frame to form a vibration bed. The vibration bed is provided with lattice bars according with the direction of the motion of materials. The bed surface between lattice bars is equably provided with vertical wind ports connected with the air chambers. A slanting backboard is attached to the back of the sorting bed surface. Affected by the vibratory force and upward flowing gases, the materials move spirally and are sorted into layers according to density. Through circulatory sorting time after time, the low-density materials are separated from the high-density materials.
However, the following problems exist in the sorting beds disclosed by above two patents:
Firstly, the above patents didn't disclose the obliquity of the bed surface of which the lateral angle and longitudinal angle directly affect the sorting effect. If the lateral angle is too small, the thickness of the materials on the table will increase and the sorting speed of the coal on the surface will decrease. If the lateral angle is too large, the vibration speed of the high-density materials at the bottom will decrease, or may not move at all, which will ruin the sorting process. If the longitudinal positive angle (waste-rock discharging end is lower than material feeding end) is too large, the waste-rocks and coal will gather into the waste-rock discharging port. If the longitudinal negative angle (waste-rock discharging end is higher than material feeding end) is too large, the waste-rocks will move at an excessively low speed and accumulate too much on the table to ruin the sorting process. Therefore, it is extremely important for the bed surface have a rational obliquity. Secondly, the functions of the parallel lattice bars on the bed surface include: (i) guiding the high-density mineral grains to move to the waste-rock channel; (ii) increasing the speed of the high-density mineral grains at the bottom of materials on the bed surface to move to the waste-rock end, which is propitious to the increasing of the processing rate of the sorting bed; (iii) sorting function to a certain extent. The low-density coal at the top of the materials on the bed surface can cross over the lattice bars to move to the material discharging side and the high-density materials at the bottom of the materials on the bed surface will be the held up by the lattice bars and can only move along the lattice bars to the waste-rock end, which increases the sorting accuracy. Therefore, an appropriate height and obliquity of the lattice bars is very important to the effect of sorting. Thirdly, the shape of the bed surface is square pentagon and the proportion of the width of the feeding side to the length of the bed surface is 4:10, resulting in shorter sorting time, easier for waste-rocks to drop in the float coal and more difficult for sorting accuracy to be increased. Fourthly, the above patents didn't provide the degree of the obliquity between the backboard and the bed surface, but the angle of the backboard guides the materials to move spirally, which is very important for the separation of light materials. Fifthly, vibration form of the bed surface is electromagnetic vibration or low amplitude inertial force vibration, which isn't propitious to the sorting of the materials whose partial sizes are comparatively large and which moves the materials at the bottom of the materials on the bed surface at a low speed and it is very difficult to increase the production capacity.

Dry separating table, a separator and equipment for the compound dry separation with this table


A neck traction device for delivering or imposing a tension force on the neck area of a person. The traction device includes a rigid vertical support member that has a connector for engaging a support surface. A neck cradle having a pair of rigid spaced apart arms adapted for engaging the scull at a location below the occipital bone is mounted from the rigid vertical member to allow a person to use his weight against the cradle to impose a tension force on the person's neck.

(a) Field of the Invention
This invention generally relates to a system for exerting a tension force along the neck area of a human. More particularly, but not by way of limitation, to a traction device that is used to pull a person's skull away from the base of the neck in order to relieve pressure between vertebra of the neck.
(b) Discussion of Known Art
A common treatment for pain caused by damage or infirmity of the neck area of the spine has been to stretch or pull on the spine in order to relieve pressure or align components of the spine. This pulling or tension on the spine is typically induced by placing weights on a lever or pulley system, which in turn transmits this tension load to the person's head. The connection of this system to the person's head is typically a harness that includes a strap or the like that engages the person's jaw, and transmits the tension load to the person's head through the jaw.
An examination of the attachment of the jaw to the human skull, the temporo-mandibular joint, reveals that the jaw is held in place by muscles that surround a relatively small contact area that is cushioned by a small cartilage disk. The entire joint is balanced and precisely adapted to withstand the loads imposed by chewing. The use of this joint to transfer the loads for obtaining the effects of traction by pulling on a person's head can easily overload temporo-mandibular joint, causing additional pain to the person who already suffers from spine ailments.
Still further, the use of a strap or other device that transfers loads through a person's jaw is very uncomfortable for the user. The pressure imposed on the jaw forces the jaw closed, making it difficult to breathe and impossible to speak without difficulty.
Examples of known devices can be found in the following U.S. patents:
U.S. Pat. No.InventorDate of Issue6,517,506PettibonFeb. 11, 20034,869,240BorenSep. 26, 19893,403,675CarrOct. 1, 19682,938,695CiampaMay 31, 19602,843,114HallJul. 15, 19582,808,049GrahamOct. 1, 19572,701,564WilhelmFeb. 8, 19552,658,506HaskellNov. 10, 19531,425,433ZookAug. 8, 1922As indicated above, these patents consistently advocate the use of a chin strap, or strap that extends across the front of the neck. Accordingly, there is a need for a device that can provide traction to the neck area without pulling or pressing against the person's jaw.
Still further, a review of known devices reveals that it is well accepted that the way to provide pressure or pull on the neck is by providing weights. The weight of these weights is transmitted by way of cables and pulleys to a harness that transmits the load the person's neck through the harness.
Therefore, a review of known devices reveals that there remains a need for a device that allows a person to provide traction to the neck and upper spine area without having to impose pressure on the jaw area.
There remains a need for a neck traction device that allows the user to control the amount of weight or tension by simply shifting his weight, thereby providing the user great deal of precise control of the amount of force-transmitted to the neck area.


A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Solid-state memory, such as flash, is currently in use in solid-state drives (SSD) to augment or replace conventional hard disk drives (HDD), writable CD (compact disk) or writable DVD (digital versatile disk) drives, collectively known as spinning media, and tape drives, for storage of large amounts of data. Flash and other solid-state memories have operation, lifespan, defect and other characteristics that differ from spinning media. Yet, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory. In addition, address spaces optimized for spinning media may be suboptimal for solid-state memory.
It is within this context that the embodiments arise.


It is an object of the invention to provide a peeling method which does not damage a peeling layer, and to perform peeling not only a peeling layer having a small-size area but also an entire peeling layer having a large-size area with a preferable yield. In the invention, after pasting a fixing substrate, a part of a glass substrate is removed by scribing or performing laser irradiation on the glass substrate which leads to providing a trigger. Then, peeling is performed with a preferable yield by performing peeling from the removed part. In addition, a crack is prevented by covering the entire face except for a connection portion of a terminal electrode (including a periphery region of the terminal electrode) with a resin.

1. Field of the Invention
The present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as a TFT), and to a method for manufacturing the same. For example, the invention relates to an electronic device on which an electro-optical device typified by a liquid crystal display panel or a light emitting display device having an organic light emitting element is mounted as its component.
In this specification, the term "semiconductor device" refers to a device in general that utilizes semiconductor characteristics to function, and electro-optical devices, semiconductor circuits and electronic devices are all included in the semiconductor device.
2. Description of the Related Art
In recent years, a technique for forming a thin film transistor (a TFT) by using a semiconductor thin film (thickness is approximately from several nm to several hundreds nm) formed over a substrate having an insulating surface has drawn attention. The thin film transistor has gained a wide application in electronic devices such as an IC and an electro-optical device, and particularly, development of a TFT as a switching element for an image display device has been hurriedly carried out.
As for applications utilizing such an image display device, a variety of applications is expected. The utilization for a portable device has drawn attention, in particular. Although a glass substrate and a quartz substrate are widely utilized at present, there is a disadvantage of being easily cracked and heavy. Moreover, a glass substrate and a quartz substrate are difficult to be made larger on the basis of mass-production, and these are not suitable for that. Therefore, forming a TFT element over a substrate having flexibility, typically, over a flexible plastic film has been attempted.
However, since the heat resistance of a plastic film is low, it cannot help lowering the highest temperature of a process. As a result, a TFT which has not so excellent electric characteristics compared with those formed over a glass substrates is formed at present. Therefore, a liquid crystal display device and a light emitting element having a high performance using a plastic film have not been realized yet.
Moreover, a method for peeling a peeling layer existing over a substrate with a separation layer therebetween from the substrate has been already proposed. For example, techniques described in Japanese Patent Laid-Open No. Hei 10-125929 and Japanese Patent Laid-Open No. Hei 10-125931 are techniques that a separation layer including an amorphous silicon (or a polysilicon) is provided, laser light is radiated by being transmitted through the substrate, and makes hydrogen contained in the amorphous silicon released, thereby generating a space-gap to separate the substrate. In addition, there is also a description in Japanese Patent Laid-Open No. Hei 10-125930 that by utilizing this technique, a liquid crystal display device is completed by pasting a peeling layer (in the gazette, referred to as a transferring layer) to a plastic film.
However, in the above-mentioned method, it is essential to use a substrate having high light-transmitting properties, and for transmitting light through the substrate and further, for the purpose of giving sufficient energy for releasing hydrogen contained in the amorphous silicon, the irradiation of laser light having comparatively large energy to the entire surface is necessary. Consequently, there is a problem that the peeling layer is damaged. Moreover, in the above-mentioned method, in the case when an element is manufactured over a separation layer, if heat treatment at a high temperature or the like is performed in the process for manufacturing the element, hydrogen contained in the separation layer is dispersed and reduced. In that case, even if the laser light is radiated on the separation layer, there is a possibility that the peeling is not sufficiently performed. Therefore, in order to maintain the amount of hydrogen contained in the separation layer, a problem that the processes after the separation layer formation are limited occurs. Moreover, in the above-mentioned gazette, there is also a description that, a light-shielding layer or a reflection layer is provided in order to prevent a damage to the peeling layer. However, in this case, it is difficult to manufacture a transmissive type liquid crystal display device. In addition, by the above-mentioned method, it is difficult to peel a peeling layer having a large area.
Accordingly, the applicant proposes a peeling technique and a transferring technique described in Japanese Patent Laid-Open No. 2003-174153.

Method for manufacturing semiconductor device

Semiconductor Energy Laboratory Co., Ltd.