A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed.

1. Field of the Invention
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Many types of EEPROM and flash memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. Each NAND string is connected to the source line by its source select gate controlled by select line SGS and connected to its associated bit line by its drain select gate controlled by select line SGD. Each bit line and the respective NAND string(s) that are connected to that bit line via a bit line contact comprise the columns of the array of memory cells. Bit lines are shared with multiple NAND strings. Typically, the bit line runs on top of the NAND strings in a direction perpendicular to the word lines and is connected to one or more sense amplifiers. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the memory array.
Each memory cell can store data (analog or digital). When storing one bit of digital data (referred to as a binary memory cell), the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0." In one example of a NAND type flash memory, the threshold voltage is negative after the memory cell is erased, and defined as logic "1." The threshold voltage after programming is positive and defined as logic "0." When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
A memory cell can also store multiple levels of information (referred to as a multi-state memory cell). In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored (two bits of data), there will be four threshold voltage ranges assigned to the data values "11", "10", "01", and "00." In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as "11". Positive threshold voltages are used for the data states of "10", "01", and "00." If eight levels of information is stored (three bits of data), there will be eight threshold voltage ranges assigned to the data values "000", "001", "010", "011" "100", "101", "110" and "111". The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one bit will be affected.
Relevant examples of NAND type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat. No. 5,774,397; U.S. Pat. No. 6,046,935; U.S. Pat. No. 6,456,528; U.S. Pat. Publication No. US2003/0002348; and U.S. Pat. Publication No. 2006/0140011. The discussion herein can also apply to other types of flash memory in addition to NAND as well as other types of non-volatile memory.
When programming a flash memory cell, a program voltage is applied to the control gate and the bit line is grounded. Due to the voltage differential between the channel of the flash memory cell and the floating gate, electrons from the channel area under the floating gate are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised.
In some implementations, the programming voltage is applied as a series of voltage pulses. Each programming pulse is followed by one or more verify operations to determine if the memory cells has been programmed to the desired state.
Modern flash memory devices, particularly those of the NAND architecture and involving multi-state memory cells, are arranged in blocks and pages. A block refers to a unit of erase, and defines a group of memory cells that are simultaneously erased in a single erase operation. Typically, a block of memory cells is the smallest group of memory cells that can be erased. A page refers to a unit of programming, and defines a group of data bits (could be memory cells) that are simultaneously programmed. Each block typically includes multiple pages. Generally, the arrangement of memory cells into pages and blocks is based on the physical realization of the memory array. For example, in many NAND memory arrays, a page of memory cells is defined by those cells that share the same word line, and a block is defined by those pages residing in the same NAND string. For example, if a NAND string includes thirty-two memory cells in series, a block will typically include thirty-two pages, or an integer multiple of thirty-two pages. In some NAND memory arrays one word line can be shared by memory cells for two pages; the data for a first page is stored in the memory cells of even-numbered columns, while the data for a second page is stored in the memory cells of odd-numbered columns along that word line. Other arrangements are also possible.
In some memory systems utilizing multi-state memory cells, each bit of data in a memory cell is in a different page. For example, if an array of memory cells store three bits of data (eight states or levels of data) per memory cell, each memory cell stores data on three pages with each of the three bits being on a different page. Thus, within a block in this example, each word line is associated with three pages or an integer multiple of three pages. Other arrangements are also possible.
Historically, the organization of data stored in a flash memory has followed the file systems used in connection with magnetic disk storage, which stores data in sectors. A sector is typically a group of data of a fixed size, for example, 512 bytes of user data plus some number of bytes of overhead. In many modern file systems, the operating system of the computer or other host system arranges data into sectors, and writes data to and reads data from non-volatile storage on a sector-by-sector basis. To permit convenient use of flash memory devices in such systems and applications, many modern flash memories handle data in a similar fashion, mapping logical sector addresses to physical addresses in the flash memory array.
In recent years, the sizes and capacities of flash memory devices have greatly increased, resulting in memory arrays of more than 4 billion cells. In such arrays, a single word line may extend to over tens of thousands of memory cells. In such large scale flash memories, each page includes multiple sectors. As such, the units of data handled by the host system (i.e., "sectors") are smaller than the smallest programming unit in the flash memory device. Typically, however, the multiple sectors of data that comprise a page of the flash memory will be sequentially communicated to the flash memory, and will be simultaneously programmed into a page of the flash memory in a single operation.
By way of further background, the use of error correction coding (ECC) in mass data storage devices and storage systems, as well as in data communications systems, is well known. As fundamental in this art, error correction coding involves the storage or communication of additional bits (commonly referred to as parity bits, code bits, checksum digits, ECC bits, etc.) that are determined or calculated from the "payload" (or original data) data bits being encoded. For example, the storage of error correction coded data in a memory resource involves the encoding of one or more code words that include the actual data and the additional code bits, using a selected code. Retrieval of the stored data involves the decoding of the stored code words according to the same code as used to encode the stored code words. Because the code bits "over-specify" the actual data portion of the code words, some number of error bits can be tolerated, without any loss of actual data evident after decoding.
Many ECC coding schemes are well known in the art. These conventional error correction codes are especially useful in large scale memories, including flash (and other non-volatile) memories, because of the substantial impact on manufacturing yield and device reliability that such coding schemes can provide, allowing devices that have a few non-programmable or defective cells to be useable. Of course, a tradeoff exists between the yield savings and the cost of providing additional memory cells to store the code bits (i.e., the code "rate"). Some ECC codes for flash memory devices tend to have higher code rates (i.e., a lower ratio of code bits to data bits) than the codes used in data communications applications (which may have code rates as low as ½). Examples of well-known ECC codes commonly used in connection with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Typically, the error correction codes used in connection with flash memory storage are systematic, in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete code word.
The particular parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four error bits, if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes, and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte sector of data, using about 72 ECC bits. In the flash memory context, error correction coding provides substantial improvement in manufacturing yield, as well as in the reliability of the flash memory over time.
By way of further background, the programming and erasing of conventional flash memory devices may involve the verification of the state of the memory cells being programmed or erased to ensure that the desired state has been reached for each of the cells subject to the operation. Indeed, considering that the programming and erasing of flash memory cells are typically performed by the application of a sequence of pulses of the appropriate voltages, and also considering that the pulse sequences consume substantial time and power, many flash memories now include verification operations during the programming or erasing operations themselves. For example, the programming of a page of memory cells is typically performed by applying a programming pulse, and then verifying the programmed cells against one or more desired "verify" voltages for the data level(s) being programmed. If not all of the memory cells verify to the appropriate desired level after a first pulse, the programming pulse is repeated (often at a higher voltage), and the cells are verified again. Upon all of the memory cells reaching the desired program level, the programming operation is terminated.
Verification is also typically performed in the erasing of a block of flash memory cells, with additional erase pulses applied as necessary to ensure all cells are erased. In general, for NAND flash memories, erase verification is typically performed by applying a selected control gate voltage to all of the word lines of the block being erased, to determine whether any of the cells conduct at that control gate voltage. Because the threshold voltages of erased cells are typically below 0 volts, and because the application of negative word line voltages is not desirable, the verifying of negative erase voltages is often done by way of a low or zero voltage on the word lines, with the common source lines biased to effectively place a negative gate-to-source voltage at each memory cell in the NAND chain. A similar approach is used during "soft" programming, which refers to the conventional operation of slightly programming erased flash memory cells, to prevent some or all of the cells from being too deeply erased.
A typical way of verifying programming is to test the conduction of each cell at a specific compare point that is set by a control gate voltage. Those cells that have previously been verified as sufficiently programmed are locked out, for example, by raising the bit line voltage for those cells in the page being programmed to a high level (e.g., the voltage of the Vdd power supply), to stop the programming process for those cells. Those cells that are not yet sufficiently programmed receive the next higher voltage pulse in the programming sequence, followed by another verify operation.
As is well known in this art, some memory cells are slower to program or erase than others, because of manufacturing variations among those cells, because those cells were previously erased to a lower threshold voltage than others, because of uneven wear among the cells within a page, or the like. And, of course, some cells cannot be programmed or erased whatsoever, because of a defect or other reason. As mentioned above, error correction coding provides the capability of tolerating some number of slow or failed cells, while still maintaining the memory usable. In some applications, a page of data is programmed by repeatedly applying programming pulses until all memory cells on that page verify to the desired programmed state. In these applications, programming terminates if a maximum number of programming pulses is reached prior to successful verifying of the programmed page, following which the number of cells that have not yet been verified to the desired state is compared with a threshold value, which depends on the capability of the error correction coding that will be used in the reading of data from that page. In other applications in which the error correction is sufficiently robust, programming and erasing time is saved by terminating the sequence of programming or erasing pulses upon the number of slow (or error) cells that are not yet fully programmed or erased being fewer than the number of bits that are correctable.
Error correction is typically performed on a sector-by-sector basis. Thus, each sector will have its own set of ECC codes. This error correction is convenient and useful because the sector is the desired unit of data transfer to and from the host system.
The usual maximum number of bits correctable within a sector of 512 bytes, using a BCH or Reed-Solomon code is four. Therefore, if a programming process results in two errors, the process can be considered successful because those two errors can be correct during a subsequent read process using ECC. In a page that stores 8 sectors, error correction should be able to tolerate 32 error bits (4 bits/sector×8 sectors). However, in conventional circuitry, the verification process counts errors (bits that have not properly programmed) across the entire page, regardless of the position of the error bit. Because it is possible that all error bits are within the same sector, the maximum number of error bits that can ignored during programming (or erase) verification over a page must be kept below the maximum number of allowed bits to ignore for a sector. Typically, in many memory systems, the maximum number of bits that can be ignored is even lower to ensure that some error correction remains to correct other errors found during the read process. Consider the example, where one bit has failed in each of eight sectors in a page. The typical system described above will not conclude that programming was successful, despite the ability of ECC to correct one error per sector.

Segmented bitscan for verification of programming


An image capture system is described that includes: a first image capture device for capturing a first image, the first image capture device having a first field of view; a viewpoint assessment sensor having a second field of view. The image capture system also includes a viewpoint assessment component for determining the location of the user viewpoint in the second field of view and an image modification component for modifying the first image responsive to the user viewpoint in the second field of view.

One step in taking a photograph or capturing video is framing of the desired image. Many cameras include an LCD display or viewfinder facing the user which displays the framed image before and after image capture. Users can, for example, adjust the image displayed in the LCD display using a combination of camera movement (the user physically moving the camera location) and zoom control to frame the desired image. For many commercially available consumer cameras, when a user raises the camera to frame a picture, the image displayed on the viewfinder does not relate to the user's view of the scene past the camera, but instead depends only on the orientation of the camera and the position of its zoom control. This mismatch between the user's and the camera's view directions can be especially problematic when the view of the viewfinder is impaired, washed out by strong sunlight, for example. Contrast this to the simple way in which a cinematographer frames a shot with their fingers: by simply moving the "frame" in front of their view, including closer to and further away from their viewpoint (to include more or less of the image respectively). They are able to directly select the view they want to capture—without recourse to additional controls such as zoom.
The drawings referred to in this Brief Description should not be understood as being drawn to scale unless specifically noted.

Modifying captured image based on user viewpoint

Hewlett-Packard Development Company, L.P.


An apparatus for mass spectrometry and/or ion mobility spectrometry is disclosed comprising a first device arranged and adapted to generate aerosol, smoke or vapour from a target and one or more second devices arranged and adapted to aspirate aerosol, smoke, vapour and/or liquid to or towards an analyser. A liquid trap or separator is provided to capture and/or discard liquid aspirated by the one or more second devices.

Gastro-intestinal cancers are a leading cause of mortality and account for 23% of cancer-related deaths worldwide. In order to improve outcomes from these cancers, novel tissue characterisation methods are needed in order to facilitate accurate diagnosis.
Rapid evaporative ionisation mass spectrometry ("REIMS") may be used for the real time identification of tissues, e.g., during surgical interventions. Coupling of mass spectrometry with a surgical diathermy device has resulted in a sampling technology which has an intra-operative tissue identification accuracy of 92-100%.
This sampling technology allows surgeons to more efficiently resect tumours intra-operatively through minimizing the amount of healthy tissue removed whilst ensuring that all the cancerous tissue is removed.
Rapid evaporative ionisation mass spectrometry analysis of biological tissue has been shown to yield phospholipid profiles showing high histological and histopathological specificity similar to Matrix Assisted Laser Desorption Ionisation ("MALDI"), Secondary Ion Mass Spectrometry ("SIMS") and Desorption Electrospray Ionisation ("DESI") imaging. A mass and/or ion mobility spectrometric signal is obtained by subjecting the cellular biomass to alternating electric current at radiofrequency which causes localized Joule-heating and the disruption of cells along with desorption of charged and neutral particles. The resulting aerosol or surgical smoke is then transported to a mass spectrometer and/or ion mobility spectrometer for on-line mass and/or ion mobility spectrometric analysis.
The known rapid evaporative ionisation mass spectrometry technique is typically performed on external tissues or tissues accessed through surgery.
It is desired to provide an improved method of and apparatus for rapid evaporative ionisation mass spectrometry.

Liquid trap or separator for electrosurgical applications


A stabilizing jack (10) for securement to the underside of a recreational vehicle. The jack includes a channel frame (25) formed with longitudinal trunnion flanges. A longitudinal screw (50) is rotatably mounted in the channel and drives a trunnion (38) that rides between the trunnion flanges (22a, 22b). A support leg (30) is rotatably connected to the trunnion. Rotation of the screw drives the trunnion towards an outboard end of the jack and lowers the support leg to its supporting position.

This invention relates generally to devices for stabilizing stationary recreational vehicles and more particularly to an improved stabilizer device mountable to the underside of such vehicle.
Recreational vehicles and trailers typically incorporate spring suspension systems mounted between the chassis frame and the wheels to provide a smooth ride during transit. While such suspension systems enhance passenger comfort and minimize vibration, they often detract from the stability of the passenger compartment when the vehicle is parked. For example, when passengers move about the compartment, the vehicle tends to rock both fore and aft as well as from side to side. Furthermore, this rocking motion is enhanced due to the inherent flexibility of the wheels and slight rolling thereof in response to forward and rearward weight shifting within the vehicle cabin.
The industry has addressed such vehicle stability concerns by developing various stabilizer jack devices and systems for use with the vehicles when stationary or parked. For example, such devices are disclosed in U.S. Pat. Nos. 3,565,396, 3,826,470, and 5,205,586.
One stabilizer jack device incorporates an elongated downwardly opening mounting channel formed with downwardly turned longitudinal marginal flanges. A cylindrical trunnion is formed with a transverse through a threaded bore for receipt of a drive screw rotatably mounted at one end of the mounting channel. The lateral opposite ends of the cylindrical trunnion pivotally mount a support leg extending longitudinally and downwardly therefrom. One end of a channel shaped strut has laterally spaced apart upwardly turned flanges and is pivotally mounted medially to the support leg and angles upwardly and longitudinally therefrom. A bracket at the opposite end of the mounting channel is formed with outwardly flared axle tabs for pivotally mounting to the opposite end of the strut. Difficulties with this stabilizer jack device were encountered in installed applications where the lateral flanges of the mounting channel and strut would spread laterally outwardly allowing the drive screw and strut to become racked and unbalanced in loading. This spreading of the upwardly turned flanges of the strut resulted in failure as the flanges slipped off of the axle tabs.
Another prior art jack device is a recreational vehicle stabilizer device having jack assemblies mounted at the laterally opposite extremities of telescopical jack housing channels for adjusting the stabilizer device to adapt to different width vehicles. While this device has enjoyed substantial commercial success, it is recognized that the stabilizing forces being directed through the jack housing to the vehicle frame allow for some degree of flex and play in the connections of such housing wherein the driving components of the jack assembly may rack or lock as weight is applied thereto from the interior of the vehicle. Furthermore, the jack assemblies resisted fore and aft longitudinal movement of the vehicle to only a minor extent. Thus, it was found that supplemental fore and aft restraint, supplied by for instance wheel blocks or chocks, was required.
In an effort to provide additional longitudinal restraint, other stabilizer devices provide a transverse frame member attached to the outer end of the jack housing and include angular extending support members attached between the lateral outer extremities of the transverse frame member and the jack assembly. Although these angular support members increase longitudinal stability, the additional components increase manufacturing costs, assembly time and complexity.
The foregoing illustrates limitations known to exist in present devices for stabilizing stationary recreational vehicles. Thus, it is apparent that it would be advantageous to provide an alternative directed to overcoming one or more of the limitations set forth above. Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter.


A pop-up enclosure system (30) for electronic equipment, includes a receptacle (31) adapted for mounting in a work-surface (15) and containing one or more electrical outlets (32) for connection of equipment thereto, and a bezel (33) supported by the receptacle and adapted for countersinking in said work-surface. A top plate (34) is dimensioned for closing an opening defined by the bezel, and a hinge (35) is mounted at an edge of the top plate and the bezel for hingedly attaching the top plate to the bezel so as to allow rotation of the top plate from a closed position to a fully open position wherein the edge of the top plate abuts an upper surface of the bezel. A releasable resilient opening force (37) is fixed to the receptacle and articulated to the top plate for opening the top plate.

Pop-up enclosures are known having a body portion that is recessed into a table top and a top plate that is substantially flush with the table and lifts off to provide access to connectors that are concealed when the top plate is closed. Such pop-up enclosures are described, for example, in U.S. Pat. No. 6,802,577, which describes an enclosure system having a saddle that is attached to a bezel and defines an open area for receiving an enclosure. The bezel defines an opening for receiving a top plate of the enclosure. An outer perimeter of the bottom surface of the bezel rests on edges of an opening cut through a table top. The enclosure pivots from a concealed position, in which the top plate is flush with the bezel, to an open position in which the face plate of the enclosure is exposed. A spring biases the enclosure towards the open position, while a latch maintains the enclosure in the concealed position.
As shown in FIG. 1 of U.S. Pat. No. 6,802,577, the top plate swings about a hinge axis close to a rear edge of the top plate. In the device disclosed by U.S. Pat. No. 6,802,577, the spring bias is constituted by a gas spring comprising a body into which a piston may be extended and retracted. In the normal state, the gas spring is extended and exerts force on the piston, which is thus applied to a lower inside surface of the top plate so as to urge it open. The top plate is closed against the force of the retracted gas spring and is latched by a catch so as to restrain the top plate in the closed position where it is flush with the top surface of the enclosure system. A similar arrangement is shown in U.S. Pat. No. 3,992,070.
Since the force exerted by the gas spring is predetermined by the type of device used and is generally a function of size, some tradeoff is usually called for between the desire for compactness of the pop-up enclosure, on the one hand, and the requirement that the top plate operate effectively, on the other. These two desiderata are, to some extent, mutually exclusive as will now be explained with reference to FIGS. 1 to 3 showing schematically in cross-section a detail of a prior art pop-up enclosure 10. The enclosure 10 includes a top plate 11 that has a rear edge 12 and is hingedly attached by a hinge axis 13 to a receptacle 14 that is flush mounted with a work surface 15. A gas spring 16 is pivotally anchored at one end 17 to an inside of the receptacle 14, its opposite end being pivotally attached to a support 18 mounted on the inner surface of the top plate 11 so as to be rotatable about a pivot axis 19.
Electronic equipment such as video, audio and power sockets represented by the box 20 in FIGS. 2 and 3 are mounted inside the receptacle 14 so as to be concealed by the top plate 11 when closed while being accessible when open. The equipment 20 occupies most of the central region of the receptacle, which limits the point on the lower surface of the top plate to where the gas spring 16 may be fixed. Specifically, the location of the pivot axis 19 determines the point of application of force by the gas spring 16, such that the greater the distance between the hinge axis 13 the pivot axis 19, the greater is the applied moment (for a given gas spring force) and vice versa. However, since most of the space within the receptacle is occupied, the gas spring 16 needs to be mounted behind the equipment. This generally requires that it be anchored via a bracket 21 that is fixed to an inner surface of the receptacle or an outer surface of the equipment 20. As the top plate opens, the gas spring extends and turns about its point of attachment to the bracket 21. Regardless of whether the bracket 21 is anchored to the receptacle or the equipment, it is clear that as the support 18 moves further away from the hinge axis 13, the lower point of attachment of the gas spring 16 must move further away from the equipment 20. This is well demonstrated in FIG. 3, which compares the two arrangements in FIGS. 1 and 2, the arrangement in FIG. 2 being illustrated by the dashed line.
It thus emerges that while mounting the support 18 farther away from the hinge axis 13 increases the moment of the gas spring 16 and facilitates opening of the top plate, it militates against compactness of the pop-up assembly.
Consequently, compactness is increased by bringing the pivot axis 19 closer to the hinge axis 13.
US D553,306 in the name of FSR, Inc. discloses a tabletop mounted connection box having a circular lid that turns about a hinge axis located toward a rear of the lid. Owing to its circular profile, the device is easily installed by drilling a hole in a work surface using a drill-mounted hole-saw, which is well within the capability of the average homeowner. The device is sold under the catalog names T3-AC2/T3-PC1/T3-PC1D and offers a low footprint and easy installation. However, it is designed for manual operation by pressing down on a tip of the lid near the hinge as shown to schematically in FIG. 4. This requires that the hinge axis 13 be displaced from the ridge of the lid in order to be able to apply an adequate moment.
It would be an advantage to use a gas spring or similar resilient bias force to lift the lid automatically. Theoretically, this might be done by anchoring a spring to a support pivot mounted near the ridge underneath the lid so as to apply a tensile force that turns the lid about the hinge axis. In practice, it does not appear to be feasible to do this to the device shown in US D553,306 for a number of reasons. First, the lid is connected to a concealed hinge via a bracket that is fixed to the lower surface of the lid with the result that the lid is vertical when fully opened. A spring would need to be affixed to the edge of the lid to pull it open to a vertical orientation and this is both neither esthetic nor practical. On the other hand, a spring mounted on the lower surface of the lid near the ridge will result in the lid being incompletely opened, thus restricting access to the equipment therein.
A gas spring is preferable to a coil spring because it opens slowly and in a controlled manner unlike a coil spring, which opens almost instantaneously upon release, resulting in too aggressive an action. However, the difficulties are compounded when attempting to automate opening of the lid using a gas spring without derogating from the compactness of the unit, as explained above.

Reduced profile pop-up electrical receptacle assembly


A unit drawing mechanism according to the invention is adapted for installation in a main unit. The mechanism includes a first and a second units, a plurality of supports, and a load-applying member. The first unit is movable along a first direction toward front of the main unit, to be drawn out thereof. Mounted in the first unit, the second unit is movable, with the first unit drawn out of the main unit, along a second direction perpendicular to the first direction, to be drawn out of the first unit. The supports are arranged at different positions along the second direction, for supporting the first unit movably along the first direction. The load-applying member is mounted in the first unit in such a manner that center of gravity of the first unit along the second direction is located between the supports whether the second unit is retracted in, or drawn out of, the drawn-out first unit.

The disclosed technology relates to a unit drawing mechanism for drawing a unit out from a main unit, and to an image recording apparatus for recording an image on a sheet being transported on a sheet transport path.
In electrophotographic image recording apparatus, a sheet is fed from a sheet feeding tray to an image recording section where an image is formed on the sheet. Then the sheet is output to a sheet output tray. A sheet may become jammed on its way on a sheet transport path. A sheet jam is likely to occur particularly in the image recording section. This is because a sheet tends to be curled while undergoing various processes in the image recording section such as: a developer-image transfer process performed by a transfer device; or a fusing process performed by a fusing device.
A sheet jam is also likely to occur in a reversing transport path on which, in duplex image formation (an image is formed on both sides of a sheet), a sheet with an image formed on a first side is reversed and transported back to the image recording section. This is because the duplex image formation involves a sheet passing through many bifurcations of the sheet transport path.
In the event of a sheet jam, image recording apparatus suspend an image forming process until all sheets present on the sheet transport path are removed. JP H09-134050A discloses that a sheet jammed in the image recording section is removed by drawing the image recording section in a forward direction out of the image recording apparatus and opening a side wall or the like of the section to expose the sheet transport path.
The foregoing configuration of the prior art apparatus, however, involves a small level of exposure of a portion of the sheet transport path located in the image recoding section, even with the image recording section drawn out and the side wall opened. Thus, this configuration renders it hard for a user to remove a jammed sheet. In particular, recent image recording apparatus with high functionality have a complex configuration that renders it hard to provide a large space for removing a jammed sheet.
In consecutive image formation that involves a plurality of sheets present on the sheet transport path, a user is necessitated, if only a small level of exposure of sheet transport path is available, to open side walls or the like of different portions of the image recording section in order to check if all the sheets are removed from the sheet transport path.
As a solution to the foregoing problem, a unit drawing mechanism adapted for use in an image recording apparatus has been proposed that includes a first unit and a second unit. The first unit, in which a first path as part of a sheet transport path is positioned, is movable along a forward direction to draw the first unit out of the apparatus. With the first unit drawn out of the apparatus, the second unit is movable along a direction, perpendicular to the forward direction, to draw the second unit out of the first unit. In the second unit, a second path as another part of the sheet transport path is positioned.
The proposed mechanism eliminates the need for provision of a dedicated space for drawing the unit 2 out of the unit 1 along the forward direction, since space for a user to remove a printed sheet also serves as the space for drawing the unit 2 out of the unit 1. Also, the proposed mechanism allows the second unit to be detached from the first unit by being drawn out of the first unit, thereby enabling the first and second paths to have a greater exposed area than in a conventional configuration where the first and second units are integrated in a single unit. Additionally, the second unit is slidably supported by a slide rail assembly.
For improved workability, it is preferable that the unit drawing mechanism has a minimum number of support members for supporting the first unit so that the first unit is movable. In the proposed mechanism, however, detachment of the second unit from the first unit involves a major shift in the center of gravity of the first unit. Therefore, repeated detachment and attachment of the second unit from and to the first unit causes deformation in the supports of the first unit, resulting in a decrease in positioning accuracy of the first and second units with respect to the apparatus. In order to ensure strength, further, it is necessary to provide a sufficient number of supports for the first unit.
Furthermore, the proposed mechanism is not provided with means for securing the second unit to the first unit so that the second unit does not move. This results in a decreased positioning accuracy of the second unit with respect to the first unit. This also may cause undesirable movement of the second unit drawn out of the first unit.
In light of the foregoing, a non-limiting feature of the disclosed technology provides a unit drawing mechanism with a simple configuration that maintains a high level of positioning accuracy of a first and a second units with respect to an apparatus provided therewith, that ensures a high level of positioning accuracy of the second unit with respect to the first unit by securing the second unit to the first unit so that the second unit does not move, and that prevents undesirable movement of the second unit drawn out of the first unit.

Unit drawing mechanism and image recording apparatus


A read head for a Wiegand wire has two C-shaped ferro-magnetic yokes in lateral alignment with one another, two magnets sandwiched between respective first and second legs-of the yokes, and a pickup coil wound on one of the legs of the read head. One magnet has a first polarity adjacent to the first leg of the first yoke, the other magnet has the first polarity adjacent to the second leg of the second yoke, and the reluctances of the two yokes are equal. When used in combination with a processor that processes the output pulses, a Wiegand token having one or more Wiegand wires therein may be detected by counting the number of output pulses of the read head and ascertaining the duration of time between occurrences of those pulses. Wiegand tokens having different values may have different numbers of Wiegand wires therein and/or different spacings between the Wiegand wires within the Wiegand token and, thus, the read head in combination with a processor can identify Wiegand tokens of different values.

This invention relates to a read head for reading a token or coin having a Wiegand wire therein, and is particularly directed to a read head for use in, for example, coin-operated machines, such as gambling machines, and which is capable of detecting the insertion of such coins/tokens by providing an electrical pulse in response to a switch in state of the Wiegand wire in the inserted token.
The Wiegand wire is a ferro magnetic wire having core and shell portions with divergent magnetic properties. The currently preferred type of Wiegand wire is disclosed in U.S. Pat. No. 4,247,601, issued on Jan. 27, 1981, and which is incorporated herein by reference. Read heads which are effective to provide an output pulse from a switch in state of the Wiegand wire are described in U.S. Pat. No. 4,263,523, issued Apr. 21, 1981, and U.S. Pat. 4,593,209, issued Jun. 3, 1986. A module employing the Wiegand wire that is effective to generate a pulse in response to a change in magnetic field is described in U.S. Pat. No. 4,484,090, issued Nov. 20, 1984.
Read heads for use with a Wiegand wire are currently employed in various access systems. Codes are incorporated in access cards and keys where the Wiegand wire is employed in the card or key to provide the encoding. One technique of positioning these wires in the access card and for reading the wires as the wires are passed over the face of a read head is described in said U.S. Pat. No. 4,593,209. The manner in which the Wiegand wires are encoded on a code strip carried in an access card is described in connection with the discussion of FIGS. 5 and 6 in said U.S. Pat. No. 4,593,209. As shown therein, the "zero" bit wires are all parallel to one another in a single column like the rungs of a ladder. The "one" bit wires are also parallel to one another in a single column. However, the center lines of the two columns are spaced from one another. Thus, the zero bits are read by one portion of the read head and the one bits are read by another portion of the read head. U.S. Pat. No. 4,736,122 discloses an improved read head of those devices discussed in the patents mentioned above. As shown in FIG. 1 of U.S. Pat. No. 4,736,122, the read head described therein is E-shaped with a polarized magnet at each of the three legs and the magnets are sandwiched between a thin yoke and a thick yoke. The thin and thick yokes forming set and reset fields, respectively.
The read head designs previously known have maximum air gap ranges that limit their usefulness to only select applications. For example, the above-mentioned access card having Wiegand wires therein can be read by previous read heads due to the relatively short distance between the Wiegand wires themselves and the face of the read head. Further, such read heads are inappropriate for reading Wiegand wires that do not by themselves represent either a zero bit or a one bit, such as Wiegand wires that are embedded within a novel coin or token.
It is therefore an object of this invention to provide a read head that has a greater air gap range than that of previous devices.
It is another object of this invention to provide a read head that is capable of reading a novel coin or token having one or more Wiegand wires therein.
Various other objects, advantages and features of the present invention will become readily apparent to those of ordinary skill in the art, and the novel features will be particularly pointed out in the appended claims.


An illumination system for a microlithography projection exposure installation is used to illuminate an illumination field with the light from a primary light source (11). The illumination system has a light distribution device (25) which receives light from the primary light source and, from this light, produces a two-dimensional intensity distribution which can be set variably in a pupil-shaping surface (31) of the illumination system. The light distribution device has at least one optical modulation device (20) having a two-dimensional array of individual elements (21) that can be controlled individually in order to change the angular distribution of the light incident on the optical modulation device. The device permits the variable setting of extremely different illuminating modes without replacing optical components.

1. Field of the Invention
The invention relates to an illumination system for a microlithography projection exposure system for illuminating an illumination field with the light from a primary light source.
2. Description of the Related Art
The efficiency of projection exposure systems for the microlithographic production of semiconductor components and other finely structured components is determined substantially by the imaging properties of the projection objectives. Furthermore, the image quality and the wafer throughput that can be achieved with the system are also determined substantially by properties of the illumination system arranged upstream of the projection objective. This must be capable of preparing the light from a primary light source, for example a laser, with the highest possible efficiency and, in the process, of producing the most uniform intensity distribution possible in an illumination field of the illumination system. Moreover, it should be possible to set various illuminating modes (settings) of the illumination system, in order for example to optimize the illumination in accordance with the structures of the individual patterns (e.g. on masks, reticles) to be imaged. Possible settings between different conventional settings with various degrees of coherence and also annular field illumination and dipole or quadrupole illumination are usual. The unconventional illumination settings for producing off-axis, oblique illumination can be used inter alia to increase the depth of focus by means of two-beam interference and also to increase the resolving power.
EP 0 747 772 describes an illumination system having a zoom-axicon objective, in whose object plane there is arranged a first diffractive raster element with a two-dimensional raster structure. This raster element is used to increase the geometric light guidance valve (or extendue) of the incident laser radiation slightly and to change the form of the light distribution in such a way that, for example, the result is an approximated circular distribution, annular distribution or quadrupole distribution. In order to change between these illuminating modes, first raster elements are interchanged. A second raster element, which is located in the exit pupil of the objective, is illuminated by the corresponding light distribution and forms a rectangular light distribution, whose form corresponds to the entry surface of a following rod-like light mixing element. By means of adjusting the zoom-axicon, the annularity of the illumination and the size of the area that is lit up (illuminated) can be adjusted.
EP 1 109 067 (corresponding to US 2001001247) describes an illumination system in which a changing device is provided for the optional changing of different diffractive optical elements in the light path of the illumination system. By interchanging the diffractive optical elements, various illuminating modes can be set. The system manages without a zoom-axicon module.
Other known possibilities for achieving off-axis illumination are shown, for example, in the U.S. Pat. No. 5,638,211, EP 500 393 B1 (corresponding to U.S. Pat. No. 5,305,054), U.S. Pat. No. 6,252,647 or U.S. Pat. No. 6,211,944.
In the case of illumination systems which operate with interchangeable optical elements (for example diffractive optical elements or spatial filters) in order to set different illuminating modes, the number of different illumination settings is limited by the number of different changeable elements. Appropriate changing devices can be constructionally complex.
DE 199 44 760 A1 discloses an illumination device for printing plates which permits modulation of the illumination intensity in the integrated digital screen imaging process (IDSI). In this case, the light from a light source falls onto a digital light modulator having a two-dimensional array of cells, which can be activated and deactivated via a computer-controlled system in order to deflect a specific pattern onto a light-sensitive substrate, which is moved relative to the light modulator. In one embodiment, the light modulator comprises a micro mirror arrangement (digital mirror device, DMD) having a large number of individual mirrors that can be driven individually. During printing, those mirrors which are not used for the exposure of the light-sensitive material are tilted in such a way that they deflect the light beam falling on them away from light-sensitive material. By means of the control system, the number of individual mirrors used in the exposure is thus changed. A similar system is disclosed by WO 00/36470.

Illumination system for a microlithography projection exposure installation


The invention refers to a method for optimising the data communication in a network comprising a wireless radio network using connection oriented protocol (TCP) over internet protocol (IP). The network comprises a router (SGSN) intervening the connection oriented setup between a host (SERVER) and a client (MS), and changing the maximum segment size (MSS, ms) into a maximum segment size (MSS, sgsn) based on the router's (SGSN) knowledge about the radio network.

In the field of data communication for wireless networks, TCP is used as a connection oriented protocol that fragments and reassembles a byte stream into discrete messages or packets. Furthermore, IP-protocols are used in the next lower layer for delivering IP-packets, e.g. by packet routing.
The TCP service is obtained by having both a host (hereinafter also called SERVER) and a client (hereinafter also called mobile station or MS) create end points called sockets. Each socket has a number (address) comprising an IP address of the host and a 16-bit number local to that host, called a port.
To obtain TCP service a connection must be established between a socket on the SERVER, and a socket on the MS. A socket may be used for multiple connections at the same time. Every byte on a TCP connection has its own 32-bit sequence number used both for acknowledgements and for a window mechanism, which use a separate 32-bit header field.
The sending and receiving TCP entities exchange data in the form of segments. A segment consists of a fixed 20-byte header (plus an optional part) followed by zero or more data bytes. The TCP software decides how the segments should be. It can accumulate data from several writes into one segment or split data from one write over multiple segments. Two limits restrict the segment size. Firstly, each segment, including the TCP header, must fit in the 65,535 byte IP payload. Secondly, each network has a maximum transfer unit (MTU), and each segment must fit in the MTU.
The MTU, is the largest physical packet size, measured in bytes (B), that a network can transmit. Any messages larger than the MTU are divided into smaller packets before being sent.
Every network has a different MTU, which is set by the network administrator. For example, on Windows 95, a user can also set the MTU of his machine. This defines the maximum size of the packets sent from that computer onto the network. Ideally, it is desired that the MTU is the same as the smallest MTU of all the networks between a certain machine and a message's final destination. In practice, the MTU is generally a few thousand bytes and thus defines the upper bound on segment size. If a segment passes through a sequence of networks without being fragmented and then hits a network whose MTU is smaller than the segment, the router at the boundary fragments the segment into two or more smaller segments, which slows down transmission speeds.
In the field of wireless communication there is a certain router in the interface (Gb or Iu) between a land line bound network and the wireless network, The wireless network may comprise MS:s in the form of mobile telephones for mobile telephone services, or mobile telephones or computers for data communication. The wireless network may be in the form of the so called 2 G or 2.5 G standard (the Gb interface) for the use of, for example, GSM or EDGE. The wireless network may also be in the form of the so called 3 G standard (the Iu interface) for the use of, for example, WCDMA. The router breaks down the data stream from the land line network into smaller segments according to the given standard. In the present GPRS standard the router is labelled SGSN, which is a node in a GPRS infrastructure that is responsible for the delivery of data packets from and to the mobile stations within its service area. Its tasks include packet routing and transfer, mobility management (attach/detach and location management), logical link management, and authentication and charging functions. The location register of the SGSN stores location information and user profiles of all GPRS users registered with this SGSN as of June 2001.
A segment that is too large for a network is broken up by the router into multiple segments. Each new segment gets its own IP header, so fragmentation by routers increases the total overhead because each additional segment adds 20 bytes of extra header information in the form of an IP header.
Each host is allowed to specify the maximum TCP payload it is willing to accept, but all Internet hosts are required to accept TCP segments of 536+20 bytes (536 bytes of TCP payload and 20 bytes TCP header+20 B of IP header ending up at an MTU of 576 B). During setup of the TCP connection, each side can announce its maximum segment size (MSS) and can also see the suggested MSS from the counterpart. According to the present TCP/IP standard, the minimum MTU that can be sent without risking fragmentation or MTU Discovery is 576 B in a correctly configured network.
A problem with prior art occurs when the SGSN is forced to fragment the IP segment(s) from the land line network into segments of lesser size in order to satisfy the demands from the wireless network. The lesser sized segments are not optimised by forehand, but serves only to fit the standard of the MS. As a consequence the last of the lesser sized segments may comprise only a small amount of information instead of a complete utilisation of the segment. By not utilising the complete segment for the transport of information, the overall performance of the system is not optimal.
Therefore, there is a need for an improved handling when setting up a connection between a host and a client using a connection oriented protocol in a system comprising a wireless network.


A system and method for a certificate verifier to make a request to a certificate distribution server for a copy of another entity's digital certificate and to have the certificate distribution center validate it. The certificate distribution center can request the appropriate certificates and validation thereof from a number of certificate authorities or may alternatively obtain copies from a certificate cache and validate the copies against a revocation list server.

In asymmetric encryption technology, each user generates a pair of keys known as a public key and a private key. The public key is widely disseminated and used by others to encrypt communications intended for the owner of the public key. Once the message has been encrypted with the public key, it can only be decrypted with the corresponding private key. This is the basis of public key encryption.
The problem with this technology is that the sender needs to have a way of guaranteeing that the public key used for encryption does indeed belong to the recipient. Otherwise, the sender could unintentionally encrypt a message that could only be decrypted by some mischievous third party. A method was therefore needed for users to be able to have a high degree of assurance that the owner of a public key was indeed the intended recipient.
Digital certificates were invented to solve this problem. A recognized certificate authority issues a certificate binding the public key of a subscriber to his real world identity. The certificate is digitally signed by the recognized issuing authority. A message is digitally signed in effect by encrypting it with a private key. The message can then only be decrypted with the corresponding public key, and provided the user has a high degree of trust in the certifying authority, he will then have assurance that the public key contained in the certificate does indeed belong to the user to whom it is bound.
Digital certificates generally follow the X.509 standard, developed by the International Standards Organization (ISO) and the Comité Consultatif Internationale Telegraphique et Telephonique (CCITT). These certificates create a binding between an entity's public key and its identity. Obtaining authentic copies of public key certificates is critical in deploying secure public key systems. Often a digital certificate is stored in a publicly accessible repository such as an LDAP or X.500 directory.
In practice, implementers of certificate revocation lists have discovered that they are difficult to manage because they can become very large and not usable by some certificate verifiers such as smartcards or mobile phones. Further, since these lists are issued only periodically, there is a time gap between when a certificate is revoked by its issuer and when it appears on a publicly available list of revoked certificates. Methods such as the online certificate status protocol have been developed as a means to make requests to validation services to determine whether a particular certificate is currently valid, however, this requires that a certificate verifier make at least two requests, one to obtain a copy of the certificate and another to obtain the current validity status of the certificate. Further requests may be required to obtain all certificates needed to construct a certificate chain that can be validated up to a trusted root held by the verifier. In many applications, in particular those where the verifier is a mobile phone, smartcard or other client devices that are relatively constrained with respect to storage capacity, processing power and communication bandwidth, the current solutions are not practical.
It will be apparent from the foregoing that prior certificate issuance and validation systems and methods are generally designed to allow a user to obtain a validated digital certificate, but are slow and cumbersome to the user under various circumstances.

System and method of looking up and validating a digital certificate in one pass


A silver halide color photographic light sensitive material is disclosed, comprising a support having thereon photographic component layers including a blue-sensitive silver halide emulsion layer, green-sensitive silver halide emulsion layer and a red-sensitive silver halide emulsion layer, wherein the green-sensitive silver halide emulsion layer comprises a magenta coupler represented by the following formula: ##STR1##

As couplers generally employed in silver halide color photographic light sensitive materials, there are known a yellow coupler comprised of a open-chained ketomethylene compound, a magenta coupler comprised of a pyrazolone or pyrazolotriazole compound and a cyan coupler comprised of a phenol or naphthol compound.
5-Pyrazolone compounds have conventionally employed as a magenta coupler. Known pyrazolone magenta couplers are described in U.S. Pat. Nos. 2,600,788 and 3,519,429 and JP-A 49-111631 and 57-35858 (hereinafter, the expression, "JP-A" refers to unexamined and published Japanese Patent Application). However, as described in The Theory of the Photographic Process, Macmillan Co. 4th Edition (1977), page 356-358; Fine Chemical Vol.14, No.8 page 38-41 (published by CMC) and Abstracts of Annual Conference in 1985 of the Society of Photographic Science and Technology of Japan page 108-110, a dye formed from the pyrazolone magenta coupler has an unwanted side absorption and its improvement is desired.
On the other hand, as described in the above references, a dye formed from the pyrazolotriazole magenta coupler has no side absorption. This coupler is superior one, as described in the above references, U.S. Pat. Nos. 3,725,067, 3,758,309 and 3,810,761. However, light fastness of a azomethine dye formed from the pyrazolotriazole magenta coupler is markedly low, leading to deterioration in photographic performance of silver halide color photographic light sensitive material and particularly those used for prints.
Studies of improvements in the light fastness have been made so far. JP-A 59-125732, 61-282845, 61-292639 and 61-279855 disclose a technique in which a pyrazoloazole magenta coupler is employed in combination with a phenol compound or phenyl ether compound; JP-A 61-72246, 62-208048, 62-157031 and 63-163351 disclose a technique of using an amine compound in combination. JP-A 63-24256 proposes a pyrazoloazole magenta coupler having an alkyloxyphenyloxy group. However, improvements in light fastness of magenta dye images through these techniques were proved to be insufficient and further improvements are strongly desired.

Silver halide color photographic light sensitive material


The combined shock absorbing seat post and air pump assembly is for use on a bicycle or the like. The assembly comprises two hollow tubes inserted one into the other defining a compression chamber from which the compressed air may be sent to an inflatable device such as a tire. A shock absorbing mechanism is further provided for attenuating jarring conditions while operating the bicycle on a rough surface. The shock absorbing mechanism comprises an helicoidal compression spring in which the tension can be adjusted by hand upon rotation of a screwed element. The assembly provides a very practical and very compact assembly that combines the advantages of an air pump in the seat post and the advantages of an easily adjustable shock absorber mounted on the seat post.

As there is a constant need for more practical and more compact bicycles, there is also a greater need for comfort. There is therefore a constant demand for devices that improve the practicality and the comfort of the bicycles.
One practical device on a bicycle is the air pump used for inflating a flat tire. It has already been disclosed that the air pump be located within the seat post for reducing the space taken on the frame itself and avoiding the pump to be lost or stolen.
On the other hand, comfort is also an important factor which many users are seeking. For that purpose, shock absorbers are often found on the frame of a bicycle.
Since most of the weight of a bicycle user is on the seat, seat posts shock absorbers and cushioning arrangements are very suitable for attenuating jarring conditions while operating the bicycle on rough surfaces. However, the shock absorbers known in the art cannot be easily adjusted according to the weight of the user and the conditions of the road or track.

Combined shock absorbing seat post and air pump assembly

Societe De Developpement De L'ile Bizard Inc.


The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

The fabrication and implementation of electronic circuits involves electrically connecting devices through specific electronic paths. In particular, very short intra-transistor circuit electrical paths are commonly formed. For example, a drain or source of a transistor can be electrically connected to the gate of the same transistor. Also, other very short path length electrical circuits are commonly formed. Short path length electrical connections are commonly referred to in the art as local interconnects.
Present processes for fabricating such local interconnects presents some problems which have not yet been successfully addressed in the industry. The following few diagrams illustrate some of the more significant problems identified in state of the art local interconnect manufacturing processes.
FIG. 1A is a simplified schematic depiction of a single transistor formed on a silicon wafer in accordance with the present state of the art. The following depicted process is a conventional process used to form a local interconnects structure. The depicted structure includes a wafer having a transistor 100 formed thereon. The transistor is generally isolated from other transistors and circuit structures on the wafer using isolation structures. In the depicted structure, the isolation is accommodated using shallow trench isolation (STI) structures 110. Also, the transistor and associated substrate are generally covered with one or more etch stop layers 111 which facilitate fabrication. Over the entire substrate is an inter-layer dielectric material 112, also known in the industry as an ILD.
Continuing with the description of FIG. 1A, the transistor 100 includes a gate portion 101 having a top gate contact 101c formed thereon. The gate contact 101c is configured to facilitate electrical contacts to the gate 101. Also, the gate 101 commonly has spacers 102 arranged on the sides to enhance electrical performance. Additionally, the transistor 100 includes a drain region 103d and a source region 103s, each of which include an associated electrical contact (104s and 104d respectively). To establish a local interconnect the gate 100 can, for example, be electrically connected with the source 103s. Such connection is typically achieved by electrically connecting the gate contact 101c with (in this case) the source contact 104s. FIGS. 1B, 1C, and 1D, 1E, 1F illustrate aspects of one conventional process for achieving this connection and some of the drawbacks of existing methodologies for its construction.
In order to establish such a local interconnect, portions of the ILD 112 and the etch stop 111 must be selectively removed. In one commonly employed conventional process (depicted by FIGS. 1B and 1C) a portion of the substrate is masked and then the surface is etched. For example, a photo resist layer 120 is patterned to include an opening 121 that will define the location of the local interconnect. A standard etch process (i.e., a plasma etch process) is used to remove the ILD 112. When the etch process reaches the etch stop layer 111 located over the gate 101, the etch process slows significantly over the gate 101. However, the etch process continues relatively unimpeded in the region over the source 103s. Unfortunately, the etch protection provided by the etch stop layer 111 is not perfect, and the etch stop layer 111 is eroded while the process removes the ILD 112. Thus, the etch stop layer 111 becomes thinner on top of the gate 101 and also in the regions near the top of the exposed spacer 102. These thickness variations lead to some significant process difficulties which were not as important when larger feature sizes were used (e.g., 1 micron technologies). However, for deep sub-micron feature sizes (e.g., for 0.18 micron CMOS technologies or smaller) certain process difficulties have a more pronounced effect on the resultant semiconductor structures.
FIG. 1C schematically depicts a simplified cross section view of a final etch profile resulting from a conventional process. The ILD 112 is removed in the opening 121. In a subsequent etch using an alternative chemistry, the etch stop layer 111 is also removed in the opening 121. However, as previously hinted at, the removal of the ILD 112 in one portion of the etched surface before the remainder of the ILD is removed means that while the remaining portions of the ILD layer are being etched away, the same etch process is working on the exposed etch stop layer 111. This leads to uneven erosion of the etch stop layer 111. Consequently, when the unevenly eroded etch stop layer 111 is etched away the substrate under the prematurely thinned etch stop layer 111 can be come damaged. This happens because the etch process is designed to remove all of the etch stop 111, including the thickest (un-eroded) layer of etch stop 111. However, where the etch stop has been previously eroded the etch process begins to etch the underlying layers. This is a very undesirable outcome. Additionally, circuit design and process technologies extend manufacturing technologies into the deep sub-micron range the processes become extremely sensitive to over etch problems. This is particularly problematic for feature sizes of less than 0.15 micron and especially so as process technologies extend below the sub 0.09 micron (90 nm) range.
FIGS. 1D, 1E, 1F illustrate some issues presented by conventional manufacturing processes used today. One difficulty is illustrated in the simplified depiction of FIG. 1D. As explained above, when the ILD is removed from the gate 101 some ILD remains above the source 103s. Therefore, when ILD etching continues to remove the ILD above the source 103s some of the etch stop layer 111 is removed in the uncovered regions. Thus, as shown, the etch stop layer 111 is thinner above the gate 101 and also above the spacer 102. In a conventional process, etch selectivity between the ILD etchant and the material comprising the etch stop layer 111 reduces this damage. However, due to ever shrinking critical dimensions even the relatively small damage done to the etch stop 111 during this ILD etch is significant enough to pose a serious problem. When the etch stop 111 is etched away, all of the thin portion 111g of the etch stop 111 will be gone, whereas some portion of the thicker layer 111s will remain. Subsequent etching will remove the rest of the thicker layer 111s, but, some portion of the substrate underlying the thin portion 111g of the etch stop 111 (here, for example, the source 103s and portions of the exposed spacer 102) will also be removed. This can have drastic effects of the performance of the resulting circuit. For example, the gate electrode 107 can be etched resulting in serious fluctuations in the gate current.
Additionally, the spacer 102 can be eroded 102e as shown in the simplified FIG. 1E. This is especially problematic near the top of the spacer 102. Such erosion can result in altered transistor parametrics.
FIG. 1F is a simplified depiction of a condition that can occur using conventional processes where an overetch condition caused by ILD thinning and excessive etching occurs. For example, the described overetch can etch through the etch stop 111 into the STI 110 creating an STI overetch condition that deepens the STI recess 113. This can cause increased junction leakage that, among other problems, can lead to higher power consumption. As can be expected, these and other related conditions, are highly undesirable and moreover, increasingly difficult to address using conventional processes.
For the reasons stated above, as well as other reasons, there is a need in the art for alternative process methods capable of establishing local interconnects used in integrated circuits.

Local interconnect manufacturing process


A component-based system and method is provided for generating and processing multi-dimensional gridded mesoscale meteorological projections. In embodiments, the system includes four integrated processes for data storage, retrieval, manipulation, communication, processing, and end user application tasks. Two or more components may interface for performing tasks. A data component stores, retrieves, and manipulates data utilizing functions under conditions of variable internet and non-internet connectivity. A communications component transmits and receives data to/from the data component for manipulation by the processing component. The processing component includes an artificial intelligence machine learning component and logic for manipulating the data to generate gridded mesoscale meteorological projections arrayed spatially and temporally. A post-processing component allows users to receive and retrieve automated projections from the data repository in a format suitable for end user application to automatically support and enhance the accuracy of computationally complex but tractable position, navigation, and timing solutions.

This disclosure is in the field of systems and methods that facilitate the use of computer implemented task management for generating and processing spatially and temporally delineated 3-dimensional mesoscale meteorological projections for accurate position, navigation, and timing.
Mesoscale meteorological phenomena are atmospheric conditions that have typical spatial scales typically ranging between 10 km and 1000 km in horizontal extent and of variable vertical height in the Earth's lower atmosphere (e.g. the troposphere, the average height being dependent on location and generally being in a range of up to 6 km, up to 14 km, and up to 18 km above the earth's surface depending on geographic location, the troposphere being of greatest height at the Equator and of lowest height at the North and South Poles). Examples of mesoscale parameters include air temperature, wind speed, wind direction, relative humidity, atmospheric pressure, density, atmospheric stability, thunderstorms, gap winds, downslope windstorms, land-sea breezes, and squall lines. Many of the weather parameters that most directly impact human activity occur on the mesoscale making accurate projections of mesoscale meteorological conditions essential to position, navigation, and timing (PNT) solutions. The embodiments in this disclosure utilize a component-based computer implemented system to generate and process multi-dimensional gridded mesoscale meteorological projections with or without reliance on internet connectivity to automatically support and enhance the accuracy of computationally complex but tractable position, navigation, and timing solutions such as but not limited to ballistic, aviation, maritime, and ground transportation applications and support adjustments or corrections along the parabola in PNT along a ballistic trajectory or non-ballistic path.

Component-based system for computer implemented multi-dimensional gridded mesoscale meteorological projection


Systems and methods are provided for receiving input data to be processed by an encrypted neural network (NN) model, and encrypting the input data using a fully homomorphic encryption (FHE) public key associated with the encrypted NN model to generate encrypted input data. The systems and methods further provided for processing the encrypted input data to generate an encrypted inference output, using the encrypted NN model by, for each layer of a plurality of layers of the encrypted NN model, computing an encrypted weighted sum using encrypted parameters and a previous encrypted layer, the encrypted parameters comprising at least an encrypted weight and an encrypted bias, approximating an activation function for the level into a polynomial, and computing the approximated activation function on the encrypted weighted sum to generate an encrypted layer. The generated encrypted inference output is sent to a server system for decryption.

Mimicking a human's cortex, Neural Networks (NN) enable computers to learn through training. With the recent progress on graphics processing unit (GPU) based computing capabilities, NN have received major improvements such as Convolutional Layers, Batch Normalization, and Residual Blocks. As part of the Deep Learning (DL) field, Deep Neural Networks (DNN) have revolutionized the creation of software based applications for problems with a non-deterministic solution space (e.g. object detection, facial recognition, autonomous driving, video processing, among others).
But, GPU hardware and labeled data sets come at a cost. In addition, NN training is data, time, and energy-intensive. This makes the outcome of DL training very valuable, including, for example, the topology, the number and type of hidden layers including design characteristics (e.g., defined before training), and the model itself, including the values of all the parameters in the trained network.
Furthermore, with the rise of edge computing and the Internet of Things (IoT), NN are meant to be deployed outside of corporate boundaries, closer to customer business, and in potentially insecure environments. This new paradigm calls for solutions to protect IP of distributed DL inference processing systems, with DNN deployment and execution on decentralized systems. The lack of solutions for IP protection exposes trained NN owners to reverse engineering on their DL models, allowing attackers to steal trained NN models.

Encrypted protection system for a trained neural network


The present disclosure provides method and apparatus for identifying flaky tests. Historical running data of a test case may be obtained. Statistical analysis may be performed based on the historical running data. It may be determined whether the test case is a flaky test based on the statistical analysis.

During software program developments, program testing may be performed on a developed program, e.g., a program product or a segment of program code, in order to validate the program. A number of test cases may be run for testing the program. Some test cases may have a running result of "pass", while other test cases may have a running result of "failure". Flaky tests may be one of reasons causing the running result of failure. Herein, a "flaky test" refers to a test case that behaves randomly and may lead to both a pass result and a failure result even with the same program.


The implementations described include an audio canceling device that receives and audio signal from within an environment, identifies desired and undesired audio from the received audio signal and generates an attenuation-signal for use in canceling out or reducing the volume of the undesired audio at a canceling location. In addition, the audio canceling device, may determine a time delay before the attenuation-signal should be transmitted from an output based on a distance between the undesired audio source location and the canceling location and a distance between the output and the canceling location.

Homes are becoming more wired and connected with the proliferation of computing devices such as desktops, tablets, entertainment systems, and portable communication devices. As these computing devices evolve, many different ways have been introduced to allow users to interact and communicate with those devices and with each other, such as through mechanical devices (e.g., keyboards, mice, etc.), touch screens, motion detectors, voice control and gesture recognition systems.
One drawback with an increased number of computing devices is the added noise present in a room that is generated by those devices and/or the people using those devices. For example, if there are two people in a room, one talking on a telephone and one watching television, it may be difficult for the person watching television to hear the television audio due to the added noise from the person talking on the telephone.

Attenuating undesired audio at an audio canceling device


In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor in the ith (1≦i≦n−1) functional block and the source voltage input terminal of the NMOS transistor therein are connected bijectively with the source voltage input terminal of the PMOS transistor in the i+1th functional block and the substrate voltage input terminal of the NMOS transistor therein. In the nth functional block, the substrate voltage input terminal of the PMOS transistor and the source voltage input terminal of the NMOS transistor are connected to their voltage supply terminals, respectively.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for reducing the power consumption of a semiconductor integrated circuit to which a forward body bias is applied.
2. Description of the Background Art
Attempts have been made to improve the degree of integration and the operation speed of semiconductor integrated circuits by providing a large number of insulated-gate field effect transistors such as MOSFETs and MISFETs and by reducing the thickness of the gate oxide film while shortening the channel length by miniaturization processes. However, this leads to a decrease in the transistor threshold voltage and an increase in the proportion of the leak current to the power consumption. Moreover, the shortened gate length results in significant variations in characteristics of MOS transistors such as the threshold voltage. As a countermeasure, a DVS (Dynamic Voltage Scaling) technique is known in the art, which realizes a reduction in the power consumption of a semiconductor integrated circuit by suppressing the leak current by dynamically changing the voltage value of the voltage supplied from the power supply circuit according to the amount of processing to be done by a processor and a SOC (System On chip).
With CMOS devices, the characteristics can be improved to some extent by adjusting the source-substrate voltage, i.e., the body bias. Specifically, if a forward body bias (FBB) is applied to a CMOS device, the threshold voltage and the operating voltage of a MOS transistor decrease, thereby making various improvements such as a suppression in the characteristics variations, a decrease in the power consumption, an increase in the operating speed (see, for example, Non-Patent Document 1). With a FBB-controlled semiconductor integrated circuit, the area efficiency is improved by employing a layout in which a substrate potential supply cell including a metal line for supplying the body bias is sandwiched between logic cells (see, for example, Patent Document 1).
Another approach to realizing a lower power consumption is to use charge reusing circuits (so-called "charge recycling circuits") to thereby increase the power conversion efficiency of a power supply circuit, e.g., a linear regulator circuit (see, for example, Patent Document 2).
Patent Document 1: Japanese Laid-Open Patent Publication No. 2001-148464
Patent Document 2: Japanese Patent No. 2774244
Non-Patent Document 1: M. Miyazaki, et al., "A 175 mV Multiply-Accumulate Unit using an Adaptive Supply Voltage and Body Bias (ASB) Architecture", ISSCC 2002/SESSION 3/DIGITAL SIGNAL PROCESSORS AND CIRCUITS/3.4
However, as pointed out in Non-Patent Document 1, if the forward body bias applied to the CMOS device exceeds a certain level, the leak current rapidly increases and the power consumption increases while the frequency characteristics of the CMOS device deteriorate. This is because as the body bias increases, the current flowing through a forward diode, a parasitic bipolar, etc., formed by a P substrate, an N well, a P well, a source region diffusion layer, etc., will have a more significant influence on the CMOS device. Therefore, if an excessively large forward body bias is applied to the CMOS device, it will rather deteriorate the operating characteristics.
In recent years, the power consumption of a semiconductor integrated circuit is reduced by lowering the operating voltage of CMOS devices. However, if a very high forward body bias is applied to a CMOS device operating at a low voltage, the substrate voltage in the N well becomes lower than that in the P well, resulting in a forward current flow in the PN junction diode formed by these wells, whereby the substrate voltage of the P well will be lower than the actually applied body bias. Since there is a forward current in the PN junction diode formed by a P substrate and an N well, the substrate voltage in the N well will be higher than the actually applied body bias. Thus, with CMOS devices operating at low voltages, it is not possible to apply a very large forward body bias, and it is therefore difficult to improve the characteristics by the FBB control. With the layout of a semiconductor integrated circuit disclosed in Patent Document 1, it is difficult to apply a sufficient body bias in portions away from the substrate potential supply cell because of the leak current due to a parasitic bipolar and the well resistance.
Based on the technique disclosed in Patent Document 2, it is possible to expect some reduction in the overall power consumption by dividing the voltage supplied from the power supply circuit and supplying the divided voltages to different stages of semiconductor integrated circuits connected together. In order to increase the number of stages of semiconductor integrated circuits to be connected together, it is necessary to increase the voltage supplied from the power supply circuit. However, increasing the voltage supplied from the power supply circuit by boosting the battery voltage of a battery-powered device, for example, is not practical because the power consumption will be large in other portions. Where the voltage supplied from the power supply circuit is not substantially increased, it is then necessary to lower the operating voltage of the semiconductor integrated circuits. However, it will then be difficult to realize the characteristics improvements by the FBB control.

Forward body bias-controlled semiconductor integrated circuit


A swash plate which is made of an iron-based or aluminum-based material and is used in a single-side compression type swash-plate compressor. A flame-sprayed copper-based alloy layer is formed on at least a sliding surface with a first shoe in a compression space side. The flame-sprayed copper-based alloy layer contains in total, by weight percentage, not less than 0.5% and not more than 50% of one or more kinds selected from not more than 40% of lead, not more than 30% of tin, not more than 0.5% of phosphorus, not more than 15% of aluminum, not more than 10% of silver, not more than 5% of silicon, not more than 5% of manganese, not more than 5% of chromium, not more than 20% of nickel, and not more than 30% of zinc and the balance essentially copper and impurities. Electrolytic plating, electroless plating, lubricant coating, phophatizing or hardening is applied on at least a second sliding surface with a second shoe in the side opposite to the compression space.

In the swash-plate type compressor, a swash-plate is rigidly secured obliquely to a rotary shaft or is secured obliquely to a rotary shaft in such a manner that its slanting angle is variable. The compression and expansion are carried out by means of rotating the swash-plate which increases or decreases the volume of a partition space within a compressor, depending upon the rotation of the rotary shaft. Such swash plate is caused to slide on a sliding member referred to as a shoe, and reciprocates a piston via the shoe. The cooling medium can therefore be compressed and expanded in the stated space.
A salient point in the sliding conditions of a swash-plate is that, during the initial operational period of a compressor, the cooling medium reaches the sliding part prior to the lubricating oil reaching the sliding part; thus the cooling medium has a rinsing effect on the lubricating oil which remains on the sliding part, with the result that the sliding condition is in a dry condition free of lubricating oil. The requirements for the sliding condition of the swash plate are therefore very severe.
The sliding properties, which are required for a swash-plate used under the condition described above, are seizure resistance, wear resistance, and the like. Proposals have thus been made to add hard matters into the aluminum material for enhancing the wear resistance, to improve the material of the swash plate, and to subject an iron-based swash-plate to heat treatment or surface treatment for enhancing the hardness and hence wear-resistance.
One of the present applicants proposed in Japanese Unexamined Patent Publication No. Sho 51-36611 to bond sintered Cu material on the shoe in the case of an iron-based swash plate. That is, an iron-based swash plate was heretofore subjected to hardening treatment. However, when the material of the opposed member, i.e., the shoe, is an iron-based material, the sliding takes place between identical kinds of materials thereby incurring a problem that a seizure is liable to occur. Sintered copper alloy is used for the opposing material (shoe) opposed to an iron-base swash plate, so as to avoid the above mentioned problem.
In addition, it was also proposed to apply tin plating on the iron-based swash-plate so as to avoid the sliding between identical kinds of materials and hence to enhance the seizure resistance.
In the ordinary swash-plate type compressor, the cooling medium is sucked into and compressed in the cylinder bores at both sides of a piston. In a recently produced single-side compression type swash-plate compressor, the compression and suction are carried out usually only in the rear (R) side. This swash plate compressor is described with reference to an example of the variable volume type compressor disclosed in Japanese Unexamined Patent Publication No. 6-288,347 filed by one of the applicants.
As shown in FIG. 13, the front housing 2 is secured to one side of the cylinder block 1, while the rear housing 3 is secured to the other side via the valve sheet 4. The driving shaft 6 is included in the crank space 5 formed by the cylinder block 1 and the front housing 2 and is rotatably supported by the bearings 7a and 7b. A plurality of the cylinder bores 9 are formed in the cylinder block 1 at a location where they surround the driving shaft 6. A piston 10 is inserted in each cylinder bore 9.
A rotor 16 is synchronous rotatably supported by the driving shaft 6 in the crank space. In addition, a sleeve 12 having a spherical surface is slidably supported by the driving shaft 6. A compression spring 13 is provided between the rotor 16 and the sleeve 12 having a spherical surface and forces the sleeve having a spherical surface in the direction toward the rear housing 3. A rotary swash plate 14 is rotatably supported on the outer peripheral surface of the sleeve 12 having a spherical surface. In the condition of the compression spring 13, which is at the maximum shrinkage condition as shown in FIG. 13, the contact surface 14, which is formed aslant on the lower back surface of the rotary swash plate 14, abuts on the rotor 16. Therefore, a further inclination of the rotary swash plate 14 to increase its inclination angle is restrained. Although not shown in the drawing, a further inclination to decrease the inclination angle of the swash plate may be restrained.
Semi-spherical shoes 15a, 15b abut on the outer peripheral parts of the rotary swash plate 14. The outer peripheral surface of these shoes 15a, 15b are engaged with the ball-bearing surfaces of the piston 10. Therefore, a plurality of the pistons 10 are coupled with the rotary swash-plate 14 via the shoes 15a, 15b and are capable of reciprocating in each cylinder bore 9, in which the pistons are mounted.
The rear housing 3 is divided into the suction space 20 and the exhaustion space 21. The suction port 22 and the exhaustion port 23 are formed through the valve sheet 4 and these ports are opened through the respective cylinder bores 9. The compression space formed between the bearing plate 4 and the piston 10 is communicated with the suction space 20 and the exhaustion space 21 via the suction port 22 and the exhaustion port 23, respectively. That is, the compression is carried out only in the single side of the swash plate, i.e., the rear (R) side.
A suction valve is provided in each suction port 22 and opens or shuts the suction port 22 in accordance with the reciprocating movement of the pistons 10. An exhaust valve is provided in each exhaustion port 22 and opens or shuts the exhaustion port 22 in accordance with the reciprocating movement of the pistons 10, while the exhaust valve is restrained by the retainer 24. A control valve (not shown) is provided in the rear housing 3 to adjust the pressure in the crank space 5.
In the compressor as constructed hereinabove, when the rotary swash-plate 14 is rotated along with the driving of the driving shaft 6, each piston 10 is reciprocated via the shoes 15a, 15b in the cylinder bore 9, thereby sucking the cooling-medium gas through the suction port 20 into the compression space, compressing the cooling-medium gas and then exhausting it into the exhaustion space 21. Here, the amount of the cooling-medium gas, which is exhausted into the exhaustion space 21, is controlled by means of adjusting the pressure in the crank space 5.
In addition, the compressor is provided with the mechanisms K, 17 through 19 which enable the exhaustion amount to be adjusted.
With reference to FIG. 14, which shows the essential parts of the above described, single-side compression type swash-plate compressor, the problems of wear in the single-side compression type swash plate compressor are explained.
In the compressing process, the compression reaction-force in the cylinder bore is transmitted via the single-head piston 10 and the shoes 15 to the rotary swash plate 14. The shoe 15a at the side of the compression space is subjected to the compression reaction force, with the result that great sliding resistance is generated between the shoe 15a and the rotary 14. Since such sliding resistance results not only in the power loss but also in the wear of the swash plate, countermeasures against such results become necessary.
Meanwhile, since the shoe 15b at the opposite side of the compression space is also brought into contact with the rotary swash plate 14, sliding resistance generates due to the relative displacement between them. However, the rotary swash plate 14 is not subjected via the shoe 15b to the compressing reaction-force, and the sliding contact between the shoe 15b and the rotary swash-plate 14 occurs only during the suction process, where the single-head piston 10 moves from the top dead center to the bottom dead center. In the suction process, the piston 10 is accompanied by the rotary swash-plate 10 via the shoe 15b, and, the force necessary for accompanying the swash-plate 10 is less than the force required in the compression process. The sliding resistance between the shoe 15b and the rotary swash-plate 14 is accordingly slight.
Since the tin plating applied on an iron-based swash-plate of the single-side compression type swash-plate compressor is soft, a problem that arises is insufficient wear-resistance. Furthermore, although a hard element added to an aluminum alloy enhances wear resistance, a problem that arises is insufficient seizure resistance of the swash plate at the compression-space side.

Swash plate of swash plate compressor and combination of swash plate with shoes