A memory for storing user data includes one or more units. Each unit has one or more pages, each with sufficient storage space for storing both several sectors of user data and related overhead data. The storage space of at least one page per unit is partitioned among user data areas (one per sector) and one or more unit field areas. Each unit field area includes at least one unit field, and the storage space includes fewer of at least one of the unit fields than there are sectors. When unit data are stored in the unit field area, there are fewer instances of at least one unit datum than there are sectors. The storage space also includes one sector field area per sector and one sector data field area per sector, and the size of the storage space is less than the sum of the area sizes times the number of sectors.

The present invention relates to flash memories and, more particularly, to a method of improving the performance of a flash memory in which multiple sectors of data are stored per page.
Flash devices are electrically erasable and programmable read-only memories (EEPROMs) made of flash-type, floating-gate transistors and are non-volatile memories similar in function and performance to EPROM memories, with an additional function that allows an in-circuit, programmable operation to erase portions of the memory. Flash devices have the advantage of being relatively inexpensive and requiring relatively little power as compared to traditional magnetic storage disks. However, flash devices have certain limitations that make using them at the physical address level a bit of a problem. In a flash device, it is not practical to rewrite a previously written area of the memory without a prior erase of the area, i.e. flash cells must be erased (e.g. programmed to "one") before they can be programmed again. Erasing can only be done for relatively large groups of cells usually called "erase blocks" (typically of size 16 to 256 Kbytes in current commercial NAND devices, and of larger size in NOR devices). Therefore updating the contents of a single byte or even of a chunk of 1 kilobytes requires "housekeeping" operations—parts of the erase block that are not updated must first be moved elsewhere so they will be preserved during erasing, and then moved back into place.
Furthermore, some of the blocks of the device are "bad blocks" that are not reliable so that their use should be avoided. Blocks are declared as "bad blocks" either by the manufacturer when initially testing the device or by application software when detecting the failure of the blocks during use of the device in the field.
To overcome these limitations of the background art, a Flash File System (FFS) was disclosed in U.S. Pat. No. 5,404,485 to Ban, which is assigned to the assignee of the present application and which is hereby incorporated by reference as if fully set forth herein. FFS provides a system of data storage and manipulation on flash devices that allows these devices to emulate magnetic disks. In the existing art, applications or operating systems generally interact with the flash storage subsystem not using physical addresses but rather virtual addresses. There is an intermediary layer between the software application and the physical device that provides a mapping from the virtual addresses into the physical addresses. While the software may view the storage system as having a contiguous defect-free medium that can be read or written randomly with no limitations, the physical addressing scheme has "holes" in its address range (due to the bad blocks, for example), and pieces of data that are adjacent to each other in the virtual address range might be greatly separated in the physical address range. The intermediary layer that does the mapping described above may be a software driver running on the same CPU on which the applications run. Alternatively, the intermediary layer may be embedded within a controller that controls the flash device and serves as the interface point for the main CPU of the host computer when the host computer accesses the storage. This is for example the situation in removable memory cards such as secure digital (SD) cards or multimedia cards (MMC), where the card has an on-board controller running a firmware program that, among other functions, implements the type of mapping described above.
Software or firmware implementations doing such address mappings are typically called "flash management systems" or "flash file systems". The latter term is a misnomer, as the implementations do not necessarily support "files", in the sense that files are used in operating systems of personal computers, but rather support block device interfaces similar to those exported by hard disk software drivers. Still, the term is commonly used, and the terms "flash file system" and "flash management system" are used herein interchangeably.
Other prior art systems that implement virtual-to-physical address mapping can be found in U.S. Pat. No. 5,937,425 to Ban and U.S. Pat. No. 6,591,330 to Lasser, both of which are incorporated by reference for all purposes as if fully set forth herein.
In U.S. Pat. No. 5,937,425, which is particularly suitable for NAND-type flash devices, the mapping is done as follows, referring to FIG. 1 (prior art). Physical address space 13 is composed of physical units 111 that are actually the erase blocks i.e. the smallest chunks that can be erased. Each physical unit 111 contains one or more physical pages 113, where a page is the smallest chunk that can be written. A virtual address space 11 is composed of virtual units 121 that have the same size as the physical units. Each virtual unit contains one or more virtual pages 123, having the same size as physical pages 113. When a virtual address is provided by an application, for reading or writing, the virtual unit number to which that address belongs is extracted from the virtual address. There is a mapping that assigns to each virtual unit 121 either one physical unit 111 or a chain of more than one physical unit 111. Then physical page 113 corresponding to requested virtual page 123 within virtual unit 121 is located within the corresponding physical unit(s) 111, using a "local" mapping rule that relates virtual pages 123 to physical pages 113, or using control information stored with physical pages 113.
One of the advantages of the methods disclosed in U.S. Pat. No. 5,937,425 is that as the main mapping is done over units rather than pages, the translation tables are much smaller than they would be otherwise, as there are many fewer units than pages. Another advantage is the write performance improvement that results from being able to assign more than one physical unit 111 to one virtual unit 121.
In order for a flash management system to implement the mapping of virtual to physical addresses, it is necessary to associate and store some control information (also called "overhead data" or "metadata") with the pages and units of the storage system. Even if the flash management system performs its address mappings using translation tables fully kept in RAM, it would still need to store some control information in non-volatile storage, as otherwise the flash management system would not be able to create and initialize its tables when starting up again after a power-down. Therefore all flash management systems write some control fields into the flash memory in addition to the user data stored within the system.
Because of this, all NAND flash devices are manufactured in advance with extra bytes of storage attached to each page. Typically the amount of extra space provided is 16 bytes per 512 bytes of user data space. This "extra area" (or "spare area") forms an integral part of the page and both the extra area and user data can be written together in a single write operation. The extra area is used by most NAND-type flash management systems for storing whatever control information they need to keep and then retrieve, either during regular operation or at power-up.
The information fields stored in the extra area can be classified into several categories. A good example for the use of such different categories can be seen in U.S. Pat. No. 6,684,289 to Gonzalez et al. (see for example FIG. 10). Note that Gonzalez et al. actually discloses an atypical flash management system that separates the storage of user data from the storage of some of the control information associated with it, unlike what was explained above. Still, Gonzalez et al. is a good example for understanding the different categories of control fields.
The categories of control fields are:
(a) Fields associated with the specific contents of a page. By that we mean the field's value changes if the user data changes. The best (and usually the only) example of such a field is an Error Correction Code (ECC) field, storing parity bits that support the correction of errors in the data. We refer to such fields herein as "page data fields" or (see the discussion below about sectors) "sector data fields".
(b) Fields associated with a page, but not with the specific data the page contains. One example for such a field is a flag indicating whether the data in the page were deleted by the user and are no longer valid. Another example is a field identifying a portion of the virtual address to which the page belongs. See for example U.S. Pat. No. 6,678,785 to Lasser, in which the disclosed flash management system associates and stores with each page a field identifying the virtual page number within the virtual unit number to which the page corresponds. We refer to such fields herein as "page fields" or (see the discussion below about sectors) "sector fields".
(c) Fields associated with a complete unit rather than with a single page. One example of such field is a flag indicating whether the unit is currently in use. Another example is a field providing the virtual unit number to which the unit corresponds. Such fields are referred to herein as "unit fields".
The page data fields and page fields are required for each page. However, unit fields need not be stored with each page but only once per unit. Typically flash management systems store the unit fields in the first page of a unit, sometimes duplicating them in another page for improving reliability. Therefore the total amount of space required for control information per page is the sum of the amounts required for the page data fields, the page fields and the unit fields. This is so even though in most cases, in all pages except the first page of the unit, at least the part of the extra area corresponding to the unit fields is not used.
The amount of extra area available for control information is limited. Typically for NAND flash devices having pages of 512 bytes each, the extra area is 16 bytes per page. Flash management systems must work within this constraint. A trade-off of design goals is necessary so as not to exceed the available extra area. For example, a system design may allocate 6 bytes for ECC bits, leaving 10 bytes for supporting its management algorithms. Or a different system design may allocate 8 bytes for ECC bits, providing for a higher number of errors that can be corrected and consequently achieving a better system reliability. But in this case only 8 bytes are left for supporting the management algorithms, and this might result in more complex and possibly less efficient management algorithms.
Even though it would thus seem advantageous to have flash devices with a larger extra area, flash manufacturers do not generally follow this path because a larger extra area means a more expensive device. Extra area bits consume silicon area exactly as user data bits do, and therefore the larger the extra area the larger the consumed silicon area. Therefore minimizing extra area is highly desirable.
Consequently for any given flash management system, each one of the following goals are desirable:
(a) Reduce the amount of extra area bytes that need to be provided per page. This goal applies to the design of new flash devices, in which it is possible to deviate from the 16-bytes value currently used.
(b) For existing devices with an extra area of 16 bytes, provide as much space as possible for ECC so as to allow better reliability, without compromising management algorithms complexity and efficiency by supporting all control fields as in the prior art.
(c) For existing devices with a given extra area of 16 bytes, keep the ECC field the same size and provide room for more control fields for management algorithms so as to achieve less complex and more efficient flash management.
One class of flash management systems to which the current invention is especially applicable is the class of systems managing flash devices having pages larger than 512 bytes. Typical file systems and operating systems handle user data in chunks called "sectors" that are 512-bytes long. This is the unit of data exchanged between the file system and the storage system in practically all personal computers, including those employing Microsoft DOS or Windows operating systems. Until quite recently most NAND flash devices had a page size of 512 bytes, so there was a natural matching between user data sectors and flash device pages. A sector of user data that is provided to the flash management system to be stored, is written into a single page together with its related control fields. The flash management system has 16 bytes of extra area available for those control fields, as explained above.
Recently however many flash devices with a page size of 2 Kbytes have been introduced into the market. Such devices are preferred by flash manufacturers for high capacities because the larger pages consume less silicon area for the same number of storage bits, and also because such devices have better read/write performance as a larger number of bytes is read or written in parallel. Flash management systems have been adapted to be able to manage such devices, herein called "large-page devices". An example of such a flash management system capable of handling large-page devices is disclosed in U.S. Pat. No. 6,760,805 to Lasser, which is incorporated by reference for all purposes as if fully set forth herein.
These prior art flash management systems handle large-page devices by allocating multiple user data sectors to a single flash page. We use as an example large pages that are 2 Kbytes as this size is the most common in commercially available large-page NAND flash devices, but other page sizes are also possible and may also benefit from the methods of the present invention. A page of 2 Kbytes can contain four times 512 bytes, and therefore is assigned to contain four user data sectors. In addition to the user data space, a large page contains an extra area of 64 bytes, 64 being four times the 16 bytes extra area of the small-page devices. This makes each large page have a size of 2112 bytes.
Some terminology clarification is required here. As stated above, in the past, flash memory pages contained 512 bytes of user data, or in other words a single data sector. This caused a one-to-one match between pages and sectors. Therefore, even though strictly speaking fields associated with the user's data should have been called "sector data fields" and "sector fields", they were called above "page data fields" and "page fields". When discussing large-page flash memories the one-to-one correspondence between pages and sectors is no longer valid as a page corresponds to multiple sectors. Therefore the sector-based terminology is the more appropriate. However, in order to be consistent with prior art, we retain the page-based terminology. To summarize, in the present disclosure and in the appended claims:
a. the terms "page data field" and "sector data field" are synonyms and mean a field associated with the specific contents of a sector of data;
b. the terms "page field" and "sector field" are synonyms and mean a field associated with a sector, but not with the specific data the sector contains.
Some prior art systems write the four sectors sequentially into their joint page, each sector data adjacent to its control area. This is shown in FIG. 2, in which the location of the four sectors and their control information within the page is illustrated. Area 210 occupies bytes 0 to 511 and contains user data of the first sector. Area 220 occupies bytes 512 to 527 and contains the control information of the first sector. Area 230 occupies bytes 528 to 1039 and contains user data of the second sector. Area 240 occupies bytes 1040 to 1055 and contains the control information of the second sector. Area 250 occupies bytes 1056 to 1567 and contains user data of the third sector. Area 260 occupies bytes 1568 to 1583 and contains the control information of the third sector. Area 270 occupies bytes 1584 to 2095 and contains user data of the fourth sector. Area 280 occupies bytes 2096 to 2111 and contains the control information of the fourth sector.
Other prior art systems do not put a sector and its related control information adjacent to each other, but group the control information of all four sectors of a page together. This is shown in FIG. 3, which is the equivalent of FIG. 2 for the case of all the page's control fields grouped together. Area 210A is the equivalent of area 210 and occupies bytes 0 to 511. Area 230A is the equivalent of area 230 and occupies bytes 512 to 1023. Area 250A is the equivalent of area 250 and occupies bytes 1024 to 1535. Area 270A is the equivalent of area 270 and occupies bytes 1536 to 2047. Area 220A is the equivalent of area 220 and occupies bytes 2048 to 2063. Area 240A is the equivalent of area 240 and occupies bytes 2064 to 2079. Area 260A is the equivalent of area 260 and occupies bytes 2080 to 2095. Area 280A is the equivalent of area 280 and occupies bytes 2096 to 2111.
The datasheet of Toshiba's large-page flash device TC58NVG1S3BFT00 also implies such an arrangement (see page 33 in the datasheet)—even though it does not explicitly address the question of where to locate control information within the page, the way the partial page programming segments are arranged implies this is what the device designers had in mind.
FIG. 4 shows a typical structure of the control fields stored in areas 220, 220A, 240, 240A, 260, 260A, 280 and 280A. Each control area is 16 bytes long and has room for 6 bytes of page data fields (typically ECC), 8 bytes of unit fields and 2 bytes of page fields. It should be noted, however, that not all fields are actually in use in this arrangement. While ECC bytes and page fields' bytes are used for every sector within the page and every page within the unit, unit fields' bytes are not always used. Assuming no redundant copies of unit fields are kept, typically only the first sector of the first page of a unit makes use of its unit fields' space. For all other sectors, these bytes remain unused in prior art flash management systems.
It is mainly for this type of flash management systems that manage large-page devices that the methods of the present invention are applicable.

Method of storing control information in a large-page flash memory device


When an electrostatic discharge event occurs to a connection pad of a chip, an electrostatic discharge detector layout in a feedback loop is able to detect an induced electrostatic discharge voltage for generating a control signal. A pass transistor can be turned off by the control signal for isolating the induced electrostatic discharge voltage, and the internal circuit of the chip can be protected from being damaged by the induced electrostatic discharge voltage. Furthermore, the designed circuit based on electrostatic discharge isolation technique for protecting the internal circuit of the chip is compatible with programmable circuits, and the connection pad can be furnished with burning signals or logic signals.

1. Field of the Invention
The present invention relates in general to ESD avoiding circuits, and more particularly, to the ESD avoiding circuits based on the ESD detectors in a feedback loop.
2. Description of the Prior Art
Since the complementary metal-oxide semiconductor (CMOS) production technology has advanced well into the deep-submicron and nanometer scale, integrated circuit (IC) performance has risen correspondingly. Nowadays, many integrated circuits are guided into mass production by the CMOS process. Some advanced process technologies for scaling-down device areas within integrated circuits, such as thinner gate-oxide and shallower drain/source, can effectively increase the integration and improve the characteristics of the devices. However, these advanced process technologies also significantly sacrifice the electrostatic discharge (ESD) robustness of the integrated circuit. Therefore, the ESD is more likely to become a bottleneck in the mass production yield rate of integrated circuits.
Please refer to FIG. 1, which is a schematic circuit diagram showing the structure of a prior art ESD protection circuit in an integrated circuit 100. The integrated circuit 100 comprises a connection pad 101, an input resistor 108, an internal circuit 120, a power clamp circuit 130, an input ESD protection circuit 105, and an input inverter 110. The input ESD protection circuit 105 comprises an NMOS transistor 106 and a PMOS transistor 107. The input ESD protection circuit 105 functions to perform an ESD protecting process between the connection pad 101 and a power terminal 190 as well as between the connection pad 101 and a ground terminal 195. The power terminal 190 and the ground terminal 195 can be a power route and a ground route respectively in the integrated circuit 100.
The power clamp circuit 130 functions to perform an ESD protecting process between the power terminal 190 and the ground terminal 195. The input inverter 110 comprises an NMOS transistor 111 and a PMOS transistor 112. The input inverter 110 is coupled between the input resistor 108 and the internal circuit 120. The resistor 108 in conjunction with the MOS capacitors of the MOS transistors 111, 112 functions to act as a resistor-capacitor circuit for providing a further ESD protection. The ESD protection circuit 105 and the power clamp circuit 130 are utilized to protect the internal circuit 120 based on discharging the ESD induced current. That is, when an ESD event occurs to the connection pad 101, the power terminal 190 or the ground terminal 195, the NMOS transistor 106, the PMOS transistor 107 or the power clamp circuit 130 is turned on or activated to efficiently guide any ESD induced current into a bypass path instead of into the internal circuit 120.
However, when the internal circuit 120 comprises a programmable circuit and a burning signal for programming the programmable circuit is furnished via the connection pad 101, the prior art ESD protection circuit of the integrated circuit 100 is not compatible with the programming requirement in that a parasitic diode structured by the junction between the drain and the channel well of the PMOS transistor 107 will clamp the voltage range of the burning signal within the supply voltage Vdd at the power terminal 190.
Please refer to FIG. 2, which is a schematic circuit diagram showing the structure of a prior art ESD protection circuit in an integrated circuit 200 with programmable functionality. It is obvious that the PMOS transistor 107 in FIG. 1 is removed so that the voltage range of the burning signal at the connection pad 101 is allowed to be greater than the supply voltage Vdd. The protection functionality concerning the PMOS transistor 107 is then replaced by the functional operation concerning the parasitic transistor of the NMOS transistor 106 in conjunction with the power clamp circuit 130. Accordingly, both the ESD protection circuits shown in FIG. 1 and FIG. 2 perform an ESD protecting process based on discharging the ESD induced current. However, when the amount of charges being accumulated instantaneously at the connection pad 101 is so great that even the ESD protecting process cannot release the accumulated charges soon enough, the ESD induced current can be furnished to the internal circuit 120, which will cause the internal circuit 120 to be damaged by the ESD induced current.


An apparatus and a method for Direct Current (DC) offset calibration in a signal transmission device of a wireless communication system are provided. The apparatus includes a first DC calibration unit for removing a DC offset from a signal, which is output from a Current-to-Voltage Converter (IVC), by using a first DC calibration value, a Variable Gain Amplifier (VGA) for amplifying the signal output from the IVC, a second DC calibration unit for removing a DC offset from a signal output from the VGA by using a second DC calibration value, a Low Pass Filter (LPF) for filtering the signal output from the VGA, a third DC calibration unit for removing a DC offset from a signal output from the LPF by using a third DC calibration value, and a controller for determining the first DC calibration value, the second DC calibration value and the third DC calibration value.

1. Field of the Invention
The present invention relates to an apparatus and a method for Direct Current (DC) offset calibration in a signal transmission device of a wireless communication system.
2. Description of the Related Art
Generally, in a wireless communication environment, a Complementary Metal-Oxide Semiconductor (CMOS) Radio Frequency Integrated Circuit (RFIC) serves to transmit a baseband modem signal using a radio wave, and serves to deliver a reception signal received through an antenna to a Modulator/Demodulator (MODEM) without distortion.
A 4th generation wireless communication standard, such as Long Term Evolution (LTE) or Mobile WiMax, uses a modulation scheme, such as a 16 Quadrature Amplitude Modulation (16QAM) scheme or a 64QAM scheme, in order to transmit and receive a relatively large amount of data without distortion. The use of this modulation scheme indicates that an Error Vector Magnitude (EVM) performance corresponding to a quality index of a signal transmitted by a signal transmission device must be good.
Major factors which affect EVM performance include the linearity of an output-side circuit, the phase noise of a Local Oscillator (LO) signal, the amount of imbalance of an In-phase/Quadrature (IQ) channel, the amount of LO leakage (for example, a DC offset), etc. Particularly, LO leakage is generated by a DC offset of an analog baseband signal which is input to a mixer, and must be minimized in order to improve the EVM performance. Moreover, if the amount of LO leakage increases, even when a signal reception device demodulates a signal transmitted by the signal transmission device, the EVM performance is degraded.
In order to efficiently operate a wireless communication network, the signal transmission device has a dynamic range of 70 to 80 dB, and 30 to 40 dB within the dynamic range of 70 to 80 dB is determined as a dynamic range of an analog baseband. Accordingly, in order to meet the specifications of LO leakage in the entire range of an output voltage (output power), a DC offset must be removed for each gain step in the analog baseband.
FIG. 1 is a block diagram schematically showing an internal configuration of a signal transmission device in a wireless communication system according to the related art.
Referring to FIG. 1, the signal transmission device may include a Digital-to-Analog Converter (DAC) 111, a Current-to-Voltage Converter (IVC) 113, a Variable Gain Amplifier (VGA) 115, a Low Pass Filter (LPF) 117, a DC calibration unit 119, a mixer 121, a Local Oscillator (LO) 123, and a drive amplifier 125.
The DAC 111, which is typically part of a MODEM, first converts an I (in-phase) signal and a Q (quadrature) signal into an analog signal, and outputs the converted analog signal to the IVC 113. The IVC 113 converts the converted analog baseband signal, which is output from the MODEM, into a voltage signal, and the converted voltage signal to the VGA 115.
The VGA 115 amplifies the signal, which is output from the IVC 113, by a previously-set gain, and a signal from the VGA 115 is output to the LPF 117. At this time, the DC calibration unit 119 first removes a DC offset from the signal, which is output from the VGA 115, by using a DC calibration value determined according to the control of the controller, and outputs a signal, which is obtained by removing the DC offset, to the LPF 117. The LPF 117 filters a signal obtained after the DC calibration unit 119 removes the DC offset in such a manner as to limit a bandwidth of the signal to a previously-set bandwidth, and outputs the filtered signal to the mixer 121.
The mixer 121 mixes the signal, which is obtained after the DC calibration unit 119 removes the DC offset, with a signal, which is output from the LO 123, and outputs a mixed signal to the drive amplifier 125. The drive amplifier 125 amplifies the signal, which is output from the mixer 121, by a previously-set gain, and outputs an amplified signal.
As described above, a DC calibration value used by the typical DC calibration unit 119 is a value used to remove a DC offset in the entire analog baseband with respect to a particular gain. Accordingly, when gains used by the VGA 115 and the LPF 117 change, a DC offset is again generated.
Therefore, a need exists for an apparatus and method for DC offset calibration in a signal transmission device of a wireless communication system.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present invention.

Apparatus and method for DC offset calibration in signal transmission device


The construction of Static Single Assignment form (SSA) is used as a dynamic conflict graph so that while constructing SSA in linear time, the program being analyzed is simultaneously register allocated. When allocating a register for the symbol, the conflict set is examined so that the register chosen for the symbol is not used by a symbol in the conflict set. When a symbol is register-allocated, the symbol is added to all the conflict set of all live symbols. A live symbol is determined by keeping two counters, called herein a use counter and a use threshold counter. Both counters are initialized when a definition of a symbol is encountered in a block. Both counters are incremented when a use of the symbol is encountered when traversing a block in a depth-first downward traversal. The use count is decremented when a use is detected when traversing the block in an upward traversal. A symbol is live when the use count is less than the use count threshold and the use count is greater than zero when a register is allocated. The register-allocated symbol is added to the conflict set of all live symbols.

Register allocation is a classic problem in computer science. The assignment of registers to variables is difficult and typically takes a long time because there are a limited number of (very fast access) registers. Variables can be stored in (much slower) memory instead of in registers, but doing so typically adversely affects run-time performance of the program. Hence optimal register allocation is considered a very difficult computer science problem and can take a very long time.
For example, assume that a computer has two registers and a user writes a program using three variables, a, b, and c. Suppose the lifetimes of variables a and c do not overlap, that is, the lifetime for a has no instructions in common with the lifetime for c. Suppose that the lifetime of b overlaps the lifetimes of both a and c. It is clear that b cannot be assigned the same register assigned to either a or c but that a and c can be assigned the same register because a and c do not conflict.
Hence, it is clear that the concept of the lifetime of variables are important when allocating registers in an efficient way. Registers can be allocated to variable lifetimes by: (1) building a conflict graph which identifies which variables cannot be assigned to the same register simultaneously; (2) assigning registers to variables until the registers are used up; (3) splitting the lifetime of some of the variables by "spilling" the contents of the registers into main memory so that registers can continue to be assigned to variables; and (4) returning to step (2). The process of assigning registers to variables is called register coloring.
Another problem encountered in an optimizing compiler is acquiring information about the structure and nature of the program. This problem has been addressed by associating every use of a variable in a program with a single unique definition for the variable by constructing a Static Single Assignment (SSA) form of the program. When a program has been put in SSA form, each use of a variable in the program will have a pointer associated with it that points to the single unique definition of the variable. These pointers are typically "use-def links" or "use-def edges."
For example, given the following simple program, Program 1:
x=
y=
z=x+y
z=z+x
the SSA form might be represented as illustrated in FIG. 1.
When more than one definition for a given variable exists, phi functions are inserted. For example, suppose the following simple program, Program 2 exists:
If (some conditional C)
{
then x=
}
else
{
x=
}
=x
endif
This program can be represented in flowgraph form, Flowgraph 1, as shown in FIG. 2.
In Flowgraph 1, block 1 represents whatever code preceded the If statement. As a result of the If statement, control will branch to either block 2 or block 3. In block 2 there is a definition of x (x=?) and in block 3 there is a definition of x (x=?). As the program is written, then, we cannot draw in an edge from the use of X in block 4 (=x) to its "single unique definition". To overcome this problem, a phi function: x3=σ(x,x) is inserted in block 4. X (in block 2) is renamed x1 and x (in block 3) is renamed x2 In this way every x has associated with it just one definition. It will be seen that there are as many inputs to a phi function as there are control flow edges that allow entrance into a block. In this case because there are two pathways to enter block 4 (via block 2 or via block 3), so there are two inputs to the phi function. The end result (Flowgraph 2)_showing the control flow edges as well as the use-def edges is shown in FIG. 3.
A dominance frontier is a property of a block in a flowgraph. For example, consider the following simple program, represented in flowgraph form in Flowgraph 3 shown in FIG. 4.
A block (e.g., block 1) is said to dominate another block (e.g., block 2) if and only if all possible paths from the entry block (e.g., block 0) to block 2 include block 1. Here you used to have the "preceding block" which was correct in this case but only because of the coincidence that the predecessor block was the entry block. In Flowgraph 3, block 1 dominates blocks 2, 3 and 4. By definition, a block also dominates itself. A block (e.g., block 1) is said to strictly dominate another block (e.g., block 2) if and only if block 1 dominates block 2 and block 1 is not block 2. Predecessors of a block are all the blocks that have edges going to it. For example, in the above diagram, block 4's predecessors are blocks 2 and 3, and block 1's predecessor is block 0 and so on. A dominance frontier of a block B (denoted df(B)) is the set of all blocks (b) such that B dominates a predecessor of b, and B does not strictly dominate b., or:
df (B)={b:B dom pred (b) & B does not strictly dom b}.
In Flowgraph 3, block 4 is a member of the dominance frontier of block 3. In this case B=block 3 and b=block 4. Block 3 is a predecessor of block 4 and block 3 dominates itself (by definition) so block 3 dominates a predecessor of 4. Block 3 does not strictly dominate block 4 because block 4 can be reached by going through block 2 (thereby circumventing block 3) therefore block 4 is a member of the dominance frontier of 3.
Dominance frontiers are useful to indicate where phi functions should be inserted. For example, if there were a definition (e.g., x=) in a block (e.g., block 3) in Flowgraph 3, a phi function (e.g., x=σ(x,x)) should be placed in the blocks associated with the dominance frontier of block 3 (e.g., a phi function x=σ(x,x) should be placed in block 4). Flowgraph 4, shown in FIG. 5, illustrates Flowgraph 3 with the addition of definitions of x and the inserted phi function.
To construct the SSA form, first the dominance frontier is constructed for all the blocks (referred to as generating an iterated dominance frontier). Then by inspection from the location of all the definitions, the phi functions are placed. Finally, the control flowgraph edges are added. To accomplish this, the flowgraph is traversed in a depth-first order, as illustrated in FIG. 6.
To traverse Flowgraph 5 in depth-first order, first block 0 is traversed, and then block 0's descendant, block 1, is traversed. Block 1 has two descendants, block 2 and block 5. One of the descendants is randomly selected (e.g., block 2), one of block 2's descendants is randomly selected (e.g., block 3), one of block 3's descendants is randomly selected (e.g., block 4). At this point there are no more descendants so traversal continues at the predecessor block (e.g., block 3), but there are no more unvisited descendants. Traversal continues at block 3's predecessor, so block 2 is traversed, but there are no more unvisited descendants. Traversal continues at block 2's predecessor (e.g., block 1). Block 1 had another predecessor (e.g. block 5) which has not been traversed yet. Block 5 is traversed. Block 5 has no unvisited descendants so the traversal continues to block 1. Block 1 has no unvisited descendants, so traversal continues to block 0. During this traversal, whenever a definition of a variable is encountered, the variable is pushed onto a renaming stack associated with that variable. When block 1 is traversed, a definition is found (labeled x1) and is placed onto a renaming stack (currently empty). Block 2 has no definitions, but has a use (=x). By definition, the use is the current top of the stack so an edge is added (e.g., edge a). Block 3 contains another definition of x (a phi function, labeled x2). Because block 3 contains a phi function, and only one definition of x (x1) has been encountered so far, the first phi function parameter is wired up to the x in block 1 (edge b). The phi function is labeled x2 and is placed onto the renaming stack. Block 4 contains neither a definition nor a use. Traversal proceeds upwards to block 1 and then down to block 5. In block 5 a new definition is encountered (e.g., X3), which is pushed on the stack. Also in block 5 a use (=x) is found and is wired up (edge c) to the definition of x on the top of the stack (x3). Upon returning to block 3, the second x in the phi function is wired up to x3 (edge d).
Hence, SSA construction is typically broken down into the following sequence of steps: first an Iterated Dominance Frontier (IDF) is constructed; then the IDF is used to inject phi-functions where necessary into the instruction stream; and finally, the variables in the program are renamed with an array of renaming stacks while a pre-order depth-first recursive walk of the flow graph is performed. Because each block is processed once, the amount of work performed is a function of the number of blocks, so that SSA construction takes place in linear time.
In traditional compilers, the time expended to transform user code into machine code is not critical. Typically, it is more important to emit the best possible resultant code (e.g., making the resultant code run 10% faster) than to emit the code as fast as possible. In the world of just-in-time (JIT) compilers, in the JAVA run-time world, in IBM's run-time world, in the .NET run-time world and so on, however, compilation occurs while a user is running an application or program, hence trade-offs have to be made between the amount of time spent performing analysis and optimization and the expected improvement in run-time performance of the transformation. It would be helpful if multiple phases of compilation, such as register allocation and SSA construction, could be combined into a single phase without adding complexity so that optimally, more could be accomplished in less time, thus enabling both an increase in analysis/optimization throughput and run-time performance.

System and method for register allocation using SSA construction


A vehicle airbag assembly, method of deployment and manufacture. The airbag assembly includes at least one inflatable portion and at least one non-inflatable portion. At least one mass is operably attached to the non-inflatable portion. Upon inflation of the inflatable portion, the mass provides a substantial tautness to the non-inflatable portion. The deployment method includes providing at least one inflatable portion and at least one non-inflatable portion. The airbag assembly is operably attached to the vehicle. A mass operably attached to the non-inflatable portion is provided. The inflatable portion is inflated. The non-inflatable portion of the airbag is extended substantially taut upon inflation of the inflatable portion with the mass. The manufacturing method includes forming at least one inflatable portion and at least one non-inflatable portion. At least one mass is operably attached to the non-inflatable portion. The mass is adapted to provide a substantial tautness to the non-inflatable portion during airbag assembly deployment.

There have been many proposals concerning airbag arrangements to be utilized in motor vehicles, such as automobiles. In particular, it has been proposed to provide an airbag arrangement in the form of an inflatable curtain that, when inflated, is located adjacent a driver or occupant of a vehicle, being positioned between the driver or occupant of the vehicle and an adjacent side door or window opening.
Typically, an inflatable curtain of this type is initially stored within a housing or recess that follows a non-linear path across the top of the doorframe of the motor vehicle. The forward end of the recess or housing may extend down an "A"-Post of the motor vehicle, and the rear end of the recess or housing may extend partly down a "C"-Post or a post located to the rear of the "C"-Post. These opposing ends are centered by a "B"-Post.
When the airbag within the housing or recess is inflated, the airbag forms a curtain extending parallel with the longitudinal axis of the vehicle. The curtain is substantially vertical and extends from the roof line, above the door or window opening, to a position located at the lower edge of the window opening or substantially in alignment with the center of the chest of the driver or occupant of the vehicle.
Various attempts have been made to develop a side curtain that can be fabricated in such a way that when it is deployed, the lower-most region of the curtain extends fully downwardly. Many side curtain airbags designs include inflatable "A"-Post and "C"-Post portions flanking a mostly non-inflatable "B"-Post portion. When the airbag is deployed, the inflation pressure augments deployment of the "A" and "C"-Post portions (i.e. by projecting the airbag in the downward direction) but not the "B"-Post portion.

Vehicle airbag assembly, method of deployment and manufacture


A method is intended for scheduling reservations of resources in a packet-switched communication network comprising end-nodes (H1-H3) and core network switches (S1-S2). This method comprises the steps of:                including a time information to each request, issued by an end-node (H1) and forwarded by at least one core network switch (S1), and requesting a resource reservation for receiving a stream defined by specifications at a time which is represented by this time information, and        storing the time information, which is included into each forwarded end-node request in correspondence with the associated stream specifications, into at least one related database managed by a core network switch (S1) which participates to the request forwarding.

Emerging standardization efforts, as in the IEEE organization, allow really considering strict resource reservation implementation at OSI level 2 (Link Layer). However, all these new mechanisms are not time correlated and thus do not allow to indicate the end-time of a current reservation or to schedule a future reservation.
In the present document the term "resource" relates to all network variables, such as bandwidth, jitter and latency, for instance, which characterize a data flow (or stream) between two nodes through a given infrastructure.
Some environments, such as professional video production and broadcast environments, are very time sensitive environment. So, it has been proposed to replace the point-to-point infrastructure they currently used with a packet switched network. But, this imposes to take care of about all latencies which could impact the overall system performances.
The well known OSI model (schematically illustrated in FIG. 1 and standardized by the ISO organization) defines a networking framework for implementing communication means in seven layers. Layers 1 to 4 are in charge of the transport of the data over a given communication medium, while layers 5 to 7 are used to allow different applications to communicate independently of the communication infrastructure used.
The present invention only concerns the OSI layer 2, i.e. the data link layer. So, all mechanisms described hereafter are handled at the OSI layer 2.
As it is known by the man skilled in the art, core network switches are core network equipments that forward traffic on information contained in the layer-2 header. This "forwarding" differs from "routing" which concerns operations on layer-3 information.
These core network switches only forward traffic to the addressees by using a forwarding table that associates a hardware address to one of their ports. When a frame is received by a core network switch, its layer-2 header gives the hardware address and thus an associated entry in the forwarding table, which designates the port to which the core network switch must forward the frame. Because they operate at a low level, network switches' processes are implemented in hardware, allowing mastering their latencies.
The IEEE 802.1 Audio/Video Bridging (AVB) Task Group (TG), which is part of IEEE 802.1, aims at providing specifications that will allow time-synchronized low latency streaming services through 802 networks. This TG comprises a sub-group "IEEE 802.1AS: Timing and Synchronization" which aims at defining through a standard Layer 2 time synchronizing service that is appropriate for the most stringent requirements of consumer electronics applications.
The 802.1AS standard specifies the protocol and procedures that must be used to ensure that the synchronization requirements are met for time sensitive applications, such as audio and video, across Bridged and Virtual Bridged Local Area Networks consisting of LAN media where the transmission delays are fixed and symmetrical, such as IEEE 802.3 full duplex links, for instance. This includes the maintenance of synchronized time during normal operation and following addition, removal or failure of network components and network reconfiguration. This 802.1AS standard specifies the use of IEEE 1588 specifications where applicable in the context of IEEE 802.1D and 802.1Q standards. Synchronization to an externally provided timing signal (e.g. a recognized timing standard such as UTC or TAI) is not part of this standard but is not precluded.
IEEE 802.1AVB task group comprises two other sub groups 802.1 Qat and 802.1 Qav concerning new resource reservation mechanism.
The 802.1Qat standard aims at defining an admission control system that allows bridges to guarantee the resources needed for Audio/Video (AV) streams. It specifies protocols, procedures and managed objects, usable by existing higher layer mechanisms, which allow network resources to be reserved for specific traffic streams traversing a bridged local area network. It identifies traffic streams to a level sufficient for switches to determine the required resources and provides a mechanism for dynamic maintenance of those resources.
This standard provides a signaling protocol to enable the end-to-end management of resource reservation for QoS guaranteed streams. The signaling protocol facilitates the registration, deregistration, and retention of resource reservation information in relevant network elements. The signaling protocol is an essential component for automatic configuration in bridged local area network applications that require latency and bandwidth guarantees. The application of current IEEE 802 technologies for high quality time sensitive streaming allows users to increase the load of their networks unknowingly to the extent that the user experience is negatively impacted. To provide the robust guaranteed QoS capability for streaming applications, the availability of network resources along the entire data path must be insured before transmission takes place. This requires the definition of traffic stream descriptors and a protocol to signal the resource reservation along the end-to-end path of streams. Multiple registration protocol (MRP) is used as a basis for this protocol.
The 802.1Qav standard aims at enhancing standard 802.1 bridge frame forwarding rules to support AV streams. It allows switches to provide guarantees for time-sensitive (i.e. bounded latency and delivery variation), loss-sensitive real-time audio video data transmission (AV traffic). It specifies per priority ingress metering, priority regeneration and timing-aware queue draining algorithms. Virtual Local Area Network (VLAN) tag encoded priority values are allocated, in aggregate, to segregate frames among controlled and non-controlled queues, allowing simultaneous support for both AV traffic and other bridged traffic over and between wired and wireless Local Area Networks (WLANs). This standard specifies enhancements to forward function of the above mentioned network switches (which are increasingly used to interconnect devices that support audio and video streaming applications) to provide performance guarantees allowing time-sensitive traffic in a local area network and harmonize delay, jitter and packet loss for Layer-2 networks.
The above mentioned new ongoing standardization efforts allow accurate synchronization connected network elements (end-node and core network equipment) and ensuring a strict resource reservation. Nevertheless, even if they aim at supporting time sensitive applications, they are not fully related because the resource reservation can not be scheduled according to the "wall" clock shared by any synchronized equipment.

This patent is subject to a terminal disclaimer.

Time synchronized resource reservation over packet switched networks


A display panel includes: an active area; a peripheral area; a solder pad area at a side of the peripheral area away from the active area; a first source-drain electrode layer, a passivation layer and a second source-drain electrode layer and a dielectric layer stacked on a back plate in the peripheral area; a touch electrode in the active area; a touch electrode line connected to the touch electrode. The touch electrode line extends from the active area to the peripheral area, and is connected to the solder pad area through the second source-drain electrode layer in the peripheral area. The touch electrode line is connected to the second source-drain electrode layer through a first through hole in the dielectric layer. A portion of a surface of the second source-drain electrode layer, which is away from the passivation layer and exposed through the first through hole, is a flat surface.

An Active Matrix/Organic Light Emitting Diode (AMOLED) relates to a display panel technology based on Organic Light Emitting Diodes (OLEDs). Compared with a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) technology, the AMOLED has characteristics of faster response speed, higher contrast, wider viewing angle, and low power consumption.
Currently, there are more and more touch display products on the market. In a Flexible Multiple Layer On Cell (FMLOC) product, a touch function is directly integrated on a display panel, which is conducive to lightness and thinness of a whole machine. In order to achieve a narrow frame of a product, it is a popular technology to set a solder pad area of the display panel on a back of an active area and connect them through a bent wiring. When the FMLOC is integrated on such product, a touch electrode line needs to be connected through a source/drain electrode layer in a peripheral area. In the foregoing display panel structure in the related art, the touch electrode line is easily broken when the wiring is bent, which seriously affects a yield of touch display products.

Display panel and method for manufacturing the same, and display device

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.


A new locking T-nut for securely fastening a threaded element, such as a threaded bolt, to a structure. The inventive device includes a cylindrical nut body with a threaded bore extending therethough. Within the bore, at least one resilient locking ring is mounted within an annular groove provided on the inner surface of the bore. A radial flange radially extends from the one end of the nut body and includes at least one securing tooth extending therefrom towards the other end of the nut body.

1. Field of the Invention
The present invention relates to lock nuts and more particularly pertains to a new locking T-nut for securely fastening a threaded element, such as a threaded bolt, to a structure.
2. Description of the Prior Art
The use of lock nuts is known in the prior art. More specifically, lock nuts heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art lock nuts include U.S. Pat. Nos. 4,004,626; 5,391,003; 4,126,170; 4,019,550; 4,993,902; and 3,952,785.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new locking T-nut. The inventive device includes a cylindrical nut body with a threaded bore extending therethough. Within the bore, at least one resilient locking ring is mounted within an annular groove provided on the inner surface of the bore. A radial flange radially extends from the one end of the nut body and includes at least one securing tooth extending therefrom towards the other end of the nut body.
In these respects, the locking T-nut according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of securely fastening a threaded element, such as a threaded bolt, to a structure.


A reaction force actuator 3 for giving reaction force to a steering wheel 2 disengaged from a steering mechanism 1 is provided. A steering control unit 4 is provided to control so that the reaction force decided in accordance with the detected results of the running speed by a vehicle speed sensor 6 and the detected results of a road surface condition by a current sensor 7a, an open air temperature sensor 7b, a wiper switch 7c and a supersonic wave sensor 7d. Also, the steering motor 5 for applying the steering force to the steering mechanism 1 is operated smaller at higher speed and larger at slower speed at running by the operation of the steering control unit 4 in accordance with the detected results of the running speed by the vehicle speed sensor 6. Therefore, the same steering feelings as those of the coupling type steering system are obtained to realize a steering system enabling the reliable steering operation to effect under the various different running conditions. Also, the bother of the steering operation at the slow speed or at the stop time is dissolved by simple construction.

1. Field of the Invention
The present invention relates generally to a steering system for causing an automobile to steer in accordance with the operation of a driver.
2. Description of the Related Art
The steering of the automobile is realized by transmitting the operation of steering operating means, for example, the rotation of the steering wheel arranged within the cabin to a steering mechanism which is disposed externally the cabin and operates the wheels for steering use (generally the front wheels).
Various types such as ball screw type, rack and pinion type or the like are put into practical use as an steering mechanism for the automobile. For example, a rack and pinion type steering mechanism, which is adapted to transmit through tie rods to knuckle arms provided on the front right and left wheels, the sliding movement along the length direction of the rack shaft extended in the right and left directions in the front portion of the automobile body, interlocks with the pinion engaged with the tip end of the rotation shaft (steering column) of the steering wheel extended out of the cabin with the rack teeth formed halfway in the rack shaft. Such steering mechanism converts the rotation of the steering wheels into the sliding, in the length direction, of the rack shaft to effect the steering operation in accordance with the rotating operation of the steering wheels.
Also, in recent years, in order to reduce steering burden of the driver, a power steering system is put into wider use. The powder steering system has an actuator for steering auxiliary use such as hydraulic cylinder, electric motor or the like halfway provided in the steering mechanism. The operation of the steering mechanism in accordance with the rotation of the steering wheel is assisted by the driving operation of the actuator in accordance with the detected results of the operating force applied to the steering wheel for steering operation.
But such a conventional steering system as described above has problems such as the mechanical coupling between the steering wheel as the steering operating means and the steering mechanism as the steering means is required in spite of whether or not it is constructed as a power steering system, and the arrangement position of the steering wheel within the cabin is restricted in a position at which coupling with the steering mechanism outside of the cabin can be realized. Also, complicated coupling construction is required for realizing the coupling therebetween even if the steering wheel is arranged in a position at which coupling with respect to the steering mechanism can be realized, thus resulting in factors interfering with light weight automobile, simpler assembling steps.
A steering system for automobiles designed to solve such problems is disclosed in Japanese Utility Model Publication No. 2-29017 (1990). In the steering system, the steering wheel is disengaged from the steering mechanism, and also, an electric motor is arranged as an actuator for steering use halfway in the steering mechanism as same in the actuator for assisting steering of the power steering system. The electric motor is driven in accordance with the detected results of the operating direction and operation amount of the steering wheel to effect the steering operation in accordance with the operation of the steering wheel.
The steering wheel disengaged from the steering mechanism has a reaction force actuator having a electric motor and a gear mechanism. The reaction force actuator applies the reaction force, which becomes larger or smaller in accordance with the vehicle speed and the steering angle, to the steering wheel by driving of the electric motor in accordance with the detected results of the vehicle speed and the steering angle. The steering operation is adapted to be effected with the same feelings as those of the general steering system (coupling type steering system) mechanically coupled between the steering wheel and the steering mechanism by increasing or decreasing the motor current of the electric motor for steering use in accordance with the detected results, namely, by increasing or decreasing the steering force generated by the electric motor on the basis of the detection result of the operation force to be applied to the steering wheel against the reaction force.
The conventional separation type steering system constructed above has following advantages. The steering system is useful for the development of the automobile technique in the future, as realization of the new steering means, such as a lever, a pedal, a joy stick and so on, replacing the conventional steering wheel, and realization of the automatic driving system following the driving information such as detection of the guiding marks on the road surface, reception of the information from satellites or the like, in addition to the above described objects such as increase of flexibility of the arrangement of the steering wheel, light weight automobile or the like. However, above conventional separation type steering system has following problems.
The operation force to be applied to the steering wheel for steering operation is necessary for changing the direction of the wheels for steering use against the reaction force from the road surface, and is known to become usually larger accompanied by the reduction in the vehicle speed, also larger accompanied by the increase in the steering angle. Accordingly, it is natural to feel lighter at the smaller steering operation at higher speed running of the steering wheel by a driver, and conversely, heavier at the larger steering operation at lower speed running by the direction action of such reaction force as described above in the case of the operation of the steering wheel in the general coupling type steering system.
On the other hand, in the separation type steering system disclosed in the above described Japanese Utility Model Publication No. 2-29017 (1990), the reaction force actuator provided on the steering wheel is adapted to apply the reaction force which becomes larger or smaller in accordance with one or both of the higher and lower vehicle speeds and the larger or smaller steering angles. But such a reaction force applying way does not correspond to the conventional general coupling type steering system. Therefore, unnatural operation feelings are given to the driver. The same steering operation as in the general steering system is not realized because of the generated force of the electric motor for steering use to be driven in accordance with the operation of the steering wheel against the reaction force.
Further, the reaction force from the road surface which is applied to the wheel for steering use does not increase or decrease simply by the vehicle speed and the steering angle. For example, even under the same conditions in the vehicle speed and the steering angle, the reaction force acting upon the wheel at running on the snow road becomes smaller than at running on the paved road, and reversibly, the reaction force acting upon the wheels at running on the gravel road becomes larger than at running operation on the paved road. In the separation type steering system disposed in the above described Japanese Utility Model Publication No. 2-29017 (1990), the same reaction force as that at running on the paved road is applied to the steering wheel even at running on the snow road or the gravel road. The steering wheel is effected against the reaction force so that there is a possibility of effecting an excessive steering operation by the driver at running on the snow road, thus causing slipping accidents to happen. Also, reversibly the driver may effect the excessively small steering operation at running on the gravel road so that the curve may not be turned by the driver.
On the other hand, there are request that the driver desires to reduce the operation force at steering and also, to reduce the operation amount to solve the bother of the steering operation when complicated steering operations onto both the right and left sides are necessary for the large reaction force in such a running condition at an extremely slow speed or at a substantially stop condition as garaging the automobile, bringing the automobile near to crosswise direction or the like. To meet such request, Japanese Patent Application Laid-Open No. 62-120272 (1987), Japanese Patent Application Laid-Open No. 63-291770 (1988) disclose that a change speed mechanism is arranged halfway in the steering column with the coupling type steering system as an object, and the operation amount of the steering mechanism with respect to the operating amount of the steering wheel is adapted to change to become larger at running in low speed or at stop time than at running in operation at the high speed by changes in the speed change ratio of the speed change mechanism in accordance with the detected results of the vehicle speed.
In such construction, heavy and massive components such as actuator or the like for speed changing are required for the speed change mechanism. Thus, it is difficult in reality to provide such speed change mechanism as described above halfway in the steering coelum. Even if the components are possible to arrange, it is unsuitable to go against the light weight automobile.

Automobile steering system including reaction feedback to operator


A method for storing a data block, including storing the data block in a storage pool, obtaining a data block location, calculating a secure data block checksum for the data block, and storing a first indirect block in the storage pool, wherein the first indirect block comprises the data block location and the secure data block checksum.

A typical operating system includes a file system. The file system provides a mechanism for the storage and retrieval of files and a hierarchical directory structure for the naming of multiple files. More specifically, the file system stores information provided by the user (i.e., data) and information describing the characteristics of the data (i.e., metadata). The file system also provides extensive programming interfaces to enable the creation and deletion of files, reading and writing of files, performing seeks within a file, creating and deleting directories, managing directory contents, etc. In addition, the file system also provides management interfaces to create and delete file systems. File systems are typically controlled and restricted by operating system parameters. For example, most operating systems limit the maximum number of file names that can be handled within their file system. Some operating systems also limit the size of files that can be managed under a file system.
An application, which may reside on the local system (i.e., computer) or may be located on a remote system, uses files as an abstraction to address data. Conventionally, this data is stored on a storage device, such as a disk.
To access a file, the operating system (via the file system), typically provides file manipulation interfaces to open, close, read, and write the data within each file. More specifically, the file system stores data on the storage device by managing the allocation of space within the storage device. Typically, the volume manager provides space which is managed by the file system. Two common types of file system space allocation strategies are known as block-based allocation and extent-based allocation. Block-based allocation creates incremental disk space for each file each time the file is extended (i.e., modified via a write request to add information), whereas extent-based allocation creates a large series of contiguous blocks (i.e., extents) each time the file exhausts the space available in the file's last extent.
When allocating space, both block-based and extent-based allocations use space provided by the volume manager. The volume manager allows multiple physical disks to be used as a single volume (i.e., a virtual disk) to provide larger consolidated storage sizes and simpler management. The volume manager allows users to organize data along volume boundaries (i.e., each volume has physical disk space allocated to the volume such that the volume is tied only to that dedicated physical disk). The volume manager is typically implemented as a separate layer between the physical disks and the file system, and is presented to the user as a virtual disk device. In other words, volume managers organize the collections of physical devices (e.g., disks) into virtual devices. Additionally, the space allocated within the volume manager is handled by the file system. Consequently, the volume manager is not aware of which blocks within the available storage space are in use and which blocks are free for data to be stored.
Further, file systems may be mounted on the virtual disk devices. Thus, physical disks are partitioned and allocated to multiple virtual disk devices, and each virtual disk device is capable of having a file system that exclusively uses that particular virtual disk device. A request to access a file is typically performed by an application, via the file system, using a file name and logical offset. This file name and logical offset (i.e., the manner in which applications express file operation requests) corresponds to a location within the virtual disk device. Subsequently, the request is translated to physical disk space on the storage device by the volume manager, allowing the user of the application to access the data within a particular file.

Method and apparatus for identifying tampering of data in a file system


An inkjet printing head including: a common ink chamber having an outlet; and an individual ink flow path having a pressure chamber and leads ink from the outlet of the common ink chamber to a nozzle through the pressure chamber, wherein the common ink chamber and the individual ink flow path are formed of a plurality of thin plate members having holes formed thereon, the thin plate members being laminated and fixed onto one another by metal-metal junction, and wherein sectional area of the common ink chamber along a planar direction of the thin plate members is configured to be smaller at an end portion where the outlet is provided than at a central portion in a direction of thickness of the plurality of thin plate members.

1. Field of the Invention
The present invention relates to an inkjet printing head for ejecting ink onto a recording medium to thereby perform printing.
2. Description of the Related Art
An inkjet printer includes at least one inkjet printing head having nozzles disposed therein so that ink can be ejected from the nozzles to apply printing onto a printing medium. In such an inkjet printing head, it is necessary to form complex and accurate ink flow paths in the inside of the inkjet printing head. Therefore, the inkjet printing head is formed by lamination of thin plate-like etching plates. To laminate and bond the etching plates on one another surely, for example, use of an adhesive agent such as an epoxy adhesive agent, a polyimide adhesive agent or an acrylic adhesive agent may be thought of. However, when the amount of the adhesive agent applied is large, the adhesive agent may flow into ink flow paths formed in the inside of the inkjet printing head. As a result, there is a possibility that the ink flow paths will be narrowed or blocked with the adhesive agent. Therefore, an inkjet printing head produced in such a manner that thin plate-like etching plates are laminated and bonded onto one another by diffusion junction which is one method of metal-metal junction has been proposed (e.g., see JP-A-UM-58-147749 (1983)). According to this technique, the thin plate-like etching plates can be bonded to one another with strong bonding force while the ink flow paths can be prevented from being narrowed or blocked because the adhesive agent is not used so that a surplus of the adhesive agent does not flow into the ink flow paths.


A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus.

Example embodiments relate to a host device, and more particularly, to a host device using a shared bus and a system including the host device.
Recently, as use of a large amount of contents, e.g., a moving picture, has become widespread, there is a growing need to increase the capacities of storage devices. Also, advancement in wired/wireless communication technology and cloud computing technology has triggered a need to increase the operating speeds of storage devices. As described above, much attention has been paid to importance of an increase in the capacities and operating speeds of storage devices capable of performing a write/read operation through a data communication with a host device.

Host device and system including the same


Described herein are techniques related to devices with wireless docking capabilities and more particularly near field communications-based techniques for docking and undocking devices. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Docking stations often have one or more persistent clients docked thereto. When the docking station operates wirelessly, as is increasingly the case, undocking and/or evicting an incumbent client and connecting another client involves many cumbersome steps often involving access to and use of the user interfaces (UIs) of the clients. For instance, some steps must occur on one client UI and other steps must occur on the other client's UI. The process often confuses the user leading to user frustration and failed docking attempts. Moreover, the UI of one or more of the clients (often the incumbent client) might not be readily accessible to the user who wishes to dock a client to the docking station.
The Detailed Description references the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components.

Near field communications-triggering for wireless display/docking


A method of fabricating the parallel leading wire in a focusing mesh of field emission display and a structure thereof is provided. A cathode leading wire is formed along one edge of a cathode plate in a field emission display. When the metal mesh is formed on the cathode plate, one edge of the mesh becomes a leading wire parallel to another edge thereof. The leading wire has a designated length and a thickness thinner than the metal mesh. Without applying external force, the parallel leading wire is drooped and contacted the cathode plate because of itself weight. Be way of sintering, parallel leading wire is connected to cathode leading wire and enveloped by the metal mesh within the cathode plate.

The present invention provides a method of fabricating a parallel leading wire in a focusing mesh of a field emission display and the structure thereof. In particular, it provides a method to fabricate a leading wire connected the metal mesh and the cathode plate in a field emission display. It not only makes the leading wire hard to break apart, but also easy to be enveloped. In addition, the method provided will not exceed the budget, affect the integral structure, and/or occur a short or break circuit. Furthermore, the method will not influence the installment of valid and invalid areas in a system and further simplify the usage of the invalid area.
It is known that the structure of the current field emission displays can be divided as 2, 3 and 4 pole types. The structure of 3 and 4 pole field emission displays both have metal mesh. When applying a controlled voltage to the metal mesh, the electron beams from the cathode plate successfully pass the metal mesh and reflect to the anode plate to display the images. Owing to the material difference with glass colloid, the cathode and anode plates, the metal mesh extends outside of the element and to be deemed as a leading wire. However, the foregoing method cannot provide the structure to be airtight enough, and thereby cause the insufficient vacuum and even sometimes happen air leakage.
In order to overcome the depicted defeats, a metal mesh is entirely enveloped within the cathode and anode plates, and additionally fabricates a leading wire extended outside of the element. Nevertheless, this method has some drawbacks as following:
1. Referring to FIGS. 1 and 2, a three-dimensional leading wire 5 is built between the metal mesh 3 and the cathode plate 4. Printing another leading wire 6 in the cathode plate 4 to extend outside of the element and then reach the purpose of vertical wire joint. Yet, the defeat is the complex process of fabricating and thus results the three-dimensional leading wire 5 easy to occur a short circuit.
2. Referring to FIG. 3, printing a silver colloid leading wire 7 between the metal mesh 3 and the cathode plate 4. However, it only can be used under the between distance is within a designated range. When the distance is beyond the range, the extensibility of silver colloid will exceed itself material allowed. In the application of vertical wire joint, it occurs a bad continuous phenomenon and even a break circuit.
3. Referring to FIGS. 4 and 5, a leading wire 31 extended outside is vertical to the edge of the metal mesh 3. Deforming the leading wire 31 and connecting it to the cathode plate 4. The vertical extension of the leading wire 31 makes the metal mesh 3 deforms and affect the restrained pore structure within the valid area of the metal mesh 3 and thereby increase the invalid area 33.

Method for fabricating mesh of field emission display and structure thereof


A lighting device configured for professional illumination. The lighting device includes a head and a component emitting oil fumes, and a fluid tight housing. An oil fume absorbing filter is arranged within the housing.

Lighting devices of various types for professional illumination of a given environment are generally known.
One or more of such lighting devices may e.g. be used to illuminate a stage, stadium, arena, or other areas during events like a music concert, theatre performance, a fashion show, a sporting event, a convention, etc.
One or more of such lighting devices may e.g. also be used to illuminate at least a part of a building, a landmark, a sporting field, a monument, or the like.
Additionally, one or more of such lighting devices may e.g. also be used to illuminate an environment or one or more parts thereof e.g. in connection with an event. This may e.g. be illuminating air by light in particular if the air contains moisture, dust, smoke, or other.
The one or more lighting devices may be installed and used more or less permanently or for a longer period of time, e.g. for illumination of a building, landmark, or the like, or for a shorter period of time, e.g. for illumination of a stage during a concert, sporting event, or the like.
In general, one or more of such professional lighting devices may be used to illuminate basically any environment or parts thereof, and/or object(s) either permanently or temporarily.
Professional lighting devices normally have some characteristics that set them further apart (than just being of another use) from lighting devices for personal/home use, such as minimum durability, illuminance and luminous emittance, reliability, etc.
Lighting devices are known which comprise a light source that can be moved in more or less any desired orientation, so that a light beam emitted by a light source can be directed along basically any desired direction (there may be one or more blind spots or areas but then normally of no practical consequence given a sufficient distance between the lighting device and the environment to be illuminated).
To this end, the light source is supported by the lighting device and may be rotated about one or two axes by use of suitable motors or similar.
Such lighting devices are within the professional lighting segment sometimes referred to as moving heads.
They are during use normally placed on a substantially flat or horizontal surface or suspended from or mounted on an appropriate frame, rack, stand, support, or the like.
The illumination need not only be static (although it can be) but may also be dynamic, e.g. as sometimes used during concerts, sporting events, etc., where the light source(s) of the lighting device(s) is/are moved over time in a controlled and/or pre-determined or programmed manner.
There is often a need for outdoor use of such lighting devices in an outdoor environment. For this purpose the lighting devices should preferably be protected against humidity and dust and other environmental hazards.
In order to solve this problem, such lighting devices may be manufactured with completely closed housings, where the components of the lighting devices are enclosed in a housing devoid of openings and where shell parts of the housing is provided with gaskets in order to make the lighting device completely water/air tight—or at least as water/air tight as possible. Such lighting devices may be manufactured to comply with national or international standards. For example it is desired that such lighting devices may comply with the International Electrotechnical Commission (IEC) standard, e.g. IEC 60529, where the Ingress Protection Rating is IP65, IP66 or higher.
As mentioned above, such lighting devices are equipped with motors in order to control a lighting direction. Such motors or actuators and in some instances also rotational joints of the lighting devices need to be lubricated in order to function correctly over prolonged periods of time. Common lubricants and oils have an evaporation temperature, such as say 72° C.
It has been found that the temperature inside the housings of lighting devices such as described above may occasionally reach temperatures above the evaporation point despite the use of modern light sources. When the oil evaporates, and cannot ventilate to the outside environment due to a dust and moisture tight housing of the lighting device there is a risk that the oil will condense on vital electrical component or on the lens or other optics in portions/parts of the lighting device where the temperature is lower or when the lighting device is turned off. Condensed oil on electrical components may cause malfunction thereof. Condensed oil on the lens may influence the quality of light emitted from the lighting device. Both situations are undesirable.
Therefore it is an object of the present invention to alleviate the problem of condensing oil in dust and water/moisture tight professional lighting devices.


Location information is tagged in a packet based network. SIP signaling messages are used to initiate a communication session between at least two end user devices in a packet based telecommunications network. The communication session is routed through various intermediate network elements of the packet based network. The intermediate network elements tag the signaling messages with information indicating their geographic location or otherwise provide such location information. In response to the signaling messages and preferably before the communication session is established, the location information indicating the location of the intermediate network elements in the routing of the communication session between the end user devices is made available. An end user device or apparatus may receive the location information and provide a user display indicating the routing and status of the communication session being initiated.

A packet based telecommunications network is a geographically distributed collection of nodes interconnected by communication links and segments for providing communication sessions (e.g., phone calls, multimedia and other data) between end nodes. The end nodes typically consist of user devices, such as personal computers, cell phones, personal digital assistants (PDAs), and the like. Many types of packet based telecommunications networks are available, with the types ranging from local area networks (LANs) to wide area networks (WANs). LANs typically connect nodes over dedicated private communication links located in the same general physical location, such as a building or campus. WANs, on the other hand, typically connect large numbers of geographically dispersed nodes over long-distance communication links, such as common carrier telephone lines. Examples of WANs are 3GPP and 3GPP2 compliant wireless networks, and Long Term Evolution (LTE) wireless networks. The nodes of packet based networks typically signal each other over the network by exchanging discrete frames or packets according to predefined protocols, such as the Transmission Control Protocol/Internet Protocol (TCP/IP). The Internet itself connects various networks throughout the world, providing global communication between nodes in the various networks.
A packet based telecommunications network may comprise a series of intermediate nodes (e.g., routers) that are configured to carry communications through the network to the end nodes. Routers are often configured to "route" data, such as packets, between various nodes in the network. Routing is typically performed at layer-3 (L3), which is the network layer of the Open Systems Interconnection (OSI) network model. Routers often maintain forwarding databases (FDBs), which are typically configured to hold routing information including L3 addresses and interface information that the router uses to determine where data (e.g., data packets) are to be forwarded in order to reach their destination. For example, a router may have a routing database containing one or more entries wherein each entry contains an L3 destination address of a destination node and interface information about an interface on the router through which the destination node may be reached. A data packet containing a destination address that matches a destination address of an entry in the routing table is forwarded by the router to the interface specified by the matching entry for transfer to the destination node.
The end nodes of a communication session are known and defined as part of the communication session. Although the physical (geographical) locations of the end nodes may initially be unknown, some IP based communication networks enable an end node to learn its geographic location from a server. In a wireless network, the server may employ triangulation or other methods to determine the end node's geographic location. The end node may then learn its location by issuing a request to the server to which the server responds with the geographic location. See, for example, European Patent Application No. 1 477 302 entitled "Integrating Geographical Contextual Information Into Mobile Enterprise Application", or IETF RFC 3825, by J. Polk et al., entitled "Dynamic Host Configuration Protocol Option for Coordinate-based Location Configuration Information". Numerous efforts to obtain the geographical location of end nodes is known for purposes of 9-1-1 and other emergency services. See, for example, draft IETF document entitled "Emergency Call Services for SIP-based Internet Telephony" by Henning Schulzrine, dated Mar. 25, 2001.
The packets for communications sessions are often routed through various networks and intermediate network elements. In packet based networks, each session (and even each message) may be transferred via a different route. For example, a call made from Australia to Finland may go through UK and Sweden while a similar call made a minute later may take a totally different route. In an ad-hoc network, such as a mesh network, this is further complicated since a user device may operate as either an end node or an intermediate node.
The physical (geographical) route of intermediate network elements through which the packets travel is not known in advance for several reasons. A router may execute one or more routing protocols that enable the router to route packets and exchange routing information with other routers in the network. The routers often use this information to configure (e.g., compute) their FDBs. The routing protocols may include distance-vector protocols, such as the Routing Information Protocol (RIP), or link-state protocols, such as the Intermediate-System-to-Intermediate-System (IS-IS) protocol and the Open Shortest Path First (OSPF) protocol.
Since the routing is not known in advance, the intermediate network elements are not known and may be signaling elements (such as a Call State Control Function (CSCF) in a 3GPP network), media gateways, or even user devices in an ad-hoc network. It would be useful to obtain information about the intermediate network elements. Furthermore, it will be useful to know the geographical location of the intermediate nodes routing a communication session. The intermediate nodes may be in different countries, even when both the end nodes are in the same country.
The reasons for this may be various. For example, an organization may want to route traffic via a foreign country for tax purposes (e.g. to avoid tax on local calls), or an operator's network infrastructure (e.g. operator's network elements) may be located in different countries. Currently, it is difficult to know reliably what network elements have been involved in a communication session and the countries in which those network elements are located.
This creates tax problems and law enforcement related problems. Different taxes may apply to communications based on the countries involved. Currently, it is very difficult to get and document this information reliably. Certain law enforcement actions, such as wiretapping, vary by jurisdiction. For example, different laws may apply to foreign communications (or communications that involve a foreign country). It is also difficult to know reliably if foreign countries were involved in the call (e.g. only the operator may be known). There are various prior attempts related to these concerns, but none of them are sufficient. For country boundary information, the operator identity provided by an network operator was typically enough to make the assumption that the home country of that operator was involved (similarly, visiting network information may have been available). For tax purposes, it was usually enough to trust the word of the operator.
For diagnostic purposes, there may be a natural disaster and/or human conflict strife affecting a region, city or neighborhood. It would be useful to know what effect this is having on communications, particularly geographic routing on a per session and/or per packet basis. Real-time diagnostic maps in which network elements are represented by their IP address or other identity information (and function name, such as CSCF) are not sufficient. Ad hoc networks could also benefit from diagnostic monitoring of routing as it is an easy way to find out which devices are willing and able to route communications traffic.
A network operator may maintain a separate database, which includes the physical location of network elements, but it is not previously known how to utilize that information in real-time or near real-time on a per session or a per packet basis. But a network element can be physically moved, and the database entry corresponding to that network element may not be updated properly when the location changes.
It also might be useful and entertaining for end users to know the geographical route for packet traffic of their communication sessions. Currently, when an end user is making a call, sending a message, or initiating another kind of communications session, the user device typically is not very informative and just displays "calling . . . " or "in progress" while the communications session is set up. While U.S. Pat. No. 6,278,454 does discuss a user interface (UI) that provides call progress information, it does not provide geographic routing or location information.
In light of the shortcomings described above, it would be advantageous to develop methods and network elements which enable tagging of the location of intermediate nodes for a communications session in a packet based network. It would be preferable to have methods and apparatus that permit a device, such as an end user device, to utilize the tagged location information for various purposes, such as displaying the routing and progress of the communication session.

Location tagging method for packet based signalling


A flexible training wheel assembly fitted on each side of the rear wheel (10) of a bicycle, each training wheel assembly comprising: an upper bracket (1) removeably attached to the bicycle axle (11), a visco-elastic connector (2) attached to the upper bracket (1), and a lower arm (3) attached to the visco-elastic connector (2) at one end and to a training wheel (6) at the other end.

Commercially available training wheel assemblies typically comprise rigid brackets rigidly attached to the bicycle rear wheel axle. This rigidity inhibits the learning process. If the wheels are set low, the bicycle cannot be leaned at all, either to make a turn or just to compensate for riding on a cambered surface. If the wheels are set high the bicycle will lurch from side to side in an unnerving manner and, once the rider is leaning on one outrigger wheel, there is no restorative force acting to encourage the rider to regain the central equilibrium position.
A number of patents have been registered showing various designs, which attempt to address this problem. Most of the configurations proposed incorporate a suspension system based on the concept of a pivoted bracket supported by a spring, with the various fittings and fasteners required to retain the spring, whilst permitting the desired range of movement.
Some of these devices are quite complex and cumbersome, for example that disclosed in U.S. Pat. No. 4,810,000. In this design, the training wheels are raised and lowered by cables attached to the front wheel forks of the bicycle, which activates the cables as the front wheel is turned. As well as complexity and cost, this device has the added drawback that the movement of the training wheels is reliant upon correct adjustment of the mechanism, rather than simply responding to the normal lean of the rider.
Simpler, more viable designs typically employ a hinged bracket supported by a compression spring, plus the necessary fittings and fasteners. Typical of these devices are those disclosed in U.S. Pat. Nos. 5,064,213, 5,100,163 and 5,352,403.
These designs appear to be functional, however, since none appear to have been commercialized their principal drawback would seem to be cost to manufacture; they also have a "gadgety" appearance, which may not appeal to the market.
More importantly, the exposed coil spring design presents numerous pinch-points for trapping and injuring small fingers, which is a significant drawback.
The simplest design is that disclosed in U.S. Pat. No. 6,113,122 and previously in U.S. Pat. No. 5,707,069. It's main feature is that it combines the structural support of the outrigger wheel and the flexible spring action desired in the one element, namely a helically wound torsion spring.
This design appears to be functional and relatively cheap to manufacture. However, it may lack torsional rigidity about the vertical rod part of the member, allowing excessive fore and aft movement of the outrigger wheel. This would be especially so if the assemblies were installed back to front (ie. on the wrong sides), as the helical spring would then tend to open, rather than close.
The assemblies would need to be marked clearly "Left" and "Right" hand and would need to be installed correctly so. In addition, the steel torsion spring has virtually no inherent damping available to damp out unwanted oscillations or vibration.