Non-doped and doped lithium titanate Li4Ti5O12 obtainable by the thermal reaction of a stoichiometric composite oxide containing Li2TiO3 and TiO2, the preparation of the stoichiometric composite oxide, as well as a process for the preparation of lithium titanate Li4Ti5O12 and its use as anode material in rechargeable lithium-ion batteries.

The use of lithium titanate Li4Ti5O12, or lithium titanium spinel for short, as a substitute for graphite as anode material in rechargeable lithium-ion batteries was proposed some time ago.
A current overview of anode materials in such batteries can be found e.g. in Bruce et al., Angew. Chem. Int. Ed. 2008, 47, 2930-2946.
The advantages of Li4Ti5O12 compared with graphite are in particular its better cycle stability, its better thermal rating and the higher operational reliability. Li4Ti5O12 has a relatively constant potential difference of 1.55 V compared with lithium and achieves several 1000 charge/discharge cycles with a loss of capacity of <20%.
Thus lithium titanate has a clearly more positive potential than graphite which has previously usually been used as anode in rechargeable lithium-ion batteries.
However, the higher potential also results in a lower voltage difference. Together with a reduced capacity of 175 mAh/g compared with 372 mAh/g (theoretical value) of graphite, this leads to a clearly lower energy density compared with lithium-ion batteries with graphite anodes.
However, Li4Ti5O12 has a long life and is non-toxic and is therefore also not to be classified as posing a threat to the environment.
Recently, LiFePO4 has been used as cathode material in lithium-ion batteries, with the result that a voltage difference of 2 V can be achieved in a combination of Li4Ti5O12 and LiFePO4.
Various aspects of the preparation of lithium titanate Li4Ti5O12 are described in detail. Usually, Li4Ti5O12 is obtained by means of a solid-state reaction between a titanium compound, typically TiO2, and a lithium compound, typically Li2CO3, at high temperatures of over 750° C. (U.S. Pat. No. 5,545,468). This high-temperature calcining step appears to be necessary in order to obtain relatively pure, satisfactorily crystallizable Li4Ti5O12, but this brings with it the disadvantage that primary particles are obtained which are too coarse and a partial fusion of the material occurs. The product obtained in this way must therefore be ground extensively, which leads to further impurities.
Typically, the high temperatures also often give rise to by-products, such as rutile or residues of anatase, which remain in the product (EP 1 722 439 A1).
Sol-gel processes for the preparation of Li4Ti5O12 are also described (DE 103 19 464 A1). In these, organotitanium compounds, such as for example titanium tetraisopropoxide or titanium tetrabutoxide, are reacted in anhydrous media with for example lithium acetate or lithium ethoxide to produce Li4Ti5O12. However, the sol-gel methods require the use of titanium starting compounds that are far more expensive than TiO2 and the titanium content of which is lower than in TiO2, with the result that preparing a lithium titanium spinel by means of the sol-gel method is usually uneconomical, in particular as the product still has to be calcined after the sol-gel reaction in order to achieve crystallinity.
In addition, preparation processes by means of flame spray pyrolysis are proposed (Ernst, F. O. et al. Materials Chemistry and Physics 2007, 101 (2-3) pp. 372-378) as well as so-called "hydrothermal processes" in anhydrous media (Kalbac, M. et al., Journal of Solid State Electrochemistry 2003, 8 (1) pp. 2-6).
Further possibilities for preparing lithium titanate, in particular by means of solid-state processes, are for example described in US 2007/0202036 A1 and U.S. Pat. No. 6,645,673, but they have the disadvantages already described above, that impurities such as for example rutile or residues of anatase are present, as well as further intermediate products of the solid-state reaction such as Li2TiO3 etc.
Furthermore, in addition to the preparation of non-doped Li4Ti5O12, the preparation and properties of Al-, Ga- and Co-doped Li4Ti5O12 have also been described (S. Huang et al. J. Power Sources 165 (2007), pp. 408-412).

Process for the preparation of lithium titanium spinel and its use


An ejecting mechanism-equipped card connector is provided which can be manufactured as a simpler and low cost unit. The card connector has a movable actuator member (74) arranged at an inner end section (52) of a push rod (50) and a cam groove (66) provided in a header body (14a) and operating the actuator member. The cam groove (66) has a drive section (66a) for, when the push rod (50) is moved from an extended position to a pushed-in position of the push rod (50), laterally projecting and guiding the actuator member (74), a latching section (66b) for, when an urging force on the pushed-in rod is released, retracting the actuator member (74) to a position not engageable with the projection (48) to latch it, and a return section (66c) for, when the push rod (50) is urged, unlatching the actuator member (74).

1. Field of the Invention
The present invention relates to a card connector for electrically and mechanically connecting a PC card to an electronic apparatus, such as a computer and, in particular, to an ejecting mechanism-equipped card connector for PC cards.
2. Brief Description of Prior Developments
Japan Patent Application Kokai Publication and U.S. Pat. Nos. 5,558,527 and 5,575,669 disclose an ejecting mechanismequipped card connector whereby, even with the PC card mounted there, a push button for the withdrawal of the PC card is retained in the same position as in a not-mounted state and the push button is projected only when the PC card is withdrawn.
The ejecting mechanism basically includes an operation rod having a push button at an outer end section and spring-urged outwardly, a drive rod for driving a PC card withdrawal plate through a lever, an intermediate member driven under an action of a cam and allowing a connection or disconnection to be made between an outer operation rod and an inner drive rod and a casing for slidably guiding the operation rod and drive rod. A generally heart-like cam groove is formed in the bottom wall of the casing with its projecting end side outward and the recessed side inward. When a cam following pin projected from the operation rod engages with the cam groove and the operation rod is moved, it can be moved in the cam groove in a given direction. In a normal state, the cam follower pin is set in the recess of the heart-like cam groove and the operation rod is retained against the urging force of the spring. As a result, the push button is not greatly projected outside the electronic apparatus, thus preventing an operation error of the push button and not interfering with other devices.
When the PC card is to be withdrawn, the push button is lightly depressed. By doing so, the cam follower pin is pushed out of the recess Ad of the heart-like cam groove. Thereafter, the pin is moved under the urging force of the spring along the groove toward the projecting end side, so that the push button is greatly projected toward an outside of the electronic device. At this time, the intermediate member is driven under a cam action to allow a force to be transmitted from the operation rod to the drive rod. When the greatly outwardly projected push rod is pushed, an urging force acting on the push button is transmitted from the operation rod to the drive rod through the intermediate member, thus driving the lever and PC card withdrawal plate. Since the operation rod and drive rod are guided along the inner surface of the casing, it is not folded at an abutting section to the intermediate member. Together with the movement of the PC card withdrawal plate, the PC card is also moved and withdrawn out of the card connector. When an urging force on the push button is released after the withdrawal of the PC card, the cam follower pin of the operation rod is retained in the recess of the heart-like cam. The intermediate member enables the drive rod and PC card withdrawal plate to be freely moved, irrespective of the position of the operation rod, without interfering with the operation rod.
However, the conventional ejecting mechanism requires more component parts since the operation rod and drive rod, together with the intermediate member, are contained in the casing and guided along the inner surface of the casing. Therefore, there is a growing demand for a card connector answering the recent tendency of the electronic devices to become smaller and smaller in size and higher and higher in function.
It is accordingly the object of the present invention to provide an ejecting mechanism-equipped card connector which is achieved, taking the above into consideration, and can be manufactured as a simpler and low-cost unit.


A heat exchanger for an oxygenator comprises multiple tube sections, each having a longitudinal tube axis, wherein the tube sections are disposed as a bundle having a longitudinal bundle axis, and the tube sections are connected to each other in at least one connecting section of the bundle by joining by way of chemical and/or physical bonded joints. A method for producing the heat exchanger is also provided.

An oxygenator is an integral part of an extracorporeal blood circuit during open heart surgery. Temperature control takes place in a heat exchanger of the oxygenator by exchanging heat between the blood and a heat exchanger medium.
A heat exchanger is known from DE 10 2010 000 820 A1, which comprises multiple tube sections that are knitted to each other by transversely extending knitted seams, known as support threads, to form a mat. The mat is rolled to form a heat exchanger body, and a heat exchanger is produced therefrom. Additional heat exchangers comprising knitted tube mats are known from DE 28 25 065 A1 and from WO 2011/139392 A1.
It is disadvantageous that a heat exchanger, in particular tube sections used therefor, can become polluted and/or damaged during production.

Heat exchanger for an oxygenator and method for producing such a heat exchanger


A level shifter circuit includes a level shifter, an inverter, a first switch circuit and a second switch circuit. The level shifter includes a first transistor, a second transistor, a third transistor and a fourth transistor. The inverter receives an input signal and thus generates an inversion input signal. The first transistor and the second transistor are respectively controlled by the input signal and an output signal to output an inversion output signal. The third transistor and the fourth transistor are respectively controlled by the inversion input signal and the inversion output signal to output an output signal. The first switch circuit is coupled to the level shifter and turns off the fourth transistor when the third transistor is turned on. The second switch circuit is coupled to the level shifter, and turns off the second transistor when the first transistor is turned on.

1. Field of the Invention
The invention relates in general to a level shifter circuit, and more particularly to a level shifter circuit capable of increasing a shifting-speed and decreasing a short current.
2. Description of the Related Art
FIG. 1 (Prior Art) is a circuit diagram showing a conventional level shifter circuit 10. Referring to FIG. 1, the conventional level shifter circuit 10 includes a level shifter 110 and an inverter 120. The inverter 120 receives an input signal IN and inverts the input signal IN into an inversion input signal IN′ to be outputted to the level shifter 110. The inverter 120 includes a transistor P3 and a transistor N3, which are respectively a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxidation semiconductor (NMOS) transistor. The control terminal of the transistor P3 is coupled to the control terminals of the transistor N3 and a transistor N1, and the second terminal of the transistor P3 is coupled to the first terminal of the transistor N3 and the control terminal of a transistor N2. The first terminal of the transistor P3 and the second terminal of the transistor N3 respectively receive a power voltage Vcc and a power voltage Vss.
The level shifter 110 outputs an output signal OUT and an inversion output signal OUT′ ranging from VDD to Vss according to the levels of the input signal IN and the inversion input signal IN′. The input signal IN and the inversion input signal IN′ may range from 0 to 1.8V, while VDD and Vss are respectively 5V and 0V, for example.
The level shifter 110 further includes the transistor N1, a transistor P1, the transistor N2 and a transistor P2, wherein the transistor N1 and the transistor N2 are NMOS transistors, while the transistor P1 and the transistor P2 are PMOS transistors, for example. The transistor N1 and the transistor P1 are respectively controlled by the input signal IN and the output signal OUT to output the inversion output signal OUT′, while the transistor N2 and the transistor P2 are respectively controlled by the inversion input signal IN′ and the inversion output signal OUT′ to output the output signal OUT.
The first terminals of the transistor P1 and the transistor P2 are coupled to a power voltage VDD. The second terminal of the transistor P1 is coupled to the first terminal of the transistor N1 and the control terminal of the transistor P2. The second terminal of the transistor P2 is coupled to the first terminal of the transistor N2 and the control terminal of the transistor P1. The second terminals of the transistor N1 and the transistor N2 receive the power voltage Vss. The control terminals of the transistor N1 and the transistor N2 respectively receive the input signal IN and the inversion input signal IN′.
FIG. 2 (Prior Art) shows waveforms of the input signal, the inversion input signal, the output signal and the inversion output signal of the conventional level shifter circuit. As shown in FIG. 2, the input signal IN, the inversion input signal IN′, the output signal OUT and the inversion output signal OUT′ are respectively represented by curves 210, 220, 230 and 240. When the input signal IN is changed from 0V to 1.8V, the output signal OUT is changed from 0V to 5V. That is, the conventional level shifter circuit 10 converts the low voltage level of 1.8V into the high voltage level of 5V for output. The inversion input signal IN′ is changed from 1.8V to 0V, and the inversion output signal OUT′ is changed from 5V to 0V
FIG. 3 (Prior Art) shows a waveform of a short current of the conventional level shifter circuit. As shown in FIG. 3, the short current of the conventional level shifter circuit 10 is represented by the curve 310. As can be clearly understood from the curve 310, a short current IDS1 generated by the conventional level shifter circuit 10 approaches 30 uA at the time of 4 n seconds.
In the conventional level shifter circuit 10 (see FIG. 1), however, when the transistor N1 is turned on, the short current IDS1 flows through the transistor N1 and the transistor P1 because the transistor P1 is not turned off in time. In addition, because the transistor N1 and the transistor P1 are in the on state, the inversion output signal OUT′ has the fighting phenomenon between the power voltage VDD and the power voltage Vss.
According to the same working principle, when the transistor N2 is turned on, another short current IDS1 often flows through the transistor N2 and the transistor P2 because the transistor P2 is not turned off. In addition, because the transistor N2 and the transistor P2 are in the on state, the output signal OUT has the fighting phenomenon between the power voltage VDD and the power voltage Vss.
Consequently, the conventional level shifter circuit 10 becomes too slow, and the short current IDS1 also causes the unessential power consumption of the level shifter circuit 10. In addition, when the power voltage Vcc is powered down and the power voltage VDD is still powered on, the higher leakage current is induced because the output signal OUT and the inversion output signal OUT′ are floating.


Disclosed is a method for identifying a user interest, including: obtaining training samples and test samples, the training samples being obtained by manually labeling after the corresponding topic models have been trained based on text data; extracting characteristics of the training samples and of the test samples, and computing optimal model parameters of a logistic regression model by an iterative algorithm based on the characteristics of the training samples; evaluating the logistic regression model based on the characteristics of the test samples and an area AUC under an ROC curve to train and obtain a first theme classifier; determining a theme to which the text data belongs using the first theme classifier, computing a score of the theme to which the text data belongs based on the logistic regression model, and computing a confidence score of the user being interested in the theme according to a second preset algorithm. Further disclosed are a device for identifying a user interest and a computer-readable storage medium.

In recent years, with the rapid development of the Internet, especially the sudden rise of social media, people are increasingly aware of the social media's various influences on themselves and on the information dissemination environment. In the past, people have been passively obtaining information from the Internet all along. Nowadays, however, more and more people are actively participating in the generation and dissemination of information on social media, resulting in a huge amount of user information and social relationship information.
But currently the internal data of many enterprises are usually mostly transaction records. The included customer information is not comprehensive enough to accurately determine potential customers and understand user needs. Therefore, how to identify a user's interest and fully understand the user through Internet data information thus helping enterprises to accurately determine potential customers has become a problem that needs to be solved urgently.

Method and device for identifying a user interest, and computer-readable storage medium


A distinctive method and apparatus for depositing a pattern of material, such as hot-melt adhesive, onto a substrate comprises a supplying mechanism for forming a first and at least a second substantially continuous stream of the selected material, and a gas-directing mechanism for forming a plurality of gas streams. The gas streams have selected velocities and are arranged to entrain the material streams to impart a swirling motion to each of the material streams as it moves toward the substrate. A transport mechanism moves the substrate relative to the supply mechanism along a selected machine direction. A regulating mechanism controls the supplying mechanism and gas-directing mechanism to direct the material stream in a selected path toward the substrate and deposit the material in adjacent semi-cycloidal patterns on the substrate while closely controlling a selected cross-directional positioning of one or more of the deposited patterns.

In the manufacture of disposable absorbent articles, such as diapers, feminine care products, incontinence products, and the like, adhesives have typically been applied in a pattern of multiple, is parallel glue lines which extend along the longitudinal dimension of the article. Such glue line patterns leave unbonded gaps between the lines, and the unbonded gap areas tend to have lower strength and lower integrity. As a result, the article can be more susceptible to stretching and tearing when adhesive tapes are employed to secure the article on the wearer, and the article may be less able to maintain its structure and hold together during use.
Sprayed and foamed adhesives have also been employed to assemble together various component layers of disposable absorbent articles. The adhesives may be thermoplastic-type adhesives or solvent-type adhesives. For example, see U.S. Pat. No. 3,523,536 to A. Ruffo and U.S. Pat. No. 4,118,531 to Minetola, et al. Swirled patterns of adhesive have been employed to construct articles such as shoes. For example, see U.S. Pat. No. 3,911,173 issued Oct. 7, 1975 to J. Sprague.
Various air forming techniques have been employed to form nonwoven fibrous webs. For example, U.S. Pat. No. 4,478,624 issued Oct. 23, 1984 to J. Battigelli, et al. describes a technique which employs a circular airflow component to help produce a more uniform distribution of fibers laid onto a foraminous conveyor. U.S. Pat. No. 2,903,387 issued Sep. 8, 1959 to W. Wade describes a technique for producing reticulated fibrous webs containing tubular or hollow fibers of elastomeric material. U.S. Pat. No. 2,950,752 issued Aug. 30, 1960 to P. Watson, et al. describes a spraying technique for forming relatively long, discontinuous, fine fibers of elastomeric materials. The fiber-forming liquid is extruded into and within a primary or high velocity stream of gas as a stream of plastic which is broken transversely into a plurality of fibers or fibrils before landing on a collector. U.S. Pat. No. 2,988,469 issued Jun. 13, 1961 to P. Watson describes a further spraying technique for forming relatively long, discontinuous, fine fibers of nonelastomeric material. A high velocity jet stream of gas attenuates and fibrillates a single large-diameter plastic stream into a multiplicity of fibers and fibrils without the formation of shot.
Molded articles and preforms have been produced by depositing fibers into a form and binding the fibers together with a resin binder. For example, U.S. Pat. No. 3,796,617 issued Mar. 12, 1974 to A. Wiltshire describes a method for making a fibrous preform which comprises the steps of randomly depositing short reinforcing fibers on a form, binding the fibers together with a settable resin binder, and rolling the resin-coated fibers on the form into a dimensionally uniform porous mat. U.S. Pat. No. 3,833,698 describes a technique in which chopped fibers are directly deposited in a localized manner onto the interior surface of a screen form. The fibers are held in place by an airflow through the screen form into a vacuum chamber, and the deposited chopped fibers are sprayed with a heat-curable resin binder. U.S. Pat. No. 3,904,339 issued Sep. 9, 1975 to J. Dunn describes a technique for depositing glass fibers and curable resin into molds. A spray means for depositing the resin and fibers is supported on an arm which is pivoted about a selected axis.
Particular nozzle structures have been developed to form filaments from thermoplastic, melt-extrudable materials. The nozzles may be configured to produce a swirling air flow which disrupts the flow of extruded material into a plurality of fine fibers. For example, U.S. Pat. No. 4,185,981 describes a technique for producing fibers from a viscous melt. High-speed gas streams have a component in the tangential direction of the circular sectional surface of the melt, and a component which approaches the central axial line of the melt towards the flowing direction of the melt and then departs from the central axial line. The melt is continuously flown as fiber in the flowing direction and outwardly in the radial direction in a vortex form, which is spiral or helical or both. The fibrous melt which has flown away is accelerated and drawn into long fibers having a diameter of 10-100 microns, or short fibers having a diameter of 0.1-20 microns. The fibers can then be accumulated to form a fibrous mat.
U.S. Pat. No. 2,571,457 issued Oct. 16, 1951 to R. Ladisch describes a technique in which a cyclone of gas disrupts a "filament forming liquid" into fibers and/or filaments which may be collected on a moving belt. U.S. Pat. No. 3,017,664 issued Jan. 23, 1962 to R. Ladisch describes a fiber-forming nozzle wherein a fiber-forming liquid is spread over the outside wall of a circular body as a thin film, and wherein a stream of spiraling elastic fluid rotates at high velocity to draw out fibers which are picked up from the film of fiber-forming liquid.
U.S. Pat. No. 3,905,734 issued Sep. 16, 1975 to E. Blair describes an apparatus for continuously making a tube of meltblown microfibers. The meltblown microfibers are deposited longitudinally upon a circumferential surface of a mandrel and then are axially withdrawn from one end of the mandrel tube.
U.S. Pat. No. 3,543,332 issued Dec. 1, 1970 to W. Wagner, et al. describes a spinning nozzle for spray spinning molten fiber-forming materials and forming fibrous assemblies such as nonwoven fabrics and the like. The nozzle includes gas passages which are inclined so that their axes do not intersect the axis of an extrusion orifice in the nozzle. Gas streams act to swirl filaments formed from the fiber-forming material to produce a random expanding conical pattern as the filaments travel toward a moving collector.
An article entitled "Application Potential of Controlled Fiberization Spray Technology" Nonwovens Industry, January 1988 by J. Raterman describes a process for spraying pressure-sensitive hot-melts. The process employs a line of spray heads using nozzles with integral air jets that produce fine monofilaments of adhesive swirled at high speeds in a helix or spiral pattern.
Conventional spray techniques, such as those discussed above, have not adequately regulated the distribution pattern and placements of the sprayed material onto a substrate. Ordinarily, the sprayed materials are deposited in a generally random pattern, and there can be excessive overspray and misplacement of the deposited materials. Where the sprayed materials are composed of adhesives, such as hot-melt adhesives, the overspray and misplacement can contaminate the equipment and require excessive maintenance. For the purpose of applying adhesives onto a substrate, the conventional techniques have not provided a sufficiently accurate control over the deposition pattern and have not been sufficiently flexible or readily adjustable to accommodate the placement of adhesives onto different widths of substrate. In addition, the conventional spray devices have been excessively sensitive to plugging when employed with viscous liquids, such as hot-melt adhesives.


A data reporting framework that works across on-premise and hosted Customer Relationship Management (CRM) platforms enabling definition and execution of secure custom reports is provided. A fetch query language of a CRM platform is used along with reporting service tools and constructs to enable users to upload and execute custom fetch based reports with support for expressions, code, formatting, and drill through. Users are also enabled to build simple reports from within CRM and, if needed, enhance those reports using reporting service tools and re-upload in CRM. Furthermore, custom reports may be executed in a sandboxed environment to provide full security in a multi-tenant, hosted CRM system.

Customer Relationship Management (CRM) is a set of strategies and programs for managing an organization's interactions with customers, clients, sales prospects, and similar entities. It involves using technology to organize, automate, and synchronize business processes such as sales activities, marketing activities, customer service, technical support, and comparable ones. With an overall goal of finding, attracting, and winning new clients, nurturing and retaining existing clients, enticing former clients back, and reducing costs of marketing and client service, CRM describes an organization-wide business strategy including customer-interface departments as well as other departments. Increases in revenue, higher rates of client satisfaction, and savings in operating costs are some of the benefits measurable of CRM to an enterprise.
For efficiency and satisfactory user experience, hosted, multi-tenant CRM systems need to provide their users a rich support for data reporting. Often these reporting solutions may be restrictive in nature when compared to their on-premise, single-tenant CRM system counterparts due to security and other reasons. Defining a rich and powerful framework for data reporting that works seamlessly between on-premise and hosted systems based on standard reporting tools remains a challenge.

Data reporting framework across on-premise and hosted CRM services


A self-test device for a monitor which enables a user to check whether the monitor is in a normal operating state or not by displaying a self-test pattern on the screen of the monitor if the user disconnect a cable connector of the monitor from a personal computer (PC). The self-test device includes a clamp signal generating section for receiving a pulse signal having a predetermined period and for generating a first pulse signal and a second pulse signal which is a clamp signal, and a self-test signal generating section for generating R',G',B' video signals which are self-test signals for the monitor by processing the first pulse signal generated from the clamp signal generating section and for outputting the R',G',B' video signals to the video processing section which is controlled by the clamp signal generated from the clamp signal generating section. If the cable connector is disconnected from the PC, a color block pattern formed by a combination of the R',G',B' video signals is displayed on the screen of the monitor, so that the user can recognize the state of the monitor by viewing the displayed color block pattern.

1. Field of the Invention
The present invention relates generally to a monitor. In particular, the present invention relates to a self-test device for a monitor which can self-test whether the monitor is in a normal operating state or not in case that a color picture is not displayed or is abnormally displayed on the screen of the monitor connected to a personal computer.
2. Description of the Related Art
Generally, a monitor has a self-test function whereby a prescribed picture for self-test is displayed on the screen so that a user can check the normal or abnormal state of the monitor by viewing the displayed picture if the user disconnect a cable connector of the monitor from the personal computer (PC) in case that a color picture is not displayed or is abnormally displayed on the screen of the monitor connected to the PC.
The conventional self-test circuit of a monitor, as shown in FIGS. 1 and 2, includes a cable connector 2 for connecting the monitor to a signal output section 1 of the PC, a display power management (DPM) section 3, connected to a self-test terminal ST of the cable connector 2, for performing a display power management function, a DPM control section 4 for receiving a self-test signal provided through the cable connector 2 and controlling the DPM section 3 according to the self-test signal, a video amplifying section 5, connected to red (R), green (G), blue (B) terminals of the cable connector 2, for amplifying R,G,B video signals inputted through the R,G,B terminals of the cable connector 2, and a video output section 6 for outputting the R,G,B video signals amplified by the video amplifying section 5 to display the outputted R,G,B video signals on the screen of the monitor.
In FIG. 2, the reference numeral B.sup.+ denotes a DC supply voltage, 5A denotes a video amplifier, R1 to R10 denote resistors, C1 to C3 denote capacitors, Q1 to Q5 denote transistors, L1 to L4 denote coils, D1 denotes a diode, and LD1 and LD2 denote light emitting diodes (LEDs).
The operation of the conventional self-test circuit as constructed above will be explained.
Referring to FIGS. 1 and 2, in a state that the signal output section 1 of the PC is connected to the cable connector 2 of the monitor, the self-test terminal ST of the cable connector 2 becomes in electric contact with the signal output section 1 of the PC which is connected to ground. Accordingly, the video signal outputted from the PC is transferred to the monitor and then displayed on the screen of the monitor.
At this time, if a suspend/standby signal of a `high` level is outputted from the DPM control section 4 which is connected to the self-test terminal ST of the cable connector, the transistors Q2 and Q3 in the DPM section 3 are turned on, causing the red LED LD1 to be turned off, while the green LED LD2 is turned on. Meanwhile, if the suspend/standby signal of a `low` level is outputted from the DPM control section 4 when no video signal is displayed on the monitor screen, the transistors Q2 and Q3 are turned off, causing both the red and green LEDs LD1 and LD2 to be turned on, resulting in that the two LEDs LD1 and LD2, as a whole, display an umber color which is the combination of the red and green colors.
For instance, since the suspend/standby signal outputted from the DPM control section 4 becomes `low` and thus the LEDs LD1 and LD2 display the umber color during the display power management (DPM) operation of the monitor, a user can recognize that the monitor is now performing the DPM function by viewing the displayed color of the LEDs LD1 and LD2.
If the cable connector 2 of the monitor is disconnected from the signal output section 1 of the PC in the normal operating state of the monitor as described above, the self-test terminal ST of the cable connector 2 is floated, causing the transistor Q1 in the DPM section 3 to be turned on. At this time, no video signal is displayed on the screen of the monitor. Also, the DPM function is not performed, and only the green LED LD2 is turned on.
In the conventional monitor which does not employ a microprocessor IC or an on-screen display (OSD) function, however, the DPM function is performed utilizing the self-test signal ST though the cable connector 2 of the monitor is disconnected from the signal output section 1 of the PC. Accordingly, a self-test pattern cannot be displayed on the monitor screen, and thus the user cannot check the normal or abnormal operating state of the monitor.


Deep draw packaging includes placing an object (C) in a concave container portion (1) formed by molding a film with small shrinkability (A), that is a film having a residual thermal shrinkage rate at 100° C. of 1 to 15 %. The film (A) is formed by stretching a film having deep draw moldability and then thermally relaxing the film. The film has a surface which is formed of a heat sealable material which becomes the inner wall of the container portion. The concave container portion (1) is thereafter transferred to to a vacuum packaging apparatus (5) where it is covered by a cover portion (2) formed of a film (B) which can be heat welded to the film (A). A side face portion (11) and a bottom face portion (12) of the concave container portion (1) are thermally shrunk into close contact with the object (C). Less curling is exhibited when an upper peripheral portion (13) of the concave container portion (1) is sealed with the film (B).

Vacuum packaging (generally deep draw packaging or skin packaging) is employed for packaging of objects (in particular, processed foods such as processed meat products and fish-based paste products).
In the case of deep draw packaging, generally, a belt-shaped film is continuously fed to a cooling mold having a plurality of concave portions; the film is heated, and then pressed onto the mold under vacuum and/or pressurized conditions, thereby forming a plurality of concave containers through deep drawing; an object (e.g., sliced ham) is placed in each of the containers; a film for a top film is continuously fed to cover the containers; and air is evacuated from the containers, followed by thermal sealing of the upper peripheral portion of each of the containers with the top film, to thereby produce a plurality of vacuum-packaged products in a continuous manner.
However, deep draw packaging involves problems in that, for example, wrinkles are formed at a portion at which a top film or an object (e.g., roast pork) placed in a concave container comes into close contact with the side(s) or bottom of the concave container, vacant gaps are formed at the contact portion and meat juice or drip enters the vacant gaps, or pinholes tend to be generated at the thus-formed wrinkles or vacant gaps. This occurs because a variation in the size of the object as measured in a horizontal direction is greater than a variation in the size thereof as measured in a vertical direction. Therefore, a mold employed in deep draw packaging is generally required to have a size and a shape which fit those of an object to be packaged.
In food processing manufacturers, in pursuit of high production efficiency, a variety of objects have been vacuum-packaged through deep draw packaging by use of a general-purpose mold (without exchange of the mold). However, there have arisen more and more quality-related problems caused by the aforementioned wrinkles, vacant gaps, or pinholes.
In view of the foregoing, there has been disclosed a method in which an object is vacuum-packaged with a conventional multi-layer film for deep draw packaging, and high-temperature steam is sprayed onto the resultant packaged product for thermal shrinkage of the film, to thereby smooth out wrinkles from being formed on the packaged product. However, this method involves problems in that wrinkles may be newly formed at a portion of the packaged product that has no wrinkles, as well as at a portion thereof that has wrinkles, and that the contents of the packaged product may collapse as a result of shrinkage of the entirety of the film.
The aforementioned method employing steam spraying, or a method in which a packaged product is boiled so as to thermally treat the contents of the product and to smooth out wrinkles (see claim 1 and sections 0024 and 0025 of Japanese Patent Application Laid-Open (kokai) No. 8-198208) involves problems in terms of moisture remaining in the packaged product or removal of the moisture.
Meanwhile, there has been disclosed an apparatus for smoothing out wrinkles on a deep draw vacuum-packaged product, which apparatus includes a hot air generation/spraying unit for spraying hot air having a temperature equal to or higher than the molding temperature onto only wrinkles formed on the surface of a film serving as a bottom film for the container portion of a vacuum-packaged product (hereinafter such a film may be referred to as a "container material film"); a unit for cooling the container material film for preventing the effect of hot air on a portion of the film that has no wrinkles; a flange portion cooling unit for preventing the effect of hot air on a flange portion of the packaged product; and a hot air jet shielding unit for preventing the effect of hot air on other units and on packaged products adjacent to the target vacuum-packaged product (see claim 1 of Japanese Patent Application Laid-Open (kokai) No. 4-31218).
However, in the case of this technique, when an object to be packaged has a shape and a size which considerably differ from those of a mold, a portion of a packaging film that undergoes shrinkage may vary depending on the type of the unit to be employed, or the film may fail to be shrunk sufficiently, and therefore, wrinkles cannot be smoothed out completely. In the case where a shrinkable film is employed, a peripheral seal portion (non-molded portion) of the container portion of a packaged product also undergoes shrinkage, and thus the seal portion is curled attributed to the difference in percent shrinkage between the seal portion and a top film, leading to poor appearance of the product.
Such a container material film employed for deep draw packaging is required to have, for example, deep draw moldability, heat resistance, pinhole resistance, labelability, and sealability to a top film. In addition, the film is required to have gloss, transparency, sealing strength, and ability to prevent removal of a label therefrom. In accordance with the type of an object to be packaged, the film may be required to have easy peelability to a top film. In order to satisfy such requirements, a variety of packaging materials have been proposed.
For example, there has been disclosed a co-extruded composite film for deep draw molding, the film including a polybutylene terephthalate resin layer serving as the outermost layer, a sealable resin layer serving as the innermost layer, and a gas-barrier resin (e.g., polyamide resin) layer serving as an intermediate layer (see claim 1 of Japanese Patent Application Laid-Open (kokai) No. 6-226930).
Also, there has been disclosed a method employing, as a container material film, a stretch-oriented multi-layer film which includes a surface layer formed of a thermoplastic resin, an intermediate layer formed of a polyamide resin, and a surface layer formed of a sealable resin, and which has an impact energy (on the basis of a 50 μm thickness) of 1.5 J or more as measured at −10° C., wherein a packaged product is produced under vacuum by use of a conventional deep draw packaging apparatus, and then the product is subjected to shrinkage with hot water (e.g., boiling) for smoothing out wrinkles thereon (see claim 1 of International Patent Publication WO 01/98081).
Meanwhile, skin packaging is advantageous in that a film for packaging can be brought into close contact with an object to be packaged, and thus no wrinkles are formed on the resultant packaged product; i.e., the packaged product exhibits good appearance. In a fundamental technique of skin packaging, an object to be packaged is placed on a base film, a heat-softened film for skin packaging is covered over the object, and air is evacuated from the resultant product, to thereby bring the skin-packaging film into close contact with the object.
There has been disclosed a skin packaging method in which an object is packaged, by use of a skin packaging apparatus, with a skin-packaging film which includes at least two layers: a sealable resin layer (a) constituting the side of the film opposite the side which faces a mold, and a stretched polyamide resin layer (b) formed of a polyamide resin having a melting point higher, by about 15° C. or more, than the heating temperature of the film, and which exhibits, at the film heating temperature, a thermal shrinkage stress of 200 g/15-mm width or less and a percent thermal shrinkage of 3% or more as measured in at least one direction (see claims 1 through 7 of Japanese Patent Application Laid-Open (kokai) No. 2001-71435).
This publication describes that the packaging method can produce a wrinkle-free skin-packaged product. However, this method fails to solve economical problems caused by low molding speed (i.e., a disadvantage derived from skin packaging).

Deep draw packing method and film with small shrinkability for deep draw packing

Kureha Chemical Industry Company, Limited


Disclosed is a liquid ejecting apparatus, and a method of controlling the liquid ejecting apparatus, whereby at a timing at which temperature detection and ejection pulse change are subsequently performed, a frequency of execution of temperature detection and driving pulse change differs according to whether temperature detected by the temperature sensor is in a first temperature range in which a degree of change in viscosity of ink for change in temperature is relatively high or in a second temperature range in which the degree of the change in viscosity for the change in temperature is relative stable. More specifically, in the first temperature range, the frequency of execution of temperature detection and driving pulse change is high compared to the second temperature range.

1. Technical Field
The present invention relates to a liquid ejecting apparatus, such as an ink jet type recording apparatus, and a method of controlling the liquid ejecting apparatus, and, in particular, to a liquid ejecting apparatus that ejects liquid from nozzles by driving a pressure generation section in such a way as to apply a driving waveform included in a driving signal to the pressure generation section and by generating pressure variation in liquid within pressure chambers which communicate with the nozzles, and a method of controlling the liquid ejecting apparatus.
2. Related Art
A liquid ejecting apparatus is an apparatus which includes a liquid ejecting head and ejects (discharges) various types of liquid from the liquid ejecting head. The liquid ejecting apparatus includes, for example, an image recording apparatus, such as an ink jet type printer (hereinafter, simply referred to as a printer) or an ink jet type plotter. In recent years, the liquid ejecting apparatus has been applied to various types of manufacturing apparatuses with emphasis on a feature in which it is possible to cause a negligible tiny amount of liquid to accurately land on a specific position. The liquid ejecting apparatus is applied to, for example, a display manufacturing apparatus which manufactures the color filters of a liquid crystal display or the like, an electrode forming apparatus which forms electrodes of an organic Electro Luminescence (EL) display, a Field Emission Display (FED), or the like, and a chip manufacturing apparatus which manufactures a biochip (biochemical element). Further, a recording head for the image recording apparatus ejects fluid ink, and a color material ejecting head for the display manufacturing apparatus ejects the solutions of respective color materials of Red (R), Green (G), and Blue (B). In addition, an electrode material ejecting head for the electrode forming apparatus ejects fluid electrode materials, and a bio organic matter ejecting head for the chip manufacturing apparatus ejects the solution of a bio organic matter.
An ink jet type recording head (one kind of a liquid ejecting head. Hereinafter, simply referred to as a recording head), which is mounted on the above-described printer, includes nozzle rows (nozzle groups) in which nozzles for ejecting ink are provided in a plurality of rows, and, for example, a piezoelectric element, a heating element, an electrostatic actuator or the like as a pressure generation section which ejects ink from the nozzles by generating pressure variation in ink within pressure chambers which communicate with the nozzles. Further, the printer is configured to eject ink by driving the pressure generation section in such a way as to apply a driving pulse, which is generated by a driving signal generation section, to the pressure generation section.
Here, in recent years, there is a case in which the printer is used for the purpose of printing a recording medium, which is larger than a recording medium, such as printing paper used in a general home printer, for example, outdoor advertisement. For example, a resin film which is formed of vinyl chloride, or a film which is acquired by coating or laminating polyester fiber woven fabric called tarpaulin using synthetic resin is used as the recording medium in this case with emphasis on weather resistance. Further, there is a case in which ink including thermoplastic resin particles (hereinafter, referred to as resin ink) are used as ink which is used to perform printing and recording on the recording medium (for example, refer to JP-A-2010-221670). When the resin ink hardens on the recording medium, a strong resin film is formed, with the result that the resin ink is excellent in abrasion resistance and weather resistance compared to water-based ink, and thus the resin ink is suitable for printing of outdoor advertisements or the like.
However, when an image or the like is recorded by ejecting resin ink to a hydrophobic recording medium, such as the resin film, the resin ink which lands on the recording medium should be rapidly solidified and fixed, and thus a configuration has been proposed in which a heating section (platen heater) that heats the recording medium on a platen is provided, and in which the ink that lands on the recording medium is promoted to be dried and fixed by heating the recording paper using the heating section.
In the above configuration in which the recording medium is heated using the heating section, heat from the heating section is transmitted to the recording head, and thus the viscosity of ink is changed as time elapses. Generally, the viscosity of ink is lowered as temperature in the recording head rises. When the viscosity of ink is lowered, the amount of ink (weight and volume) which is ejected using the same pressure increases. That is, ejection characteristics vary according to temperature. Therefore, in a printer according to the related art, a configuration has been proposed in which a temperature detection section, such as a thermistor, is provided in the vicinity of the inside or the outside of a recording head and in which ejection characteristics are uniformly maintained regardless of temperature by changing a driving pulse according to detected temperature. However, if temperature detection and driving pulse correction are frequently performed during a printing process, there is a problem in that the throughput of the entire printing process is lowered because the processing function of the control unit of the printer is caused to be lowered.
The problem is not limited to a printer that ejects ink and exists in a liquid ejecting apparatus that ejects liquid which has relatively large change in viscosity with regard to temperature in the same manner.

Liquid ejecting apparatus and method of controlling liquid ejecting apparatus


The present technology is generally directed to horizontal heat recovery coke ovens having monolith crowns. In some embodiments, an HHR coke oven includes a monolith crown that spans the width of the oven between opposing oven sidewalls. The monolith expands upon heating and contracts upon cooling as a single structure. In further embodiments, the crown comprises a thermally volume-stable material. In various embodiments, the monolith and thermally-volume-stable features can be used in combination or alone. These designs can allow the oven to be turned down below traditionally feasible temperatures while maintaining the structural integrity of the crown.

Coke is a solid carbon fuel and carbon source used to melt and reduce iron ore in the production of steel. In one process, known as the "Thompson Coking Process," coke is produced by batch feeding pulverized coal to an oven that is sealed and heated to very high temperatures for 24 to 48 hours under closely-controlled atmospheric conditions. Coking ovens have been used for many years to convert coal into metallurgical coke. During the coking process, finely crushed coal is heated under controlled temperature conditions to devolatilize the coal and form a fused mass of coke having a predetermined porosity and strength. Because the production of coke is a batch process, multiple coke ovens are operated simultaneously.
The melting and fusion process undergone by the coal particles during the heating process is an important part of coking. The degree of melting and degree of assimilation of the coal particles into the molten mass determine the characteristics of the coke produced. In order to produce the strongest coke from a particular coal or coal blend, there is an optimum ratio of reactive to inert entities in the coal. The porosity and strength of the coke are important for the ore refining process and are determined by the coal source and/or method of coking.
Coal particles or a blend of coal particles are charged into hot ovens, and the coal is heated in the ovens in order to remove volatile matter ("VM") from the resulting coke. The coking process is highly dependent on the oven design, the type of coal, and the conversion temperature used. Typically, ovens are adjusted during the coking process so that each charge of coal is coked out in approximately the same amount of time. Once the coal is "coked out" or fully coked, the coke is removed from the oven and quenched with water to cool it below its ignition temperature. Alternatively, the coke is dry quenched with an inert gas. The quenching operation must also be carefully controlled so that the coke does not absorb too much moisture. Once it is quenched, the coke is screened and loaded into rail cars or trucks for shipment.
Because coal is fed into hot ovens, much of the coal feeding process is automated. In slot-type or vertical ovens, the coal is typically charged through slots or openings in the top of the ovens. Such ovens tend to be tall and narrow. Horizontal non-recovery or heat recovery type coking ovens are also used to produce coke. In the non-recovery or heat recovery type coking ovens, conveyors are used to convey the coal particles horizontally into the ovens to provide an elongate bed of coal.
As the source of coal suitable for forming metallurgical coal ("coking coal") has decreased, attempts have been made to blend weak or lower quality coals ("non-coking coal") with coking coals to provide a suitable coal charge for the ovens. One way to combine non-coking and coking coals is to use compacted or stamp-charged coal. The coal may be compacted before or after it is in the oven. In some embodiments, a mixture of non-coking and coking coals is compacted to greater than 50 pounds per cubic foot in order to use non-coking coal in the coke making process. As the percentage of non-coking coal in the coal mixture is increased, higher levels of coal compaction are required (e.g., up to about 65 to 75 pounds per cubic foot). Commercially, coal is typically compacted to about 1.15 to 1.2 specific gravity (sg) or about 70-75 pounds per cubic foot.
Horizontal Heat Recovery ("HHR") ovens have a unique environmental advantage over chemical byproduct ovens based upon the relative operating atmospheric pressure conditions inside HHR ovens. HHR ovens operate under negative pressure, whereas chemical byproduct ovens operate at a slightly positive atmospheric pressure. Both oven types are typically constructed of refractory bricks and other materials in which creating a substantially airtight environment can be a challenge because small cracks can form in these structures during day-to-day operation. Chemical byproduct ovens are kept at a positive pressure to avoid oxidizing recoverable products and overheating the ovens. Conversely, HHR ovens are kept at a negative pressure, drawing in air from outside the oven to oxidize the coal's VM and to release the heat of combustion within the oven. It is important to minimize the loss of volatile gases to the environment, so the combination of positive atmospheric conditions and small openings or cracks in chemical byproduct ovens allow raw coke oven gas ("COG") and hazardous pollutants to leak into the atmosphere. Conversely, the negative atmospheric conditions and small openings or cracks in the HHR ovens or locations elsewhere in the coke plant simply allow additional air to be drawn into the oven or other locations in the coke plant so that the negative atmospheric conditions resist the loss of COG to the atmosphere.
HHR ovens have traditionally been unable to turn down their operation (e.g., their coke production) significantly below their designed capacity without potentially damaging the ovens. This restraint is linked to temperature limitations in the ovens. More specifically, traditional HHR ovens are at least partially made of silica brick. When a silica oven is built, burnable spacers are placed between the bricks in the oven crown to allow for brick expansion. Once the oven is heated, the spacers burn away and the bricks expand into adjacency. Once HHR silica brick ovens are heated, they are never allowed to drop below the silica brick thermally-volume-stable temperature, the temperature above which silica is generally volume-stable (i.e., does not expand or contract). If the bricks drop below this temperature, the bricks start to contract. Since the spacers have burned out, a traditional crown can contract up to several inches upon cooling. This is potentially enough movement for the crown bricks to start to shift and potentially collapse. Therefore, enough heat must be maintained in the ovens to keep the bricks above the thermally-volume-stable temperature. This is the reason why it has been stated that a HHR oven can never be turned off. Because the ovens cannot be significantly turned down, during periods of low steel and coke demand, coke production must be sustained. Further, it can be difficult to perform maintenance on heated HHR ovens. Other portions of the coke oven system can suffer from similar thermal and/or structural limitations. For example, the crown of a sole flue running under the oven floor can collapse or otherwise suffer from heaving of the oven floor, ground settling, thermal or structural cycling, or other fatigue. These stresses can cause bricks in the sole flue to shift and drop out.

Horizontal heat recovery coke ovens having monolith crowns


A method for manufacturing a solid state imaging device includes steps of forming a photodiode layer buried in a semiconductor substrate by ion injection and of forming a shielding layer buried in the photodiode layer by ion injection. At least in the ion injection process in the step of forming the shielding layer, an ion injection pause period is provided at least one time during whole ion injection step. According to the method, crystal defects are prevented from generating even if ion injection is performed with high energy, thereby suppressing dark current without complexity in manufacturing process.

The present invention relates to a method for manufacturing a solid state imaging device and, in particular, to a method for manufacturing a photodiode layer and a shielding layer formed on the photodiode layer in a solid state imaging device.
In a photoelectric conversion element formed in the solid state imaging device, for example, a P-type impurity diffusion region is formed at a surface region of an N-type semiconductor substrate and a PN junction is formed at a boundary between these regions. The PN junction functions as a light receiving element which performs photoelectric conversion. On the P-type impurity diffusion region, an N+-type impurity diffusion region is formed. The N+-type impurity diffusion region functions as a shielding layer for protecting the P-type impurity diffusion region from incorporation of any other substance or from thermal energy in a manufacturing process. On the N-type semiconductor substrate formed with the P-type impurity diffusion region and the N+-type impurity diffusion region, an oxide film serving as an insulating film is formed on the whole surface thereof. On the oxide film, there is provided a gate electrode for transferring a signal charge produced by the photoelectric conversion element to a signal charge transfer section.
In forming the photoelectric conversion element for the solid state imaging device, conventionally, a shielding layer is formed by injecting an ion to be an impurity with high ion injection energy at a time. However, an energy range used for ion injection in forming the shielding layer, which is an impurity diffusion region, is much larger than the binding energy of atoms forming a crystal of a semiconductor substrate and therefore the atoms brought into collision with an incident ion are plastically deformed and are cut off from lattice points, thus generating crystal defect. The crystal defect caused by the plastic deformation weakens binding energy between lattices of semiconductor atoms and an energy level is formed in the energy level within a forbidden band where no crystal failure exists. Accordingly, a band gap becomes narrow and electrons move from a valence electron band to a conductive band in the forbidden band, thereby causing a dark current.
Generally, there has been used a method for recovering the crystal defect by annealing a semiconductor substrate which has undergone ion injection, however, a heavy metal trap during this process makes an energy level in the forbidden band, which causes a dark current.
For a solution of such a problem with ion injection process, there has been known a method for preventing crystal defect from generating even when high energy ion injection is performed.
Specifically, Japanese Patent Application Laid-Open No. 2007-109818 has disclosed that in forming an impurity diffusion layer, ion injection to the vicinity of a semiconductor substrate surface is performed with injection energy of at least 100 keV and at most 300 keV, using an ion having approximately same atomic radius as that of an element used for the substrate and, on the contrary, ion injection to a deep section of the semiconductor substrate is performed with injection energy of at least 300 keV and at most 4,000 keV, using an ion having approximately same mass as that of an element used for the substrate.
However, such a process requires use of different types of ions for forming the same impurity diffusion region, which causes a problem of complexity in a manufacturing process.
As described above, in a conventional process for forming an impurity diffusion layer, crystal defect occurs because ion injection is performed with high energy and hence dark current is generated. As means for solving the foregoing problems, there is a method for forming the same impurity diffusion region using different ions, however, this method has a problem of complexity in manufacturing process.


A vehicle body structure includes a rear seat, a forward shelf and an aft shelf. The forward shelf is movable between first and second retention locations and the aft shelf is movable between horizontal and vertical retention locations defined by side wall structures. The second retention location is above the first retention location. In the second retention location the forward shelf is located proximate an upper end of the upright seatback. With the aft shelf in the horizontal retention location and the forward shelf in the first retention location, the forward shelf and the aft shelf are co-planar. With the seatback upright, the aft shelf in the vertical retention location and the forward shelf in the second retention location, the back surface of the seatback, the forward shelf and the aft shelf define an enclosed storage space.

1. Field of the Invention
The present invention generally relates to a vehicle body structure that defines a vehicle cargo area. More specifically, the present invention relates to vehicle body structure that includes a plurality of shelf supporting surfaces with a forward shelf positioned at any one of a plurality of locations within the vehicle cargo area and an aft shelf positionable at any one of a plurality of locations within the vehicle cargo area.
2. Background Information
A new passenger vehicle typically includes a cargo area that can receive a variety of cargo. Most cargo areas typically include a deck surface and an optional cover in order to conceal any cargo related objects placed on the deck surface.


An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

The present invention relates to semiconductor circuit devices implemented by integration of a large number of MIS transistors, and in particular relates to measures to reduce variations in transistor characteristics.
In recent years, an LSI (Large Scale Integration), as typified by a microprocessor, has generally been implemented by combining a large number of units each of which has a basic function and is called a cell. In each cell, numerous elements such as MIS transistors, capacitors and resistors are provided. As the performance and packing density of an LSI are increased, the circuit design for cells that determine the performance of an LSI is becoming very important. Furthermore, in carrying out the circuit design for cells with high precision, a CAD (Computer Aided Design) tool plays an extremely important role.
As a CAD tool deeply concerned in design accuracy, a circuit simulator is known. A circuit simulator is used to carry out circuit simulation for cells and an LSI that have been designed. To be more specific, using a circuit simulator, conceivable circuit operations of the cells and LSI that are to be presumably fabricated according to the design are simulated based on a netlist including pieces of information concerning connections between associated elements such as transistors, capacitors and resistors, and pieces of information concerning characteristics of the elements such as transistor sizes, capacitance values and resistance values. For example, such a netlist can be extracted from mask layouts of designed cells by using a circuit extractor. As for pieces of information concerning transistor characteristics, in order to precisely reproduce complicated electrical characteristics of transistors in a circuit simulator, numerous expressions representing electrical characteristics (hereinafter, called "transistor model") are now being developed. Besides, in order to reproduce a desired transistor characteristic using a transistor model, model parameters included in the transistor model must be optimized in accordance with the desired transistor characteristic (hereinafter, simply called "model parameter extraction").
Described below are a layout of a cell provided in a conventional semiconductor circuit device and a transistor model used in designing a conventional cell.
First, the cell layout will be described by using a cell layout shown in FIG. 8 as an example.
FIG. 8 is a plan view schematically illustrating an exemplary layout of a conventional cell 100 provided in a part of a semiconductor substrate. The semiconductor substrate is provided with an N-well 102 and a P-well 103 that are adjacent to each other with a well boundary 110 located therebetween. The N-well 102 is provided with first through third PMIS active areas Rtp1 through Rtp3 surrounded by a trench isolation Ris. On the other hand, the P-well 103 is provided with first through third NMIS active areas Rtn1 through Rtn3 surrounded by the trench isolation Ris. Herein, the "PMIS active area" refers to an active area for a P-channel MIS transistor, while the "NMIS active area" refers to an active area for an N-channel MIS transistor. Although three active areas are exemplarily provided in each of the N-well 102 and the P-well 103 in FIG. 8, a considerably large number of active areas are provided in an actual semiconductor circuit device. The first, second and third PMIS active areas Rtp1, Rtp2 and Rtp3 are provided with gates 107 of P-channel transistors. On the other hand, the first, second and third NMIS active areas Rtn1, Rtn2 and RTn3 are provided with gates 109 of N-channel transistors. It should be noted that, like a known transistor, each gate has a so-called "insulated gate structure" formed by a gate insulating film and a gate electrode, although not shown.
The semiconductor substrate is further provided with: an N-type substrate active area 104 through which a power supply voltage is supplied to respective elements in the cell 100; and a P-type substrate active area 105 through which a reference electric potential is supplied to respective elements in the cell 100.
Parts of each active area, located on the sides of each gate, are defined as source/drain regions. Upon application of voltage between the source/drain regions and application of bias to each gate, a channel is formed in a part of each active area, located under each gate, and an electric current flows through the channel.
Since various cells are generally combined in an LSI, a distance between a width YN+ of the N-type substrate active area 104 extending in a Y-direction and a width YP+ of the P-type substrate active area 105 extending in the Y-direction, i.e., a distance Dsell between the N-type substrate active area 104 and the P-type substrate active area 105, is standardized at a common value for each group of cells. Furthermore, a layout rule for the process of forming the cell 100 specifies: a lower limit S1 of a distance between the N-type substrate active area 104 and the first through third PMIS active areas Rtp1 through Rtp3; a lower limit S2 of a distance between the first through third PMIS active areas Rtp1 through Rtp3 and the well boundary 110; a lower limit S3 of a distance between the well boundary 110 and the first through third NMIS active areas Rtn1 through Rtn3; and a lower limit S4 of a distance between the first through third NMIS active areas Rtn1 through Rtn3 and the P-type substrate active area 105. Accordingly, in the Y-direction, the first through third PMIS active areas Rtp1 through Rtp3 can be laid out within a range SP located at a distance of the lower limit S1 or more from the N-type substrate active area 104 and at a distance of the lower limit S2 or more from the well boundary 110. Similarly, in the Y-direction, the first through third NMIS active areas Rtn1 through Rtn3 can be laid out within a range SN located at a distance of the lower limit S3 or more from the well boundary 110 and at a distance of the lower limit S4 or more from the P-type substrate active area 105.
FIG. 9 is a diagram schematically illustrating the structure of a transistor for the description of a conventional transistor model. As shown in FIG. 9, the transistor model includes: an active area Rt surrounded by a trench isolation Ris; a gate electrode 112 straddling the active area Rt to reach the trench isolation Ris at both sides of the active area Rt; source/drain regions 114a and 114b located on the sides of the gate electrode 112 of the active area Rt; and a channel region 113 located under the gate electrode 112 of the active area Rt. As indicated by the hatching in FIG. 9, in the transistor model, the channel region 113 of the transistor is defined by a region at which the active area Rt and the gate electrode 112 are overlapped. In addition, in the transistor model, the current drive capability of the transistor is determined by a width W (channel width) and a length L (channel length) of the channel region 113, an electric resistance of the active area Rt, and a load (not shown) added to the active area Rt, and information concerning the layout around the transistor is not taken into consideration.
The conventional semiconductor circuit device has been designed as described above because the design has been carried out on the assumption that the performance of the semiconductor circuit device is determined by the gate length and gate width of each transistor.
However, from the experiments carried out by the present inventors, it is found that the performance of a semiconductor circuit device provided with the latest miniaturized transistors might vary depending on not only the gate length and gate width of each transistor but also the layout of each active area. That is, even if circuit configurations are alike, the current drive capability of each transistor, for example, might vary depending on the layout, and therefore, the performance of an overall semiconductor circuit device is also affected by the layout. Accordingly, depending on a method for extracting model parameters of a transistor model used in designing the conventional cell 100, the performance of a semiconductor circuit device formed based on the design often falls short of the design goal, and it is difficult to maintain the design accuracy of the semiconductor circuit device at a high level.
A compressive stress applied from a trench isolation to a channel region (which will be hereinafter called a "trench isolation stress") affects transistor characteristics in such a manner that a difference occurs between the performances of transistors having identical gate lengths and gate widths. How a trench isolation stress affects transistor characteristics will be described below. In a channel region of each transistor, a lattice strain occurs due to a trench isolation stress. Therefore, in an N-channel transistor, an effective mobility in a channel portion is decreased, and the performance of the N-type transistor tends to be reduced. In a P-type transistor, an effective mobility is also decreased in a channel portion due to a trench isolation stress applied in a gate width direction.
Suppose that one transistor is provided in one active area and the other transistor is provided in the other active area located adjacent to the one active area. In that case, if a distance between the one transistor and the other active area is varied, in particular, in a channel width direction, the transistors might exhibit different current drive capabilities.
Even if the transistors have identical channel widths and identical channel lengths, a difference occurs between the current drive capabilities of the transistors due to a variation in a distance between the one transistor and the other active area located adjacent to the one active area in which the one transistor is provided. Hereinafter, how this difference occurs will be described in detail with reference to FIG. 10. FIG. 10 is a plan view illustrating the layout for circuit simulation of the conventional semiconductor circuit device.
As shown in FIG. 10, three kinds of P-channel transistors TrpA, TrpB and TrpC have identical channel lengths and identical channel widths Wp. Three kinds of N-channel transistors TrnA, TrnB and TrnC also have identical channel lengths and identical channel widths Wn. A distance DpA between an active area RtpA, in which the transistor TrpA is located, and an N-type substrate active area 104 is equal to a distance DpC between an active area RtpC, in which the transistor TrpC is located, and the N-type substrate active area 104, while the distance DpA is different from a distance DpB between an active area RtpB, in which the transistor TrpB is located, and the N-type substrate active area 104. A distance DpnA between the active area RtpA and an active area RtnA is different from a distance DpnB between the active area RtpB and an active area RtnB. A distance DpnC between the active area RtpC and an active area RtnC is equal to the distance DpnB between the active area RtpB and the active area RtnB. A distance DnA between the active area RtnA and a P-type substrate active area 105 is equal to a distance DnB between the active area RtnB and the P-type substrate active area 105. And a distance DnC between the active area RtnC and the P-type substrate active area 105 is different from the distance DnA and the distance DnB.
In the above-described layout, the characteristics of the transistors TrpA through TrpC and the transistors TrnA through TrnC will be compared.
First, a comparison is made between the characteristic of the P-channel transistor TrpA and that of the P-channel transistor TrpB. The characteristic of the P-channel transistor TrpA facing the N-channel transistor TrnA in a Y-direction is determined by the channel length and the channel width Wp of the P-channel transistor TrpA, the distance DpA and the distance DpnA. The characteristic of the P-channel transistor TrpB facing the N-channel transistor TrnB in the Y-direction is determined by the channel length and the channel width Wp of the P-channel transistor TrpB, the distance DpB and the distance DpnB. The distance DnA between the active area RtnA, in which the N-channel transistor TrnA is located, and the P-type substrate active area 105 is equal to the distance DnB between the active area RtnB, in which the N-channel transistor TrnB is located, and the P-type substrate active area 105. That is, the N-channel transistors TrnA and TrnB are located similarly with respect to the Y-direction in the cell 100. In this layout, the following formulasDpA≠DpBDpnA≠DpnBhold true. In the Y-direction, the distance DpnA between the active area in which the P-channel transistor TrpA is located and another active area located adjacent thereto is different from the distance DpnB between the active area in which the P-channel transistor TrpB is located and another active area located adjacent thereto. Therefore, different trench isolation stresses are applied to the channel regions of the two P-channel transistors TrpA and TrpB. As a result, a difference occurs between the characteristics, e.g., the current drive capabilities, of the two P-channel transistors TrpA and TrpB. Even though the two NMIS active areas facing the two PMIS active areas are located similarly with respect to the Y-direction, the PMIS active areas are located differently with respect to the Y-direction. Therefore, the characteristics, e.g., the current drive capabilities, of the P-channel transistors located in the two PMIS active areas are varied in accordance with the distances between the PMIS active areas and the NMIS active areas in the Y-direction.
Next, a comparison is made between the characteristic of the P-channel transistor TrpA and that of the P-channel transistor TrpC. The characteristic of the P-channel transistor TrpC facing the N-channel transistor TrnC in the Y-direction is determined by the channel length and the channel width Wp of the P-channel transistor TrpC, the distance DpC and the distance DpnC. The distance DpA between the active area RtpA, in which the P-channel transistor TrpA is located, and the N-type substrate active area 104 is equal to the distance DpC between the active area RtpC, in which the P-channel transistor TrpC is located, and the N-type substrate active area 104. That is, the P-channel transistors TrpA and TrpC are located similarly with respect to the Y-direction in the cell 100. Therefore, the following formulaDpA=DpCholds true. However, the following formulaDpnA≠DpnCalso holds true. In the Y-direction, the distance DpnA between the active area in which the P-channel transistor TrpA is located and another active area located adjacent thereto is different from the distance DpnC between the active area in which the P-channel transistor TrpC is located and another active area located adjacent thereto. Therefore, different trench isolation stresses are applied to the channel regions of the two P-channel transistors TrpA and TrpC. As a result, a difference occurs between the characteristics, e.g., the current drive capabilities, of the two P-channel transistors TrpA and TrpC. Even though the two PMIS active areas are located similarly with respect to the Y-direction, the NMIS active areas facing the PMIS active areas are located differently with respect to the Y-direction. Therefore, the characteristics, e.g., the current drive capabilities, of the P-channel transistors located in the two PMIS active areas are varied in accordance with the distances between the PMIS active areas and the NMIS active areas in the Y-direction.
Next, a comparison is made between the characteristic of the P-channel transistor TrpB and that of the P-channel transistor TrpC. The distance DpnB between the active area RtpB, in which the P-channel transistor TrpB is located, and the active area RtnB, in which the N-channel transistor TrnB is located, is equal to the distance DpnC between the active area RtpC, in which the P-channel transistor TrpC is located, and the active area RtnC, in which the N-channel transistor TrnC is located. However, the distance DpB between the active area RtpB, in which the P-channel transistor TrpB is located, and the N-type substrate active area 104 is different from the distance DpC between the active area RtpC, in which the P-channel transistor TrpC is located, and the N-type substrate active area 104. Since the following formulaDpB≠DpCholds true, different trench isolation stresses are applied from the N-type substrate active area 104 to the P-channel transistors TrpB and TrpC, resulting in a difference between the characteristics of the transistors. Even though distances between the PMIS active areas, in which the two P-channel transistors are located, and the NMIS active areas facing the PMIS active areas in the Y-direction are identical, the characteristics, e.g., the current drive capabilities, of the P-channel transistors are varied if the active areas, in which the two P-channel transistors are provided, are located differently with respect to the Y-direction.
Although the description of the characteristic variations of the N-channel transistors are omitted, the characteristic variations of the N-channel transistors are similar to those of the P-channel transistors in that the greater the trench isolation stress in a channel region, the lower the current drive capability.
As described above, it can be understood that even if the conventional semiconductor circuit device is designed to allow the transistors to have identical channel lengths and identical channel widths, the characteristics of the transistors having identical channel widths in the cell 100 are considerably varied due to the trench isolation stress, thus making it difficult to realize the optimum LSI design.
Furthermore, in a method for extracting model parameters of a conventional transistor model, transistor characteristic variations due to the trench isolation stress cannot be taken into consideration in the transistor model itself, and therefore, the transistor characteristic variations in each cell cannot be reproduced, which increases errors in circuit simulation for each cell.

Semiconductor circuit device and circuit simulation method for the same

Matsushita Electric Industrial Co., Ltd.


Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

Thermistors are used in a wide variety of applications, including electronics, battery systems, environmental control, petroleum exploration and medical monitoring. If a resistance value of a thermistor differs from a nominal design value due to, e.g. manufacturing variation, a temperature determined from the resistance may not accurately reflect the true temperature of the environment in which the thermistor is located.

Trimmable silicon-based thermistor with reduced stress dependence


According to this invention, allergenicity in an indoor space is reduced by denaturing allergens in allergen reservoirs that are capable of producing respiratory or skin reactions and physically removing the allergens from the allergen reservoirs in the indoor space. The allergen reservoirs may also be treated with pesticides and fungicides/fungistats to prevent reinfestation of house dust mites, molds and cockroaches.

1. Field of the Invention
This invention relates to medically sound procedures for reduction in environmental allergenicity due to certain airborne allergens known to produce asthma, allergic rhinitis and atopic eczema in both humans and animals. Specifically, allergens derived from house dust mites, certain molds, cockroaches, cats and dogs are removed from indoor living spaces to provide sanctuaries for asthma sufferers.
2. Review of Related Art
Asthmatic bronchitis (asthma), allergic rhinitis (hay fever), and atopic eczema are immunologic reactions which, in the majority of cases, are triggered by one or more allergens from five primary sources: cat dander, dog dander, mold spores, cockroach fecal pellets and house dust mite fecal pellets. All of the primary asthmatic allergens from these five sources are protein in nature, typically glycoprotein. These allergens accumulate on various indoor surfaces and in allergen reservoirs, such as carpets, upholstery, mattresses and pillows. The presence of these allergens in any interior space can make that space hazardous for an asthmatic patient.
Of the primary allergens, house dust mite (HDM) accounts for 50-55% of the asthmatic's problems. HDMs proliferate indoors when temperature, humidity and the presence of sloughed epithelial cells (the mite's primary food source) are adequate for their survival and reproduction. Adult HDMs produce 20-30 fecal pellets per day per mite over a life span of 2½ months. Each fecal pellet is heavily inoculated during its midgut formation with proteins (principally digestive enzymes) capable of evoking an immune response.
HDM allergenic proteins have been identified for mites of the genus Dermatophagoides, and the proteins fall mainly into two immunological groups: Der I (Der pI and Der fI) and Der II (Der pII and Der fII). The primary sequence of HDM allergens has been disclosed (see a series of U.S. patents and also reviews by Thomas, et al. (1998), "House-dust-mite allergens," Allergy, 1998 September; 53(9):821-32; Platts-Mills TA, et al. (1997), "Indoor allergens and asthma: report of the Third International Workshop," J Allergy Clin Immunol 1997 December; 100(6 Pt 1):S2-24; and Chua Ky., et al. (1996), "Analysis of sequence polymorphism of a major mite allergen, Der p 2," Clin Exp Allergy. 1996 July; 26(7):829-37). HDMs are primarily found in indoor textiles (carpet, upholstery, mattresses and pillows) where their population can become enormous—well into the millions. Mechanical disturbance can release the proteins from dried fecal pellets into the air, producing an allergenic cloud that will resettle onto textile surfaces over time.
Mold spores account for 10-15% of asthmatic reactions, and four mold genera account for nearly all of the allergenic spores. These genera are: Alternaria, Cladiosporium, Aspergillus, and Penicillium, with Alternaria accounting for about 80% of the mold spore responses of asthmatics. Cat dander accounts for 10-15%, cockroaches account for 5-10%, and dog dander accounts for 5-10% of asthmatic reactions.
HDM, cockroach and mold allergens tend to be larger and heavier; therefore, they often settle on textile-covered surfaces, such as carpets and upholstery. Even after being disrupted, such as when a person walks on a carpet or sits on a sofa, the allergens will only rise up a few feet in the air (e.g., about three feet) and quickly settle again.
Cat and dog allergens, on the other hand, tend to be smaller and lighter; thus, they often "float" in the air for up to six months. Eventually, those allergens will attach to a surface, such as a textile-covered surface, wall or ceiling. However, once they are disrupted, the allergens will again "float" in the air for a lengthy period of time before settling.
Physicians currently address the disorders produced by allergens with symptomatic medicinal approaches, desensitization methods and preventive measures such as textile removal from the home, air filters, dehumidifiers, mattress covers and the like, yet the problem still exists. Ablative HDM chemicals currently in use include short term insecticides or denaturants that reduce the allergenicity of protein allergens, such as the proteins in HDM fecal pellets. Insecticides that have been tested include benzyl benzoate (U.S. Pat. Nos. 5,916,917; 6,107,341; and 6,117,440) phenyl salicylate, the organophosphate, pirimiphos methyl (Mitchell, et al., 1985, "Reduction of house dust mite allergen levels in the home: uses of the acaricide, pirimiphos methyl," Clin. Allergy, 15:234), and synthetic pyrethroids such as permethrin (U.S. Pat. Nos. 5,843,981; 5,916,580; and 5,965,602; Glass, et al., "Evaluation of the acaricide permethrin against all stages of the American house dust mite Dermatophagoides farinae Hughes (Pyroglyphidae)," in Mitchell, et al., eds., Acarology IX Proceedings, Columbus, Ohio Biological Survey, 1997, pp. 693-695). International Publication No. WO 98/30236 discloses a pesticide using protease enzymes to kill insects for the purpose of decreasing or eliminating the incidence of allergic reaction to dust, but this reference does not address allergic reactions to the enzyme. Tannic acid has been used to denature HDM fecal pellets short term (Green, "Abolition of allergens by tannic acid," Lancet, 2:160 1984; U.S. Pat. No. 4,977,142), and polyphenol denaturants have been used in combination with insecticides (Green, et al., 1989, "Reduction of house dust mites and mite allergens: Effects of spraying carpets and blankets with Allersearch DMS, an acaricide combined with an allergen reducing agent," Clin. Exp. Allergy, 19:203; U.S. Pat. No. 4,806,526).
Either the insecticide treatments or the chemical denaturants must be reapplied at 2-3 month intervals for any hope of efficacy. These products are available over-the-counter, and are subject to the variability existing among do-it-yourselfers who apply such products. These products are also displaced from textiles during vacuuming and become air-borne, are inhaled, and can serve as a major irritant to asthmatics or hay fever sufferers. Therefore, there remains a need for improved methods of reducing allergenicity in indoor spaces to alleviate the suffering of asthmatics and hay fever sufferers.

Method for reducing allergencity in indoor spaces


The present invention pertains to a method for efficiently determining the validity of terminal location information in a minimization of drive test (MDT) measurement report procedure in a 3GPP system. The method for reporting channel measurement information of a terminal in a wireless communication system according to the present invention comprises: a reception step of receiving setup information for wireless channel measurement from a base station; an acquisition step of acquiring wireless channel information, location information of the terminal, and time information when the location information is collected according to the setup information; a determination step of determining whether the location information of the terminal is valid; and a transmission step of generating and transmitting channel measurement information including the time information to the base station when valid.

1. Technical Field
The present disclosure relates to a channel measurement information generation and report method and apparatus of a terminal in a wireless communication system and, in particular, to a Minimization of Drive Test (MDT) measurement method and apparatus of a terminal in the connected mode in the 3rd Generation Partnership Project (3GPP) system.
2. Background Art
The mobile communication system has been developed for the user to communicate on the move. With the rapid advance of technologies, the mobile communication system has evolved to the level capable of providing high speed data communication service as well as voice telephony service. Recently, as one of the next generation mobile communication system, Long Term Evolution-Advanced (LTE-A) is on the standardization by the 3rd Generation Partnership Project (3GPP). LTE-A is expected to be ratified aims at very high peak data rate as compared to the legacy technology and its standard is expected to be ratified around late 2010.
With the evolvement of the 3GPP standard, many discussions are being conducted for optimizing the radio network in addition to the effort for increasing data rate. In the initial radio network configuration or optimization stage, a base station or a base station controller should collect radio environment information related to its own cell coverage, and this process is called Drive Test.
Since the conventional drive test is carried out by an operator manually with the test apparatus equipped on a vehicle on the move. The measurement result is analyzed for use in configuration of the system parameters of the base stations and base station controllers. However, conventional derive tests are time consuming and labor intensive to achieve radio network optimization.

Method and apparatus for generating and reporting channel measurement information in wireless communication system


To provide a crystallized glass substrate including a surface with a compressive stress layer, in which a stress depth DOLzero of the compressive stress layer, at which the compressive stress is 0 MPa, is 45 to 200 μm, a compressive stress CS on an outermost surface of the compressive stress layer is 400 to 1400 MPa, and CS×DOLzero, which is a product of the compressive stress CS on the outermost surface and the stress depth DOLzero (μm), is 4.8×104 or more.

A cover glass for protecting a display is used in a portable electronic device such as a smartphone or a tablet PC. A protector for protecting a lens is also used in an in-vehicle optical device. In recent years, there is a demand for a use in a housing or the like serving as an exterior of an electronic device. There is an increasing demand for a hard and near-unbreakable material so that these devices can withstand more rigorous use.
Conventionally, there is known chemical strengthening as a method for strengthening a glass substrate. For example, Patent Document 1 discloses a crystallized glass substrate for an information recording medium. However, when this crystallized glass substrate is chemically strengthened, it is not possible to achieve a sufficient compressive stress value.

This patent is subject to a terminal disclaimer.


A red-eye phenomenon preventing device includes a light emitting part for flash photography, a light emitting part for preventing the red-eye phenomenon, a reflection shade arranged to surround the light emitting part for flash photography and the light emitting part for preventing the red-eye phenomenon, and a protector disposed in front of the light emitting part for flash photography and the light emitting part for preventing the red-eye phenomenon.

1. Field of the Invention
This invention relates to a device for preventing a red-eye phenomenon occurring in flash photography.
2. Description of the Related Art
Color photographs of persons sometimes show red eyes. This is called a red-eye phenomenon. This phenomenon results from the retinal blood vessels taken in the photograph as the pupil of a person is wide open in taking a picture in a dark place with the aid of an auxiliary light such as a flash light.
To prevent the red-eye phenomenon, it has been proposed in Japanese Patent Publication No. SHO 58-48088 to carry out flash photography after making the open pupil smaller by turning on a preliminary illumination lamp prior to the emission of flash light.
The preliminary illumination by a lamp must have a relatively large degree of luminance for closing the human pupil. The sufficient degree of luminance for this purpose is hardly obtainable from the use of a small lamp but rather the use of a large lamp gives sufficient luminance. However, it not only causes a cost increase but is disadvantageous in respect of practical arrangement. A method of raising the luminance of a small lamp by condensing its light with a reflection mirror is conceivable. However, this method increases not only the cost but also the size of the camera.