A transport platform structure which is configured for vehicle roll on/roll off has a deck having a downwardly angled sloped portion at at least one end to produce an end-edge at an end of the platform. This end edge is dimensioned to have a vertical height configured to allow wheeled vehicles to roll from a surface on which the platform is disposed, against and up over the end-edge, and onto the deck without the interposition of structures movable with respect to the deck.

1. Field of the Invention
The present invention relates generally to transport platforms for transporting cargo on container ships, and more specifically to open transport platforms which are configured for transporting oversized cargo such as vehicles/equipment and the like that cannot fit onto currently available transport platforms, and which are configured to permit vehicles to roll on and off without the need of additional structures such as ramps and the like.
2. Description of the Related Art
Open transport platforms, which have been used to transport vehicles or the like, have usually, due to their configuration and limited structural strength, been left to last during the loading process so that they can be placed on top of the uppermost containers on the deck of the container ship. That is to say, due to the limited ability of the platforms to bear large vertically acting loads such as those generated by the placement of a fully laden container on top thereof, the platforms have had to be disposed at the very tops of the container stacks. This, of course, severely limits both their utility and the number of platforms which can be carried on any one vessel.
A further drawback that open transport platforms suffer from is that, in order to have sufficient structural strength and durability, the platform and deck are relatively thick. Therefore, the ends of the platforms have a substantial vertical dimension and resemble a small vertically extending wall which juts up above the surface on which the platform is resting. The height of this end wall which can be about 24″ for example, tends to be such that only wheels having large diameter can readily roll up and over the end of the platform, and then later roll off the end of the platform without noticeable impact. Accordingly, it is therefore usually necessary to either use cranes to lift the cargo into place, or provide ancillary pieces of equipment such a ramp or ramps in order to allow wheeled vehicles to smoothly roll on and off the end of the platform during unloading/unloading.
This, of course, reduces the utility of the platform in that additional/ancillary equipment which is in itself heavy must either be carried with the platform, adding to its dead weight and complexity, or alternatively some means for moving the ancillary equipment about, such as fork lift of the like, must also be provided at both the site where the vehicles are loaded and the site wherein the vehicles are unloaded. In the case of a military operation (for example), it is often such that conditions are less than favorable and in the case of war or the like, the availability of ramps and fork lifts cannot be guaranteed and the daunting task of manually moving such heavy pieces of equipment from platform to platform may be too much should sufficient man-power (for example) not be available.
In addition to the above shortcoming, open transport platforms have suffered from the drawback that the holds of modern container ships are usually constructed to receive predetermined sized containers which are usually 40′×8′ long ISO (International Standards Organization) containers. These holds have bulkheads at each end which extend laterally from port to starboard. These bulkheads are each provided with vertically extending cell guides that are sized to permit the 40′×8′ ISO sized containers to be slid down between T-shaped guide members which define the cell guides, and thus be securely held at each end thereby.
With this construction, the containers can be secured against both rolling and pitching of the container ship. That is to say, disposition of 40′ containers between the bulkheads, which are spaced by about 40′, prevents fore-aft movement of the containers due to pitching of the vessel during transit, while the engagement of the ends of the containers with the T-guides prevents lateral movement (port/starboard movement) due to rolling of the vessel. It should be noted that it is also possible with this type of arrangement to dispose two 20′ ISO containers in an end-to-end arrangement, between the bulkheads.
After a hold is filled with the above-mentioned types of ISO containers, a hatch is placed over the top to close the hold. Containers are then stacked on top of the hatches.
However, it has been extremely difficult, if not impossible, to dispose anything but the 40′×8′ ISO containers in the holds, and attempts to dispose transport platforms below deck have not met with success. Thus, storage in such holds has been limited to the above mentioned 40′×8′ ISO containers which are dimensioned to fit in the cell guides. This means that off-sized containers or platforms, which are either wider or narrower than the width of the cell guides, cannot be secured below deck in the holds and are relegated to possible disposition above deck.
As will be readily understood, in many instances it is highly desirable to store cargo which is being carried on an open transport platform, below deck so as to enclose same and thus limit the amount of exposure to the elements during shipping.

Roll on/roll off ramp-deck transport platform


According to one embodiment, a non-volatile memory device includes a base layer, a first stacked unit and a second stacked unit disposed above the base layer and arranged in parallel to each other and spaced apart from each other in a first direction, in a plane parallel to the base layer, a first semiconductor layer penetrating the first stacked unit, a second semiconductor layer penetrating in the second stacked unit, the first memory film disposed between the first semiconductor layer and the first stacked unit, and a connecting portion disposed between the base layer and the first stacked unit and between the base layer and the second stacked unit and electrically connecting the first semiconductor layer and the second semiconductor layer. An end portion of the first semiconductor layer is positioned between the connecting portion and the base layer.

A non-volatile memory device, such as an NAND-type flash memory, is manufactured using semiconductor device manufacturing processes. Enlarging the capacity, reducing the power consumption, and reducing the cost of the non-volatile memory device are achieved by employing known miniaturization technology utilized in semiconductor device manufacturing. On the other hand, development of a memory cell array having a three-dimensional structure is necessary for further enlargement of the capacity of the non-volatile memory device. However, where a three dimensional memory cell array is formed, operation of the memory cell array may become unstable when the degree of miniaturization of the memory cell array is increased.


A voltage detecting device includes a voltage detecting circuit configured to detect voltages of a plurality of battery cells constituting a battery; a plurality of voltage detecting lines connecting the respective battery cells to the voltage detecting circuit; discharging circuits connecting the respective voltage detecting lines to a ground, and discharging the battery cells in an overcharged state; a power adjusting section adjusting power of the battery, and supplying the voltage detecting circuit with the adjusted power as driving power; the voltage detecting circuit detecting the voltages of the respective battery cells via the voltage detecting lines; and an overvoltage protecting circuit protecting the voltage detecting circuit from voltage equal to or higher than a predetermined threshold value, the voltage being generated in the voltage detecting lines, the discharging circuits, and the power adjusting section.

A battery module that can prevent an overvoltage from being applied to a voltage measuring section when a disconnection occurs between battery cells is disclosed in Japanese Patent Laid-Open No. 2013-121246 ("JP '246"), which describes a battery module includes a plurality of battery cells connected in series with each other; a voltage measuring section measuring respective voltages of the plurality of battery cells; voltage measuring lines establishing connections between the voltage measuring section and the battery cells; overcurrent protecting circuits inserted in the voltage measuring lines, each of the overcurrent protecting circuits being formed by connecting an overcurrent interrupting element and an overcurrent preventing element in series with each other; and reverse voltage protective diodes each having a cathode connected in parallel with a corresponding battery cell via an overcurrent interrupting element on a positive electrode side of the battery cell and having an anode connected in parallel with the corresponding battery cell via an overcurrent interrupting element on a negative electrode side of the battery cell. The overcurrent interrupting elements are formed by a fuse.


A lens holder (20) used in a digital camera includes a first housing (21) and a second housing (22) complementary thereto. Each housing includes a joining edge (203,204) and a plurality of screw threads (201,202) on an outside surface of the housings. A plurality of mounting holes (211) and a plurality of mounting pins (221) are formed on the joining edges of the housings. A plurality of partition platforms (213,223) is formed inside each housing to define a plurality of rooms for accommodating and securing a plurality of lenses. Each partition platform has a semi-circular opening (214,224) therethrough. In assembly, a plurality of lenses is inserted into the rooms and secured therein. Then, the second housing is assembled with the first housing with the locking pins inserting into the mounting holes of the joining edges. A lens holder used in a digital camera is thus formed.

1. Field of the Invention
The present invention generally relates to digital cameras, and more particularly to a lens holder used in a digital camera.
2. Prior Art
Multifunctional portable personal communication devices, such as mobile phones with cameras, are very popular in current days, since they provide users not only with voice communications but also image communications, or can at least provide the users with picture-taking functions.
Existing mobile phones with digital cameras are classified into two types, according to the way the camera is assembled with the mobile phone. One type is a mobile phone with a build-in camera; the other is a mobile phone with an externally pluggable camera. Referring to FIG. 5, a lens holder 10 used in a digital camera built into a mobile phone (not shown) comprises a housing 11, a plurality of rubber cushions 13, and a top cover 14. The housing 11 is cylindrical in shape and is used to receive the plurality of rubber cushions 13 and a plurality of lenseses 12. Each rubber cushion 13 has an annular shape. In assembly, the plurality of rubber cushions 13 and the plurality of lenseses 12 are arranged in the housing 11 in an alternating fashion. Each two of the plurality of rubber cushions 13 defines a space therebetween for receiving one of the plurality of lenseses 12, and each rubber cushion 13 has a thickness that defines a desired distance between the lenses 12 to each of its sides. Finally, the top cover 14 is assembled with the housing 11 to secure the plurality of lenseses 12 therebetween.
However, during assembly, the plurality of lenses 12 and the plurality of rubber cushions 13 are alternately tightly fit in turn into the housing 11 through an opening thereof, which makes the assembly inconvenient. More seriously, the lenses 12 are prone to be tilt due to improper manipulation or due to the flexibility of the rubber cushions 13. As a result, the optical axes of the plurality of lenses 12 may become misaligned.


Downhole mechanical or electrical equipment that possess, induce or supply large electromagnetic interference or magnetic fields are sometimes placed in subterranean wells, usually as part of or attached to wellbore tubulars. These magnetic fields can interfere with the efficient operation of some electronic, gyroscopic or magnetic well tools that pass by, through, near or adjacent to such downhole equipment. In general, a subterranean magnetic field protective shield apparatus is provided which reduces or substantially eliminates this magnetic field interference or enhances the operation of, or minimizes damage to, sensitive electronic or magnetic well tools. Such a subterranean magnetic field protective shield enhances the operation of other tools and protects other devices from adverse effects of magnetic fields stronger than the earth's magnetic field intensity.

It is sometimes desirable to place into a subterranean wellbore, temporarily or permanently, mechanical or electrical downhole equipment which possesses, induces or provides a magnetic field with a stronger intensity than that of the earth's natural magnetic field. Examples of this equipment include, but are not limited to, MRI tools, solenoid actuators, and magnetic couplings. Magnetic couplings might be used to operate downhole safety valves, sliding sleeves, adjustable chokes, and pumps.
It is also sometimes desirable to use certain magnetic or electric downhole tools which may be affected or whose operation may be impeded by the presence of strong magnetic or electric fields. Examples of such downhole tools include but are not limited to subterranean logging devices, flow meters, formation evaluation tools, directional drilling equipment, directional or other survey instruments, coils, gyroscopic apparatus, MRI tools, photo-multipliers, casing or tubing collar locators, information gathering and/or transmitting devices and various electrical tools.
An objective of this invention is to reduce or minimize the interference of subterranean electric or magnetic fields with the efficient or effective operation of downhole tools.

Subterranean magnetic field protective shield


In a data processing system having a plurality of commander nodes and at least one resource node interconnected by a system bus, a bus arbitration technique determines which commander node is to gain control of the system bus to access the resource node. The bus arbitration technique assigns priority levels to all commander nodes, with at least one commander node receiving more than one priority level. Each priority level has an associated signal path. During each arbitration, each contending commander node can activate or assert the signal path associated with its priority level, and the commander node having more than one priority level can assert the signal path associated with any one of its priority levels. All commander nodes monitor all the signal paths to determine the identity of the contending commander node that asserted the signal path associated with the highest priority level among those that were asserted, and, thus, the contending commander node that "won" the arbitration.

A. Multiprocessor Computer
Typically, a multiprocessor data processing system has a number of devices, including multiple (i.e., two or more) processors, interconnected by a system bus for communication. The devices on the system bus can also include a number of memory modules, and one or more input/output (I/O) units, such as disk, tape or I/O bridge controllers. Each memory module includes at least one independently accessible memory bank. Depending on system configuration, a number of the I/O units can be connected directly to the system bus, and the rest can be connected to one or more I/O buses, which connect to the system bus via an I/O interface or adapter.
Essentially, the memory banks serve as shared resources for the processors and I/O units, and therefore can be called "resource nodes" on the system bus. The processors and I/O units can be called "commander nodes." The commander nodes initiate requests to gain control of the system bus to access the memory banks. Essentially, the system bus can be viewed as a shared resource used by the commander nodes to access the resource nodes. Upon gaining control of the system bus, the commander nodes transmit commands (e.g., read or write) over the system bus, to which the resource nodes respond.
In a known data processing system, the commander nodes transmit the requests and commands in synchronization with system bus cycles. The bus cycles specify periodically occurring times for transmitting requests, for transmitting commands and for transmitting data over the system bus. During the system bus cycles, the times when requests can be transmitted are called "request cycles." Each commander node desiring bus access transmits a request during one of the request cycles, typically during the next-occurring request cycle.

Dynamic arbitration for system bus control in multiprocessor data processing system


Disclosed herein is an electrode for capacitive deionization device including an active material, a waterborne polyurethane, and a conducting agent. Disclosed herein too is a method of manufacturing the electrode and a capacitive deionization device employing the electrode. The waterborne polyurethane is a product of reaction of a polyurethane prepolymer prepared by reacting a polyol, a diisocyanate-based compound, and a dispersing agent, with a neutralizing agent and a chain extending agent.

This disclosure relates to an electrode for capacitive deionization device, and too a method of manufacturing the electrode and a capacitive deionization device that comprises the electrode.
Recently, rapid industrialization has inflicted damage to the environment and has induced climatic change. Thus, clean water has been drying up, while demand for purified water has been increasing due to increases in human population and improvements in the standard of living. In addition, a lot of attention has been paid to develop a method of purifying water.
Water softener, which converts hard water to soft water acts to reduce the amount of cations in water to less than a predetermined level. In general, ion exchange resins have been used in water softening systems to soften water. In such systems, cations (such as bivalent ions) present in the hard water are removed by being exchanged with Na+ ions adsorbed to the ion exchange resin. The Na+ ions are thus released into the water while the bivalent ions are adsorbed into the ion exchange resin. When the ion exchange resin is saturated with the bivalent ions and the capability of the resin for further exchange of ions is reduced, the resin is restored through a reversible reaction by bringing NaCl into contact with it. The bivalent ions adsorbed to the resin are desorbed through a concentration differential by contacting it with a large amount of NaCl, and Na+ is adsorbed to the ion exchange resin again. The ion exchange resin is widely used in water softener systems and is easily available.
However, the ion exchange resin has a serious drawback with regard to secondary waste, since about 100 pounds of NaCl is required to restore 1 pound of the ion exchange resin. In addition, water generated during the regeneration of the ion exchange resin contains a large amount of Cl− ions, thereby being harmful to plants. Accordingly, damage to crops by the waste water containing Cl− ions is often reported in farms across the United States, and the costs for treating Na+ ions is therefore increasing. Thus, the development of technology replacing such ion exchange resins is urgently required to inhibit such environmental damage.
Capacitive Deionization (CDI) is a system in which ionic materials in a medium are adsorbed on the surface of an electrode and then removed by applying a voltage to a nano porous carbon electrode so as to provide the electrode with a polarity. The adsorbed ionic materials are discharged with water by applying an inverse voltage to the electrode during its regeneration. This system has similar characteristics to conventional supercapacitors. CDI is advantageous since chemicals are not required for regeneration, and ion exchange resins, expensive filters or membranes are not required. Elements of hard water and harmful ions are removed and capacitance increases in CDI.
In CDI, when a direct current having a low potential difference is applied to water flowing between the carbon electrodes in which ions are dissolved, anions among the dissolved ions are adsorbed on the cathode and cations are adsorbed on the anode. When the application of the direct current ceases, the concentrated ions are desorbed from the electrodes and removed. Here, low resistance and wide specific surface area are desirable properties for the carbon electrodes. Thus, the carbon electrode may be prepared by binding active carbon using a polytetrafluoroethylene (PTFE) binder, or by forming a plate through carbonization of a resorcinol formaldehyde resin and complicated drying process (U.S. Pat. Nos. 5,196,115 and 5,425,858).
However, the electrode using the active carbon and the PTFE binder needs to be prepared from a paste, and thus operational efficiency may decrease, and electrical conductivity may decrease since a large amount of the binder is required.
Although the electrode prepared from resorcinol formaldehyde resin has high efficiency since it has low electric resistance and wide specific surface area, the preparation process is very complicated, and thus manufacturing costs, working load, and maintenance expenses are high.

Electrode for capacitive deionization device and capacitive deionization device having the electrode

JEONBUK NATIONAL UNIVERSITY INDUSTRY FOUNDATION


A tactile biological cell model comprising: a plurality of organelle models configured to be manipulated by hand and arranged on a generally flat surface; where the plurality of organelle models are further configured to be arranged with respect to each other so as to represent the arrangement of a plurality of organelles of an actual biological cell. A tactile biological cell model kit comprising: a cell membrane model; a cell wall model; a central vacuole membrane model; a nucleus model; a plurality of chloroplast models; a plurality of amyloplast models; a plurality of chromoplast models; a plurality of coccus bacteria models; a plurality of bacillus bacteria models; and where each of the models are configured to be manipulated by hand and arranged on a generally flat surface with respect to each other so as to represent the arrangement of a plurality of organelles of an actual biological cell. A tactile biological cell model kit comprising: a plurality of organelle models; and where each of the organelle models are configured to be manipulated by hand and arranged on a generally flat surface with respect to each other so as to represent the arrangement of a plurality of organelles of an actual biological cell.

Most biology classes teach the detailed structure of cells and students learn about different cell types. Cells do not come in one size or shape. Cells are almost as diverse as the life forms on our planet. When students first attempt to view cells and recognize them under the microscope, they often find them hard to understand—the microscopic world is new to them. They may be unable to decipher individual cells, let alone tell the different cell types apart. Thus cell models have been made available for use by students. However, the current models available for teaching cell biology are static; that is their components, if any, cannot be changed, and they lack tactile qualities. These currently available models may lead to the students inferring that the cells themselves are static and all the same.
Therefore, there is a need for cell models that overcome the above listed and other drawbacks.


A sign waving apparatus that includes a base, a housing enclosing a motor, a frame support connecting the base and the housing, and a sign mount mechanically connected to a motor. The sign or signs attach to the surfaces of the sign mount. The sign mount moves relative to the housing in a variety of different motions.

There are many ways to promote one's products, businesses or operations. One frequently used method is by using signs. Signs can be used in a variety of ways, and in recent years, many businesses use human sign spinners who hold, spin or throw the signs to attract attention. Businesses generally place the sign spinners outdoors and in locations where substantial pedestrian or automobile traffic exist. Although effective, using sign spinners to perform such tasks present a number of limitations such as health risks, limited advertising time and higher costs.
Sign spinners generally work outdoors and are exposed to excessive heat or cold. In addition, in order to make advertising most effective, sign spinners position themselves at or near major traffic centers, further exposing them to hazardous exhaust gases from vehicles and/or getting hit by a vehicle.
Further, use of sign spinners is generally limited to daytime hours due to potential security risks. Additionally, in instances where sign spinners are used after dark, additional costs are incurred to provide lighting equipment. Finally, the sign spinners' wages can also add up resulting in unexpected cost issues for the advertiser.
Therefore, what is needed is a sign waving machine that can be operated without any temporal or geographical limitations.


An indexed drive system (10) for mechanised tools, in particular an electric toothbrush, for selectively imparting various drive modes to a pair of concentrically-arranged drive shafts (12, 14) thereby imparting various brushing modes to the head (H) of the mechanised tool, in particular an electric toothbrush.

Electric or otherwise powered mechanised tools for various applications are well known in the art. In particular with reference to electric brushes such as but not exclusively electric toothbrushes, the majority of conventional electric toothbrushes apply a brushing action by means of a mechanical drive in order to brush teeth, tongue, gums and any other parts of the mouth, thereby reducing the manual force required to clean the teeth while also providing brushing motions which may not be conveniently replicated manually. In addition known toothbrushes provide dual, multi directional or scatter brushing motion, and the use of one or more shafts used to drive the head of the brush in these various defined brushing motions is known. The direction of the brushing motion produced by mechanised toothbrushes is however generally the same irrespective of the part of the mouth or teeth with which they are in contact. However this single non variable motion is not generally effective or efficient in cleaning every part of the teeth, gums and tongue.
The Applicants earlier European Patent EP2142138 discloses an improved electric toothbrush which incorporates a substantially spherical brush head having two substantially hemispherical sections separated from one another, in addition to electric drive means in the form of a motor and drive means which extends upwardly through the channel and which is adapted to impart first and second independent brushing motions to the head, in particular a first motion in which the head spins about a first axis which passes through the centre of the head, and a second motion in which the brush head spins about a second axis substantially perpendicular to the first axis. In this way multiple improved brushing motions may be achieved, and which may be selected depending on the part of the mouth being cleaned.
It is an object of the present invention to provide an improved drive system for such mechanised tools, and in particular for an electric toothbrush, which is capable of more accurately controlling the application of drive from a motor to a driven component such as a head of the mechanised tool.

GlaxoSmithKline Consumer Healthcare (UK) IP Limited


An electronic device is obtained in such a way that a MEMS substrate having a MEMS element mounted thereon and a CMOS substrate are bonded together at bonding surfaces and with a bonding material M having fluidity, wherein the MEMS substrate has a bonding projection part provided to project from a substrate main body and having the bonding surface and a gap formation part disposed between the bonding projection part and the MEMS element, and the gap formation part is supported by the bonding projection part via a plurality of support pieces extending from the bonding projection part and forms reception gaps, which are capable of receiving the bonding material M extruded from the bonding surface to the side of the MEMS element, between the wall surface thereof and the bonding projection part.

As such, a known electronic device is one in which a MEMS substrate having a MEMS structure, a CMOS substrate having an integrated circuit that controls the MEMS structure, and a bonding section that bonds the MEMS substrate and the CMOS substrate together and seals the same are provided and in which the two substrates are bonded together to be packaged (see Patent Document 1). The bonding section is constituted of a bonding projection part provided to project from the MEMS substrate and a eutectic alloy deposited on the bonding projection part. Further, the MEMS substrate and the CMOS substrate are bonded together in such a way that the bonding surface of the bonding projection part and the bonding surface of the CMOS substrate are eutectically bonded together with the eutectic alloy.
[Patent Document 1] Japanese Patent No. 481328


A device (300) to produce a color image using four or more primary colors. The device may include four or more transmissive spatial light modulators (309, 310, 311, 312) to modulate four or more, respective, light beams in accordance with four or more, respective, primary color image components of the color image to produce four or more, respective, modulated light beams. The device may also include a beam combining arrangement (320) to combine the four or more modulated light beams into a combined light beam carrying the color image.

Various types of color display technologies are known in the art. For example, there are CRT display systems, LCD systems, and projection display systems. In front projection displays, the projected images are viewed from a reflective viewing screen. In rear projection displays, the projected images are viewed through a transmissive viewing screen.
To produce color images, existing display devices use three primary colors, typically, red green and blue, collectively referred to as RGB. In simultaneous projection display systems, the three primary color components of the image are modulated and displayed simultaneously using one or more SLMs.
FIG. 1 schematically illustrates an optical configuration of a RGB display device 100 implementing three transmissive Liquid Crystal Display (LCD) panels to produce a color image. The device includes an illumination unit 101 and a dichroic mirror 102 to reflect the part of the light produced by unit 101 having a blue spectrum, and to transmit the other parts of the light. The reflected blue light is further reflected by a mirror 104 and passes through a transmissive LCD panel 107 according to a pattern corresponding to a blue component of the image. A dichroic mirror 103 reflects the part of the light transmitted by mirror 102 having a green spectrum and transmits the other parts of the light. The reflected green light passes through a LCD panel 108 according to a pattern corresponding to a green component of the image. The part of the light transmitted by mirror 103, is further reflected by mirrors 105 and 106 and passes through a LCD panel 109 according to a pattern corresponding to a red component of the image. An X-cube 110 combines the light transmitted by panels 107, 108 and 109 to form a combined light beam. The combined light beam is projected on a screen by a projection lens 111. The device may include narrow band filters in order to increase saturation of the colors. However, the use of the narrow band color filters will provide a decreased brightness of the display.


A method for transmitting data from a downhole component includes: measuring a borehole fluid pressure by a receiver at a selected sampling rate and estimating a pressure signal transmitted through the fluid based on the sampled fluid pressures; measuring, by at least one pump stroke sensor, operation of a pump configured to advance fluid through the borehole; identifying individual stroke events from the pump stroke sensor measurement; generating a digital pump stroke signal in response to detecting one or more stroke events, each pump stroke signal including a digital time value associated with each of one or more stroke events; and transmitting the pump stroke signal to the receiver.

Mud pulse telemetry (MPT) is used to transmit data from downhole instruments to the surface using drilling mud or other fluids in a borehole (e.g., the mud column) as a "communication channel". Controlled pressure variations are used to modulate signals on top of the static mud pressure, which is generated by surface mud pumps. Pressure waves travel up to the surface, weakened by attenuation and other effects, where they are detected by one or more pressure transducers. During transmission, the pressure signals can be significantly affected by many "noise" sources. Pressure transducers are typically positioned closer to the mud pumps than to the pressure signal generators (e.g., mud pulsers), resulting in significant noise from the mud pumps in the detected signals. To attenuate the effect of the individual contributions of each piston in a mud pump, dampeners are used to smooth the pressure. Despite the use of dampeners, some pressure signal artifacts of each pump can remain and distort the MPT pressure signals.


The present invention relates to determining an optimized write power used for writing electronic data on optical disc and includes a method, a device and a computer program product for determining a write power for writing electronic data on a medium (32, 108), based on a sequence of written data, using a power control model, which includes a written data deviation measure, a written data asymmetry and a written data asymmetry target value, the method comprising the steps determining the written data deviation measure for the sequence of written data (step 202), adjusting the written data asymmetry target value in relation to the written data asymmetry, if the written data deviation measure has changed (steps 218, 220, 226, 228), determining the write power in dependence on written data asymmetry (step 210), and writing another sequence of data on the medium using said determined write power (step 212), so as to obtain power optimized writing of data.

In order to achieve good performance during reading and writing on an optical disc, calibration management is undertaken during the reading and writing process. Parameters such as write power, tilt, and focus offset, to mention a few, can be optimized. These parameters are dependent on both the temperature and the actual disc. Temperature variations lead to changes of the wavelength of lasers used and disc variations can cause parameter variations in the radial direction of the disc.
Optical dye discs are very sensitive to above-mentioned changes due to narrow margins for these types of discs.
In order to provide a continuous optimal write power, determining an asymmetry parameter, such as beta, is used. This parameter is chosen as it is linear with respect to the laser write power. This linearity is used to determine the regulation direction of the write power.
The jitter or Bit Error Rate (or Block Error Rate, Bler) is parabolic with respect to write power, which disables using this parameter alone to determine regulation direction of the write power.
Beta will thus be determined and this determining is performed at certain moments in time of parts already written. Typically after having written an amount of electronic data the beta value is determined. This determined value is then compared with a certain beta target reference value and the difference is calculated. The difference is further translated to a write power correction. This type of procedure of determining a beta related value, compensates for variations in radial direction of the disc and is denoted Walking Optimal Power Control (WOPC).
The international patent application WO 03/065357 A2 discloses a device for scanning a record carrier and a method for controlling a power of a radiation source, which method includes detecting a sense signal from a beam via a sensor and controlling the laser power to a desired value in dependence on the sense signal, and comprises correcting the desired value in dependence on a correction signal indicative of local optical properties of the record carrier in dependence on at least one sense signal measured on at least one part of the track near the scanning spot. The sense signals are measured on an empty track and on a written track and correction signals are defined as being dependent on linear combinations of said two sensed signals. These correction signals, dependent on measurements on empty and written tracks, define a correction value for the asymmetry parameter beta.
More generally, when writing electronic data on an optical disc using a Constant Linear Velocity (CLV) procedure, the rotation speed decreases with increasing distance from the disc center, as the data is written on the disc.
For Constant Angular Velocity (CAV) writing the rotational angular speed of the disc remains unchanged as data is written on the disc. Hence the linear (tangential) velocity increases with increasing distance from the center of the disc. For CAV writing the beta target value is therefore dependent on the linear velocity.
When accessing a certain position of the disc, corresponding to a certain overspeed factor, Nx, the beta target value, βtNx can be determined by interpolation between two states having well-known speeds or overspeed factors, Nx_min and Nx_max.
                              β                                                                          t            Nx                          =                              β                                                                                t                              N                                                                                x                                                                                _                                                                                m                                                                                i                                                                                n                                              +                                                    (                                                      Nx                    Ns                                    -                                      Nx                                          m                                                                                i                                                                                n                                                                      )                                            (                                                      Nx                                          ma                                                                                x                                                        -                                      Nx                                          m                                                                                i                                                                                n                                                                      )                                      ·                          (                                                β                                                                                t                                          Nx                                                                                _                                                                                m                                                                                ax                                                                      -                                  β                                                                                t                                          Nx                                                                                _                                                                                m                                                                                i                                                                                n                                                                                )                                                          (        1        )
The speed at the current position Ns is NxNs, and the beta target value at Nxmax and Nxmin are βtNx—max and βtNx—min, respectively. If for instance, 6x<Nx<8x, then Nxmin=6x and Nxmax=8x.
The beta target value for 6x and 8x may be accurately determined by OPC. By linear interpolation the beta target can be determined at any speed. If however, no OPC can be performed at the outside of the disc, the beta target value can be determined based on beta target values from a table and from OPC at 6x, following equations 2 and 3, for known discs.Δβ=(βt6x)table−(βt6x)OPC  (2)βt8x=(βt8x)table+Δβ  (3)
For discs that are unknown to the disc drive, information can be read from a pre-groove, a so called ADdress In Pre-groove (ADIP), to determine the beta target value at non-PC speeds, compare equations 4 and 5, which are similar to equations 2 and 3, shown above.Δβ=(βt6x)ADIP−(βt6x)OPC  (4)βt8x=(βt8x)ADIP+Δβ  (5)
The calculation of the beta target value as well as reading and determining the beta target values on the disc, result in beta values that do not take into account the variations among the actual discs and the difference between the drives that are used. These beta target values are therefore not very accurate.
For this reason, two different problematic effects can occur. The first is an effect called the post heat effect and this effect increases with increasing write power. This jitter effect is manifested in partly collapsing written marks on the disc as the pits and the lands interact with each other on the disc. This jitter effect therefore increases with increasing speed. Due to this jitter effect the regulation direction based on beta could be wrong, which would increase the jitter and Bler parameters and which would result in an undesired write performance.
The second problem is that non-OPC beta target values for non-OPC speeds are not very accurate. For some writing profiles including CAV, the beta target values for in-between speeds are determined based on estimations. This means that write power determination/regulation will be more difficult and may result in a non-appreciated write performance.
There is thus a need to overcome the issue of shortcuts becoming less relevant.


A mirror (13) for use e.g. in an EUV lithography apparatus or an EUV mask metrology system, with: a substrate (15) and a coating (16) reflective to EUV radiation (6), the reflective coating having a capping layer (18) composed of an oxynitride, in particular composed of SiNxOY, wherein a nitrogen proportion x in the oxynitride NxOY is between 0.4 and 1.4. Also provided are an EUV lithography apparatus having at least one such EUV mirror (13) and a method for operating such an EUV lithography apparatus.

The present invention relates to a mirror comprising a substrate and a coating reflective to EUV radiation, an EUV lithography apparatus comprising at least one such mirror, and a method for operating such an EUV lithography apparatus. The mirror can also be used in a different optical device than an EUV lithography apparatus, e.g. in an EUV mask metrology system.
Projection exposure apparatuses for microlithography serve for producing microstructured components using a photolithographic method. In this case, a structure-bearing mask, the so-called reticle, is imaged onto a photosensitive layer with the aid of a projection optical unit. The minimum structure size that can be imaged with the aid of such a projection optical unit is determined by the wavelength of the imaging light used. The smaller the wavelength of the imaging light used, the smaller the structures that can be imaged with the aid of the projection optical unit. Imaging light having the wavelength of 193 nm or—in so-called EUV lithography apparatuses—imaging light having a wavelength in the range of the extreme ultraviolet (EUV), i.e. 5 nm-30 nm, is principally used nowadays. Reflective optical elements (EUV mirrors) are exclusively used in EUV lithography apparatuses since no optical materials having a sufficiently high transmission at these wavelengths are known.
An EUV mirror for such an EUV lithography apparatus comprises a substrate and a reflective coating having a plurality of layers, said reflective coating being applied to the substrate. Such a multilayer coating generally consists of alternating layers composed of materials having high and low refractive indices, e.g. alternating layers composed of molybdenum and silicon, the layer thicknesses of which are coordinated with one another such that the coating fulfils its optical function and a high reflectivity is ensured. The multilayer coating typically has a capping layer in order to protect the underlying layers against oxidation or other degradation mechanisms. Said capping layer can consist of a metallic material, e.g. of ruthenium, rhodium or palladium.
EP 1 065 568 A2 discloses using carbides as materials for the capping layer, e.g. boron carbide (B4C) or silicon carbide (SiC). Nitrides, for example silicon nitride (Si3N4) or titanium nitride (TiN), are also specified there as materials for the capping layer. Analogously, US 2006/0066940 A1 describes an EUV mirror comprising a capping layer system, wherein alongside silicon nitride (Si3N4) boron nitride (BN), too, and alongside boron carbide (B4C) molybdenum carbide (MoC), too, are proposed as materials for the capping layer system.
US 2008/0316595 A1 has also disclosed a multilayer mirror for EUV applications, wherein silicon nitride, inter alia, is used as capping layer material. Since the substrate materials of EUV mirrors typically cannot withstand excessively high temperatures, it is proposed therein to implement the capping layer utilizing chemical vapor deposition (CVD) involving plasma enhanced chemical vapor deposition (PE-CVD) or low pressure chemical vapor deposition (LP-CVD). These coating methods allow a deposition at lower temperatures than is the case for a conventional chemical vapor deposition.
Capping layers composed of silicon nitride have the advantage that they have a comparatively low adhesion rate for metal deposits such as e.g. tin, such that EUV mirrors comprising such capping layers can be used e.g. in the vicinity of LPP (laser produced plasma) light sources, which can release gaseous tin. Moreover, a capping layer composed of silicon nitride on which tin has deposited can generally be completely freed of the tin deposits by cleaning using activated hydrogen (e.g. in the form of hydrogen radicals or hydrogen ions). By contrast, in the case of capping layers composed of ruthenium, for example, there is often the problem that, even after such hydrogen cleaning, tin residues remain on the surface of the capping layer and lead to a degradation of the reflectivity and/or the uniformity of the reflectivity of the EUV mirror.
During exposure operation of an EUV mirror comprising a capping layer composed of silicon nitride in an EUV lithography apparatus, it has been found that, during hydrogen cleaning of the capping layer, often it has not been possible to achieve the expected result, namely reversible cleaning of the surface of the capping layer to remove tin deposits or carbon deposits.

This patent is subject to a terminal disclaimer.

EUV mirror comprising an oxynitride capping layer having a stable composition, EUV lithography apparatus, and operating method


A new and distinct Gentiana scabra×triflora variety named ‘RI0405128’ is described. The variety results from selection among a population of seedlings derived from controlled crossing of the Gentiana varieties known as ‘SR3004’ (not patented) and ‘13-414’ (not patented). The new variety is distinguished from others by its purple flower color and compact plant form.

Seedlings obtained from the deliberate crossing of the Gentiana scabra×triflora selections 'SR3004' (female parent) (not patented) and '13-414' (male parent) (not patented), in 2005, were planted out at Palmerston North, New Zealand, where the cross was also conducted. In 2008, 'RI0405128' was asexually propagated and underwent simultaneous evaluation at Palmerston North and in Hachimantai City, Japan. In 2010, 'RI0405128' was selected for its purple flower color and branching habit in both trial planting locations, New Zealand and Japan. Plants have been asexually propagated by both cuttings and tissue culture and subsequently found to be true to type demonstrating that the characteristics of the new variety 'RI0405128', are stable and transmitted without change through succeeding generations.


A voltage comparator for use in a subranging A/D converter includes a coarse preceding comparison circuit 30, a fine preceding comparison circuit 31, and an amplification circuit 32 having an automatic zero compensation function. The coarse preceding comparison circuit 30 compares an analog input voltage Vin and a coarse reference voltage Vai. The fine preceding comparison circuit 31 compares the analog input voltage Vin and a fine reference voltage Vbi. The coarse and fine preceding comparison circuits 30, 31 sequentially outputs comparison results to the amplification circuits 32 so that the comparison results do not overlap each other. The amplification circuits 32 resets offset voltages before amplifying the comparison results applied. The number of elements necessary for a subranging A/D converter can be reduced, and a voltage comparator operating at a high speed and highly accurately can be provided.

1. Field of the Invention
The present invention relates to a voltage comparator and a subranging A/D converter including such a voltage comparator.
2. Description of the Background Art
An A/D converter converts an analog signal to a digital signal. There are flash A/D converters, subranging A/D converters, etc. A subranging A/D converter A/D-converts an analog signal in two stages, i.e. stages of more significant bits and less significant bits. This subranging A/D converter has a smaller circuit scale and smaller power consumption as compared to a flash A/D converter. The subranging A/D converter is suited for installation in an LSI (Large Scale Integrated circuit) or a VLSI (Very Large Scale Integrated circuit) for this characteristic. This advantage of the series-parallel type has recently accelerated its development. An example of a subranging A/D converter as described above is presented in a document entitled "A CMOS 40 MHz 86 105 mW Two-Step ADC", IEEE ISSCC Dig. of Teach. Papers. pp. 14-15, 1989.
FIG. 12 is a block diagram showing the conventional subranging A/D converter disclosed in the above-stated document. The subranging A/D converter shown in FIG. 12 conducts A/D conversion of a total of m+n bits formed of more significant m bits and less significant n bits. Referring to FIG. 12, the subranging A/D converter includes a reference voltage generation circuit 1, coarse voltage comparators A.sub.0 -A.sub.k-1 (k=2.sup.m 1), a coarse encoder 2 for encoding m bits, fine voltage comparators B.sub.0 -B.sub.l-1 (l.gtoreq.2.sup.n -1), a fine encoder 3 for encoding n bits, and an error correction circuit 4. The reference voltage generation circuit 1 has two input terminals 5 and 6 for applying reference voltages Vrt and Vrb, and an input terminal 7 for controlling a signal. The reference voltage generation circuit 1 has k coarse reference voltage output terminals a.sub.0 -a.sub.k-1 and l fine reference voltage output terminals b.sub.0 -b.sub.l-1 for outputting analog voltages based on these input voltages or input signals. The coarse voltage comparators A.sub.i (i=0 to k-1) each has 2 input terminals, one of which is connected together to an analog voltage application terminal 8, the other is connected to the coarse reference voltage output terminal a.sub.i. The coarse encoder 2 has k input terminals connected to the outputs of k coarse voltage comparators a.sub.i, a 4 bit encoder result output terminal for outputting an encoder result, and an output terminal for control. The terminal to output an encoder result is connected to the input terminal of the error correction circuit 4, the output terminal for control signal is connected to the input terminal for control signal 7 of the reference voltage generation circuit 1. As is the case with the coarse voltage comparator A.sub.i, the fine comparators Bj (j=0 to l-1) each have 2 input terminals, one of which is connected together to the analog voltage application terminal 8, and the other is connected to the fine reference voltage output terminal b.sub.j. The fine encoder 3 has l input terminals connected to the outputs of the fine voltage comparators B.sub.j, an output terminal 9 for outputting an encode result of n bits, and an error detection signal output terminal 10 for outputting an error detection signal to the error correction circuit 4. The error correction circuit 4 has m input terminals connected to the output of coarse encoder 2, an input terminal connected to the error detection signal output terminal 10, and an output terminal 11 for outputting a final coarse encoder result of m bits which has been subjected to error correction.
An operation of the subranging A/D converter shown in FIG. 12 will be described. The subranging A/D converter operates in two stages, in other words in stages of coarse A/D conversion and fine A/D conversion. In the first stage, in other words in the coarse A/D conversion stage, each of the coarse voltage comparators A.sub.i compares an analog signal voltage Vin and a coarse reference voltage Va.sub.i output from the coarse reference voltage input terminal a.sub.i. The coarse reference voltage Va.sub.i is usually obtained by dividing the two voltages Vrt and Vrb applied to the reference voltage application terminals 5 and 6 of the reference voltage generation circuit 1. Such reference voltage Va.sub.i and the analog signal voltage Vin are compared at the voltage comparator, and a range of voltage in which the analog voltage Vin exists is detected, and then a conversion into a desired code is conducted at the encoder 2. At the same time, a detection signal of the above-stated voltage range is applied to the control signal input terminal 7 of the reference voltage generation circuit 1.
In the second stage, in other words in the fine A/D conversion stage, a fine reference voltage Vb.sub.j to be output to the fine reference voltage application terminal B.sub.j is generated by the reference voltage generation circuit 1 based on a control signal. For example, if the presence of the analog signal voltage Vin between the coarse reference voltages Va.sub.i and Va.sub.i+1 in the course of a coarse A/D conversion, a voltage further divided including both voltages is generated. Thus generated fine reference voltages V.sub.bj are each input into one input end of a corresponding voltage comparator B.sub.j. The analog signal voltage Vin is applied in common to the other input end of each of the voltage comparators B.sub.j, comparison and encoding are conducted as is the case with the coarse A/D conversion operation, and finally a fine A/D conversion result in a desired code is output from the terminal 9. At the same time, a determination is made whether or not the range in which the analog signal voltage Vin detected in the fine A/D conversion exists coincide with that of the coarse A/D conversion result, and if no coincidence is found, a control signal is transferred to the error correction circuit 4 through the error detection signal output terminal 10. The error correction circuit 4, based on the control signal, corrects the coarse encoder result, and finally outputs a coarse A/D conversion result to the terminal 11.
FIG. 13 is a circuit diagram showing an example of a conventional 2-input voltage comparator. Referring to FIG. 13, in the voltage comparator, a coarse voltage comparator A.sub.i and a fine voltage comparator Bj are independently provided. The voltage comparator is controlled by clock signals .phi..sub.1 -.phi..sub.31 generated by a clock signal generation circuit 50 externally provided.
The coarse voltage comparator A.sub.i is formed of a series-connection of an input circuit 12, amplification circuits 13a and 14a of first and second stages having an automatic zero compensation function, and an inversion amplifier 15a. The input circuit 12 includes a switch S1 connected to an analog signal application terminal 8, and a switch S2 connected to a coarse reference voltage application terminal a.sub.i. The switch S1 is turned on/off in response to the clock signal .phi.1. The switch S2 is turned on/off in response to the clock signal .phi.2. The output terminals of the switches S1 and S2 are connected together to the input end of the first stage amplification circuit 13. The first stage amplification circuit 13 includes a coupling capacitor Cc, an inversion amplifier 16, and a switch S3 connected between the input and output of the inversion amplifier 16. The coupling capacitor Cc has one end connected to the output of the input circuit 12 and the other end connected to the input of the inversion amplifier 16. The switch S3 is turned on/off in response to the clock signal .phi.1. When the switch S3 conducts, the output of the inversion amplifier 16 is fed back to the input of the amplifier 16. The second stage amplification circuit 14a has the same construction as that of the first amplification circuit 13.
As is the case with the coarse voltage comparator A.sub.i, a fine voltage comparator B.sub.j is formed of a series-connection of an input circuit 17, first stage and second stage amplification circuits 13b and 14b, and an inversion amplifier 15b. An essential difference from the coarse voltage comparator A.sub.i is that the input circuit 17 is connected to the fine reference voltage output terminal b.sub.j (see FIG. 12), and the fine reference voltage output terminal b.sub.j is connected to the input end of the first stage amplification circuit 13b through a switch S4. The switch S4 is turned on/off in response to the clock signal .phi.3.
FIG. 14 is a representation showing the signal waveforms of the circuits shown in FIG. 13. The waveforms of V.sub.3, V.sub.4, V.sub.5 indicated by the solid lines in FIG. 14 are voltage waveforms in the coarse comparison, while the waveforms of V.sub.3, V.sub.4, V.sub.5 depicted by the chain dotted lines are voltage waveforms in the fine comparison. Referring to FIG. 14, a description of an operation of the coarse voltage comparator A.sub.i shown in FIG. 13 follows. In a period when the clock signal .phi.1 is in an "H" level (this period is referred to as an auto zero period), the switches S1 and S3 are turned on, while the switch S2 is turned off. With the switch S1 made conductive, the analog signal voltage Vin is applied to the first stage amplification circuit 13a. With the switch S3 made conductive, the outputs of the internal nodes N1 and N2 of first stage and second stage amplification circuits 13a and 14a are biased to the logic threshold voltage Vb of the inversion amplifier 16. Thus, charges are accumulated on the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13a and 14a. Assuming that the accumulated charges are Q and Q.sub.2, respectively, and the parasitic capacitance of nodes N1 and N2 are Cs and Cs.sub.2, respectively, the following equations hold. EQU Q.sub.1 =PCc (Vb-V.sub.in)+C.sub.s1 Vb (1) EQU Q.sub.2 =PCc (Vv-V.sub.b)+C.sub.S2 Vb (2)
At the same time, the output of the inversion amplifier 15a is also biased to the threshold Vb.
In a period when the clock signal .phi.2 is in an "H" level (this period is referred to as coarse comparison period), the switch S2 is turned on, while the switches S1 and S3 are turned off. With the switch S3 conducting, the first stage and second stage amplification circuits 13a and 14a lose an inlet and outlet path for charges to and from the internal nodes N1 and N2, and the charges Q.sub.1 and Q.sub.2 accumulated in the auto zero period are held therein. Meanwhile, the coarse reference voltage Va.sub.i rather than the analog signal voltage Vin is applied to the input terminal of the first stage amplification circuit 13a of the coarse voltage comparator A.sub.i in this period. Thus, the voltages of the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13a and 14a change its level from the threshold voltage Vb to certain voltages V.sub.1 and V.sub.2. Accordingly, the amount of charge Q at the internal node N1 of the first stage amplification circuit 13 is given by the following equation using the voltage V.sub.1. EQU Q.sub.1 =Cc (V.sub.1 -Va.sub.i)+Cs.sub.1 V.sub.1 ( 3)
Therefore, from equations (1) and (3), the voltage V.sub.1 is finally given by the following equation. EQU V.sub.1 =Vb+.lambda.(Va.sub.i -V.sub.in) (4)
where, EQU .lambda.=Cc/(Cc+Cs) (5)
Equation (4) means that the voltage of the internal node N1 of the first stage amplification circuit 13a shifts from the threshold voltage Vb in response to a voltage change (this proportion amount is referred to as a voltage transmission rate) generated at the input. More specifically, the amount of voltage change created on the input side by the coupling capacitor Cc and the parasitic capacitor Cs is multiplied by .lambda., and the .lambda.-multiplied voltage change is superimposed to the threshold voltage Vb. Now, assuming that the voltage change on the input side is .DELTA.Vin, the voltage on the output side before this voltage change is transferred is Vout.sub.0, the voltage on the output side after the transfer is Vout, Vout is generally given by the following equation EQU Vout=Vout.sub.0 +.lambda..DELTA.Vin (6)
Accordingly, the input of the first stage amplification circuit 13a is shifted from the threshold voltage Vb by .lambda..DELTA.Vic (where .DELTA.Vic=Va.sub.i -Vin; coarse input differential voltage). Such shift amount is amplified by the inversion amplifier 16 of the first stage amplification circuit 13a. When the voltage amplification factor of the inversion amplifier 16 is -G and the output voltage is V.sub.3, the output voltage V.sub.3 is given by the following equation: EQU V.sub.3 =Vb-.lambda.G.DELTA.Vic (7)
In the second stage amplification circuit 14, the above-stated voltage V.sub.3 is applied rather than the threshold voltage Vb in the auto zero period. The application of the output voltage V.sub.3 changes the voltage of the internal node N2 from Vb. The amount of this voltage change can be produced based on the principle of conservation of charge in the input node N2, but herein, only the result is given based on equation (6). More specifically, the voltage change .DELTA.V.sub.3 on the input side of the second stage amplification circuit 14 is -.lambda.G.DELTA.Vic from equation (7), and therefore the voltage change .DELTA.V.sub.2 generated at the node N2 is given by the following equation: EQU .DELTA.V.sub.2 =.lambda..DELTA.V.sub.3 =-.lambda..sup.2 G.DELTA.Vic (8)
This voltage change .DELTA.V.sub.2 is further amplified by the inversion amplifier 16 of the second stage amplification circuit 14a. The voltage change .DELTA..sub.V4 in the output end of the inversion amplifier 16 is given by the following equation: EQU .DELTA..sub.V.sub.4 =-G.DELTA.V.sub.2 =.lambda..sup.2 G.sup.2 .DELTA.Vic (9)
This is further amplified by the inversion amplifier 15a, and, therefore, the output voltage V.sub.5 of the amplifier 15a is given by the following equation: EQU V.sub.5 =Vb-G.DELTA.V.sub.4 =Vb-.lambda..sup.2 G.sup.3 .DELTA.Vic (10)
Equation (10) indicates that the coarse input differential voltage .DELTA.Vic is multiplied by .lambda..sup.2 G.sup.3 for output in the coarse voltage comparator A.sub.i. Accordingly, if, for example, .lambda.=1, G=10, Vb=2.5 V, and an input differential voltage is equal to or larger than 1.7 mV, amplification can be made up to a logic level ("H" is more than 4.2 V, while "L" is less than 0.8 V with a power supply voltage of 5 V). At that time, the voltage comparator outputs an "H" level when Vin>Va.sub.i, and an "L" level when Vin<Va.sub.i. Based on this output result (comparison result) the reference voltage generation circuit 1 generates the fine reference voltage Vb.sub.j, and applies the generated voltage to the fine reference voltage application terminal b.sub.j.
The fine voltage comparator B.sub.j operates based on the same principle as the coarse voltage comparator A.sub.i with only the difference being that comparison is conducted when the clock signal .phi.3 is in an "H" level (this is called fine comparison period). Therefore, description will not be repeated here.
As described above, when the conventional 2-input voltage comparator is used in a subranging A/D converter, it is necessary to separately provide a voltage comparator for coarse A/D conversion and a voltage comparator for fine A/D conversion. As described above, the subranging A/D converter conducts series-parallel A/D conversion in two stages, and as is well known the converter needs at least 2.sup.m -1 voltage comparators for a parallel A/D conversion of, for example, m bits. Accordingly, with increase of resolution, the number of voltage comparators necessary increases as an exponential rate. In order to alleviate such disadvantage of the subranging A/D converter, use of a 3-input voltage comparator is proposed in an article entitled "An 8-bit 20 MS/s CMOS A/D Converter with 50-mW Power Consumption" IEEE Journal of Solid State Circuit 1990 Vol. 25, No. 1 pp. 167-172.
FIG. 15 is a circuit diagram showing the 3-input voltage comparator disclosed in the above-stated article, and FIG. 16 is a representation showing the signal waveforms of the circuits in FIG. 15. The voltage comparator shown in FIG. 15 is different from the voltage comparator shown in FIG. 13 in that a three-input input circuit 19 is used instead of two 2-input input circuits 12 and 17, and first stage and second stage amplification circuits 13 and 14, and the inversion amplifier 15 are provided one for each. The input circuit 19 includes three input terminals, an analog signal application terminal 8, a coarse reference voltage application terminal a.sub.i and a fine reference voltage application terminal b.sub.j. The input terminals 8, a.sub.i and b.sub.j are connected together to the input end of the first stage amplification circuit 13 respectively through switches S1, S2 and S4. The switch S1 is turned on/off in response to the clock signal .phi.1. The switch S2 is turned on/off in response to the clock signal .phi.2. The switch S4 is turned on/off in response to the clock signal .phi.3.
A description of an operation follows. The voltage comparator is controlled by the clock signals shown in FIG. 16 (the same as those shown in FIG. 14), and operates in three stages. When the clock signal .phi.1 is in an "H" level (auto zero period), the switches S1 and S3 are turned on, while the switches S2 and S4 are turned off. With the switch S1 being turned on, the analog signal voltage Vin is applied to the input of the first stage amplification circuit 13. With the switch S3 being turned on, the internal nodes N1, N2 and outputs of the first stage and second stage amplification circuits 13 and 14 are biased to the logic threshold voltage Vb of the inversion amplifier 16. The output of the inversion amplifier 15 is biased to the voltage Bb accordingly.
In a period when the clock signal .phi.2 is of "H" level (coarse comparison period), only the switch S2 is turned on, and the other switches S1, S3, and S4 are turned off. The operation in this case is the same as the above-stated voltage comparator (FIG. 13), a description will not be repeated here.
In a period when the clock signal .phi.3 is of "H" level (fine comparison period), the switch S4 is turned on, and the other switches S1-S3 are turned off. Also in this period, with the switch S3 still being turned off, the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13 and 14 attain a high impedance state. Therefore, in the auto zero period, charges accumulated at the internal nodes N1 and N2 are still conserved in this period, and equation (6) given above holds in this period. Meanwhile, with the switch S4 being turned on, the fine reference voltage Vbj instead of the coarse reference voltage Va.sub.i is applied to the input of the first stage amplification circuit 13. The voltage obtained by multiplying this voltage change (Vb.sub.j -Va.sub.i) by .lambda. is superimposed to the voltage V.sub.1 produced by equation (4). Accordingly, the voltage V.sub.11 of the node N3 of the amplification circuit 13 in the fine comparison period is given by the following equation: ##EQU1##
Equation (11) indicates that voltage change from Vin to the fine reference voltage Vb.sub.j takes place at the input end of the first stage amplification circuit 13. The voltage shift from the logic threshold voltage Vb is transferred to succeeding stages as is the case with the voltage comparator shown in FIG. 13, and a fine comparison is conducted. When the voltage comparator is constructed as shown in FIG. 15, the coarse and fine voltage comparisons can be conducted in a single voltage comparator. Therefore, A/D conversion of a total of 2m bits formed of more significant m bits and less significant m bits is conducted, (2.sup.m -1) voltage comparators may be provided. This means that the number of voltage comparators necessary is reduced by half as compared to the 2-input voltage comparator (FIG. 13) which requires 2.multidot.(2.sup.m -1) voltage comparators. The voltage comparator of this construction however still suffers from the following disadvantage.
This disadvantage will be described in conjunction with the output transient responsive waveforms of the amplification stages of fine voltage comparator Bj and the transient responsive waveforms of the amplification stages of the 3-input voltage comparator shown in FIG. 16. In FIGS. 14 and 16, V3 represents the output voltage of the first stage amplification circuit 13, V4 the output voltage of the second stage amplification circuit 14, and V5 the output voltage of the inversion amplifier 15. As can be seen from FIG. 14, all the internal nodes N1-N4 are biased to the threshold voltage Vb immediately before fine comparison in the 2-input voltage comparator (this state is referred to as initial state), the internal nodes N1-N4 start responding for outputting a correct comparison result the moment the fine reference voltage Vb.sub.j is supplied. In contrast, in the 3-input voltage comparator, the internal nodes have shifted from the logic threshold voltage Vb immediately before execution of the fine comparison depending upon the coarse comparison result. Accordingly, the 3-input voltage comparator requires an extra time period (this is referred to as recovery time) until the voltage at the end of the coarse comparison returns to the initial state. For example, in the first stage amplification circuit 13, time until the output voltage V3 crosses the logic threshold voltage Vb is the recovery time of the amplification circuit 13. The output voltage V4 of the second stage amplification circuit 14 begins to be inverted at the moment the output voltage of the first stage amplification circuit 13 crosses Vb. Therefore, the recovery time of the amplification circuit 14 is produced as the sum of the recovery time of the first stage amplification circuit 13 and its recovery time. Recovery time increases in succeeding stages, which results in degradation in the comparison speed for the entire voltage comparator.
Additionally, in the conventional 2-input and 3-input voltage comparators, comparison accuracy sometimes degrades due to a clock noise. A transmission gate as shown in FIG. 17 is generally used for the switches S1-S4 in the voltage comparators shown in FIGS. 13 and 15. The transmission gate includes a PMOS transistor 20, and an NMOS transistor 21 connected in parallel thereto. The PMOS and NMOS transistors 20 and 21 have their gate terminals 22 and 23 supplied with clock signals which are complementary to each other. The drain electrodes and source electrodes of the transistors 20 and 21 are connected together to terminals 24 and 25, respectively. Gate-drain capacitors 26 and 27 of capacitance values C.sub.1 and C.sub.2 exist in a parasitic manner between the gate electrodes 22, 23 and drain electrodes 24 of the transistors 20, 21. Similarly, gate-source capacitors 28 and 29 of capacitance values C.sub.3 and C.sub.4 exist in a parasitic manner between the gate electrodes and source electrodes of transistors 20 and 21.
Now, an operation of the transmission gate taking into account the parasitic capacitance will be described. When a signal applied to the gate electrode 22 changes its level from "L" to "H", and a signal applied to the gate electrode 23 changes its level from "H" to "L", the transmission gate is turned off. This gate voltage change is transferred to the terminals 24 and 25 through the parasitic capacitor. More specifically, charge is implanted into terminals 24 and 25 by the change of the gate voltage. When the terminals 24 and 25 are in the state of high impedance, a minor voltage change takes place by the implanted charge. When a signal of a large amplitude is dealt with as in the case of a digital circuit, such minor voltage change does not cause any problem, but results in a significant problem in an analog circuit.
Now, an operation of the 2-input coarse voltage comparator A.sub.i taking into such implanted charge will be described. Consider, for example, the switch S3 of the first stage amplification circuit 13a shown in FIG. 13. When the switch S3 is formed of a transmission gate, it generates a voltage change caused by the change of the clock signal at the internal node N2 at the moment it is turned off. The voltage change .DELTA.V.sub.21 of the internal node N2 caused exclusively by this clock change is given by the following equation, wherein the gate terminal voltage of a P type transistor is .DELTA.Vclk, and the gate terminal voltage of an N type transistor is -.DELTA.Vclk: ##EQU2##
Therefore, the voltage V.sub.1 of the internal node N1 in the first stage amplification circuit 13 in the coarse comparison period when such clock noise is taken into account is given by the following equations: EQU V.sub.1 =Vb+.lambda..DELTA.Vic+.lambda.C.DELTA.Vclk (13)
, where EQU .lambda.C.fwdarw.(C.sub.1 -C.sub.2)/(Cc+Cs.sub.1) (14
From the above equations, when, for example, .DELTA.Vic=-1 mV, and .DELTA.Vclk=5 V, and the following expression holds: EQU C.sub.1 -C.sub.2 >Cc/5000 (15)
This indicates that an erroneous operation is caused by the clock noise. When expression (15) is satisfied, V.sub.1 -Vb>0 is true despite that .DELTA.Vic<0. In order to prevent such erroneous operation, if Cc=0.1 fF, the expression C.sub.1 -C.sub.2 <0.02 fF or smaller must be satisfied. C.sub.1 and C.sub.2 are parasitic capacitors, and, therefore, it is difficult to control the capacitance values in the above-stated order. Upon occurrence of an erroneous operation in the first stage amplification circuit 13, this error is amplified and output as a comparison result. Such clock noise is also generated in the second stage amplification circuit 14, but the signal has already been amplified at the first stage amplification circuit 13, and therefore does not cause such a significant problem as compared to the first stage.
With the conventional 2-input voltage comparator constructed as in the above-described manner, the number of voltage comparators necessary when an A/D converter is formed using such voltage comparators increases as an exponential function with increase of the resolution of A/D converter. Also, the conventional 3-input voltage comparator alleviates the above-stated problem, but its comparison speed decreases. Furthermore, both 2-input and 3-input voltage comparators are prone to erroneous operations caused by clock noises, and both have problems in the comparison accuracies.

Voltage comparator and subranging A/D converter including such voltage comparator


A transimpedance amplifier (TIA) with integrated filtering. A capacitance is integrated into the TIA and connected to the power supply and to an internal ground of the TIA. Noise on the power supply of the transimpedance amplifier is filtered by the capacitor such that the power supply noise is reduced. The integrated capacitor also reduces noise ground. The integrated capacitor also reduces the effects of common mode noise that may be received from another circuit.

1. The Field of the Invention
The present invention generally relates to optoelectronic components, such as optical receivers. More particularly, embodiments of the invention relate to systems and methods for filtering high frequency noise from a transimpedance amplifier including power supply noise, ground noise, and output common mode noise.
2. Related Technology
Fiber optic cables are one of the mediums used in computer and telecommunication networks. Fiber optic networks use modulated light signals to transmit data. The light is often generated by a laser whose current is modulated to represent the ones and zeroes of the digital data stream. Although light signals are used to carry data over fiber optic cables, the light signals are typically converted into electrical signals in order to extract and process the data. Computers need some type of device to detect and translate the optical signals.
Optical receivers are specifically built for the purpose of receiving and interpreting light signals. An optical receiver typically includes some sort of detector that can generate an electrical current or voltage in response to changes in the power of the incident optical signal. After the fiber optic receiver converts the optical signal received over the optical fiber into an electrical signal, the optical receiver amplifies the electrical signal, and converts the electrical signal into an electrical digital data stream.
One of the common devices used as a detector in an optical receiver is a photodiode. A photodiode operates by generating a current in response to incident light. The optical power of the incident light determines the current that flows in the photodiode. In effect, the optical signal generates current in the photodiode that corresponds to the digital data carried by the optical fiber.
In order to operate properly, the photodiode is reverse biased having its anode connected to the input of the transimpedance amplifier and its cathode to a power supply or a biasing circuit. Ideally, the power supply or biasing circuit provides a constant voltage such that the current in the photodiode is attributable to the incident optical signal. Unfortunately, power supplies almost invariably have noise. The noise may come from switching, host board connections, and other sources. Further, power supply noise often is at a frequency that may be in the same range as the frequency of the data being transmitted on the optical network. As a result, the noise of the power supply can influence the current that is generated by the photodiode and has a detrimental effect on the performance of the optical receiver.
The noise on the power supply enters the transimpedance amplifier with the current generated by the incident light signal. The noise is amplified by the transimpedance amplifier along with the signal from the photodiode. Thus, the performance of the transimpedance amplifier suffers. One potential solution to the problem of power supply noise is to use a decoupling capacitor at the cathode of the photodiode to shunt the noise to ground. Decoupling capacitors are discrete circuit components and therefore introduce additional cost into the production of each optical receiver. Decoupling capacitors are also connected to an external ground that is often different from the ground associated with integrated circuits. This is particularly true for higher frequencies.
Other sources of high frequency noise, such as integrated circuit internal ground noise, and common mode noise are unaffected by the external decoupling capacitor. In transimpedance amplifiers, the local ground of the transimpedance amplifier is often connected to an external ground with, for example, bond wires. At higher frequencies, the inductance of the ground bond wires introduces a significant impedance between the IC internal and external ground and can therefore introduce noise that is amplified by the transimpedance amplifier, thereby reducing the performance of the transimpedance amplifier.
Common mode noise can often enter into the transimpedance amplifier through the output of the transimpedance amplifier. Other integrated circuits that connect to the output of the transimpedance amplifier can introduce common mode noise in this manner. One of the reasons that common mode noise becomes a problem is because the input stage of the transimpedance amplifier is not a differential input. As a result, common mode noise that migrates to the input stage of the transimpedance amplifier can impact the performance of the transimpedance amplifier.

Transimpedance amplifier with integrated filtering and reduced parasitic capacitance


In some embodiments, methods and systems are provided for processing reimbursement requests submitted by retail stores to distribution centers responsible for delivering products to the retail stores. A claim processing server is configured to analyze a reimbursement request, an associated electronic invoice, and a set of business rules, all of which are stored in electronic databases and obtained by the processing server. Based on this analysis, the claim processing server is programmed to either approve or deny the reimbursement request submitted by a retail store, and if the reimbursement request is approved, to generate a corrected invoice to be sent to the distribution center.

Major retail stores typically receive products from product distribution centers via delivery by carriers (typically trucks). Generally, the quantity of the products delivered corresponds to the quantity indicated on the documentation (e.g., purchase order, invoice, etc.) associated with the delivery, and the condition of the products delivered is new and undamaged, such that the products can be displayed and sold to the customers of the retail store. It is not uncommon for carriers to deliver to the retail store a number of product that is greater than or less than the number of products ordered by the store, or to deliver products that have been damaged during delivery, or to deliver products that are unsuitable for sale to consumers for any other reason (e.g., past expiration date, poor quality, etc.). In such situations, retail stores typically submit reimbursement requests to the distribution centers in order to rectify the mis-shipment condition.
Conventional systems for processing reimbursement requests rely on facsimile and/or electronic mail. For example, a retail store typically submits a reimbursement request by manually assembling papers (e.g., invoice, photographs, etc.) and faxing the paperwork to the distribution center, where a worker at the distribution center would review the reimbursement request and would then notify the retail store by facsimile that whether the reimbursement request was approved or denied by the distribution center. Such conventional systems are time consuming due to the many manual steps involved and are subject to human error.
Elements in the figures are illustrated for simplicity and clarity and have not been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. Certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. The terms and expressions used herein have the ordinary technical meaning as is accorded to such terms and expressions by persons skilled in the technical field as set forth above except where different specific meanings have otherwise been set forth herein.

Systems and methods for processing reimbursement requests submitted by retail stores to distribution centers


In a method for raising the pH in acidic soils, said acidic soils are treated with crosslinked polyacrylates or polymethacrylates.

The present invention relates to a method for raising the pH in acidic soils, especially in soils having a pH in the aluminum buffer range, i.e. less than 4.2. The aluminum buffer range is the pH range in which aluminum from the weathering of clay minerals, which is present as oxide or hydroxide, i.e. in nonionic form, at higher pH, passes into cationic solution.
To raise the pH such soils have hitherto been treated with lime, for example by sprinkling on or mixing into the soil. Existing stands were limed with about 3 t per ha every five years to stop further acidification. In the case of first afforestations, the recommended liming quantities are appreciably higher, up to 15 t per ha, depending on soil acidification, because of the higher acid sensitivity of the young plants. Since, owing to the now appreciably decreased acid emissions, significant further acidification of soils is no longer likely, liming will in future no longer have such immense importance in the case of mature stands. However, the mortality problem of afforestations on problem sites will continue, since the acid in the soils is not so quickly neutralized.
Attempts have been made to improve soil quality by mixing alkaline sandy and loamy soils with poly(meth)acrylates (Arid-Soil-Research-and-Rehabilitation, 1996, 10; 3, 277-285). The pH was observed to rise. This effect of pH being raised, which is actually undesirable in alkaline soils, can be explained by the bonding of protons to the acrylate, releasing metal cations, such as potassium, from the acrylate.
The situation is different in acidic soils. Soil suspensions in pure water have a pH some 0.6 units higher than a suspension in CaCl2 solution. This is because, in such soils, the exchange sites on the clay-humus complex are mostly occupied by protons and cationic acids and the pH of the soil solution is very slow to become established, i.e. equilibration is very slow between the clay-humus complexes of the soil and the soil solution (see: xe2x80x9cBodenxc3x6kologiexe2x80x9d, Georg Thieme Verlag Stuttgart 1997, p. 125). On adding KCl or CaCl2 to a soil suspension, the counterions on the exchanger complex are immediately released and the pH correspondingly lowered.
When the method of the invention is used to add poly(meth)acrylates to an acidic soil, the protons in the soil solution are trapped by the negatively charged carboxyl groups of the poly(meth)acrylates, so that a higher pH becomes established in the soil solution. This effect persists for a prolonged period, surprisingly for a period of many months. This could not be foreseen by one skilled in the art and permits a long-term raising of the pH of acidic soils.

Method for increasing the pH value in acidic soil