A method and system for transforming and verifying downloaded programs fragments with data type restriction in an embedded system in which a program fragment being temporarily stored a verification process of the stored program fragment object code is executed instruction by instruction so as to discriminate for each instruction the existence of a target, a branching instruction target, a target of an exception handler call or a target of a subroutine call. On the occurrence of a target of a branching instruction as the current instruction, the empty status of the stack is verified and the program fragment is rejected otherwise. A verification process and updating of the effect of the current instruction on the data types of the type stack and the table of register types is performed. The verification process is successfully executed instruction by instruction until the table of register types is stable, with no modification being present, and interrupted with the program fragment being rejected otherwise.

1. Field of the Invention
The invention relates to a process for managing, a method of verifying and a method of transforming a downloaded program fragment and the corresponding systems, more particularly intended for embedded data-processing systems with limited memory and of computing power resources.
2. Prior Art
In a general way, by reference to FIG. 1a, it is reiterated that embedded data-processing systems 10 include a microprocessor 11; a computer readable storage medium, including, but not limited to: a permanent memory, such as a non-writable memory 12 containing the code of the executable program, and a rewritable, nonvolatile, permanent memory 13 of EEPROM type containing the data stored in the system, a volatile, random-access memory 14 in which the program stores its intermediate results while it is executing; and input/output devices 15 allowing the system to interact with its environment. When the embedded data-processing system consists of a microprocessor card, of the bank-card type, the input/output device 15 consists of a serial link allowing the card to communicate with a terminal, such as a card-reader terminal.
In conventional embedded data-processing systems, the code of the program executed by the system is fixed during construction of the system, or, at the latest, when the latter is customized before delivery to the final user.
More sophisticated embedded data-processing systems have, however, been implemented, these systems being reprogrammable, such as microprocessor cards of the JAVACARD type, for example. Compared to the earlier types, these reprogrammable systems add the possibility of enhancing the program after the system has been put into service, via an operation of downloading program fragments. These program fragments, commonly known as "applets", will be referred to as applets or program fragments indiscriminately in the present description. For a more detailed description of JAVACARD systems, reference could usefully be made to the documentation published by the company SUN MICROSYSTEMS INC., and in particular to the electronically available documentation, JAVACARD technology chapter, on the World Wide Web at site http://java.sun.com/products/javacard/index.html, available since June 1999.
FIG. 1b illustrates the architecture of such a reprogrammable embedded data-processing system. This architecture is similar to that of a conventional embedded system, apart from the fact that the reprogrammable embedded system can in addition receive applets via one of its input/output devices, then store them in its permanent memory 13 from which they can then be executed complementing the main program.
For reasons of portability between different embedded data-processing systems, applets take the form of code for a standard virtual machine. This code is not directly executable by the microprocessor 11, but it has to be interpreted in software terms by a virtual machine 16, which consists of a program resident in a non-writable permanent memory 12. In the above-mentioned example of JAVACARD cards, the virtual machine used is a subset of the JAVA virtual machine. For a description of the specifications relating to the JAVA virtual machine and of the virtual machine used, reference could usefully be made to the work published by Tim LINDHOLM and Frank YELLIN, entitled "The Java Virtual Machine Specification", Addison-Wesley 1996, and to the documentation published by the company SUN MICROSYSTEMS INC. "JAVACARD 2.1 Virtual Machine Specification", documentation available electronically on the World Wide Web at site http://java.sun.com/products/javacard/JCVMSpec.pdf, since March 1999.
The operation of downloading applets onto an embedded data-processing system in service poses considerable security problems. An applet which is unintentionally, or even deliberately, badly written may incorrectly modify data present on the system, prevent the main program from being executed correctly or at the right time, or even modify other applets downloaded previously, making them unusable or harmful.
An applet written by a computer hacker may also divulge confidential information stored in the system, information such as the access code in the case of a bank card, for example.
At the present time, three solutions have been proposed with a view to remedying the problem of applet security.
A first solution consists in using cryptographic signatures in order to accept only applets originating from trusted organizations or persons.
In the abovementioned example of a bank card, only the applets bearing the cryptographic signature of the bank having issued the card are accepted and executed by the card, any other unsigned applet being rejected in the course of the downloading operation. An ill-intentioned user of the card, not having available encryption keys from the bank, will therefore be unable to execute an unsigned and dangerous applet on the card.
This first solution is well suited to the case where all the applets originate from the same single source, the bank in the abovementioned example. This solution is difficult to apply in the case where the applets originate from several sources, such as, in the example of a bank card, the card manufacturer, the bank, the organizations managing bank card services, the large commercial distribution organizations offering customers loyalty programs and legitimately offering to download specific applets onto the card. The sharing and the holding among these various economic participants of the encryption keys necessary for the electronic signature of the applets pose major technical, economic and legal problems.
A second solution consists in carrying out dynamic access and typing checks while executing the applets.
In this solution, the virtual machine carries out a certain number of checks, while executing the applets, such as:                memory access check: upon each read or write in a memory area, the virtual machine verifies the right of access by the applet to the corresponding data;        dynamic verification of the data types: upon each instruction from the applet, the virtual machine verifies that the constraints on the data types are satisfied. By way of example, the virtual machine may apply special processing to data such as valid memory addresses, and prevent the applet generating invalid memory addresses by way of integer/address conversions or arithmetic operations on the addresses;        detection of stack overflows and of illegal accesses to the execution stack of the virtual machine, which, under certain conditions, are likely to disturb the operation thereof, to the point of circumventing the preceding check mechanisms.
This second solution allows execution of a wide range of applets under satisfactory security conditions. However, it presents the drawback of a considerable slowing of the execution, caused by the range of dynamic verifications. In order to obtain a reduction in this slowing effect, some of these verifications can be managed by the microprocessor itself, at the cost, however, of an increase in the complexity thereof and thus of the cost price of the embedded system. Such verifications furthermore increase the random-access and permanent memory requirements of the system, because, of the additional type information which must be associated with the data handled.
A third solution consists in carrying out a static verification of the code of the applet during the downloading.
In this solution, this static verification simulates the execution of the applet at the level of the data types and establishes, once and for all, that the code of the applet complies with the rule of data types and of access control imposed by the virtual machine and does not cause a stack overflow. If this static verification is successful, the applet can then be executed without it being necessary dynamically to verify that this rule is complied with. In the event that the static verification process fails, the embedded system rejects the "applet" and does not allow its subsequent execution. For a more detailed description of the abovementioned third solution, reference could usefully be made to the work published by Tim LINDHOLM and Frank YELLIN quoted above, to the article published by James A. GOSLING entitled "Java Intermediate Byte Codes", proceedings of the ACM SIGPLAN, Workshop on Intermediate Representations (IR'95), pages 111-118, January 1995, and to the U.S. Pat. No. 5,748,964 granted on May 5, 1998.
Compared with the second solution, the third solution presents the advantage of a much more rapid execution of the applets, since the virtual machine does not carry out any verification during execution.
The third solution, however, presents the drawback of a process of static verification of the code which is complex and expensive, both in terms of size of code necessary to conduct this process and in terms of size of random-access memory necessary to contain the intermediate results of the verification, and in terms of computation time. By way of illustrative example, the code verification incorporated in the JAVA JDK system marketed by SUN MICROSYSTEMS represents about 50 kbytes of machine code, and its consumption in terms of random-access memory is proportional to (Tp+Tr)×Nb, where Tp designates the maximum stack space, Tr designates the maximum number of registers and Nb designates the maximum number of branch targets used by a subroutine, also commonly called method, of the applet. These memory requirements greatly exceed the capacities of the resources of most present-day embedded data-processing systems, especially of commercially available microprocessor cards.
Several variants of the third solution have been proposed, in which the publisher of the applet sends to the verifier, in addition to the code of the applet, a certain amount of specific supplementary information such as precalculated data types or preestablished proof of correct data typing. For a more detailed description of the corresponding procedures, reference could usefully be made to the articles published by Eva ROSE and Kristoffer HØGSBRO ROSE, "Lightweight Bytecode Verification", proceedings of the Workshop on Formal Underspinning of JAVA, October 1998, and by George C. NECULA, "Proof-Carrying Code", Proceedings of the 24th ACM Symposium on Principles of Programming Languages, pages 106-119, respectively.
This supplementary information makes it possible to verify the code more rapidly and slightly to reduce the size of the verification program code but does not make it possible, however, to reduce the requirements for random-access memory, and even increases them, very substantially, in the case of the correct-data-typing preestablished-proof information.

Method for transforming and verifying downloaded program fragments with data type restrictions and corresponding system


A card-shaped memory device includes first to third chips which are stacked together on a first surface of a substrate. The first chip has a control function, the second chip has a memory function, and the third chip has an IC card function. The third chip is located in a position other than the lowest one of the positions of the first to third chips.

1. Field of the Invention
The present invention relates to a card-shaped memory device such as a memory card, which incorporates multiple IC chips.
2. Description of the Related Art
A small memory card serving as a data storage medium for, e.g., a digital camera or cell phone has been developed. The memory card can exchange data with a host device, such as the digital camera or cell phone, while it is inserted in the host device. The memory card comprises a circuit substrate on which, e.g., a nonvolatile semiconductor memory chip and a memory controller chip are mounted, and a package accommodating the circuit substrate. Memory cards having increasingly smaller size and greater memory capacity have been produced in accordance with which, techniques have been developed by which the memory chips are incorporated into the memory card and stacked together (as disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publications Nos. 2001-160125, 2000-123141 and 11-204720).
In recent years, the functions of memory cards have diversified. As a result, as well as a data storage function, a memory card is required to have a so-called IC card function which enables it to double as a financial card such as a credit card, cash card or prepaid card, and an ID card such as a driving license or passport.
It is necessary to reliably prevent a chip having such an IC card function from being broken by stress when the memory card is manufactured or used, since it stores vital data such as accounting information.
Furthermore, since the chips incorporated in the memory card have different functions, it is required that each chip be easily manufactured and easily testable during manufacture.

Card-shaped memory device incorporating IC card function


The invention relates to compositions and methods useful in the detection of nucleic acids using a variety of amplification techniques, including both signal amplification and target amplification. Detection proceeds through the use of an electron transfer moiety (ETM) that is associated with the nucleic acid, either directly or indirectly, to allow electronic detection of the ETM using an electrode.

The detection of specific nucleic acids is an important tool for diagnostic medicine and molecular biology research. Gene probe assays currently play roles in identifying infectious organisms such as bacteria and viruses, in probing the expression of normal genes and identifying mutant genes such as oncogenes, in typing tissue for compatibility preceding tissue transplantation, in matching tissue or blood samples for forensic medicine, and for exploring homology among genes from different species.
Ideally, a gene probe assay should be sensitive, specific and easily automatable (for a review, see Nickerson, Current Opinion in Biotechnology 4:48-51 (1993)). The requirement for sensitivity (i.e. low detection limits) has been greatly alleviated by the development of the polymerase chain reaction (PCR) and other amplification technologies which allow researchers to amplify exponentially a specific nucleic acid sequence before analysis as outlined below (for a review, see Abramson et al., Current Opinion in Biotechnology, 4:41-47 (1993)).
Sensitivity, i.e. detection limits, remain a significant obstacle in nucleic acid detection systems, and a variety of techniques have been developed to address this issue. Briefly, these techniques can be classified as either target amplification or signal amplification. Target amplification involves the amplification (i.e. replication) of the target sequence to be detected, resulting in a significant increase in the number of target molecules. Target amplification strategies include the polymerase chain reaction (PCR), strand displacement amplification (SDA), and nucleic acid sequence based amplification (NASBA).
Alternatively, rather than amplify the target, alternate techniques use the target as a template to replicate a signalling probe, allowing a small number of target molecules to result in a large number of signalling probes, that then can be detected. Signal amplification strategies include the ligase chain reaction (LCR), cycling probe technology (CPT), and the use of "amplification probes" such as "branched DNA" that result in multiple label probes binding to a single target sequence.
The polymerase chain reaction (PCR) is widely used and described, and involve the use of primer extension combined with thermal cycling to amplify a target sequence; see U.S. Pat. Nos. 4,683,195 and 4,683,202, and PCR Essential Data, J. W. Wiley & sons, Ed. C. R. Newton, 1995, all of which are incorporated by reference.
Strand displacement amplification (SDA) is generally described in Walker et al., in Molecular Methods for Virus Detection, Academic Press, Inc., 1995, and U.S. Pat. Nos. 5,455,166 and 5,130,238, all of which are hereby incorporated by reference.
Nucleic acid sequence based amplification (NASBA) is generally described in U.S. Pat. No. 5,409,818 and "Profiting from Gene-based Diagnostics", CTB International Publishing Inc., N.J., 1996, both of which are incorporated by reference.
Cycling probe technology (CPT) is a nucleic acid detection system based on signal or probe amplification rather than target amplification, such as is done in polymerase chain reactions (PCR). Cycling probe technology relies on a molar excess of labeled probe which contains a scissile linkage of RNA. Upon hybridization of the probe to the target, the resulting hybrid contains a portion of RNA:DNA. This area of RNA:DNA duplex is recognized by RNAseH and the RNA is excised, resulting in cleavage of the probe. The probe now consists of two smaller sequences which may be released, thus leaving the target intact for repeated rounds of the reaction. The unreacted probe is removed and the label is then detected. CPT is generally described in U.S. Pat. Nos. 5,011,769, 5,403,711, 5,660,988, and 4,876,187, and PCT published applications WO 95/05480, WO 95/1416, and WO 95/00667, all of which are specifically incorporated herein by reference.
The ligation chain reaction (LCR) involve the ligation of two smaller probes into a single long probe, using the target sequence as the template for the ligase. See generally U.S. Pat. Nos. 5,185,243 and 5,573,907; EP 0 320 308 B1; EP 0 336 731 B1; EP 0 439 182 B1; WO 90/01069; WO 89/12696; and WO 89/09835, all of which are incorporated by reference.
"Branched DNA" signal amplification relies on the synthesis of branched nucleic acids, containing a multiplicity of nucleic acid "arms" that function to increase the amount of label that can be put onto one probe. This technology is generally described in U.S. Pat. Nos. 5,681,702, 5,597,909, 5,545,730, 5,594,117, 5,591,584, 5,571,670, 5,580,731, 5,571,670, 5,591,584, 5,624,802, 5,635,352, 5,594,118, 5,359,100, 5,124,246 and 5,681,697, all of which are hereby incorporated by reference.
Similarily, dendrimers of nucleic acids serve to vastly increase the amount of label that can be added to a single molecule, using a similar idea but different compositions. This technology is as described in U.S. Pat. No. 5,175,270 and Nilsen et al., J. Theor. Biol. 187:273 (1997), both of which are incorporated herein by reference.
Finally, U.S. Pat. Nos. 5,591,578, 5,824,473, 5,770,369, 5,705,348, and 5,780,234, and PCT application WO98/20162 describe novel compositions comprising nucleic acids containing electron transfer moieties, including electrodes, which allow for novel detection methods of nucleic acid hybridization.

Amplification of nucleic acids with electronic detection


An improved method and apparatus for producing an extremely fine micron and sub-micron size water mist using an electronic ultrasonic device that produces the mist at ambient-pressure and delivering the mist for application in suppressing fire. A piezoelectric transducer is arranged to produce a water mist having at least a portion of sub-micron size droplets. The water mist is produced by high frequency pressure waves or ultrasonic waves of predetermined or variable frequency, including frequencies which may exceed 2.5 MHz. The water mist is directed to a firebase to be self-entrained by the fire's flame. The momentum provided the water mist in directing the mist is minimized to enhance the ability of the fire to entrain the mist, and the flow of the carrier medium is usually directed tangentially about the water fountain creating the mist. Further, the throughput and concentration of the mist is controlled to ensure that the entrained mist will be sufficient to cool and suppress the fire. The water mist may be effectively utilized for mitigating blast and reducing over pressures. The fine water mist may also be utilized for humidification because of its fast vaporization and efficient cooling behavior. The apparatus may be modified in its physical design and direction of output, and the method may be modified by adjusting the throughput of mist, composition of mist, concentration of mist, and momentum of mist, whereby fire may be suppressed under many different scenarios.

1. Field of the Invention
The present invention relates to suppression of fire by extremely fine droplet water mist and more particularly, but not by way of limitation, to an improved method and apparatus for producing an extremely fine sub-micron size water mist using an electronic ultrasonic device that produces the mist at ambient-pressure and delivering the mist for application in suppressing fire.
2. Description of the Prior Art
Water based fire suppression systems have been in existence for many years. However, such systems were mostly replaced and the technology forgotten because of the advent of halon gas systems in the 1960's. In recent years, it has been discovered that halon gas is not environmentally safe, and its continued use has been banned due to its alleged potential to deplete ozone in the atmosphere. Thus, there is an urgent need for an alternative fire suppression system, which is effective and environmentally friendly and safe to use.
Because of several favorable properties, water mist has been reconsidered as a potential agent to replace halon gas. Water is environmentally friendly with no known toxic properties. Water has a specific heat of 4.18 J/g, and a high latent heat of vaporization of 2260 J/g that assist in cooling a flame. Finally, water is readily available and cost efficient.
Water mist suppresses fire through different mechanisms. Each mechanism exhibits a different degree of influence on the overall suppression efficiency of a water mist. The four important operating mechanisms are heat extraction, oxygen displacement, radiant heat attenuation, and dilution of the vapor/air mixture. Heat extraction and cooling of the flame has the maximum effect on the efficiency of fire suppression and the other mechanisms usually supplement the heat extraction mechanism. The inventors have found through computer simulation and experimentation that the success of water mist in its application to fire suppression depends on the ability to produce nearly nanometer-scale and sub-micron size droplets of water mist and deliver the mist to various fire scenarios. Extremely small droplets vaporize instantaneously and absorb energy to extract heat from the flame. Water mist droplets of larger diameters vaporize more slowly and are not as efficient in suppressing fires. Also, larger droplets are not as easily entrained into the fire and need additional momentum if the mist has to be introduced away from the firebase.
An extremely small amount of water is needed for suppressing a fire using extremely small sub-micron droplet mist because of considerable volume expansion accompanied by the transition from liquid state to mist (about 1700 times). This water expansion is based on the ratio of the density of liquid water and the gas-like nanoscale mist.
An extremely fine mist of sub-micron size water droplets avoids several of the disadvantages normally associated with the conventional water mist fire suppression technology. For instance, typical water mist applications having larger droplet size may cause a kinetic effect on flames causing flare-up from the water droplets striking the fuel surface. Further, because of slower vaporization and greater momentum needed, larger droplets wet surfaces within the area of application, conduct electricity and often damage items. Thus, a key to the success of water mist technology is the use of very fine nanometer-scale sub-micron water mist produced using a cost-effective and ambient-pressure method.
Previously, fine water mist production for fire suppression has been an expensive technology in terms of installation and maintenance. These prior art systems have included one or more expensive components such as high pressure storage of fluids, conduit pipes often under high pressure, and pumps providing pressurized fluid to specialized atomizer nozzles. Besides the expense of the components these components and conduit piping require valuable space for installation. Space may be limited for certain applications such as marine vessels, machine space, and computer data centers.
In addition to the expense of installing known water mist fire suppression systems, these systems present safety and mechanical concerns. In particular, pressurized systems are subject to leaks and hazards of bursting posed by retaining fluids under pressure. These systems require nozzles that are subject to clogging because of the small nozzle diameters and are also expensive and difficult to construct because of their precise specifications.
Even with state-of-the-art mechanical atomizers, the droplet size obtainable in these prior art systems is on the order of 50–200 microns. For many applications, these droplets are effective in cooling the flame. However, the water mist droplets may still wet surfaces and cause electrical conductance. This limits the ability to use water mist fire suppression in computer and data center applications or in precious item preservation rooms in libraries and museums. Moreover, the mechanical atomization technology required by conventional fine water mist fire suppression systems is still very expensive.
The prior art mist generation methods for fire suppression involve well-documented methods such as pressurized water or twin-fluid atomizers. Single fluid pressure based atomizers use water stored or pumped at high pressure (40 to 200 bar) and spray nozzles with relatively small orifice sizes. Twin-fluid systems use air, nitrogen, or other gases to atomize water at a nozzle. Although rare, there are some references to utilization of extremely high (hypersonic velocity) gas streams to generate ultrasonic waves to generate mist for suppressing fires and explosions. For instance, U.S. Pat. No. 4,378,851 to Egbert deVries describes ultrasonic nozzles of a general type in which a gas orifice penetrates a liquid filming surface. The method uses a high velocity gas stream to shear the thin layer of liquid and atomizing it. Others, U.S. Pat. Nos. 5,211,336 and 5,323,861, teach a method of producing a mist using a compressed air stream, and U.S. Pat. No. 5,597,044 teaches using a carrier gas having supersonic velocity. All the prior methods use either pressurized water or compressed gas as means of atomizing water to produce a water mist. As a result, these prior technologies produce atomized water mist using mechanical means that are not user friendly and are not very economical for generating water mist for fire suppression.
Thus, an objective of this invention is to provide a water mist fire suppression method using an electronic ultrasonic device to produce a water mist having sub-micron diameter water droplets.
Another objective of the invention is to provide a fire suppression device using an electronic ultrasonic device to produce a water mist and optionally powered by line fed electric power or a portable power source such as a battery.
Another objective of the invention is to provide a fire suppression method using a mist generation method that does not need pressurized water or gas.
Another objective of the invention is to use a method of generating mist for fire suppression that does not use an atomizing nozzle and is free from nozzle clogging and flow blockage.
Another objective is to provide a device and method to deliver a sub-micron diameter mist to a fire such that the mist that is entrained by the fire.
Another objective is to provide a mist for fire suppression without mechanically imparting excessive momentum to the mist.
Another objective is to provide a mist for fire suppression in which the mist is introduced from the base of the fire.
Another objective is to minimize water usage and the quantity of mist needed to suppress a fire by delivering the mist to the most reactive zone in the fire base using very low injection velocity.
Another objective is to reduce the quantity of water needed for suppressing a fire by several orders of magnitude compared to conventional mists by using water mist having submicron diameter droplets.
Another objective is to deliver a sub-micron mist to a fire such that the mist will vaporize before impact with surface areas and not wet surface areas or equipment.
Another objective is to provide a tangential flow of air or gas for carrying the mist out of the mist generator without affecting the centerline mist producing water fountain.

Fire suppression using water mist with ultrafine size droplets


An apparatus and method for extruding, cooling and cutting can include an extruder for producing an extrudate which can be fed through appropriate sizing, support and cooling devices, which can include a vacuum chamber, cooling chamber, and calibrators, which can have internal cooling passageways. The apparatus can also include a cutting blade, a programmable temperature controller for controlling the temperature of the extrudate prior to being cut by the cutting blade, and a temperature sensor, which can be positioned near the cutting blade and provide feedback to the temperature controller. The method can include sensing the temperature of the extrudate, at a point near the cutting blade, after it is fed through the sizing, support and cooling devices and before being cut. Such feedback can be used to control the temperature of the extrudate such that the extrudate is maintained within a desired range of temperature as it is cut. The temperature controller can automatically cool and maintain the extrudate within a desired range of temperatures using the temperature feedback at the point near the cutting blade. Where calibrators are used the apparatus can include additional temperature sensors at different sides of a multi-sided extrudate at a point near where the extrudate exits the calibrator. Such additional temperature feedback can be used by a temperature controller to adjust the temperature of the extrudate, and also at different surfaces of a multi-sided extrudate.

The invention relates generally to the extrusion and cutting of thermoplastic material, and more particularly to using feedback from a temperature sensor to provide control over the cooling rate of the extruded material to improve the process of cutting the extrusion.
Methods and systems are known the art for simultaneously producing and cutting a thermoplastic extrusion in a continuous process. For example, the apparatus may include an extruder to produce a continuous extrusion, whether hollow or solid. In association with the extruder, such apparatus may include a vacuum chamber, in the case of hollow extrusions, and a cooling chamber to cool the extrudate as it is extruded. A belt or rollers may also be provided to feed the extrudate from the extruder to a cutting blade which can cut the extrudate to desired lengths. The vacuum chamber can help support a hollow extrusion until it is sufficiently cooled to maintain its shape. Where the extrusion is solid or semi-hollow (such as a channel), one or more devices known as calibrators can be used in place of the vacuum chamber in order to align and size the extrusion as it is produced and until sufficiently cooled. The calibrators can have internal passageways forming cooling circuits through which coolant can be circulated to cool the extrudate as it passes through the calibrators. Such known apparatus can further include a cooling chamber, which can be partially or completely filled with coolant to cool the extrudate as it passes through the chamber. Alternatively, instead of immersing the hot extrudate in coolant, the cooling chamber can have spray nozzles which spray the extrudate with the coolant to effect the cooling process. The cooling processes in the vacuum chamber, calibrators and the cooling chamber can be controlled by conventional electronic devices in a known manner which is described in more detail below.
The conventional method can include feeding a continuous hot extrudate from the extruder through a vacuum chamber, or calibrators, and then to a cooling chamber which cools the hot extrudate to a desired temperature. Although the vacuum chamber and calibrators provide some initial cooling, the cooling is mainly provided in the cooling chamber. From the cooling chamber the cooled extrudate is fed to cutting blades which can cut the cooled extrudate into sections of the desired lengths. The temperature of the extrudate when cut by the cutting blades can be crucial to obtaining an acceptable product. If the temperature of the extrudate is either too hot or too cold when it is cut, the cut sections can be of unacceptable quality. For example, if the extrudate is too cold when cut, deformation or fracturing can occur. Conversely, if the extrudate is too hot when cut, the ends of the cut sections may stick together. In additional to problems with the cut parts, the extrudate may warp if the temperature is not controlled properly. Consequently, it can be vital to control the temperature of the extrudate to prevent warping and so that it is within a certain desired range of temperatures at the point where it is cut by the cutting blade in order to produce products of an acceptable quality. In order to obtain the proper temperature of the extrudate at the point of cutting, the conventional manner is based upon a manually performed trial-and-error process. For example, a certain temperature is estimated and the cooling chamber is brought to that temperature. Next, the quality of the cut is closely observed to determine whether the temperature of the extrudate is too hot or too cold. If the cutting process indicates that the temperature of the extrudate is too hot, the temperature in the cooling chamber is lowered, typically in a small increment to avoid overshooting the desired temperature. After the temperature adjustment has had an opportunity to take effect, the cutting process is again closely observed to determine whether the appropriate temperature has been achieved. If the cut quality again indicates that a temperature adjustment is needed, the process is repeated by adjusting the temperature in the cooling chamber and observing the cut quality. This procedure may be repeated over and over until the cut quality indicates that the proper temperature has been achieved. In addition to the time required to arrive at the desired temperature, material is wasted with each cut that produces unacceptable parts until the proper temperature is finally achieved.
Accordingly, there is a need for an improved apparatus and method for bringing the extrudate to the proper temperature in a more efficient and less wasteful manner.
An apparatus and method for extruding and cutting an extrusion can be provided which more quickly and efficiently brings a hot extrudate to the temperature required to permit the extrudate to be properly cut. The apparatus can include an extruder for producing a continuous extrusion which can be fed through a vacuum chamber, or calibrators, a cooling chamber which brings the extrudate to the desired temperature, and a cutting blade for cutting the extrudate into desired lengths. The apparatus can include a temperature controller for controlling the temperature in the cooling chamber. The temperature controller can include a programmable processor for automatically regulating the temperature in the cooling chamber. According to a presently preferred embodiment, the apparatus can include a temperature sensor which can be positioned near the cutting blade to provide feedback on the temperature of the extrudate at a point near the cutting blades. Such feedback can be provided to the temperature controller which can use the feedback information to control the temperature in the cooling chamber. Similarly to the conventional manner, the cut quality can be observed to determine when an acceptable temperature has been arrived at. In contrast however, the temperature at the cooling chamber can be regulated directly from the actual temperature of the extrudate near the cutting blade, instead of simply gradually adjusting the temperature up and down based upon what the cut looks like, as in the trial-and-error method. Also, once a proper temperature has been arrived at, that information can be stored in a memory portion of the processor in the temperature controller, which can then use that information as a reference point in the future each time the process is carried out using the same materials and cutting conditions. Thus, no observation of the cut quality need normally be done to start running the process the next time and the system can automatically adjust to changes in ambient temperatures. In order to ensure that the temperature of the extrudate is within a desired range of temperatures at the point at which the extrudate is cut by the cutting blade, the temperature controller can continuously monitor feedback from the temperature sensor near the cutting blade. Any necessary adjustments in the temperature can be automatically carried out by the temperature controller, thus eliminating much, if not all, of the manual adjustments previously required according to the prior art method.
Moreover, where calibrators are used additional temperature sensors can be utilized in conjunction with cooling circuits provided in the calibrators. The temperature feedback from such sensors can be provided to a temperature controller which can use such feedback to control the temperature of the coolant circulated through the aforementioned cooling circuits. Besides being used to generally control the cooling of the extrudate, similarly to as described in connection with the cooling chamber, this feedback information and temperature control can advantageously permit different surfaces of a multi-sided extrudate to be cooled at different rates.
Other details, objects, and advantages of the invention will become apparent from the following detailed description and the accompanying drawings figures of certain embodiments thereof.

Apparatus and method for producing and cutting extruded material using temperature feedback


An efficient method for codebook search, employed in speech coding, uses an optimal pulse-position grouping and a split track arrangement, based on a likelihood estimator. Also disclosed are codecs, mobile voice communication devices, telecommunications equipment and telecommunications methods.

One common objective of communication technology is to transmit information using a minimum number of bits, without losing important intelligence, by removing the redundancies in the original information. In the wireline/wireless speech communication field, advancements in speech compression have resulted in compression ratios of 1:10 or better. This compression is typically implemented using speech codecs (encoder and decoder) that use signal transformations. However, these transformations also increase the processing complexity required to encode and decode voice signals. This complexity can add a significant cost to enhancements providing higher channel density on an existing backbone. Hence, in practice, there is a trade-off between the computation complexity (based on the compression technique) and degradation in speech quality.
The Code-Excited-Linear-Prediction (CELP) is one of the techniques used in speech codecs that currently offers an optimal performance in the quality-complexity space. Several alternate realizations of CELP have been brought forward such as Algebraic CELP (ACELP), Qualcomm CELP (QCELP), Relaxed CELP (RCELP), and others, with varying degrees of complexity. Currently, the ACELP realization is widely used, since it avoids the larger memory requirements of CELP. ACELP aims at searching the best codebook excitation vector by minimizing the Mean Square Error (MSE) or maximizing the correlation between the weighted speech signal and the weighted synthesized speech signal.
In typical ACELP codec standards such as ITU-T G.729A/B, GSM-EFR, GSM-AMR, TIA/EIA-EVRC the maximum complexity lies in a single place—the random excitation codebook search, which may be up to one third of a codec encoder operational capacity. Accordingly, reduction of the complexity of a codebook search can significantly increase the capacity of a codec without adding cost.

Apparatus, methods and articles incorporating a fast algebraic codebook search technique


Internal servo loop circuitry is included on the same chip (10C) with an ADC (10B). Automatic test equipment (12) operates with the internal servo loop circuitry and external servo loop circuitry (1B) to test the ADC. The internal servo loop circuitry includes a target register (14), a digital comparator (18), and a crossover counter (22). An integrator (32) responsive to the digital comparator (18) produces an input signal (Vin) to the ADC, which generates a corresponding digital output sample (Dout). The comparator compares the output sample with a target code in the target register and causes the direction of the input signal to reverse each time the digital output sample crosses over the target code. The counter causes a voltmeter to measure a transition voltage value of the input voltage after a predetermined number of crossovers.

The present invention relates generally to servo loop hardware utilized in testing integrated circuit chips, and more particularly to utilizing additional logic circuitry provided on ADC (analog to digital converter) chips being tested as part of the servo loop hardware, the remaining portion of the servo loop hardware being provided in a test board external to the ADC chips.
Referring to FIG. 1, prior art ADC test system 100A includes computer-controlled automatic test equipment (ATE) 12, which can be implemented by means of any of a variety of commercially available automatic (i.e., computer-controlled) integrated circuit chip test systems. Automatic test equipment 12 is coupled by control conductor 16A, digital bus 16, control conductor 17, digital bus 24, and control conductor 23 to a "special test board" 1A into which a DUT (device under test) 10A is plugged. An ADC chip 10 to be tested is included in DUT 10A. DUT 10A can also include control circuitry and interface circuitry etc. Special test board 1A also is referred to herein as "servo loop board 1A", and includes a target code register 14, an ADC data register 15, a digital comparator 18, and an integrator 32. Target register 14 has a digital output bus 20 connected to one input of digital comparator 18. ADC data register 15 has a control input connected to control conductor 17 and a digital input connected to digital bus 24. Digital bus 24 is also connected to the digital output of ADC 10 in DUT 10A. ADC data register 15 has a digital output bus 19 connected to another input of digital comparator 18. ADC 10 can, for example, be a 12 bit ADC, in which case the various digital buses are 12 bit buses. The output of digital comparator 18 is connected by conductor 26 to a control terminal of a single pole, double throw switch circuit S1 in integrator 32. Integrator 32 also includes an operational amplifier 30, an integrating capacitor C, a current source −I and another current source +I. The pole terminal of switch circuit S1 is connected by conductor 29 to the (−) input of operational amplifier 30 and to one terminal of integrating capacitor C, the other terminal of which is connected by conductor 25 to the output of operational amplifier 30 and to the input of ADC chip 10. Conductor 25 also is connected to the voltage measuring terminal of a precision voltmeter 34 which is included in automatic test equipment 12. One terminal of switch circuit S1 is connected to current source −I so that a constant current flows out of that terminal to ground. The other terminal of switch S1 is to receive a constant current from current source +I. The voltage Vin on conductor 25 produced by integrator 32 thus ramps up when switch S1 connects conductor 29 to current source −I and ramps down when switch S1 connects conductor 29 to current source +I.
Automatic test equipment 12 can be a very complex, expensive automatic test system or it can be a relatively simple, inexpensive system. Every differently designed ADC chip requires an associated unique "servo loop board" such as 1A which must be designed to interface between the automatic test equipment 12 and the ADC chip 10 to be tested.
A common method for testing a ADC device is to use a "servo loop method". This method is widely used because it reduces the amount of required testing time, averages out noise in the system, and thereby increases the accuracy and repeatability of the test results. For the servo loop method, special servo loop boards which may be very expensive (for example, as much as $3000 each) are required, and in some cases they may not even be available.
When the analog input voltage Vin on conductor 25 is applied to integrated circuit ADC chip 10 in the course of testing it in the prior art system of FIG. 1, the digital output code Dout which is produced by ADC chip 10 has been influenced by noise that inevitably is present in servo loop board 1A, including noise present on the digital bus 24, on power supply conductors (not shown), and on the analog signal Vin applied to the input of ADC 10.
It should be understood that conventional ADC test system 100A measures the values of analog input "transition voltages" of Vin in response to which the ADC digital output signal Dout on bus 24 switches from each digital output level to the next higher digital output level (or to the next lower digital output level). Testing and/or characterization of integrated circuit ADCs is based on the values of such transition voltages. The analog voltage is ramped up and down, and the transition voltage measurement begins when the input signal Vin has "oscillated" up and down around the actual transition voltage for a sufficient amount of time. The sufficient amount of time before starting each transition voltage measurement, i.e., the waiting time before starting the measurement by voltmeter 34, typically should be based on a worst-case ADC testing scenario, for example a scenario in which the initial input voltage Vin applied to the ADC is far from the actual transition voltage. In this worst case scenario, the integrating time before Vin reaches the actual transition voltage will be a long time. The selection of the actual waiting time before starting the voltmeter measurement should be based on that long time. After all of the appropriate transition voltages for the ADC have been measured, converted to digital representations thereof, and stored for future use, then the needed characteristics of the ADC chip can be computed and compared to appropriate reference values to determine if the ADC chip performance is acceptable.
As an example, after an initial target code value has been loaded into target code register 14, the analog input voltage Vin of ADC chip 10 is ramped up (or down) to a voltage level corresponding to the present target code in target code register 14, and ADC chip 10 generates corresponding values of Dout. The corresponding value of Dout might be greater than the present target code value. The purpose of the servo loop is to lower (or increase) the analog input signal Vin until ADC chip 10 provides a value of Dout that is lower than (or greater than or equal to) the target code value in register 14. When this happens, the servo loop reverses the direction of change of Vin on conductor 25, causing it to increase (or decrease).
Vin is repeatedly ramped up and down around the average transition voltage in this manner, depending on the resulting noise-dependent values of the ADC output code Dout. Dout may, for example, be 1-3 LSB (least significant bit) values above or below the present target code value. The number of times Dout "crosses over" from below the present target code value to above that value and vice versa depends on the particular test system and DUT noise levels therein, but a somewhat typical number of crossover times might be 8, depending on the resolution of ADC chip 10. After that number of crossovers has occurred, analog voltmeter 34 makes a relatively slow measurement of Vin over a sufficiently long period (e.g., 20 milliseconds) so as to provide a precise transition voltage wherein the ramping up and down of the input Vin and the various noise components have been averaged. The values of the transition voltage measured by analog voltmeter 34 in automatic test equipment 12 are stored in a memory (not shown) for use in subsequent computations. (For example, the DNL (differential nonlinearity) and INL (integral nonlinearity) characteristics of the ADC can be computed using the transition voltages.) Then another value of the target code is loaded into target code register 14 and the foregoing process is repeated for a desired number of additional target code values.
The increments of Vin which cause each of the one-LSB changes in Dout should be identical, but as a practical matter they are not. The differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics indicate the extent to which the LSB changes are not identical. The difference of the LSB change in each value of Dout from the average LSB change of Dout is the differential nonlinearity DNL. An ideal value of both of the DNL and the INL of an ADC is zero, but as a practical matter some values of the differential nonlinearity can be 10 to 90% greater than or less than the average LSB value. For example, the DNL for this particular code might be 20% greater than average, i.e., +0.2 LSB greater than the average (or −0.2 LSB less than average).
To calculate the differential nonlinearity for every value of Dout, it is necessary to have the values of all of the upper side transition voltages and lower side transition voltages of ADC 10 so that for any particular value of Dout the upper side transition voltage and lower side transition voltage both are captured and stored for subsequent use in the conventional ADC chip testing process. As an example of measurement of an "upper side transition voltage", assume that for a particular value of Vin the ADC performs a conversion and produces a value of Dout equal to 10. Assume that as Vin continues to ramp up a bit more, the ADC produces another conversion of the slightly larger value of Vin, and the result of that conversion is the same value of Dout equal to 10. The ramping up of Vin continues a bit more, and this time the ADC converts a value of Vin to a Dout value of 11. That means the "upper side transition voltage" or "upper border" associated with the Dout value of 10 has been crossed. That causes the output state of digital comparator 18 to change, thereby reversing the direction of ramping of Vin.
Similarly, as an example of measurement of a "lower side transition voltage", assume that for a particular value of Vin the ADC performs a conversion and produces a value of Dout equal to 10. Assume that as Vin continues to ramp down a bit more, the ADC produces another conversion of the slightly smaller value of Vin, and the result of that conversion is the same value of Dout equal to 10. The ramping down of Vin continues a bit more, and this time the ADC converts a value of Vin to a Dout value of 9. That means the "lower side transition voltage" or "lower border" associated with the Dout value of 10 has been crossed. That causes the output state of digital comparator 18 to change, thereby reversing the direction of ramping of Vin.
FIG. 2 shows the waveforms "LOAD TARGET CODE" on conductor 16A, "CONVERT" on conductor 23 and the resulting "Dout SAMPLES" on bus 24, the comparator output "COMP OUT" on conductor 26, and "Vin" generated by integrator 32 on the input conductor 25 of ADC 10. The "LOAD TARGET CODE" waveform indicates times at which a new target code is loaded by automatic test equipment 12 into target code register 14. The COMP OUT waveform indicates the outputs generated by digital comparator 18 on conductor 26 in response to comparison of the Dout samples on bus 24 which have been loaded into ADC data register 15 and applied to one input of digital comparator 18. Each change in the COMP OUT waveform in FIG. 2 causes integrator 32 to reverse the direction of the ramp signal Vin produced on ADC input conductor 25. At time T1 in FIG. 2, automatic test equipment 12 has made a decision to cause analog voltmeter 34 to begin measuring the "transition voltage".
A problem with the system of Prior art FIG. 1 is that sufficient time must be allowed for the above mentioned "worst case" scenario for testing any DUT, and that worst case amount of time may be two or three times as long as the amount of time required for testing a typical DUT of the same kind. The voltmeter measurement during an interval T2 is lengthy because the integrator output voltage Vin on conductor 25 is continuously ramping up and down. Also, longer voltmeter measurement times ensure adequate averaging of the noise that is inherently present on Vin conductor 25 of servo loop board 1A due to the fact that the conductors of Dout bus 24 are changing state after the ADC conversions and imparting noise into the test board. At the end of the voltmeter averaging measurement, which occurs at time T2, a new target code is loaded into target register 14 by automatic test equipment 12, and the foregoing process then is repeated for the new target code.
Note that in FIG. 1, the ADC chip sends out the acquired ADC data Dout via bus 24 to the test system 12 to control the servo loop. The large amount of noise resulting from digital communication of Dout from ADC 10 to the input of digital comparator 18 can result in substantial inaccuracy in the measurement of the above described transition voltages. Consequently, analog voltmeter 34 may need to average its measurement over a much longer time (i.e., a much larger number of ADC conversion times) than would be necessary in the absence of such noise. That noise is added to other electrical noise present on the final test board and contributes substantially to the inaccuracy of each value of Dout produced during the testing of ADC chip 10. This noise can also affect the performance of any additional DUTs of the same kind if they are simultaneously tested on the same servo loop board IA. Another problem is that a substantial amount of time, e.g. 10 microseconds, may be required to send the digital conversion results from ADC 10 to digital comparator 18 if the servo loop board 1A is implemented by means of a slow data bus, such as a data bus having an I2C data format.
Other available servo loop boards are specially designed for specific automatic test equipment and/or a specific ADC. Such servo loop boards are expensive. Even more expensive general purpose servo loop boards are available, but they typically need adjustments in order to be operable when plugged into final test boards for automatic test equipment. For example, the servo loop user interface, speed, or signal levels of the general purpose servo loop board may not match those used on the DUT to conduct the ADC conversion result Dout to one input of the digital comparator of such a general purpose servo loop board. Also, the general purpose servo loop board might not be operable from the available power supply voltage range. Dealing with such incompatibilities between the automatic test system and the general-purpose servo loop board typically is time-consuming for system debugging, and furthermore is very costly. For example, one general purpose servo loop board containing a servo loop costs about $3000.
Thus, there is an unmet need for a way of testing an ADC device or chip that reduces the amount of test hardware required to implement a servo loop test method of testing the ADC.
There also is an unmet need for a way of testing an ADC device or chip that reduces the amount of test hardware required to implement a servo loop test method of testing the ADC and also substantially improves the conversion accuracy of the ADC during the testing.
There also is an unmet need for a way of testing an ADC device or chip that reduces the amount of test hardware required to implement a servo loop test method of testing the ADC and is easily applicable to testing of any ADC and is not limited to a certain ADC resolution, a specific user interface, a specific interface speed, or a specific automatic integrated circuit chip test system.
There also is an unmet need for a way of testing an ADC device or chip that reduces the amount of test hardware required to implement a servo loop test method of testing the ADC and which reduces the amount of time required to test the ADC.
There also is an unmet need for a way of testing an ADC device or chip that reduces the amount of test hardware required to implement a servo loop test method of testing the ADC and also improves ADC test results by eliminating noise on digital communication lines.
There also is an unmet need for a way of testing an ADC device or chip that reduces the amount of test hardware required to implement a servo loop test method of testing the ADC and also reduces test program debugging time.
There also is an unmet need for a way of testing an ADC device or chip that makes it easy for customers to verify ADC performance data supplied by the manufacturer.

On-chip servo loop integrated circuit system test circuitry and method


The present invention is directed to a process for forming a yarn having at least one conductive filament wherein the conductive and nonconductive filaments which make up the yarn are simultaneously co-spun. The present process can be performed at spinning speeds of above about 3500 meters per minute to produce a yarn useful in antistatic carpet production.

1. Field of the Invention
The present invention is directed to a process for forming a yarn useful in forming antistatic carpet. More specifically, the present invention is directed to a process for forming a yarn which includes a plurality of nonconductive filaments and at least one conductive filament. Most specifically, the present invention is directed to a process for forming a yarn wherein the conductive filament or filaments are simultaneously co-spun with the nonconductive filaments.
2. Description of the Prior Art
It is well known that static electricity may be generated when a person walks across a conventional carpet formed from synthetic fibrous materials such as nylon, acrylics, polyester, and the like. The discharge of the static electricity when a person is grounded subsequent to walking across such a carpet can be annoying if not discomforting.
One solution to this problem has been to incorporate electrically conductive fibers (hereinafter referred to simply as conductive fiber) into yarns which are subsequently incorporated into carpets to dissipate static electric charges. These conductive fibers typically include a non-conductive fiber-forming polymer as their major component and a conductive material, usually a dispersion of a conductive particulate material in a polymeric carrier.
The prior art has provided a number of methods for incorporating such a conductive fiber into a yarn to impart antistatic properties. For example, U.S. Pat. No. 4,612,150, to De Howitt, discloses a process for combining antistatic filaments and nylon filaments wherein separately spun conductive bicomponent filaments are pneumatically introduced into a freshly spun nonconductive threadline within the quench chimney. U.S. Pat. No. 4,900,495 to Lin discloses a similar antistatic yarn production process wherein a previously formed conductive filament is combined with freshly spun, nonconductive filaments.
Although these processes are useful in producing acceptable products, they have a number of serious drawbacks. First, this procedure is quite expensive, as the separate formulation of the conductive fiber and its subsequent addition in the threadline can add a significant amount to the end product cost. Also, as the addition of the previously formed conductive filament is at the periphery of the nonconductive threadline, intermingling of the conductive filament with the nonconductive filaments is limited. This limited intermingling can have a negative effect on the subsequent processing of the resulting yarn and can result in severe color pollution (due to visibility of conductive filament). Further, since the conductive filaments and nonconductive filaments were separately formed and have different thermal histories, their individual properties, such as shrinkage and crystalline structure are different. These differences can cause breakage of one or more of the conductive filaments during processing. More specifically, it is noted in the description of the '150 patent found in the '495 patent that the spinning and winding speed of the nonconductive filaments are established so that the conductive filaments will not break when they are drawn at the same ratio as is required for the nonconductive filaments.
A need, therefore, exists for an improved antistatic yarn production process which overcomes these and other deficiencies which are inherent in the prior art processes.

Process for forming a yarn having at least one electrically conductive filament by simultaneously cospinning conductive and non-conductive filaments


The present invention is to provide calixcrown derivatives of formulae 1 to 3 requisite for the preparation of a self-assembled monolayer as well as a process for the preparation thereof. Further the present invention is to provide a self-assembled monolayer which is produced by immersing a gold substrate or related metal substrate in an organic solution containing said calixcrown derivatives of formulae 1 to 3. Still further the present invention provides a process for fixing a protein monolayer by fixing proteins having molecular weight of not less than 20,000D (20KD) on said self-assembled monolayer.

The present invention relates to novel calixcrown derivatives, a process for the preparation thereof, a self-assembled monolayer prepared by using the same and a process for immobilizing a protein monolayer by using the self-assembled monolayer of the novel calixcrown derivatives. In particular, the present invention relates to novel calixcrown derivatives having thiol functions indispensable for the preparation of a self-assembled monolayer of said calixcrown derivatives, which can be applied for immobilization of proteins by multiple ionic recognition. The present invention further relates to a process for the preparation of said novel calixcrown derivatives, a self-assembled monolayer prepared by applying said calixcrown derivatives to a gold substrate or related metal substrate and a process for immobilizing a protein monolayer by using the self-assembled monolayer.
The immobilization of enzymes, antigens, antibodies and the like on solid carriers has become one of the most basic techniques in biotechnology or in protein research, such as immunochemistry and enzyme chemistry. For example, the enzyme linked immunosorbentassay (ELISA) is a technique that has been widely used in biotechnology for the assay of a particular protein or specific proteins causing a certain disease in experimental or clinical laboratories. Assay kits of such ELISA are commercially available in the market. More recently, development of protein chips, which require improved methods of protein immobilization on a solid matrix, is of a great concern in the field of biotechnology for the further advancement of proteomics research in the post-genomic era.
Previously, the immobilization of proteins such as antigens, antibodies or enzymes has been commonly practiced by physical adsorption of said proteins on a high molecular weight biopolymers such as various derivatives of collagen, dextran or cellulose. Covalent bonding between proteins and carrier surface by chemical reaction has been also widely used as a method for protein immobilization. The protein immobilization method by a xe2x80x9cSandwichxe2x80x9d technique (triple-molecular layer) has been disclosed in literature [Science, 1993, Vol. 262, ppl706-1708], which describes a chemical bonding method by the biotin-avidin (or streptoavidin) interaction between proteins and carrier surface. That is, biotin is attached to the carrier surface and subsequently avidin or steptoavidin is linked thereto. Finally, proteins linked with biotin can be immobilized on said chemically modified carrier surface.
However, numerous problems are present in the various methods of protein immobilization described above. The physical adsorption method as well as the methods of covalent bonding and the biotin-avidine binding, which have recently been used, do bear problems as follows.
1. Density
The most critical problem of the protein immobilization method used in the past has been noted as that the amount of protein immobilized on the surface of a substrate is extremely small. When the density of a protein to be immobilized on a carrier surface is low, other proteins may form non-specific binding. It is thus necessary to carry out chemical treatment for the carrier surface so as to eliminate the undesired proteins bound to the carrier surface. However, such a chemical treatment may cause inactivation or denaturation of the immobilized protein molecule. In addition, even if a specific target protein is immobilized successfully onto the surface of a carrier, only an extremely small amount of the protein can be captured and consequently, it is often required that the assay result be further confirmed by various assay methods. It is also noted that the more the amount of proteins is immobilized on an unit area on the surface of a carrier, the easier the assay process is. In this regard, many studies have been carried for the development of methods for a single molecular layer of proteins with the maximum amount immobilized on a carrier surface. A satisfactory result, however, is yet to be achieved.
2. Activity
In prior methods for protein immobilization by either chemical bonding or physical adsorption on surface of a carrier, the activity of an immobilized protein could be decreased in comparison with the free protein in a solution. It has been known as the reason that an immobilized protein on a solid carrier could lose its activity due to conformational changes or denaturation of the protein especially around its active site as it binds tightly to the carrier surface via physisorption or chemical binding.
3. Orientation
In prior methods for protein immobilization on surface of a carrier, an active site of the protein may become essentially oriented toward the carrier surface in such a way that the active site is masked and thus the activity of the protein becomes lost. Such orientation of the protein is also a serious problem in procedures of protein immobilization. It is known that such phenomena is occurred in almost half of the immobilized proteins.
An object of the present invention is to provide calixcrown derivatives having two recognition sites essential as a molecular linker applicable for protein immobilization onto the surface of a carrier, one of which can recognize the ammonium residue of a protein while the other can bind tightly to the surface of a carrier; said calixcrown derivatives are active for the formation of a self-assembled monolayer, which is useful for a- process of protein immobilization solving the problems of prior processes. Another object of the present invention is to provide a process for the preparation of said novel calixcrown derivatives.
A further object of the present invention is to provide a self-assembled monolayer of calixcrown derivatives by binding said calixcrown derivatives on a gold substrate or related metal substrate; said monolayer of calixcrown derivatives can be used for high-density protein immobilization on a monolayer, the surface of which can allow to interact with all kinds of other proteins in a test solution thereof without any additional complicated procedures.
A further object of the present invention is to provide a immobilization process for protein molecules such as antigens, antibodies or enzymes of which the molecular weight are respectively not less than 20,000 D (20KD) on said self-assembled monolayer.
A further object of the present invention is to provide an immobilization process for said protein molecules by applying the compounds of formulae 1 to 3 of the present invention onto inorganic or organic solid substrate such as gold, silver, glass, silicon, polystyrene, polycarbonate, etc. for the preparation of protein chip, diagnostic kit, protein separation pack, etc.

CALIXCROWN DERIVATIVES, A PROCESS FOR THE PREPARATION THEREOF, A SELF-ASSEMBLED MONO-LAYER OF THE CALIXCROWN DERIVATIVES PREPARED BY USING THE SAME AND A PROCESS FOR IMMOBILIZING A PROTEIN MONO-LAYER BY USING THE SELF-ASSEMBLED MONO-LAYER OF THE CALIXCROWN DERIVATIVES


The imaging system converts raw data for an image to formatted data concurrently with compressing the formatted data for the image. The exemplary imaging system includes an image processor for generating blocks of formatted data from raw image data. The exemplary imaging system also includes an image compressor for compressing the blocks of formatted data. The compressor compresses one or more of the blocks while the image processor generates one or more blocks of formatted data.

1. Field
The present invention relates generally to imaging systems and more particularly to processing image data in imaging systems.
2. Background
Imaging devices such as digital cameras typically include an image sensor that generates raw image data. The imaging device converts the raw image data to a format such as the YCbCr format. The formatted data is then compressed to a size suitable for storage. The process of formatting and compressing is a source of the delay between when pictures can be taken by the imaging device. For instance, the camera is often unable to take a second image because the camera is processing the data for a first image. As a result, there is a need for improved processing of image data.


A hydraulic fluid power cylinder assembly 10 includes a cylinder chamber 14, a piston 15, a piston rod 19 and an end cap 21. End cap 21 includes a drift stop chamber 24 and a drift stop blocking surface 25. Chamber 24 is in open fluid pressure communication with chamber 14 under all conditions. Piston 15 includes a piston body portion 16 and a drift stop body portion 29. Drift stop body portion 29 includes a drift stop blocking member 31 and a positioning surface 34 for preventing the blocking member 31 from contacting the walls of cavity 24 and cylinder chamber 14 when disengaged from blocking surface 25. In one position drift stop body portion 29 is received within drift stop cavity 24, and blocking member 31 engages blocking surface 25 to prevent unintended movement of piston 15.

Fluid power cylinder assemblies including, for example, hydraulic cylinder assemblies, are widely used to impart controlled motion to objects in many applications including, for example, construction, agricultural, industrial, aerospace, marine, and land vehicle applications. In some of these assemblies or applications, technical problems may include unintended drift or movement of the piston of the hydraulic cylinder assembly. Such drift may be caused by, for example, forces acting on the piston including weight of the piston and objects connected to it, seal or system leakage, cylinder housing internal surface damage, vibrations, or contamination. Additional technical problems may include alignment, assembly, complexity, cost, and reliability.
Various hydraulic locks may be used to lock and unlock hydraulic cylinders. One prior art fluid power cylinder assembly with a hydraulic lock is shown in U.S. Pat. No. 4,524,676, in which controlled hydraulic pressure in a bore 17 causes a plunger 17 to lift to permit extension or retraction of the piston of the assembly. Another fluid power cylinder assembly with a lock is shown in U.S. Pat. No. 5,097,748, in which a locking piston 11 holds balls 25 in a locked position to lock a piston 3 and releases the balls 25 in an unlocked position to allow the balls 25 to move out of groove 26 while executing a stroke. Another fluid power cylinder assembly with a lock is shown in U.S. Pat. No. 7,784,392, in which a bidirectional control relief valve 10 includes a poppet valve 30 that closes under certain conditions to seal off fluid volume 60 to lock a piston 12. Further, European Patent Application EP 1,197,668 A1 discloses a hydraulic lock device in which high pressure fluid from a pressure booster 7 acts on the outside of a thin wall sleeve 5 and deforms the sleeve 5 inwardly to lock a rod 3.
The present invention departs from these prior art hydraulic fluid power cylinder assemblies and addresses the above described and other technical problems and provides a fluid power cylinder assembly that is relatively easy to assemble and align and that has low complexity and low cost and high reliability.
At least one embodiment of the invention may provide a fluid power cylinder assembly that includes a cylinder body and a piston. The cylinder body may have a generally cylindrical interior surface defining a longitudinally extending cylinder chamber. The piston may have a generally cylindrical longitudinally extending piston body portion with a generally cylindrical exterior surface slidably disposed within the cylinder interior surface.
At least one embodiment of the invention may provide a drift stop body portion that may be fixed to the piston body portion and spaced laterally inwardly from the interior surface of the cylinder body. A longitudinally extending drift stop cavity may be defined by a longitudinally extending drift stop cavity wall, and the drift stop cavity may have an open end opening into the cylinder chamber. The drift stop cavity may be in open fluid pressure communication with the cylinder chamber under all conditions. The drift stop body portion may extend longitudinally into the drift stop cavity when the piston body portion and the drift stop body portion are each in one position. The drift stop body portion may be longitudinally spaced from the drift stop cavity when the piston body portion and the drift stop body portion are each in another position.
At least one embodiment of the invention may provide a drift stop blocking surface that may be carried by one of the drift stop cavity wall and drift stop body portion, and a laterally movable drift stop blocking member carried by the other of the drift stop cavity wall and the drift stop body portion. The drift stop blocking member may have one position engaging the drift stop blocking surface to limit longitudinal movement of the piston when the piston body portion and the drift stop body portion are each in their one position. The drift stop blocking member may have another position spaced from the drift stop blocking surface when the piston body portion and the drift stop body portion are each in their other position.
At least one embodiment of the invention may provide a drift stop blocking surface that may be carried by the drift stop cavity wall, and the drift stop blocking member may be carried by the drift stop body portion. The drift stop blocking member may be laterally aligned with and laterally spaced from the drift stop cavity wall when the drift stop body is received in the drift stop cavity. The drift stop body portion may extend longitudinally from the piston body portion. The combined lateral cross sectional area of the drift stop body portion within the drift stop cavity and piston body portion within the cylinder chamber may be substantially equal to the lateral cross sectional area of the cylinder chamber, and the combined lateral cross sectional area may be exposed to fluid pressure of the drift stop cavity and cylinder chamber under all conditions. The drift stop blocking member may be pressure balanced under all conditions. The force of fluid pressure acting on the combined lateral cross sectional area may provide the sole means for disengaging the drift stop blocking member from the drift stop blocking surface.
At least one embodiment of the invention may provide a laterally extending drift stop blocking member passage in the drift stop body portion, and the drift stop blocking member may be slidably disposed in the passage. An end cap may be fixed against movement relative to the cylinder body, and the drift stop cavity may be disposed in the end cap. A drift stop blocking member positioning surface may be provided, and the drift stop blocking member may engage the positioning surface to retain the drift stop blocking member away from the drift stop cavity wall and away from the cylinder interior surface when the drift stop blocking member and the drift stop surface are disengaged from one another. A drift stop blocking member spring may be carried by the drift stop body member, and the drift stop spring may bias the drift stop blocking member laterally outwardly against the positioning surface when the drift stop blocking member is disengaged from the drift stop blocking surface. The positioning surface may be a reduced diameter region of the passage.
At least one embodiment of the invention may provide the drift stop blocking surface including an annular ridge extending laterally inwardly from the drift stop cavity wall and at least one substantially conical surface. The drift stop blocking member may be generally spherical. The drift stop body portion may extend longitudinally from the piston body portion, and the piston body portion and the drift stop body portion may be of integral single piece construction. The piston body portion and the drift stop body portion may be concentrically disposed along a longitudinal axis.
This Summary is not intended to identify all key features or essential features of the claimed subject matter, and these and other features of the invention are more fully described and particularly pointed out in the description and claims set out below. The following description and claims and the annexed drawings set forth in detail certain illustrative embodiments of the invention, and these embodiments indicate but a few of the various ways in which the principles of the invention may be used.


A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

The fabrication processes for silicon chips often lead to the formation of small stress-induced silicon defects that may coalesce into dislocations or stacking faults that degrade the product functionality, yield and reliability. Examples of such processes include ion implantation, trench isolation and other dielectric isolation processes, trench capacitor processes, oxidation processes in general and film deposition processes. Results of stress-induced defects include gate and capacitor dielectric leakage, which may be yield or reliability defects.
Semiconductor silicon substrates, being crystalline are subject to shearing of one portion of the crystal with respect to another portion of the crystal along a specific crystal plane. Dislocations, which are postulated as crystalline defects, occur in different types including: edge dislocations, screw dislocations and declinations.
In dynamic random access memory (DRAM) technologies employing deep trench storage capacitors, the leakage requirements for the capacitor are very stringent, and monitor systems are introduced for the detection of process induced defects in the active area of the DRAM deep trench storage capacitors.
While methods exists for monitoring processes for defects and other methods exist for detecting stress during processes development, an efficient and sensitive monitoring systems for detecting stress-induced defects that could be used for both development and routine monitoring in manufacturing is limited. Therefore, a method is needed to detect the formation of silicon defects that is sensitive, simple, applicable to process monitoring and process development and applicable to logic and DRAM technologies.

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

International Business Machines Corporation


An improved fusion welding system having a perforating device and a heating combination is adapted for welding in tandem a set of adjacent overlapping workpieces. The system preferably includes a first laser that perforates the workpieces to produce an opening spaced from the edges; and the combination preferably includes a second laser and electrode for cooperatively melting fusible material into the opening.

1. Field of the Invention
The present invention relates to fusion welding systems, and more particularly to a fusion welding system having a perforating or cutting device configured to produce an opening within a plurality of workpieces and a heating combination configured to produce a lap weld within the opening.
2. Discussion of Prior Art
The process of material joining and treatment is a necessary condition for the industrial progress. As such, fusion-welding systems have been developed for joining multi-component workpieces. One such system, metal-arc robotic welding, utilizes an arc discharge to provide a more affordable and less expensive heat energy source during joining, and is commonly used, for example, in the automotive industry. These conventional systems are typically used to produce fillet welds along seams formed by adjacent workpieces, as shown in FIG. 1; and provide good gap bridgeability, weld penetration, and low cost. The electrodes that produce the arc may also be fusible by the process, so that metallic drippings are produced to contribute to the weld. Other welding systems, such as conventional hybrid laser-arc systems, which feature the simultaneous application of heat generated from laser radiation and an electric arc, have also been developed.
Due to workpiece dimension variations, improper fixture designs, and distortions from welding, however, weld bead misalignment (also shown in FIG. 1) presents a major issue during the use of these and other systems. Although various seam tracking devices have been used, they have not been successful due in part to long cycle time, arc lighting interference with camera and other technical difficulties. As a result, part inspection and repair provisions have been added to the production process, which thereby increase production time and total man-hours.
The increase in costs associated therewith, results in a need in the art for a more efficient welding process that reduces the likelihood of weld misalignment.

System and method of joining overlapping workpieces


An acceleration sensor can ensure rigidity of its movable electrode despite a large number of through-holes formed in the movable electrode. The acceleration sensor has an SOI substrate in which a silicon oxide layer is formed on a silicon support layer and an active silicon layer is formed on the silicon oxide layer, wherein the active silicon layer of the SOI substrate has a movable electrode supported by elastic beams and configured with a weight, and also has fixed electrodes disposed in a fixed manner around the movable electrode to face the movable electrode, and wherein through-holes penetrating in a Z-axis direction are formed over the entire surface on the inner side of an outer circumference to which the elastic beams of the movable electrode are connected.

A capacitance semiconductor sensor is proposed as this type of acceleration sensor. In the capacitance semiconductor sensor, movable electrodes are disposed on the front and rear sides of a fixed electrode, with a predetermined distance between each movable electrode and the fixed electrode, in such a manner that detection surfaces of the movable electrodes face detection surfaces of the fixed electrode, and a through-hole is formed in such a manner as to penetrate from the detection surfaces of the movable and fixed electrodes to the surfaces opposite thereto, to reduce air damping generated between each movable electrode and the fixed electrode (see Patent Document 1, for example).    Patent Document 1: Japanese Patent Application Publication No. 2004-69541
According to the prior art disclosed in Patent Document 1, the movable electrodes are disposed on the front and rear sides of the fixed electrode, with a predetermined distance between each movable electrode and the fixed electrode, in such a manner that the detection surfaces of the movable electrodes face the detection surfaces of the fixed electrode, and the through-hole is formed in the middle of this structure in such a manner as to penetrate from the detection surfaces of the movable and fixed electrodes to the surfaces opposite thereto, to reduce air damping generated between each movable electrode and the fixed electrode.


An insertable strain gauge spanner which comprises a spanner body having a rod body and a driving head insertable into the rod body; the rod body having a handle and an inserting opening at one end thereof; the inserting opening can be received the driving head; the rod body being installed with a strain gauge; a lower end of the rod body being formed as an inserting opening; the inserting opening being in contact with the strain gauge; thereby the twisting force from the driving head can be transferred to a sensing end of the strain gauge; the twisting force being displayed in a window of the strain gauge; and the driving head having an inserting end with a shape corresponding to that of the inserting opening; and the orientation of the driving head with respect to the rod body is adjustable.

Spanners with strain gauges are more and more popular because it can measure the strains in operation so that the user can determine the applied force and to control the size of the applied force not to be too large so as to destroy the element to be released.
There are many kinds of spanners with strain gauges are developed. In one prior art, disclosed in Taiwan Patent No. 284306, the strain gauge spanner is installed with a strain gauge for determining the strain gauge in operation so that the user can determine that the element to be released has been released to a desired level. Thus, the element will not be too loose or too tight. In this prior art the spanner has a driving head and a rod body. The rod body has an inclined surface which is in contact with the strain gauge. When the driving head serves to drive an element, the twisting force will be transferred to the strain gauge through the inclined surface. Thus the strain gauge can measure the twisting force. If the twisting force is over a predetermined value, the strain gauge is possibly destroyed. Thus the use of the strain gauge spanner is limited.
Furthermore, in this prior art, the use of the spanner must be adjusted to an orientation matched to the inclined surface. If the user drives an element along another direction, the strain gauge cannot measure the twisting force. Thereby the operation is inconvenient. Thus, it is not practical.


A piezoelectric thin-film resonator includes a piezoelectric thin film which includes aluminum nitride containing Sc and which has a concentration distribution such that the concentration of Sc is non-uniform in a thickness direction of the piezoelectric thin film; a first electrode; a second electrode facing the first electrode across the piezoelectric thin film; and a substrate supporting a piezoelectric vibrating section defined by the piezoelectric thin film and the first and second electrodes.

1. Field of the Invention
The present invention relates to piezoelectric thin-film resonators including an aluminum nitride material and particularly relates to a piezoelectric thin-film resonator including an Sc-containing aluminum nitride layer.
2. Description of the Related Art
Various piezoelectric thin-film resonators including piezoelectric thin films have been proposed. Japanese Unexamined Patent Application Publication No. 2011-15148 discloses a method for producing a piezoelectric thin film for use in such a piezoelectric thin-film resonator. That is, Japanese Unexamined Patent Application Publication No. 2011-15148 discloses a technique in which aluminum and scandium are sputtered at a substrate temperature of about 5° C. to 450° C. in a nitrogen atmosphere. This allows the content of scandium in an aluminum nitride thin film containing scandium to be about 0.5 atomic percent to 50 atomic percent, leading to an increase in piezoelectric response. Japanese Unexamined Patent Application Publication No. 2011-15148 describes that the content of scandium in the scandium-containing aluminum nitride thin film is about 0.5 atomic percent to 50 atomic percent as described above, preferably about 35 atomic percent to 43 atomic percent, and most preferably about 43 atomic percent.
However, in the case of fabricating a piezoelectric thin-film resonator using an Sc-containing aluminum nitride thin film having an Sc content described in Japanese Unexamined Patent Application Publication No. 2011-15148, there is a problem in that the absolute value of the temperature coefficient of frequency TCF of the piezoelectric thin film is large. Therefore, it has not been possible to obtain a piezoelectric thin-film device which has a sufficient fractional bandwidth and in which the absolute value of the temperature coefficient of frequency TCF is small.
In a piezoelectric thin-film resonator including the Sc-containing aluminum nitride thin film disclosed in Japanese Unexamined Patent Application Publication No. 2011-15148, properties according to the concentration of Sc can be obtained; however, it is difficult to vary the properties thereof. That is, the degree of freedom in designing various properties such as fractional bandwidth and frequency-temperature properties is low.

Piezoelectric thin-film resonator and method for producing piezoelectric thin film