A circuit for determining and reporting the energy consumed by an electronic device having a microprocessor and power supply lines for supplying power to the device is disclosed. The circuit comprises a voltage divider connected for sensing the voltage across the power supply lines and generating a voltage signal indicative of the sensed voltage. A current sense resistor is connected in series with a power supply line for sensing the current passing through the power supply lines and generating a current signal indicative of the sensed current. An analog multiplier is connected for receiving and computing the product of the voltage and current signals, and for generating a power signal indicative of the product of the voltage and current signals, the power signal being indicative of the power consumed by the device. A proportional voltage-to-frequency converter is connected for receiving the power signal and for generating primary signal pulses at a frequency proportional to the voltage level of the power signal, each of which pulses is indicative that a predetermined quantity of energy has been consumed by the device. An opto-coupler, connected to the converter, is responsive to generation of the primary signal pulse for reporting to the microprocessor a secondary signal pulse indicating that a predetermined quantity of energy has been consumed by the device.

The power supply circuit of a computer system provides usable power to the electrical components and devices of the computer. Because most computers require voltage and current different from that generated and supplied by local utility companies, the computer's power supply must convert the incoming voltage and current to a form appropriate for use by the computer. For example, most utility companies in the United States produce power at 120 volts, as 60 hertz, sinusoidal alternating current (AC). A computer system, however, typically requires direct current (DC) power at a voltage level significantly lower than 120 volts, such as 12 volts or less. Hence, the computer's power supply converts "utility power" into "computer power."
As computer technology has progressed, computers have become more "powerful" and, as a consequence, require more electrical power, and are therefore more costly to operate than earlier computers. The impact of increasing operating costs of computers is particularly acute in large organizations having networks comprising a large number of computers. It is therefore desirable that computers be operated efficiently and economically so that operating costs are minimized. To this end, some computers are provided with power supplies having support circuitry that measures power consumed on the primary side of a power supply transformer and reports the measurements as a serial bit stream of data to a computer microprocessor on the secondary side of the transformer. Such support circuitry, however, comprises a relatively expensive microcontroller and, as a consequence, is relatively expensive to implement. It can be appreciated that the savings in operating costs made possible by such support circuitry are, to a certain extent, offset by the cost of the microcontroller required to achieve the savings, thereby defeating the purpose of the microcontroller.
Therefore, what is needed is a low cost (i.e., a non-microcontroller) system for measuring the amount of power, or energy, consumed by a computer on the primary side of the PC transformer and for generating to the secondary side thereof data indicative of the power measured.

System for reporting computer energy consumption


A system is provided for remote controlling equipment, which allows at least one server and at least one remote piece of equipment to be interconnected according to the MQIsdp protocol. The system associates at least one of the remote pieces of equipment with radio communication device that emits and receives AT-type commands issued by and/or addressed to an external application which is used by the distance piece of equipment. The radio communication device is provided with a set of specific AT commands for exchanging data with at least one server that uses the MQIsdp protocol such that said server/s and the remote piece/s of equipment can be interconnected via the radio communication device without the distant pieces of equipment having to know the MQIsdp protocol.

Many solutions already exist for performing such operations. They have generally been developed specifically for a given application. In other words, they are "proprietary" solutions that are difficult to adapt to other applications.
There is also a protocol developed by the IBM and ARCOM Control Systems companies (registered trademarks), known as the "MQIsdp Messaging" technology. This technique proposes a communication protocol between one or several items of equipment with limited resources, and one or several servers, using a TCP/IP link.

System and method for remote controlling equipment with the aid of at commands, and corresponding device, radiocommunication module, and set of commands


A cordless electric dual condiment grinder includes a hollow housing elongated to extend between a base for supporting the grinder uprightly and an opposing top, the top of the housing having a bulbous form to define two condiment reservoirs (e.g. for receiving salt and pepper respectively). A unidirectional rotary grinding mechanism is disposed in a lateral opening in each of the reservoirs. The lateral openings are on opposing sides of the housing and a tilt switch controls the direction of rotation of a reversible drive motor. One-way clutches in the transmission are provided such that each grinding mechanism is selectively rotated depending upon the direction of rotation of the motor output. The user can thus selectively dispense from one or other of the compartments by rotating the grinder through an acute angle from the upright such that the selected lateral opening faces downwardly and thus is particularly suited for use by people with limited dexterity.

Hand-held cordless electric grinders provide a convenient and fast method for dispensing freshly ground pepper, salt, or other condiments. A conventional grinder of this type has an elongate housing which defines a grip by which the grinder is held and which has first and second longitudinally opposing ends. A battery compartment at the first end of the housing provides power to an electric motor connected via a speed reduction geartrain to a drive shaft. The drive shaft extends through a condiment reservoir to a grinding mechanism at the second end of the housing. In an upright design the second end may be supported on a table, or a like horizontal surface, when not in use. However, a drawback of this is that, following use, the impact caused by placing the grinder upon a table tends to dislodge condiment particles from or through the grinding mechanism which drop from the grinder and, for instance, may soil a table cloth.
An inverted design is therefore preferable, in which the first end is adapted to be supported upon the table so that the second end is uppermost and a recess is provided in the housing to catch any particles dislodged following use. However, an inverted grinder of this type has ergonomic drawbacks as it is necessary to rotate the grinder approximately 180° to dispense the ground condiment and this can be troublesome for people having reduced mobility of the forearm and wrist. Moreover, operating a switch to initiate grinding at the same time as rotating the grinder in this manner can pose further difficulties to disabled people. One object of the invention is to provide a condiment grinder which addresses these drawbacks.
There is a continuing need for and interest in improvements to electric condiment grinders of this type. In particular there is a need for a grinder able to selectively dispense two freshly-ground condiments. The grinder should have an efficient geartrain with a low weight and inertia and which can be readily installed. It should also be compact with coaxial drive and driven shafts, relatively efficient and quiet in operation, while being able to operate at high motor speeds. It is a further object of the present invention to address the above needs or more generally to provide an improved condiment grinder.

Samson Bright Industrial Company Limited


A driver circuit for powering a load is disclosed. The driver circuit includes a self-oscillating half-bridge circuit, a resonant driver in electrical communication with the self-oscillating half-bridge circuit, and a DC voltage supply in electrical communication with the resonant driver. The self-oscillating half-bridge circuit is configured to generate a high-frequency AC signal. The resonant driver is configured to limit a current of the high-frequency AC signal and produce a limited output voltage based on the high-frequency AC signal. The DC voltage supply is configured to rectify the limited output voltage into a DC output voltage including a substantially constant current for powering the load.

Light emitting diode (LED) based lighting systems may offer several energy and reliability advantages over other types of lighting systems such as, for example, incandescent or fluorescent lighting. Thus, LED based lighting systems may be used to replace other existing lighting technologies. Some types of LED drive circuits may include a controller integrated circuit (IC) in combination with a metal-oxide-semiconductor field-effect transistor (MOSFET) for driving one or more LEDs. However, components such as controller ICs and MOSFETs are typically expensive, and add cost and complexity to an LED lamp. Therefore, there exists a continuing need in the art for a cost-effective drive circuit for an LED lamp.

Low-cost self-oscillating driver circuit


A method for managing a fault involves detecting an error, gathering data associated with the error to generate an error event, and categorizing the error event using a hierarchical organization of the error event.

An error is an unexpected condition, result, signal, or datum in a computer system or network. A fault is a defect that may produce an error. When an error occurs that is attributable to a fault, logging the error and fault information is helpful to diagnose the fault, and effect recovery.
Conventional methods of logging system information include obtaining messages that provide information about the overall system, obtaining subsystem-specific kernel statistics, and polling subsystems to extract other subsystem-specific data. The aforementioned methods of logging system information may be coupled with a conventional notification scheme to allow data to be obtained when specific events occur. The system information obtained using the conventional methods is typically processed either using a system-specific diagnosis engine or read by a user, to determine the corresponding fault associated with the error.
In general, the conventional methods that provide information about the overall system, typically centrally log events that occur anywhere in the system. The conventional methods log events such as password changes, failed login attempts, connections from the internet, system reboots, etc. Information about the events is typically recorded in text format in a log file or series of log files, depending on how a utility performing the conventional message logging is configured. The individual events that are recorded are referred to as messages. In some cases, the utility performing the conventional message logging is configured to incorporate various types of information into the messages. For example, the messages may include information regarding the severity level of the event.
Further, the utility performing the conventional message logging may also be configured to indicate the general class of a program, commonly referred to as the "facility," that is generating the message. The standard facility names include: "kern" indicating that the message originated from the operating system, "user" indicating that the message originated from a user process, "mail" indicating that the message originated from the mail system, "auth" indicating that the message originated from a user authentication process or system, "daemon" indicating that the message originated from a system daemon (e.g., ftpd, telnetd), "syslog" denoting internal syslog messages, etc.
The following is a code sample showing an example of a message obtained using conventional message logging.
Code Sample 1 Jun 19 19:13:45icein.telnetd[13550]:connect fromalpha.eng.brandon.edu  (1)(2)(3)(4)(5)Segment (1) corresponds to the date and time of the logged information, segment (2) corresponds to the system the message originated from (i.e., ice), segment (3) corresponds to the process the message originated from (i.e., in.telnetd), segment (4) corresponds to the identification number of the originating process, and segment (5) corresponds to the body of the message.
Utilities performing the conventional message logging may also include functionality to perform a certain action when a particular event occurs. The actions may include, for example, logging the message to a file, logging the message to a user's screen, logging the message to another system, and logging the message to a number of screens.
As noted above, information about system events may also be obtained using subsystem-specific kernel statistics. The utilities that obtain subsystem-specific kernel statistics typically examine the available kernel statistics on the system and reports those statistics which are requested by the user. The user typically specifies which statistics she would like to see using a command line interface. An example of output obtained using a typical utility for obtaining subsystem-specific kernel statistics is shown below.
Output Samplecpu_stat:0:cpu_stat0:intr29682330cpu_stat:1:cpu_stat 1:intrblk51   (1)  (2)  (3)   (4) (5)Segment (1) corresponds to the module where the statistic was generated. Segment (2) corresponds to the instance of the module in the system, in this particular example there are 2 instances (0 to 1) of the cpu_stat module. Segment (3) corresponds to the name of the module instance (e.g., cpu_stat0) from which the statistic is obtained. Segment (4) corresponds to the particular kernel statistic within the module (e.g., intrblk). Segment (5) corresponds to the fractional second since the particular process tracked by the system has been operating, in fractional seconds, since the system booted. While the above example provided fractional time of a given process within a module has been operating, the utilities providing subsystem-specific kernel statistics typically include functionality to provide additional kernel statistics including user access, system calls, wait times, etc.
The aforementioned means of obtaining system information, may be used with notification schemes to obtain system data when a particular event occurs. The notification schemes typically use traps to trigger the recording of an event.

Event protocol and resource naming scheme


A diagnostic computed tomographic imaging apparatus, comprises a patient support structure including a tabletop to support a patient in front-down, prone position. The tabletop includes an opening to permit a breast of the patient to be vertically pendant below the tabletop. A scanning mechanism is disposed below the opening and orbitable about the breast pendent through the opening to obtain perimeter data and image reconstruction data of the breast. The scanning mechanism rotates about an axis of rotation transverse to the tabletop. One of the tabletop and scanning mechanism is movable in x-y axes to center the breast about the axis of rotation.

Cancer of the breast is a major cause of death among the American female population. Effective treatment of this disease is most readily accomplished following early detection of malignant tumors. Major efforts are presently underway to provide mass screening of the population for symptoms of breast tumors. Such screening efforts will require sophisticated, automated equipment to reliably accomplish the detection process.
The x-ray absorption density resolution of present photographic x-ray methods is insufficient to provide reliable early detection of malignant tumors. Research has indicated that the probability of metastasis increases sharply for breast tumors over 1 cm in size. Tumors of this size rarely produce sufficient contrast in a mammogram to be detectable. To produce detectable contrast in photographic mammograms, 2-3 cm dimensions are required. Calcium deposits used for inferential detection of tumors in conventional mammography also appear to be associated with tumors of large size. For these reasons, photographic mammography has been relatively ineffective in the detection of this condition.
Most mammographic apparatus in use today in clinics and hospitals require breast compression techniques that are uncomfortable at best and in many cases painful to the patient. In addition, x-rays constitute ionizing radiation, which adds a further risk factor into the use of mammographic techniques as most universally employed.
Ultrasound has also been suggested as in U.S. Pat. No. 4,075,883, which requires that the breast be immersed in a fluid-filled scanning chamber. U.S. Pat. No. 3,973,126 also requires that the breast be immersed in a fluid-filled chamber for an x-ray scanning technique.
In recent times, the use of light and more specifically laser light to noninvasively peer inside the body to reveal the interior structure has been investigated. This technique is called optical tomography. Rapid progress over the past decade has brought optical tomography to the brink of clinical usefulness. Optical tomography has the benefits compared to mammography of no breast compression and no ionizing radiation.
The patient lies prone on a scanning apparatus with one breast pendent in a scanning chamber. A laser beam impinges upon the breast; light is scattered throughout the breast and detected by an array of optical detectors. The scanning apparatus acquires data from one or several slices through the breast, parallel to the chest wall. The detection mechanism then moves some small distance away from the chest wall and the data for more slices are acquired. This process continues until the entire breast has been imaged.
One complication, and the subject of the present invention, is that the shape of the breast varies from patient to patient and particularly changes dramatically as the scanning proceeds from the chest wall toward the nipple. It is an absolute requirement of a 3rd generation optical CT scanner that the center of rotation of the scanning mechanism lay within the breast. It is desirable that the center of rotation of the scanning mechanism lies near the center of the breast. But breasts do not hang vertically in the prone position. Cooper's Droop occurs when Cooper's ligaments stretch over time, causing the breasts to sag when upright. In the prone position, breasts hang somewhat towards the feet as the scanning apparatus progresses from the chest towards the nipple (see FIG. 3A). A breast that is well centered at the chest wall through the axis of rotation of the scanning mechanism usually will be off-center near the nipple.

Laser imaging apparatus with variable patient positioning


A method is disclosed for rendering a volumetric obscurant in a computer generated graphical image. The method can include the operation of defining a polygon template as a first surface of the volumetric obscurant comprising pixels and sub-pixels. A further operation can be spreading a depth of the sub-pixels for pixels in the polygon template to create a thickness in the volumetric obscurant. Finally, another operation can be modulating a depth density of the sub-pixels to vary the distances between the sub-pixels in the volumetric obscurant.

Most computer graphics devices currently available are very efficient at rendering points, lines, and polygons. Some even support more complex surfaces, but when it comes to rendering volumetric objects such as smoke or clouds, the application developer is often left to develop unique solutions.
Beginning in the early 1980's, various approaches have been developed for rendering volumetric obscurants. William T. Reeves introduced particle systems in 1983. James Kajiya published an approach using ray tracing in 1984. Geoffrey Y. Gardner discussed a method of rendering clouds using textured ellipsoids. David S. Ebert and Richard E. Parent combined volumetric techniques with the popular Scanline A-buffer in 1990. Richard Voss developed a technique based upon fractals, while Nelson Max used height fields. In 1991, Rick D. Bess and Brian T. Soderberg developed a technique specifically for the simulation of smoke on the battlefield.
While not an exhaustive list of approaches, it is clear that there are numerous methods for rendering volumetric obscurants. Because of the complexity of the volumetric phenomenon, there has not yet been a single algorithm that is cost effective, efficient, and visually sufficient for all graphics applications. Particle systems create very realistic results, but a large quantity of particles is required. Consequently, a particle system approach may be fine for non-time-critical applications, but it is not appropriate for many real-time or interactive applications. Ray tracers also produce good results, but hardware accelerators are not commonly available. Thus, many applications simply do their best to simulate volumetric effects using points, lines, or polygons, since low cost graphics devices are readily available which efficiently handle these primitives.
Polygons with textures can be used to render very realistic looking clouds in the distance, but as the eye position or other objects get near or even penetrate the volume, the illusion starts to fall apart. Not only should the object 'look' like a cloud, it preferably will 'behave' like a cloud to complete the illusion. For example, polygonal techniques work fine when an observer views an object that is in front of a cloud or fully behind a cloud, but as an object penetrates a cloud, the volumetric nature of the cloud must be properly accounted for. The portions of the object near the front (as seen from the observer's position) of the cloud may be mostly visible, while more distant portions of the object may be mostly or even totally obscured. Maintaining this volumetric behavior can enhance the realism of rendered scenes.
It is common practice to use a single polygon with a texture pattern to simulate complex objects. Certain classes of polygons are processed such that they always face the observer. These polygons are often referred to as 'stamps', 'splats', or 'imposters'. This technique can be very effective for the simulation of distant clouds and other volumetric effects. Each cloud puff can comprise a single polygon with a texture pattern. From a distance, a polygon image with a texture can be fairly realistic looking. However, if an object moves through what should be a volumetric obscurant, such as a cloud that is simulated with a two dimensional polygon, it will become apparent as the object moves through the cloud stamp that each cloud puff is really just a flat billboard-like polygon.
For example, as an aircraft penetrates a polygon with a texture pattern designed to simulate a cloud, a portion of the aircraft is in front of and a portion behind the polygon. Instead of a volumetric obscuration of the aircraft, the polygon will cause a hard, planar interpenetration. The portion of the aircraft in front of the polygon will be fully visible while that portion lying behind may be totally obscured. This hard edge will be readily apparent to a viewer, giving away the polygonal structure of the cloud and breaking the illusion of a volumetric cloud. Of course, the situation can be improved by using more polygons. Unfortunately, to achieve high quality results you have to use a very large number of small polygons, which in the limit is a particle system.

Method for rendering volumetric obscurants

Rockwell Collins Simulation And Training Solutions LLC


Particles of strontium carbonate, barium carbonate, strontium sulfate and/or barium sulfate having a sufficient degree of fineness, especially when produced synthetically, are suitable as abrasive agents in chemical mechanical polishing (CMP polishing) of components, e.g., microelectronic components such as silicon wafers. The alkaline earth metal salt compounds are used as slurries in water and/or organic liquids and optionally may contain a dispersing agent, and preferably have a pH value of at least 8.

The present invention relates to the use of certain alkaline earth metal salts as auxiliary agents in chemical mechanical polishing (CMP method), particularly of microelectronic components.
In certain fields of the industry, components are often needed that have been polished to a certain profile on at least one side. For example, the components may need to be uniformly flat and have a low surface roughness. Components which may need polishing include, for example, optical components, semiconductor components and ceramics.
One method of manufacturing such components with a high degree of polish is the chemical mechanical polishing (CMP) method using polishing slurries. Chemical mechanical polishing is usually performed as described below. The workpiece to be polished, e.g., a silicon wafer, is positioned with the surface to be polished facing down on a rotating pressure plate (platen). The wafer is secured by a carrier. The wafer and platen rotate in the same direction. A polishing pad or polishing substrate with a polishing slurry is provided on the surface of the platen. The polishing slurry contains very fine abrasives such as silicon dioxide or cerium oxide.
When oxide layers are to be polished, a basic slurry is generally used, e.g., a slurry containing potassium hydroxide solution or ammonia water and having a pH in the range from 10 to 11. To polish metals such as tungsten, slurries which typically contain an oxidizing agent such as hydrogen peroxide and have a low pH, e.g., from 0.5 to 4, are used. U.S. Pat. No. 5,695,384 discloses the use of slurries in the neutral pH range, using colloidal silicon dioxide to which a soluble halide salt, e.g., sodium chloride has been added. Ceramics such as barium strontium titanate as well as other materials such as gallium arsenide, diamond, silicon carbide and other perovskite materials can be polished with such slurries.

Method of chemical mechanical polishing using abrasive particles of alkaline earth metal salts


Methods and systems for managing virtual working pages are disclosed. One method includes storing a first set of parameters in a working page within the tested system, where the first set of parameters is used for calibration of the tested system. The method also includes storing a second set of parameters in a virtual working page within an observation system having a plurality of virtual working pages. The method further includes transferring the second set of parameters from the observation system to the tested system. The method also includes storing one or more parameters of the second set of parameters in the working page. A related user interface is also disclosed.

Calibration of a system for determining an optimal operational configuration generally requires monitoring operation of the tested system, and adjusting one or more parameters affecting operation of the tested system until the system reaches a desired performance level. Observation systems exist which are configured to monitor the activity of the tested system so that calibration of that system can take place. One possible system requiring testing and calibration is an Electronic Control Unit (ECU), such as those found in vehicle control systems for determining fuel consumption, monitoring exhaust gas valves, and other physical characteristics of the vehicle.
Generally, tested systems such as ECU's contain some additional memory used to save changed parameter values, referred to as a "working page". The size of the working page is generally limited due to cost reduction of the tested system. Therefore, the number of changed parameter values is limited.
Various methods of calibration of these tested systems are known. Such methods generally involve changing in a subsequent way one parameter after another to change the behavior of the tested system. Existing tools also load a file containing parameter values into the working page of a tested system. These existing methods are inconvenient and time-consuming, because of the various loading and parameter changing steps involved.
For these and other reasons, improvements are desirable.

Changing parameters in a tested system using virtual working pages


The invention provides a liquid crystal display device capable of realizing a display, which has a high brightness and a wide viewing angle in both transmissive display and reflective display. A liquid crystal display device according to the present invention includes a transmissive display region and a reflective display region, and also is formed of liquid crystal with a negative dielectric anisotropy such that an initial alignment state is vertical. Electrodes to drive the liquid crystal are provided with slit-shaped openings and convex portions to regulate the alignment of liquid crystal molecules, and an insulating film to allow the thickness of the liquid crystal layer in the transmissive display region to be larger than the thickness of the liquid crystal layer in the reflective display region is formed between a substrate and the liquid crystal layer. The insulating film has an inclined plane to continuously vary its layer thickness in the vicinity of the boundary of the transmissive display region and the reflective display region, and a longitudinal direction of the inclined plane intersect a longitudinal direction of the openings and/or the convex portions, as viewed in plan view.

1. Field of Invention
The present invention relates to a liquid crystal display device and an electronic apparatus. More specifically, the invention relates to obtaining a display having a high contrast and a wide viewing angle in a transflective liquid crystal display device in which display is performed in both a reflective mode and a transmissive mode.
2. Description of Related Art
A related art liquid crystal display device includes a transflective liquid crystal display device that provides a display that is visible using external light, similarly to a reflective liquid crystal display device, in a bright place. The transflective liquid crystal display device also provides a display that uses a backlight, similarly to the transmissive liquid crystal display device, in a dark place. Such a related art transflective liquid crystal display device includes a liquid crystal display device in which a liquid crystal layer is interposed between an upper substrate and a lower substrate, a reflective film obtained by forming windows to transmit light in a metal film made of, for example, aluminum is provided on the inner face of a lower substrate, and the reflective film is then allowed to serve as a transflective plate. In this case, in the reflective mode, the external light incident from the upper substrate side passes through the liquid crystal layer, is reflected by the reflective film at the inner surface of the lower substrate, passes through the liquid crystal layer again, and is emitted from the upper substrate side, thereby contributing to the display. On the other hand, in the transmissive mode, light from a backlight incident from the lower substrate side passes through the liquid crystal layer from the windows of the reflective film and is emitted from the upper substrate side to the outside, thereby contributing to the display. Therefore, the area in which the windows are formed in an area in which the reflective film is formed become the transmissive display region, and the areas other than transmissive display region become the reflective display region.
However, the related art transflective liquid crystal display device is subject to a problem in that the viewing angle in the transmissive display is narrow. This is because a transflective plate is provided at an inner surface of a liquid crystal cell so as not to generate parallaxes, and thus there is a restriction that the reflective display should be performed using only one polarizer provided on the observer side. Therefore, the degree of freedom in the optical design is small. Therefore, in order to address or solve the above problem, a related art liquid crystal display device uses a vertically aligned liquid crystal, which is disclosed in "Development of transflective LCD for high contrast and wide viewing angle by using homeotropic alignment", M. Jisaki et al., Asia Display/IDW'01, pp. 133–136 (2001), (hereinafter "Jisaki et al.). Three features thereof are as follows:
(1) A "VA (Vertical Alignment) mode" is employed in which a liquid crystal with a negative dielectric anisotropy is aligned vertically at the substrate, and then it falls down by applying a voltage.
(2) A "multi-gap structure" is employed in which the thicknesses of the liquid crystal layer in the transmissive display region and the reflective display region are different from each other (for this feature, see, for example, Japanese Unexamined Patent Application Publication No. 11-242226.
(3) The transmissive display regions are formed as regular octagons, and protrusions are provided at the centers of the transmissive display region on the counter substrate such that the liquid crystal molecules fall down in eight directions in those areas. That is, a so-called "alignment division structure" is employed.

Multi-domain transflective liquid crystal display with plurality of band-shaped reflectors


A false color composite image is created by assigning mid infrared data from three time-spaced images of an area of interest to corresponding RGB color components for the false color composite image. The RGB color components for the false color composite image are then converted into color space data and classified into a number of color classes. An age is assigned to the color classes to create a classified image of age classes of the area of interest.

For timberland companies, governments or research institutions, it is often important to be able to accurately classify the ages of trees in a forest without having to physically go and inspect the forest. For example, access to remote forest lands may be difficult or the forest may be so large that it is not cost effective to send crews out to survey the entire site. As a result, satellite or aerial images of the forest are often used to classify the ages of the trees in the forest.
One conventional method of tree age classification using satellite images involves detecting differences in a number of time-spaced images to determine when a forest area is harvested and tracking the corresponding area in a number of the later images to determine how the trees are growing. From the analysis of the changes between images, the age of the trees can be determined. Such a method is both time consuming and requires a certain amount of human insight thereby making it difficult to automate.
Given these problems, there is a need for a system and method for automatically classifying the ages of trees using remotely obtained images in a way that is more efficient and can be automated.

Automatic age classification of forest land


An apparatus and method for location estimation in a wireless communication system are provided. The method includes identifying if a received at least one signal passed through at least one repeater, when the received at least one signal is identified as having passed though at least one repeater, measuring a Base Station (BS) basis delay time and calculating a repeater basis delay time using the measured BS basis delay time, and estimating a location of the MS using the repeater basis delay time.

1. Field of the Invention
The present invention relates to an apparatus and method for estimating a location of a Mobile Station (MS) in a wireless communication system. More particularly, the present invention relates to an apparatus and method for reducing a location estimation error caused by a repeater.
2. Description of the Related Art
In order to support a higher transmission rate than a 3rd Generation (3G) mobile communication system and extend service coverage, a new 4th Generation (4G) mobile communication system is being developed. Many research institutes and enterprises of advanced countries are promoting the development of technology for future 4G-standardization.
A 4G mobile communication system operating in a high-frequency domain is limited in its service coverage because of a high path loss. In order to address this problem, a multi-hop signal forward scheme has been investigated. A multi-hop technology can reduce a path loss and make a high-speed data communication possible by relaying data using a relay, and can extend service coverage by forwarding a signal to a Mobile Station (MS), even if the MS is far away from a Base Station (BS).
As such, a multi-hop relay system requires one or more relays for relaying data between a transmitter and a receiver. In a cellular system, a relay can be a separate device distinguished from a BS and an MS. However, an MS can serve as a relay for a different MS. In the multi-hop relay system, a communication between two nodes is implemented through a transmitter-relay, relay-relay, relay-receiver radio link and the like.
Typically, a multi-hop relay technology can be divided into an amplify-and-forward scheme and a decode-and-forward scheme. The amplify-and-forward scheme is a scheme in which a relay amplifies a Radio Frequency (RF) signal received from a transmitter and relay-forwards the amplified signal to a receiver. The amplify-and-forward relay may be referred to in the alternative as a "repeater." The decode-and-forward scheme is a scheme in which a relay demodulates and decodes a received signal, again modulates and encodes the signal, and relay-forwards the signal to a receiver. The decode-and-forward relay may be referred to in the alternative as a "Relay Station (RS)." The description below is made describing an amplify-and-forward relay (i.e., a repeater) as an example.
Due to an increase of demand for a variety of services, a Location Based Service (LBS) has been developed in various forms. The LBS is, for example, a service of estimating a location of a user who is under emergency (i.e., disaster) circumstances, a service of estimating a location of a user (that is, an MS) and guiding the user to a restaurant and the like.
A Location Detection Technology (LDT) for the LBS has been widely known as a cell IDentifier (ID) technique, an Angle Of Arrival (AOA) technique, a Time Of Arrival (TOA) technique, a Time Difference Of Arrival (TDOA) technique, an Assisted-Global Positioning System (A-GPS) technique and the like. Among the LDT technologies, the A-GPS technique is the one mostly used due to it having the highest degree of accuracy. However, the A-GPS technique requires a minimum of four GPS satellites and thus, in a shadow area where less than four satellites are available, a hybrid GPS technology using TDOA or cell ID is used. That is, hybrid GPS can use either TDOA or cell ID according to requirements of a desired service or number of BSs that can be secured by a user and the like.
In a metropolitan area, many shadow areas can exist between a BS and an MS and thus, many repeaters may be used. When a TOA or TDOA technology is used for LBS, it requires a minimum of three BSs. However, when a signal from a BS is received by an MS through a repeater, a time delay of the received signal through the repeater is different then a time delay of the signal received directly from the BS. This difference in the time delay results in a location estimation error.
FIG. 1 illustrates that an MS receives signals from three BSs in a conventional wireless communication system.
When a signal from each BS is received via a real path through a repeater and not a desired path, a time delay occurs because of the repeater. Thus, an MS cannot calculate an accurate propagation delay (i.e., TDOA, TOA, etc.). That is, because the MS calculates TDOA considering a received signal as directly received from a BS, a location estimation error can occur.
In addition, when a signal from a BS is received by an MS through a plurality of repeaters, the MS cannot be aware if a signal is received through a repeater and thus it cannot accurately determined if the measured time delays correspond to a path though a repeater. Moreover, numerous repeaters are installed in a metropolitan area. These numerous repeaters deteriorate location estimation performance, which causes a problem when using a LDT.

Apparatus and method for location estimation in a wireless communication system


Apparatus and methods are disclosed for performing time-reversed scheduling of a data dependency graph representing a target program instruction loop in an optimizing compiler. The instruction scheduling function is the modulo scheduling function of an optimizing compiler and it is noted that the time-reverse transforms preserve all modulo constraints. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units and typically contain multi-level memory devices such as on-chip cache, off-chip cache as well as main memory. For such microprocessors this invention can, where applicable, accelerate the process of modulo-scheduling loops in the target program code. The invention consists of a technique to transform the data dependency graph of the target program instruction loop in order to produce an improved schedule of the loop instructions.

It is desirable that computer programs be as efficient as possible in their execution time and memory usage. This need has spawned the development of computer architectures capable of executing target program instructions in parallel. A recent trend in processor design is to build processors with increasing instruction issue capability and many functional units. Some examples of such designs are Sun's UItraSparc.TM. (4 issue), IBM's PowerPC.TM. series (2-4 issue), MIPS' RlOOOO.TM. (5issue) and Intel's Pentium-Pro.TM. (aka P6) (3 issue). (These processor names are the trademarks respectively of Sun Microsystems, Inc., IBM Corporation, MIPS Technologies, Inc., and Intel Corporation). At the same time the push toward higher clock frequencies has resulted in deeper pipelines and longer instruction latencies. These and other computer processor architectures contain multiple functional units such as I/O memory ports, integer adders, floating point adders, multipliers, etc. which permit multiple operations to be executed in the same machine cycle. The process of optimizing the target program's execution speed becomes one of scheduling the execution of the target program instructions to take advantage of these multiple computing resource units or processing pipelines. This task of scheduling these instructions is performed as one function of an optimizing compiler. Optimizing compilers typically contain a Code Optimization section which sits between a compiler front end and a compiler back end. The Code Optimization section takes as input the "intermediate code" output by the compiler front end, and operates on this code to perform various transformations to it which will result in a faster and more efficient target program. The transformed code is passed to the compiler back end which then converts the code to a binary version for the particular machine involved (i.e. SPARC, X86, IBM, etc). The Code Optimization section itself needs to be as fast and memory efficient as it possibly can be and needs some indication of the computer resource units available and pipelining capability of the computer platform for which the target program code is written.
In the past, attempts have been made to develop optimizing compilers generally, and code optimizer modules specifically which themselves run as efficiently as possible. A general discussion of optimizing compilers and the related techniques used can be found in the text book "Compilers: Principles, Techniques and Tools" by Alfred V. Aho, Ravi Sethi andJeffrey D. Ullman, Addison-Wesley Publishing Co 1988, ISBN 0-201-10088-6, especially chapters 9 & 10 pages 513-723. One such attempt at optimizing the scheduling of instructions in inner loops in computer platforms with one or more pipelined functional units is a technique called "modulo scheduling." Modulo scheduling is known in the art and is generally described in the paper entitled "Some Scheduling Techniques and An Easily Schedulable Horizontal Architecture For High Performance Scientific Computing" by Rau B. R. and Glaeser, C. D., Proceedings of Fourteen Annual Workshop on Microprogramming, Advanced Processor Technology Group, ESL, Inc. October 1981, Pages 183-198 which is incorporated fully herein by reference. Modulo scheduling is one form of software pipelining that extracts instruction level parallelism from inner loops by overlapping the execution of successive iterations.
The modulo schedule is derived by traversing the data dependency graph for the loop assigning time-stamps to the instructions. Since a data dependency graph represents precedence relationships between instructions, the traditional approach is to schedule the sources of dependencies before the targets. The problem arises when the scheduling of a target needs to be delayed either because of unsatisfied precedence relationships with other sources or because of modulo constraints. In such cases, the lifetime of the register between the source and the target is lengthened. This has two negative consequences for the software pipelined loop:
1) Since register lifetimes are lengthened, increased register pressure may result in more register spills.
2) Since the number of times the kernel is unrolled depends on the longest register lifetime, greater code expansion may occur.
This invention addresses this problem by introducing a time-reversed scheduling approach for modulo scheduling. Forms of data dependency graphs, flow graphs etc. have been known for use in various fields requiring data flow analysis such as Operations Research and in optimizing compilers for some time. Time reversed scheduling of of such data flow graphs is a technique that has also been known in various of these fields. However, there is no known prior art which uses or suggests the use of time-reversed data dependency graph scheduling in modulo scheduling a target programs loop instructions in an optimizing compiler.

Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler


An electronic device includes an anisotropic conductive adhesive film as a connection material, wherein the anisotropic conductive adhesive film has a flowability of 50% or more after preliminary pressing at 80° C. and 1 MPa for 1 second and final pressing at 180° C. and 3 MPa for 5 seconds, and a connection resistance increment greater than 0% but not greater than 25%, as calculated by Expression 1:Connection resistance increment (%)=|(A−B)/A|×100  (Expression 1)where A is a connection resistance measured after preliminary pressing at 80° C. and 1 MPa for 1 second and final pressing at 180° C. and 3 MPa for 5 seconds, and B is a connection resistance measured after reliability evaluation at a temperature of 85° C. and a humidity of 85% for 250 hours following preliminary pressing and final pressing.

1. Field
Embodiments relate to an electronic device that includes a conductive adhesive film as a connection material.
2. Description of the Related Art
With the recent trend toward large size and slimness in display devices, pitches between electrodes and between circuits have become finer. Anisotropic conductive adhesive films may play an important role as interconnection mechanisms for the connection of fine circuit terminals. As a consequence, anisotropic conductive adhesive films are receiving much attention as materials for electrical connection.

Semiconductor device using composition for anisotropic conductive adhesive film or anisotropic conductive adhesive film


Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.

Computers may emulate hardware to provide the appearance of hardware that does not actually exist to an operating system, application, logic, or process. Computers may also use emulation to partition one hardware function between multiple operating systems, applications, and so on. This emulation may also be referred to as virtualization.
Virtualization may be accomplished by mechanisms including, for example, pure software virtualization, hardware supported software virtualization, and so on. Software virtualization tends to produce general performance penalties, even when the virtualized hardware is not being employed. However, software virtualization does facilitate emulating hardware on a variety of processors, particularly if the virtualization code is written in a portable, structured manner. Hardware virtualization tends to require hardware functions to be designed into an underlying chip. Designing in virtualization hardware functions may increase the size, complexity, design time, cost, time to market, and so on, of a chip set. Furthermore, if a chip set does not initially support virtualization, it may be difficult, if not impossible to "add-on" virtualization. Additionally, if the built-in virtualization hardware functions are not employed, they still consume chip real estate, power, and so on.

Virtualization of a parition based on addresses of an I/O adapter within an external emulation unit

Hewlett-Packard Development Company, L.P.


Nails are driven into hard receiving materials such as concrete, rock, metal and the like by explosive powder charge operated setting tools. To achieve the high mechanical strength required for such nails, the nails are formed of two parts, one a shank and the other a head fitted onto the shank. While the head is formed of a deformable corrosion resistant steel, the shank is formed of an austenitic steel alloyed with nitrogen having a very high mechanical strength. The steel forming the shank can only be shaped to a very limited extent, whereby a narrow flange is provided on the rear end of the shank. A disk fitted on the shank serves as a guide for the nails during the driving operation.

The present invention is directed to a nail to be driven into hard receiving materials such as concrete, rock, metal and the like with the nail having a shank and a head axially penetrated by the shank. The head has a larger outside diameter than the shank. The material forming the shank is harder than the material forming the head.
Nails of the above type are driven into hard receiving materials such as concrete, rock, metal and the like by explosive powder charge operated setting tools. These nails can be used for attaching parts to the hard receiving material and they can also be driven directly into the hard receiving materials for use as junction elements. Where the nails are used to fasten parts, they usually have a flange-like head. If they are used as junction elements, the head can have a thread or other engagement means such as a transverse bore. If the nails have a thread, they are usually characterized as bolts or studs.
Such nails are required to have a high mechanical strength because of the stresses developed in the driving operation. Due to the type of application, a high resistance to corrosion is also required. These two requirements have not been combined in nails used in the past. A compromise was found by using austenitic steels to provide corrosion resistance and the slightly lower strength of such nails was found to be advantageous for shaping work in fabrication. Because of the uses of these nails, the lower mechanical strength has been disadvantageous.
Known austenitic steels alloyed with nitrogen have a high mechanical strength and also a high resistance to corrosion. Such nails have not been used, because they are very difficult to form or shape. Shapes of the head required for different applications cannot be formed from such steels.
The fabrication of expensive head shapes, such as disclosed in U.S. Pat. No. 2,353,315, cannot be produced from the austenitic steels alloyed with nitrogen. For these complicated and expensive head shapes, a soft material is used according to U.S. Pat. No. 2,353,315 and is connected in a positively locked manner with the shank; however the shank does not have a high mechanical strength. For the nails disclosed in this patent, a material with low mechanical strength is adequate for fabrication of the shank, since the nails are not being driven into hard receiving materials by explosive powder charge operated setting tools. The use of such known nails in explosive powder charge operated setting tools is barred due to economic considerations, since nails for explosive powder charge operated setting tools are formed mostly as mass produced items, whereby the expensive fabricating manner set forth in U.S. Pat. No. 2,353,315 is unsuitable.

Corrosion-resistant nail for driving into hard materials


The inflatable penis ring is a device facilitating attachment of medical appliances to the penis. The device comprises an annular ring having an internal and external diameter. An array of inflatable balloons is evenly spaced around the internal diameter of the ring. A pressure control is provided to inflate or deflate the array of balloons as desired. Either air or liquid may be employed as an inflation medium. Inflation of the balloons, functions to efficiently and comfortably hold the ring in place on the penis. A rim or sleeve is mounted on the ring. Medical appliances may be attached to the rim.

1. Field of the Invention
The present invention generally relates to medical appliances. More specifically, the present invention is drawn to an inflatable penis ring that is positioned at the base of the penis for facilitating attachment of various medical devices thereto.
2. Description of the Related Art
In the treatment of problems associated with the penis, treatment devices must somehow be attached to the penis for proper functioning. For example, catheters of various types, condoms and penile erection devices must often be attached to the penis to drain fluids, enhance erections, or the like. There are many attachment devices that have been developed to address these problems. Pertinent examples of such attachment devices are cited and identified in the accompanying IDS. However, none of the cited and identified attachment devices are considered to disclose an inflatable penis ring structure as will be subsequently described and claimed in the instant invention. Thus, an inflatable penis ring solving the aforementioned problems is desired.


Provided is a lactam compound, a tautomer, a stereoisomer, a racemate, a nonequal mixture of enantiomers, a geometric isomer, a solvate, a pharmaceutically acceptable salt thereof, or a solvate of the salt of the compound, and a pharmaceutical composition containing the compound. Also provided are the use of such compounds and their pharmaceutical compositions as drugs, especially as antiviral drugs.

Viruses can be easily divided into two categories, enveloped virus and non-enveloped virus, depending on whether their outer shell contains a lipid rich membrane or not. The non-enveloped virus enters the infected cells mainly through swallowing through clathrin. The invasion of enveloped virus is mainly the fusion process between the capsid and the host cell membrane. At present, the research and development of antiviral agents are mainly based on two aspects: one is the level of virus infection, the other is the level of host cell defense. Most antiviral drugs now on the market are based on the virus itself, which means the receptor is virus itself. Interferon (IFN), the first generation of antiviral drugs to be developed, is named for its ability to "interfere" with virus replication. In recent years, more and more antiviral drugs have been developed and widely used in clinical treatment. For example, after interferon, ribavirin, acyclovir, valacyclovir, zidovudine, telbivudine and other nucleoside drugs which can interfere with virus transcription or replication developed rapidly, which occupy 50% antiviral drug market.
Although many antiviral drugs have been used effectively in clinic, drug-resistant viruses have emerged in recent years. The cause of drug resistance is mainly caused by the mutation of virus gene, which makes the antiviral drugs lose their target. For example, herpes simplex virus mutated in the thymidine kinase gene, acyclovir and ganciclovir cannot convert into active components in cells, thus becoming resistant to these drugs. Mutations in the M2 protein gene of influenza A virus make it resistant to amantadine or rimantadine. The variation of HIV reverse transcriptase or protease gene is also the main cause of drug resistance. Mutations in the unstructured 5 A and envelope gene 2-glycoprotein of HCV make it resistant to interferon. In conclusion, the development of new antiviral drugs is urgent.

Lactam compound, preparation method and use thereof


A packaging clip for maintaining a first side rail of a ladder adjacent a second side rail of a ladder. The clip comprises a first portion for removably holding the first side rail and a second portion for removably holding the second side rail. The clip also is comprised of a support element that is disposed such that it is common with the first portion and the second portion. In a preferred embodiment, the first portion includes a first opening for removably receiving the first side rail, and the second portion includes a second opening for removably receiving the second side rail. When the first side rail is inserted into the first opening of the first portion, and the second side rail is inserted into the second opening of the second portion, the clip limits and essentially eliminates the movement of the first side rail relative to the second side rail with respect to normal forces experienced during a given application. Thus, the ladder is not damaged by the first side rail moving excessively relative to the second side rail. In an alternate application, the first side rail of a ladder is maintained by the clip adjacent a second side rail of another ladder to facilitate transportation of the ladders.

Ladders have become a common tool to enable people to reach locations that would otherwise be too high off the ground. One type of ladder, otherwise known as a stepladder, essentially forms an inverted V when in place. This inverted V shape allows the ladder to be self-supporting, with the weight of the ladder and the weight of anything on the ladder being distributed about the bottom ends of the four side rails that comprise the ladder.
However, because of this ability of the ladder to fold together for storage purposes, there is also present the problem of the two sets of side rails moving sideways (rather than toward or away from each other) relative to each other about the joint at the top of the ladder. Since the joint is designed to function in a forward or back motion with respect to the two sets of side rails, any side motion experienced by the joint is injurious to it. Over time, this abuse can loosen the joint with respect to its ability to hold the sets of side rails from moving in a sideways motion. In addition, the movement of the side rails relative to each other can also cause damage to the rails themselves if they contact each other during their relative movement.
One type of clamp that has been used to hold the side rails adjacent each other is in the form of a C, with the C formed of three straight portions and having hooks at each end of the C. The hooks fit about the adjacent side rails and attempt to prevent sideways motion of the side rails during shipping. While this C clip seems to limit sideways motion of the side rails, it does not provide the ability to maintain the side rails of two different ladders adjacent, for instance, for stacking and storage purposes during shipping.


Portable Vacuum Food Storage System with a housing that contains a vacuum pump, an on off power switch, a vacuum pressure switch and a plurality of rechargeable DC batteries. The top of the housing has a gripping member help the user to twist and fasten the housing onto a mating container lid. The housing has a bayonet type fastener at its lower center portion that mates to a receptacle located on the lid, the lid has a vacuum releasing member that can be pressed by the user to relieve the vacuum in the container. The vacuum housing is capable of resting on the lid in a stable manner so that the vacuum operation can take place unattended by the user. The vacuum lid is capable of fitting on standard TupperWare or Rubber Maid containers.

This invention relates generally to the field of vacuum producing appliances and more specifically to a portable vacuum food storage system.
The idea of using a vacuum to extend the useful live of various types of foods is well known.
A vacuum is routinely used in the canning process to remove oxygen that can otherwise cause mold or bacteria to build up inside a food can. More recently, vacuum producing devices have been marketed that remove air from plastic bags and containers so that the user can create their own long term vacuum food storage.
These devices are primarily designed for use with plastic bags where a food is inserted into the bag, the open end of the bag is placed in a vacuum producing device so that the air is removed from the bag and the device then heat seals the end of the bag to trap the vacuum inside the bag. A major manufacturer of such an appliance is the Tilia Corporation of San Francisco, Calif. Their device, known as "Food Saver" also can come with a hose attachment to mate with specially designed lids and associated containers.
Although the Food Saver system is effective, there are certain deficiencies that the present invention addresses. First, when the user of the Food Saver System attaches the vacuum hose to a container, he or she is forced to hold the hose until the vacuum is produced. This means that either the vacuum pump must be large enough to quickly produce a vacuum or, if a small vacuum pump is used, the user must wait patiently for the vacuum to be produced. Second, the Food Saver unit and others like it tend to be powered by household voltage and therefore are required to be in close proximity to an outlet. Thirdly, a separate lid must be used for each container having a different top dimension. Fourth, The Food Saver unit and others like it are designed for long term food storage. They use heavy walled polycarbonate containers to be able to store a vacuum for long periods because there is no provision to automatically recharge the vacuum of a less expensive thinner walled container such as a polyethylene container.


HIV-related weight loss, HIV-related cachexia and HIV-related wasting syndrome can be treated by administering therapeutic amounts of the steroid .DELTA.5-androstene-3.beta.-ol-7,17 dione and metabolizable precursors thereof, such as .DELTA.5-androstene-3.beta.-acetoxy-7,17 dione, which are readily metabolized in vivo to .DELTA.5 androstene-3.beta.-ol-7,17 dione. Such treatment can be prophylactic, modulatory, ameliorative or curative in nature.

An involuntary and progressive loss in body weight is a common symptom of HIV infection (hereinafter "HIV-related cachexia"). Such weight loss can be conveniently categorized as "chronic" when the weight loss occurs gradually over a period of about three months, and "acute" when the weight loss occurs rapidly (i.e., over a period of less than about three months) with an eventual recovery of the lost weight. As defined by the Centers for Disease Control (hereinafter "CDC"), when such weight loss amounts to greater than a ten percent (10%) loss in baseline body weight and is combined with either chronic diarrhea (i.e., at least two loose stools per day for more than thirty days) or chronic weakness and fever (i.e., weakness and/or fever which has been constant or intermittent for more than thirty days) in the absence of a secondary infection (i.e., lack of an infectious agent other than HIV which may account for any of the referenced symptoms), the weight loss is classified as HIV-related wasting syndrome (hereinafter "wasting syndrome"). It is noted that, based upon this definition of the wasting syndrome, all persons afflicted with the wasting syndrome suffer from HIV-related cachexia, but only a portion of those suffering from HIV-related cachexia are afflicted with the wasting syndrome.
In contrast to starvation-induced weight loss, HIV-related cachexia results in profound tissue depletion that does not respond readily to nutritional therapy.
It has been suggested by various researchers in the field that the wasting syndrome would best be characterized by the degree of involuntary depletion of lean body mass, predominately muscle protein, rather than simply body weight. However, this suggestion has not been widely accepted by the medical community and is still being debated.
The wasting syndrome is known to play a major role in the decreased quality of life of AIDS patients, and constitute a major cause of morbidity and mortality in patients infected with HIV. After years of ignoring the syndrome, the CDC officially recognized the wasting syndrome as an AIDS-defining illness in 1987. Despite the use of antiretroviral agents, improvements in therapy and prophylaxis against many of the major disease complications, the prevalence of the wasting syndrome is increasing.
Etiology
It is widely believed that HIV-related cachexia and the wasting syndrome are mediated by a combination of factors including hypermetabolism, metabolic derangement, decreased caloric intake, malabsorption, cytokine activity, endocrine dysfunction, and myopathy.
Various treatment regimens have been investigated, including enteral & parenteral alimentation, appetite stimulants, anabolic agents, cytokine modulators and fatty acid supplements, with limited success. Hence, the search continues for alternative treatments for HIV-related cachexia and the wasting syndrome.

Use of .DELTA.5 androstenes in the treatment of HIV wasting syndrome


A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and reference bit lines being sensed are each from the same memory array of the CAM device. Noise present in one array therefore appears as common mode noise in both the active and reference bit lines, thereby permitting the sensing operation to be performed accurately even in the presence of increased noise.

An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing).
Once information is stored in a memory location, it is found by comparing every bit in memory with data in the comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, the local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a "match" indication. Otherwise, the CAM device returns a "no-match" indication. In addition, the CAM may return the identification of the address location in which the desired data is stored or one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.
FIG. 1 is a circuit diagram showing a conventional DRAM-based CAM cell 100, which includes two one-transistor (1T) DRAM cells 110a and 110b, and a four-transistor comparator circuit 120 made up of transistors Q2 through Q6. DRAM cells 110a and 110b are used to store values. Generally, the content of cell 110a is the logical NOT of the content of cell 110b. However, the cells 110a, 110b may also store the same values, i.e., "1", "1", or "0", "0", so that the CAM cell is respectively set to "always match" or "always mismatch" states. DRAM cell 110a includes transistor Q1 and a capacitor CA, which combine to form a storage node A that receives a data value from bit line BL1 at node U during write operations, and applies the stored data value to the gate terminal of transistor Q2 of comparator circuit 120. Transistor Q2 is connected in series with transistor Q3, which is controlled by a data signal transmitted on data line D1, between a match line M and a discharge line D. The second DRAM cell 110b includes transistor Q3 and a capacitor CB, which combine to form a storage node B that receives a data value from bit line BL2 at node V, and applies the stored data value to the gate terminal of transistor Q4 of comparator circuit 120. Transistor Q4 is connected in series with transistor Q5, which is controlled by a data signal transmitted on inverted data line D1#, between the match line and the discharge line.
FIG. 2 is a block diagram of a portion of a CAM device 200 which includes a plurality of CAM cells, such as the CAM cell 100 of FIG. 1. For purposes of simplicity, only a portion of the CAM device 200 is illustrated. In particular, some well known components, such as the previously discussed comparand register, control logic, and I/O logic are not illustrated. The device 200 includes two arrays 210a, 210b of CAM cells 100. Each array 210a, 210b includes its own bit lines (e.g., BL11–BL16 for array 210a, BL21–BL26 for array 210b) and word lines (e.g., WL11–WL13 for array 210a). Each word line WL11–WL13, WL21–WL23 is coupled a respective word line driver 220a, 220b. Similarly, each bit line is also coupled to respective bit line drivers (not illustrated). The CAM device 200 also includes a plurality of sense amplifiers 230. Each sense amplifier 230 is coupled to the CAM cells 100 of two separate bit lines (e.g., bit lines BL11, BL21) from two different arrays. This type of architecture, where a sense amplifier is coupled to bit lines from different arrays, is known as an open bit line architecture.
Now referring back to FIG. 1, in order perform a write operation upon a CAM cell, the data values (which are complements) to be stored are respectively written to dynamic storage nodes A and B by applying appropriate voltage signals (e.g., Vcc for logical '1' or ground for logical '0') on bit lines BL11 and BL21, and then applying a high voltage signal on word lines WL1 and WL2. The high voltage on word lines WL1 and WL2 turn on transistor Q1 and Q2, thereby passing the voltage signals to dynamic storage nodes A and B. Refresh circuitry (not illustrated), periodically refreshes the charges stored in capacitors CA and CB, so the data does not decay over time.
In order to perform a match operation, the data stored at nodes A and B are respectively applied to the gate terminals of transistors Q2 and Q5 of comparator circuit 120. Comparator circuit 120 is utilized to perform match (comparison) operations by, for example, precharging the match line M, grounding the discharge line D, and transmitting an applied data value and its complement respectively on data lines D1 and D1# to the gate terminals of transistor Q3 and Q6, respectively. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q2 and Q3 and the discharge line D, or through the signal path formed by transistors Q5 and Q6 and the discharge line D. For example, when the stored data value at node A and the applied data value transmitted on data line D1# are both logic "1", then both transistors Q2 and Q3 are turned on to discharge match line M to the discharge line (e.g., ground). When a match condition occurs, match line M remains in its pre-charged state (i.e., no signal path is formed by transistors Q2 and Q3, or transistors Q5 and Q6).
In order to perform a read operation, data stored as a charge level in the capacitors CA, CB of one of the dynamic storage nodes A, B of the CAM cell 100 is sensed using an associated sense amplifier 230 (FIG. 2) which compares the voltage level of a bit line coupled to one of the dynamic storage nodes (known as the active bit line) with the voltage level of a bit line not coupled to any dynamic storage nodes (known as the reference bit line). For example, node A of the CAM cell 100 which appears as the top left CAM cell illustrated in FIG. 2 can be sensed by first precharging two bit lines. The two bit lines to be precharged would include the bit line BL11 which will couple the CAM cell 100 to the sense amplifier 230 (i.e., the active bit line), as well as the other bit line BL21 coupled to the same sense amplifier 230 (i.e., the reference bit line). As illustrated in FIG. 2, each sense amplifier has one input coupled to a bit line of array 210a and another input coupled to a corresponding bit line of array 210b. The word line WL13 associated with the CAM cell 100 would then be charged, causing the transistor Q1 in the CAM cell 100 to conduct and thereby share the charge of capacitor CA with bit line BL1. The charge sharing alters the voltage level of bit line BL11. The sense amplifier 230 is then used to detect the change in potential between BL11 and BL21. The sense amplifier outputs an indication of the state stored at storage node A as a signal indicating the relative potential difference between bit lines BL11 and BL21 on line 235.
The performance of the above described read operation suffers from many noise issues since the sensing mechanism relies on the reference and active bit lines to be from two separate arrays of the device during a sensing operation. As CAM devices increase in density and therefore power consumption, the level of noise within a CAM cell is likely to increase. There is therefore a need for a CAM device architecture which has better noise immunity.

This patent is subject to a terminal disclaimer.


A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.

1. Field of the Invention
The present invention relates to a memory control apparatus, an information processing apparatus, and a memory control method.
2. Description of the Related Art
When printing process is performed with image data in PDL (Page Description Language) format, the image data in the PDL format are expanded into image data in a raster format (hereinafter referred to as "raster image data"), and the printing process is performed based on the raster image data. The processing for generating the raster image data from the image data in the PDL format is called RIP (Raster Image Processing) processing. An image forming system for performing high-speed processing for large-volume printing businesses is likely to employ a configuration in which a DFE (Digital Front End) apparatus for performing the RIP processing and an image forming apparatus for printing an image onto paper, which is a recording medium, based on raster image data are separately provided. In this case, the DFE apparatus and the image forming apparatus are connected via a communication cable and the like, and the RIP-processed raster image data are transferred from the DFE apparatus to the image forming apparatus via information communication based on, for example, PCI Express (hereinafter referred to as "PCIe") standard.
In this kind of image forming system, a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) capable of achieving high-speed data transfer speed is often used as memory for temporarily storing raster image data transferred from the DFE apparatus to the image forming apparatus. The DDR-SDRAM (hereinafter abbreviated as "DDR") can exchange data both at the rising and the falling edges of a clock signal. Theoretically, the DDR provides a data transfer speed twice as fast as the data transfer speed of an SDRAM operating with the same clock.
Writing and reading of data to/from the DDR is achieved by access to a memory cell specified by two addresses, i.e., a row address and a column address. When the same row address is accessed successively at this occasion, writing and reading of data can be performed at a high speed. On the other hand, when a row address is switched frequently, and in particular, when data are written and read alternately by specifying different row addresses, it takes time to wait for completion of command reception every time writing and reading are switched, and this reduces the performance.
The above image forming system performs, in parallel, processing for transferring raster image data from the DFE apparatus to the image forming apparatus and writing the raster image data to the DDR and processing for printing an image based on the raster image data read from the DDR. Therefore, writing and reading of the raster image data to/from the DDR is alternately performed in a time division manner, and switching frequently occurs between writing and reading of data with different row addresses specified, and the data transfer efficiency is considered to decrease.
For example, a memory bandwidth control apparatus as described in Japanese Patent Application Laid-open No. 2005-84907 is known as a technique for improving the data transfer efficiency between an external device and memory. In this memory bandwidth control apparatus, an I/O buffer is provided to dynamically allocate a memory bandwidth for only an external device requesting data transfer among multiple external devices connected via an input/output port, and this can reduce useless consumption of the memory bandwidths as compared with a case where memory bandwidths are fixedly allocated to the multiple external devices, whereby the data transfer efficiency between the external devices and the memory is enhanced.
However, the technique described in Japanese Patent Application Laid-open No. 2005-84907 is a technique for improving the data transfer efficiency by allocating a memory bandwidth for only an external device requesting data transfer among the multiple external devices. Therefore, when the technique described in Japanese Patent Application Laid-open No. 2005-84907 is applied to the above image forming system, it is impossible to perform, in parallel, the processing for transferring the raster image data from the DFE apparatus to the image forming apparatus and writing the raster image data to the DDR and the processing for printing an image based on the raster image data read from the DDR, and this reduces the performance as the image forming system. When the transfer of the raster image data from the DFE apparatus to the image forming apparatus and the printing of the image based on the raster image data read from the DDR are performed in parallel, switching frequently occurs between writing and reading of data having different row addresses specified for the DDR even if the technique described in Japanese Patent Application Laid-open No. 2005-84907 is applied, and therefore, the data transfer efficiency is considered to decrease.

Memory control apparatus, information processing apparatus, and memory control method


Provided are a CMOS image sensor and a method for fabricating the same. A nanopillar is plurally formed at an upper end of a light receiving element.

1. Field
The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor, and more particularly, to a CMOS image sensor having a great photosensitivity and a method for fabricating the same.
2. Description of the Background Art
A charge-coupled device (CCD) image sensor has been much used owing to its simple circuit and its good performance about a picture quality and a noise. However, because a mobile equipment needs a low power and a high integration, attention is being paid to a complementary metal oxide semiconductor (CMOS) image sensor satisfying the low power and the high integration.
The CMOS image sensor refers to a semiconductor device for converting an optical image into an electric signal. The CMOS image sensor comprises a light detecting part for detecting light, and a logic circuit part for data processing the detected light into the electric signal. The CMOS image sensor employs a switching method in which a MOS transistor is provided as much as the number of pixels using a CMOS technology, and an output is sequentially detected using the MOS transistor.
The CMOS image sensor is fabricated using a conventional CMOS transistor process. The CMOS image sensor has an advantage of less power consumption, low price, and high integration. Accordingly, by an intensive research for some years past, the CMOS image sensor is being expected to be an alternative of the CCD image sensor in many applications.
However, despite having the lower power and the high integration, the CMOS image sensor has a disadvantage that it has a smaller photosensitivity than the conventional CCD image sensor due to a dark current. Thus, many researches are in progress to solve the disadvantage.
The conventional CMOS image sensor will be described below.
FIG. 1 is a plan view illustrating the conventional CMOS image sensor. FIG. 2 is a cross-sectional view taken along line 2-2′ of FIG. 1.
Only a light receiving region for receiving light, and a transistor region for processing the received light into an electric signal will be illustrated and described below.
In the conventional CMOS image sensor, light receiving elements 106 and 108 such as a photodiode (PD) are formed in the light receiving region on a silicon substrate 101 having P-impurity regions 102 formed at both sides. A floating diffusion 104 is formed in parallel at one side of the light receiving elements 106 and 108 in the transistor region. A transfer gate 103 is positioned on the floating diffusion 104. A shallow trench isolation 105 is formed along an edge of the silicon substrate 101 to isolate the above devices from other devices.
The CMOS image sensor comprises a reset transistor (Rx), a driving transistor (Dx), and a selection transistor (Sx) connecting with the floating diffusion 104.
A non-described reference numeral 107 denotes an oxide film.
As shown in FIG. 2, in the conventional CMOS image sensor, the light receiving elements 106 and 108 are formed by a large area to effectively receive a large amount of light. The light receiving elements 106 and 108 are of a structure where a P+ impurity region 106 doped with P-type impurities is layered on an N impurity region 108 doped with N-type impurities, and are of a type where they are exposed as light receiving surfaces.
The light receiving surfaces of the light receiving elements 106 and 108 are of a flat structure where they are formed of crystalline silicon. Due to the flat structure, the conventional light receiving elements 106 and 108 have a limitation of a light receiving capability as follows.
First, in light receiving portions of the light receiving elements 106 and 108, the crystalline silicon has a small absorption coefficient for visible rays. In general, a wavelength of light absorbed by material is greatly dependent on a bandgap of the material. The crystalline silicon used for the light receiving portions of the light receiving elements 106 and 108 has an indirect bandgap of 1.12 eV and thus, absorbs only light having a short wavelength of 1.1 μm or less. However, the absorption coefficient of the crystalline silicon for the visible rays of the wavelength of 1.1 μm or less cannot sufficiently generate carriers transferred to the floating diffusion 104. Thus, in the crystalline silicon of the light receiving portion, its absorption coefficient is too small to sufficiently form the carriers.
Second, there is a loss of light not absorbed but reflected from the crystalline silicon that is the light receiving portion. Some of the light incident on the light receiving elements 106 and 108 induce light generation and form the carriers flowing to the floating diffusion 104, but other is reflected and lost without re-absorption. It is known in the art that an amount of the reflected and lost light is greater than an amount of the light inducing the light generation.
Third, a light receiving area of the CMOS image sensor does not exceed an area of the CMOS image sensor. In the conventional CMOS image sensor, the light receiving elements 106 and 108 are parts of the CMOS image sensor. Thus, the area of the light receiving elements 106 and 108 does not exceed the area of the CMOS image sensor. Since a cell size of the CMOS image sensor should reduce for high integration, a reduction of the area of the light receiving elements 106 and 108 gradually degrades the light receiving capability of the CMOS image sensor.

Complementary metal oxide semiconductor image sensor and method for fabricating the same

Korea Advanced Institute of Science & Technology


In one example, a method includes outputting, by a computing device and for display, a graphical keyboard comprising a plurality of keys, and receiving, by the computing device, an indication of a gesture detected at a presence-sensitive input device. The method further includes determining, by the computing device, an input posture of the gesture at the presence-sensitive input device, and applying, by the computing device and based at least in part on the input posture, at least one offset to a location associated with a key from the plurality of keys to determine an offset location associated with the key, and in response to receiving the indication of the gesture, selecting, by the computing device and based at least in part on the offset location, the key as a selected key.

Some computing devices (e.g., mobile phones, tablet computers, etc.) may provide a graphical keyboard as part of a graphical user interface for composing text (e.g., using a presence-sensitive input device and/or display, such as a touchscreen). The graphical keyboard may enable a user of the computing device to enter text (e.g., an e-mail, a text message, or a document, etc.). For instance, a display device of a computing device may output a graphical (or "soft") keyboard that enables the user to enter data by indicating (e.g., by tapping) keys displayed at the presence-sensitive display.
In some cases, the computing device may present a graphical keyboard with which the user interacts by tapping individual keys of the keyboard or essentially gesturing out a word by sliding his or her finger over the regions associated with the keys. In this way, graphical keyboards provide an input method that allows the user to enter characters, words, or a group of words by one or more gestures. As such, a graphical keyboard may allow the user to achieve a certain degree of efficiency by quickly and accurately entering text.
However, graphical keyboards have certain drawbacks. For example, a computing device may receive a series of tap gestures or sliding gestures from a user paying little attention to accuracy. The characters inputted by the computing device, though, may be different than the characters that the user attempted to select. Consequently, the user may need to correct the inputted characters. As such, entering text with gestures using a graphical keyboard may be difficult and reduce the speed at which the user may interact with the computing device.

Key selection of a graphical keyboard based on user input posture


This invention encompasses a method for inhibiting vascular cellular activity of cells associated with vascular lesion formation in mammals which involves administering an effective dosage of at least one antisense sequence to at least one gene expressing a cyclin or a cyclin dependent kinase which inhibits the expression of the gene. More particularly, the invention involves administering antisense sequences which inhibit the expression of cyclin A, B1, B2, C, D1, D2, D3, E or cyclin X (p46) cyclin X and cyclin dependent kinase cdc2, cdk2, cdk4 or cdk5. It is preferable to use two antisense sequences each from a different cyclin or cyclin dependent kinase. The cyclin or cyclin kinase depending kinase dosage is preferable administered in combination with proliferating cell nuclear antigen (PCNA). Antisense methods and compositions direct to inhibiting the expression of growth factors such as TGF-.beta..sub.1, TGF, bFGF, PDGF are also contemplated by the present invention.. The antisense sequences are incorporated into liposomes, particularly liposomes containing HVJ and which are directly administered intraluminally, intramurally or periadventitiously.. The methods of this invention are useful in treating a broad spectrum of vascular lesions such as lesions in the carotid femoral and renal arteries, particularly lesions resulting from renal dialysis fistulas. The invention is particularly useful in treating vascular grafts ex-vivo and prior to surgical grafting.

1. Technical Field
The field of this invention is inhibition of cellular activity related to vascular lesions.
2. Background of The Related Art
In the growth and maintenance of multi-cellular organisms, the organism has had to develop processes to activate or inhibit the proliferation of cells. The organism has developed numerous mechanisms, whereby signals are given to cells, by either intracellular or extracellular messengers. Control of proliferation provides for modeling of organs, maintenance of subsets of leukocytes in hematopoiesis, wound healing and the like. However, in many situations, such as injury or disease states, the response of the organism to the injury or disease may, in fact, be deleterious to the health of the organism.
The vascular response to injury involves an alteration in three fundamental cellular processes; cell growth, cell migration and extracellular matrix production. This vascular response to injury is characteristic of the pathogenesis of various vascular diseases including (but not limited to): atherosclerosis, restenosis after angioplasty, vein bypass graft stenosis, prosthetic graft stenosis, angiogenesis and hypertension. For example, atherosclerotic lesions evolve as a result of vascular smooth muscle migration into the subintimal space, proliferation and the production of abundant extracellular matrix. Similarly, restenosis after angioplasty, vein bypass graft stenosis, prosthetic graft stenosis, angiogenesis and hypertension involve abnormalities in vascular cell growth, migration and matrix composition. The precise mechanisms responsible for alterations in the regulation of these cellular processes are poorly characterized.
Dzau, Hypertension 8, 553-559 (1986) describes the vascular renin-angiotensin pathway. Geisterfer, et al., Circulation Research 62, 749-756 (1988) report that angiotensin II induces hypertrophy of cultured rat aortic smooth muscle cells. Barrett and Benditt, Proc. Natl. Acad. Sci. USA 85, 2810-2814 (1988) describe the expression of platelet-derived growth factor in human atherosclerotic plaques and normal artery wall. Powell, et al., Science 245, 186-188 (1989) report that inhibitors of angiotensin-converting enzyme prevent myointimal proliferation after vascular injury. Naftilan, et al., J. Clin. Invest. 83, 1413-1424 (1989) report the induction of platelet-derived growth factor A chain and c-myc gene expression by angiotensin II in cultured rat vascular smooth muscle cells. Sarzani, et al., J. Clin. Invest. 83, 1404-1408 (1989) describe the expression of various growth factors in aorta or normotensive and hypertensive rats. Majesky, et al., J. Clin. Invest., 88, 904-910 (1991) report the production of TGF-.beta..sub.1 during repair of arterial injury. Linder, et al., Circulation Research 68, 106-113 (1991) describe the role of basic fibroblast growth factor in vascular lesion formation. Daemen, et al., Circulation Research, 68, 450-456 (1991) report the role of angiotensin II in inducing smooth muscle cell proliferation in the normal and injured rat arterial wall. Ferns, et al., Science, 253, 1129-1132 (1991) report the inhibition of neointimal smooth muscle accumulation after angioplasty by an antibody to PDGF, Gibbons, et al., Clin. Research, 38, 287A (1990) report the modulation by transforming growth factor-.beta. of the bifunctional growth response of vascular smooth muscle cells to angiotensin II. Itoh, et al., Biochem. Biophys. Res. Comm., 176, 1601-1609 (1991) report the interaction of atrial natriuretic polypeptide and angiotensin II on protooncogene expression and vascular cell growth.
Simons and Rosenberg, Circ. Res., 70, 835-843 (1992) report that antisense oligonucleotides to non-muscle myosin heavy chain and c-myb suppress smooth muscle cell proliferation in vitro. Speir and Epstein, Circulation, 86, 538-547 (1992) report that antisense to proliferating cell nuclear antigen (PCNA) inhibits smooth muscle cell proliferation in vitro. Rosenberg et al., PCT/US92/05305, January 1993 describes an antisense approach of localized oligonucleotide therapy involving the inhibition of the c-myb or PCNA protein.
The relationship of the expression of cyclins at various phases of the cell synthesis and mitosis cycle are described in The Journal of NIH Research, December 1992, Vol. 4, pp. 55-59. FIG. 1 for example shows the approximate level of Cyclins A, B1, B2, C, D1, D2 and E during G1 (gap 1), synthesis, G2 (gap 2) and mitotic phase of cell proliferation. Williams, et al., The Journal of Biological Chemistry, Vol. 266, No. 12, Apr. 25 (1993), pp. 8871-8880 shows the isolation of cyclin x (p46).
Both of these later two articles and references such as O'Connor, et al., The Journal of Biological Chemistry, Vol. 286, No. 11, April 15, pp. 8298-8308 (1993) elucidate the interaction of various Cyclin dependent kinases such as cdc2 and cdk2 and Cyclins A and B.
Jaskulski et al., Science, Vol. 240, No. 4858, pp. 1544-6 (1988) describes the effects of antisense oligonucleotides on growing Balb/C313 cells. It was shown that the antisense molecule inhibited synthesis and mitosis and sense oligos had no effect. Sala et al., Proc. Natl. Acad. Sci., USA, Vol. 89, No. 21, pp. 10415-9 (November 1992) describes antisense sequences to c-myb gene which inhibit c-myb expression. Kimeki, J. Cell Biochem, Vol. 50, No. 1, pp. 1-9 (1992) describes antisense interruption of C-myc or Cyclin A in vitro. Doyle et al., Antisense Res. Dev., Vol. 1, No. 1 Spring, pp. 11-20 (1991) describes antisense oligonucleotides to Cyclin B in xenopus oocytes. Zindly et al., Biochem Biophys. Res. Commun., Vol. 1897, No. 3, pp. 1144-54 (1992) describes antisense interruption of the production of Cyclin A or Cyclin B in rats. Cyclin A antisense oligonucleotides are also described in Nature, Vol. 354, No. 6351, pp. 314-7 (1991) and Guerria et al., EMBO J., Vol. 10, No. 11, pp. 3343-9 (1991). These references report the effect of Cyclin A or Cyclin B oligos in metaphase I oocytes. Further, antisense studies in xenopus embryos are described in Development, Vol. III, No. 4 pp. 1173-8 (1991) and J. Cell. Biol., Vol. 114, No. 4, pp. 767-72 (1991). Lapidot-Lifson et al., Proc. Natl. Acad. Sci., USA, Vol. 89, No. 2, pp. 579-83 (1992) describe the down regulation of cdc2 with antisense oligonucleotides.

Inhibition of proliferation of vascular smooth muscle cell

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