A plurality of sensors measure rope depth at a plurality of locations along an axis of a winch drum for use by a control unit in determining rope defects.

Winch rope (often woven wire cable) is wound about a drum to effect lifting or pulling of the rope and/or load. The drum is normally rotated under power to wind the rope to provide lift or pulling force. The drum may be allowed to counter rotate in a controlled fashion to unwind the rope, thereby lowering the load or extending the rope from the drum.
Rope may be allowed to wind onto the drum in a free-form fashion. This may result in the rope winding onto the drum in a random or chaotic fashion. Rope may become concentrated in one area on the drum creating so called "bird's nests" or other undesirable states.
Steps can be taken to alleviate miswinding and other problems once they become known. However, the operator or control systems of the winching device may need to be made aware that a winding non-uniformity or error has occurred before the remedies can be deployed.
What is needed is a system and method for addressing the above, and related, issues.

System and method for detection and warning of winch rope non-uniformity


A golf tee comprising a shaft, a stopper portion disposed at an upper end of the shaft and a pivotable support portion mounted atop the upper end of the shaft is described. The shaft is adapted for insertion into a surface of ground. The support portion has a plurality of prong members mounted upon an upper horizontal surface thereof. The position of the support portion can be adjusted so that the upper surface of the support portion is arranged in parallel horizontal alignment with the ground surface. The prong members are adapted to support a golf ball placed thereupon.

Golf tees comprising an inflexible shaft with a substantially bowl-shaped support surface, upon which a golf ball is balanced, are known. It may be difficult to balance a golf ball upon such golf tees, detracting from the ability of a golfer to strike the ball in a fashion that affords the best drive possible. Difficulties in balancing the ball may be particularly enhanced where the playing surface is irregular. Further, it is theorized that the amount of surface contact necessary between the ball and the tee may hinder the distance of the drive when the ball is struck by a golf club in the known manner of play.
Such known golf tees may also be difficult to remove from the ground after a shot has been played from the tee. This difficulty may be enhanced in situations where the playing ground is hard and dry.
The present invention attempts to overcome at least in part the aforementioned disadvantages of previous golf tees.


An image module including a base member including a light transmissive material; a first layer having a first protruding pattern protruding from a first surface of the base member; a second layer including an opaque material and covering a second surface of the base member; and one or more image through-holes in the second layer and configured to pass light from a light source through the image through-holes and towards the protruding pattern to form one or more images.

1. Field of the Invention
The present disclosure relates to a mobile terminal, and more particularly, to an image module for implementing one or more images exposed to the outside of a mobile terminal, a mobile terminal having the same, and a manufacturing method of the image module.
2. Background of the Invention
In general, a terminal may be classified into a mobile (portable) terminal and a stationary terminal. The mobile terminal may be also classified into a handheld terminal and a vehicle mount terminal.
As functions of the terminal become more diversified, the terminal can support more complicated functions such as capturing images or video, reproducing music or video files, playing games, receiving broadcast signals, and the like. By comprehensively and collectively implementing such functions, the mobile terminal may be embodied in the form of a multimedia player or a device.
Various attempts have been made to implement complicated functions in such a multimedia device using hardware or software. As an example of such efforts, research on implementing images such as icons or logos on the mobile terminal is ongoing. However, there is the following problem. That is, icons of a user input unit, logos of a case, etc. are not easily implemented by any methods rather than printing.

Image module, mobile terminal having the same and manufacturing method of image module


The use of a palladium-doped zeolite for the adsorption of volatile organic compounds is described wherein the zeolite has a CHA framework type and is polymer-bound. Such zeolites have been found to have particular utility as packaging materials for the adsorption of volatile organic compounds, such as those originating from organic matter.

The over-ripening or spoiling of fruit, vegetables and other organic matter during transit or storage can lead to significant produce loss and wastage. This is an increasing issue for those involved in fresh produce supply chains which may involve long transit times and variable climatic conditions. Modification of the atmosphere in which the organic matter is stored has been shown to be an effective strategy to prolong produce life. For example, alterations in oxygen and carbon dioxide levels within produce packaging can reduce produce respiration rates and therefore slow down the spoiling of fresh produce.
Other strategies involve the removal of volatile organic compounds (VOCs) from within, or surrounding, the produce packaging. VOCs are typically emitted by the produce itself, or may be present in the environment in which the produce is stored or transported. The presence of such VOCs can, for example, accelerate the spoiling of produce, lead to unwanted odours or tastes, or produce colour changes or other changes in appearance.
One such VOC is ethylene. Ethylene is a plant hormone and has a key role in many physiological processes in plants. For example, exogenous ethylene can initiate fruit ripening which in turn can lead to release of ethylene as the fruit ripens leading to high local concentrations. Other fresh produce types are also sensitive to ethylene even if their own ethylene production is low. The rate of ethylene generation can be a key factor in determining local ethylene concentrations, and this rate varies significantly between produce types. Excessive ethylene levels can lead to, for example, the premature ripening of fruit and vegetables, the wilting of fresh flowers, and the loss of green colour and an increase in bitterness of vegetables.
The control of ambient ethylene levels has been found to be effective in prolonging the shelf-life of many horticultural products, and various methods of ethylene control are utilised commercially. Methods include those based on ethylene adsorption and oxidation, for example the use of potassium permanganate.
Palladium-doped zeolites have been found to act as ethylene adsorbents. For example, it is described in WO2007/052074 (Johnson Matthey Public Limited Company) that palladium-doped ZSM-5 may be used to adsorb VOCs, such as ethylene, which are derived from organic matter.
Adsorbents used to remove VOCs are typically used in the form of a powder or as granules. In the case of use within a fresh produce package the adsorbent material is typically incorporated into a label attached to the inside of the package, or may be contained within a sachet, pad or other insert located within the package.
WO2014207467A1 (Johnson Matthey Public Limited Company) describes a water-resistant composition for adsorbing VOCs comprising palladium-doped hydrogen ZSM-5 and at least one water soluble binder. Compositions are prepared and applied to Tyvek® paper.
It would be advantageous to incorporate the adsorbent materials into packaging materials as an alternative to providing the adsorbent inside a sachet, pad or other type of insert. In this case the adsorbent material would be more widely dispersed within the package and could be protected from direct contact with water. Furthermore, if the adsorbent material is combined with primary packaging there is no need for an additional insert or inserts to be placed inside the packaging. These advantages could lead to less adsorbent material being included, reduced packaging material, and fewer processing steps.
WO2016181132A1 (Innovia Films Ltd, Food Freshness Technology Holdings Ltd) describes a film for use in a packaging structure which comprises a coating on the film surface which comprises a binder and a particulate protuberent component able to remove VOCs. The examples describe the use of a palladium-doped zeolite as the protuberent component and ZSM-5 is mentioned.
The combination of adsorbent and polymeric materials remains a challenge, as binding of adsorbent materials with polymeric materials typically leads to a significant loss of adsorbent capacity and/or rate of adsorption, leading to poor performance. Resulting materials may also suffer from low stability. There remains a need to develop additional materials incorporating adsorbents which are suitable for use with fresh produce, for example as packaging films or other packaging materials.


A computer network system for building and/or synchronising a second database based on a first database. Accesses by work units are carried out on the first database from an application workstation, to generate, change or delete contents of the database. A first server and second server interconnected via a data connection guide and maintain the first database and a second database, respectively. The accesses take place using an encapsulation module that receives and decomposes the work units into one or more messages, enters the messages in the first database and sends the messages to the second database. A coexistence controller places change messages sent by the first database in a coexistence database, determines whether all messages of a transaction have been transmitted, determines application program elements for which changes are relevant, if all of the messages of the transaction have been transmitted, and reads out the placed change messages in a correct order.

This invention concerns a computer network system and procedures for building and/or synchronising a second database from/with a first database. In particular, the invention concerns those computer network systems in which a first, already existing database is to be transferred into a second database which is to be newly constructed. In complex systems with one or more front end stations/applications and a back end, migrations traditionally take place in such a way that first the front end is migrated and only then the back end. In practice, simultaneous migration of both the front end and the back end is often not indicated, for various reasons (high complexity, long down time of system). Above all in the case of large DP projects in which a single-step migration (so-called "big bang") from an existing database platform to the new database platform is ruled out, for a wide variety of reasons—e.g. because not all applications for access to the new database are yet completed, because for security reasons a full changeover to the new database is not yet indicated, because the operational behaviour of the new database still has to be investigated in detail, or similar—there is a need for a systematic approach which allows a controlled, gradual changeover from the existing database to the new database.
Furthermore, there is often the operational requirement to have the two databases in the practically consistent state at certain defined points in time, for instance at the end of the day. In other words, the data should be continuously kept synchronised on both database systems, and users should also be able to maintain the data, for instance using application software programs.
Since even after the initial transmission of the data from the first database to the second database (initial load), because of the continued maintenance of the first database, a very large number of changes of the data held in it can occur in a short time, approaches which are efficient regarding computing time and transfer cost (required communication bandwidth, incurred costs) are required. The demand on the system also increases if the changes are maintained online in the first database and are to be made available also in the second database as closely as possible in time (at least approximately in real time). In some cases, for collective or group changes, offline maintenance—at times of low operation—is also required and must be made possible.
Since the migration from the first database platform to the second database platform is generally carried out, as well as for application reasons (enterprise flow optimisation, enterprise restructuring, etc.) mostly from technical or IT points of view (faster access, more complex query options, change of hardware system platform, etc.), there are mostly considerable differences regarding the physical implementation, structures and organisational forms between the first and second databases. This aspect is particularly intensified if between the first and second databases there are structurally considerable differences regarding system architecture (hardware, operating system, database design and database implementation). In this case, changes which are to be made in the first database (=changes, deletions of existing entries, creating and filling new entries) cannot be mapped in the same way, i.e. not identically (1:1) in the second database. Also, changes are often complex, that is they affect a first plurality of entries in the first database, but because of the different structures and organisational forms a different plurality of entries in the second database, or entering changes in different and/or additional fields in the second database. This circumstance too excludes immediate maintenance of the changes in the second database in the identical way as it takes place in the first database.
Finally, it must be taken into account that in the case of large DP projects, usually multiple computer program applications access and change the databases. This circumstance—particularly in the case of online systems which are quasi-concurrent regarding accesses—has considerable influence on the strategy for keeping the second database up to date.
Because of transit times of messages/data flows in the networks in which the two databases are included and/or by which the two database platforms are connected to each other, and other influences (file length, priorities, etc.) in real time or online environments or even mixed (real time and batch processing systems), it is not directly possible to ensure that the changes are made available to the application software programs which access the second database in exactly the same sequence as they are executed in the first database. In other words, when data is transferred from one database to the other database, it can be overtaken by data which was transmitted earlier. This has the unwanted consequence that an "older" change can reset the data of a "newer" change to the "old" value. Also, because of these effects, the problem can occur that records are not yet completely maintained in the second database, so that incompletely changed, and thus in the end false, data is made available to the application software programs which access the second database.
Not least, efforts must be made so that the quality, operability, performance etc. of the original database is not considerably—ideally not at all—limited by the migration process.

Computer network system for building, synchronising and/or operating a second database from/with a first database, and procedures for it


A system for determining a fluid level in a pressurizable container comprising is disclosed. The system includes a service valve having a set of wrench flats defining parallel flat surfaces, one of the wrench flats having a recess defined entirely within its flat surface, a stop-fill device interconnected with the service valve and operable to rotate a first magnet inside the service valve in proximity to the recess in proportion to the amount of fluid in the pressurizable container, and a dial assembly having a dial face and a pointer attached to a second magnet, the second magnet housed in a magnet protrusion on a side of the dial face opposite the pointer and operable to fit into the recess in the service valve such that the dial moves on the dial face proportionately to the degree of rotation of the first magnet inside the service valve. In one variation, a sensor placed in the recess or adjacent a throat of the service valve is electrically connected to a remotely located gauge for displaying a reading corresponding to the level of fluid in the container.

There are many different types of containers, tanks, vessels, and canisters that are used for storing fluids. For convenience, this document will use the term "tank" throughout to refer to what could be any kind of container, vessel, canister, tank, or the like.
It is often desirable to allow for monitoring of the fluid level in a tank, particularly in cases where the tank is such that the fluid cannot conveniently be visually inspected. For this reason, many tanks are provided with devices for communicating a fluid level, for example through the use of a fluid-level gauge that can provide an indication of the amount of fluid present in a tank. There are many known examples of fluid level gauges that use a float or a capacitance to mechanically and/or electrically drive an indicator.
It is also desirable in some cases to provide a stop-fill device for preventing a tank from being over-filled. Known stop-fill devices include those intended to be used in tanks that require a fluid to pass through an inlet valve in order to enter the tank. Typically such stop-fill devices include a float that rides on the surface of the fluid in the tank. As fluid is added to the tank, the float rises to a certain level at which point it causes, for example by releasing a spring, the inlet valve to close. Once the inlet valve is closed, no additional fluid can be added to the tank.
It is further desirable in some cases to allow the indicating dial of the level gauge to be removable from the tank-valve assembly. For example, tanks are commonly traded-in for refilling, and the owner returning an empty tank may wish to remove the dial and use it on the newly filled tank. In other cases, the dial may be removed to prevent damage during storage or refilling.

Service valve assembly having a stop-fill device and remote liquid level indicator


Systems and methods for automatically editing a softcopy document using a hardcopy markup document are disclosed. The method includes scanning pages of the hardcopy markup document including editing marks; identifying file information of the hardcopy markup document; retrieving the softcopy document corresponding to the hardcopy markup document from a storage device based on the identified file information; recognizing marked regions present on at least one of the scanned pages, the marked regions includes at least one of the editing marks; creating an edit information document based on the recognized marked regions; converting the marked regions into an editable format; and creating an edited softcopy document by making one or more changes on each page of the retrieved softcopy document based on the edit information document.

For editing documents, such as an electronic document, an editor, such as a senior editor, can either edit the electronic copy directly on the computing device, or may print a hardcopy, and then make hand-written mark-up corrections to the hardcopy. Based on the hardcopy including mark-ups, the senior editor or some other person can change the electronic copy later. Further, in the legal industry, for example, lawyers receive numerous memos and/or briefs that they mark up, edit, revise, and have their assistants make copies of to be distributed to other lawyers or their clients. Some editors may prefer marking-up a hardcopy to marking-up an electronic copy as it can be more convenient or comfortable to their tradition of working with pen and paper.
Further, the format or layout of text, etc., may change on the electronic document as editing marks are added. The three dimensional nature of hardcopy may help some people organize and structure their work and allow free form marking. Further, the editing marks on hardcopy can capture a history of interactions on the document. More than one editor can interact and communicate through written annotations. Lastly, hardcopy does not require any presentation device, such as computers, laptops, PDAs, cellular phones, etc. For these and other reasons, marking-up a document from a hardcopy can be preferred over marking-up an electronic document.
While marking-up the hardcopy can be convenient for the editor, it is also often tedious and time consuming to associate the indicated changes within the electronic document. In many instances, there are significant costs associated with the expense and time required to manually incorporate hand written editing markings such as proofreader's marks into an electronic document. The person must repeatedly reference the hardcopy markup, and manually associate the marking within the unmarked electronic copy.

Systems and methods for editing documents


An analog value adjustment circuit includes a fuse circuit that outputs fuse data whose value changes corresponding to whether first through Nth (N is an integer of two or more) fuse elements are in a cutting state, or in a non-cutting state and an analog value output circuit that receives the fuse data from the fuse circuit, and outputs an analog value that is adjusted in a given adjustment range corresponding to the fuse data. When the fuse data from the fuse circuit is data indicating that all the first through Nth fuse elements are in the non-cutting state, the analog value output circuit outputs the analog value with a typical value that is a value between a maximum value and a minimum value in the given adjustment range.

1. Field of the Invention
The present invention relates to an analog value adjustment circuit, a display driver circuit, and a method of adjusting an analog value.
2. Description of the Related Art
In order to absorb the process-parameter variation due to a manufacturing variation in semiconductor integrated circuits, a fuse circuit is sometimes used. Using the fuse circuit, analog values, such as a desired voltage value, current value, and oscillation frequency in a circuit, can be adjusted corresponding to the states set up by fuse elements that can be cut (blown out). For example, in the case of a display driver circuit which drives a display panel, such as a liquid crystal panel, a liquid crystal driving voltage with high precision is needed in order to carry out extremely fine picture expressions. However, it is difficult to generate an optimal liquid crystal driving voltage because of manufacturing variations or the like of the liquid crystal materials and the display driver circuit of the liquid crystal panel. Then, by generating a condition corresponding to a setup state (cutting state or non-cutting state) of the fuse elements using the fuse circuit and by carrying out fine-adjustments of the liquid crystal driving voltage corresponding to this state, an optimal picture expression can be realized.
However, a cutting (trimming) process of the fuse elements in an inspection process of semiconductor integrated circuits needs to be carried out on all semiconductor integrated circuits (semiconductor chips) on a wafer. For this reason, the cutting process of the fuse elements ends up taking a long time, thereby causing a problem of inviting an increase in the cost of the chip or the like.

Analog value adjustment circuit, display driver circuit, and method of adjusting analog value


A device is disclosed for removing a nut frozen is place regardless of the degree to which the corners of the nut have been rounded by a prior attempt to remove such nut by an ordinary wrench. The device is formed with an opening, which is sized to receive the nut and formed with a plurality of teeth preferably arranged such that a leading or cutting edge of each tooth engages approximately with a midpoint of a flat of the nut. The front and rear faces of each tooth form an angle of less than 90.degree. and a gullet between teeth, which is defined by a rear face of one tooth and a front face of a next adjacent tooth, is sized to freely receive the corner(s) between the flats with which the leading edges of an adjacent pair of teeth engage. The gullet is shaped and sized to permit the formation of a chip upon penetration of a leading edge into a flat of a nut, which is operable to lock the nut for rotation with the device.

It is oftentimes found that nuts become frozen on a bolt due to the build-up of rust on their mounting threads and/or due to the improper threading of the nut onto the bolt. The resultant tight fit makes it extremely difficult to remove the nut by manual manipulations of a conventional wrench with the result that the nut, which is typically formed of relatively soft metal as compared to the wrench, has its corners rounded off due to slippage of the wrench. When this occurs, a wrench is no longer able to effectively grip the nut and a saw, torch or special cutting tool is required to be employed to remove the damaged nut.


A toy construction set has a plurality of interconnectable objects each having a plurality of faces. Some of these faces have a connector, while other faces lack a connector but have a fibrous or pierceable material. The connector includes a first hub and a second hub that are concentrically nested. Each of the hubs has on one side thereof a plurality of spiral prongs. The spiral prongs on the first hub spiral in a direction opposite that of the spiral prongs on the second hub. The connector also has a manually operable link connected between the first and the second hub for relatively rotating them in opposite directions. The play activity proceeds by adjoining a pair of the objects with a prominent, connector-bearing face of one of the pair touching a prominent connector-free face of the other one of the pair. The player will counter-rotate the hubs in the connector of the prominent connector-bearing face to embed their spiral prongs in the fibrous or pierceable material of the prominent connector-free face.

1. Field of the Invention
The present invention relates to toys, and in particular, to construction sets allowing a player to interconnect play objects.
2. Description of Related Art
Toy constructions sets have been popular for generations. Early Erector™ sets used stamped metal struts that could be bolted together to build various constructions. However, using nuts and bolts requires significant manual dexterity and such small parts present a swallowing risk to small children.
More recent Lego™ construction sets employ rectangular blocks that connect by snapping the lower edges of a block down around cylindrical studs atop an underlying block. Such an arrangement is easy to assemble but the block to block strength is relatively small. In addition, the blocks interconnect in only a small number of ways and the position of a block cannot be finely adjusted relative to another block.
Hook and loop fasteners have been used to interconnect objects. While such fasteners interconnect with relatively little effort, disconnecting them can require some strength. Small children may not have the strength needed to disconnect such fasteners if they are used in toys.
Other known playsets include a number of pieces that can be mixed and matched to produce different figures. For example, the set can have a number of different items representing different faces, hairstyles, upper torsos, hips and legs, shirts, pants, skirts, shoes, fashion accessories, etc. A child can select different elements to compose a custom figure. These elements are often thin panels intended to create a two dimensional image.
See also U.S. Patent Application Publication No. 2004/0069980 and the following U.S. Pat. Nos. D367,438; D374,609; 226,453; 2,033,039; 2,205,550; 2,354,810; 2,407,879; 2,668,304; 2,809,067; 3,176,979; 3,222,744; 3,386,763; 3,634,178; 3,813,094; 3,849,839; 3,964,364; 4,003,549; 4,009,786 4,007,516; 4,165,811; 4,308,646; 4,338,836; 4,498,827; 4,505,468; 4,518,277; 4,526,363; 4,605,216; 4,641,826; 4,645,193; 4,705,442; 4,761,027; 5,007,616; 5,496,021; 5,624,110; 5,624,167; 5,728,116; 6,296,656; 6,468,309; 6,494,657; 6,520,464; 4,474,489; 4,532,622; 4,711,596; 5,133,617; 5,651,570; 5,873,379; 5,899,621; 6,123,035; 6,336,766; 6,616,369; 6,726,421; 6,726,422; and 7,100,854.


Systems, methods, computer-readable media, and graphical user interfaces for presenting search results having collapsed domains are provided. A search result obtaining module obtains search results based upon a received query. Upon obtaining the search results, search results having the same domain are associated with one another. Thereafter, search result clusters of associated search results are formed. In some embodiments, the search result clusters may be formatted to include desired search result cluster attributes. The search result clusters are presented such that two or more associated search results form a single cluster of search results rather than being presented individually. In some embodiments, an option to view more search results with the same domain may be provided.

Search engines have become an efficient and effective tool for finding and retrieving information, i.e., search results, relevant to a user's query. The relative placement of search results greatly affects the probability that a user will find desired information. Today, to determine the relative placement of search results, many search engines organize search results based on a document ranking. The method employed to rank documents varies widely among search engines. Most search engines, however, determine a document ranking based on, at least in part, one or more query terms, e.g., a word or phrase entered by a user. For instance, in a vertically displayed listing of search results, the result(s) most relevant to the user's query terms are generally positioned at or near the top of the listing.
As a result of listing documents based, at least in part, on document ratings, documents having the same domain may be dispersed throughout the displayed search results. For example, the search results of a specific query may list a document on the first search result page and another document having the same domain on the fifth search result page. Accordingly, the dispersed listing of documents having the same domain may require a significant amount of time to view each search result page to locate the desired information. As such, user satisfaction may decline. Moreover, a user with a limited amount of search time may be unsuccessful in locating the desired information.
In addition, a dispersed listing of documents having the same domain may utilize a significant amount of search result space. For example, the search results of a specific query may list ten documents on the first search result page having the same domain and another ten documents on the second search result page having the same domain. Each such search result listing may include, for example, a snippet, the URL, the title, and the like. As such, multiple search results pertaining to documents having the same domain may utilize and clutter a majority of both the first and second search result pages. In addition to the amount of search result space utilized by multiple search results related to documents having the same domain, the clutter may result in a tedious and time consuming user query experience.


A transmission can be provided which achieves multiple speeds while maintaining good balance of gear ratio steps between gears by having a first clutch which selectively connects a first intermediate output member and a fourth rotating element RE4 together, a second clutch which selectively connects an input shaft and a second rotating element RE2 together, a third clutch which selectively connects the first intermediate output member and a first rotating element RE1 together, a fourth clutch which selectively connects the input shaft and the first rotating element RE1 together, a fifth clutch which selectively connects a second intermediate output member and the first rotating element RE1 together, a first brake which selectively holds the first rotating element RE1 to a transmission case, and a second brake which selectively holds the second rotating element RE2 to the transmission case.

1. Field of the Invention
This invention relates to a multi-speed transmission for a vehicle, which is provided between a prime mover and a driven wheel in a vehicle such as an automobile.
2. Description of the Related Art
A vehicle is normally provided with a transmission between a primer mover and driven wheels. One such known transmission is a multi-speed transmission that is used to achieve a plurality of predetermined gear ratios or gears. Planetary gear type multi-speed transmissions which use a plurality of planetary gear sets and engagement elements such as clutches and brakes to engage the elements that form those planetary gear sets together are widely used. For example, Published Japanese National Phase Application No. 2003-514195, JP(A) 2002-206601, JP(A) 2002-213545, JP(A) 2002-227940, JP(A) 2002-266956, and JP(A) 2002-295609 propose a multi-speed transmission which has a first transmitting portion which includes two front planetary gear sets and a second transmitting portion which includes two rear planetary gear sets and can achieve multiple speeds of seven or more forward gears. In particular, the multi-speed transmission disclosed in Published Japanese National Phase Application No. 2003-514195 has two non-switchable front planetary gear sets and a plurality of engagement elements, and is able to achieve at least seven forward speeds (i.e., gears) by selectively engaging those engagement elements.
When further increasing the number of speeds (i.e., gears) of the multi-speed transmission for a vehicle, it is desirable that the gear ratio steps (i.e., the change ratio of the gear ratios of consecutive gears) be equal or near thereto. With this kind of conventional multi-speed transmission, however, the gear ratio steps of the gears are not always good. For example, as illustrated in FIG. 1(B) of Published Japanese National Phase Application No. 2003-514195, the gear ratio step between first gear and second gear is 1.86, which is a large step. There is also a fair amount of variation in the sizes of the gear ratio steps, which is undesirable. There has therefore been a need for the development of a multi-speed transmission for a vehicle that can achieve multiple speeds (i.e., gears) while maintaining good balance among the gear ratio steps between gears.


Methods, apparatuses, and systems for software stack building using a logically protected region of a computer-readable medium are described. An image of a software stack may be stored in a computer-readable medium. A computer, coupled to the computer-readable medium, may build an executable software stack on the same computer-readable medium from the image. The image may be stored in a logically-protected region of the computer-readable medium. After the storing and prior to the building, data stored on the computer-readable medium outside of the logically-protected region may be erased.

Service providers such as banks and other financial institutions typically provide self-service financial transaction devices (SSFTDs) such as automated teller machines (ATMs) for use by their customers. While the SSFTDs provide a useful service to the customers, there is a significant burden imposed on the service provider to maintain and upgrade the SSFTDs. This burden becomes nearly overwhelming in the case of large institutions, which may have thousands upon thousands of SSFTDs distributed across thousands of miles.
When periodically upgrading the software on the SSFTDs, the service provider may often need to upgrade all of the SSFTDs within a short window of time, so that, for instance, all of the SSFTDs provide a consistent user experience. The SSFTDs are commonly interconnected by a network, however providing upgraded software to all of the SSFTDs over the network may not be practical or economical due to typical network bandwidth limitations.
Even if a software upgrade is eventually provided to the SSFTD, the upgrade usually involves a complex installation sequence, performed locally at the SSFTD, which is prone to error and therefore not reliably repeatable over a large number of machines. Potential errors are even more likely where a human service operator is involved in locally managing the installation sequence at a given SSFTD.

Software stack building using logically protected region of computer-readable medium


A plurality of internal power supply voltage generating circuits generate internal power supply voltages. A column select signal at the same voltage level as a first internal power supply voltage applied to a sense amplifier is generated to an I/O gate circuit connecting a bit line pair and an internal data line pair together. A current driving capability of an I/O gate circuit is made relatively small, so that rapid change in potential on a sense node of a sense amplifier is prevented. Thereby, inversion of latched data of the sense amplifier due to collision of data is prevented in such a case voltages on the internal data line pair are not equalized sufficiently.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which has an internal power supply voltage generating circuit for generating a plurality of internal power supply voltages at different voltage levels.
2. Description of the Background Art
FIG. 17 schematically shows a whole structure of a semiconductor memory device in the prior art. In FIG. 17, a semiconductor memory device includes a memory cell array 900 which has a plurality of memory cells MC arranged in a matrix form. In this memory cell array 900, a word line WL is arranged corresponding to each row of memory cells MC, and a bit line pair BLP is arranged corresponding to each column of memory cells MC. Each word line WL is connected to memory cells MC in the corresponding row, and each bit line pair BLP is connected to memory cells MC in the corresponding column. As will be described later further in detail, each bit line pair BLP has bit lines BL and /BL transmitting data signals complementary with each other.
The semiconductor memory device further includes an address buffer 902 which receives an externally supplied address signal and generates an internal address signal, a row select circuit 904 which drives the word line corresponding to an addressed row in memory cell array 900 to the selected state in accordance with an internal row address signal generated from address buffer 902, a column select circuit 906 which generates a column select signal for selecting the addressed column in memory cell array 900 in accordance with an internal column address signal generated from address buffer 902, sense amplifiers which are arranged corresponding to the respective bit line pairs BLP in memory cell array 900 for differentially amplifying potentials on the corresponding bit line pairs when made active, and I/O gates which connect a bit line pair corresponding to an addressed column in memory cell array 900 to an internal I/O bus line 907 in accordance with the column select signal generated from column select circuit 906, respectively. In FIG. 17, the sense amplifiers and the I/O gates are represented by one block 908.
The semiconductor memory device further includes an I/O buffer 910 for performing input/output of data into and from the device, and a read/write circuit 912 for transmitting internal data between I/O buffer 910 and internal I/O line 907. Read/write circuit 912 includes a preamplifier which amplifies memory cell data read from memory cell array 900 for transmission to an output buffer included in I/O buffer 910, and a write driver which produces and transmits write data to internal I/O bus 907 at a predetermined timing in accordance with the internal write data received from an input buffer included in I/O buffer 910.
Further, the semiconductor memory device includes a timing control circuit 914, which receives externally supplied control clock signals, i.e., a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, and generates control signals for controlling operations related to the row selection and input/output of data, and an ATD circuit 916 which operates in accordance with the internal signal from timing control circuit 914, and detects a transition in the internal column address signal from address buffer 902. An address transition detection signal ATD generated from ATD circuit 916 is applied to timing control circuit 914 for determining operation timings of the circuits related to the column selection.
Row address strobe signal /RAS determines a standby cycle and an active cycle of this semiconductor memory device. When row address strobe signal /RAS is activated and attains L-level, the semiconductor memory device enters the active cycle and performs the memory cell selecting operation. Column address strobe signal /CAS determines the timing for latching the column address signal and the timing for input/output of data. Write enable signal /WE designates the mode for writing/reading data. The timing of reading out data is determined by activation of column address strobe signal /CAS. The timing of data input is determined by activation of both column address strobe signal /CAS and write enable signal /WE.
ATD circuit 916 is activated at a predetermined timing after row address strobe signal /RAS is activated, and determines the operation timings of column select circuit 906 and read/write circuit 912 as well as the timing of internally reading out data at I/O buffer 910.
In the following description, the term "row-related operations" represents a series of operations staring from input of a row address to amplification of stored data in the corresponding memory cells by the sense amplifiers. The term "column-related operations" represents operations starting from input of a column address to connection of an addressed bit line pair to the internal I/O line pair and subsequent reading/writing of data from or into the memory cell. The row-related operation is driven by row address strobe signal /RAS. The column-related operation is triggered by address transition detection signal ATD. Usually, column address strobe signal /CAS drives the column-related operation. However, the address access time from application of the address signal to data reading depends on specifications, and the triggering by the address transition detection signal ATD is employed for performing operations accurately based on this access time.
FIG. 18 schematically shows a structure of a portion in memory cell array 900 and block 908 related to one column in the semiconductor memory device shown in FIG. 17. In FIG. 18, bit line pair BLP has bit lines BL and /BL which are complementary with each other. Bit line pair BLP is connected to memory cells MC on one column. FIG. 18 representatively shows a memory cell MC arranged corresponding to a crossing between one word line WL and bit line BL. Memory cell MC includes a memory cell capacitor MQ for storing information, and an access transistor MT formed of an n-channel MOS transistor which is turned on to connect memory cell capacitor MQ to corresponding bit line BL in response to a signal potential on word line WL. Memory cell capacitor MQ is supplied on one electrode node, i.e., cell plate electrode node with a cell plate voltage Vcp of a constant value equal to half the power supply voltage. Based on this cell plate voltage Vcp, positive or negative electric charges are accumulated on the other electrode node, i.e., storage node of the memory cell capacitor MQ.
For bit lines BL and /BL, there is arranged an equalize/precharge circuit 901 for equalizing bit lines BL and /BL to an intermediate voltage Vb1 in response to a bit line equalize instructing signal .phi.BQ. This bit line precharge voltage Vb1 is also at the intermediate voltage level equal to half the power supply voltage Vcc. Bit line equalize instructing signal .phi.BQ is active during the standby cycle, and is inactive during the active cycle.
Block 908 of the sense amplifiers and I/O gates includes a sense amplifier circuit 908a which is provided for each bit line pair BL and /BL, and is activated to amplify differentially potentials on bit lines BL and /BL in response to activation of sense amplifier activating signal .phi.SA, and an I/O gate circuit 908b which is turned on in accordance with column select signal CSL from column select circuit 906 (see FIG. 17), and connects bit lines BL and /BL to an internal data line pair 907a included in internal I/O bus 907. I/O gate circuit 908b includes n-channel MOS transistors provided for bit lines BL and /BL, respectively. An operation of the semiconductor memory device shown in FIGS. 17 and 18 will be described below with reference to a waveform diagram of FIG. 19.
Before time t1, row address strobe signal /RAS is at H-level and inactive, and the semiconductor memory device is in the standby cycle. In this state, bit line equalize instructing signal .phi.BQ is at H-level and inactive, so that equalize/precharge circuit 901 is activated, and bit lines BL and /BL are precharged to the intermediate level of Vb1. Word line WL is in the nonselected state and at L-level, and column select signal CSL is also in the nonselected state of L-level.
At time t1, row address strobe signal /RAS falls to L-level, so that the active cycle starts, and the memory cell select operation starts. In accordance with falling of row address strobe signal /RAS, externally applied address signal AD is taken and applied into row select circuit 904 as a row address signal X. Row select circuit 904 is activated under the control of timing control circuit 914, and drives word line WL provided corresponding to the row X corresponding to row address signal X to the selected state. In response to falling of row address strobe signal /RAS, bit line equalize instructing signal .phi.BQ is set to the inactive state of L-level, so that equalize/precharge circuit 901 is deactivated, and bit lines BL and /BL are electrically floated at precharge voltage Vb1.
When word line WL is selected to have potential raised, access transistor MT shown in FIG. 18 is turned on, and charges accumulated in memory cell capacitor MQ are transmitted onto bit line BL. FIG. 19 shows, as an example, change in potential on bit line BL in the case where memory cell MC has stored data of H-level. When a potential difference between bit lines BL and /BL sufficiently increases, sense amplifier activation signal .phi.SA is activated, and sense amplifier circuit 908a (see FIG. 18) differentially amplifies the potentials on bit lines BL and /BL. Thereby, the potential on bit line BL attains the power supply voltage Vcc level, i.e., H-level, and the potential on bit line /BL attains the ground voltage level, i.e., L-level.
In parallel with this sensing operation of the sense amplifier, the address signal is taken in as a column address signal Y in accordance with column address strobe signal /CAS, and the column select operation starts. This column select operation is actually performed after completion of the sensing operation of the sense amplifier. After the sensing operation is completed at time t2, the column select operation is performed in accordance with column address strobe signal /CAS. At time t3, column select signal CSL attains H-level or the selected state, so that I/O gate circuit 908b is turned on, and bit lines BL and /BL are connected to internal I/O line pair 907a. Internal I/O line pair 907a has been equalized by an equalize circuit (not shown), and the potentials on internal data line pair 907a are driven by sense amplifier circuit 908a to H- and L-levels, respectively. Thereafter, writing/reading of data for the selected column is performed.
Then, row address strobe signal /RAS is deactivated to attain H-level, so that the potential on word line WL lowers to L-level, and sense amplifier activating signal .phi.SA is deactivated. Then, bit line equalize instructing signal .phi.BQ attains the active state of H-level. Thereby, bit lines BL and /BL are precharged and equalized again to the intermediate voltage level, i.e., precharge voltage Vb1 level. When column address strobe signal /CAS is deactivated to attain H-level, column select signal CSL falls to L-level.
FIG. 20 schematically shows a structure including the timing control circuit, row select circuit and column select circuit in the semiconductor memory device shown in FIG. 17. In FIG. 20, word line WL, bit line pair BLP and I/O gate circuit 908b connected to bit line pair BLP are representatively shown as components in memory cell array 900.
Timing control circuit 914 includes an RAS buffer 914a which receives externally applied row address strobe signal /RAS and produces internal row address strobe signal int/RAS, an address control circuit 914b which produces signals RAL, RADE and CAI for controlling the address take-in timing in accordance with internal row address strobe signal int/RAS, a bit line equalize control circuit 914c which generates bit line equalize instructing signal .phi.BQ in accordance with internal row address strobe signal /RAS from RAS buffer 914a, a word line drive control circuit 914d which generate a word line drive signal RX determining a timing of driving of the word line to the selected state in accordance with internal row address strobe signal int/RAS, and a sense amplifier control circuit 914e which generates sense amplifier activating signal .phi.SA in accordance with internal row address strobe signal /RAS and bit line equalize instructing signal .phi.BQ generated from bit line equalize control circuit 914c.
The timing control circuit 914 further includes a column-related interlock control circuit 914f which produces column address enable signal CADE and column enable signal /CE for controlling operations of the column-related circuits. Column-related interlock control circuit 914f drives column enable signal /CE and column address enable signal CADE to the active state when a predetermined time elapses after sense amplifier activating signal .phi.SA is activated. In accordance with activation of column address enable signal /CE, the column-related circuits are enabled. In accordance with activation of column address strobe signal CADE, production of the internal column address is allowed.
Timing control circuit 914 further includes a CAS buffer 914g which receives externally applied column address strobe signal /CAS and produces a column address latch instructing signal CAL, an output control circuit 914i which produces a data transfer instructing signal DT for controlling transmission of data to an output buffer from a read circuit (preamplifier) included in a read/write circuit in accordance with write enable signal /WE and the internal column address strobe signal from CAS buffer 914g, and a column-related control circuit 914h which generates control signals for the column-related circuits in accordance with the address transition detection signal from ATD circuit 916. As the signals generated from column-related control circuit 914h, FIG. 20 shows a column decoder enable signal CDE to column decoder (column select circuit) 906a, and an equalize instructing signal IOEQ to I/O equalize circuit 920 provided to internal data line pair 907a.
Column decoder 906a is included in column select circuit 906 shown in FIG. 17. Column select circuit 906 may include a column predecoder. Column decoder 906a generates column select signal CSL to I/O gate circuit 908b. I/O equalize circuit 920 equalizes potentials on internal data line pair 907a when data line equalize instructing signal IOEQ is active.
Address buffer 902 includes a row address buffer 902r which receives the externally applied address signal and generates the internal row address signal, and a column address buffer 902c which receives the externally applied address signal and generates the internal column address signal.
Row address buffer 902r includes an address latch circuit 902ra which takes in and latches the externally applied address signal in accordance with row address latch instructing signal RAL from address control circuit 914b, and an internal address generating circuit 902rb which generates complementary internal row address signals in accordance with the internal row address signal from row address latch circuit 902ra in response to activation of row address enable signal RADE from address control circuit 914b.
The complementary internal row address signals generated from internal address generating circuit 902rb are applied to a row decoder/driver 904a included in the row select circuit. Row decoder/driver 904a decodes the address signal from internal address generating circuit 902rb, and drives the word line corresponding to the addressed row to the selected state in accordance with word line drive signal RX from word line drive control circuit 902d. Row select circuit 904 may include a row predecoder in addition to row decoder/driver 904a.
ATD circuit 916 is activated in response to activation of column enable signal /CE from column-related interlock control circuit 914f. Now, an operation of the timing control circuit shown in FIG. 20 will be described below with reference to signal waveform diagrams of FIGS. 21 and 22.
Referring to FIG. 21, description will first be given on an operation in the case where column address strobe signal /CAS is activated prior to activation of column enable signal /CE.
Before time t1, row address strobe signal /RAS and column address strobe signal /CAS are at H-level or inactive. The semiconductor memory device is in standby state. Row address latch instructing signal RAL from address control circuit 914b is inactive, and column address inhibiting signal CAI is active. In this state, row address latch circuit 902ra generates the internal address signal in accordance with the externally applied address signal. Column address buffer 902c is inhibited from taking in the externally applied address signal in accordance with activation of column address inhibiting signal CAI. I/O equalize circuit 920 equalizes internal data line pair 907a to a predetermined voltage level in accordance with activation of data line equalize instructing signal IOEQ.
When row address strobe signal /RAS falls to L-level and is activated at time t1, the active cycle starts. In response to falling of row address strobe signal /RAS, bit line equalize instructing signal .phi.BQ generated from bit line equalize control circuit 914c attains L-level, so that equalization of the bit line pair stops. In response to falling of row address strobe signal /RAS, row address latch instructing signal RAL rises to H-level, and the address latch circuit 902ra attains the latching state. Then, row address enable signal RADE is activated, and the complementary internal row address signals from internal address generating circuit 902rb attain states according to the address signal latched by address latch circuit 902ra.
When address latch circuit 902ra completes latching of the row address, column address inhibiting signal CAI is deactivated, and column address buffer 902c is enabled to take in the externally supplied address signal.
The row select operation is performed in accordance with address signal X which is taken in and latched in accordance with falling of row address strobe signal /RAS. More specifically, word line drive control circuit 914d generates word line drive signal RX at a predetermined timing, and row decoder/driver 904a drives the addressed word line to the selected state in accordance with word line drive signal RX. Then, sense amplifier activating signal .phi.SA generated from sense amplifier control circuit 914e is activated at time t2, so that sensing and amplification of data of the memory cells connected to the selected word line are performed.
At time t2 after a delay from activation of sense amplifier activating signal .phi.SA, column address strobe signal /CAS attains the active state of L-level, and correspondingly column address latch instructing signal CAL attains the active state of H-level. Thereby, column address buffer 902c latches the externally applied address signal. In this state, column enable signal /CE is still inactive, and ATD circuit 916 is also inactive. Further, column address enable signal CADE is inactive. All the internal column address signals from column address buffer 902c are inactive, so that the column select operation is not performed.
At time t3 after elapse of a predetermined time from activation of sense amplifier activating signal .phi.SA, column enable signal /CE from column-related interlock control circuit 914f attains the active state of L-level, and column address enable signal CADE also attains the active state of H-level. Although the address signal changes its level before time t2, the column enable signal /CE is kept at the inactive state of H-level, and the address transition detection signal ATD holds H-level. In accordance with activation of this column address enable signal CADE, the internal address signal from column address buffer 902c attains the state corresponding to the address signal which has already been latched. ATD circuit 916 is activated to lower the address transition detection signal ATD to L-level for application to column-related control circuit 914h in response to activation of column enable signal /CE. Column related control circuit 914h drives column decoder enable signal CDE to the active state in response to falling of address transition detection signal ATD. Responsively, column decoder 906a decodes the complementary internal column address signals from column address buffer 902c, and drives column select signal CSL to the selected state for driving the addressed column to the selected state.
At the same time, column related control circuit 914h drives internal data line equalize instructing signal IOEQ to the inactive state, so that I/O equalize circuit 920 is deactivated and stops equalizing of the internal data line. Thereby, data on bit line pair BLP is transmitted through I/O gate circuit 908b onto internal data line pair 907a, and is further transmitted to the read/write circuit, whereby data is written into or read from the selected memory cell.
At time t4, row address strobe signal /RAS rises to H-level, so that the semiconductor memory device returns to the standby state. In response to rising of row address strobe signal /RAS, row address enable signal RADE attains the inactive state of L-level, and subsequently the row address latch instructing signal RAL attains the inactive state of L-level. Thereby, the address latch circuit 902ra is set to the state for incorporating the externally applied address signal. Also, internal address generating circuit 902rb drives the internal address signal together with its complementary internal address signal to the nonselected state.
In response to rising of row address strobe signal /RAS, word line drive signal RX and sense amplifier activating signal .phi.SA are driven to the inactive state. In response to deactivation of sense amplifier activating signal .phi.SA, column address enable signal CADE and column enable signal /CE are deactivated.
In response to rising of row address strobe signal /RAS, column address inhibiting signal CAI rises to H-level, so that column address buffer 902c is inhibited from taking in the externally applied address signal. Also, column enable signal /CE is set to the inactive state of H-level, and responsively address transition detection signal ATD from ATD circuit 916 rises to H-level. Column decoder enable signal CDE is deactivated, and I/O equalize circuit 920 is activated to equalize internal data line pair 907a to a predetermined voltage level in response to activation of internal data line equalize instructing signal IOEQ.
Then, column address strobe signal /CAS rises to H-level, and column address latch instructing signal CAL attains L-level. Further, bit line equalize instructing signal .phi.BQ is set to the active state of H-level, and potentials on bit line pair BLP is precharged and equalized.
In the operation shown in FIG. 21, if column address strobe signal /CAS is activated prior to activation of column enable signal /CE, the column select operation starts in accordance with the activation of column enable signal /CE, so that the selected memory cell is accessed.
Referring to FIG. 22, description will be given on an operation in the case where column address strobe signal /CAS is set to the active state of L-level after activation of column enable signal /CE.
At time t0, row address strobe signal /RAS is set to the active state of L-level. In accordance with activation of row address strobe signal /RAS, currently applied address signal AD is taken in as row address signal (X) for performing the row select operation. In accordance with this select operation, data of the memory cells connected to the selected word line are read onto the corresponding bit lines, respectively. FIG. 22 representatively shows two bit line pairs BLP0 and BLP1. FIG. 22 specifically shows, by way of example, waveforms in such a case that data of H-level is read onto bit line pair BLP0, and data of L-level is read onto bit line pair BLP1.
In this state, column enable signal /CE and column address enable signal CADE are both inactive, and generation of the internal column address signal and column select operation are inhibited.
When the sense amplifier is activated and data signals on each bit line pair are fixed at H- and L-levels in accordance with the selected memory cell data, respectively, column address enable signal CADE and column enable signal /CE from the column related interlock control circuit shown in FIG. 20 are activated at time t1. Since row address strobe signal /RAS is in the active state of L-level and column address strobe signal /CAS is at H-level, column address buffer 902c takes in the applied address signal, and generates the complementary column address signals in accordance with column address enable signal CADE. The internal column address signal from column address buffer 902c has already changed its state, and ATD circuit 916 lowers address transition detection signal ATD to L-level in response to falling of column enable signal /CE.
In response to falling of address transition detection signal ATD, column decoder enable signal CDE is activated, and internal data line equalize instructing signal IOEQ is deactivated. Then, column decoder 906a performs the column select operation in accordance with currently applied address signal Y0. FIG. 22 shows a waveform in such a case that bit line pair BLP0 is selected in accordance with column address signal Y0, and data of H-level on bit line pair BLP0 is read.
At time t2, the address signal changes its state. Even in this state, column address strobe signal /CAS is still at H-level, and ATD circuit 916 generates address transition detection signal ATD of one shot. In response to activation (rising) of address transition detection signal ATD, column decoder enable signal CDE is set to the inactive state of L-level, and internal data line equalize instructing signal IOEQ is set to the active state at H-level. Thereby, the column select operation according to internal column address signal Y0 stops. Bit line pair BLP0 is isolated from internal data line pair 907a, and I/O equalize circuit 920 equalizes internal data line pair 907a to a predetermined voltage level.
This address transition detection signal ATD is a pulse signal of one shot having a predetermined time width. When address transition detection signal ATD falls to L-level again, column decoder enable signal CDE is activated, and internal data line equalize instructing signal IOEQ is set to the inactive state of L-level. Thereby, the operation of equalizing internal data line pair 907a is completed, and the column select operation is performed in accordance with address signal Y1. Also, bit line pair BLP1 is connected to internal data line pair 907a.
At time t3, equalizing of internal data line pair 907a is to be completed. Even if equalizing of internal data line pair 907a is not yet completed at this time t3, the sense amplifier circuit provided at bit line pair BLP1 functions to change the data on internal data line pair 907a in accordance with data of L level on bit line pair BLP1.
At time t4, column address strobe signal /CAS falls to L-level. Thereby, column address latch instructing signal CAL shown in FIG. 19 is activated, and column address buffer 902c attains the address latching state. While this state is kept, the internal column address signal does not change.
As shown in FIG. 22, column address strobe signal /CAS may be activated after activation of column enable signal /CE. In this case, column address buffer 902c is activated even if internal row address signal X of address signal AD does not change. Column address buffer 902c thus activated produces the complementary internal column address signals in accordance with the currently applied address signal, and lowers address transition detection signal ATD to L-level for column selection in accordance with activation of column enable signal /CE. When the address signal changes thereafter, address transition detection signal ATD from ATD circuit 916 is activated, so that the column select operation is performed. This operation is repeated in accordance with transition in the address signal and the column-related circuits operate until column address strobe signal /CAS is activated. Column address strobe signal /CAS functions only to provide timings for externally inputting and outputting data and a timing for latching the column address signal.
In this case, a period for equalizing internal data line pair 907a depends on a pulse width of address transition detection signal ATD. If address transition detection signal ATD has a sufficiently large pulse width, i.e., if internal data line equalize instructing signal IOEQ has a sufficiently large pulse width, the internal data line pair is reliably equalized to a predetermined voltage level. In this case, however, the column select operation starts with a delay, so that fast access cannot be achieved. Therefore, it is impossible to increase the period for equalizing the internal data line pair (the column decoder is activated after deactivation of the internal data line pair equalize signal). The column select operation described above usually occurs in the fast serial access mode such as a page mode, and it is necessary to provide a countermeasure for reliably reading memory cell data even in the case of insufficient equalizing of the internal data line pair.
FIG. 23 shows a structure of a portion including the sense amplifier circuit and I/O gate circuit. In FIG. 23, sense amplifier circuit SA (908a) includes a p-channel MOS transistor P1 which has a one conduction node connected to a sense node SNDa and a gate connected to a sense node SNDb, a p-channel MOS transistor P2 which has a one conduction node connected to sense node SNDb and a gate connected to sense node SNDa, and a p-channel MOS transistor P3 which is responsive to activation of a sense amplifier activating signal .phi.SP for transmitting power supply voltage Vcc to the other conduction node (source) of each of p-channel MOS transistors P1 and P2. Sense node SNDa is located on bit line BL, and sense node SNDb is located on bit line /BL.
Sense amplifier circuit SA further includes an n-channel MOS transistor N1 which has a one conduction node connected to sense node SNDa and a gate connected to sense node SNDb, an n-channel MOS transistor N2 which has a one conduction node connected to sense node SNDb and a gate connected to sense node SNDa, and an n-channel MOS transistor N3 which is turned on, in response to activation of sense amplifier activating signal .phi.SN, to transmit ground voltage Vss to the other conduction node terminal (source) of each of n-channel MOS transistors N1 and N2.
This sense amplifier circuit SA drives one of sense nodes SNDa and SNDb, which is at a higher potential, to power supply voltage Vcc level, and also drives the other at a lower potential to the ground voltage level.
I/O gate circuit 908b includes transfer gates Ta and Tb each formed of an n-channel MOS transistor and turned on to connect bit lines BL and /BL to internal data bus lines 907aa and 907bb, respectively in response to activation of column select signal CSLa. I/O equalize circuit 920 is provided for internal data bus lines 907aa and 907ab. I/O equalize circuit 920 includes an n-channel MOS transistor, which is turned on to electrically short-circuits internal data lines 907aa and 907ab in response to activation of internal data line equalize instructing signal IOEQ. An operation of the sense amplifier circuit and I/O gate circuit shown in FIG. 23 will be briefly described below.
In the following operation, it is assumed that, as shown in FIG. 23, the potential on bit line BL is at ground voltage Vss level, or at L-level, and bit line /BL is at power supply voltage Vcc level or at H-level. Data of H-level has been read onto internal data lines 907aa and 907ab from unillustrated another bit line pair, so that internal data lines 907aa and 907ab are at H- and L-levels, respectively. Further, a parasitic capacitance Cp is present at each of internal data lines 907aa and 907ab.
As shown in FIG. 24, data is read onto the internal data lines 907aa and 907ab from the unillustrated bit line pair, so that the potentials on internal data lines 907aa and 907ab are at H- and L-levels, respectively. When the address signal changes, internal data line equalize instructing signal IOEQ is activated to attain H-level at time ta, so that internal data lines 907aa and 907ab are electrically short-circuited, and the potentials thereon change toward the intermediate potential level. This change in potential is caused by transfer of electric charges accumulated in parasitic capacitance Cp. When internal data line equalize instructing signal IOEQ is deactivated at time tb, equalizing of internal data lines 907aa and 907ab stops. At time tb, the potentials on internal data lines 907aa and 907ab are not completely equalized, and the potential on internal data line 907aa is at a level slightly higher than that on internal data line 907ab.
In this state, column select signal CSLa is driven to the selected state at time tb, and I/O gate circuit 908b is turned on, so that bit lines BL and /BL are electrically connected to internal data lines 907aa and 907ab. Sense amplifier circuit SA holds the potentials on bit lines BL and /BL at L- and H-levels through sense nodes SNDa and SNDb, respectively. When sense nodes SNDa and SNDb are and electrically connected to internal data lines 907a and 907b rapidly in this state, the potentials on sense nodes SNDa and SNDb change. Sense amplifier circuit SA is required to drive the newly added parasitic capacitance Cp which is charged to the opposite data (data reverse in logic) potential. Therefore, the voltage level of the sense amplifier lowers from power supply voltage Vcc level, and accordingly the drive capability of the sense amplifier lowers. When the potentials on sense nodes SNDa and SNDb rapidly change due to the opposite data, sense amplifier circuit SA cannot hold the original data, and its latch state is inverted, so that the potential levels on bit lines BL and /BL change to H- and L-level, respectively, and the memory cell data is inverted.
In order to prevent inversion of the data which may be caused by this conflict or collision of data, change in potential level on sense nodes SNDa and SNDb of the sense amplifier must be relatively slow, and it is also necessary to keep a balance between the driving capabilities of transfer gates Ta and Tb included in I/O gate circuit 908b and the driving capabilities of MOS transistors P1-P3 and N1-N3 forming the sense amplifier. If the potentials on sense nodes SNDa and SNDb rapidly change as shown in FIG. 25, the latching state of the sense amplifier is inverted in accordance with this rapid potential change. Conversely, if the potentials on the sense nodes change slowly, the original latching state is held.
Therefore, even when the collision of data occurs due to insufficient equalizing of internal data lines 907aa and 907ab, it is necessary to prevent inversion of the latching state of the sense amplifier circuit. If the driving capability powers of transfer gates Ta and Tb are sufficiently reduced for reducing a speed of voltage change at sense nodes SNDa and SNDb, the potentials on sense nodes SNDa and SNDb change slowly in the data write operation, so that fast data writing is impossible. Also, internal data lines 907aa and 907ab cannot be driven fast in accordance with the voltages on sense nodes SNDa and SNDb, and fast data reading is impossible. In order to perform fast and stable writing and reading of data, extremely fine adjustment of sizes is required between MOS transistors P1-P3 and N1-N3 forming the sense amplifier circuit and transfer gates Ta and Tb.
In accordance with increase in storage capacity of the semiconductor memory device, components have been miniaturized, so that the semiconductor memory device must use a low operation power supply voltage for ensuring a reliability of components, reducing a power consumption and achieving a fast operation. This is because the power consumption is proportional to the square of the power supply voltage, and a smaller signal amplitude allows faster charging and discharging of a signal line.
However, MOS transistors which are components of processors in a system have not been miniaturized compared with semiconductor memory devices, and cannot employ the low power supply voltage which is required in the semiconductor memory device. The operation power supply voltage of the semiconductor memory device depends on the system power supply voltage required by the processors and others. Therefore, the semiconductor memory device employs an internal power supply voltage generating circuit, which internally lowers an externally supplied power supply voltage to a desired power supply voltage level for generating an internal power supply voltage. The circuit generating the internal power supply voltage in the above manner is called an internal voltage down converting circuit.
FIG. 26 schematically shows a whole structure of a semiconductor memory device having an internal voltage down converting circuit in the prior art. In FIG. 26, the semiconductor memory device includes an internal voltage down converting circuit 950 which receives an external power supply voltage extVcc and generates an array power supply voltage VccA (i.e., power supply voltage for an array), and an internal voltage down converting circuit 952 which receives external power supply voltage extVcc and generates a peripheral internal power supply voltage VccP (i.e., internal power supply voltage for peripheral circuitry). Internal voltage down converting circuit 950 supplies array internal power supply voltage VccA to an array-related circuit 954. Internal voltage down converting circuit 952 supplies peripheral internal power supply voltage VccP to peripheral circuitry 956. Array-related circuit 954 includes sense amplifiers. Peripheral circuitry 956 includes a read/write circuit, a row select circuit, a column select circuit and a timing control circuit. All the bit line amplitudes in the memory cell array are held at the voltage level of array internal power supply voltage VccA.
Peripheral internal power supply voltage VccP supplied to the peripheral circuit is at a higher level than array internal power supply voltage VccA. By using this relatively high internal power supply voltage VccP, the gate voltage of MOS transistors which are components of the peripheral circuitry is increased, and fast operation of peripheral circuitry 956 is allowed. For array-related circuit 954, the voltage level is kept at a slightly low level in order to ensure a reliability of a dielectric film of a memory cell capacitor, ensure a reliability of a gate insulating film of an access transistor and reducing a current consumption during operation of the sense amplifier.
Particularly in a dynamic semiconductor memory device, a boosted voltage VPP which is higher than array power supply voltage VccA and is nearly equal to 3.multidot.VccA/2 is applied onto the selected word line in order to write data of H-level into a memory cell capacitor without causing a voltage loss by a threshold voltage of an access transistor. For the above reason and for ensuring the reliability of the gate insulating film of the access transistor, the operation power supply voltage of array-related circuit 954 is set to a low value.
FIG. 27 schematically shows voltage levels applied to portions related to one bit line pair. In FIG. 27, memory cell MC is arranged corresponding to a crossing between word line WL and bit line BL. Memory cell MC includes memory cell capacitor MQ storing information, and access transistor MT which connects memory cell capacitor MQ to bit line BL in response to the potential on word line WL. A cell plate electrode node CP of memory cell capacitor MQ is supplied with intermediate voltage Vcp. Cell plate voltage Vcp is at at a level of half the array internal power supply voltage VccA. Although not shown, bit line equalize voltage Vb1 is at a level of half the array internal power supply voltage VccA.
Sense amplifier circuit SA is supplied with array internal power supply voltage VccA and ground voltage Vss as a sense amplifier power supply. Therefore, amplitudes of bit lines BL and /BL are between array internal power supply voltage VccA and ground voltage Vss. The voltage across the storage node SN and cell plate electrode node CP of memory cell capacitor MQ is equal to VccA/2, and therefore the capacitor dielectric film can have a sufficiently high insulation breakdown voltage.
The gate of access transistor MT is supplied with the boosted voltage of 3.multidot.VccA/2. However, array internal power supply voltage VccA is relatively low. Therefore, the gate insulating film of access transistor MT can reliably have desired insulating characteristics.
The column select circuit is supplied with peripheral internal power supply voltage VccP, and the peripheral circuits perform fast operations. In this case, column select signal CSL attains the voltage level equal to peripheral internal power supply voltage VccP when made active, and column select signal CSL at the voltage level of peripheral internal power supply voltage VccP is supplied to gates of transfer gates Ta and Tb included in I/O gate circuit 908b. In this case, the following problem arises.
FIG. 28 shows a relationship between a gate voltage and a drain current of an MOS transistor. The abscissa gives a drain-source voltage Vds, and the ordinate gives a drain current Ids. A curve I represents a relationship between the drain current and drain voltage in the case where the gate-source voltage is equal to a voltage Vgs1, and a curve II represents a relationship between the drain current and drain voltage in the case where the gate-source voltage is equal to a voltage Vgs2. Voltage Vgs1 is higher than voltage Vgs2.
As shown in FIG. 28, a higher gate-source voltage increases a drain current Ids if the drain voltage Vds with reference to the source is constant. More specifically, as the voltage level of column select signal CSL applied to gates of transfer gates Ta and Tb shown in FIG. 27 increases, the current driving capability of transfer gates Ta and Tb increases. Therefore, when column select signal CSL is driven to the selected state in such a state that internal data line pair 907a is equalized insufficiently as already described with reference to FIG. 25, internal data bus line pair 907a is rapidly connected to bit line pair BL and /BL and the potential change occurs due to the opposite data, resulting in a problem that the latched data of sense amplifier circuit SA is inverted.
In order to keep a balance between the sizes of transfer gate transistors Ta and Tb and the sizes of the MOS transistors included in sense amplifier circuit SA in such a case that column select signal CSL is driven to the level of peripheral internal power supply voltage VccP, it is necessary to adjust sizes of transfer gate transistors Ta and Tb and the MOS transistors included in sense amplifier circuit SA in accordance with the voltage level of peripheral internal power supply voltage VccP. Therefore, the relationship in sizes which has already been established cannot be utilized, and redesigning is required. In particular, the voltage levels of internal power supply voltages VccP and VccA have been gradually lowered in accordance with increase in integration density of the semiconductor memory devices, and cannot be set to a fixed value. Therefore, it is necessary to adjust the sizes of MOS transistors included in sense amplifier circuit SA and transfer gate transistors included in I/O gate circuit every time the internal power supply voltage level is changed. This requires a complicated design, and therefore increases a manufacturing cost.

Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels


The present invention provides hats with attachment assemblies allowing them to be detachably secured in an exterior-side out configuration to a belt of medium width worn around the wearer's waist, without requiring the hats to be inverted, reversed, or folded in a complex fashion, and without any need for pockets, linings, zippers or the like. The hats may also be provided with retention members for holding the hats in a simple folded configuration when carried on a belt.

Hats are a valuable defense against the sun and inclement weather. Available in a wide variety of shapes, sizes, and styles, they may shield the wearer's eyes from glare, may protect the head from excessive heat and cold, and may reduce the risk of skin cancer. However, a perennial question remains concerning how and where one is to store or carry a hat that is not currently being worn; for example, when the wearer is indoors or at nighttime. Hats are constantly lost or misplaced as a result of their owners simply forgetting where they set them down or left them, or when a hat slips onto the floor unnoticed.
U.S. Pat. No. 5,799,335 to Ethier and U.S. Pat. No. 7,257,845 to Conner disclose convertible hats that can be reassembled into handbags, shoulder bags, satchels, fanny packs or the like. However, each of these hat designs is somewhat complicated and requires that the hat be folded, collapsed, turned inside out, or otherwise inverted in a way that would not be intuitive or convenient to most users. Furthermore, although Ethier and Conner disclose embodiments in which the hat may be converted in form, for example, to a fanny pack or a self-containing bag or other container, and worn joined to an elastic cord or strap that is incorporated as part of the convertible hat for use in one or more of these other, "non-hat" forms. Furthermore, none of these convertible hats is structured and designed to be fastened to a separate, medium-width belt of the type normally worn with slacks, jeans or similar casual clothing.
U.S. Pat. No. 6,317,892 to Galigani, U.S. Pat. No. 7,036,155 to Rugg, U.S. Pat. No. 6,320,331 to Aguilar et al., and international patent application US20060048279 by Bartos, all show hats provided with hard fasteners such as clasps, clips, or rings for attachment to a belt. These rigid fasteners can be problematic, however, in that their hardness makes them uncomfortable if they rub against the user's head. They also may be somewhat costly, prone to breakage, bulky, and easily lost.
Accordingly, there is a long-felt need for hats that can easily be secured to belts of a wide variety of width in a simple and intuitive fashion, are inexpensive to manufacture, and do not require separate extra parts.


The improved image processing apparatus has a circuit for tonal and color matrix transformations of image which performs tonal transformation on image data of three primary colors and with which a 4.times.3 matrix is multiplied by a column matrix composed of the tone transformed image data so as to produce four-color image data including image data of a block color, and this circuit for tonal and color matrix transformations of image has: a lookup table in which the values of multiplication of the tone transformed image data, which have been obtained from the image data of three primary colors using nonlinear tonal transformation curves for the respective colors, by the elements of the matrix to be subjected to matrix multiplication have been written for each color in association with all of the image data of three primary colors; address signal generator which generates address signals for referencing the lookup table from the image data of three primary colors and color identification signals; and accumulator which adds the values of multiplication within the lookup table for each color as addressed by the address signal generated by the address signal generator and which repeats the addition by a predetermined number of times. The apparatus features a smaller circuit scale and is capable of precise corrections of four colors Y, M, C and K by performing independent nonlinear transformations on the respective colors.

This invention relates to an image processing apparatus for performing tonal and color matrix transforming on image signals. The apparatus may be applied to a color scanner system which reads image on an original, performs predetermined image processing steps and which thereafter produces a platemaking film. In this application, the apparatus is typically used to perform preliminary image processing steps such as color processing and sharpening on the input signal.
In the printing and platemaking fields, an image scanning, reading and reproducing system which produces a platemaking film by electrically processing the image information carried on an original has been extensively used with a view to streamlining the operational process and improving the image quality.
The system consists basically of an image reading apparatus which is an input machine and an image recording apparatus which is an output machine. The image reading apparatus uses typically a reading scanner which is transported in a sub-scanning direction such that the image information carried on the original is read by photoelectric scanning with a solid-state imaging device such as a CCD (charge coupled device) and converted to an electric signal. The image information thusly undergoing photoelectric conversion is sent to an associated image processing apparatus, where it is subjected to predetermined image processing in accordance with the preset conditions for platemaking. If the original image is a continuous tone image, its shades are subsequently reproduced by generating halftones to effect conversion to a halftone image, which in turn is supplied to the image recording apparatus where it is converted to an optical signal such as one of laser light and recorded on an image recording medium comprising a light-sensitive material such as a film. The image recording medium is processed photographically with a specified processor to produce a platemaking film for subsequent use as in printing.
The conventional image scanning, reading and reproducing system is such that image signals of three primary colors, such as red (R), green (G) and blue (B), are color processed for conversion to image signals of four colors Y, M, C and K, which are then subjected to resolution transformation, edge (sharpness) enhancement, tonal (gradation) transformation and other processing steps in that order, before they are finally delivered as output image signals Y, M, C and K to the image recording apparatus.
In order to reproduce an image having a greater degree of sharpness or three-dimensional effect, sharpeness or edge enhancement is performed on the image data. In the conventional sharpeness enhancement circuit, unsharp signal data are first constructed from the original image data. Then, the unsharp signal data is subtracted from the original image data to construct USM (UnSharp Mask) data. Finally, the original image data are added to the USM signal data times a constant, thereby constructing a sharpened image data. This procedure is repeated for individual monochromatic image data.
When original image data of three primary colors is to be sharpened in the prior art, said original image data is first converted to original image data of four colors including K (black) color in a color processing circuit which performs various steps such as 3-4 transformation, color correction and tonal transformation and then sharpening is carried out with the above-described sharpening circuit.
With a view to improving the conventional technology for sharpening color image data, the assignee of the subject application proposed in Japanese Patent Application No. 80733/1994 an image processing method and apparatus which are capable of freely changing the densities of respective colors, Y, M, C and K such that the degree of sharpness is adjustable to a desired level for the density of each color and which are capable of producing image data for reproducing image of reduced noise.
The proposed image processing apparatus is shown in FIG. 5, in which the apparatus is generally indicated by 80. As shown, the image processing apparatus 80 comprises: a tone transforming circuit 82 using a lookup table (LUT) for tonal transformation from 10-bit image data of three primary colors R, G and B to 8-bit image data of Y, M and C; a matrix computing circuit 84 in which a 4.times.3 matrix is multiplied by a column matrix composed of the tone transformed image data of three primaries, thereby effecting conversion to 8-bit image data of four colors Y, M, C and K; a color processing and transforming circuit 86 in which the 10-bit image data of three primaries are subjected to color processing steps such as 3-4 transformation, color correction and tonal transformation, thereby effecting conversion to 8-bit image data of four colors Y, M, C and K; and a sharpening circuit 92 consisting of a USM signal data constructing circuit 88 which receives the four-color image data from the matrix computing circuit 84 to construct USM signal data for each color and an adder circuit 90 which, for each color, adds the 4-color USM signal data to the 4-color image data delivered from the color processing and transforming circuit 86.
The LUT 82 stores 8-bit image data for each of the three colors Y, M and C, such as Yj (j=0-255), Mj (j=0-255) and Cj (j=0-255), that have been obtained by performing a specified procedure of tonal transformation on all of the 10-bit image data for each of the three primary colors, say, R, G and B, namely, Ri (i=0-1023), Gi (i=0-1023) and Bi (i=0-1023). For example, LUT 82 is such that the tone transformed image data that correspond to image data Ri (i=0-1023) are written at addresses (0,0)-(0,1023), data corresponding to Gi (i=0-1023) are written at addresses (1,0)-(1,1023), and data corresponding to Bi (i=0-1023) are written at addresses (2,0)-(2,1023); the LUT 82 outputs 8-bit tone transformed image data (Yj, Mj, Cj) that have been read in response to the 10-bit input image data (Ri, Gi, Bi).
In the matrix computing circuit 84 at the next stage, a 4.times.3 matrix is multiplied by a column matrix of input image data (Yin, Min, Cin) to deliver an output (Yout, Mout, Cout, Kout) in accordance with the following formula (I): ##EQU1##
A problem with the image processing apparatus 80 shown in FIG. 5 is that in order to perform tonal transformations and matrix calculations as pre-sharpening steps, tone transforming LUT 82 and matrix computing circuit 84 are respectively required and this adds to the scale of the overall circuit. As a further problem, matrix computing circuit 84 requires a number of multipliers, which adds to the cost of the circuit.
Another problem concerns the 3-4 transformation for transforming image data of three primary colors to image data of four colors. Since the first step of this process is tonal transformation from 10-bit image data to 8-bit data, image data of the fourth color, namely, K (black) color, will be subjected to matrix calculations on the basis of tone transformed image data of three primary colors such as Y, M and C and the intended matrix computation cannot be performed independently of those data of three primary colors. In other words, independent tone transformed data cannot be constructed for the fourth (i.e., black) color.

Image processing apparatus for performing tonal and color matrix transformations


A green tire includes a surface layer defining a green tire surface and made up of a plurality of windings of an unvulcanized rubber tape. A part of each of the windings is exposed on the green tire surface so that the exposed part has a width of from 50% to 80% of the width W1 of the rubber tape. Each of the windings has a substantially rhomboid cross section and has one end at an acute angle corner exposed on the green tire surface and the other end at the opposing acute angle corner. An angle theta of a diagonal line of the rhomboid drawn between the one end and the other end is not more than 30 degrees with respect to a tangential line to a profile line of the green tire surface.

1. Technical Field
The present invention relates to a green tire and a method for manufacturing a pneumatic tire, the green tire having a surface layer defining a part of the green tire surface by a rubber tape laminate circumferentially wound on the green tire.
2. Related Art
A recently proposed pneumatic tire has its various rubber members, such as tread rubber, side wall rubber, and inner liner rubber, formed of a tape laminate that is made up of an unvulcanized rubber tape circumferentially wound on the tire. The idea of winding eliminates the need for a large rubber extruder and thus enables plant equipment to be miniaturized. Also there is no troublesome work conventionally required on every occasion when there was a change in kind of the tires to be manufactured, such as nozzle replacement for the rubber extruder and adjustments. Thus, the idea of winding can be highly advantageous for tires manufactured in a wide variety of kinds but in small quantities.
However, as shown in FIG. 12, a rubber member "a" formed by winding is weak in strength even after vulcanization at an interface J between adjacent windings g of the rubber tape, so that the interface J is exposed on the surface of the rubber member "a". In the case of the rubber member "a" being, for example, a side wall rubber a1, which is largely distorted on the surface during tire deformation, an exposed point Jp of the interface J serves as a starting point of cracking, thus posing the problem of degraded tire durability.
In view of this, a technique to inhibit cracking is disclosed in, for example, Japanese unexamined Patent Application Publication No. 2005-225278. This technique decreases the number of exposed points on the tire surface by forming the side wall rubber a1 of an inner layer with larger overlapping widths of the rubber tape and a surface layer with smaller overlapping widths. However, a study conducted by the present inventors has revealed that cracking is difficult to inhibit on a sufficient level only by a decrease in the number of exposed points, especially in the case of running under the severe conditions of low internal pressure and overload.
Pneumatic tires include what is called self-supporting run-flat tires, which are known to enable the vehicle to be driven safely over some distances at relatively high speeds even when the air within the tire is greatly reduced because of puncture and the like. The run-flat tire is provided with a side reinforcing rubber substantially in the form of a crescent on the inner cavity side of the side wall portion. Recently, an attempt is being made to form the side reinforcing rubber of a tape laminate. However, even the run-flat tire is largely deformed during the run-flat occasion, which excessively distorts the inner surface (inner cavity surface) of the side reinforcing rubber. Thus, cracking on the side reinforcing rubber is difficult to inhibit on a sufficient level by the technique disclosed in the JP2005-225278 publication. Thus, there is a need for further improvement in winding.

Green tire and method for manufacturing pneumatic tire