A fluorine gas generator for generating highly pure fluorine gas in a stable and safe manner by electrolyzing an electrolytic bath 2 comprising hydrogen fluoride in the form of a molten mixed gas is provided which comprises an electrolytic cell 1 divided, by a partition wall 16, into an anode chamber 3 in which an anode is disposed and a cathode chamber 4 in which a cathode is disposed, pressure maintenance means for maintaining the anode chamber 3 and cathode chamber 4 at atmospheric pressure, and liquid level sensing means 5, 6 capable of sensing the levels of the electrolytic bath 2 in the anode chamber 3 and in the cathode chamber 4, respectively, at three or more level stages.

1. Field of the Invention
The present invention relates to an on-site type fluorine gas generator.
2. Description of the Prior Art
Fluorine gas is one of the key gases essential in the field of semiconductor production, for instance. While it is used as such in certain instances, the demand for nitrogen trifluoride gas (hereinafter referred to as "NF3 gas") and like gases synthesized based on fluorine gas and intended for use as cleaning gases or dry etching gases in semiconductor manufacturing apparatus has been rapidly increasing. Further, neon fluoride gas (hereinafter referred to as "NeF gas"), argon fluoride gas (hereinafter referred to as "ArF gas"), krypton fluoride gas (hereinafter referred to as "KrF gas") and the like are excimer laser oscillation gases used in patterning of integrated semiconductor circuits, and the raw materials thereof used in many cases are mixed gases composed of a rare gas and gaseous fluorine.
The fluorine gas or NF3 gas for use in the manufacture of semiconductors and the like is required to be highly pure with the impurity content as low as possible. On the sites of semiconductor manufacture, for instance, necessary amounts of fluorine gas are taken out of gas cylinders filled with nitrogen gas. It thus becomes very important to secure sites for storing such cylinders, store the gas safely, maintain the purity of the gas, and manage for such purposes. As for NF3 gas, for which the demand has been increasing lately, the demand tends to exceed the supply, hence there arises a problem that certain amounts of the gas should be in stock. In view of these, to have a fluorine gas generator or producer of the on-demand and on-site type at the site of use thereof is preferred to handling high-pressure fluorine gas cylinders.
Conventionally, fluorine gas is produced in a electrolytic cell such as shown in FIG. 3. The electrolytic cell body 201 is generally made of Ni, Monel, carbon steel or the like. At the bottom of the electrolytic cell body 201, a bottom plate 212 made of polytetrafluoroethylene or the like is disposed for preventing the hydrogen gas and fluorine gas generated from being mixed with each other. The electrolytic cell body 201 is filled with an electrolytic bath 202, namely a potassium fluoride-hydrogen fluoride system (hereinafter referred to as "KF-HF system") in the form of a mixed molten salt. The cell or bath is divided into an anode chamber 210 and a cathode chamber 211 by means of a skirt 209 made of Monel or the like. Upon applying a voltage between a carbon or nickel (hereinafter referred to as "Ni") anode 203 contained in the anode chamber and a Ni cathode 204 contained in the cathode chamber 211, electrolysis occurs and fluorine gas is produced. The fluorine gas generated is discharged through a product line 208, and the hydrogen gas formed on the cathode side is discharged through a hydrogen gas discharge line 207. There is a problem, however. Contamination by carbon tetrafluoride (hereinafter referred to as "CF4 gas") generated simultaneously upon electrolysis and hydrogen fluoride gas (hereinafter referred to as "HF gas") evaporating from the electrolytic bath, among others, makes it difficult to obtain highly pure fluorine gas.
For on-demand and on-site operation, automatic control of the electrolytic bath level in the electrolytic cell body 201 is indispensable to the safety in automatic operation. As regards the technology of controlling the fluctuation in electrolyte level, for instance, Laid-open Japanese Patent Application (JP Kohyo) H09-505853 corresponding to FP0728228B1, EP0852267B1, EP0965661B1 and U.S. Pat. No. 5,688,384 proposes the so-called start/stop (on/off) control. However, when electrolysis is carried out using this technology, there arises a problem. Namely, the electrolysis is interrupted upon occurrence of a certain extent of fluctuation in liquid level, and the electrolysis cannot be restarted until the electrolyte level returns to the original level.
Accordingly, it is an object of the present invention to provide a fluorine gas generator capable of generating highly pure fluorine gas stably and safely.

This patent is subject to a terminal disclaimer.


An electronic pillbox includes a plurality of compartments for storing different medications, an LCD-based user interface for interacting with a user, and a software-programmable electronic computer for controlling the administration functions of the pillbox. The pillbox may also include a battery and one or more types of alarms. Using the user interface, a user can schedule a multiple drug therapy by inputting sleeping pattern data and a dosage amount for a particular compartment. The computer automatically calculates the dosage schedule based on this information, and automatically recalculates the schedule if this information is altered by the user. A visual indicator on the user interface is illuminated when a particular medication is to be taken, and at the same time an audible and/or mechanical alarm may be activated. The combination of the visual and audible or mechanical alarms ensures that the correct medication is administered according to the programmed schedule.

The present invention is directed toward the field of portable electronic pillboxes. In particular, a compact, portable electronic pillbox is disclosed that includes special-purpose electronic circuitry and software that enables the user (i.e. patient) of the pillbox to schedule a multiple-drug therapy and also to automatically re-schedule the therapy by changing input data regarding the user's sleeping pattern.
The portable electronic pillbox disclosed herein includes a plurality of compartments for holding different medications. At the center of the pillbox is an electronic computer that allows a user to program the daily dosage of each pill (or medication) for each compartment. The user can also program the start and end times for actuating an alarm feature, wherein the start and end times are based on the user's sleep pattern. Having programmed the dosage for each compartment, and the start and end times of the user's day (i.e. the sleep pattern), the electronic computer can automatically calculate the times that the user should take a particular medication and can then notify the user when those times occur via an alarm, which can include a visual, audible and/or mechanical indicator. The electronic computer also provides numerous other features and functions, as described in more detail below, such as (i) the ability to inform the user of the next dosage time and the next dosage medications so that the user can always obtain precise information concerning the medication schedule; and (ii) the ability to automatically re-calculate the medication schedule when the user changes their sleeping pattern by responding to a change in the user-input start and end times, to name a few.
Today there are many ailments that require patients to take a multiple-drug therapy, such as high blood pressure, heart disease, kidney disease, AIDS, etc. In addition, it is very common for elderly persons to take multiple drugs for a variety of therapeutic reasons. These multiple drug therapies require that a plurality of different drugs are taken during the day, often in different dosage levels and at different times. For example, the dosage of one drug may be twice per day, while the dosage of another drug may be three times a day, etc., depending upon how many drugs are part of the multiple-drug therapy. Thus it can be very difficult for the patient, particularly if the patient is elderly, to remember when and what dosage to take for each of the plurality of medications. Non-compliance with the drug therapy as prescribed can pose serious health consequences for the patient, in the extreme case it could even cause loss of life. It is important, therefore, that patients who are taking a multiple-drug therapy are able to precisely administer their medications according to a prescribed schedule.
Presently there are known pillboxes (some electronic) that have been designed to assist patients with organizing their medications. Some of these include a plurality of compartments that are arranged, indexed and differentiated in units for use over a selected period of time. Many of these pillboxes do not have any kind of timing device to remind patients to take their medications so they do not enable patients to precisely administer their own medications. Some of these pillboxes do include electronic timers that remind the patient when to take a particular medication at a fixed time interval. However, these designs are generally not portable, and do not provide the features and functions that are necessary to intelligently administer, schedule, reschedule and provide information to the user regarding a multiple-drug therapy.
One presently known electronic pillbox is manufactured by American Medical Industries. This pillbox includes only two compartments, and also includes a timer device. Each of the two compartments can be programmed with a count-down timer. The user sets the timer to a particular time interval, and then starts the count-down by pressing a button. When the countdown timer reaches zero, an alarm sounds. The user then takes a pill and presses another button to reset the count-down timer. This design suffers from many disadvantages that make it not particularly useful for administering a multiple-drug therapy, such as: (1) it only includes two compartments, and thus it is limited to a two-drug therapy; (2) there is no "one-to-one" correspondence between the alarm and the compartment, meaning that when the alarm sounds there is no indication of what pill to take--this could obviously have disastrous consequences for the patient; (3) the user must "reset" the timer each time the alarm goes off, so if the user forgets to press the reset button, the device will not remind the user to take their next dosage, again with potentially disastrous consequences for the patient; and (4) it does not provide the intelligence to schedule, reschedule and display pertinent information to the user regarding their therapy.
Another presently known electronic pillbox is set forth in U.S. Pat. No. 5,020,037 to Raven ("Raven"). The Raven pillbox includes a timer device. The user can set nine different alarm times, e.g., at 1:00 pm, 3:00 pm, 6:00 pm, etc. When the current time measured by an internal clock matches one of the alarm times, an alarm will sound. The alarm remains on until the user opens the lid of the container, and then the alarm will go off. Each time the user opens the lid, a visual indicator is displayed on an included LCD to indicate that the pillbox has been opened. By counting the visual indicators, the user knows how many times he has taken a particular pill. This design also suffers from many disadvantages that make it not useful for administering a multiple-drug therapy, such as: (1) it does not indicate which medication the user should take; (2) it does not provide a one-to-one correspondence between the nine different alarm times and a plurality of different compartments; (3) it requires the user to count the number of times a particular medication has been taken, which could be difficult for a mentally challenged individual; (4) it is not designed to provide multiple-pill indications, i.e., there is no way to indicate that a user needs to take more than one kind of medication at any specific time; and (4) it does not provide information to the user regarding the schedule of medications to take in the next dosage cycle.
Another presently known electronic medication organizer is set forth in U.S. Pat. No. 4,626,105 to Miller ("Miller"). The Miller organizer has four compartments, and each compartment has an associated timer device that can be programmed with dosage interval and start time. Using this information, the compartment timer calculates the next dosage time and displays it to the user. Like the previously discussed systems, this device also suffers from many disadvantages that make it not useful for administering a multiple-drug therapy, such as: (1) it is not a compact, portable design and therefore cannot be taken with a user who is traveling, at work, or otherwise not at home; (2) it requires a plurality of timers that must be individually set by the user; (3) its scheduling principle is based on a fixed time interval between each dosage, so that if a user changes their sleeping pattern a dosage could be missed; and (4) it is complex, large, and would be costly to manufacture, and thus not available to lower income users.
Therefore, there remains a general need in this field for a low cost, portable, electronic pillbox that is capable of administering a multiple-drug therapy.
There remains a more particular need for such an electronic pillbox that provides a one-to-one correspondence between a plurality of medication compartments and indicators that inform the patient of which medications should be taken.
There remains still an additional need for such an electronic pillbox that is capable of dynamically rescheduling dosage times and alarms based upon a change in the user's sleeping pattern.
There remains another need for such an electronic pillbox that includes computer software intelligence that enables the user to precisely administer, schedule, reschedule and obtain information regarding the multiple-drug therapy.
There remains still another need for such an electronic pillbox that can provide numerous alarm types, such as audible, visual, and/or mechanical alarms, and which provides a correspondence between these alarms and the medications to be administered.

Electronic pillbox for administering a multiple-drug therapy


A flexible architecture for nesting joint test action group (JTAG) test access port (TAP) controllers for FPGA-based embedded system-on-chip (SoC) is provided. Advantageously, a programmable approach permits bits in a selectable bit register (302) to be selected based on the number of JTAG TAPs that will be utilized. The selected bits can be used to vary the apparent length of an instruction register (302). Importantly, the flexible architecture permits access to any combination of a plurality of JTAG TAP controllers in the FPGA-based embedded SoC without the need to rewire any I/O pins of the FPGA and/or embedded IP cores.

As chip capacity continues to significantly increase, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized chip that is designed for a particular application. Notably, an FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity of FPGAs. Importantly, FPGAs can be designed using a variety of architectures which can include user configurable input/output blocks (IOBs) and programmable/configurable logic blocks (PLBs/CLBs) having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or "plugin card." Advancement of FPGA technology has led to the development of FPGA-based system-on-chip (SoC), including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, a SoC can include all required ancillary electronics. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. FPGA-based SoCs with embedded operating systems (OSs) have further enhanced their popularity and flexibility.
FPGA-based SoCS have resulted in the proliferation of numerous consumer devices such as wireless telephones, personal digital assistants (PDAs), and digital cameras. In order for device manufacturers to develop FPGA-based SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or IP cores. An electronic file containing component information can typically be used to represent the core. A device manufacturer will generally acquire rights for one or more IP cores that are integrated to fabricate the SoC.
Notwithstanding the advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. Although a vast proportion of cores lie in the public domain, a significantly greater proportion of cores are proprietary. In order to use proprietary cores, a vast quantity of time, effort and money can be spent negotiating licensing agreements. Even after the cores are licensed, great care must be taken to properly integrate the cores prior to fabrication of the FPGA-based SoCs. Integration of the cores can include simulating, modeling and debugging the integrated cores in an operating environment. These tasks can be extremely daunting and time consuming and expensive. For example, during simulation and modeling, it can take hours if not days to simulate a few milliseconds of real time operation.
Importantly, verifying logic externally by probing the external pins has become increasingly difficult, if not impossible in certain scenarios. For example, flip-chip and ball grid array (BGA) packaging do not have exposed leads that can be physically probed using external tools such as an oscilloscope. Using traditional methods, capturing traces on devices running at system speeds in excess of 200 MHz can be challenging. Furthermore, most circuit boards are small and have multiple layers of epoxy, with lines buried deep within the epoxy layers. These lines are inaccessible using an external tool. Notably, attaching headers to sockets or SoCs to aid in debugging can have adverse effects on system timing, especially in the case of a high-speed bus. Notably, attaching headers can consume valuable printed circuit board (PCB) real estate.
Boundary-scan has been used to solve physical access problems resulting from high-density assemblies and packaging technologies used in PCB design. Boundary-scan solves physical access problems by embedding test circuitry, such as test access ports (TAPs), at chip level to debug, verify and test PCB assemblies. The institute of electronic engineers (IEEE) joint test action group (JTAG) has defined a standard, JTAG TAP also known as IEEE 1149.1, that utilizes boundary-scan for debugging and verifying PCB assemblies, such as SoCs.
FGPAs and IP cores utilized for SOC applications typically employ boundary-scan techniques by integrating one or more test access ports (TAPs), which can be used to verify and debug FPGA and embedded IP core logic. Notwithstanding the advantages of boundary-scan offered by JTAG TAP, there are inherent problems with debugging an verifying PCB assemblies that utilize multiple IP cores. For example, when multiple IP controller cores are utilized, the design arrangement of the IP controller cores can result in problems accessing each individual controller signals. Notably, such design arrangements are generally inflexible because they are hardwired and as a result, are permanent and non-programmable. Importantly, because of the non-programmability of such designs, designers have no choice but to test a hard-wired connection and subsequently re-wire the IP cores if changes are necessary. This often consumes a significant amount of development time, which translates directly into increased development cost.
The IP cores used in an SoC may have TAP controllers built into them. An SoC will generally have a TAP controller of its own. It would be desirable to have multiple TAPs on an SoC connected together so that they may be accessed simultaneously for test, debug, and other purposes. One method of connecting the TAPs together is to connect their Instruction Registers (IRs) in series in accordance with the present invention. This effectively creates a single, longer, IR. On a PLD, the connections between various IP blocks may be made through programmable interconnections. These interconnections are made by programming SRAM cells or other means. The interconnections do not exist prior to programming or configuration of the PLD. This leads to the problem that the IR will have one length prior to programming the PLD and a longer length afterward. Since it is required by the IEEE 1149.1 standard that the length of the Instruction Register (IR) of a TAP controller be fixed, this presents a problem.
One method of fixing this problem in accordance with the present invention is to have a selectable length shift register in the PLD TAP controller that can be placed in series with the PLD IR prior to programming. A multiplexer or other logic can be used to select between the output of the selectable shift register and the output of the IP core's IR. This selection can be made by a programmable SRAM cell as previously mentioned.
Given these inflexibilities and other inherent drawbacks, there is a need for a method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC).

Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)


Wire fencing having a plurality of elongate picket members that lie adjacent to a side face of the chain link fencing so as to be substantially superposed over the fencing. Engagement members extend from the back faces of the picket members to project into the fencing and engage respective mounting members positioned within the fencing or on the opposite side face of the fencing. The interengagement of the engagement members and the mounting members holds the picket members firmly in place on the side of the fencing.

Field of the Invention
The present invention relates to wire fences, such as chain link fencing, which have a plurality of decorative, elongate slats that also provide privacy by blocking the view through the fence. Heretofore, the slats have generally been woven through the links of the chain link fabric of the fence. More particularly, the present invention relates to improved means for arranging decorative slats in the form of decorative pickets on the side of wire fences, including chain link fences, so as to essentially block visual observation through the fence, i.e., providing essentially complete privacy. Further, the present invention relates to an improved means for locking and retaining adjacent slats in a uniform position along the fence, wherein the locking means provides interlocking engagement between the slats and the wire fencing.

Wire fencing with decorative slats that provide essentially complete privacy


According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

1. Field
Example embodiments relate to field effect transistors including graphene, and more particularly, to field effect transistors including graphene as channel layers.
2. Description of the Related Art
Currently, carbon-based materials including fullerene, carbon nanotube, diamond, graphite, and graphene are being researched in various fields.
From among those materials, carbon nanotube has been in the limelight since the 1990s. However, recently, some attention has been focused on graphene. Graphene may have a plate-like structure. Graphene is a thin-film in which carbon atoms are 2-dimensionally arranged. Since charges in graphene may function as zero effective mass particles, graphene may have very high electric conductivity, high heat conductivity, and high elasticity.
Various research has characterized some properties of graphene and/or studied applications of graphene to various fields. Particularly, Novoselov and Geim have fabricated graphene having a hexagonal structure, in which carbon atoms are 2-dimensionally arranged, by mechanically peeling off graphene, fabricated a transistor using the same, and have reported field effect property of graphene. In other words, a transistor using graphene features linear increase of conductivity according to gate voltages.

Seoul National University R&DB Foundation


A rotating separator has a housing preventing separated liquid carryover. A plenum between the annular rotating separating filter element and the housing sidewall has one or more flow path separating guides minimizing the flow of separated liquid to the outlet. The flow path guides may include one or more fins and/or swirl flow dampers and/or a configured surface.

Parent Applications
The noted parent '742 and '755 applications relate to internal combustion engine crankcase ventilation separators, particularly coalescers. Internal combustion engine crankcase ventilation separators are known in the prior art. One type of separator uses inertial impaction air-oil separation for removing oil particles from the crankcase blowby gas or aerosol by accelerating the blowby gas stream to high velocities through nozzles or orifices and directing same against an impactor, causing a sharp directional change effecting the oil separation. Another type of separator uses coalescence in a coalescing filter for removing oil droplets. The inventions of the parent '742 and '755 applications arose during continuing development efforts in the latter noted air-oil separation technology, namely removal of oil from the crankcase blowby gas stream by coalescence using a coalescing filter.
Present Application
The present disclosure arose during continuing development efforts in separating liquid from a fluid mixture, including the above noted technology, and including a rotating separator separating liquid from a fluid mixture, including air-oil and other liquid-fluid mixtures.
In one embodiment, the present disclosure provides a housing for an annular rotating separating filter element, which housing prevents separated liquid carryover.

Rotating separator with housing preventing separated liquid carryover


A soldering apparatus including a vessel containing a molten solder, a casing defining therewithin a soldering chamber in which a flat overflowing wave of the molten solder is formed, a conveyor physically integrated with the casing for movement therewith and operable for transferring a printed circuit board through the soldering chamber, actuators and for vertically moving the casing, inert gas feeders for feeding an inert gas to the soldering chamber, and a controller for controlling the operation of the actuators and, so that the printed circuit board is contacted with the surface of the flat overflowing wave in an atmosphere of the inert gas during its passage through the soldering chamber.

As methods for soldering a printed circuit board having electronic parts such as leads and terminals mounted thereon, various methods, such as a flat dip method, a dual pot method, a flow method, a wave method, a double wave method, a flow-dip method and a cascade method, are known for supplying a molten solder onto the electronic parts to be soldered and the soldering lands, that is, the regions to be soldered on the printed circuit board.
Such soldering methods are described in "Denshi Gijutsu, extra edition of the June 1981 issue (Vol. 23, No. 7, 1981)" (Document 1). In Document 1, the flow-dip method is explained to have features of both of the flow or wave method and dip method. That is, in the flow-dip method, a molten solder in a solder vessel is caused to overflow by a pump to form an overflowing wave as in the flow or wave method, and a printed circuit board is transferred and dipped in the overflowing wave to carry out soldering as in the dip method.
As described in Document 1, the flow-dip method is useful for soldering parts with long leads, because the temperature of the molten solder is stable and does not drop when the printed circuit board is brought into contact with a surface of the molten solder, and because the surface of the molten solder can be always kept clean and the surface of the overflowing wave is stable. Another reason is that even long leads of the parts do not have the possibility of contacting the edges of the discharge opening from which the molten solder overflows.
U.S. Pat. No. 4,512,510 (Document 2) discloses a method for improving the quality of soldering by the flow-dip method. In this method, when a printed circuit board is brought into contact with a surface of a molten solder, the printed circuit board is tilted so that the printed circuit board can be gradually brought into contact with the molten solder from one end to the other to permit a gas between the printed circuit board and the surface of the molten solder to escape. The printed circuit board is then moved along the surface of the molten solder to apply a kinetic pressure from the molten solder to the regions to be soldered so that the regions to be soldered can be fully wetted with the molten solder. Finally, the printed circuit board is gradually separated from the surface of the molten solder from one end to the other so that an appropriate amount of solder can remain on each region to be soldered by a peel back effect and a solder bridge cannot be formed between adjacent regions to be soldered.
Japanese Unexamined Patent Publication No. H6-198486 (Document 3) discloses a soldering method in which soldering is carried out in an atmosphere of a non-oxidizing inert gas such as nitrogen gas. In an inert gas atmosphere with a low oxygen concentration, because oxidation of the regions to be soldered can be prevented. Further, because the surface tension of the molten solder is decreased and, therefore, the wettability of the regions to be soldered to the molten solder is significantly improved, the molten solder can be supplied onto minute regions to be soldered so easily that what is called micro-soldering can be carried out. Additionally, since the amount of flux to be applied on the regions to be soldered can be significantly reduced, there is no need for washing of the printed circuit board (removal of residual flux) after soldering.
The method disclosed in Document 3 is exclusively applied to a flow method, a wave method, a double wave method or a cascade method in which the printed circuit board is transferred only linearly, since a conveyor can be easily installed in a chamber maintained in an inert gas atmosphere. Therefore, there has been no soldering apparatus employing a flow-dip method in which soldering is carried out in an inert gas atmosphere, since a complicated transfer means is required to transfer the printed circuit board not only horizontally but also vertically.
More specifically, in order to provide a complicated transfer means as described in Document 3 in a chamber maintained in an inert gas atmosphere, the chamber must have an extremely large volume. Thus, the inert gas feed rate must be significantly large to achieve an intended low oxygen concentration (1000 ppm, for example).
Even if a soldering apparatus having such a transfer means provided outside a chamber maintained in an inert gas atmosphere is realized, the chamber will have a large capacity to permit the printed circuit board to move up and down and, further, outside air will enter the chamber from where a part of the transfer means extends into the chamber. Therefore, the inert gas feed rate must be significantly large to maintain an intended oxygen concentration. A large inert gas feed rate leads to an increase in the cost of soldering.
In addition, soldering of a printed circuit board having parts with long leads mounted thereon, that is, a printed circuit board having a surface to be brought into contact with molten solder (a surface to be soldered) from which long leads protrudes cannot be carried out by the apparatus disclosed in Document 3. Soldering of such a printed circuit board cannot be carried out by a method other than a dip or flow-dip method. However, there is no soldering apparatus employing a flow-dip method which can carry out soldering in an inert gas atmosphere with a low oxygen concentration at a low cost for the same reason as described above.
When electronic parts with long leads such as connectors are soldered onto a printed circuit board which has been once subjected to reflow soldering, partial soldering is carried out by a flow-dip method using a mask plate having openings at positions corresponding to the regions to be soldered (see FIG. 5(b)). However, there is no soldering apparatus which can carry out soldering by a flow-dip method in an inert gas atmosphere with a low oxygen concentration for the same reason as described above. The soldering is carried out by a soldering iron robot while blowing nitrogen gas onto the regions to be soldered. Therefore, the soldering of such connectors yields low productivity.
British Patent No. 801510 (Document 4) discloses what is called a Sylvania system, in which solder is pumped continuously to a plurality of upwardly extending tubes and ejected therefrom. An article to be soldered is moved into position to touch the solder ejected from selected numbers of the tubes so that selected regions on the article are soldered.
The Sylvania method disclosed in Document 4 has the following drawbacks.
(1) The mechanism of the system is so complicated that adjustment of the mechanism or recovery from a failure takes a significant amount of time, resulting in low productivity.
(2) Since different types of tubes must be used for different types of printed circuit boards to be soldered and it takes long time (about 60 minutes) to exchange the tubes. Thus, the downtime of the soldering apparatus is long, resulting in low productivity.
(3) Since there are many tubes, it takes long time (about 30 minutes, for example) to clean the tubes, resulting in low productivity.
(4) The tubes are very expensive (about one million yen per one tube, for example).
(5) It is difficult to perform the soldering in an inert gas atmosphere in a simple manner.


A home appliance includes a tactile signal generator and a controller. The tactile signal generator has a first function which allows the home appliance to perform a predetermined function and a second function to generate a tactile signal. The controller determines whether an event is generated and controls the generation of the tactile signal generated by the tactile signal generator upon determination that the event is generated.

1. Field
Embodiments of the present disclosure relate to home appliances to notify a user of generation of an event using a tactile signal.
2. Description of the Related Art
In general, home appliances send feedback regarding generation of an event to a user using audio signals, visual signals, and the like. In order to notify the user of the event, home appliances need to include an additional component.
For example, a washing machine that is a machine used to wash laundry using electric power includes a tub to contain wash water, a rotary tub rotatably installed in the tub, a drive device to rotate the rotary tub, a water supply device to supply water to the tub, and a drain pump to forcibly discharge the wash water from the tub.
A variety of events may be generated in a washing machine while washing laundry. In general, a user is notified of generation of an event via a speaker or a display mounted in the washing machine.
Meanwhile, a drain pump generally includes a pump case, which includes a wash water inlet chamber to contain wash water and a drain pump chamber, and a pumping motor installed at one side of the pump case. A pump filter to remove foreign matters contained in the wash water is installed in the pump case, and an impeller rotatably driven by the pumping motor is installed in the drain pump chamber. When the drain pump is driven, vibration generally occurs.

Home appliance and controlling method thereof


In accordance with one embodiment, an image forming apparatus comprises a heating member configured to heat a recording medium, on the surface of which a toner image is carried, to fix the toner on the recording medium; a pressing member configured to contact with the recording paper from the back side of the recording paper; an induction heating section configured to heat the heating member through induction heating; a temperature sensor configured to detect the temperature nearby the heating member; a driving control section configured to carry out a control based on the temperature detected by the temperature sensor so that the temperature of the heating member based on the induction heating section is within an allowable temperature range; a temperature range setting section configured to set the allowable temperature range so that the allowable temperature range is narrowed as time elapses from the start of a fixing processing.

An image forming apparatus generally forms a latent image on a photoconductive drum, develops and visualizes the latent image with toner, and then transfers the visualized toner image to a recording paper and fixes the visualized toner image on the recording paper by heating. Heating is needed on the fixing process, and a fixing device which heats and fixes an image through induction heating is known.
The heating temperature control in the fixing device is important, and in the induction heating, generally, the power supplied for an IH coil is controlled to control the heating temperature. However, if the temperature is set to a given value, the frequency of changing power is increased and the temperature ripple is increased. When the temperature is low, an image defect is caused and a stable fixing processing cannot be carried out due to the low temperature offset and the like. Thus, it is necessary to maintain the heating temperature in a constant width and reduce the temperature ripple.
However, in most cases, the fixing condition changes due to the temperature in the image forming apparatus even if the heating temperature is maintained in a constant width, which leads to an unstable fixation.
Thus, the purpose of the present invention is to provide an image forming apparatus capable of carrying out a stable fixing processing constantly.


A system and to prevent data corruption due to split brain in shared data clusters includes two or more nodes of a cluster, a shared storage device, and an update manager. The update manager may be configured to maintain a local persistent store corresponding to each node of the cluster. On receiving an update request directed to the shared storage device from a first node, the update manager may be configured to redirect the update to the local persistent store corresponding to the first node. The update manager may be further configured to verify a cluster membership status of the first node, and to transfer the contents of the update from the local persistent store to the shared storage device if the cluster membership verification succeeds.

1. Field of the Invention
This invention relates to computer systems and, more particularly, to management and data integrity maintenance of clustered computer systems.
2. Description of the Related Art
Many business organizations and governmental entities rely upon complex mission-critical applications that require substantial computing power and also often access large amounts (e.g., terabytes or more) of data. The amount of computing power required may exceed the capacity of single computer servers, even in environments where multiprocessor servers are employed. Similarly, the amount of data being handled by the applications may exceed the limits of local storage capabilities of single computer servers. As a result, in many such environments, computer servers may be organized as one or more clusters of multiple cooperating nodes, where each node of a given cluster includes a computer server, and where the nodes of a cluster cooperate with each other to perform the data accesses and computations desired. In addition to providing aggregate increased computing and data processing power, clusters may also be configured to support other features desired in enterprise computing environments, such as increased application availability (e.g., using failover mechanisms) and centralized management.
A number of different types of cluster architectures may be implemented, based for example on application needs such as the expected type of computing and storage access patterns, the desired levels of availability, the nature of coupling (e.g., tight vs. loose coupling) or synchronization between different nodes, or on other factors. In general, components of clustering software are run on each node of a cluster to help coordinate the operations of the nodes and to manage cluster configuration. In one cluster organization, called "shared data clustering", the nodes of a cluster (each of which may correspond to a separate physical server and/or to an instance of a distributed or clustered application) share access to data storage devices, such as disk arrays or collections of independent disks. For example, the shared data storage devices may be accessible to each node of a cluster over a Storage Area Network (SAN) implemented using a combination of Fibre Channel and other storage interconnects such as various forms of SCSI. Shared data clustering may allow each node to access large amounts of data, and may allow data access and processing to continue in the event of one or more node failures—for example, surviving nodes may take up the functions originally performed by the failed nodes, and may access the data previously being accessed by the failed nodes. In general, the servers comprising a shared data cluster, as well as the collection of shared data storage devices, may be heterogeneous. For example, nodes may differ from one another in number of processors, processing power of each processor, processor architectures or vendors, operating systems, etc., and shared storage devices may differ from each other in storage capacity, vendor, protocols supported, reliability and performance levels, etc.
During normal operation, clustering software at a given node of a shared data cluster may be configured to communicate with clustering software at other nodes over a cluster interconnect. A component of the clustering software, which may be termed a cluster monitor in some environments, may be responsible for maintaining cluster membership information and propagating the information to each node, so that each node retains a consistent view of the set of nodes constituting the cluster. In the event of a failure of communication between the nodes of a cluster, for example due to a hardware failure in the interconnect and/or due to a software error, a cluster may become partitioned—that is, instead of all the nodes being able to communicate with each other, each node may only be able to communicate with a particular subset (or none) of the other nodes. Thus, nodes may form isolated pools, where a given node can communicate only with other nodes in its own pool, but not with a node in any other pool. Under some circumstances, more than one cluster partition or node may assume that it is the only surviving valid partition or node, and may attempt to access shared data as though no other node or partitions remained operational. Such a situation, in which multiple nodes or sets of nodes form independent clusters, may be termed a "split-brain" condition.
In a split-brain environment, more than one partition or node may attempt to access and update shared storage in an uncoordinated manner, thereby potentially causing data corruption. A number of solutions to avoiding data corruption as a result of split-brain have been attempted, such as quorum-disk based protocols and/or reservation-based protocols (e.g., using SCSI-3 persistent reservation mechanisms, based on a particular version of the Small Computer System Interface (SCSI) protocol). Reservation-based protocols may require each shared storage device to support an identical version of a storage protocol, which may not be a practical requirement in many heterogeneous storage environments. In quorum-disk protocols, a particular disk in the storage network may be designated as the quorum disk. Each node in the cluster may be given one vote in determining a quorum, while the quorum disk (or the node containing the quorum disk) may be given a higher number of votes (for example, as high as (N−1) votes if the cluster is expected to include a maximum of N nodes). The partition that has the maximum number of votes is considered to form a quorum and is allowed to continue to support the applications originally running on the cluster, while remaining partitions may be considered invalid (e.g., the nodes of the remaining partitions may be restarted in some cases). Quorum-disk based protocols may be too strict for small clusters, and are often prone to transient connectivity failures. It is possible for the storage devices to end up being partitioned between the pools as well. In cases of host-based mirroring and other data redundancy solutions, this can result in potential data corruption, for example if different mirrors of a mirrored data storage volume end up in different pools and their data are modified in mutually incompatible ways.

System and method to prevent data corruption due to split brain in shared data clusters


An apparatus and method for Transmit Diversity mode transition in a mobile communication system for use with transmit diversity is disclosed. In a mobile communication system including a Node B comprising one or more antennas and a Mobile Station (MS) for transmitting Transmit Diversity information to the Node B to enable the plurality of antennas to implement the maximum Transmit Diversity. The apparatus and method for assigning weights to transmission data of the antennas to enable the Node B to implement the maximum Transmit Diversity when the mode transition occurs in the Transmit Diversity modes comprise determining whether the mode transition occurs using the Transmit Diversity information; and assigning a weight generated considering the relationship between a current weight and a previous weight used before the mode transition time to the data transmitted over the antennas if it is determined that the mode transition occurs.

1. Field of the Invention
The present invention relates to a mobile communication system. More particularly, the present invention relates to an apparatus and method for adapting different weights according to change in a Transmit (Tx) Diversity scheme when a Node B transmits data using a Tx Diversity scheme.
2. Description of the Related Art
As mobile telecommunication systems have been developing and the amount of data transmitted on such systems has been increasing, a third generation mobile telecommunication system providing data at a higher speed has recently been developed. As for the third generation mobile telecommunication system, a Wideband-Code Division Multiple Access (W-CDMA) format which is asynchronous has been widely used in Europe as a wireless access standard, and a Code Division Multiple Access-2000 (CDMA-2000) format which is synchronous has been widely used in North America as a wireless access standard. Typically, the mobile telecommunication system enables a plurality of User Equipments (UE's) to communicate via one Node B. However, phase distortion of a reception signal occurs in the mobile telecommunication system resulting in a fading phenomenon during transmission of high-speed data. The fading phenomenon causes an amplitude of a reception signal to be reduced from several tens of dBs to a few dBs. Therefore, if the distorted phase of the reception signal is not compensated for during a data demodulation process, an undesired information error occurs in the transmission data from a transmission end such that a Quality Of Service (QoS) of the mobile telecommunication system deteriorates. In order to transmit high-speed data without QoS deterioration, the fading phenomenon must be addressed. A variety of diversity schemes have been widely used to overcome the fading phenomenon.
Typically, a CDMA scheme uses a rake receiver for performing diversity reception using a delay spread of a channel signal. A general rake receiver uses a Receive (Rx) Diversity scheme for receiving a multi-path signal, and each finger of the rake receiver is assigned one signal path such that it performs a demodulation process. However, the above rake receiver based on a diversity scheme using the delay spread is inactive when a value of the delay spread is lower than a prescribed value. Also, a Time Diversity scheme using an interleaving operation and a coding operation is typically used for a Doppler spread channel. However, it is difficult to use the Time Diversity scheme in a low-speed Doppler spread channel.
Therefore, in order to solve the fading phenomenon, a Space Diversity scheme has been used for both a channel having a low delay spread, such as an indoor channel, and a channel having a low-speed Doppler spread, such as a walker channel. The Space Diversity scheme is indicative of a diversity scheme for use with at least two transmission and reception antennas. Specifically, if the magnitude of a signal transmitted via one antenna is reduced by the fading phenomenon, the Space Diversity scheme demodulates a transmission signal by receiving signals transmitted via the remaining antennas. The Space Diversity scheme is classified into a Receive Antenna Diversity scheme using a reception antenna and a Transmit Antenna Diversity scheme using a transmission antenna. However, because the Receive Antenna Diversity scheme is used for UEs, it is difficult to install a plurality of antennas for each UE due to the size and cost of each UE. Therefore, the Transmit Antenna Diversity scheme for installing many antennas to a Node B is preferably used.
The Transmit Diversity scheme controls a transmission end to transmit signals over multiple antennas, and controls a reception end to receive, demodulate, and combine output signals of individual antennas to overcome fading channels. The W-CDMA implements the Transmit Diversity scheme by adapting two antennas to the Node B according to specified communication standards.
The Transmit Antenna Diversity scheme uses a specific algorithm for receiving a downlink signal to obtain a diversity gain, and is classified into an open loop transmit diversity and a closed loop transmit diversity. The open loop transmit diversity is classified into a Time-Switched Transmit Diversity (TSTD), and a Space-Time Transmit Diversity (STTD), and the closed loop transmit diversity includes a Transmit Antenna Array (TxAA) scheme.
For the open loop transmit diversity, if a Node B encodes information bits and transmits them via a plurality of diversity antennas, the UE receives signals transmitted from the Node B and decodes the received signals such that a diversity gain is obtained.
For the closed loop transmit diversity, if the UE estimates and calculates channel environments through which signals transmitted via transmission antennas of a Node B will travel in the future, calculates weights of the antennas of the Node B on the basis of the calculated estimation values in order to obtain a maximal power value of a reception signal, and finally transmits the weights to the Node B via an uplink, the Node B receives the weights from the UE and applies each of the weights to each antenna, thereby adapting received weights to individual antennas. In this case, the Node B transmits a pilot signal for every antenna to measure a channel of the UE, and thereby the UE measures a channel using the pilot signal for every antenna and generates an optimal weight based on the measured channel information.
The closed loop transmit diversity method will hereinafter be described with reference to FIG. 1. FIG. 1 is a block diagram illustrating a TxAA-scheme transmitter indicative of a representative technique of the closed loop transmit diversity scheme.
A Dedicated Physical Control CHannel (DPCCH) for transmitting a plurality of control signals and a Dedicated Physical Data CHannel (DPDCH) for transmitting information signals are multiplexed to configure a Dedicated Physical CHannel (DPCH) 102. In this case, the DPCCH and the DPDCH are typically time-multiplexed in a downlink direction.
The multiplier 104 scrambles the DPCH signal using a scrambling code. The scrambled DPCH signal is multiplied by a predetermined weight W1 in the multiplier 106, and is multiplied by a predetermined weight W2 in the multiplier 108, such that the closed loop transmit diversity is applied to the scrambled DPCH signal. Separate calculation signals are transmitted over a first antenna 114 and a second antenna 116.
The closed loop transmit diversity scheme is classified into a first mode scheme and a second mode scheme according to weight use methods. Specifically, the first mode scheme (Mode 1) determines a weight by considering only a phase difference between signals received over the two antennas 114 and 116, and the second mode scheme (Mode 2) determines a weight by considering the phase difference and the magnitude difference between signals received over the two antennas 114 and 116.
Signals transmitted to the first and second antennas are multiplexed with unique pilot signals CPICH1 and CPICH2 assigned to every antenna in individual multiplexers 110 and 112, respectively, such that the state information of channel signals transmitted over individual antennas can be measured.
The Mobile Station (MS) receives signals from individual antennas, measures channel states of individual antennas using the pilot signals, and multiplies weights by pilot signals of two antennas, such that it determines a specific weight for maximizing a power level of a reception signal indicative of the sum of the multiplied results in association with individual antennas. Information of the weight is defined as predetermined sets. If the weight from among three available weights is adapted to a reception end, the reception end determines one weight for maximizing a necessary reception power. If information of the determined weight is transmitted over the feedback information (FBI) field of an uplink DPCCH message, the FBI message determination unit 118 analyzes the feedback information received from the reception end. The weight generator 120 generates weights W1 and W2 for every antenna, and multiplies the weights W1 and W2 by a DPCH signal to be transmitted.
The uplink DPCCH configuration and the FBI configuration will hereinafter be described with reference to FIGS. 2 and 3. FIG. 2 is a view illustrating a configuration of the uplink DPCCH. One frame of the uplink DPCCH comprises 15 slots, and each slot includes a pilot symbol, a Transmit Format Combination Indicator (TFCI) bit, a feedback information (FBI) symbol, and a downlink Transmit Power Control Commander (TPC). The pilot symbol is used as a channel estimation signal when data transmitted from the MS to the Node B is demodulated. The TFCI bit indicates which one of the Transport Format Combinations (TFCs) is applied to a downlink channel transmitted during a current transmission frame. The FBI symbol transmits feedback information according to the used Transmit Diversity scheme, and the TPC symbol is a symbol for controlling Downlink Channel Transmit Power. The uplink DPCCH is spread using an orthogonal code, and is transmitted to a destination. In this case, a Spreading Factor (SF)is fixed at a specific number, for example, 256.
FIG. 3 illustrates a configuration of an FBI symbol included in the uplink DPCCH. The FBI symbol is classified into an S field and a D field. The S field is indicative of a field for the STTD signal, and the D field is indicative of a field for the closed loop transmit diversity. Therefore, the MS transmits weight information over the D field of the uplink DPCCH's FBI symbol. The D field includes a maximum of 1 bit for every slot.
A channel for use in the W-CDMA communication system is mainly classified into a Physical Channel, a Transport Channel, and a Logical Channel according to signal processing of hierarchical information. The physical channel for spatially transmitting data is classified into a downlink physical channel and an uplink physical channel according to information transmission directions.
The Transmit Diversity scheme for use in individual physical channels is shown in the following Table 1:
TABLE 1Open loop TransmitClosed loop TransmitDiversityDiversityPhysical Channel TypeTSTDSTTDMode 1Mode 2P-CCPCHX◯XXSCH◯XXXS-CCPCHX◯XXDPCHX◯◯◯PICHX◯XXPDSCHX◯◯◯HS-PDSCHX◯◯XHS-SCCHX◯◯XAICHX◯XXCSICHX◯XXAP-AICHX◯XXCD/CA-ICHX◯XXDL-DPCCH for CPCHX◯◯◯
In this case, the principles for adapting the Transmit Diversity scheme to the physical channels will hereinafter be described.
1) According to the first principle, the STTD scheme and the closed loop transmit diversity scheme cannot be applied to the same physical channel at the same time.
2) According to the second principle, when adapting the Transmit Diversity scheme to one of downlinks, the Transmit Diversity scheme must be applied to the P-CCPCH and the SCH.
3) According to the third principle, a PDSCH and its associated DPCH must use the same Transmit Diversity scheme at all times.
4) According to the fourth principle, the HS-SCCH, the HS-PDSCH, and their associated DPCH must use the same Transmit Diversity scheme.
The UMTS system based on the W-CDMA scheme must combine DPCH signals transmitted from several Node Bs at a soft handover time. The Node Bs for transmitting the DPCH signals to be received at the same time must satisfy the following regulations associated with Transmit Diversity scheme usage according to prescribed standards.
1) According to the first regulation, the Node Bs use one Transmit Diversity scheme when transmitting a DPCH signal to a desired UE. Specifically, the Node Bs avoid duplication of the open loop transmit diversity scheme and the closed loop transmit diversity scheme.
2) According to the second regulation, if all the Node Bs currently providing UEs with necessary services do not use the Transmit Diversity scheme, a recently added Node B for DPCH transmission is not affected by conventional Node Bs in association with specific information indicative of a used or unused Transmit Diversity scheme.
3) According to the third regulation, if one or more Node Bs from among a plurality of Node Bs currently providing UEs with necessary services transmit the DPCH using the open loop transmit diversity scheme, the recently added Node B can transmit the DPCH using the open loop transmit diversity scheme or can also transmit the DPCH without using the transmit diversity scheme.
4) According to the fourth regulation, if one or more Node Bs from among a plurality of Node Bs currently providing UEs with necessary services transmit the DPCH using the closed loop transmit diversity Mode1 scheme, the recently added Node B can transmit the DPCH using the closed loop transmit diversity Mode1 scheme or can also transmit the DPCH without using the transmit diversity scheme.
5) According to the fifth regulation, if one or more Node Bs from among a plurality of Node Bs currently providing UEs with necessary services transmit the DPCH using the closed loop transmit diversity Mode2 scheme, the recently added Node B can transmit the DPCH using the closed loop transmit diversity Mode2 scheme or can also transmit the DPCH without using the transmit diversity scheme.
Upon receiving downlink DPCH signals from more than two Node Bs at a soft handover time, individual Node Bs are not affected by specific information indicating whether the Transmit Diversity scheme is adapted to the Node Bs. When using the Transmit Diversity scheme, the closed loop transmit diversity scheme and the open loop transmit diversity scheme cannot be used at the same time. In the case of using the closed loop transmit diversity scheme, the aforementioned Mode1 and Mode2 schemes cannot be used at the same time. A plurality of Node Bs for providing UEs with necessary services must select one scheme from among a plurality of Transmit Diversity schemes, and must use only the selected scheme.
A method for controlling the MS to generate weights will hereinafter be described. The MS performs channel estimation using the CPICH, and this channel estimation value configured in the form of a matrix H can be represented by the following equation 1:H=[h1, h2]
With reference to Equation 1, h1 and h2 are channel estimation vectors for two transmission antennas, respectively. The MS selects weights w1 and w2 capable of maximizing the result value of the following equation 2 using the channel estimation vectors.P=wHHHHw
With reference to Equation 2, w is [w1, w2]T, and P is indicative of reception power when weight information is adapted to the first and second antennas in current channel environments. The MS searches for a weight for maximizing the reception power, and transmits the weight to the Node B.
FIG. 4 is a configuration of a Feedback Signal Message (FSM) transmitted from the MS to the Node B to establish the closed loop transmit diversity scheme. The FSM configuration is transmitted over the D field contained in the FBI field shown in FIG. 3. The FSM is classified into an FSMph field indicative of phase information and an FSMpo field indicative of magnitude information.
If the MS performs a handover function as described above, a Transmit Diversity scheme for use in the former Node B before performing the handover function may be different from the other Transmit Diversity scheme for use in the latter Node B after performing the handover function. Provided that the Transmit Diversity scheme of the former Node B is equal to that of the latter Node B, the MS need not change the Transmit Diversity scheme. Otherwise, provided that the Transmit Diversity scheme of the former Node B is different from that of the latter Node B, the MS must change the Transmit Diversity scheme according to handover situations.
If the MS changes the Transmit Diversity scheme, and particularly, if there arises a variation in mode of the closed loop transmit diversity scheme, the MS must establish an initial weight at a time of changing the mode to another mode. The Node B must receive weight information capable of maximizing reception power in the MS, and transmit data using the received weight information. However, as shown in FIG. 4, the weight information comprises 2 bits when the closed loop transmit diversity scheme is set to Mode1, comprises 4 bits when the Transmit Diversity scheme is set to Mode2, and one bit is transmitted over one slot. The Node Bs take a predetermined time to receive all of the weight information transmitted from the MS in such a way that they can receive appropriate weights from the MS. Therefore, the Node B must transmit data to be transmitted prior to the predetermined time using a predetermined weight determined between the Node B and the MS. However current channel environments are not reflected in the aforementioned case, such that the weight for maximizing the reception power is not applied to the aforementioned case, and an optimum weight is not applied to signals generated until applying a weight where a channel situation is reflected, resulting in deterioration of system performance. In conclusion, a method must be developed for solving the aforementioned problems during a handover.

Apparatus and method for mode transition of a transmit diversity scheme in a mobile communication system for using transmit diversity scheme in a mobile communication system for using transmit


A method for realizing content sharing among mobile terminals comprises: receiving an index of access content sent by a requesting mobile terminal; looking up a shareable content index table for the index of the access content; and sending identification information of a mobile terminal having the index of the access content to the requesting mobile terminal if the index of the access content is found, so that the requesting mobile terminal obtains the requested access content from the mobile terminal having the index of the access content via wireless communication.

Global mobile internet has entered into an explosively increasing stage. Till now the user number of China Mobile becomes more than half a billion. However, traditional telecommunication operators face a dilemma: 3G wireless data traffic is sharply increased, while a bandwidth bottleneck gradually emerges. Users also have increasing requirements for mobile data content services comprising digital multimedia content services and content services of websites. In order to make effort to satisfy such increasing requirements for mobile data content services from the users, networks and frequency spectrums of most operators run at full capacity.
FIG. 1 shows a schematic view of requesting to obtain content services by communication among mobile terminals and base stations in a cell in the prior art. In order to acquire data content services, a mobile user needs to communicate with a base station via an Air Interface. The "Air Interface" represents a wireless transmission specification between a base station and a mobile phone, and defines the use frequency and bandwidth of each wireless channel and the employed coding method. After receiving a request from a mobile terminal, the base station obtains content to which the mobile user requests to access from a network server and a content server in an IP core network via a wired network, and sends it to the mobile terminal through the Air Interface.
With the increasing of the number of mobile users, the wireless spectrum resources of the Air Interfaces are increasingly limited so that the quality of data content services obtained by the mobile users is degraded, and the user experience is deteriorated.
Thus, how to sufficiently increase the utilization of the spectrum in the case of current spectrum resources is very important and valuable for dealing with crisis of spectrum resources and enhancing the experiences of mobile users.

International Business Machines Corporation


A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter, in a second or subsequent clock cycle, the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.

The present invention relates generally to a bus arrangement which interconnects a number of modules or components in a digital system and more particularly to a synchronous bus arrangement and associated method for providing high speed, efficient digital data transfer between the modules. Implementation of the bus arrangement is contemplated at chip level, forming part of an overall integrated circuit, and is also contemplated as interconnecting discrete modules within an overall processing system.
Many bus structures have been implemented for purposes of interconnecting modules in a digital system. Module interfacing may generally be performed with relative ease when all of the modules are designed in accordance with the same set of design parameters (i.e., rules) such as, for example, those of a particular manufacturer. However, in the instance of modules designed by different manufacturers or obtained from different sources, complex interface problems may be introduced which, in turn, require significant special provisions (typically in the form of logic circuitry) in order to properly interface with a bus structure.
While the concept of modular components was initially implemented using discrete modules, it should be appreciated that there now exists an industry wide movement toward the use of modular components (i.e., functional blocks) at the integrated circuit level. This movement toward modular design in integrated circuit manufacturing has been fueled, at least in part, by the desire to manage the continually increasing complexity and overall size of integrated circuit chips. As a result of the modular design methodology, however, single IC chips may now incorporate modules which are designed to different standards and which are provided by different sources such that complex interface problems are now present at the chip design level. In an environment such as, for example, a custom IC manufacturing house using modules designed by various sources, such interface problems can be particularly troublesome.
In the prior art, module interface problems are typically resolved by using logic circuitry which resides in the bus structure between the modules. This approach was initially applied for interfacing discrete modules and, as one would expect, later applied for interfacing modules integrated within a single IC. As will be seen, the use of logic circuitry in resolving interface discrepancies is not without a price.
When a bus structure is implemented between a configuration of discrete and/or co-integrated modules, it should be appreciated that the bus structure itself determines, to a significant extent, the highest speed at which the configuration may operate. If the bus structure incorporates logic circuitry, data is subjected to specific delays during any clock cycle. These specific delays are imposed solely by the logic circuitry. If any delay imposed by logic circuitry is longer than the clock cycle, the configuration will fail to operate properly unless the clock speed is adjusted (i.e., reduced) whereby to disadvantageously inhibit the overall data throughput of a particular system.
In spite of this disadvantage, however, logic circuitry forming part of the bus structure remains as the standard approach in resolving the complexity of interface problems between co-integrated modules in an IC. At the same time, it should be noted that this approach has proven to be effective when used in producing relatively small IC""s, since bus related problems can be traced in a relatively straightforward manner by observing the overall operation of the chip. In a very large scale IC, however, the complex interactions between the modules in combination with other factors such as, for example, the immense numbers of signals which are present essentially eliminate the possibility of utilizing a simplistic troubleshooting technique. Moreover, other concerns come into play with regard to IC implementations at the very large scales contemplated herein, as will be seen immediately hereinafter.
It should be mentioned that delay times are introduced by factors other than interfacing logic circuitry. For instance, loading (i.e., the number of loads driven by a particular line) and the physical length of the bus structure each cause delays. With particular regard to the design of very large scale IC""s, which use the aforedescribed modular approach, bus loading and length are some of the most unpredictable and difficult to control variables. For example, the number of modules can vary from one implementation to the next and/or the physical distribution of the modules on the chip can vary. Thus, the addition of logic circuitry to the bus structure further complicates the design process by adding still more unpredictability to an already substantially unpredictable area.
As will be seen hereinafter, the present invention provides a highly advantageous bus arrangement and associated method which eliminate the need for logic circuitry within the bus arrangement so as to maximize the clock rate at which a particular configuration of integrated and/or discrete digital modules may operate in accordance with a reliable design approach.
As will be described in more detail hereinafter, there is disclosed herein a bus arrangement and an associated method. The bus arrangement is used in a digital system including three or more modules, which are configured for sending and/or receiving data using one or more respective inputs and/or outputs. The bus arrangement includes an input synchronization arrangement having a plurality of first, input latches. Each input latch includes an input terminal and an output terminal such that each module input is connected with the output terminal of an associated input latch. The bus arrangement also includes an output synchronization arrangement having a plurality of second, output latches each of which includes an input terminal and an output terminal such that each module output is connected with the input terminal of an associated output latch. An interconnection arrangement is provided for electrically interconnecting the output terminals of certain output latches with the input terminals of certain input latches in a predetermined way for transferring data between the modules such that the data does not encounter logic circuitry between the certain input and output latches.
In one aspect of the present invention, a single master clock signal is provided to the modules of the system. Using a first one of the modules, data is generated for use by a second one of the modules. During a first cycle of the master clock signal, data generated by the first module is latched and, thereafter, transferred to all other modules via the bus arrangement. During a second cycle of the master clock signal, the transferred data is latched at all modules other than the first module such that the transferred data is available for use by the intended, second module.

Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method


To provide a thin metal base circuit board which can be not only installed on a flat portion but also closely attached to a side or bottom surface of a case or to a stepped or curved portion and which is excellent in heat dissipation performance, electrical insulating performance and flexibility; a process for its production; and a hybrid integrated circuit, an LED module and a bright, ultra-long-life LED light source employing it. A metal base circuit board having insulating layers and conductive circuits or metal foils alternately laminated, characterized in that the thickness of each conductive circuit or metal foil is from 5 μm to 450 μm, each insulating layer is made of a cured product of a resin composition comprising an inorganic filler and a thermosetting resin, and the thickness of each insulating layer is from 9 μm to 300 μm; and a hybrid circuit board employing it.

In recent years, circuit boards for mounting semiconductors are required to have the boards small-sized and to accomplish high density mounting and high performance. Further, it has been a problem how to dissipate the heat generated from e.g. semiconductor elements in a narrow space limited by small-sizing or high power of e.g. the semiconductor elements. Particularly, a metal base circuit board having a circuit formed by bonding a metal foil via an insulating layer on a metal plate has been commonly employed for the reason that it is excellent in heat dissipation performance mainly in the electric power source field or the automobile electric installation field.
However, in a metal base circuit board, the thickness of the base board is usually from 1.0 mm to 3.0 mm, whereby it is difficult to reduce the thickness, and the installation site is rather limited. Further, it has a structure formed via a thin insulating layer on a metal plate, whereby there has been a problem such that noises are likely to occur, or malfunction of a module is likely to occur.
In order to shield noises or to increase the heat dissipation performance, a metal base multilayer board is, for example, known wherein an upper layer circuit board having a circuit is laminated, via an adhesive agent, on is the entire surface or a part of the surface of a metal base circuit board (Patent Document 1).
In such a construction, an adhesive layer poor in the heat conductivity is present between the metal plate and the upper layer board, and in a case where a high power element is mounted on the upper layer circuit pattern, the heat dissipation performance tends to be inadequate, and the temperature of the element tends to rise, thus leading to a problem of malfunction.
In order to solve such a problem of heat dissipation performance, a metal base circuit board having a highly heat conductive insulating layer is known (Patent Document 2).
However, the metal plate was thick and could not be installed as attached along the shape of a case such as a case having a curved surface, and thus the heat dissipation performance of the insulating layer could not be sufficiently utilized. Besides, a large space was required for its installation, since it could not be installed in a bent form, and there was a problem such that the module could not be small-sized.
On the other hand, a metal base circuit board having an insulating layer made of e.g. an epoxy resin containing an inorganic filler formed on a metal plate, and having a circuit pattern formed thereon, is excellent in heat dissipation performance and electrical insulating performance and thus is used as a circuit board for an electronic equipment for e.g. automobiles and communication instruments having highly heat generating electronic components mounted (Patent Document 3).
If a metal base circuit board can be optionally bent, the limitation in the installation site which used to be limited to installation on a flat portion, will be relaxed, and it will be possible to adhere, bond or closely attach by e.g. a screw it to a side or bottom surface or to a stepped or curved surface of a case, whereby an electronic equipment having a highly heat generating electronic component mounted, can be small-sized. Further, if a metal base circuit board itself can be made thin, it can be inserted or fixed in a narrow space, whereby an electronic equipment having a highly heat generating electronic component mounted, can be made thin.
It has been proposed that by a method of heating a metal base circuit board at a high temperature of at least 120° C., i.e. by carrying out bending or drawing in such a state that the metal base circuit board is heated at a temperature higher by at least 10° C. than the glass transition temperature (Tg) of the insulating layer, the metal base circuit board having a non-flat portion is used also as a case or an electronic circuit package (Patent Document 4).
Further, a light-emitting diode (LED) light source unit using a light-emitting diode (LED) as a light source, has been used in various fields, but, for example, in a light source for backlight of a liquid crystal display device, it has been common to use a small size fluorescent tube so-called CFL (compact fluorescent lamp).
The light source of the above CFL (compact fluorescent lamp) adopts a construction such that Hg (mercury) is sealed in a discharge tube, and ultraviolet rays discharged from mercury excited by electrical discharge will impinge on the phosphor on the tube wall of CFL (compact fluorescent lamp) and will be converted to visible light. Therefore, recently, from the viewpoint of the environment protection, it has been desired to use a substitute light source not using hazardous mercury.
As a new light source, one using a light-emitting diode (hereinafter referred to simply as "LED") has been proposed. With LED, the light has directional characteristics, and particularly with a surface mounting type on e.g. a flexible board, the light will be taken out in one direction, and as different from a structure using conventional CFL (compact fluorescent lamp), the light loss is small, and thus, it is used as a light source for backlight in a planar light source system (Patent Document 5).
The backlight using LED as a light source is now being widely used as backlight of a liquid crystal display device along with reduction of the price, improvement in the luminous efficiency and environmental regulations. At the same time, along with the higher brightness of a liquid crystal display device and enlargement of the display area, the increase in number of LED mounted on e.g. a flexible board and the trend for higher output are in progress in order to improve the luminescence.
However, the light source of LED has low luminance efficiency, and majority of the input power to illuminate LED will be discharged as heat. When an electric current is conducted, LED generates heat and becomes to have a high temperature due to the generated heat, and in an extreme case, LED will be destroyed. Also in a backlight using LED as a power source, such generated heat will be accumulated in LED and the board having LED mounted, and along with the increase of the temperature of LED, the luminance efficiency of LED itself tends to deteriorate. Besides, if it is attempted to increase the number of LED to be mounted or to increase the input power in order to make the backlight bright, the heat generation will further increase, and it is therefore important to remove such heat.
In order to reduce the heat accumulation in the LED-mounted board and to reduce the temperature rise of a LED chip, it has been proposed that a metal film having a LED chip mounted on a LED chip-mounted surface of a LED-mounted board, a metal drive wiring to supply a drive current to the LED chip and a metal film pattern intended for heat dissipation, are formed, a metal film for heat dissipation is formed on a surface facing the LED chip-mounted surface, and a metal through-hole is formed in a thickness direction of the LED chip-mounted board to connect the metal pattern on one main surface side to the metal film for heat dissipation on the other main surface side, so that heat generation from LED is dissipated through the metal through-hole to the rear side metal film (Patent Document 6).
However, in a case where the shape of LED to be mounted is small, the area of the mounted metal film will be limited, and the number of metal through-holes which can be formed immediately beneath LED will be limited, and in a case where a metal film pattern can not be formed on the mounted board from the restriction of the board area, there will be a problem such that the heat generated by LED can not efficiently be released to the rear side of the board.
Further, if a metal base circuit board using a metal base plate having a thickness of 2 mm is used instead of the flexible board, good heat dissipation can be obtained without necessity to provide metal through-holes, but there will be a problem that the thickness of the board tends to be thick, and it will be necessary to enlarge the size for punching out from e.g. an electrode and a circuit pattern over the flexible board, whereby the board area is obliged to be large. Further, it is not possible to optionally bend a portion other than the LED-mounted portion, whereby e.g. the position to form an input terminal will be restricted.
Besides, if the thickness of the metal base of the metal base circuit board is made thin to have such a structure that the size for punching out from e.g. an electrode and a circuit pattern is made small like a flexible board, even when the metal base circuit board is slightly bent, the insulating layer will have cracking and become useless. Likewise, there has been a problem that the LED-mounted portion can not be optionally bent.
Further, a metal base circuit board using a metal foil of from about 9 to 40 μm having a conductive circuit provided via an insulating layer containing a heat conductive filler and having heat dissipation performance and good bendability at room temperature, instead of a conventional polyimide type insulating layer, has been developed, since it can be used as being bent at room temperature and has bending processability.
However, if the conductive circuit was bent at an angle of 90° with a very small radius of curvature of at most 0.5 mm, the insulating layer at the bent portion was likely to have cracking and become useless. Therefore, if it was reinforced with a coverlay having an epoxy adhesive layer formed on a polyimide film, it was possible to prevent cracking in the insulating layer at the bent portion, but the bendability decreased, and there was a problem that it became difficult to bend it at an angle of at least 90° with a very small radius of curvature of at most 0.5 mm.
Further, in a case where a circuit board for mounting a semiconductor or a small size precision motor is, for example, mounted, there has been a problem that noises are likely to occur, or malfunction of a module is likely to occur.    Patent Document 1: JP-A-05-037169    Patent Document 2: JP-A-09-139580    Patent Document 3: JP-A-62-271442    Patent Document 4: JP-A-2001-160664    Patent Document 5: JP-A-2005-293925    Patent Document 6: JP-A-2005-283852

Metal base circuit board, LED, and LED light source unit


Embodiments relate to a monolithic arrangement comprising one or more electrochemically responsive electrodes that are configured to generate a signal relating to a characteristic of a fluid sample; and one or more electronic circuits for processing signals generated by the at least one electrode. Optionally, the monolithic arrangement comprises a plurality of electrodes configured to implement potentiostat and/or galvanostat measurement techniques. Optionally, at least two of the plurality of electrodes have different electrochemical material layers to obtain correspondingly different electrode functionalization.

Chemical analysis of fluid or humid materials is a common problem for which a large number of investigation techniques exist. Electrochemical methods are of particular simplicity and ease of use. Electrochemical techniques encompass a class of analytical chemistry methods which measure the concentration of a chemical analyte by measuring the electric potential and/or the electrical current in an electrochemical cell in which the analyte is present in a fluid sample. In practice, the two main electrochemical categories are potentiometry and galvanometry (also called amperometry or voltammetry).
Potentiometry is implemented with a so-called potentiostat, measuring the voltage difference between a working electrode (also: WE) and a reference electrode (also: RE) in a two-electrode electrochemical cell. Potentiometry is used to measure the concentration of ions (charged atoms or molecules) in a fluid sample.
Galvanometry is implemented with a so-called galvanostat, measuring the current between a counter-electrode and a working electrode, while controlling the electrical potential between the reference and the working electrode in a three-electrode electrochemical cell. Galvanometry is used to measure the concentration of uncharged analytes in a liquid sample, by converting an analyte from one oxidation state into another. By measuring the number of electrons transferred in this redox reaction, the concentration of the analyte in the sample can be determined.
References which may be considered to be relevant as background to the presently disclosed subject matter are listed below:
International patent application WO2016/070083, "Multichannel Potentiostat Analyzer System and Method" to L. I. Baichen discloses (Abstract):    "The present disclosure outlines a device having a multi-channel potentiostat circuit and a microcontroller for controlling the multi-channel potentiostat circuit. The multi-channel potentiostat circuit includes a counter electrode, a reference electrode, and a first switch between the counter electrode and the reference electrode. The multi-channel potentiostat circuit also includes a plurality of measurement circuits coupled to respective second switches. The microcontroller can configured [sic!] to provide a first signal to the multi-channel potentiostat circuit to control the first switch, wherein a state of the first switch changes an operating mode of the multi-channel potentiostat circuit. The microcontroller is also configured to provide a second signal to the multi-channel potentiostat circuit to control at least one of the second switches to couple at least one of the plurality of measurement circuits to a working electrode."
European patent application EP2980577 titled "Electrochemical Sensor System and Sensing Method" to Marshall, discloses (Abstract):    "A sensor system for assessing a target species in a liquid medium is disclosed. The sensor system includes a sensor element which is inserted a sample of liquid medium to be tested. The sensor element has three or more electrodes and receives a predetermined potential from a potentiostat. This potential is determined as the potential associated with an electrochemical reaction characteristic in the liquid medium of a target species. The sensor system also includes an output to display data corresponding to the current passing through the liquid medium which is indicative of the concentration of the target species and resulting from the electrochemical reaction which occurs."
European patent application US4670127 titled "Ion-sensitive membrane electrode" to Ritter et al. discloses (Abstract):    "In order to produce a sensitive membrane electrode with high selectivity with respect to other anions and lipophilic ions or interfering substances, the membrane is based on an unplasticized polymer matrix whose content of electroactive component is between 50 and 90 percent by weight."
Maalouf et al. disclose in "Label-Free Detection of Bacteria by Elecrochemical Impedance Spetroscopy: Comparison to Surface Plasmon Resonance", Anal. Chem. 2007, 79, 4879-4886: (Conclusion):    "The present study has demonstrated the successful deposition of mixed SAMs of biotin-thiol and OH-thiol on a gold electrode, enabling the subsequent immobilization of biotinylated anti-E. coli via a strong biotin—neutravidin interaction."
Acknowledgement of the above references herein is not to be inferred as meaning that these are in any way relevant to the patentability of the presently disclosed subject matter.
Moreover, the description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.

Chip-based multi-channel electrochemical transducer and method of use thereof


A forward rescue procedure (FRP) for preventing loss of signal and dropped connections between a mobile station and the infrastructure in a wireless telecommunications network is disclosed. The FRP allows wireless systems to recover from forward link failures at the mobile station that would otherwise result in dropped connections. Examples of failure scenarios that can be overcome using the FRP include forward link Layer 2 acknowledgement failures and loss of forward link signal due to a fade that causes loss of signal for a period of time exceeding a threshold value. In response to a potential connection drop situation, a mobile station will autonomously add base station pilot channels to the active set of its rake receiver in order to rescue the connection in danger of dropping. Concurrently, the wireless network infrastructure will initiate transmission on alternative forward link channels that are likely to be monitored by the mobile station during an FRP. If the same channels are monitored by the MS and transmitted on by the infrastructure, the connection in danger of dropping can be rescued.

1. Field of the Invention
The present invention relates, generally, to communication network management and, in one embodiment, to methods and apparatus for preventing loss of signal and dropped connections between a mobile station, such as a cellular or PCS phone, and a wireless communication infrastructure (network).
2. Description of Related Art

Forward link based rescue channel method and apparatus for telecommunication systems