A numerical control machining apparatus, having a section for reading out and analyzing machining programs from a storage section to control the axis drive section of a machine tool, also can display the quantity and direction of movement for each axis on a display section. The axis movement is identified by symbols that reflect a pre-set correspondence between the direction of movement instruction to each axis of the machine tool and the direction of the actual movement of each axis of the machine tool seen by an operator. That correspondence is stored beforehand when an operator inputs instructions for the various movements of the axes and the operator examines the machine's response and identifies a symbol that corresponds to that response, such as an arrow whose orientation corresponds to an observed movement direction. Thereafter, when the programmed operation is conducted, the presence or absence of axis movement, the quantity and the direction thereof as seen by the operator is determined and, on the basis of the previously input data, an axis movement symbol creation section selects from storage the visual symbols that respectively match the direction etc. of the movement of each axis. These symbols are displayed on the display section to indicate the current position of each axis, and the direction of the actual movement of each axis as seen by the operator.

1. Field of the Invention
The present invention relates to a machining apparatus, such as a numerically controlled apparatus (hereinafter, NC apparatus) or programmably controlled apparatus (hereinafter, PC apparatus) that controls the machining operations of a machine tool and, in particular, to an NC apparatus or PC apparatus, including method therefor, which is capable of displaying in an easily identifiable manner the operation of each axis of a machine tool.
2. Description of the Related Art
FIG. 8 is a view illustrating the hardware configuration of a conventional NC apparatus and the main sections of the numerically controlled apparatus. In FIG. 8, reference numeral 1 denotes a numerical control section, 2 denotes a storage section in which machining programs and various parameters are stored, 3 denotes a display control section for outputting various machining information based on the machining programs and various parameters to a display section 4, having a CRT monitor, and 5 denotes an operation section which is integrally provided with the display section 4. Various operations performed on an NC apparatus, using a machine tool, are input to the numerical control section 1 by way of an operation control section 6. Reference numeral 7 denotes an axis drive section for each of the axes of a machine tool 8 which controls the driving of each axis on the basis of machining data obtained from computations made by the numerical control section 1. The machine tool 8 is provided with two tool turrets 17 and 18, each having one or more tools that are rotatable about an axis into a machining position. A workpiece 16 is mounted on a so-called C axis, which is a main axis of the machine tool 8. The tool turret 17 has axes X1 and Y1, and the other tool turret 18 has axes X2 and Z2. The tool turrets are selectively moveable in their axial directions to permit selected tools to engage the workpiece and perform a desired machining operation.
The conventional NC apparatus is constructed as described above. The numerical control section 1 reads out and analyzes machining programs which have been previously stored in the storage section 2, determines the movement quantity of each axis, and outputs it to the axis drive section 7. The axis drive section 7 controls the machine tool 8 to perform a desired machining on the workpiece 16. Specifically, section 7 converts the axis movement quantity into drive signals that can drive a motor section (not shown) disposed in the machine tool 8 in order to rotate the workpiece 16 and move the tool turrets 17 and 18 according to the stored programs.
At the same time, the numerical control section 1 determines the current position of each axis in the coordinate system, on the basis of the previous axis position and axis movement quantity, and displays this position data on the display section 4 by way of the display control section 3. That is, axis names 9 and data 10 indicating the current position of each axis corresponding to a name of the axis are displayed by the display section 4.
Concerning the movement instruction to each axis, the arrow direction is denoted as + and its opposite direction as - in FIG. 8. Since the position data 10 matches the instruction of the machining program, the data 10 shows only the current position of each axis that increases or decreases in accordance with the + or - instruction in the coordinate system of the machine tool.
The rotation of the workpiece 16 is represented by the movement about the C axis. Rotation is to the right (clockwise) for the + instruction and to the left (counterclockwise) for the - instruction.
In the above-described conventional NC apparatus, there has been a disadvantage in that, when an operator desires to confirm the operating status of a machine tool on a display section, he cannot know immediately in which direction each axis of the machine tool has actually moved and, therefore, sometimes he must confirm the operating status of the machine tool by direct inspection of the tool. In particular, where a certain axis of a machine tool operates in a wrong direction because an error has been made regarding the instruction direction of a machining program, a problem arises in that it is difficult to know that the machine tool is operating in a wrong direction from the display of the current position by the display section. Similarly, if the motor is faulty, the machine may not respond correctly, in the manner commanded by the programs. Of course, where there are keyboard inputs to control the movement of the tools or workpiece, errors can easily occur which cause the machining to proceed in the wrong direction.
Even if the above errors may be detected by an automatic detector that can give an alarm, often the operator will be quicker to recognize the mistakes than a detector with pre-programmed limits.
The present invention has been devised to solve the above-mentioned problems.
Accordingly, an object of the present invention is to provide a machining apparatus having a display, and method therefor, which provides an operator with the operating status of each axis of a machine tool such that it can be identified rapidly and accurately.

Method and apparatus for display of machining status


A set of interlocking hangers includes a frame portion, a hook portion coupled to the frame portion for suspending the frame portion, and a support portion coupled to the frame portion. The support portion includes opposed front and back sides. A lock includes a catch, defines an aperture, and includes an actuator. The catch has an extension and a lip, the catch extending from the front side of the support portion and is disposed between the lip and front side of the support portion. Further, the aperture has a front perimeter on the front side of the support portion, the front perimeter being contained in a first plane and a back perimeter on the back side of the support portion. The hangers are movable between a separated configuration at which the hangers are spaced apart and a joined configuration at which the first hanger is adjacent the second hanger.

This invention relates generally to hangers such as hangers for holding clothing and, more particularly, to a set of clothing hangers that are lockable and securable to each other so that the secured set of hangers may be carried with risk of the hangers becoming separated and falling to the floor.
Typically, multiple hangers are simply stacked atop one another and then dumped into a box and carried. The very act of placing the hangers in a box or tub results in the hangers being separated and having to be stacked and gathered again at the desired new location. In some previous instances, hangers have defined a hole to which a next hanger having a flange may be attached. Although assumably effective when carried, such hanger sets often become separated if tossed into a box or tub or simply when manipulated to couple multiple hangers together.
Therefore, it would be desirable to have a set hangers that not only defines an aperture and an extension member configured to be received into the aperture but also includes an extension member with a lock portion and actuator for securing a set of hangers together.


An object of the present invention is to provide an optical multiplexing apparatus and a projector that keep an optical system small, and easily adjust a number of light source units. The optical multiplexing apparatus has: a light source section that uses light source units to emit collimated beams; a first lens portion that converges the collimated beams which enter at different incident angles from each other to define converging positions; and a second lens portion that has focal points that correspond to the converging positions, respectively, wherein the first and second lens portions form an optical reduction system, and an optical axis of the second lens portion, which is directed to the corresponding focal point to one of the converging positions, extends along another optical axis of the second lens position, which is directed to the corresponding focal point to another of the converging positions.

Various optical multiplexing apparatuses and projectors for emitting highly bright light at high power have been proposed. For example, Patent Document 1 discloses an illuminator which has a few light source units. The illuminator has a fly-eye lens to which convergent beams emitted from the light source units enter at different incident angles. The illuminator uses the fly-eye lens to multiplex the beams.
Patent Document 2 discloses a display apparatus which projects highly bright light. The display apparatus has a few light source units. The beams from the light source units are collimated, and then enter one fly-eye lens. The incident beams to the fly-eye lens are parallel with each other. The display apparatus uses the fly-eye lens to multiplex the beams.
Patent Document 3 discloses an image display apparatus which has two light sources. The polarization planes of the beams emitted from the light sources are perpendicular to each other. The image display apparatus uses a polarizing prism to multiplex the beams.
Patent Document 4 discloses an illuminator which has a few laser sources for emitting collimated beams. The illuminator has a special prism configured to reduce optical axis intervals of the collimated beams. The illuminator uses an inclined surface of the prism to multiplex the beams.
According to the technologies disclosed in Patent Document 1, the beams multiplexed by the fly-eye lens become divergent light thereafter. Therefore, an increase in a quantity of the light source units increases the divergent angle. This means that the illuminator of Patent Document 1 needs a large optical system to process the multiplexed light.
According to the technologies disclosed in Patent Document 2, an increase in a quantity of the light source units means an increase in collimated beams, which are parallel with each other. Therefore, like the illuminator of Patent Document 1, the display apparatus of Patent Document 2 needs a large optical system to process the multiplexed light.
The image display apparatus of Patent Document 3 uses the polarization planes, which are perpendicular to each other, and the polarizing prism to multiplex the beams. Therefore, a quantity of the light source units, which is available according to the disclosed technologies in Patent Document 3, is limited to two. This means that the disclosed technologies in Patent Document 3 are not directed to increase a quantity of the light source units.
According to the technologies disclosed in Patent Document 4, an increase in a quantity of the light source units means an increase in collimated beams, which are parallel with each other, like the display apparatus of Patent Document 2. The illuminator of Patent Document 4 uses the special prism to reduce the optical axis intervals of the collimated beams, but still needs a large optical system to process the multiplexed light.
Patent Document 1: JP H5-045605 A
Patent Document 2: JP H10-293545 A
Patent Document 3: JP 2000-180795 A
Patent Document 4: JP 2003-31872 A

Optical multiplexing apparatus and projector

Panasonic Intellectual Property Management Co., Ltd.


A method and apparatus are for receiving a portion of a message by a call receiver (2). A radio signal is intercepted (910) which is modulated with a hierarchical signalling protocol having variable bit rate protocol divisions (443). A particular variable bit rate protocol division (443) includes the portion of the paging message and a bit rate indicator (460). An optimum bit rate that is being used in the particular variable bit rate protocol division is determined (930) from the bit rate indicator (460). Words (450, 455) in the particular variable bit rate protocol division (443) are decoded (940) using the optimum bit rate. The portion of the paging message is obtained (950) from the words.

A known technique of increasing information throughput in synchronous signalling systems is to use increased bit rates to communicate the information. Older wide area radio communication systems, such as systems using the POCSAG (Post Office Commission Standards Advisory Group) signalling protocol, were designed to operate with pagers having a fixed bit rate. Newer systems, such as those using the FLEX.TM. family of signalling protocols licensed by Motorola, Inc., of Schaumburg, Ill., allow the use of a bit rate selected from a set of predetermined bit rates, typically by a set of portable or mobile receiving units operating in a common transmission cell.
The POCSAG and FLEX.TM. signalling protocols, like other signalling protocols, are defined using a hierarchical signalling protocol, with several protocol divisions of differing levels, wherein each protocol division is formed by a plurality of protocol divisions of a next lower level. The protocol divisions can be further identified as protocol divisions of the first, second, etc., level, with the first level protocol division being a POCSAG frame in POCSAG, comprising two POCSAG words and a FLEX.TM. block in FLEX.TM., comprising 8, 16, or 32 FLEX.TM. words, depending on the bit rate, so that FLEX.TM. blocks are of the same duration regardless of bit rate. The second level protocol division in POCSAG is a POCSAG batch, comprising eight POCSAG frames; the second level protocol division in FLEX.TM. is a FLEX.TM. frame, comprising 11 FLEX.TM. blocks. In POCSAG, no higher level protocol divisions are formally named; at this level, a single POCSAG transmission comprises any number of POCSAG batches, each preceded by a synchronization code. The third level protocol division in FLEX.TM. is a FLEX.TM. cycle, comprising 128 FLEX.TM. frames. The fourth level protocol division in FLEX.TM. is an hour, which comprises 15 FLEX.TM. cycles and has a duration of sixty minutes. Protocol division of higher levels in FLEX.TM. are defined by standard time divisions (day, month, and year).
As stated above, a bit rate used in the FLEX.TM. signalling protocol can be one of several predetermined bit rates. The bit rate being used for subsequent information being transmitted within a FLEX.TM. frame is identified at the beginning of each FLEX.TM. frame, during a synchronization pattern which is provided to allow any radios, such as pagers, that have been not receiving for a FLEX.TM. cycle or more to acquire exact word and bit synchronization. Pagers and other radios that are active in a FLEX.TM. system can be set up to go into a battery saving mode for all frames except one in a FLEX.TM. cycle, or can alternatively be set up to go into an active receiving mode for a plurality of frames, such as two or four in each cycle, effectively reducing an average latency for receiving messages, but at a trade-off of poorer battery life than when only one frame per cycle is used. Thus, the frame can alternatively be described as a battery saving protocol division in FLEX.TM..
Each time a radio goes into the active receiving mode, it acquires exact synchronization and determines the bit rate to be used within the FLEX.TM. frame. It further determines a protocol position within a frame at which information for the specific radio is located, for example, a frame number, a block number and a word number. The frame number could be the same frame at which the radio went into the active mode, or any other frame.
This design provides an efficient approach to operating a group of radios which receive message information within the same FLEX.TM. frame at a common bit rate which is maximized for the group. Generally, this works well when a common bit rate is used by a group of radios which always receive at one of the predetermined bit rates; the radios in the group can be assigned to a certain frame or frames that are predeterminedly sent using the bit rate. Thus, a maximum bit rate can be chosen for the group based on the capability of the system (for example, the density and power of fixed system transmitters) and the sensitivity of the receiving radios.
A third signalling protocol is described in U.S. Pat. No. 5,613,194 issued Mar. 18, 1997 to Olds et al., entitled "SATELLITE-BASED CELLULAR MESSAGING SYSTEM AND METHOD OF OPERATION THEREOF," in which the bit rate used for communicating information to pagers is fixed. Although this system is quite efficient, it does not provide for optimization of the bit rate as determined for a particular link to a particular receiving radio.
When all radios in a group of radios are of the same sensitivity and operate within a communication cell associated with a transmitter, it is well known to one of ordinary skill in the art that a specific link to one radio can be substantially better or worse than a link to another radio in the same group. Further improvements in throughput efficiency would be possible if a bit rate could be conveniently established for transmitting a portion of a message (up to and including a complete message) to each radio for which a portion of a message is queued depending on the characteristics of a specific link to the one radio.
Thus, what is needed is an improved technique within a radio communication system for establishing an optimum bit rate for transmitting a portion of a message to a radio which is compatible with a battery saving scheme, and a corresponding technique in a radio for responding to the optimum bit rate.

Method and apparatus for adjusting data rate in a synchronous communication system


In an embodiment, a data processing system comprises a repository configured to store a plurality of event message definitions for error messages, syslog messages, or other notification messages that may be emitted by one or more managed network elements; event annotation logic coupled to the data repository and configured to receive and store one or more annotations to each of the event message definitions, wherein each of the annotations specifies event context information to be collected in the managed network elements when an associated event message occurs; event forensics definitions generator logic coupled to the event annotation logic and configured to generate an event forensics definitions file capable of interpretation by one or more managed network elements and comprising event type identifiers and context information identifiers for context information to be collected, and configured to cause distributing the event forensics definitions file to the one or more managed network elements.

The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Problems in data communication networks generally lead network devices (such as routers and switches) generating event messages. Often, the event messages refer to symptoms rather than root causes, and in many cases the significance of an event is not immediately recognized at a network management computer or through review by a human analyst. At the same time, many events contain only limited information about context in which they occur. Such context can include information about certain state or even statistical information at the time of event occurrence, such as current link or CPU utilization. Context information is fleeting, and by the time an external application, or user, or support staff decides to issue a query, it may already have been lost. Context information may be different for different event messages, so that each particular event or event type is associated with a different interesting and unique context. The information that is relevant and needed is often specific to the event, operational environment, heuristics that are applied by a particular operator, and/or the network deployment; in many cases it is not known a priori what that information is; instead, it is the result of operational experience that is gained over time.
Thus, collecting timely and relevant information about network events has been a difficult task in past practice, and past attempts to address the problem have been inadequate. For example, network devices can be programmed with scripts that can be executed on the device, triggered by certain events. The Package Distribution System allows to dynamically distribute and to install packages containing data files (for data driven systems) or even entire applications. SUT (Syslog Usability Tool) maintains information about system messages, message definitions, and facilitates system message definition development. SUT allows users to provide additional information about messages that improve their documentation and over time help build a knowledge base.
However, even these components provide no practical way for a user to dynamically customize, over time, the context information that is to be collected in a timely manner for events within a device or across the network. Historically heavy system, or network, administration tasks have been required, involving writing scripts and managing their installation and activation across the network. Further, the learning of one user about what constitutes interesting context in a given situation has been difficult to benefit another user.

Adaptively collecting network event forensic data


The present invention provides a large scale integrated circuit which is capable of coping with the problems associated with the situation in which the number of pins used in the circuit is increased, and is capable, even when dummy bumps (DBPs) are installed, of suppressing storage of an excessive charge to the DBPs and prevent discharge to adjacent bump electrodes and prevent breakdown of a semiconductor chip due to electrostatic noise. On the element formation face of the semiconductor chip wherepads (PDs) are formed, a layer insulating film for rewiring, external bumps (EBPs) that correspond respectively to PDs formed on the layer insulating film, dummy bumps (DBPs) lacking corresponding PDs on the semiconductor chip, external bump rewirings that connect the PDs and the corresponding EBPs, and dummy bump rewirings that connect DBPs and prescribed EBPs are formed in addition. An electrostatic protection means is installed between a PD connected to an EBP that is connected to a DBP and an internal circuit section or an I/O circuit section of the semiconductor chip.

1. Field of the Invention
The present invention relates to a semiconductor device which uses bumps formed of solder balls or the like as external connection terminals, and more particularly to a semiconductor device that is enhanced in the breakdown voltage to electrostatic noise.
2. Description of the Prior Art
In the semiconductor devices (referred to as LSIs hereinafter) of recent years, the increase in the number of pins used is remarkable along with the achieved high level of integration and scale, as a result of advancement in the micro processing technology. As the methods of making the increase in the number of pins and miniaturization of the LSIs compatible, flip chip type LSIs (referred to as FCLSIs hereinafter), CSP (chip size package/chip scale package) type LSIs, and the like, in which bumps for external connection are formed two-dimensionally on the main face side where semiconductor chip elements are formed via an insulating resin layer, an interposer, or the like, have been developed. In addition, as another method for making the increasing pin number and the miniaturization compathatible, there have been developed the ball grid array (BGA) type LSIs. In this method, a semiconductor chip is mounted on the face opposite to the bump formation face of a printed board where bumps of solder ball or the like are arranged two-dimensionally, then after bonding a wiring conductor of the printed board connected to each bump to an electrode on the semiconductor chip with a wire of metal such as gold (Au), or solder connecting the electrode on the semiconductor chip with a bump formed thereon to the wiring conductor on the printed board, the semiconductor chip on the printed board and bonding wires and the like are sealed with a resin.
In FIG. 7 which shows an example of the conventional FCLSIs, part (a) is a plan view showing schematically the arrangement state of ball bumps on the face on which ball bumps are formed, and part (b) is an enlarged plan view of the portion including the connection wirings between the ball bumps and the electrodes on the chip in part C of part (a), and FIG. 8 is a sectional view along line P2–P2′ in part (a). Referring to FIG. 7 and FIG. 8, it can be seen that a conventional FCLSI 500 is provided with external connection bumps 521 and 523 formed two-dimensionally, via an insulating resin layer 515, on its main face where elements of a semiconductor chip 510 are formed, and rewiring conductors 541 which connect respective bumps 521 and 523 to respective electrodes 513 of the semiconductor chip 510.
Moreover, in FIG. 9 which shows an example of the conventional BGA type LSIs, (a) is a plan view of the back face where ball bumps are formed, and (b) and (c) are sectional views along line P3–P3′ of (a), showing the cases in which the electrodes of the semiconductor chip and the wiring conductors on the printed board are connected by bondings of metal wire and by bumps, respectively. Referring to FIG. 9, a conventional BGA type LSI 600 has a semiconductor chip 610 or 630 mounted on one main face of a printed board 602, first bump electrodes 620 of solder or the like formed at openings of an insulating film 607 formed on the face opposite to the one main face of the printed board 602, board wirings 604 and the chip 610 or 630 are connected either by bondings of metal wire 606 or by second bump electrodes 632 formed on the chip 630, and the semiconductor chip 610 and the metal wires 606 or the semiconductor chip 630 and the second bump electrodes 632 formed thereon are covered with a sealing resin 608.
In the FCLSI, CSP type LSI, BGA type LSI, and the like, the problems related to the increasing pin number and the miniaturization of the LSI are simultaneously taken care of by arranging the bumps that serve as external connection electrodes in two dimensions. In connection with these LSIs, installment of dummy bumps (referred to as DBPs hereinafter) is disclosed in, for example, Japanese Patent Applications Laid Open, No. Hei 1-238148 (referred to as well-known example 1 hereinafter) and Japanese Patent Applications Laid Open, No. Hei 10-12620 (referred to as well-known example 2 hereinafter) in order to increase the connection strength at mounting on the mount substrate as well as to enhance the connection reliability by securing parallel holding of the LSI and the mount substrate through uniformization of bump arrangement within the bump formation plane of the LSI, although it is not necessarily indispensable for realization of the functions of the LSIs.
In FIG. 10 for describing the semiconductor chip disclosed in well-known example 1, (a) and (b) are a plan view showing the arrangement of the bump electrodes and a sectional view of an important part of the chip, respectively, and (c) and (d) are schematic sectional views showing sequentially the mounting processes as seen at a position corresponding to line P4–P4′ in (a), respectively. Referring to FIG. 10, a semiconductor chip 701 disclosed in the well-known example 1 has, in its central section, bump electrodes 702 for connecting circuit elements in the chip to wiring conductors of a support substrate 709 to be mounted, and has DBPs 703 provided, at nearly a constant interval, in the periphery of the chip 701 surrounding the bump electrodes 702. The bump electrodes 702 and the DBPs 703 are formed in a manner stated roughly as in the following. On a first wiring conductor 731 which makes contact with an element region 711 of the chip 701 at an opening of an oxide film 721, a second wiring conductor 732 is formed via a layer insulating film 722, making contact with the first wiring conductor 731 at an opening in the layer insulating film 722. A passivation film 708 is formed to cover the top faces of the second wiring conductor 732 and the layer insulating film 722, and openings are formed on the second wiring conductor 732 and near the outer periphery of the chip 701 by photoetching. Then, after formation of an underlying metal layer 707 by laminating a chromium (Cr), a copper (Cu) and a gold (Au) films, the layer is patterned by photoetching, solder spots are attached onto the underlying metal layer 707 by solder plating, and solder spots are made spherical by heating to about 350° C., forming bump electrodes 702 and somewhat larger DBPs 703. At mounting of the chip 701, the bump formation face of the chip 701 is placed on the wiring support substrate 709, opposing the surface of the substrate 709. In this case, a thickness supplementing solder layers 710 are attached on the substrate in advance to compensate for the height difference between the DBPs 703 and the bump electrodes 702. When the system is subjected to solder reflow thereafter, the bump electrodes 702 with small diameter melt first to be adhered to the supplementary solder layers 710 during which time the bump electrodes 702 are formed into solder posts with height equal to the distance between the chip and the substrate that is kept constant by the DBPs with largediameter. After lapse of a certain time, the DBPs 703 start to melt and the peripheral part of the chip 701 and the substrate 709 are bonded. Following that, the DBPs 703 are fixed to the substrate 709 by covering their surroundings with, for example, an epoxy resin 704.
FIG. 11 is the plan view showing an example of configuration of bump electrodes of an FCLSI disclosed in the well-known example 2. The bump electrodes of the FCLSI 750 consist of a main bump electrode line 752a which is connected to the elements within the chip and a dummy auxiliary bump electrode line 752b which is not connected to the elements within the chip, and these are arranged along the periphery of the chip with the auxiliary bump electrode line 752b on the outer peripheral side. Moreover, the diameter of the bump electrodes in the auxiliary bump electrode line 752b is made larger than the diameter of the bump electrodes in the main bump electrode line 752a in order to facilitate filling of the resin between the chip and the substrate through increase in the amount of solder per chip and to enhance the bonding life of bump electrodes that are further away from the center of the chip.
However, it became clear with the configuration of the semiconductor chip as disclosed in well-known examples 1 and 2 that when electrostatic noise is applied to the DBPs, there arises a problem in that discharge is caused between the neighboring bump electrodes, and the internal elements connected to the bump electrodes are damaged or broken down.
More specifically, when there exist externally connected electrodes, like the DBPs in this case, that are not connected to any of the elements within the semiconductor chip, and electrostatic noise is applied to the DBPs, it results in a gap discharge phenomenon due to absence of discharge route for the charge. Moreover, since the voltage in the gap discharge phenomenon is higher in the case of an FCLSI, CSP type LSI, BGA type LSI, or the like where the bump electrode space (pin space) is larger than that in the case of a supermultiple-pin quad flat package (QFP) or the like where the pin space is smaller, damages to the adjacent bump electrodes are more conspicuous accordingly.
For example, in the chip 701 of the well-known example 1, the bump electrodes 702 adjacent to the DBPs 703 are connected to an electrostatic discharge protection circuit (not shown) formed on the semiconductor chip 701 via the first wiring conductor 731 and the second wiring conductor 732. Since, however, the electrostatic noise due to the gap discharge phenomenon is a pulse steeper than the breakdown voltage of the electrostatic discharge protection circuit, there is a possibility that it breaks down the semiconductor chip.
The gap discharge phenomenon is described in detail in, for example, Technical Research Report of the Institute of Electronics, Information and Communication Engineers (Environmental Electromagnetic Engineering), Dec. 18, 1998, pp. 37–42. According to the paper, the discharge is a very steep pulse with the current rise time of less than ins for voltages below 3,000V. On the other hand, according to the ESDA specifications, the JEDEC specifications, or the like used as the reference for the breakdown voltage in the design of normal LSI devices, the rise time of the discharge waveform is defined to be about 2–10 ns. The problem mentioned above is brought about because this value is gentle compared with the rise time of the discharge waveform in the gap discharge.
As the methods of resolving such a problem, a method of, for example, providing an electrostatic discharge protection circuit exclusively for external connection electrodes not connected to any of the elements within the semiconductor chip, namely, exclusively for non-connected (NC) pins, is disclosed in Japanese Patent Applications Laid Open, No. Hei 11-163247 (referred to as well-known example 3 hereinafter), although it is intended for dealing with a lead frame such as a QFP. In addition, a method of connecting dummy pins being NC pins to an adjacent input terminal via a resistor is disclosed in Japanese Patent Applications Laid Open No. Hei 11-233777 (referred to as well-known example 4 hereinafter).
FIG. 12 is an explanatory drawing of NC pins and the electrostatic discharge protection circuit disclosed in the well-known example 3. Referring to FIG. 12, there is shown a semiconductor device in which a bonding pad 812 and an electrostatic discharge protection circuit 814 dedicated to an NC pin are formed on a semiconductor chip 810, and an NC pin P1 (inner lead 803) and the bonding pad 812 dedicated to the NC pin are connected by a bonding wire 807. In this case, a method of preventing breakdown of the semiconductor chip due to electrostatic discharge to the input pins P3 adjacent to the NC pin P1 is disclosed by absorbing the overvoltage of the electrostatic noise applied to the NC pin P1 by the electrostatic discharge protection circuit 814 dedicated to the NC pin, and discharging (through surge path SGP) the charge to a power supply (Vcc, for example) line.
This method is effective in the point that the breakdown of the semiconductor chip 810 due to electrostatic discharge to the input pins P3 adjacent to the NC pin P1 is prevented by discharging the electrostatic noise applied to the NC pin P1 to the power supply line.
However, since the bonding pad 812 and the electrostatic discharge protection circuit 814 dedicated to the NC pin are formed in this method, the chip size becomes large as the number of the NC pins increases and the number of effective chips per semiconductor wafer decreases, so that it gives rise to the problem of increase in the production cost.
Moreover, in the well-known example 4, a method is disclosed in which the dummy terminal is connected to an adjacent input terminal via a resistor section, and a large quantity of static electricity generated in the dummy terminal is attenuated by the resistor section and the result is made to be absorbed by a protective circuit connected to the input terminal, or when a larger quantity of static electricity is generated, the protective circuit or internal TFT elements that are connected to the input terminals are protected by disconnecting the resistor section. However, it is also necessary in this method to provide a resistor for each NC pin which requires the chip size to be increased, so that similar to the well-known example 3, the number of effective chips per semiconductor wafer, leading to the problem of increase in the production cost.
Moreover, the problem relating to the electrostatic noise will not arise if the DBPs of the semiconductor device in the well-known examples 1 and 2 are connected to a power supply wiring such as the ground potential. However, it will result in a problem that the lead-out of the wiring conductors connected to the bump electrodes for signals on the mounting substrate becomes difficult. FIG. 13 shows drawings for describing the problem, which consists of a plan view of the electrodes and a wiring pattern of a mounting substrate 900 to be connected to external connection bumps of an FCLSI 500 when, for example, the FCLSI 500 in FIG. 5 is mounted on the mounting substrate 900, and a schematic enlarged plan view of the portion corresponding to portion B of the FCLSI 500. If DBPs 523a and DBPs 523b of the FCLSI 500 are connected to, for example, the ground potential within the FCLSI 500, the wiring patterns connected respectively to corresponding electrodes 923a and electrodes 923b of the mounting substrate 900 are also connected to the ground potential. If it is assumed that the number of passable wirings between electrodes in the mount substrate 900 is two, for example, the number of wirings between one pitch of the electrodes that can be led out to the outside from the mounting region of the FCLSI is three, including the one for the outermost peripheral electrode. However, when the outermost peripheral electrode is a DBP connected to a fixed potential such as the ground potential, the number that can be l;ed out as the signal lines is only two. Accordingly, when the outermost peripheral electrode is a DBP connected to a fixed potential such as the ground potential, the number of signal lines that can be led out to the outside from the mounting region of the FCLSI 500 is reduced, so that the number of BPs for signal that can be available for input/output of signals among the bumps of the FCLSI 500 is reduced, which becomes an especially serious problem in a signal processing LSI or the like needed for a large number of signal terminals.
Furthermore, the problems related to the LSI or the semiconductor chip disclosed in the well-known example 1 or the well-known example 2 will become more serious because of the anticipation that the bump electrode space will be reduced further with a further advancement in miniaturization and increase in the pin number of the future LSIs.


A screen frame formed from a metal sheet in a single unit folds and locks on V-cuts in a tube by a locking mechanism that is configured to engage in crossed directions by the folding.

1. Field of the Invention
The invention pertains to window screen frames, more particularly to a window screen frame that is made by folding a strip of formed stock.
2. Description of the Prior Art
The prior art is replete with patents for screen frames made by folding a strip of formed stock.
U.S. Pat. No. 1,596,950 patented Aug. 24, 1926 by P. F. Semonin describes a stamped sheet metal strip folded into a frame. A narrow longitudinal portion of the strip forms the outer wall of the frame. The side walls of the frame are 90 degree folded upward portions of the strip which are each folded again toward one another so that a longitudinal slot is formed along the inner center of each leg of the frame by the facing edges of the side walls. At a transverse folding line across the strip for making a corner, opposite portions of the side walls are removed each by 90 degree and 45 degree cuts which meet at the longitudinal fold line between the side wall and the narrow longitudinal portion. When the fold is made, the 90 degree and the 45 degree cuts in each wall abut. A hole near each corner is formed by circular notches in the facing edges of the longitudinal slot so that a rod mounting one side of the screen can be held within the leg behind the slot in each of two opposing legs of the frame.
U.S. Pat. No. 5,018,263 patented May 28, 1991 by M. J. Stern describes a continuous thin die cut metal strip which when folded to form a corner of a frame, has the side walls of one leg of the frame epoxy fastened within the adjacent leg of the frame to 45 degree end-cut side walls of the adjacent leg. The side walls are further formed into longitudinal channels extending the length of each leg for receiving screen fabric.


A distinct cultivar of Schefflera arboricola plant named ‘Fan’, characterized by its upright plant habit: rapid growth rate; closely-spaced leaves and parted palmate leaves that are palmately veined, very glossy and dark green which give a dense full appearance.

The new cultivar was discovered by the inventors in a controlled environment in Homestead, Fla. United States in September 2003 as a naturally occurring mutation of Schefflera arboricola. The new cultivar was observed as a single plant in a group of plants of Schefflera arboricola. Compared to plants of Schefflera arboricola, the plants of the new Schefflera are denser having closely-spaced and parted palmate leaves that are palmately veined, very glossy and dark green.
Asexual propagation of the new cultivar by terminal cuttings taken in the controlled environment in Elfin Forest, Calif., United States, has shown that the unique features of this new Schefflera are stable and reproduced true to type in successive generations.
The new Schefflera has not been observed under all possible environmental conditions. The phenotype may vary somewhat with variations in environment such as temperature and light intensity, without, however, any variance in genotype. The following traits have been repeatedly observed and are determined to be the unique characteristics of plants of the new Schefflera. These characteristics in combination distinguish the new Schefflera as a new and distinct cultivar:                1. Upright plant habit.        2. Rapid growth rate.        3. Parted palmate leaves that are palmately veined and closely spaced.        4. Very glossy and dark green leaves.


One aspect of the invention involves a method that includes: in a first area of the touch screen, displaying a current character string being input by a user with the keyboard; in a second area of the touch screen, displaying the current character string or a portion thereof and a suggested replacement for the current character string; replacing the current character string in the first area with the suggested replacement if the user activates a delimiter key on the keyboard; replacing the current character string in the first area with the suggested replacement if the user performs a first gesture on the suggested replacement displayed in the second area; and keeping the current character string in the first area if the user performs a second gesture on the current character string or the portion thereof displayed in the second area.

In recent years, the functional capabilities of portable electronic devices have increased dramatically. Current devices enable communication by voice, text, and still or moving images. Communication by text, such as by email or short message service (SMS), has proven to be quite popular.
However, the size of these portable communication devices also restricts the size of the text input device, such as a physical or virtual keyboard, in the portable device. With a size-restricted keyboard, designers are often forced to make the keys smaller or overload the keys. Both may lead to typing mistakes and thus more backtracking to correct the mistakes. This makes the process of inputting text on the devices inefficient and reduces user satisfaction with such portable devices.
Accordingly, there is a need for more efficient ways of entering text into portable devices.

This patent is subject to a terminal disclaimer.

Method, system, and graphical user interface for providing word recommendations


The present disclosure provides a flexible circuit board, a driving structure and a display device. The flexible circuit board includes: a base plate, including a bonding region and a first routing region between the bonding region and the first edge, touch lines and shielding lines on the base plate and insulated and spaced from each other, and the touch lines includes a first routing portion in the first routing region; wherein the flexible circuit board further includes: a first shielding layer electrically connected to the shielding lines and insulated and spaced from the touch lines, wherein the first shielding layer is in the first routing region and on a side of the first routing portion distal to the base plate, and an orthographic projection of the first shielding layer on the base plate covers an orthographic projection of the first routing portion on the base plate.

At present, a structural design commonly adopted by a touch display panel is to adopt a flexible multilayer on cell (FMLOC) technology. Specifically: a touch electrode layer is disposed on a package substrate of an OLED (Organic Light-Emitting Diode) display panel, thereby performing a touch control without an external touch substrate. The structure has the characteristics of low energy consumption, small screen thickness and the like.

Flexible circuit board, driving structure and display device

Chengdu BOE Optoelectronics Technology Co., Ltd.


A wireless communication device (200) and method (300) customizable power management. The method (300) can include: providing (310) a wireless communication device including an energy storage device; sensing (320) heart rate data of a user; and configuring (330) the wireless communication device's functionality based on the sensed heart rate data. Advantageously, the device (200) and method (300) can provide a real-time attribute of a user, which can be used to configure the functionality of a device and conserve power.

1. Field
The present disclosure relates to a method and device with customizable power management.
2. Introduction
Watch phones have been around for some time and the form factor has not gained much consumer attention. Perhaps that is due to the fact that they are not compelling products, functional and impressive, fail to have highly desirable specifications, applications and functions, and because a user has to hold his or her arm in the air to make a call or use a headset.
However, wearable devices and watch phones do provide use cases, such as minimizing the possibility of leaving ones phone behind, not taking up valuable pocket space, and appearing to be a secret agent when making a call. Wearable devices have excellent use cases, in connection with health, medical and wellness applications requiring twenty four hour connectivity.
There is a need for enabling effective and reliable power management for wireless communication devices, including wearable devices that are smart, portable and can communicate with accessories, such as with sensors configured to monitor users health condition using various technologies or systems, such as a Personal Area Network (PAN), Body Area Network (BAN), Near Field Communication (NFC), BLUETOOTH® or WIFI®, for example.
One of the more important design challenges in wireless communication devices including wearable devices is maximizing battery life and managing power use. Now that "wireless mobility and connectivity" has become a major user expectation, users demand power longevity in such devices. As more and more features, computing power, and memory are packed into wireless communication devices and wearable devices, there is a need for enhanced functionality in such devices, with satisfactory battery life.
There is also need to reduce the amount of power a circuit consumes and techniques to effectively manage the available power using on-device techniques, circuits and sensors.
There is a further need for methods and devices with customizable power management, to better manage power to maintain the usefulness of a device. Thus, there is a need for improving, customizing and managing battery life in electronic devices, such as wireless communication devices, such as cell phones, wearable devices and accessories.
It would be considered an improvement in the art, if a wireless communication method and electronic devices with enhanced power management were developed. There is yet a further need to provide an intelligent method and device adapted to provide personalized and reliable battery management information to a user. Thus, a method and device with intelligent or customized power management that addresses these needs, would be considered an improvement in the art.

Method and device with customizable power management


A method and a system of stitching a plurality of views of a scene, the method including extracting points of interest in each view to include a point set from each of the plurality of image views of the scene, matching the points of interest and reducing an outlier, grouping the matched points of interest in a plurality of groups, determining a similarity transformation with a smallest rotation angle for each grouping of the match points, generating virtual matching points on a non-overlapping area of the plurality of image views, generating virtual matching points on an overlapping area for each of the plurality of image views, and calculating piecewise projective transformations for the plurality of image views.

Field of the Invention
The disclosed invention relates generally to image processing, and more particularly, but not by way of limitation, relating to image stitching and summarizing aerial views.
Description of the Related Art
UAVs (Unmanned Aerial Vehicles) are emerging as de facto imaging method for many applications including defense, surveillance, asset management. Surveillance and reconnaissance tasks are currently often performed using an airborne platform such as a UAV. The airborne platform can carry different sensors. EO/IR cameras can be used to view a certain area from above. To support the task from the sensor analyst, different image processing techniques can be applied on the data, both in real-time or for forensic applications. Effective summarization of view of the multiple cameras on an (unmanned) aerial vehicle is of great importance in such uses. Additionally, a method of stitching images provided by such UAVs is needed.
Stitching images for use in visual analytic business is of great importance. For example, creating a panoramic view from videos of multiple cameras is a critical component for many analytic applications including defense, surveillance, asset management.
Algorithms for aligning and stitching images into seamless photo-mosaics are among the oldest and most widely used in computer vision. One of the most important aspects of image stitching is to seamlessly blend overlapping images, even in the presence of parallax, lens distortion, and scene illumination, to provide a mosaic without any artifacts that looks as natural as possible. Evidently, there is some subjectivity in interpreting how natural a panorama or a mosaic looks. Furthermore, the stitching techniques must be able to extrapolate well to the regions of the panorama where there is information only from a single image.
Therefore, it is desirable to provide an improved way to stitch images and provide image summarization.

System and method for perspective preserving stitching and summarizing views

International Business Machines Corporation


The data signal line driving circuit of the present invention is arranged so that data signal line groups, each of which is made up of two data signal lines sequentially disposed, are connected to two video signal lines, each of which allows a two-phased video signal to be forwarded. A shift register SR, a drive switching circuit, and a waveform shaping circuit, that constitute a video signal fetching section, collect the data signal line groups via the two video signal lines as a single block. At this time, the data signal lines are respectively driven so as to fetch the video signal from the video signal lines into the data signal lines of the data signal line groups in each block. Thus, in performing multiphase development, it is possible to provide the data signal line driving circuit which can reduce power consumption in low resolution driving compared with a case of high resolution driving.

Generally, as shown in FIG. 21, an image display device such as a liquid crystal panel and an organic EL (Electroluminescence) panel includes: data signal lines SL1 to SLx; scanning signal lines GL1 to GLy which cross the data signal lines SL1 to SLx at a right angle; a pixel array PIXARRAY having pixels PIX disposed on intersections of the data signal lines and the scanning signal lines; a data signal line driving circuit SD for driving the data signal lines; a scanning signal line driving circuit GD for driving the scanning signal lines; and a control signal generating section for supplying a control signal to the data signal line driving circuit SD and the scanning signal line driving circuit GD.
The data signal line driving circuit SD, the scanning signal line driving circuit GD, the control signal generating section, and the pixel array PIXARRAY are integrally formed on an insulating substrate made of material such as glass, quartz, and the like. In this case, each of the driving circuits is constituted of a thin film MOS transistor made of poysilicon (hereinafter, referred to as a polysilicon TFT).
Incidentally, a driving circuit using a polysilicon TFT has such disadvantage that its operation speed is much slower than that of a driving circuit using a monocrystal silicon TFT. Particularly, in a case of realizing large-screen and large-volumetric display by using the data signal line driving circuit for driving the data signal lines, a shift resister which constitutes the data signal line driving circuit operates too slowly. Thus, various methods are studied to drive the data signal line within the operation speed of the shift resister constituted of the polysilicon TFT.
For example, there is proposed the following multiphase development technique: in the data signal line driving circuit, a plurality of video signal lines are provided, and a multiphased video signal DAT is inputted to the video signal lines, and the video signal inputted to one video signal and the video signal inputted to another video signal line are simultaneously outputted from the data signal lines connected to the video signal lines, thereby dropping a frequency of the shift resister as the video signal is further multiphased.
FIG. 22 is a block diagram schematically showing the data signal line driving circuit in a case where a video signal is two-phased. In this example, the video signal DAT is divided into two video signals: a video signal DAT1 and a video signal DAT2, and the video signals DAT1 and DAT2 are outputted from the data signal lines via the respective video signal lines. In this case, as shown in FIG. 23, two data signal lines SL are driven at the same timing by a single shift resister SR and a single waveform shaping circuit SMP (see a timing chart shown in FIG. 24).
Note that, FIG. 22 illustrates (i) two video signal lines and (ii) a single shift resister corresponding to the two video signal lines, so as to simplify the illustration, but a technique, based on the same technical idea, which has eight video signal lines and four shift resisters corresponding to the four video signal lines, is disclosed in Patent Document 1 (U.S. Pat. No. 6,219,023 B1) for example.
As described above, when the data signal line driving circuit is driven in accordance with two-phase development, it is possible to slow an operation speed (frequency) of a shift resister constituting the data signal line driving circuit.
Note that, FIG. 24 is a timing chart showing a case where it is assumed that resolution of the pixel PIXARRAY which functions as a display section is the same as resolution of the inputted video signal.
However, in the foregoing display device, it is required that the resolution of the display section is the same as the resolution of the video signal, and it is also required to input the video signal whose resolution is less than the resolution of the display section so as to display an image. For example, in order to display an image appropriately in inputting the video signal whose resolution is half of the resolution of the display section, the data signal line driving circuit is operated in accordance with the timing chart shown in FIG. 25. That is, by causing two data signal lines to output the same video signal, it is possible to display the video signal whose resolution is half of the resolution of the display section. Note that, at this time, also in the scanning line driving circuit, every two scanning signal lines are driven.
Incidentally, in a conventional data signal line driving circuit which performs multiphase development, the data signal lines adjacent to each other are respectively connected to the video signal lines different from each other. For example, in a case of a data signal line driving circuit shown in FIG. 22, two data signal lines adjacent to each other are respectively connected to the video signal lines DAT1 and DAT2. Moreover, the two data signal lines adjacent to each other are connected to the same shift resister SR via the same waveform shaping circuit SMP.
Thus, when displaying the video signal whose resolution is the same as the resolution of the display section (high resolution driving), as shown in FIG. 24, the video signals from the two video signal lines are outputted to the data signal line in synchronism with a timing pulse from the shift resister, so that the development is performed in accordance with two-phase development. Thus, it is possible to make the frequency of the shift resister half of the frequency in the case where the phase development is not performed while keeping the frequency of the video signal as it is. As a result, it is possible to obtain such advantage that power consumption of the data signal line driving circuit can be reduced compared with the case where the phase development is not performed.
However, when displaying the video signal whose resolution is lower than the resolution of the display section (low resolution driving), as shown in FIG. 25, the same video signal is supplied to the data signal lines adjacent to each other, so that it is necessary to supply the same video signal to the two video signal lines. Thus, in performing the low resolution driving, the phase development is not performed unlike the high resolution driving.
In this manner, when the low resolution driving is performed, as described above, it is necessary to supply the same data to the two video signal lines, so that the frequency of the shift resister of the data signal line driving circuit shown in FIG. 22 is the same as the frequency in the case where the high resolution driving is performed, but the frequency of the video signal supplied from the video signal line is also the same as the frequency in the case where the high resolution driving is performed. As a result, the power consumption etc. in the data signal line driving circuit is equal to the power consumption etc. in the case where the high resolution driving is performed. As a result, the power consumption of the data signal line driving circuit in performing the low resolution driving is equal to the power consumption of the data signal line driving circuit in performing the high resolution driving.
Thus, in the conventional data signal line driving circuit which performs the multiphase development, the power consumption etc. in the case where the high resolution driving is equal to the power consumption etc. in the case where the low resolution driving is performed, so that this raises such problem that the power consumption is not reduced even when the resolution is lowered.

Data signal line driving method, data signal line driving circuit, and display device using the same


An angle-of-rotation sensor comprises a coil, a magnetically conductive element within the coil which is rotatable around an axis of rotation, the axis of rotation of the magnetically conductive element being at least partially within the coil, and a single winding for the coil. The angle-of-rotation of the magnetically conductive element is determined by measuring the change in self-inductance in the coil when the magnetically conductive element is caused to rotate.

The instant invention relates to an inductive angle-of-rotation sensor in which a rotatable magnetically conductive element is positioned within a coil body.
An angle-of-rotation sensor of this type is known from DE 43 35 594 A1 (U.S. Pat. No. 5,455,508).
This known angle-of-rotation sensor operates on the principle that a variation takes place in the ratio of the inductances of two windings which are wound on a coil body as a result of rotation of a magnetic conductive element mounted rotatably within the coil body. An arrangement of this type can thus be compared to a transformer with a variable degree of coupling.
In order to produce a signal characterizing the angle of rotation, a.c. voltage is fed into the first coil winding in this known angle-of-rotation sensor. This a.c. voltage induces a certain output voltage in the second coil winding which is a function of the inductance ratio of the two coil windings, and also a function of the angular position of the magnetic conductive element. The ratio between the amplitude of this output voltage and the amplitude of the input voltage fed into the first coil winding therefore represents a measure of the sensed angle of rotation of the magnetic conductive element.
The disadvantage of this principle of operation is that in order to operate the angle-of-rotation sensor, a high-frequency a.c. voltage signal is required, the form of which is sinusoidal. However, sensors of this type are normally used in combination with electronic systems carrying out the evaluation of the sensor signals. Such, electronic systems are at this time almost always based on digital technology. Since these systems usually are also equipped with a microprocessor for the control of other functions in addition to the evaluation of signals from a sensor, it is desirable to operate sensors of such systems with signals that are commonly used in digital electronic systems having microprocessors. A sinusoidal a.c. voltage is not such a signal.
Operation of the known angle-of-rotation sensor with a rectangular a.c. voltage signal normally used in digital technology would have the disadvantage that the harmonics accompanying such a signal may cause undesirable and sometimes unexpected resonance effects which could result in a deterioration of the electronic system with respect to its electromagnetic compatibility with other electronic systems.
Another disadvantage of the operating principle of the known angle-of-rotation sensor is the fact that the output signal carried in the second coil winding is also an a.c. voltage signal. Since it is necessary for the sensing of the angle-of-rotation sensor to measure the amplitude of the output signal, it is necessary in a digital electronic system to transform this output signal by means of a rectifier, and possibly by means of an amplifier as well, into a d.c. voltage signal of suitable magnitude. In this case, the d.c. voltage signal must be of a magnitude which can be processed by an analog/digital converter. Electronic circuit components such as rectifiers, amplifiers and analog/digital converters are expensive components and should therefore be avoided, if possible.
In addition to the above-mentioned disadvantages, the known angle-of-rotation sensor has the additional disadvantage that because two coil windings are employed, at least three but usually even four electrical connections are necessary. A suitable plug-in connector for the connection of such an angle-of-rotation sensor requires therefore at least three and possibly even four electrical contacts. For many applications, however, it is advantageous to use sensors with as few electrical connections as possible.
It is therefore the object of the present invention to provide an inductive angle-of-rotation sensor in a simplified form, with as few electrical connections as possible, which could furthermore be used in a digital electronic system, preferably, in a digital electronic system which includes a microprocessor, and without using analog circuit means.
Analog circuit means are understood in this context to be electronic circuit means suited exclusively or especially for the processing of analog signals, and includes, e.g., rectifier, analog/digital converter, analog amplifier, sinoid generator, etc.

Inductive angle-of-rotation sensor having rotatable magnetically conductive element within single winding coil


A method is shown to provide remote access to one or more debug access points whose functions include capabilities other than accessing memories across an application interface such as USB, IEEE 802.3 (Ethernet) and other protocols. The capabilities available include all or many of the capabilities provided by a dedicated debug interface.

Current state of the art debug of general purpose processors takes two forms:
1. A lesser set of visibility and control provided through an application interface.
2. A wide range of visibility and control provided with a dedicated debug interface.
In both of the above cases the debug control function provides a means to access debug features on-chip that support visibility into the current state of the processor(s) and even historical information about the state of an application. Some examples of this include: writing/reading system memory, viewing the contents of caches, controlling the execution of application programs, setting/clearing breakpoints, etc.

Pseudo dedicated debug port with an application interface


An isotropic, biaxially stretched polyimide film prepared by casting a solution of a polyamic acid precursor in an organic solvent containing a cyclization catalyst and dehydrating agent onto the surface of a support, imidizing the polyamic acid to give a continuous self-supporting gel film containing 5-50% by weight of solids, stretching the gel film in the machine direction (MD) at a ratio of 1.1-1.9, and stretching in the transverse direction (TD) with respect to the machine direction so as to maintain a TD/MD stretch ratio of from 0.9 to 1.3.

The present invention relates to a polyimide film for use as a support for electrical circuit boards to which a metal layer is either laminated or deposited and to a process for the manufacture thereof. Specifically, it relates to a biaxially stretched polyimide film having excellent dynamic properties and in-plane isotropy, as well as improved dimensional stability, and a process for the manufacture thereof.
Due to its high heat resistance and good electrical insulation properties, polyimide film can be used as an electrical insulation material in a broad range of industrial applications which require heat resistance. More particularly, polyimide film can be used as a support for an electrical circuit board to which a metal layer is subsequently laminated or deposited and wherein an electrical part, such as an IC chip, can be soldered to the metal layer, thereby miniaturizing the electrical wiring. An electrical circuit board having a polyimide film support can also be folded to form a long continuous electrical circuit board to such an extent that polyimide film has come to occupy an important position as a support for electrical insulation applications. However, due to the diversification in the applications of electrical circuit boards and the increased density in the number of wirings, the polyimide film requires improvements in dynamic properties, in-plane isotropy, and dimensional stability for use as an electrical insulation support. In order to meet these requirements prior art proposals have been made based on improving physical properties of the polyimide film by stretching or by improving dimensional stability by the use of a copolyimide, or the like.
For example, Japanese Patent Application Publication Kokai 63-297029, discloses a process for improving the dynamic properties of an aromatic polyimide shaped article, comprising cyclizing and imidizing a solution of an aromatic polyamic acid in an organic polar solvent containing an imidization agent, shaping to give a self-supporting shaped article containing 20-87% by weight of volatile solvent and stretching the shaped article at a stretch ratio of at least 1.3 and heat-treating the stretched article at a temperature of at least 150.degree. C. The prior art process improves dimensional stability in the stretching direction, but it adversely affects not only the dimensional stability in the direction perpendicular to the stretching direction, but also the dynamic property of in-plane anisotropy.
Japanese Patent Application Publication Kokai 44-20878, discloses stretching a polyamic acid-imide gel film wherein the ratio of imide units to polyamic acid precursor units is at least 30:70 undirectionally at 20.degree.-550.degree. C. by at least 5%. However, the prior art reference fails to disclose how to reduce in-plane anisotropy of the film.
U.S. Pat. No. 3,619,461, issued on Nov. 9, 1971, discloses a process for preparing a polyimide film by immersing a film having a volatiles content of from 10 to 15% in a volatile liquid and heating and stretching the treated film to increase the orientation in at least one direction. In the invention process, the polyimide film is not immersed in a volatile liquid prior to stretching.
Japanese Patent Application Publication Kokai 64-16833, Kokai 64-16834, Kokai 1-131241 and Kokai 62-125329, and many similar proposals, disclose the use of special copolyimides for improving the dimensional stability of polyimide films. However, these disclosures fail to disclose a way to reduce in-plane anisotropy of the polyimide film.
The object of the present invention is to provide a polyimide film having improved dimensional stability and dynamic properties and excellent in-plane isotropy, and to a process for preparing said film.

Process for preparing biaxially stretched isotropic polyimide film


A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.

1. Field of the Invention
The invention relates generally to a nonvolatile semiconductor memory device. More particularly, the invention relates to a nonvolatile semiconductor memory device constructed with bitlines extending from a cell array in a single direction.
A claim of priority is made to Korean Patent Application No. 2005-81553, filed on Sep. 2, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A conventional nonvolatile semiconductor memory device comprises a plurality of memory cells arranged in a cell array, and various peripheral circuits adapted to control the transfer of data to and from the cell array. The memory cells in the cell array are connected to a plurality of corresponding bitlines used to transfer data to and from the memory cells. Each of the bitlines can be individually controlled by either charging it to a power source voltage or discharging it to ground using a voltage control block.
FIGS. 1 and 2 are circuit and layout diagrams showing interconnections between bitlines and voltage control blocks in a conventional nonvolatile semiconductor memory device.
Referring to FIGS. 1 and 2, the conventional nonvolatile semiconductor memory device comprises a cell array 10, a lower voltage control block 20, and an upper voltage control block 30.
Cell array 10 contains a plurality of bitlines extending up and down. In particular, cell array 10 comprises four bitlines BL1, BL2, BL5, and BL6 extending down into lower voltage control block 20, and four bitlines BL3, BL4, BL7, and BL8 extending up into upper voltage control block 30. Bitlines BL1 through BL8 are formed in respective bit layers BMT connected to voltage control blocks 20 and 30. In the conventional nonvolatile semiconductor memory device shown in FIGS. 1 and 2, pairs of adjacent bitlines extending in the same direction are coupled to respective latch blocks 41, 42, 43, or 44.
FIGS. 3 and 4 show respective layout patterns for voltage control blocks 20 and 30. In FIGS. 3 and 4, power source voltage lines 21, 25, 31, and 35 are connected to a power source supplying a power source voltage VDD, and ground voltage lines 23, 27, 33, and 37 are connected to ground. Power source voltage lines 21, 25, 31, and 35, and ground voltage lines 23, 27, 33, and 37 are formed in a metal layer MET, which is formed after bit layers BMT.
Power source voltage lines, 21, 25, 31, and 35, and ground voltage lines, 23, 27, 33, and 37, are connected to source/drain junctions of respective pre-charging and discharging transistors TD and TS through respective bit layers (BMT) 26 and 28 (See, FIGS. 1 and 5). Thus, when bitlines BL1 through BL8 extend toward a single side of cell array 10, half of bitlines BL1 through BL8 intersect bit layers, 26 and 28, which are respectively connected to power source voltage VDD and ground VSS. Accordingly, bitlines BL1 through BL8 are generally divided in half between lower and upper voltage control blocks 20 and 30.
In the conventional nonvolatile semiconductor memory device employing lower and upper control blocks 20 and 30, the timing of data passing through lower and upper control blocks 20 and 30 can be skewed due to slight differences in the lengths of data buses carrying the data. The data skew tends to complicate the design of control circuits used to operate the semiconductor memory device.
Furthermore, by having bitlines extending in more than one direction away from the cell array, the size of the memory device is significantly increased.

Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction


In one embodiment, an ultrasonic diagnostic apparatus includes a plurality of transmission-wave generation circuits configured to supply a plurality of transducers of an ultrasonic probe with a plurality of transmission waves for driving the plurality of transducers via a plurality of channels; and a transmission control circuit configured to independently and dynamically control each of the plurality of transmission-wave generation circuits at a timing different for each channel.

An ultrasonic diagnostic apparatus is configured to non-invasively acquire information inside an object by transmitting an ultrasonic pulse and/or an ultrasonic continuous wave generated by transducers included in an ultrasonic probe to an object's body, receiving a ultrasonic wave reflected due to difference in acoustic impedance between respective tissues in the object, and converting the reflected ultrasonic wave into an electric signal using the transducers.
In an ultrasonic examination using an ultrasonic diagnostic apparatus, various types of moving image data and/or real-time image data can be easily acquired by scanning an object such that an ultrasonic probe is brought into contact with a body surface of the object. Thus, an ultrasonic diagnostic apparatus is widely used for morphological diagnosis and functional diagnosis of an organ.
The number of transducers included in an ultrasonic probe tends to increase, although depending on a type of ultrasonic probe. In recent years, a two-dimensional array probe in which transducers are two-dimensionally arranged has been developed for acquiring three-dimensional data. A two-dimensional array probe has more transducers than a one-dimensional array probe.
The larger number of transducers of an ultrasonic probe becomes, the larger size of a transmission circuit configured to supply power to the respective transducers becomes, which increases power consumption of the transmission circuit. Additionally, a control signal and a clock signal are used in a transmission circuit for generating transmission waves. With an increase in number of transducers, a size of a circuit for distributing the control signal and the clock signal increases as well, and thus, noise caused by the control signal and the clock signal has also increased.


To provide a method for assaying soluble LR11 in a biological sample, which method realizes a simple and accurate assay of soluble LR11 present in the sample by immunological means without requiring isolation of soluble LR11 from the biological sample (e.g., a serum sample).

LDL receptor relative with 11 ligand-binding repeats (LR11) is an LDL receptor-like protein having a structure characteristic to the LDL receptor family and a molecular weight of about 250 kD (Patent Document 1, Non-Patent Document 1). In addition to membrane-bound type LR11, soluble LR11, a segment cleaved by protease is known as LR11 (Non-Patent Document 4). It is reported that little or no expression of LR11 was observed in normal vascular wall cells, but expression thereof was observed specifically in thickened intima smooth muscle cells (Non-Patent Document 2). Moreover, it is reported that expression of LR11 was promoted in response to proliferation of cultured smooth muscle cells, leading to secretion of soluble LR11 to the culture liquid, and that thickening of vascular intima, which would be caused by migration and proliferation of smooth muscle cells, is inhibited in a cuff injury mouse model by functionally impairing LR11 gene in the mouse by developmental engineering (Non-Patent Document 3). Furthermore, the present inventors previously found that the blood soluble LR11 levels of arteriosclerosis patients are significantly higher than those of healthy subjects, and reported that the blood soluble LR11 could be used as a new marker for arteriosclerosis (Non-Patent Document 5, Patent Document 2).
Hitherto, there is a known method for determining soluble LR11 through separating soluble LR11 from a sample by use of an insoluble carrier to which a chaperone molecule, a receptor associated protein (RAP) having affinity to LR11, has been bound, followed by performing SDS-PAGE and Western blotting to detect LR11 through immunostaining by use of an anti-LR11 antibody (Non-Patent Documents 5, 6). However, since the known method includes cumbersome steps such as separation of soluble LR11 from a sample, the method is not practical for application to clinical tests or the like.
The present inventors previously tried to establish an immunological assay method employing an anti-soluble LR11 antibody, as a simple and practical soluble LR11 determination method. However, when a biological sample such as a serum sample was analyzed, an unidentified interfering substance present in the biological sample (hereinafter may be referred to simply as an "interfering substance") was found to interfere with correct determination of soluble LR11.
Therefore, the present inventors extensively studied on means for eliminating the effects of interfering substances on the immunological assay method. As a result, the inventors found that, when a biological sample such as a serum sample is mixed with a specific surfactant such as N-acyl-N-methylglucamine, and the thus-treated sample is subjected to an immunological assay, soluble LR11 present in the sample can be correctly determined in a simple manner while eliminating the effects of interfering substances, and the inventors previously filed a patent application (Patent Document 3).

Method for immunologically measuring soluble LR11

Abstract: The method of the invention for immunologically assaying soluble LR11 present in a biological sample, characterized in that the method includes treating the sample with at least one surfactant selected from among one or more sulfobetaine amphoteric surfactants and one or more amidosulfobetaine amphoteric surfactants.


An antenna which is advantageous for low frequency communications and suitable for use in a portable electronic device comprises an antenna resonator element and a grounding line. The resonator element is configured to resonate at a frequency f, and comprises a first port and a second port that are configured to be differentially fed. The grounding line couples a virtual node of the resonator element to ground, where the virtual node defines a negligible current when the resonator element is resonant at the frequency f. In the specific examples the antenna could be a folded monopole, a folded dipole, a loop, or other type of differential antennas. Radiation efficiency is quantified for a long folded monopole implementation which shows a marked improvement over an identical antenna without such a grounding line, particularly when used with a radio receiver.

This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
In a field of antenna technology a low frequency differential antenna has been difficult to realize in practice. For low frequency single ended (unbalanced) antennas, the ground plane is the main radiator and currents are induced in it by the antenna wire which acts as an excitation element, so below 1 GHz the size of the ground plane has a large effect on performance of an unbalanced antenna. But in an idealized low frequency differential (balanced) antenna the current flows only in the wire/resonating element and not in the ground plane so the size of the radiating element becomes more important to the antenna performance. For a truly balanced 900 MHz antenna the radiating element would be quite large. Because modern consumer electronics such as mobile terminals are very constrained in size, there is a desire to find an alternative arrangement for a balanced antenna that has efficient performance in both the low and high frequency bands and which is small enough to integrate effectively with other close-packed electronics within a handheld device.
As radio spectrum becomes more scarce and the ability to pack multiple radios into a single handset continues to improve, the need for low frequency communications using a mobile user device is growing. Low frequencies in this context refers to frequencies below about 1000 MHz. While different regions and countries define their radio spectrum differently, in some areas the 900 MHz band is in the Industrial/Scientific/Medical ISM band or television whitespace TV WS bands (and thus is license-exempt spectrum), in others it was once used for the Global System for Mobile Communications GSM radio access technology, and it is also the band used by the ZigBee radio access technology. Generally low frequency refers to the lower half of the UHF band, roughly about 200 MHz to about 1000 MHz.

Low frequency differential mobile antenna


A volume control for in-wall building stereo systems. Specifically, there is a sliding switch coupled between a mounting bracket and a printed circuit board that has components mounted thereon including two multi-tap inductors or transformers. The in-wall mounted speaker volume control slide selector switch assembly. Specifically, the assembly has a sliding selector switch, for housing electrical components, having a shaft extending from the sliding selector switch, for sliding in a linear direction to control volume of the in-wall mounted speaker. Additionally, there is a transformer, for supplying power to the in-wall mounted speaker, having a plurality of transformer taps. Further, there is a printed circuit board, for electrically connecting and physically mounting the transformers and the sliding selector switch thereto. Also, there is a mounting bracket, for supporting the printed circuit board and the transformer and sliding selector switch. The mounting bracket has a slot, for receiving the shaft during linear actuation, and a mounting tab, for attaching the mounting bracket to the printed circuit board. Finally, there are a plurality of selector switch pin lead holes mounted in the printed circuit board for electrically and mechanically connecting pins from the transformer and sliding selector switch.

1. Field of the Preferred Embodiment(S)
This invention generally relates to volume controls for in-wall building stereo systems. Specifically, there is a sliding switch coupled between a mounting bracket and a printed circuit board that has components mounted thereon including two multi-tap inductors or transformers.
2. Description of the Related Art
Various devices are well known for controlling the volume of speakers located in walls of buildings. The controls are typically mounted behind a control panel or a multi-gang control panel, or individual stand along volume control switch.
Examples of patents related to the present invention are as follows, wherein each patent is herein incorporated by reference for related and supporting teachings:
U.S. Pat. No. 5,191,971, is a multi-position wall mountable control switch with tactile feedback linear actuator.
U.S. Pat. No. 4,710,600, is a detent mechanism for sliding electric parts.
U.S. Pat. No. 4,668,849, is a detent mechanism for sliding electric parts.
U.S. Pat. No. 4,491,703, is a detenting and contact registration system for a linear DIP switch.
U.S. Pat. No. 3,781,866, is a binary encoding switch.
U.S. Pat. No. 3,632,909, is a slide selector matrix keyboard switch assembly with improved contact structure.
U.S. Pat. No. 3,461,252 is a multiposition slide switch.
The foregoing patents reflect the state of the art of which the applicant is aware and are tendered with the view toward discharging applicants' acknowledged duty of candor in disclosing information that may be pertinent in the examination of this application. It is respectfully stipulated, however, that none of these patents teach or render obvious, singly or when considered in combination, applicants' claimed invention.

Slide actuated audio volume control assembly


A road surface inspection device detects an abnormal region on a road surface from the road surface on a road image captured by a camera. The road surface inspection device determines whether the detected abnormal region overlaps a trace on the road image, along which the wheels of a patrol car are expected to pass on the road surface. When the abnormal region overlaps the trace of wheels, the road surface inspection device determines whether an acceleration at the measurement time corresponding to the captured time of the road image among the accelerations measured during driving on the road surface by a G-sensor is outside a predetermined range.

The surface of a road is deteriorated by a vehicle traffic load and the action of a natural environment. Thus, a special vehicle such as a road surface state measurement vehicle drives on a road to periodically inspect the state of a pavement on the road. As a result of the inspection, when a bump, a groove, or a crack is detected on the road surface of a road, repair of the road is performed.    Patent Literature 1: Japanese Laid-open Patent Publication No. 2001-134889
However, in the related art, there is a problem in that it is difficult to detect the deterioration of the road surface at an early stage.
That is, since the road surface state measurement vehicle is expensive and rare, it is difficult to perform the inspection of the road surface frequently. Thus, when the road surface is inspected using the road surface state measurement vehicle, it is difficult to detect the deterioration of the road surface at an early stage. As a result, detection of the deterioration of the road surface is delayed, and the cost for repair increases.

Road surface inspection device, road surface inspection method and recording medium


A clamping device for clamping mold boards together includes a base, a bracket extended upward from the base, a space and a chamber formed in the bracket, a lever pivotally coupled between the wall members and having a number of teeth formed on the lower end. A cover is engaged on the bracket for covering the bracket and includes a slit formed in the upper surface for engagement with the lever.

1. Field of the Invention
The present invention relates to a clamping device, and more particularly to a clamping device for clamping mold boards together.
2. Description of the Prior Art
A typical clamping device for mold boards is disclosed in FIG. 4 and comprises a base 11 having a hole 111 formed in the middle portion and having a bracket 12 extended upward therefrom, the bracket 12 includes a space 13 formed between a pair of wall members 15, and a chamber 14 communicated with the space 13 and connected with the hole 111, a bolt for coupling mold boards may extend into the chamber 14 via the hole 111 and to be fixed in place, a lever 16 includes a lower end pivotally coupled between the wall members 15 and a plurality of teeth 17 located in the chamber 14 for engaging with the bolt so as to lock the bolt in place, and a spring 18 for biasing the lever 16, whereby, the mold boards can be solidly fixed together. However, the upper portion of the wall members 15 is exposed such that water or dust, particularly the mud, slurry or concrete such that the parts of the clamping device are apt to be rusted, and such that the working life of the clamping device is short.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional clamping devices for mold boards.


Fabrication of a termination structure in a semiconductor device increases in some cases the numbers of ion implantation processes or of photolithography processes, thus leading to an increase in fabrication costs. To overcome this problem, a semiconductor device is provided which includes an n-type drift layer formed on a semiconductor substrate; an element region formed in a surface portion of the drift layer; a recess formed in a loop in a laterally outer portion of the drift layer, spaced away a predetermined distance from the element region; and a p-type dopant region formed ranging from a bottom of the recess to a position away from the recess and toward the element region, a thickness of the dopant region where no recess is provided being greater than that where the recess is provided.

A silicon carbide (SiC) power semiconductor device is known as a device having excellent temperature and breakdown voltage characteristics. An electric field relaxation structure, which is called termination structure, is provided to a laterally outer edge of an active region of the power semiconductor device.
Known as a termination structure of the Schottky diode element—a kind of the power semiconductor device—is, for example, a junction termination extension (JTE) structure in which a region of conductivity different from that of a semiconductor region in the lower center of a Schottky electrode is provided in the semiconductor region of a perimeter of the Schottky electrode, and a dopant concentration in the termination structure is gradually reduced toward a circumference of the element (a literature such as Patent Document 1). Another structure is also known in which, in addition to a planar direction of the device, regions having plural dopant concentrations are provided also in a depth direction thereof, and a dopant sheet density of a termination structure is gradually reduced toward a circumference of the element (a literature such as Patent Document 2).
In order to form such a structure where the dopant concentration and the dopant sheet density are varied gradually, additional doping process such as ion implantation or epitaxial growth is performed. For that reason, the number of fabrication processes required for forming the structure having the dopant profile gradually varied needs to be undergone, resulting in some cases in an increase in the fabrication process. The increase in fabrication process leads to an increase in fabrication costs.
On the other hand, in a method of fabricating semiconductors, some attempts are known which form plural regions that are different in dopant concentration from each other, without increasing the number of photolithography processes. Among the known examples are: a method where when implanting ions into a semiconductor layer using a mask, the ion implantation is performed in a predetermined mask shape and with a predetermined density and thereafter by reducing the mask size and causing the mask to move backward, the ion implantation is performed with another density (Patent Document 3 and the like); a method where, by providing a portion where the ion implantation is performed through a film that partially passes ions therethrough, a region where the ion implantation is performed without passing through the film that partially passes the ions therethrough, and another region where a dopant concentration distribution varies in a depth direction, are formed simultaneously (a literature such as Patent Document 4); and a method where a stepped surface or a slanted cross-sectional shaped portion is provided to a mask, and dopants are ion implanted through this mask and thereafter the dopants are thermally diffused (a literature such as Patent Document 5).
Also known is an alignment mark having a slanted structure with a double stepped bottom (Patent Document 6, for example).

Semiconductor device and method of fabricating same


A method and arrangement for enforced heat transmission between a solid or liquid alimentary body and an ambient gas takes place in connection with cooling/freezing or when cooking, frying or drying the entire part or parts of the alimentary body. This method and arrangement uses a low-frequency standing sound wave. The apparatus uses a low-frequency sound generator having a pulsator part and a resonator part. The resonator part is acoustically virtually closed and is designed so that the alimentary body, which is to be exposed to enforced heat transmission, is located within a zone inside the resonator part where the standing sound wave has a particle velocity anti-node.

A fundamental problem in cooling/freezing alimentary bodies, i.e. products intended as food for human beings or animal fodder, is that the transferred thermal effect per surface unit from the alimentary body to a gas flow enveloping the alimentary body will be low at low gas flow rates. In order to transfer large thermal effects, high gas flow rates are required, which implies that a large air flow will be necessary. At the same time, however, the temperature rise in the air will be slight. The large flow entails that cooling/freezing will be expensive and, in consequence of the slight temperature rise, the energy in the heated air can seldom be utilized.
Depending on, among other things, the feeding temperature of the alimentary bodies, their consistency, thickness etc., variations in transit time must be foreseen in order to achieve the desired outlet temperature of the alimentary bodies. The transmit time, i.e. the time during which the alimentary bodies are present in the cooling/freezing chamber, is generally controlled by the feed rate of the product flow, so that a low feed rate result in a longer transmit time than a high feed rate would.
It is previously known from V. B. Repin, "Heat exchange of a cylinder with low-frequency oscillations", Zhurnal Prikladnoi Mehaniki i Tekhnicheskoi, No. 5, pp. 67-72, September-October 1981, that heat transmission may be improved by generating a sonic field in the liquid. It is also previously known that it is advantageous if such a sonic field is of low frequency.
It will be obvious from the two parameters sound pressure and particle velocity in a sonic field that it is the particle velocity which provides the enforced heat transmission. It is also obvious that the heat transmission increases with increasing particle velocities. The reason why the prior-art method of employing low-frequency sound for heating or cooling of bodies has not hitherto enjoyed any practical importance is that there have not been any usable method or apparatus for generating sound with a sufficiently high particle velocity throughout the entire surface of the body intended to be cooled, or alternatively, heated.

Method and arrangement for an enforced heat transmission between alimentary bodies and gases