An end-effector that loads disks into a pallet of a sputtering machine, for example, has a two-piece mandrel with a rigid inner core and a plastic outer sleeve slideably axially mounted on the core. The sleeve is attached to the core with a coupling providing a predetermined attachment force. A breakaway force exerted on the sleeve that exceeds the attachment force causes the sleeve to separate from the mandrel, this separation being sensed by a breakaway sensor.

Hard disk drives provide fast non-volatile, rewritable and economical computer memory. Most disk media, such as magnetic hard disks, magneto-optical disks and phase-change optical disks, involve codings by various deposition techniques such as sputtering or chemical deposition. One of the types of sputtering machines for sputter-deposition of a succession of various layers onto the disk surfaces to produce the memory media is an in-line (or "pass-through") machine. Such a machine includes either a linear arrangement of relatively small, individual but connected chambers, or one or two long chambers with vacuum transition locks at each end of the line. Processing stations are located either along the long chambers or in each individual chamber. During deposition, a multiple-disk substrate carrier, called a pallet, continuously passes in front of the sputtering targets or sources.
In high-speed operations, load robots are employed to transfer disk media from a presentation location to load the disks into a transfer pallet. Using the end-effector, the robot picks a group or series of axially aligned disks from the presentation location, and places the disks one at a time into the pallet.
A previous design of a robotic end-effector used by load robots to transfer disk media employs two opposing mandrels mounted to a central hub. The mandrel is a one-piece cantilever design constructed from "PEEK" plastic, and has thirteen slots for holding disks. In operation, the robot inserts the mandrel into the center of the axially aligned disks at the presentation location, removes them from the presentation location, and subsequently places the disks one at a time into the transfer pallet. There are certain concerns related to the conventional device, caused by the one-piece mandrel design made of plastic. These concerns include quality, throughput and line yield loss.
Scratches and dings in a disk may be caused by inaccurate placement of the disk in the pallet by the robot, affecting the quality of the disk. Dimensional instability of the plastic material of the one-piece mandrel, as well as the flexure of the mandrel, may be a major factor in the accuracy of the placement of disks into the pallet. Another quality factor is the ability to track the disk products through the factory. For example, a product may be tracked in lots of twenty-five disks. Using a mandrel having a different number of slots than the disk lot size causes the lots to be broken up and disordered during a transfer process. This makes product tracking more difficult and prone to errors.
Another concern with conventional design relates to the throughput. Using a thirteen-slot mandrel design, the robot may frequently run out of disks while loading a pallet. The robot must then take time out from the loading to resupply itself with disks, causing a reduction in throughput. Another throughput factor is the relatively limited payload that can be carried by the one-piece plastic design, due to the flexure of the plastic mandrel under load. As such, the plastic design of the mandrel may not work well with next generation media form-factors, which are expected to be heavier. Another throughput issue is that periodic maintenance is difficult and time consuming, causing lost production while a technician replaces and recalibrates the one-piece plastic mandrels.
A still further concern regards line yield loss. Over time, placement accuracy of a disk into the pallet can degrade to the point where disks are misloaded in the pallet. The degrading of the placement accuracy may be due to the one-piece plastic design of the mandrel. The disks will either fall out onto the ground, or fall back into the mandrel and have to be removed. In either event, the disks become scrap. Further, in the event of a severe misload of a disk into the pallet, the disk can get lodged such that the robot rips the disk out of the pallet, resulting in damage to the pallet, the mandrel, and any previously placed disks. Also, error recovery from misloads has a significant impact on line yield loss.

Breakaway mandrel for transporting disks


Automated techniques ensure that system central processing unit (“CPU”) power is not a bottleneck when migrating logical partitions from one system to another system or systems (e.g., in the event of a system evacuation). CPU resources needed to fully drive available bandwidth during the migration are computed. CPU resources of the system are then adjusted for the migration, which may comprise scaling down the CPU resources that are guaranteed for the executing partitions and/or adjusting relative partition variable weights to limit the amount of excess capacity that can be allocated to a partition.

The present invention relates to computer programming, and deals more particularly with automated techniques for ensuring that system central processing unit ("CPU") power is not a bottleneck when migrating logical partitions from one system to another system or systems (e.g., in the event of a system evacuation).
The term "logical partitioning" refers to the ability to make a server run as if it were two or more independent servers. When a server is logically partitioned, the resources on the server are divided into subsets called logical partitions. Processors, memory, and input/output ("I/O") devices are examples of resources that can be assigned to logical partitions. A logical partition runs as an independent logical server with the processor, memory, and I/O resources allocated to it. Examples of software that can be installed and run on logical partitions include the AIX®, i5/OS™, and Linux® operating systems and Virtual I/O Server ("VIOS") software. ("AIX" is a registered trademark, and "i5/OS" is a trademark, of International Business Machines Corporation in the United States, other countries, or both. "Linux" is a registered trademark of Linus Torvalds in the United States, other countries, or both.)

System and program product to allocate and reallocate CPU resources needed to utilize full available network adapter bandwidth capacity for logical partition migration

INTERNATIONAL BUSINESS MACHINES CORPORATION


A lighting fixture includes first and second elongated lamp carriage assembles supporting respective first and second elongated lamps and an enclosure including first and second spaced plates. The first lamp carriage assembly is fixedly coupled between the first and second plates for directing light output by the first lamp in a first direction. The second lamp carriage assembly is slidably and pivotally coupled at its ends to the first and second plates for directing light output by the second lamp in a second direction that crosses the first direction. The lighting fixture can further include a third elongated lamp carriage assembly supporting a third elongated lamp. The third lamp carriage assembly is slidably and pivotally coupled at its ends to the first and second plates for directing light output by the third lamp in a third direction that crosses the first and second directions.

1. Field of the Invention
The present invention relates to lighting fixtures for plaster/drywall ceiling and drop ceilings, and, more particularly, to lighting fixtures that include fixed direction lighting and directionally adjustable lighting.
2. Description of Related Art
Dropped ceilings are well known in the art as secondary ceilings that are hung below a main (structural) ceiling. Dropped ceilings are also referred to as a drop ceiling, false ceiling, or suspended ceiling, and are utilized widely in modem construction and architecture.
It is well known in the art for dropped ceilings to include one or more lighting fixtures that are supported by the grid-work of the dropped ceiling in a plenum space defined in the area above the dropped ceiling.
Plaster or drywall ceilings are also known in the art to include one or more lighting fixtures supported in one or more spaces above the ceilings, typically between joists that define the support structure of the plaster or drywall ceiling.
Heretofore, such lighting fixtures were configured to direct light in a single direction into a room below the ceiling. It is, however, desirable in certain applications to be able to direct light from a lighting fixture into two or more directions into a room below the ceiling. Such applications include, without limitation, architecturally ecstatic lighting, video conferencing, distance learning, telemedicine, internet video streaming, and non traditional studio environments.

Light fixture with adjustable direction lighting


The invention relates to a method for presenting interventional instruments in a 3D data set of an anatomy to be treated. A 3D data set of the anatomy is recorded before introduction of an interventional instrument. Once the interventional instrument has been applied, the spatial position of the instrument is determined by x-ray fluoroscopy from images created at two different angulations. A 3D model of the instrument is formed from the x-ray images. The 3D model of the instrument is fused with the 3D data set of the anatomy. A 3D hologram is reproduced from the fused 3D data set. The 3D hologram is repeatedly reproduced in real time to follow the application of the instrument in the presentation.

In medicine the switch from surgical interventions to minimally-invasive therapies is becoming established for serious illnesses.
Among the most frequent diseases with a fatal outcome are vascular angiopathies, with the resulting diseases such as heart attacks or strokes. The heart attack (myocardiac infarction=MI) is caused by diseases of the coronary vessels. In such cases arteriosclerotic plaque causes a thrombocyte activation and local thrombus formation. This can lead to a total occlusion ("blockage") of coronary vessels and thereby to a blocking of the blood flow. The occlusion in a heart attack is treated nowadays in the majority of cases by a minimally-invasive PCTCA (percutaneous transluminal coronary angioplasty). In this treatment the constricted points of the coronary artery are expanded with a "balloon catheter"
A further example of the switch from surgical to minimally-invasive therapy is characterized by the treatment of diseases of the heart valves. Until a few years ago replacement of heart valves involved an operation on an open heart. In this procedure mechanical or biological prosthetic heart valves (aortic valve, pulmonary valve) are implanted or the existing valve opening is surgically reshaped (mitral valve and tricuspidal valve). This was associated with high risks and long recuperation times of up to six weeks for the patient. For a few years now there have been methods of treating heart valve stenoses with the aid of special catheters.
Very important for a successful and low-risk minimally-invasive therapy is the 3D presentation of the anatomy to be treated, of an organ for example.
The disadvantage of the new minimally-invasive therapies is that they can only be performed with the aid of x-ray fluoroscopy. This previously only supplied 2D images of organs, of the heart for example and of the catheters or tools located there. This meant that a spatial assignment was barely possible.
Further developments in x-ray image processing have led to 3D presentations of vessels or cavities with the aid of contrast media.
It is known from a paper titled "AXIOM Artis FD Systems / DynaCT-A Breakthrough in Interventional 3D Imaging" by Patrick Kurp, a "Reprint from Medical Solutions, Jan. 2005, page 46-51", Order no. A91100-M1400-D105-1-7600, Reference CC 66105 SD 12043, that 3D soft tissue of non-moving organs can also be presented using x-ray technology. This type of method for 3D soft tissue creation, recognized in the medical imaging field as DynaCT imaging method, is described in DE 10 2004 057 308 A1, (which corresponds to U.S. Pat. No. 7,734,009) the content of which is included in this description. The term DynaCT (as capitalized) constitutes a registered trademark of the assignee of the present invention.
A distinct advance would be made with a C-arm x-ray apparatus currently being developed (CardDynaCT), with which images of 3D soft tissue and optionally high-contrast 3D images of the beating heart become possible by injecting contrast media.
Such a method is disclosed for example in DE 10 2005 016 472 A1, the contents of which is included in this description.
All known solutions however present the 3D x-ray images on 2D displays. The impression of a 3D image is achieved by volume rendering and rotation of the 3D image with the aid of a mouse of joystick.
With the aid of special eyeglasses, such as with polarization filters for example, it is possible to obtain an impression of a 3D image. However, this technology has not become established in medicine because of the additional eyeglasses required.
3D displays which manage without additional eyeglasses are known, made by companies such as newsight for example (see under http://www.newsight.com).
In these solutions the angles of view of the observer are detected and the polarization filter present in the display is controlled accordingly so that an impression of the 3D image is produced. This solution has the disadvantage that only one observer in each case perceives the impression of the 3D image. In addition the solution does not always operate reliably and has not established itself in the field of medical therapy.
A display system for image systems for reproducing medical images described in DE 100 36 143 C2, in which, instead of a display, a projector is used in the medical examination or intervention room, only allows 2D presentations however.
In the not yet published U.S. patent application Ser. No 11/093,561, "Creating a Stereoscopic Image Pair From Two Different Image Sources, Using Image Registration" a stereoscopic image impression is possible with the aid of two projectors and special eyeglasses worn by the observers. This solution has the advantage that a number of observers can see the 3D images; otherwise the disadvantages given above apply.
A method is described in the U.S. Pat. No. 6,672,165 B2 with which three-dimensional ultrasound images can be created holographically.
In the older DE 10 2008 015 312.5 a display system for reproducing medical hologram system is described in which the holographic images can be used for therapy, guidance and control. In practice however this is not a simple matter since many medical imaging systems, especially angiography systems, cannot generate any 3D data at a sufficiently high repetition rate in real time in order to make guidance possible. The known methods of 2D/3D overlaying are also not able to be used for holographic representation, so that it is not at all clear how such holographic images can be used for guiding an intervention.
DE 10 2005 051 102 A1 relates to a system and method for medical navigation, especially with C-arm and CT x-ray devices. In order to reduce the time outlay required for a medical navigation in percutaneous interventions, it is proposed to determine the position of a medical instrument in an object with the aid of projection images and to display the position in a three-dimensional structure image.
DE 10 2005 023 743 A1 describes a projection apparatus and a method for holographic reconstruction of scenes with a hologram matrix, an imaging system with a least one imaging means and an illumination system with sufficiently coherent light for illuminating a hologram encoded in the hologram matrix, with the light of the illumination device reconstructing the hologram. In a first step a reconstruction is undertaken as a Fourier transform of the encoded hologram in one plane of a first imaging means. In a second step the first imaging means forms an image of the hologram in a plane directly in front of the second imaging means. Simultaneously the second imaging means forms an image of the Fourier transform from the plane in an observer plane. In this way the reconstructed scene is provided enlarged in a reconstruction space stretched between the second imaging means and at least one observer window to at least one observer. The enlarged display of the hologram extends the size of the reconstruction space.

Method for representing interventional instruments in a 3D data set of an anatomy to be examined as well as a reproduction system for performing the method


The present invention uses the capacitive, or inductive, or resistive impedance component to constitute the first impedance, and the parallel connected capacitive and the inductive impedance components in parallel resonance to constitute the second impedance; and is characterized as that the first impedance and the second impedance in series connection is configured for inputting bi-directional power, thereby dividing its power source voltage to drive the bi-directional conducting light emitting diode.

(a) Field of the Present Invention
The bi-directional light emitting diode drive circuit in bi-directional power parallel resonance is disclosed by that a bi-directional power is used as the power source which is supplied to a first impedance which is constituted by a capacitive impedance component, or an inductive impedance component or a resistive impedance component as well as to a second impedance which is constituted by a capacitive impedance component and an inductive impedance component in parallel connection, whereby the inherent parallel resonance frequency of the second impedance is the same as the frequency of the bi-directional power source such as the frequency of an AC power, or the periodically alternated polarity power converted from the DC power to produce a parallel resonance status through the bi-directional power input. Thereof it is characterized in that the first impedance and the second impedance are series connected to receive a bi-directional power, whereby the power source voltage of the said bi-directional power is divided by the series connected first impedance and second impedance in parallel resonance to form a divided power for driving the bi-directional conducting light emitting diode.
(b) Description of the Prior Art
The conventional light emitting diode drive circuit using AC or DC power source is usually series connected with current limit resistors as the impedance to limit the current to the light emitting diode, whereof the voltage drop of the series connected resistive impedance always result in waste of power and accumulation of heat which are the imperfections.

This patent is subject to a terminal disclaimer.

Bi-directional light emitting diode drive circuit in bi-directional power parallel resonance


A read control flip-flop circuit is activated upon activation of an internal readout instruction signal from a command decoder to generate a signal for activating an internal data reading circuit. A write control flip-flop circuit activates an internal data writing circuit in response to an internal write operation instruction signal from the command decoder. When one of the internal write instruction signal and the internal readout instruction signal from this command decoder is activated, a burst length counter counts a predetermined number of clock cycles, and when the counted value reaches a predetermined value, a reset signal is activated to reset the read control flip-flop circuit and the write control flip-flop circuit. Thus, the layout area of the control portion for internal data read operation and internal data write operation in a synchronous semiconductor memory device is reduced.

1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and particularly to a structure of a portion of a synchronous semiconductor memory device for controlling input/output operation of internal data.
2. Description of the Background Art
FIG. 10 schematically shows an entire structure of a conventional synchronous semiconductor memory device. Referring to FIG. 10, the synchronous semiconductor memory device includes a memory array 1 having a plurality of dynamic type memory cells arranged in rows and columns. Although the structure of the memory cells included in this memory array 1 is not shown, generally 1 transistor/1 capacitor type memory cells are employed.
The synchronous semiconductor memory device further includes an input buffer circuit 2 which incorporates externally applied control signals, that is, a row address strobe signal ZRAS, a column address strobe signal ZCAS, and write enable signal ZWE in synchronization with externally and repeatedly applied clock signals CLK to generate an internal control signal, a command decoder 4 which determines the states of the internal control signals applied from the input buffer circuit 2 to generate a signal for activating a designated internal operation, a readout control circuit 6 activated in response to readout operation instruction signal R from command decoder 4 to generate a readout operation activation signal READ for activating an operation of reading out data of a selected memory cell of memory array 1, and a write control circuit 8 activated in response to a write instruction signal W applied from command decoder 4 to generate a write operation activation signal WRITE for activating an operation of writing data to a selected memory cell of memory array 1.
Input buffer circuit 2 incorporates externally applied control signals ZRAS, ZCAS and ZWE in synchronization with the rise of clock signal CLK and generates internal control signals each in the form of a one-shot pulse signal according to the state of these external control signals. Command decoder 4 decodes this internal control signals applied from input buffer circuit 2 in the form of one-shot pulse to determine the designated internal operation. In other words, in the synchronous semiconductor memory device, the operation to be executed within this device is designated by the combination of the states of the external control signals at the time of rise of clock signal CLK. Here, clock signal CLK may either be an externally applied clock signal or an internal clock signal obtained by buffering this externally applied clock signal.
The synchronous semiconductor memory device further includes an address buffer 18 which incorporates an externally applied address signal AD in synchronization with clock signal CLK to generate an internal address signal, a cell selecting circuit 20 activated in response to a cell selecting operation activation signal from command decoder 4 to select a corresponding memory cell in memory array 1 in accordance with the internal address signal applied from address buffer 18, a write circuit 10 activated in response to write operation activation signal WRITE from write control circuit 8 to write an internal write data applied from input buffer circuit 14 successively to a selected memory cell of memory array 1, and a readout circuit 12 activated in response to readout operation activation signal READ from readout control circuit 6 to successively read out data of a selected memory cell of memory array 1 and to apply the data to output buffer circuit 16.
Normally, write circuit 10 and readout circuit 12 respectively have a plurality of registers and conduct the data stored in these registers in synchronization with the clock signal. There are various data transfer sequences for these write circuit 10 and readout circuit 12, but in this specification, description is simply made that when activated write circuit 10 and readout circuit 12 perform data writing or data reading with a predetermined sequence in synchronization with clock signal CLK.
Input buffer circuit 14 operates in synchronization with clock signal CLK and incorporates external write data DQ (D) applied to data input/output terminal 21 for application to write circuit 10. Output buffer circuit 16 is activated in response to data output enable signal OEM applied from output control circuit 22, buffers the internal readout data applied from readout circuit 12 in synchronization with the clock signal and conducts this buffered data to data input/output terminal 21.
Output control circuit 22 delays readout operation activation signal READ applied from readout control circuit 6 for a prescribed time period (CAS latency) to produce data output enable signal OEM. CAS latency indicates the number of cycles of clock signal CLK required after application of a read command (that is, set of states by which data readout operation is designated by external control signals ZRAS, ZCAS and ZWE) until appearance of valid data DQ(Q) at data input/output terminal 21. More specifically, valid data appears at input/output terminal 21 upon expiration of CAS latency after the application of the read command.
In this synchronous semiconductor memory device, externally applied control signals ZRAS, ZCAS and ZWE are incorporated in synchronization with external clock signal CLK applied periodically and repeatedly to designate this internal operation. Address signal AD is also incorporated in synchronization with clock signal CLK. Internal operation timing is determined by the clock signal, and data input and data output are also performed in synchronization with clock signal CLK. Accordingly, there is no need to take into consideration the timing margin for skew of external control signals ZRAS, ZCAS and ZWE as well as address signal AD (since the defined timings of these signals are determined at the time of the rise of clock signal CLK), so that the internal operation can be started in a faster timing. In addition, since data are also input and output in synchronization with clock signal CLK, data can be input and output in a faster speed.
FIG. 11 is a diagram showing an example of a structure of readout control circuit 6 in FIG. 10. Referring to FIG. 11, readout control circuit 6 includes a burst length counter 6a activated in response to internal readout operation instruction signal R applied from command decoder 4 shown in FIG. 10 to count clock signals CLK to a predetermined number (i.e., burst length), and a flip-flop 6b set in response to activation of internal readout instruction signal R and reset in response to reset signal RST (R) which is a count-up signal from burst length counter 6a. Readout operation activation signal READ is output from this flip-flop 6b. The burst length counted at burst length counter 6a indicates the number of data which can be read out successively upon data reading when a read command is applied thereto once.
Flip-flop 6b includes an inverter 6ba receiving readout operation instruction signal R, an inverter 6bb receiving write operation instruction signal W, an NAND circuit 6bc receiving an output signal of inverter 6ba at its one input, and an NAND circuit 6bd receiving an output signal of NAND circuit 6bc, an output signal of inverter 6bb and reset signal RST(R) applied from burst length counter 6a through an inverter 6be. An output signal of NAND circuit 6bd is applied to the other input of NAND circuit 6bc.
The write operation instruction signal W is generated (that is, activated) from command decoder 4 upon the rise of clock signal CLK when external control signals ZRAS, ZCAS and ZWE are set at predetermined states and data write operation is designated. Readout operation activation signal READ is output from NAND circuit 6bc. This readout control circuit 6 is set when readout operation instruction signal R is activated and is reset when reset signal RST (R) from burst length counter 6a is activated. Accordingly, the activation period of readout operation activation signal READ is determined by the burst length counted by burst length counter 6a.
FIG. 12 shows an example of a structure of write control circuit 8 in FIG. 10. Referring to FIG. 12, write control circuit 8 includes a burst length counter 8a activated upon activation of write instruction signal W to count a burst length, and a flip-flop 8b set upon activation of write instruction signal W and reset upon activation of reset signal RST (W) from burst length counter 8a. Internal write operation activation signal WRITE is output from this flip-flop 8b.
Flip-flop 8b includes an inverter 8ba receiving write instruction signal W, an inverter 8bb receiving readout instruction signal R, an NAND circuit 8bc receiving an output signal of inverter 8ba at its one input to output write operation activation signal WRITE, and an NAND circuit 8bd receiving an output signal of NAND circuit 8bc, an output signal of inverter 8bb, and reset signal RST (W) from burst length counter 8a applied via an inverter 8be. An output signal of this NAND circuit 8bd is applied to the other input of NAND circuit 8bc.
Burst length counter 8a counts the burst length at the time when data write operation is performed. The operations of readout control circuit 6 and write control circuit 8 shown in FIGS. 11 and 12 will now be described hereinbelow, with reference to FIG. 13 which is a timing chart for these operations. Here, it is assumed that the burst length is 4 for both reading and writing operations.
In the period of clock cycle #0, active command (memory cell selecting operation start instruction signal) is already provided. Cell selecting circuit 20 is activated in the synchronous semiconductor memory device and a memory cell would be at a selected state in memory cell array 1.
In clock cycle #1, a write command is applied so as to activate write operation instruction signal W from command decoder 4 for a prescribed period. In response to this activation of write operation instruction signal W, flip-flop 8 is set and write operation activation signal WRITE is activated at H level. At this time, burst length counter 8a is also activated to start the counting operation of clock signal CLK. According to this write command, a column selecting circuit included in cell selecting circuit 20 selects a column of the memory cell. Input buffer circuit 14 incorporates an external write data DQ (D0) applied to data input/output terminal 21 and provides this data to write circuit 10. Write circuit 10 is activated in response to write operation activation signal WRITE to write the write data from this input buffer circuit 14 to a selected memory cell of memory array 1. During the period in which this write operation activation signal WRITE is in activation, write circuit 10 successively writes the write data applied from input buffer circuit 14 in synchronization with clock signal CLK to selected memory cell of memory array 1.
In clock cycle #5, reset signal RST (W) from burst length counter 8a is activated, and write operation activation signal WRITE is reset at L level. In this clock cycle #5, external write data is not applied, and thus write operation of this write circuit 10 is inhibited even when input buffer circuit 14 operates according to clock signal CLK, so as to prevent writing of undefined data. More particularly, in the data write cycle, write circuit 10 internally writes the data from input buffer circuit 14 to a selected memory cell of memory array 1 with a delay of 1 clock cycle per each data writing.
In clock cycle #7, when read command is applied, internal readout instruction signal R from command decoder 4 is activated to attain H level for a prescribed period, and in response to this activation, flip-flop 6b is set to activate readout operation activation signal READ to attain H level. In response to this activation of readout operation activation signal READ, a selecting operation for a memory cell in memory array 1 is performed, and the data of this selected memory cell is readout by readout circuit 12.
Output control circuit 22 delays this readout operation activation signal READ for a prescribed period (CAS latency, i.e., one clock cycle) and activates data output enable signal OEM to attain H level. Output buffer circuit 16 is activated in response to this activation of data output enable signal OEM and conducts the data which is successively readout from readout circuit 12 to data input/output terminal 21. Accordingly, data Q0, Q1, Q2 and Q3 are successively readout from clock cycle #9.
After burst length counter 6a has counted clock signal CLK four times, reset signal RST (R) is activated to attain H level in clock cycle #11. Thus, readout circuit 12 is inactivated. At this time, data output enable signal OEM is still in an activated state at H level, and in clock cycle #12, data Q3 is output to data input/output terminal 21 via output buffer circuit 16. After this readout of data Q3, data output enable signal OEM is inactivated in clock cycle #12.
At the time of this data readout, the period between the application of a read command and the first output of a valid data, that is, the period between clock cycle #7 to clock cycle #9, is called the CAS latency.
By the operation described above, it is made possible to input or output four data (burst length 4) successively in synchronization with clock signal CLK.
As shown in FIGS. 11 and 12, burst length counters are provided in readout control circuit 6 and write control circuit 8, respectively. Reset of flip-flop 6b is performed by internal write instruction signal W as well as by reset signal RST (R) for the following reason. If, write command is applied after the read command is applied and data write operation is started before burst length counter 6a completes counting the burst length, readout circuit 12 has to be inactivated so as to stop the data readout operation. In addition, reset of flip-flop 8b is performed by readout instruction signal R as well as by reset signal RST (W) in write control circuit 8 as shown in FIG. 12 for the following reason. After the write command is applied, if a read command is newly applied before burst length counter 8a finishes counting the burst length, this write circuit 10 has to be inactivated so as to stop the data write operation. The operation as described above in which a command designating a different access mode is provided before input or output of the burst length data is referred to as an "interruption."
In addition to such situations, there may be a difference between the burst length at the time of readout operation and the burst length at the time of write operation. To accommodate such difference, respective control circuitries for data readout operation and for data write operation are separately provided.
However, as shown in FIGS. 11 and 12, readout control circuit 6 and write control circuit 8 are provided with burst length counters 6a and 8a. These burst length counters 6a and 8a are generally formed of clock shift circuits which shift readout operation instruction signal R or write operation instruction signal W in synchronization with clock signal CLK, occupying a relatively large area. Accordingly, when burst length counters 6a and 8a are respectively provided to readout control circuit 6 and write control circuit 8, the area occupied by the portion for controlling the data input/output operation would be made large, which is a significant disadvantage for the implementation of a highly integrated synchronous semiconductor memory device which occupies only a small area.

Synchronous semiconductor memory device in which burst counter is commonly employed for data writing and for data reading


A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Memory subsystems that utilize memories such as double data rate (DDR) synchronous dynamic random access memory (SDRAM) has a source synchronous interface that requires precise timing. The timing on the interconnect coupling the memory to a controller is edge aligned for the data and the strobe signals. The strobe signal is generally delayed to the center of the data and utilized to latch the data. The range timing from the beginning to the end of valid data is referred to as the valid data eye. The eye is defined by two edges, between the two edges the data may be correctly latched, outside of the two edges the data becomes invalid. Thus, the strobe must fall between the edges of the data eye to obtain correct data. As the speed of memory increases, not only does the eye become narrower, but other conditions related to memory operation can cause the eye to drift. For example, thermal conditions may cause the eye to drift. Thermal conditions of the memory devices may change based on power consumption changes from different workloads (i.e. as data throughput across the memory channel increases, power consumption may increase for the memory devices, which would lead to a higher thermal load per device). The latest versions of memory continue to increase in speed, such as DDR2, DDR3, DDR4, DDR5 is not yet defined or in definition process, refer to it as future DDR standard? and graphics memory implementations (e.g. GDDR5), among others.


According to one embodiment, an information processor divides input image data for a plurality of information processors so as to perform a super resolution process as a distributed processing. The super resolution process generates a high resolution image based on a plurality of low resolution input images. The information processor includes a division point determining unit, a division processor, and a combination processor. The division point determining unit determines a division point for an input image of a sequence of image frames. The division processor divides, for each of the information processors, the input image at the division point, and allocates each divided input image to each corresponding one of the information processors.

In recent years, a television or a display to which a super resolution technology is applied is available in the market. The super resolution technology is a technology for reproducing a detailed portion (a component of the Nyquist frequency or higher) that disappears at the time of sampling pixels of an image (at the time of photoelectric conversion or a reduction process by an imaging element), through image processing. For example, when a video of a video camera of the NTSC system or a DVD that has low resolution is displayed on a large-screen liquid crystal TV while using the super resolution technology, a detailed portion is reproduced and a clear image having high resolution can be acquired.
While there have been proposed various systems implementing the super resolution technology, there exists an image processing technology referred to as a multiple frame super resolution that generates a high-resolution output image by matching positions of a plurality of frames of low-resolution input images. In the multiple frame super resolution, while a processing result of high image quality having high resolution can be acquired, there is a high processing load.
Meanwhile, a platform (cloud platform) of cloud computing capable of handling a large scale data by connecting a plurality of servers through a network and distributing the process has been prepared, and the super resolution process can be performed in a distributed manner on the platform. Conventionally, the super resolution process is performed at one node (information processor). However, in such a case, the processing time is too long and thereby, there has been proposed a technology for performing a distributed process at a plurality of nodes using a cloud platform.
However, conventionally, when the multiple frame super resolution process is performed as the distributed process at a plurality of nodes, compatibility with the cloud platform is not so good as well as compressed and encoded image could not efficiently handled.

Information processor, cloud platform, information processing method, and computer program product thereof


Various example embodiments are disclosed herein. According to an example embodiment, an apparatus for use in a wireless transmitter may include a continuous phase modulation (CPM) sample generator configured to generate a group of constant envelope CPM modulated signal samples, a Fourier transform block configured to perform a Fourier transform on the group of constant envelope signal samples to generate an initial group of Fourier coefficients, a zero insertion block configured to generate an expanded group of Fourier coefficients by inserting one or more zeros in the initial group of Fourier coefficients, and an inverse Fourier transform block configured to perform an inverse Fourier transform on the expanded group of Fourier coefficients to generate a group of constant envelope time-domain samples and to map the constant envelope time-domain samples onto a group of orthogonal subcarriers for transmission.

Orthogonal Frequency Division Multiplexing (OFDM) is a linear modulation scheme in which a set of orthogonal subcarriers are used to carry user data. OFDM can be efficiently implemented using Fourier transforms, such as the Fast Fourier Transform (FFT) and can be designed to be especially robust to multipath. Low complexity frequency domain equalization algorithms can be used to mitigate the impact of the channel. OFDM may provide a spectrally efficient scheme in which the subcarriers can overlap but remain orthogonal (in the absence of synchronization errors).
OFDMA (orthogonal frequency division multiple access) is an extension of OFDM in which multiple users share the same transmission band. OFDMA is a multi-user version of the OFDM modulation scheme. The multiple access feature is achieved in OFDMA by assigning subsets of the subcarriers to individual users, and allows the simultaneous low data rate transmission from several users over the same band. In conventional OFDMA, a different number of the available sub-carriers can be assigned to different users, in order to support differentiated quality of service (QoS).
A disadvantage of multi-carrier modulation, such as OFDM or OFDMA, is that it can exhibit high peak-to-average power ratio (PAPR), where the peak value of the signal can be much larger than the average (typical) value. For example, the peak value of an OFDM waveform may typically grow linearly with the number of subcarriers because for some OFDM symbols, all of the subchannel waveforms can potentially add up together in phase at some time during the transmission. This may require the use of circuits with linear characteristics over a large dynamic range, such as linear power amplifiers. However, most power amplifiers may he most power-efficient when they are operating in a saturation (or nonlinear) region. In general, linear power amplifiers are less efficient, more expensive, and often require larger areas (for heat dissipation) than their nonlinear counterparts. Furthermore, clipping the signal at high levels may occur which may distort the information-bearing amplitude of the signal and yields out-of-band radiation, and which may degrade bit error rate (BER) performance of the system.

Techniques to generate constant envelope multicarrier transmission for wireless networks


A signal processing device using a liquid crystal device having a plurality of pixels includes a storage unit that stores a signal which controls a level of transmittance in a plurality of pixels, a detection unit that, based on the signal that is stored in the storage unit, detects a first pixel associated with a second value which indicates higher transmittance than a first value, and a second pixel adjacent to the first pixel and associated with a fourth value which indicates the higher transmittance than a third value; and a correction unit that corrects the second value so that a difference of the transmittance indicated by the second value and the fourth value decreases. The third value indicates the higher transmittance than the first value, and the fourth value indicates a higher transmittance than the second value.

1. Technical Field
The present invention relates to a technology for reducing a disclination.
2. Related Art
Originally, a liquid crystal panel is configured to control an alignment state of liquid crystal molecules using an electric field between a pixel electrode and an opposing electrode in a pixel. However, in a high definition liquid crystal panel, for example, the distance between the pixels adjacent to each other becomes shorter, an electric field between the pixel electrodes of the two pixels (lateral electric field) is generated, and hence there may be a case where a so-called disclination occurs in which the liquid crystal molecules are aligned in an unintended direction. The occurrence of the disclination causes a display quality of the liquid crystal panel to deteriorate. JP-A-2009-25417, JP-A-2009-104053, JP-A-2009-104055, JP-A-2009-237366 and JP-A-2009-237524 disclose technologies for suppressing the occurrence of the disclination.
When a correction to suppress a disclination is performed, depending on how to choose a pixel to be corrected, there has been cases of a discrepancy between whether or not the correction is necessary and whether or not the correction is actually performed.

Signal processing device, liquid crystal device, electronic apparatus and signal processing method


A decoder circuit includes a first delay means for delaying unit data read out from a dictionary, a selecting means for selecting data and a second delay means for delaying data selected by the selecting means, wherein delayed data from the second selecting means is written again in the dictionary, the selecting means is supplied with delayed data from the first delay means and delayed data from the second delay means and the selecting means selects delayed data from the second delay means if a read address and a write address of the dictionary fall within a range of a predetermined distance corresponding to delay amounts of the first and second delay means and the selecting means selects delayed data from the first delay means in other cases.

1. Field of the Invention
The present invention relates to a decoder circuit for decoding data compressed by using a LZ 77 method (Lempel-Ziv 77 method), for example, and particularly to a decoder circuit and a decoding method which can make decoding processing become faster.
2. Description of the Related Art
A LZ 77 method exists as a kind of dictionary type data compression algorithms. The LZ77 method is used in data compressing and decoding circuits provided within various kinds of data recording apparatus such as an ALDC (Adaptive Lossless Data Compression) encoder and an ALDC decoder within an AIT format tape drive, an S-AIT format tape drive or an LTO format tape drive.
A data compression principle of the LZ77 method will be described. That is, a last character string of a predetermined size of character strings (data strings) that have been inputted in the past is registered in a dictionary (history buffer), a match character string of a newly inputted character string (that is, a character string to be compressed) is retrieved from the dictionary and the newly inputted character string is replaced with address information of the match character string. This dictionary is not a static type dictionary but it is updated so as to remove an old character string by adding the character string just before the character string to be compressed in accordance with a progress of data compression. Hence, this dictionary is called a "sliding dictionary".
FIG. 1 of the accompanying drawings is a schematic diagram showing an example of the manner in which data is compressed by the above-mentioned LZ77 method. Although it has been customary that the ordinary dictionary is 512 bytes, 1024 bytes or 2048 bytes in size, this sliding type dictionary is 16 bytes in size for simplicity of explanation. As shown in FIG. 1, a last character string "ABCCAB . . . BCC" (each of the characters A, B and C is one byte) of 16 characters of character strings that had been inputted in the past is registered as a dictionary. The character "A" that was inputted 16 bytes before is assigned an address 0, the character "B" that was inputted 15 bytes before is assigned an address 1 and the character "C" that was inputted one byte before is assigned an address 15.
When the newly inputted character string is "ABCA", for example, a character string of addresses 9 to 12 is matched with "ABCA" by the retrieval processing. Accordingly, in this case, the address 12 is outputted as a match address (address defined as the end address of the match character string). Then, in the end, the character string "ABCA" of 4 bytes is compressed to 2 bytes by transforming the character string "ABCA" into a code word (Copy Pointer, Match Count=4 and Match Address=9) indicating a match address length 4 and a leading address 9.
When the thus compressed data is decoded, referring to this dictionary in the opposite manner, the code word (Copy Pointer, Match Count=4 and Match address=9) is transformed into the character string "ABCA". In that case, as the processing opposite to the processing in which the dictionary is updated when data is compressed, the dictionary used upon compressing may be restored by rewriting characters in the dictionary in accordance with a progress of decoding processing.
FIGS. 2 to 6 are respectively schematic diagrams showing the manner in which compressed data are decoded, from a standpoint of elapse of time, in association with the dictionary shown in FIG. 1. First, as shown in FIG. 2, a dictionary address 9 (Match Address=9 indicated by a code word) is designated as a read address radr and a dictionary address 2 is designated as a write address wadr. Then, as shown in FIG. 3, a character "A" is read out from the address 9 and this character "A" is written again in the address 2, whereafter addresses 10 and 3 are designated as the read address radr and the write address wadr, respectively.
Subsequently, as shown in FIG. 4, a character "B" is read out from the address 10 and this character "B" is written again in the address "3", whereafter addresses 11 and 4 are designated as the read address radr and the write address wadr, respectively.
Subsequently, as shown in FIG. 5, a character "C" is read out from the address 11 and this character "C" is written again in the address 4, whereafter addresses 12 and 5 are designated as the read address radr and the write address wadr, respectively.
Subsequently, as shown in FIG. 6, a character "A" is read out from the address 12 and this character "A" is written again in the address 5, whereafter addresses 13 and 6 are designated as the read address radr and the write address wadr, respectively.
As described above, based on the code words (Copy Pointer, Match Count=4 and Match Address=9), data is read out from the dictionary character by character (unit data) and thus read character is written again in other address of the dictionary, whereafter the next one character is read out and thereby the character string "ABCA" is decoded.
According to the related art, in the decoder circuit for decoding data compressed by using this LZ77 method, the read unit data is written again in the dictionary at one period of operation clock.
[Cited Patent Reference 1]: Republished Patent Application of International Publication Number W02003/032296 (pp. 12 to 13, FIGS. 3 and 4)


A color signal correcting method for correcting a color signal of each pixel outputted from a single-plate color image pickup element having a given color filter arrangement to correct a color reproduction error in an image, comprising the steps of:                computing color signals of filter colors other than a filter color at the spatial location of a pixel to be corrected, wherein the other color signals at the spatial location are computed on the basis of color signals of a plurality of pixels of the same filter color located around the pixel to be corrected; and        obtaining a correction value by multiplying the color signal of the pixel to be corrected and the computed other color signals by a predetermined correction coefficient and combining the products.

1. Field of the Invention
The present invention relates to a color signal correcting method, apparatus, and program and, in particular, to a color signal correcting method, apparatus, and program for correcting color reproduction errors in image signals outputted from a single-plate color image pickup element having a given color filter arrangement.
2. Description of the Related Art
Color imaging apparatuses such as video cameras and digital cameras generally include a color reproduction correcting circuits, which applies linear matrix processing to image signals to improve the color reproduction of a subject. The linear matrix processing is conventionally performed after interpolation of R, G, and B dot sequential color signals outputted from an image pickup element. After the interpolation, the color image signals are corrected according to the following equation so as to match a desired color space (for example, Japanese Patent Application Laid-Open No. 11-298909).
                              (                                                                      R                  ′                                                                                G                  ′                                                                                B                  ′                                                              )                =                              (                                                            a                                                  b                                                  c                                                                              d                                                  e                                                  f                                                                              g                                                  h                                                  i                                                      )                                          (                                                            R                                                                              G                                                                              B                                                      )                                              [                  Formula                                                              1                ]

Color signal correcting method, apparatus, and program


A medical apparatus, including a lithotripsic device configured to break a stone into one or more fragments in a body lumen and an endoscope which is configured to obtain a captured image in the body lumen. The medical apparatus further includes an image processor which is configured to process the captured image and create a processed image for display on a monitor, and which is also configured to process and display a track of a movement of at least one of the stone or the one or more fragments.

A lithotripsy medical procedure consists of breaking a stone or other hardened mass into fragments, typically in a body lumen such as the bladder, so that the stone no longer affects operation of the lumen. The procedure inherently creates fragments of the stone being broken, and in a successful procedure the fragments are sufficiently small so that operation of the lumen is no longer affected.
US Patent Publication 2011/0054363, to Cain et al., whose disclosure is incorporated herein by reference, describes a device that delivers lithotripsy therapy to a patient so as to fractionate urinary stones in the patient. The device is claimed to be configured target and track urinary stones.
PCT Patent Publication 2011/133922, to Bailey et al., whose disclosure is incorporated herein by reference, describes a method for detecting stones by ultrasound, in which the ultrasound reflections from a stone are preferentially selected and accentuated relative to the ultrasound reflections from blood or tissue. The disclosure also describes displaying a stone as it is pushed in real time.
Japanese Patent Publication 05-076539, to Aida Satoshi et al., whose disclosure is incorporated herein by reference, describes a stone crushing device using a piezoelectric element. The device is claimed to exactly irradiate only a stone so as to decrease side effects.
US Patent Publication 2011/0074943, to Modell et al., whose disclosure is incorporated herein by reference, describes an imager configured to generate a plurality of frames at a frame frequency greater than an electromagnetic energy emission pulse frequency of a medical device. In the disclosure, an imaging system is claimed to be able to be used to locate a stone and to appropriately target treatment such that pulses are aimed at the place where the stone is located.
PCT Patent Publication 2013/154708, to Chia et al., whose disclosure is incorporated herein by reference, describes a surgical laser system for use in fragmenting of targeted kidney or bladder stones. The system has a laser probe which is optically coupled to a beam combiner and which is configured to output a combined laser pulse train.
Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Location of fragments during lithotripsy


A device and a method, in particular for labeling containers, in particular bottles, having a corresponding conveyor device, several equipment units, in particular labeling units, and a controller as well as a control console for controlling certain unit functions. To ensure reliable operation of the device, the control console is arranged to be variable in position and at least one position detector is provided, whereby the controller enables or blocks certain functions in a safety-oriented manner as a function of the position of the control console.

A device and/or a method of this type is already known from WO 2005-068 302 A1, for example. A corresponding device and such a method are already known from WO 2005-068 301 A1 as well. With the known devices for furnishing bottles, in particular for labeling bottles, a carousel is provided for conveying the bottles. Labeling units are arranged interchangeably on the periphery of the machine. To do so, equipment unit receptacles supported at the bottom, for example, are provided.
For the various equipment units, however, various parameters must be input at the controller end in particular. Furthermore, the heights of the individual equipment units must be adjusted individually according to the desired labeling task, especially in the case when units are changed or when changing the labeling process (height of label adhesive on the bottle). A suitable control console is provided for this purpose. Input and/or adjustment of certain parameters or execution of certain functions, in particular adjustment of the height of the labeling units or "tilting," i.e., manual rotation of the machine and/or carousel, e.g., with opened protection, could not be performed easily from a console at a great distance and would result in considerable adjustment problems as well as safety problems because of the risk of injury when raising and lowering the equipment units.


The invention concerns a device (102) for X-ray imaging, comprising a device mount (104) and an arm (106) movably connected to said device mount for rotation, relative to said device mount, around a device axis of rotation (108). The device (102) furthermore comprises an X-ray source (110) for emitting an X-ray beam (111) and an X-ray detector (112). In addition the system (102) comprises a carrier (114) having a U-arm geometry, wherein said U-arm geometry is provided with mutually facing portions (116, 118) and an intermediate portion (120) connecting said mutually facing portions (116, 118); wherein said mutually facing portions (116, 118) are configured for carrying said X-ray source (110) and said X-ray detector (112), respectively; and wherein said intermediate portion is movably connected to the arm (106) for rotation, relative to said arm (106), around a carrier axis of rotation (122) substantially perpendicular to the device axis of rotation (108).

Generally speaking, it is of clinical benefit in X-ray imaging to be able to generate images of various intersections of a patient, however, without repositioning the patient relative to the patient support. This requires a device for X-ray imaging having a mechanical geometry capable of appropriately positioning the X-ray source and X-ray detector relative to such patient. Various geometries have been contemplated towards that extent. For example, U.S. Pat. No. 6,644,852 B2 discloses a device having two independently articulated arms supporting an X-ray tube and an X-ray detector. In addition, U.S. Pat. No. 5,155,757 discloses a C-arm having a curved sliding mechanism. However, state of the art devices rely on complex and heavy hence expensive mechanical geometries.
U.S. Pat. No. 3,281,598 A discloses an overhead support for a vertically and rotatably movable X-ray tube support arm and cooperating tiltable X-ray table.
U.S. Pat. No. 4,412,346 A discloses an X-ray photography apparatus comprising an X-ray tube and an image receiving device attached to two tilting members which are each rockably supported on the distal end portion of a traveling support frame telescopically protruding parallel to a horizontal main axis from a rotating base rotating about the main axis.
US 2014/105357A1 discloses an X-ray apparatus including a source for emitting X-rays to an object; a detector for detecting the X-rays penetrating the object; an arm for connecting the source to the detector and moving the detector up and down according to a rotation of the source; and a controller for controlling an imaging of the object by driving the arm.
US 2003/112926 A1 discloses an X-ray apparatus that has a radiation source and a radiation receiver that are movably mounted at a stand arranged at the ceiling of an installation room.
US 2014/033432 A1 discloses a patient positioning system which employs an arm having a first portion and a second portion which is telescopic relative to the first portion.

Device for remote fluoroscopy, nearby fluoroscopy and radiology


An x-ray detector with a scintillator element connected to a detection area of a photodiode via an optically transparently curing adhesive. To increase the sensitivity of the x-ray detector, it is proposed to mix the adhesive with a powder prepared from a material with a refractive index of at least 1.8 and an average grain size of less than 100 nm.

There are known x-ray detectors, for example directly converting x-ray detectors, in which a scintillator element is adhesively attached to a detection area of a photodiode by way of an optically transparent adhesive, for example an epoxy resin. An intensity of a scintillation light produced in the scintillator element is attenuated when the adhesive is penetrated. This detracts from the sensitivity of the x-ray detector.


In one embodiment, a relationship is determined between radio link protocol (RLP) sequence numbers in received RLP packets and real-time protocol (RTP) sequence numbers in RTP packets decompressed from the received RLP packets. An RTP sequence number associated with a compressed RTP packet is determined based on the determined relationship and at least one of the RLP sequence numbers of the received RLP packet or packets forming the compressed RTP packet. An RTP time stamp may be determined in a similar manner.

The Internet Protocol (IP) has become the dominant transport protocol in both wireline and wireless networks, which has led to the convergence of telecommunication and data networks. In many services and applications (e.g., Voice over IP (VoIP), interactive games, instant messaging, etc.), the payload of an IP packet is almost of the same size or even smaller than the header. In addition to the IP network protocol, other protocols (e.g., real-time protocol (RTP), user datagram protocol (UDP), etc.) are added to the original information bits for effective transport in a packet data network.
Fortunately, it is not necessary to send the enormous RTP/UDP/IP header for each packet all the time. Instead a header compression algorithm such as the robust header compression (RoHC) may be used. The principle behind header compression is that most of the fields in the RTP/UDP/IP header are static; hence they can be sent once uncompressed during a first communication (e.g., the initial transmitted packets in a wireless system) from the compressor at the transmission side to the decompressor at the reception side. Once the decompressor has reliably acquired the static information, the compressor starts sending compressed headers carrying information regarding the dynamic parts of the header. From the compressed header, the decompressor is able to fully reconstruct the RTP/UDP/IP header and pass the packet on. In this way, the large headers are not transmitted for each packet, leading to tremendous savings in capacity.
However, current header compression schemes do have some drawbacks. For ease of explanation, these drawbacks will be described with respect to header compression implemented in a conventional wireless communication system.
FIG. 1 illustrates a general architecture of a well-known wireless communication network. As shown, an access terminal (AT) 10 communicates with a base station (BTS) 12 over an air interface. Examples of an AT include a mobile station, a mobile unit, a wireless phone, wireless equipped PDA or computer, etc. Multiple base stations 12 communicate with a radio network controller (RNC) 14, which provides signaling and traffic processing for each wireless data session. FIG. 1 shows the AT 10, BTS 12, RNC 14 and the interfaces between these components form what is known as a radio access network (RAN). The RAN communicates with a core network to access, for example, the internet. In the example of FIG. 1, the core network includes one or more packet data service nodes (PDSNs) 16 connected between the RNCs 14 and, for example, the internet (not shown).
As examples, header compression may occur between the AT 10 and the PDSN 16, between the AT 10 and the RNC 14, etc. When the AT 10 establishes a connection with the network, for example, a VoIP call, the application layer packet will be carried over the RTP/UDP/IP protocol stacks. The RTP/UDP/IP headers will be compressed by a compressor at the AT 10 using, for example, the RoHC algorithm mentioned above. The compressed packet will be sent uplink from the BTS 12 to the RNC 14 and from the RNC 14 to the PDSN 16. The decompressor at the RNC 14 or the PDSN 16 decompresses the RoHC header to re-establish the RTP/UDP/IP header. Similarly, on the downlink direction, the PDSN 16 and RNC 14 receive packets and the compressor at the PDSN 16 or RNC 14 compresses the RTP/UDP/IP headers to generate the RoHC or compressed header. The packet with compressed header is sent to the BTS 12 and on to the AT 10. A decompressor at the AT 10 decompresses the RoHC header to obtain the original RTP/UDP/IP header, and passes the packet onto the application layer.
FIG. 2 illustrates another architecture of a wireless communication network—the so called flat IP network architecture. As shown, the AT 10 communicates with a base station (BS) 20 over an air interface. The BS 20 converges multiple mobile network elements into a single entity and combines the signaling and bearer into one IP connection. In this flat IP architecture, the BS 20 contains all the radio access technology based functionalities. In other words, the functionalities in BTS, RNC and PDSN of FIG. 1 are be converged to the BS. The BS 20 functions like a router in the network and communicates with other BSs and network elements. Compared to FIG. 1, there are no separate RNC and PDSN elements anymore. The BS may also communicate with an access gateway 22, which provides for external connection to other networks such as the internet.
In the architecture of FIG. 2, header compression may occur between the AT 10 and the BS 20, or between the AT 10 and the access gateway 22. When the AT 10 establishes a connection with the network, for example, a VoIP call, the application layer packet will be carried over the RTP/UDP/IP protocol stacks. The RTP/UDP/IP headers will be compressed by a compressor at the AT 10 using, for example, the RoHC algorithm mentioned above. The compressed packet will be sent uplink from the AT 10 to the BS 20, or from the AT 10 to the BS 20 and from the BS 20 to the access gateway 22. The decompressor at the BS 20 or the access gateway 22 decompresses the RoHC header to re-establish the RTP/UDP/IP header. Similarly, on the downlink direction, the access gateway 22 and BS 20 receive packets, and the compressor at the access gateway 22 or the BS 22 compresses the RTP/UDP/IP headers to generate the RoHC or compressed header. The packet with the compressed header is sent to the AT 10. A decompressor at the AT 10 decompresses the RoHC header to obtain the original RTP/UDP/IP header, and passes the packet onto the application layer.
The robust header compression (RoHC) algorithm uses several encoding methods, including the window-based least significant bits encoding algorithm, for the compression of the dynamic fields in the protocol headers. The RoHC compression algorithm also incorporates a feedback mechanism. The RoHC compression algorithm is very efficient on wireless links with high error rates and/or long round trip time. Because of its efficiency and robustness, the RoHC compression algorithm is suitable on wireless networks where the radio resource is costly.
When there are large consecutive packet losses in the link layer and/or a large degree of packets out of order, the decompressor is not able to decompress newly received packets. When decompression failure happens, the decompressor will loose its context. The context of a header compression session is the state of the compressor and the state of the decompressor, and these states must be synchronized for successful header reconstruction. The decompressor usually sends a feedback packet to the compressor instructing the compressor to resynchronize the compression status by sending the full header. The decompressor will discard received packets with the compressed header, including uncorrupted packets, until the full header information is received in an uncompressed packet. As a result, during resynchronization between the compressor and decompressor, additional packet losses will occur, degrading the performance and quality of the call. These packet losses caused by loss of synchronization between the compressor and decompressor should be minimized or eliminated.

Header compression in a wireless communication network


The present disclosure concerns methods for producing purified saponins, such as QS-21, which reduces the number of necessary lyophilization cycles to one by a step of solvent exchange and optional subsequent exposure of the purified saponin product to at least one exposure to dry gas followed by exposure to a vacuum to further rid the purified saponin product of residual solvent molecules.

Saponins, steroid or triterpenoid glycosides found widely in the plant kingdom, have a wide range of medicinal and commercial uses. The saponins of some plant species have been shown to be useful as adjuvants that can be used to enhance immune responses to specific antigens. Some types of plant saponin adjuvants not only enhance immune responses to antigens but can also preferentially induce specific types of cell mediated immune responses.
Current procedures for purifying pharmacologically useful saponins are not optimal in terms of product uniformity, reconstitutability, or homogeneity. In addition, current methods of purifying saponins can take as long as 14 days.
In view of the potential usefulness of immunogenic compositions containing saponins, a need exists for more efficient saponin purification methods.


A method and apparatus for extracting a model vector representation from multimedia documents. A model vector provides a multidimensional representation of the confidence with which multimedia documents belong to a set of categories or with which a set of semantic concepts relate to the documents. A model vector can be associated with multimedia documents to provide an index of its content or categorization and can be used for comparing, searching, classifying, or clustering multimedia documents. A model vector can be used for purposes of information discovery, personalizing multimedia content, and querying a multimedia information repository.

The growing amount of digital information in the form of video, images, textual and other multimedia documents is driving the need for more effective methods for indexing, searching, categorizing, and organizing the information. Recent advances in content analysis, feature extraction, and classification are improving capabilities for effectively searching and filtering multimedia documents. However, a significant gap remains between the low-level feature descriptions that can be automatically extracted from multimedia content, such as colors, textures, shapes, motions, etc., and the semantic descriptions, such as objects, events, scenes, and people, that are meaningful to users of multimedia systems.
The problem of multimedia indexing can be addressed by a number of approaches that require manual, semiautomatic, or fully automatic processing. One approach uses annotation or cataloging tools that allow humans to manually ascribe labels, categories, or descriptions to multimedia documents. For example, authors M. Naphade, C.-Y. Lin, J. R. Smith, B. Tseng, and S. Basu, in a paper entitled "Learning to Annotate Video Databases," IS&T/SPIE Symposium on Electronic Imaging: Science and Technology—Storage & Retrieval for Image and Video Databases X, San Jose, Calif., January, 2002, describe a video annotation tool that allows labels to be assigned to shots in video. The authors also teach a semiautomatic method for assigning labels based on active learning. Fully-automatic approaches are also possible. For example, authors M. Naphade, S. Basu, and J. R. Smith teach, in "A Statistical Modeling Approach to Content-based Video Retrieval," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2002), May, 2002, methods for automatically assigning labels to video content based on statistical modeling of low-level visual features. The automatic labeling technique is useful for allowing searching of video based on the automatically assigned labels, however, the indexing is limited to matching values of a small vocabulary, such that if the user enters a search term that does not match one of the label terms, then the search does not find any target multimedia documents.
Given that automatic systems are improving capabilities for assigning labels, categories, and descriptions to multimedia documents, new techniques are needed that leverage these descriptions to provide more meaningful ways for indexing, searching, classifying and clustering these documents using the descriptions. Furthermore, the systems should take into account the uncertainty or reliability of the automatic systems as well as the relevance of any labels, categories, or descriptions assigned to multimedia documents in order to provide an effective index.
It is, therefore, an objective of the present invention to provide a method and apparatus for indexing multimedia documents using a model vector representation that captures the results of any automatic labeling and its corresponding scores, such as confidence, reliability, and relevance.
It is another objective of the invention to use the model vector representation in applications of information discovery, personalizing multimedia content, and querying of a multimedia information repository.

Method and apparatus for content representation and retrieval in concept model space

International Business Machines Corporation


A radar device derives, plurality of parameters according to a target and target detection distances, based of received signals that are acquired by receiving reflected waves, each of which is a radar transmission wave transmitted toward vicinity of an own vehicle and then reflected from the target existing in the vicinity. The radar device computes, from likelihood models in which first and second already-known correlations are modeled for each of the detection distances, an indicator based on likelihood ratios, which correspond to derived parameters and detection distances, of a stationary vehicle and upper object, in which the first already-known correlations correlate parameters and likelihoods of the stationary vehicle with each other and second already-known correlations correlate the parameters and likelihoods of the upper object with each other. The radar device performs a threshold determination on the computed indicators to determine whether the target is the stationary vehicle or upper object.

Conventionally, a radar device provided in the front side etc. of a body of a vehicle outputs transmission waves within an external transmission range of the vehicle, receives a reflected wave from a target so as to derive target data including position information etc. of the target, thereby discriminating, by using the target data, a stationary vehicle etc. positioning at the forward of the vehicle. The vehicle controlling device provided in the vehicle acquires, from the radar device, information on the stationary vehicle and the like so as to control a behavior of the vehicle based on this information, and avoids a collision with, for example, the stationary vehicle and the like, thereby providing a safe and comfortable travel to a user of the vehicle (see Japanese Laid-open Patent Publication No. 2016-006383, for example).
However, the aforementioned conventional technology has a problem that discriminant precision between a stationary vehicle and an upper object is insufficient, and thus the upper object may be erroneously detected as the stationary vehicle.

Radar device and control method of radar device


The present invention provides for a bicycle rack, which is capable of securely locking bicycles to the rack. The rack comprises a channel member for holding the wheels of the bicycle, the channel member being provided with holes in the region where the bicycle wheels are to be located. The bicycle rack further is provided with a slideable locking member, the slideable locking member having a generally extended U shape and having a central bar region joining two end bars which are insertable through the holes in the channel member. The slideable locking member is movable between a first unlocked position where the end bars are free of the interior of the channel member to allow the bicycle wheels to be located within the channel member and a second locked position where the end bars extend across the interior of the channel and hold the bicycle wheels within the channel member.

There have been many designs of bicycle racks developed with the intention of securely holding bicycles and enabling them to be locked to the rack. Examples of some such designs are shown in U.S. Pat. No. 3,865,244, 3,964,611, 4,136,782, 4,416,379, 5,292,009 and 5,690,259.
U.S. Pat. Nos. 3,865,244 and 3,964,611, both to Galen and Vanderpoel, describe a bicycle rack for supporting a bicycle having a channel member for receiving the front and rear wheels of the bicycle. The bicycle rack has a supporting section fixed to the channel number and a pivotally mounted clamping mechanism for clamping the frame of the bicycle to the support member against movement relative to the support member. Wheel locking bars also provided for clamping the front and rear wheels in the channel member.
U.S. Pat. No. 4,136,782, describes a wall-mounted rack for storing a bicycle. The rack has a horizontal bracket mounted to a wall, the bracket being just wider than the tire of the bicycle to be stored. The rack is also provided with a rail perpendicular to the bracket mounted to the wall, the rail being provided with a slide that can be adjusted along the vertical length of the rail and a hook for suspending the bicycle with the wheels placed upon the horizontal bracket hinged to the slide.
U.S. Pat. No. 4,416,379, describes a bicycle storage device having a wheel-receiving channel adapted to receive the front and rear wheels of the bicycle. The device is provided with a bicycle wheel-engaging hook mounted on one end of the channel to engage the front wheel of the bicycle and support the bicycle within the channel.
U.S. Pat. No. 5,292,009, describes a bicycle rack having channel member with a wall on one side and a stepped base. The bicycle rack has a retaining and locking means o hold a bicycle within the rack.
U.S. Pat. No. 5,690,259, describes a modular bicycle rack system useful for a vehicle having a pair of rooftop transverse load bars spaced along the length of the vehicle. The rack system includes a channel member for containing the wheels of the bicycle and clamping members for clamping the wheels within the channel member and for clamping the frame to the modular bicycle rack system.
There still remains a need for a simple to use bicycle rack which enables storage of a bicycle and which is capable of allowing the bicycle to be locked to the rack.


A system and method for supplying voltage to electrical loads in the onboard electrical system of a motor vehicle are provided. The onboard electrical system consists of at least two onboard electrical system regions. The first onboard electrical system region has an electric generator, a vehicle battery, as well as one or more first electrical loads. The second onboard electrical system region has a double-layer capacitor or a so-called supercap and one or more second electrical loads. Between the two onboard electrical system regions, a blocking device is provided, in particular, a semiconductor diode or a power switch, which permits a current flow from the first onboard electrical system region into the second electrical system region and largely prevents a reverse current flow from the second onboard electrical system region into the first onboard electrical system region. The output voltage of the electric generator is raised and the supercap is charged when a first threshold value of the electric voltage in the second onboard electrical system region is undershot.

The invention relates to a system and method for supplying voltage to electrical loads in the onboard electrical system of a motor vehicle.
In the case of known systems, the generator required for generating the voltage consumes a considerable amount of power, which has to be made available by the engine of the motor vehicle.
It is an object of the present invention to reduce the power to be provided by the motor vehicle engine for supplying the onboard electrical system of the motor vehicle with sufficient electric energy.
This object is achieved by a system and method for supplying the voltage to electrical loads in the onboard electrical system of a motor vehicle. The onboard electrical system includes at least two onboard electrical system regions. The first onboard electrical system region has an electric generator, a vehicle battery, as well as one or more first electrical loads. The second onboard electrical system region has a double-layer capacitor or a so-called supercap and one or more second electrical loads. Between the two onboard electrical system regions, a blocking device is provided, particularly a semiconductor diode or a power switch, which permits a current flow from the first onboard electrical system region into the second electrical system region and largely prevents a reverse current flow from the second onboard electrical system region into the first onboard electrical system region. The output voltage of the electric generator is raised and the supercap is charged when there is a falling below a first threshold value of the electric voltage in the second onboard electrical system region. Advantageous embodiments of the invention are described herein.
According to the invention, the electrical loads in the onboard electrical system of a motor vehicle are divided into a group of at least two types of electrical loads. The first group of electrical (non-sensitive) loads will also operate reliably when there are relatively wide voltage fluctuations and/or when the voltage is relatively low; for example, when, in the case of a 12 volt onboard electrical system, the voltage falls below 10 volts and/or fluctuates between approximately 9 and 16 volts.
In contrast, the second group of electrical (sensitive) loads will operate reliably only when there are relatively slight voltage fluctuations about the nominal voltage; for example, when, in the case of a 12 volt onboard electrical system, the voltage fluctuates only between approximately 11 and 13 volts. According to the invention, the onboard electrical system is divided into at least two electrical system regions; the non-sensitive electrical loads are arranged in the first electrical system region, and the sensitive electrical loads are arranged in the second electrical system region.
A current flow from the second onboard electrical system region into the first onboard electrical system region, according to the invention, is largely prevented by a blocking device or circuit, preferably a semiconductor diode arranged between the first and the second electrical system region. In the first onboard electrical system region, the electric generator and a vehicle battery are arranged in parallel to the first electrical loads, and in the second onboard electrical system region, an energy accumulator, a battery or a capacitor, preferably a double-layer capacitor or a so-called supercap, is arranged in parallel to the second electrical loads. During operation of the motor vehicle, the double-layer capacitor is regularly charged to a voltage which keeps the sensitive second electrical loads ready to operate while it discharges.
During the phases in which the double-layer capacitor does not have to be charged, the voltage of the generator is reduced to such an extent that the operational readiness of the first electrical loads (still) exists (see DE 2006 002 985). In this case, the voltage at the double-layer capacitor is higher than at the first (non-sensitive) loads, and the blocking device or diode prevents the discharge of the double-layer capacitor by way of the loads of the first onboard electrical system region. Inversely, the blocking device permits an electric current flow from the electric generator by way of the blocking device or diode into the second onboard electrical system region when the output voltage of the generator is raised in order to charge the double-layer capacitor.
The monitoring of the charge condition or of the output voltage of the double-layer capacitor takes place by way of a charge control device or a control/power unit which controls the generator such that, when the capacitor voltage falls below a threshold voltage, the generator increases the voltage for charging and subsequently reduces it again.
In contrast to the known state of the art, the generator can be controlled such that, during operation of the motor vehicle, it predominantly provides only a lower voltage for operating the non-sensitive loads. In the case of the known state of the art, it was, however, necessary to lastingly raise the voltage to such an extent that even the sensitive loads always had a sufficient operating voltage available.
Thus, by means of the solution according to the invention, the power consumption of the generator can be reduced for long periods of time and the fuel consumption and the CO2 emission of the motor vehicle can thereby clearly be reduced.
In a particularly advantageous embodiment of the invention, it is provided that precharging and/or coupling or separating of the supercap to the onboard electrical system or from the onboard electrical system takes place by a separate control/power unit. The control/power unit preferably also carries out the diagnosis of the supercap, particularly a capacitance and/or resistance determination, during the precharging operation. As a result of this measure, the supercap can be smoothly integrated into the onboard electrical system of a vehicle.
In a further development of the invention, it is provided that, during precharging or charging of the supercap to the onboard electrical system voltage of the second electrical system region, the temperature of the supercap is measured and is compared with a maximal value. As an alternative or in addition, a fault memory assigned to the supercap is read out, preferably in the control/power unit.
According to the invention, the fault memory preferably has a fault input if, in the past, a comparison of the capacitance (C) values present at the time and/or of the resistance (R) values of the supercap with stored temperature-dependent or charging-current-dependent characteristic values of the supercap pointed to the presence of a fault at the supercap. On the basis of these diagnoses, disturbances of the onboard electrical system as a result of a faulty supercap can be avoided.
In the case of a preferred further development of the system according to the invention, it is provided that, when the supercap falls below a maximal temperature value and the fault input is absent, the supercap is charged to the actual voltage of the second onboard electrical system region or to largely the actual voltage of the second onboard electrical system region, before the supercap is electrically connected with the second onboard electrical system region. The supercap subsequently stabilizes the voltage in the second onboard electrical system region. This measures allows a careful coupling of the supercap to the electrical system of the vehicle.
As a further development of the invention, it is provided that, when the terminal R and/or the terminal 15 are currentless and/or the doors are locked for longer than a predetermined time period, the supercap is discharged to approximately 9 volts by way of a feed back into the onboard electrical system, and is then electrically uncoupled from the onboard electrical system. As a result, a careful uncoupling of the supercap from the onboard electrical system is achieved, and the electrical system is relieved because of the otherwise high quiescent current requirement of the supercap.
In addition, by way of the above-mentioned measures, the charging operation is optimized, particularly with respect to a further reduction of the CO2 emission.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of one or more preferred embodiments when considered in conjunction with the accompanying drawings.

System and method for supplying voltage to electrical loads of a motor vehicle by using a supercap

Bayerische Motoren Werke Aktiengesellschaft


The present invention is directed to a control system which interfaces a plurality of telephones, referred to as extensions, to a central office telephone line. The control system includes a ring detector, a ring generator, a controller and a telephone extension bus. In accordance with one embodiment of the present invention, the control system is programmable to: (i) control the ringing function of a plurality of extensions when an incoming call is received; (ii) control the staging of the ringing function of a plurality of extensions when an incoming call is received; (iii) control the use of one or more of a plurality of extensions to initiate an outgoing call; (iv) control the use of one or more of a plurality of extensions when another extension is in-use, i.e. presently being used to engage in an ongoing telephone call; (v) control the use of one or more of a plurality of extensions when another extension is being used for a data call, i.e., a data transmission or communication between machines including, for example, facsimile machines and computers; and (vi) control access to a central office telephone line by one or more extensions when another extension is in-use.

Generally, residential telephone service is provided via a central office telephone line which electrically connects a residence to a central office switch. This connection, which is usually made to the residence at a location known as the protector block, enables a residential telephone to be used to communicate with others via the central office switch. Typically, multiple telephones, referred to as extensions, are located throughout the residence and are all individually electrically connected to the protector block (i.e., a "home run" connection) or are connected to each other (i.e., "parallel" connection). Thus, any one of a plurality of extensions located in, for example, the kitchen, living room, family room, study, bedrooms, basement, garage, or workshop, can be used to answer incoming calls from others or initiate outgoing calls to others, via the central office telephone line. Multiple extensions are desirable because they provide easy access to answer or initiate telephones calls, regardless of a person's location in the residence.
Electrically connecting multiple extensions to a central office telephone line causes all such extensions to ring to indicate the presence of an incoming call. In this regard, an extension's ringer is driven by a nominal voltage, usually 86 volts rms at 20 hertz, superimposed temporarily on the central office telephone line by the central office switch to indicate the presence of an incoming call. It is sometimes undesirable to ring all extensions in a residence when an incoming call is received, including for example, ringing an extension in a child's bedroom when the child is studying; or ringing a extension in a bedroom when a family member is asleep. Further, it is sometimes undesirable to ring all extensions during certain times of the day when persons within the residence tend to congregate in particular areas of the residence, including for example, ringing bedroom, study, workshop extensions, during times when family members are likely to be eating dinner in the kitchen; or ringing bedroom, workshop, kitchen extensions during times when the only family member present is likely to be in the study.
Electrically connecting multiple extensions to a central office telephone line also allows all such extensions to be used to initiate an outgoing call, via the central office telephone line. In this regard, any extension can be used to initiate an outgoing call by taking the extension's hand set off-hook to obtain central office dial tone and dialing a number sequence corresponding to a called party's telephone number. It is sometimes undesirable to allow multiple access to the central office telephone line by all the extensions, including for example, allowing an extension in a child's bedroom to be used to initiate an outgoing call during times when the child should be studying.
Electrically connecting multiple extensions to a central office telephone line also allows such extensions to access the central office telephone line when another extension is in-use, i.e., presently being used to engage in an ongoing call. Consequently, the possibility arises that a second user may disrupt a first user's ongoing call by attempting to initiate an outgoing call at another extension. For example, a second family member may disrupt a first family member's ongoing call by taking an extension's hand set off-hook and attempting to dial a telephone number, without realizing that the first family member is already engaged in a call.
Typically, residential telephone service is used for voice calls. However, residential telephone service is increasingly being used for data calls, i.e., data transmissions and communications between machines including, for example, facsimile machines and computers. In this regard, it is becoming more common for a central office telephone line to be electrically connected to, for example, a computer for the purpose of allowing a user of the computer to navigate the Internet, send or receive e-mail messages, or send or receive facsimiles. Providing multiple extensions within a residence raises the possibility that a data call at one extension may be appreciably disrupted by an attempt to initiate an outgoing call at another extension. For example, a second family member disrupting, e.g. disconnecting, a first family member's facsimile transmission by taking an extension's hand set off-hook and dialing a telephone number, without realizing that the first family member is engaged in a data call.

Apparatus for telephone extension control