The present invention relates to a multi piece trunnion. More specifically, this invention relates to a multi piece trunnion for use in scissor-type jacks. The multi piece trunnion allows the use of a trunnion segment with an enlarged center section without a corresponding increase in the size of the channel members of the jack. The enlarged trunnion segment increases the load capacity if the scissor jack without a significant size or weight increase.

Scissor-type jacks are used to apply force to lift many objects including motor vehicles. Many auto manufacturers include scissor type jacks as standard equipment for emergency tire changes. The compact size and ease of use make scissor-type jacks a popular choice for this type of application.
Generally, prior art scissor jacks include one pair of upper channel members and one pair of lower channel members, a base plate, a load bearing plate, pivot pins and a screw bar. The top ends of the upper channel members are pivotally mounted to a load bearing plate. The bottom ends of the lower channel members are pivotally mounted to a base plate. Each upper channel member is pivotally engaged to a lower channel member using a cylindrical pivot pin. These pins are herein referred to as trunnions. The trunnions have a centrally located through hole disposed perpendicular to their longitudinal axis.
A common scissor type jack employs one trunnion in which the through hole is threaded, and one trunnion with a plain through hole. A screw bar that is threaded on one end is placed through the plain through hole in one trunnion and is threadably engaged in the threaded trunnion. The trunnions are typically inserted through the channel members by way of circular holes formed in each of the opposed planar sides of each channel member. These holes are limited in size by the size of the channel members, as too large a hole would adversely weaken the channel members. The hole size in the channel limits the diameter of the cylindrical trunnion that can be inserted into the hole. The diameter of the cylindrical trunnion limits the diameter of the through hole centrally located in the trunnion, and also limits the length of engagement of the internal threads that are disposed in the hole of the threaded trunnion. In turn, the diameter of the through hole located in the threaded trunnion limits the diameter of the screw bar.
All of these limitations dictate the load capacity of the jack. Destructive testing has shown that a typical failure location for a scissor jack occurs at the internal threads of the threaded trunnion. Therefore, it would be desirable to increase the thread area of the threaded trunnion, thereby increasing the length of engagement between the threaded trunnion and the screw bar, which would increase the load capacity of the jack. The easiest way to accomplish this is to increase the diameter of the cylindrical trunnions, thus allowing a longer through hole and therefore more threads. This however would require an increase in the size of the channel members to accommodate the larger hole required for the larger diameter cylindrical trunnions. Such a size increases would demand more storage space be allotted in the trunk of a vehicle for the larger jack, and the corresponding increase in weight would be undesirable by making the jack more difficult to maneuver and operate.
An alternate method of increasing the length of thread engagement requires that a tube with internal threads be affixed to the cylindrical trunnion. This is disclosed in U.S. Pat. No. 5,449,149. This method makes the jack more difficult to manufacture. Using a finer thread pitch on the screw bar and in the threaded trunnion would also increase the strength of the threaded connection, but would require more revolutions of the screw bar to achieve the same vertical displacement. Therefore, it would be desirable to increase the load carrying capacity of the jack without a dramatic increase in the weight of the jack, and without making the use and manufacture of the jack more complex.
The cylindrical trunnions are secured in place by a variety of methods including spring clips, bolts, nuts and swaging the ends of the trunnion. These methods also strengthen the channel member by creating a flange surface to prevent the channel sides from spreading under a load. However, these methods all add parts and/or production steps. Therefore, it would also be desirable to have a method to secure the trunnions with a flange formed integrally to the trunnion.
In light of the deficiencies in prior art, the applicants' invention is herein submitted.

Multipiece trunnion for a scissor type jack


An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

1. Field of the Invention
The present invention relates to a method of fabricating a low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD), and more particularly, to a method of fabricating a LTPS TFT-LCD composed of P-type LTPS TFT by utilizing seven photo-etching processes (PEPs).
2. Description of the Prior Art
Currently, liquid crystal displays (LCDs) represent a commona flat panel display technology. Applications for LCDs are extensive and include mobile phones, digital cameras, video cameras, notebooks, and monitors. Due to high quality display requirements and the expansion of new application fields, the development of LCDs have found on the following criteria: high resolution, high brightness, and low price. Development of LTPS TFTs, being actively driven, has been a break-through in achieving the above objectives. Therefore, technological innovation based on the LTPS TFT concept has become an important subject for further development.
Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are schematic diagrams of a method for forming a LTPS TFT-LCD according to a prior art. The prior art LTPS TFT-LCD 98 is formed on an insulation substrate 10. The insulation substrate 10, composed of transparent materials, may be a glass substrate or a quartz substrate. A pixel array area 11 and a periphery circuit area 13 are formed on a surface of the insulation substrate 10.
As shown in FIG. 1, an amorphous silicon (α-Si) thin film (not shown) is first formed on the surface of the insulation substrate 10. Then, an excimer laser annealing (ELA) process is performed to re-crystallize the amorphous silicon thin film into a polysilicon layer (not shown). A first photo-etching processes (PEP-1) is thereafter performed to define an active area 12 in the pixel array area 11 and at least one active area 14 in the periphery circuit area 13. A source region (not shown), a drain region (not shown), a channel region (not shown), and a predetermined region for a bottom storage electrode (not shown) are formed in the active area 12; a source region (not shown), a drain region (not shown), and a channel region (not shown) are formed in each active area 14.
As shown in FIG. 2, a second photo-etching process (PEP-2) is performed to form a photoresist layer 16 on the top surface of the insulation substrate 10. The photoresist layer 16 is used to define the location for the bottom storage electrode 18 in the pixel array area 11. After that, an ion implantation process is performed to add high concentration N-type dopants into the exposed portion of the active area 12 in the pixel array area 11, completing the fabrication of the bottom storage electrode 18.
The photoresist layer 16 is removed. As shown in FIG. 3, an isolation layer 22 and a first conductive layer (not shown) are formed on a surface of the entire structure sequentially. Then a third photo-etching process (PEP-3) is performed to simultaneously form a gate electrode 24 of a TFT, a top storage electrode 26 on the bottom storage electrode 18 in the pixel array area 11, a gate electrode 28 of an NMOS and a gate electrode 32 of a PMOS in the periphery circuit area 13.
As shown in FIG. 4, an etching process is performed, by utilizing the gate electrodes 24, 28, 32, and the top storage electrode 26 as etching masks, to remove portions of the isolation layer 22 to form the gate insulating layers 34, 36, 38, and the capacitor dielectric layer 42. The manufacturing of the storage capacitor 44 is thus completed.
After that, an ion implantation process, by utilizing the gate electrodes 24, 28, 32 as masks, is performed to dope low concentration N-type ions into the active areas 12, 14 at either side of the gate electrodes 24, 28, 32 to form lightly doped drains (LDDs) 46, 48, 52. Due to the low concentration N-type ions implanted in this ion implantation process, the doping concentration of the bottom storage electrode 18 is not affected.
As shown in FIG. 5, a fourth photo-etching process (PEP-4) is performed to form a photoresist layer 54 on a surface of the entire structure. The photoresist layer 54 covers the gate electrode 24 and the predetermined region for a lightly doped drain 56 in the pixel array area 11 and simultaneously covers the predetermined region for a PMOS in the periphery circuit area 13. An ion implantation process is thereafter performed to dope high concentration N-type ions to form a source electrode 62 and a drain electrode 64 of a TFT 58 in the active area 12 in the pixel array area 11 and simultaneously form a source electrode 68 and a drain electrode 72 of an NMOS 66 in the active area 14 in the periphery circuit area 13.
The photoresist layer 54 is removed. As shown in FIG. 6, a fifth photo-etching process (PEP-5) is performed to form a photoresist layer 74 on a surface of the entire structure. The photoresist layer 74 exposes the predetermined region for the PMOS 76 in the periphery circuit area 13. After that, an ion implantation process is performed to dope high concentration P-type ions to form a source electrode 78 and a drain electrode 82 of the PMOS 76 in the active area 14 in the periphery circuit area 13. Due to the high concentration P-type ions implanted in this ion implantation process, the previously formed N-type lightly doped drain 52 (shown in FIG. 5) is compensated and the source electrode 78 and the drain electrode 82 are thus formed.
The photoresist layer 74 is then removed. As shown in FIG. 7, an isolation layer 84 is formed on a surface of the entire structure. The isolation layer 84 covers the gate electrodes 24, 28, 32 and the top storage electrode 26. Then a sixth photo-etching process (PEP-6) is performed to remove portions of the isolation layer 84 to form a plurality of contact holes 85. The contact holes 85 are electrically connected to the source electrodes 62, 68, 78 and the drain electrodes 72, 82, respectively. A source wire 86, electrically connected to the source electrode 62, is formed on top of the isolation layer 84 in the pixel array area 11. Source wires 88, electrically connected to the source electrodes 68, 78 respectively, are formed on top of the isolation layer 84 in the periphery circuit area 13. A wire 92 electrically connecting the NMOS 66 to the PMOS 76 is formed to complete the manufacturing of the CMOS.
As shown in FIG. 8, an isolation layer 94 is formed on a surface of the entire structure to cover the isolation layer 84, the source wires 86, 88, and the wire 92. A seventh photo-etching process (PEP-7) is performed to remove portions of the isolation layer 94 to form a contact hole 95. The contact hole 95 extends downward and is electrically connected to the drain electrode 64. A transparent conductive layer is thereafter formed on the isolation layer 94. Finally, an eighth photo-etching process (PEP-8) is performed to remove portions of the transparent conductive layer to form a pixel electrode 96 on the isolation layer 94. The pixel electrode 96 is electrically connected to the drain electrode 64 downward though the contact hole 95 filled with the transparent conductive layer (not shown) to complete the fabrication of the LTPS TFT-LCD 98.
However, the prior art method for forming the LTPS TFT-LCD results in a very severe problem. When forming the bottom storage electrode, the source electrode, the drain electrode, and the lightly doped drain electorde, three different photoresist layers and four different ion implantation processes required. When forming each photoresist layer, a photolithography process that tends to cause alignment error is required. After so many and complicated photolithography processes, defects are unavoidable in the product. Specifically, the alignment errors incurred from forming the gate electrode and the alignment errors incurred from forming the source electrode and the drain electrode of the thin film transistor in the pixel array area often result in the lightly doped drain having an uneven width. The asymmetric lightly doped drain cannot inhibit the hot electron effect. Moreover, an early breakdown of the device is likely to happen.
Furthermore, the prior art method for forming the LTPS TFT-LCD, following the integrated circuits industry, integrates CMOS. However, with both the NMOS and the PMOS in the circuits, it is impossible to decrease the number of photolithography and ion implantation processes. In addition, the magnitude of the leakage current of the N-type LTPS TFT is difficult to control, resulting in problems in image quality when the N-type LTPS TFT is used in the pixel array area. Therefore, it is very important to develop a method of forming a LTPS TFT-LCD having reduced manufacturing complexity and fewer photolithography processes to lower the probability of misalignment, improve the device defect problem, and improve production yield and image quality.

Method of forming a liquid crystal display


A battery pack (110) comprises a discharge current acquisition component (11), a status acquisition component (12), a similarity calculator (112), and a use application determination component (113). The discharge current acquisition component (11) acquires the current value of a discharge current supplied to a vehicle (30). The status acquisition component (12) acquires the speed of the vehicle (30) operated by the current value acquired by the discharge current acquisition component (11). The similarity calculator (112) compares the current value acquired by the discharge current acquisition component with the speed of the vehicle (30) acquired by the status acquisition component (12), and calculates the similarity between the two. The use application determination component (113) determines whether or not the battery pack is being used for something other than its intended use application, according to the similarity calculated by the similarity calculator (112).

In recent years, a system has been constructed in which a battery pack installed in a vehicle such as an electric motorcycle or an electric bicycle is used and then exchanged at a battery station where charged battery packs are available.
When a battery pack is thus rented out, there is the risk that it may be used for something other than in a vehicle or other specific power consumption element. If this happens, as a result of using the power of the battery pack for something other than a specific use application, there may be problems, such as a decrease in how accurately the service life of the battery can be predicted, or being unable to ensure the original battery performance (output, capacity, etc.).
For example, Patent Literature 1 discloses a system that permits the functioning of a vehicle according to preset permission information. With this vehicle function permission system, a user who has rented a vehicle can use it within the range of what has been permitted in advance by the owner.

Battery pack, battery system comprising the same, and method for distinguishing use application of battery pack


A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

The present generally relates to semiconductor devices and more particularly to a miniaturized high-speed semiconductor device and a fabrication process thereof.
With the development in the art of device miniaturization, the operational speed of field-effect semiconductor devices such as a MOS transistor is increasing every year. On the other hand, such an extremely miniaturized semiconductor device tends to suffer from the problem of so-called short-channel effect, which appears conspicuously in such a miniaturized device having a short gate length, due to the deviation from the classical gradual channel approximation model. When a short-channel effect appears, there arise problems such as deviation of threshold voltage. In the worst case, the drain current becomes no longer controllable by the gate voltage.
Thus, it has been practiced in conventional miniaturized field effect semiconductor devices to reduce the thickness of diffusion regions as small as possible in correspondence to the reduced gate length of the device.
As such an extremely shallow diffusion region tends to cause a problem of increased resistance, it is proposed to provide a layer of low-resistance silicide such as CoSi2 on the surface of the diffusion region by conducting a self-aligned process. See for example Japanese Laid-Open Patent Publication 7-115198.
Meanwhile, there is proposed a process of forming an extremely miniaturized semiconductor device that includes a self-aligned contact structure. See for example Japanese Laid-Open Patent Publication 8-274278.
FIGS.1A-1H show the foregoing conventional process of forming a self-aligned contact structure.
Referring to FIG. 1A, a gate oxide film 2 and a field oxide film 2A are formed on a p-type Si substrate 1, and a polysilicon layer 3 is deposited on the structure of FIG. 1A in the step of FIG. 1B. The polysilicon layer 3 thus deposited is then doped to the n+-type by an ion-implantation of P+ ions and patterned in the step of FIG. 1C to form a gate electrode 3A. In the step of FIG. 1C, an ion implantation process of As+ is further conducted while using the gate electrode 3A as a mask, to form shallow diffusion regions 1A and 1B of the n+-type at both lateral sides of the gate electrode 3A by a self-alignment process.
Next, in the step of FIG. 1D, an SiO2 film is deposited on the structure of FIG. 1C uniformly by a CVD process, followed by an anisotropic etching process acting substantially perpendicularly to the surface of the substrate 1 to form side wall oxide films 3a and 3b on both side walls of the gate electrode 3A. Further, additional diffusion regions 1C and 1D are formed so as to partially overlap the diffusion region 1A or 1B by conducting an ion-implantation process of As+ while using the gate electrode 3A and the side-wall oxide films 3a and 3b as a mask, to form a so-called LDD (lightly doped drain) structure.
Next, in the step of FIG. 1E, an SiN film 4 is deposited uniformly on the structure of FIG. 1D by a CVD process or a sputtering process, followed by the step of FIG. 1F in which an interlayer insulation film 5 of SiO2, PSG or BPSG is deposited on the foregoing SiN film 4. The interlayer insulation film 5 is further formed with a contact hole 5A in correspondence to the diffusion region 1C by an anisotropic dry etching process. Similarly, a contact hole 5B is formed in the insulation film 5 in correspondence to the diffusion region 1D. The contact hole 5A or 5B may be formed with a size sufficiently larger than the size of the corresponding diffusion region 1C or 1D and can be formed easily by a photolithography without experiencing a difficulty of resolution limit, which generally arises when forming a deep contact hole.
The dry etching process for forming the contact holes 5A and 5B stops spontaneously upon the exposure of the underlying SiN layer 4 as indicated in FIG. 1F. Thus, a step of FIG. 1G is conducted for removing the exposed SiN film 4 by an etching process. Further, a step of FIG. 1H is conducted for removing a part of the gate oxide film 2 that is now exposed at the bottom of the contact holes 5A and 5B, by conducting a selective etching process with respect to the Si substrate 1. As a result of the step of FIG. 1H, minute openings 1c and 1d respectively exposing the diffusion regions 1C and 1D are formed.
It should be noted that the opening 1c is defined by the field oxide film 2A and the side wall oxide film 3a. Similarly, the opening 1d is defined by the other field oxide film 2A and the side wall oxide film 3b. In other words, the openings 1c and 1d are formed in a self-aligned manner, without using a mask process. This means that the openings 1c and 1d can be formed reliably and with reproducibility without restrained from the problem of resolution limit of exposure even when the semiconductor device is extremely miniaturized. Further, as explained already, it is not necessary to miniaturize the contact holes 5A and 5B. Thus, the photolithography for forming the contact holes 5A and 5B can be conducted easily.
Thus, the foregoing self-aligned process of FIGS. 1A-1H is advantageous for forming extremely miniaturized semiconductor devices. As already noted, it is desired in such extremely miniaturized high-speed semiconductor devices to form a low-resistance silicide layer on the surface of the diffusion regions 1C and 1D so as to compensate for the unwanted increase of the resistance, which tends to occur in such extremely shallow diffusion regions.
One possibility of forming such a silicide layer may include the steps of: removing the gate oxide film 2 for the part covering the diffusion regions 1C and 1D; depositing a metal layer of Co or Ti on the exposed surface of the diffusion regions 1C and 1D; and forming a silicide in a self-aligned manner by causing a reaction between the metal layer and the diffusion region. The remaining metal layer may be removed by an etching process. See for example the process disclosed in the Japanese Laid-Open Patent Publication 7-115198.
In such a conventional process of forming a silicide layer, however, there is a substantial risk that the etching process, used in the step of FIG. 1G for removing the SiN film 4 from the bottom of the contact holes 5A and 5B, may proceed further to the diffusion region 1C or 1D and cause a damage thereto.
In order to be sure that such a damage is not to be caused, it is necessary to deposit another SiO2 film in the step of FIG. 1E before depositing the SiN film 4, as an etching stopper. It should be noted that the additional SiO2 film acts as an etching stopper for the etching process employed for removing the SiN film 4, and the problem of damaging of the diffusion region 1C or 1D is positively eliminated. Further, such an additional SiO2 film can be easily removed by a selective etching process without causing a damage to the diffusion region 1C or 1D.
It is generally practiced to form such an SiO2 etching stopper layer by a CVD process. In the case of the a semiconductor device in which the silicide layer is formed on the surface of a shallow diffusion region, however, there is a substantial risk that the metal elements constituting the silicide may cause a diffusion and reach the Si substrate because of the high deposition temperature employed in the CVD process. Thus, it has been necessary to form the additional SiO2 film by using a plasma CVD process at a low temperature of typically about 500° C. or less.
On the other hand, the SiO2 etching stopper film thus deposited at a low temperature plasma CVD process tends to contain H2O therein. As the SiO2 etching stopper is covered by the SiN film 4 in the step of FIG. 1G, it is difficult for the H2O molecules in the SiO2 etching stopper film to escape therefrom once covered by the SiN film 4. Thereby, the H2O molecules tend to be confined in the SiO2 film in the form of OH and H ions. It should be noted that the OH ions in the SiO2 etching stopper film, when reached to a region close to the gate oxide film 2 by way of diffusion, may form a surface state which captures electrons.
FIG. 2 shows an example of the self-aligned contact structure that uses an SiO2 etching stopper film, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2, there is provided an etching stopper film 6 of SiO2 on the gate oxide film 2 by a low temperature plasma CVD process such that the SiO2 film 6 covers the gate electrode 3A including the side wall oxide films 3a and 3b. Further, the SiN film 4 is provided so as to cover the SiO2 film 6.
In such a structure, the escaping of H2O from the SiO2 film 6 is difficult as already noted, due to the existence of the SiN film 4 covering the SiO2 film 6. Thus, there is a substantial risk that the OH ions confined in the SiO2 film 6 cause a diffusion toward the interface between the gate oxide film 2 and the Si substrate 1. As noted already, the OH ions thus reached the foregoing interface may form a surface state that captures electrons, particularly the hot electrons created in the channel region right underneath the gate electrode 3A. The capturing of the hot electrons by the surface state may in turn cause an unwanted shift of threshold voltage of the semiconductor device.
It should be noted that the self-aligned contact structure of FIGS. 1A-1H may also be used in a high-speed semiconductor memory device that has a so-called local interconnection structure such as SRAM. In the semiconductor device having such a local interconnection structure, there tends to occur a reaction between the metal layer forming the local interconnection structure and a silicide that is formed on the surface of the diffusion region. In order to avoid the foregoing problem, it is necessary to conduct the deposition of the etching stopper film 6 at a low temperature. However, such a low temperature deposition of the SiO2 etching stopper film 6 causes the problem explained above.

Method for fabricating a semiconductor device having an insulation film with reduced water content


A bearing assembly comprises a pair of relatively rotatable bearing components, where at least a portion of one of the bearing components is journalled to at least a portion of the other one of the bearing components. One of the first bearing component includes an outer, annular journalled surface and the second bearing component includes an inner, annular journalled surface, and one of the outer or inner and inner journalled surfaces include a plurality of recesses disposed there about. Each of the plurality of recesses are filled with an insert formed from a solid, abrasion resistant, self lubricating material; and the insert protrudes outwardly from the recesses, thereby providing a bearing surface for wearing against the other one of the annular journalled surfaces. Preferably, the solid, abrasion resistant, self-lubricating material is a polyamide resin material.

The present invention relates to a journal bearing assembly and to a method for fabricating the journal bearing assembly.
Shear shredder machines, briquetting machines, grinding machines, and other types of material processing machines typically use a pair of co-acting, substantially parallel, counter-rotating roller assemblies. For example, U.S. Pat. No. 5,484,112 and U.S. Pat. App. Ser. No. 09/032,388, filed Feb. 27, 1998 (docket number 511515-028C1) disclose a modular material processing apparatus that includes a pair of co-acting, substantially parallel, counter-rotating roller assemblies, where each of the roller assemblies includes a substantially cylindrical, material processing roller member mounted to a rotating shaft which extends substantially parallel with the longitudinal sides of the frame of the apparatus. Each of the roller assemblies are supported onto the frame by a pair of supports, a first support mounted to one lateral end of the frame and a second support is mounted to the opposite lateral end of the frame. Each of the supports include a bearing housing journalling a cylindrical bearing member mounted or keyed to the shaft of the associated roller assembly.
Conventional bearing assemblies for use with such material processing apparatuses commonly utilize roller-bearing components, such as tapered roller bearings. A disadvantage with such roller-bearing components is their expense and relatively short life span. Another disadvantage of such roller-bearing components is that they provide a limited surface area for bearing the load of the rotational member. Accordingly, it is desirable to provide a bearing assembly which has a greater life span than the comparably size roller-bearing assemblies, that is less expensive than conventional roller-bearing assemblies, and which provides a greater surface area to bear the load of the rotating members.

c/o Komar Industries, Inc. 4425 Marketing Pl.


A rearview system component for a vehicle including a housing for attachment to the vehicle, a camera positioned in the housing to have a first axial direction, a first sensor positioned in the housing to have a second axial direction, and a second sensor positioned in the housing to have a third axial direction, wherein the first, second and third axial directions are in different directions.

1. Field of the Invention
The present invention relates to a rearview system for vehicles, and more particularly, to a rearview camera and sensor system for vehicles.
2. Discussion of the Related Art
In general, a camera or a sensor is used to detect an object behind vehicles. Typically, large vehicles, such as SUVs, or vehicles with trailers have a large blind spot behind them. Regardless of whether a mirror is used, a driver can have difficulties in judging distances between an object and the rear of a vehicle. A rearview camera is used to visually detect an object and a rearview sensor is used to electronically detect an object.
A rearview camera gives a clear indication of an object behind the vehicle as well as the relative location of the object behind the vehicle. However, a camera's perspective of an object does not clearly convey the distance of the object. In addition, a camera's field of view can have such a wide field of view such that the image is distorted. A non-distorted image can be generated if camera's field of view is very narrow to generate.
A rearview sensor, such as an infrared or sonic sensor, can accurately determine the distance of an object only within a field of view that is significantly less than 180°. Thus, there can be blind spots even when a sensor is used. Further, a sensor can not indicate the actual location of an object behind a vehicle. In other words, a sensor indicates the presence of an object within the field of view for the sensor but does not indicate where the object is located in the field of view.

Rearview camera and sensor system for vehicles


Novel squaraine dyes and compositions of matter containing such dyes are disclosed . The novel squaraine dyes have an absorption maximum greater than 600 nanometers and are particularly useful in conjunction with a helium/neon (He/Ne) laser. Some of the squaraine dyes are hydrophilic and are therefore water soluble or water compatible and others of the squaraine dyes are lipophilic.

1. Field of the Invention
This invention relates to squaraine dyes and compositions of matter containing such squaraine dyes. Squaraine dyes have a structural element of cyclobutenolate, generally being a condensation product of squaric acid (dihydroxycyclobutenedione) and an active compound such as a pyrrole or an aniline. Squaraine dyes have been found to have a number of uses based on their unique properties. One such use involves layered photo responsive imaging devices. Such devices are responsive to visible light and infrared illumination needed for laser printing.
Many of the known squaraine dyes are fluorescent compounds absorbing light in the wavelength region of from about 400 to about 1000 nanometers. Consequently, another use that has been proposed for squaraine dyes is in the area of assays. Fluorescent compounds have achieved wide application in assays because of their ability to emit light upon excitation with energy within certain energy ranges. By virtue of this ability, fluorescers have found employment as labels in chemical or biological processes. Various compounds can be conjugated to fluorescent compounds, the conjugate subjected to some type of partitioning, and the fate of the conjugate determined by irradiating the sample with light and detecting the zone in which the conjugate exists. Fluorescent labels find use in immunoassays, involving specific binding pairs, such as ligands and receptors, for example, antigens and antibodies. For such use, the fluorescent compounds preferably are soluble in an aqueous medium or at least water compatible.
Another use of fluorescent compounds is to incorporate such compound into a cell wall or a liposome. The cell or the liposome with the fluorescent compound incorporated therein can also be employed in assays. For example, dyes incorporated into cell membranes are useful in the area of blood typing where a change in fluorescence as a result of agglutination of cells is determined. Liposomes containing fluorescent dyes also find use in the assay area, particularly in immunoassays. For this purpose it is desirable that the fluorescent dyes be lipophilic.
Laser beams find use in the assay area as means for irradiating a fluorescent compound. In the field of assays it is important to avoid contributions to a signal produced in relation to the amount of analyte, which contributions result from other than the analyte. For example, serum or plasma from a patient is often used to conduct the assay. Serum is itself fluorescent. The materials that cause fluorescence in serum or plasma normally absorb light at a wavelength below 600 nanometers. Therefore, it is desirable to employ fluorescent dyes in fluorescent assays that have an absorption maximum greater than 600 nanometers. It is also desirable to employ a laser beam to provide the source of energy for activation of the fluorescent dye. One such laser is the helium/neon laser which emits light at 633 nanometers.
2. Description of the Related Art
Various squarate dyes are discussed by Sprenger, et al., Angew. Chem., 80, 541 (1968); Sprenger, et al., Angew. Chem., 79; 581, 1967; Sprenger, et al., Angew. Chem. Internat. Edit., 5:894, 1966; and Maaks, et al., ibid., 5:888, 1966.
Novel unsymmetrical squaraine systems are disclosed in U.S. Pat. No. 4,521,621. A process for the preparation of squaraine compositions in the presence of an amine component is disclosed in U.S. Pat. No. 4,524,220. A process for preparation of squaraine compositions is disclosed in U.S. Pat. No. 4,525,592. A process for preparation of squaraine compositions from half esters of squaric acid is disclosed in U.S. Pat. No. 4,524,219. Processes for the preparation of squaraine compositions are described in U.S. Pat. No. 4,524,218. A process for the recovery of high purity squaric acid is described in U.S. Pat. No. 4,523,980. Amine derivatives of squaric acid are described in U.S. Pat. Nos. 4,123,270, 4,353,971, 3,838,095, and 3,824,099.


An automated insurance quote system allows users to apply for one or more insurance quotes through a self-service communication channel. The system includes an interface that may receive applicant data from a remote location. A front-end processor selectively passes applicant data to a record keeping system retained in a memory. A controller or quote processors selects and transmits one or more insurance policies that are allowed under a user's governmental law and are tailored to the user's price and/or coverage preferences. The system conveys coverage details to users through the interface.

1. Technical Field
This application relates to insurance, and more particularly to customizing an insurance quote online.
2. Related Art
Insurance companies insure against risk in return for a premium. The companies may offer a limited number of policies that bind them to indemnify against specific losses. Many companies offer different types of coverage at different prices. These coverages are actuarially priced and these rates are typically filed with the Department of Insurance in a given state.
While some minimum insurance coverage amount may be required by state regulations, many users must choose from quotes that also include various coverages in various limits or amounts. These users, when utilizing a self-service channel, may find it difficult to build or modify the coverages to suit their individual needs.


A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.

Voltage reference circuits and biasing circuits of one form or another exist in many integrated circuits, and are especially common in large integrated circuit applications such as memories. In order to supply stable biasing and reference voltages, the power supply voltage must be stable and consistent throughout the integrated circuit memory. The power supply voltage is usually distributed across the integrated circuit by metal power supply lines, or conductors. As the length of these relatively thin metal lines increases, the resistance and capacitance between the connection point and the outside supply increases. The amount of voltage drop depends on the amount of current flowing through the conductor and the resistance of the conductor. In an integrated circuit memory the amount of current flow varies, causing voltage fluctuations at the demand end of the conductor. Normally, the voltage drop along a power supply conductor is reduced by making the metal lines of the power supply conductors as wide as possible. But there is a tradeoff between the width of the metal lines and integrated circuit size. Size constraints do not normally allow the metal lines to be wide enough to reduce the series resistance and capacitance enough to provide a power supply voltage adequate to guarantee proper operation of the integrated circuit at very high speeds.
The power supply lines can also be a source of noise on an integrated circuit memory. The noise immunity of an integrated circuit is commonly specified in terms of noise margins. Noise margins are usually given for worst case conditions, which includes the most unfavorable connections of the input terminals and the poorest combination of circuit and device parameters, along with a maximum fan-out. As the operating speed of an integrated circuit memory increases, the negative effects of noise or a voltage drop in the power supply increase. The more noise or voltage drop there is on the power supply lines, the smaller the range of variability allowed in the reference and bias voltages because the memory must operate within narrower margins.
The introduction of the so called revolutionary pinout technique has alleviated some of the problems with power distribution on integrated circuit memories by decreasing the power supply conductor lengths and increasing the number of power supply bonding pads and power supply pins. But increasing the size and density of the integrated circuit memory have correspondingly caused an increase in the length of the power supply conductors. Nevertheless, as higher speeds are demanded of integrated circuit memories, any power supply variations that interfere with system operation become intolerable. The biasing and reference voltage generation circuits must remain stable and must supply constant voltage levels in order to insure accurate system operation.

Memory having distributed reference and bias voltages


A wireless actuation system comprises a transmitter, an actuation system comprising a receiving antenna, and one or more sliding members transitional from a first position to a second position. The transmitter is configured to transmit an electromagnetic signal, and the sliding member prevents a route of fluid communication via one or more ports of a housing when the sliding member is in the first position. The sliding member allows fluid communication via the one or more ports of the housing when the sliding member is in the second position, and the actuation system is configured to allow the sliding member to transition from the first position to the second position in response to recognition of the electromagnetic signal by the receiving antenna.

When wellbores are prepared for oil and gas production, it is common to cement a casing string within the wellbore. Often, it may be desirable to cement the casing string within the wellbore in multiple, separate stages. The casing string may be run into the wellbore to a predetermined depth. Various "zones" in the subterranean formation may be isolated via the operation of one or more packers, which may also help to secure the casing string and stimulation equipment in place, and/or via cement.
Following the placement of the casing string, it may be desirable to provide at least one route of fluid communication out of the casing string. Conventionally, the methods and/or tools employed to provide fluid pathways out of the casing string require mechanical tools supplied by a rig and/or downhole tools needing high temperature protection, long term batteries, and/or wired surface connections. Additionally, conventional methods may not allow for individual, or at least selective, activation of a route of fluid communication from a plurality of formation zones.

This patent is subject to a terminal disclaimer.


A thermoformed thermoplastic bedliner has a ribbed bottom wall which overlies the floor of a truck cargo bed. Two side walls extend upwardly from the bottom wall. The ribs extend longitudinally along the bottom wall and terminate at a transverse flat portion. The bedliner can be modified to accommodate mounting of a fifth wheel hitch to the truck frame, either by bolting through the bedliner or by cutting away the transverse flat portion.

This invention relates generally to truck bedliners and in particular to thermoformed thermoplastic liners for use on truck beds having fifth wheel mounts.
Although long used in agricultural and commercial applications, pick-up trucks with open cargo beds have also become increasingly popular as personal and family vehicles. The commercial vehicle owner, although concerned with performance and cost effectiveness of the vehicle, often considers the vehicle as a traveling company advertisement or symbol. A neat and well-maintained vehicle is more likely to favorably impress customers. Owners of personal vehicles, while concerned with functionality and efficiency, are also concerned with pride of ownership, personal image, and outward appearances. In addition, the automotive enthusiast desires to maintain his vehicle in as close to a "like new" condition as possible.
Truck bedliners of plastic or rubber are commonly employed to protect the painted metal surfaces of a pick-up truck cargo bed. These truck bedliners are available in a wide variety of configurations to suit the wide variety of available trucks. Bed liners protect the cargo bed from scratching and denting as well as paint fading from exposure to sunlight and elements. One-piece thermoformed thermoplastic truck bedliners provide a cost-effective means of protecting the truck cargo bed.
Because of the thin sheet construction of bedliners, to restrain the twisting and warping of the bottom wall, the bottom wall is formed with an array of parallel longitudinal ribs. In addition to the stiffening benefits of these ribs, they also serve as passageways for the escape of rain water and other liquid collected within the truck bed.
Pick-up trucks may be provided with trailer hitches which, rather than mounting to the rear of the vehicle, are secured to the bed of the truck approximately between the wheel wells. These fifth wheel or goose neck hitches provide greater towing capacity.
Fifth wheel hitches have been mounted to bedliners over the undulating ribs by positioning metal shims, such as round rods beneath or between ribs, and then fastening the fifth wheel hitch to the truck frame directly through the raised ribs.
What is needed is a truck bedliner which readily permits fifth wheel hitch mounting while still providing some level of protection to the truck bed.

Liner for a truck bed having a fifth wheel mount


In method for manufacturing an external cladding for a laminate battery according to the present invention, austenitic stainless steel foil having a thermoplastic resin layer on one of a front surface and a rear surface and a lubricating film on the other surface is used as a material, the stainless steel foil is disposed such that the surface provided with the thermoplastic resin layer opposes a punch, and drawing is implemented on the stainless steel foil without using lubricating oil in a condition where an annular region of the stainless steel foil, which is contacted by a shoulder portion of the punch, is set at a temperature of 20° C. or lower, and an exterior region on an exterior of the annular region is set at a temperature between 40° C. and 100° C.

Recently, laminate batteries in which a battery element is sealed by external cladding (laminate sheets) have drawn attention as a form of a secondary battery such as a lithium battery. Japanese Patent Application Publication No. 2004-052100 A discloses a method for manufacturing the external cladding on which a projecting portion for housing the battery element is formed by using austenitic stainless steel foil as a material, and by implementing drawing on the stainless steel foil at room temperature. By employing the external cladding made of the stainless steel foil in this manner, a strong and lightweight laminate battery can be constructed.
This type of laminate battery is applied to electric automobiles or the like, and therefore requires a large capacity in order to extend the range of electric automobiles for instance. To increase the capacity of the laminate battery, a space that can accommodate a larger battery element must be secured. With the configuration described above, however, drawing is implemented on the stainless steel foil at room temperature, and therefore molding defects such as cracks occur when an attempt is made to form a deep projecting portion.
Japanese Patent Application Publication No. 2009-113058 A discloses a configuration for realizing deep drawing, when drawing is implemented on austenitic stainless steel sheet, by performing warm working in which a region of the stainless steel foil that contacts a punch is cooled, a region on an exterior thereof is heated, and the punch is pressed into the stainless steel foil while supplying lubricating oil.
The present applicant considered the application of drawing such as that described in Japanese Patent Application Publication No. 2009-113058 A to manufacture external claddings for laminate batteries such as that described in Japanese Patent Application Publication No. 2004-052100 A, but found that the following problems arise. The method described in Japanese Patent Application Publication No. 2009-113058 A requires the performance of washing for degreasing after the drawing because the drawing is performed while supplying lubricating oil. When a laminate battery is constructed using external claddings manufactured by this drawing process, however, the lubricating oil as well as dust and the like adhered to the lubricating oil may infiltrate interior of the battery, causing the battery to malfunction. If the lubricating oil is simply not used, on the other hand, the material can no longer be moved smoothly, and therefore deep drawing cannot be realized.

Method for manufacturing external cladding for laminate battery


A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses the floating point instructions into one or more floating point operations and one or more integer operations such as memory load operations. The floating point operations are conveyed to the floating point unit. The memory load operations load the floating point operands of the floating point operations. Floating point operands that are wider than integer operands are handled by multiple memory load operations. Each memory load operation loads a portion of the floating point operand. The portions of the floating point operand are combined is a queue in the floating point unit. When the floating point unit has received the floating point operation and the memory operands that comprise with the floating point operand, the floating point unit dispatches the floating point instruction for execution. Floating point instructions that are too complex to be completed in one pass through the floating point execution pipeline are further parsed into a plurality of floating point operations by the floating point unit.

1. Field of the Invention
This invention relates to the field of microprocessors and, more particularly, to the handling of floating point instructions within microprocessors.
2. Description of the Related Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term "clock cycle" refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term "instruction processing pipeline" is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion. Generally speaking, a pipeline comprises a number of stages at which portions of a particular task are performed. Different stages may simultaneously operate upon different items, thereby increasing overall throughput. Although the instruction processing pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally comprises fetching the instruction, decoding the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
Microprocessors are configured to operate upon various data types in response to various instructions. For example, certain instructions are defined to operate upon an integer data type. The bits representing an integer form the digits of the number. The binary point is assumed to be to the right of the digits (i.e. integers are whole numbers). Another data type often employed in microprocessors is the floating point data type. Floating point numbers are represented by a significand and an exponent. The base for the floating point number is raised to the power of the exponent and multiplied by the significand to arrive at the number represented. While any base may be used, base 2 is common in many microprocessors. The significand comprises a number of bits used to represent the most significant digits of the number. Typically, the significand comprises one bit to the left of the binary, and the remaining bits to the right of the binary. The bit to the left of the binary is not explicitly stored, instead it is implied in the format of the number. Generally, the exponent and the significand of the floating point number are stored. Additional information regarding the floating point numbers and operations performed thereon may be obtained in the Institute of Electrical and Electronic Engineers (IEEE) standard 754.
Floating point numbers can represent numbers within a much larger range than can integer numbers. For example, a 32 bit signed integer can represent the integers between 2.sup.31 -1 and -2.sup.31, when two's complement format is used. A single precision floating point number as defined by IEEE 754 comprises 32 bits (a one bit sign, 8 bit biased exponent, and 24 bits of significand) and has a range from 2.sup.-126 to 2.sup.127 in both positive and negative numbers. A double precision (64 bit) floating point value has a range from 2.sup.-1022 and 2.sup.1023 in both positive and negative numbers. Finally, an extended precision (80 bit) floating point number has a range from 2-16382 to 2.sup.16383 in both positive and negative numbers.
The expanded range available using the floating point data type is advantageous for many types of calculations in which large variations in the magnitude of numbers can be expected, as well as in computationally intensive tasks in which intermediate results may vary widely in magnitude from the input values and output values. Still further, greater precision may be available in floating point data types than is available in integer data types.
Floating point data types and floating point instructions produce challenges for the microprocessor designer. For example, operands of floating point instructions may be larger than operands of integer instructions. As noted above, floating point numbers may be 32, 64, or 80 bits in width. In contrast, integer instructions typically have operands that are 32 bits or less. Because the microprocessor must accommodate 80 bit floating bit operands, data paths and other circuitry of the microprocessor must be designed to handle 80 bit operands. When the microprocessor is executing integer operations, which typically comprise the majority of instructions, the additional data paths and circuitry for handling 80 bit operands are not utilized. This additional and largely nonutilized circuitry increases the size of the microprocessor. Increasing the size of the microprocessor, disadvantageously reduces the maximum clock rate at which the microprocessor can operate, increases the power dissipation of the microprocessor, and reduces the yield in manufacturing the microprocessor.

Hierarchical microcode implementation of floating point instructions for a microprocessor


A sealer for the adhesive-containing seam of a tubular wrapper surrounding a running filler of tobacco or filter material for tobacco smoke has an at least partially ceramic heating device which contacts the moving seam and contains an electric conductor of ceramic material. The temperature of the heating device can be regulated to decrease, either stepwise or gradually, in the direction of movement of the seam. The heating device can consist of or contain silicon nitride and can be doped with titanium nitride to enhance its heat conductivity.

The invention relates to improvements in apparatus, known as sealers or band sealers, which can be utilized in machines for the making of rod-shaped products of the tobacco processing industry to heat and thus stabilize or strengthen the adhesive-containing seams of tubular wrappers for rod-like fillers of tobacco, filter material for tobacco smoke or other material of the tobacco processing industry. For example, the improved apparatus can be utilized to stabilize the longitudinally extending seam of a tubular wrapper which consists of cigarette paper and surrounds a rod-like filler of natural, reconstituted and/or artificial tobacco while the filler advances from a wrapping mechanism to a so-called cutoff of a cigarette rod making machine.
The purpose of the sealer is to condition the moving adhesive-containing seam of the tubular wrapper for the purpose of heating the adhesive in the seam. This causes a water-base adhesive to set or liquefies an adhesive of the type known as hot melt. As a rule, an elongated heated strip-shaped heating device is maintained in actual contact with the exposed outer side of the outer layer of the moving seam.
The strip-shaped heating devices of conventional sealers are made of a metallic material and are connected with heating cartridges which, as a rule, are installed at a considerable distance from the locus of contact between the heating device and the seam. This renders it necessary to employ cartridges whose thermal output is relatively high which, in turn, brings about serious problems during certain stages of operation of such conventional sealers. Thus, the seam portion which contacts the sealer when a cigarette maker is brought to a halt is likely to be overheated and a seam portion which is caused to move along the sealer immediately after the cigarette maker is started or restarted is likely to be heated to a temperature well below the optimum temperature for the particular adhesive. An overheating of te seam is likely to entail charring or other undesirable consequences involving an undesirable change of appearance and/or the strength of the overheated portion of the seam. On the other hand, underheating of the seam can adversely affect the strength of the respective portion of the seam, i.e., the seam is likely to open up during advancement through the cutoff which is located downstream of the sealer as considered in the direction of advancement of a wrapped rod-like filler in a cigarette maker or another rod making machine of the tobacco processing industry.
Another drawback of conventional sealers is that losses due to undesirable heat radiation are very high. Furthermore, the temperature of a conventional sealer cannot be regulated with a desired degree of accuracy and/or within a short or very short interval of time. The reason is that the thermal inertia of conventional sealers is too pronounced. Still another drawback of conventional sealers which include metallic seam-contacting portions is that such portions are likely to become distorted in response to unavoidable fluctuations of their temperature; this can result in the development of unsatisfactory contact between the metallic portion and the moving seam.
U.S. Pat. No. 3,575,766 granted Apr. 20, 1971 to McArthur et al. discloses a band sealer for a cigarette or filter maker wherein the moving seam of a tubular wrapper of cigarette paper or the like is contacted by a thin strip consisting of a metallic material. The strip conducts electric current and forms part of an electric resistance heater, i.e., the heat to be transmitted to the seam is generated directly in the metal strip.

Apparatus for heating the adhesive-containing seams of wrappers of rods of the tobacco processing industry


Multiple network processors (201, 202, 203) are connected in a pipeline via control (206) and data (205) ports of the network processors. The network processors (201, 202, 203) communicate with neighboring network processors through the control and data ports. Through these ports, the network processors can implement a variety of data flow control protocols.

A. Field of the Invention
The present invention relates to network devices and, more specifically, to network devices for implementing network protocols that control data flow.
B. Description of Related Art
In digital communication systems, data is routinely transmitted over processing devices in a network. In packet-based networks, for example, data is transmitted in discrete quantities known as packets. A packet destined for a remote computer is typically transmitted through multiple intermediate network devices (e.g., through routers, switches, or bridges) before reaching its final destination. At each intermediate device, the intermediate network device may examine the packet and, based on the examination, determine the next network device (or hop) to which to transmit the packet.
Each intermediate network device runs one or more protocols that define how the device is to forward received packets. For example, the intermediate network device may assign the packet a high transmission priority, may apply quality of service rules to the packet, or perform error checking operations on the packet to ensure that the packet has not suffered transmission errors.
The protocols are often performed in the network devices by general purpose processors. In high performance network devices, such as high performance routers or switches, it can be difficult for these general purpose processors to keep up with the input data flow. Accordingly, specialized network processors, which may implement frequently used network operations in hardware, have been developed. These specialized processors may be optimized for protocol processing.
One function which may be performed by specialized processors is data flow control. Flow control refers to the management of data flow between devices so that the data can be handled at an efficient pace. Too much data arriving before a device can handle it can cause data overflow, potentially resulting in lost data. Flow control can also be applied in the context of refusing additional device connections until the flow of data has subsided.
It is desirable to enable specialized network processors to implement a wide variety of flow control techniques in the context of various network protocols.

Digital network processor-based multi-protocol flow control


A communication apparatus which occupies small space and yet can be connected with numerous external cables and which permits a cooling arrangement to be constructed at low cost. An information processing device constituting the communication apparatus has external cable connection ports provided on both top and bottom surfaces thereof, and thus, more external cables can be connected than in the case of connecting the cables to the side surfaces. Also, the external cables connected to the ports are guided along the top and bottom surfaces toward the front of the communication apparatus with their heights restricted by external cable covers and, therefore, do not occupy substantial space above and below the device. Further, since the external cables are connected to the top and bottom surfaces, the front and rear surfaces of the device have spare space, making it possible to construct a ventilation arrangement such as vent holes and fans.

1. Field of the Invention
The present invention relates to an information processing device containing a printed wiring board on which electronic components are mounted, a communication apparatus comprising such information processing devices installed in a rack, and a method of connecting external cables to the information processing device.
2. Description of the Related Art
Conventional communication apparatus comprises a vertical row of information processing devices each containing a printed wiring board on which electronic components are mounted, and is installed at the site of a base station or the like. Such electronic components include heat-emitting devices, and accordingly, the information processing device is often equipped with a plurality of fans or the like constituting a ventilation arrangement for cooling the internal components (see, e.g., Unexamined Japanese Patent Publication No. H01-238097).
FIGS. 21A to 21C schematically illustrate an exemplary construction of a conventional communication apparatus, wherein FIG. 21A is a front view of the apparatus, FIG. 21B is a rear view of the apparatus, and FIG. 21C is a left side view of the apparatus.
The communication apparatus 101 comprises a vertical row of information processing devices 103 arranged on a rack 102 constituted by metal plates welded together. In the figures, only one information processing device 103 is shown for convenience' sake. The information processing device 103 contains a printed wiring board on which electronic components are mounted. Also, external cables 104 for inputting/outputting signals and power cables 105 for supplying electric power are connected to the front and rear, respectively, of the information processing device 103.
FIGS. 22A and 22B schematically illustrate an exemplary construction of the conventional information processing device, wherein FIG. 22A is a front view of the device and FIG. 22B is a rear view of the device.
The front of the information processing device 103 is provided with connectors 106 to which personal computers etc. are connected, a slot 107 in which a memory card storing predetermined settings is inserted, a display section 108 constituted by a plurality of LEDs, and connection ports 109 to which external cables 104 are connected. A plurality of vent holes 110 for admitting fresh air are formed in the other region of the front surface.
The rear of the information processing device 103 is provided with power supply terminals 111 to which power cables 105 are connected, motor-driven fans 112, and breakers 113 for cutting off the power supply.
Meanwhile, with the recent tendency toward larger capacity and higher output of communication apparatus, an increasing number of external cables are connected to individual information processing devices. To secure a connection space for numerous external cables, the areas of the front and rear surfaces of the information processing device are increased, for example.
However, the following problems arise when a large number of external cables are connected.
Specifically, in communication apparatus in which numerous external cables are connected to the front and rear of each information processing device, the front and rear surfaces of each device need to be increased to secure a connection space for the external cables. As a result, the body of each information processing device increases in size, requiring an installation space larger than the capacity that the internal electronic circuitry originally requires. Namely, increase in the number of external cables leads to useless increase of the space occupied by the information processing device.
Also, in small-sized communication apparatus with a relatively small height, printed wiring boards are horizontally positioned within each information processing device and cooling air is introduced into the device so as to flow in the depth direction. Consequently, the front and rear of the device need to be provided with a cooling arrangement such as vent holes and fans, besides the connection ports for the external cables. In this case, the number of external cables and the size of the cooling arrangement are the factors that determine the overall size of the information processing device and thus of the communication apparatus. To reduce the size of the information processing device without decreasing the number of external cables, expensive components such as small-sized, high-output motors need to be used, giving rise to a problem that the cost increases.
In medium- or large-sized communication apparatus with a relatively large height, printed wiring boards are vertically positioned within each information processing device and cooling air is introduced into the communication apparatus so as to flow in the vertical direction. Consequently, the body of the information processing device is increased in height and occupies an installation space larger than the capacity that the internal electronic circuitry originally requires. It is also necessary to provide the top and bottom of the communication apparatus with a cooling arrangement such as fans and convection inducers, which entails useless increase of the installation space for the communication apparatus.

Communication apparatus, information processing device, and external cable connection method


The present invention relates to an improved air extraction apparatus for continuous package making. More particularly, the present invention relates to an improved air extraction apparatus that continuously packages a continuous succession of objects in a continuous length of heat-sealable packaging film. The apparatus extracts air from the packaging film that has been folded in a manner so that margins along opposite longitudinal edges of the film form a seam with two overlapping flaps for heat sealing, wherein just ahead of a heat sealing station, the improved apparatus of the invention extracts air from between the film flaps.

(1) Field of the Invention
The present invention relates to an improved air extraction apparatus for continuous package making. More particularly, the present invention relates to an improved air extraction apparatus that continuously packages a continuous succession of objects in a continuous length of heat-sealable packaging film. The apparatus extracts air from the packaging film that has been folded in a manner so that margins along opposite longitudinal edges of the film form a seam with two overlapping flaps for heat sealing, wherein just ahead of a heat sealing station, the improved apparatus of the invention extracts air from between the film flaps.
(2) Description of the Related Art
Air suction systems employed with apparatus that continuously package a continuous succession of objects in heat-sealable packaging film are known in the art. Prior art continuous packaging apparatus are typically comprised of several stations that progressively package a series of objects as the objects and a continuous supply of packaging film are conveyed past the stations. The typical apparatus comprise a supply station supplying packaging film in a continuous length to a folding station. At the folding station, the continuous length of packaging film is folded around a continuous succession of objects conveyed past the station. The manner of folding the film produces a continuous, longitudinal tube (usually not cylindrical) of packaging film with the objects enclosed therein. The manner of folding the film also produces a continuous seam along the tube where the opposite lateral edges or margins of the packaging film meet. The seam is formed by overlapping flaps of the film that extend along the longitudinal length of the film tube. After exiting the folding station, the tube and its two overlapping flaps are conveyed to a heat-sealing station that comprises a pair of driven rollers with opposed surfaces for gripping the flaps therebetween. The surfaces of the rollers are heated and seal the overlapping flaps of heat-sealable film together as the overlapping flaps pass between the rollers.
Prior to sealing the packaging film, it is desirable to extract as much air as possible from the interior volume of the packaging, thereby reducing the size of the packaged objects and reducing their shipping costs. For these typical continuous package making apparatus, the present invention is an improvement over the air suction systems of the prior art.
One type of prior art air suction system involves a suction nozzle. In use, the suction nozzle is stationed just ahead of the heat-sealing station. The suction nozzle draws air from the interior of the packaging tube by being positioned between the overlapping flaps of the packaging material as they are conveyed past the nozzle. This mode of operation requires that the nozzle separate the two flaps as they are conveyed past and slide across the opposite sides of the nozzle, with the flaps being rejoined after they have passed the nozzle and air has been extracted from the packaging. Prior art systems of this type are shown by U.S. Pat. Nos. 4,170,863 and 4,663,915.
Another type of prior art air suction system involves a vacuum chamber. The vacuum chamber is defined within a hollow housing positioned underneath or behind a conveyor surface on which the continuous tube of packaging film, with the objects enclosed therein, continuously slides across. The conveyor surface and chamber housing are provided with longitudinal slots that receive a packaging tube's two overlapping flaps as the packaging material is conveyed past the housing of the vacuum chamber. The vacuum chamber communicates with a vacuum pump that creates a vacuum pressure in the chamber housing and draws air from the packaging from between the two flaps during their passage through the chamber housing. Prior art systems of this type are shown by U.S. Pat. No. 5,052,166 and U.K. Patent No. 2,124,995.
Still another type of prior art air suction system involves an eductor pipe connected to a source of vacuum pressure. The eductor pipe is inserted between the two lapped edges of the packaging film at a location still ahead of the heat-sealing station. The eductor pipe extends longitudinally within the confines of the two lapped edges to an open pipe end positioned at a point past the heat-sealing station. Therefore, the eductor pipe extends right through the heat-sealing station, and the heat-sealing station is modified accordingly. Thus this type of an air suction system works on a different principle from the others in that air is siphoned out of the tube of packaging material at a location along the tube that is past the heat-sealing station rather than ahead of it. A prior art system of this type is shown by U.S. Pat. No. 4,272,944.
There are several disadvantages associated with the prior art systems. The type involving a nozzle is often unable to provide a desirable degree of vacuum. This results from numerous leaks which permit the reentry of air into the tube. The leaks are difficult to avoid because the overlapping flaps of packaging material must be separated in order for them to slide over the opposite sides of the nozzle. There are open voids between the flaps both before and after they pass around the nozzle and, in consequence, air persistently leaks between the passing flaps and stationary nozzle. This system is also disadvantaged in that the flaps will often be displaced from their positions extending around the nozzle as the packaging material is conveyed past the nozzle, requiring the system to be closed down until the flaps are repositioned.
The type of prior art air suction system involving the vacuum chamber is likewise unable to provide a desirable degree of vacuum. The leaks are present here because of the configuration of the longitudinal slot, and particularly because of the configuration of the entry and exit ends of the slot. The slot ends are open to permit the sliding entry and exiting of the continuously passing flaps of packaging material. The slots are often configured to be wide enough to avoid the imposition of any frictional engagement drag on the flaps being conveyed through the slot. Yet this also means that there are gaps between the flaps and the slot side walls that permit air from outside the packaging to leak into the slot. The result is a low operating efficiency and a less than desirable degree of vacuum.
The type of prior art air suction system involving an eductor pipe is chiefly deficient in requiring a modified, non-typical apparatus for continuous package making. These types of prior art air extraction systems have specialized constructions that are not readily retrofit to existing packaging conveying systems.

Air extraction apparatus for continuous package making


The present invention relates to a process for the arylation of olefins by reaction of haloaromatics or arylsulfonates with olefins in the presence of a palladium catalyst, a bulky nitrogen base and a salt.

1. Field of the Invention
The present invention relates to a process for the arylation of olefins by reaction of haloaromatics or arylsulfonates with olefins in the presence of a palladium catalyst, a bulky nitrogen base and a salt.
2. Brief Description of the Prior Art
Many aryl olefins have great industrial importance as fine chemicals, UV absorbers, starting materials for polymers and intermediates for active compounds.
The preparation of arylolefins is frequently carried out by means of palladium-catalyzed coupling of iodoaromatics or bromoaromatics, and to a lesser extent chloroaromatics or arylsulfonates, with olefins. Owing to the high price of iodoaromatics and bromoaromatics and the large amounts of waste product caused by the high molar masses, their use on an industrial scale is disadvantageous. However, the more readily available and therefore more attractive chloroaromatics have a comparatively low reactivity.
Zapf and Beller (Chem. Eur. J. 2001, 7, 2908) describe, inter alia, the palladium-catalyzed reaction of chloroaromatics with olefins at temperatures of 160° C. with addition of 20 mol % of quaternary ammonium salts in the presence of a base. Catalyst turnover numbers (TONs) of 850–1000 are achieved in 24 hours.
However, disadvantages of this process are the high quaternary ammonium salt requirements and the low catalyst turnover frequencies (TOFs) of a maximum of 42 per hour.
Littke and Fu (J. Am. Chem. Soc. 2001, 123, 6989) describe a process in which chloroaromatics are reacted with olefins at room temperature using palladium-dibenzylideneacetone ([Pd2(dba)3]) and tri-tert-butylphosphine in the presence of dicyclohexylmethylamine. However, large amounts of palladium catalyst are required for the process described, which makes its industrial application uneconomical.
There was therefore a need to develop a process which makes it possible for haloaromatics, in particular chloroaromatics, to be coupled with olefins in an efficient way.