An animal accident reduction system, method, and apparatus. The apparatus including at least some of a housing having substantially the same external size and shape of a raised reflective pavement marker, at least one input detector located within the housing, at least one logic and control circuit located within the housing, and at least one output device located within the housing, wherein the logic and control circuit is capable of receiving a signal from the input detector, wherein the output device is capable of receiving a signal from the logic and control circuit, and wherein the output device is capable of producing a determined sound, noise, or other vibration.

1. Field of Invention
This invention relates generally to animal warning devices.
2. Description of Related Art
It is well know for raised reflective pavement markers to be installed along portions of roadway to mark lane lines, center and edge lines, turn pockets, curb dividers and stop bars. The raised reflective pavement markers typically employ a corner-cubed retro-reflector technology that gathers light from an approaching vehicle's headlights and returns the light to the vehicle's driver in a narrow, focused beam. In this manner, it is easier for a driver to identify the roadway, particularly at night or during inclement weather.
Raised reflective pavement markers are typically formed from a weather-resistant acrylic or polymer blend housing, which affixed either directly to the roadway surface, in specifically designated snow-plowable housings, or within indentions specifically created in the surface of the roadway. The pavement markers are shaped such that they are relatively resistant to impact damage from vehicle tires and to breakage due to spot loading from uneven road surfaces.
It is also known that certain sounds, noises, or other vibration can be used to effectively deter certain animals from entering or remaining in a given area.

Animal accident reduction systems, methods, and apparatuses


A milling tool 8 includes a tool holder 10 for housing multiple thread cutting inserts 24 for precise milling of threads on a workpiece. The tool holder 10 is rotatable in an orbitable path spaced radially from a milling axis and is simultaneously rotatable about its own axis for repeatedly bringing each of the cutting inserts into engagement with the workpiece. Each cutting insert is precisely positioned within the tool holder by a stop surface 62 located at an axially rearward end of an insert cavity 28 in the tool holder. An axially elongate tool holder groove 32 is provided in communication with a side face of the generally rectilinear insert cavity. Each cutting insert defines a substantially rectangular plate, an end face for mating engagement with the stop surface 62 and an axially elongate insert groove 26 extending from a corresponding side face on the rectangular plate. A plurality of elongate pins 30 are each insertably engaged within each respective tool holder groove and insert groove, and are each secured by a plurality of screws 34 and 35 for applying a uniform force through the axis of the elongate pin for securing the respective cutting insert into a precise stabilized position within the tool holder.

Cutting inserts are utilized in a variety of applications, including use in milling tools and reaming tools. A milling tool may be used for cutting threads, and is then commonly referred to as a thread mill. A reaming tool is used for reaming a hole in a workpiece. The relationship between a thread mill and a reaming tool is that each tool rotates during the cutting operation, and may include several cutting inserts thereon. Numerous differences otherwise exist, however, between a thread mill and a reaming tool.
Thread milling tools may be generally categorized as tools which are indexable or non-indexable. In either case, however, one or more inserts extend radially outward from a tool holder, with each insert including a plurality of cutting teeth positioned parallel or slightly tapered to the tool holder axis for cutting threads on a workpiece. The thread mill tool cutter thus exerts a torsional and radial force on the insert during the cutting operation. One or more cutting inserts on a reamer tool holder may enlarge holes and/or finish a drilled hole to required tolerances. The reamer tool holder rotates while moving along its axis of rotation and the insert, which includes the cutting surface, thus moves axially for reaming the hole. The reamer tool holder thus exerts an axial force on the insert during the reaming operation.
Cutting inserts on some adjustable reamers are secured within the reamer holder by a single screw and dowel assembly. Since the force encountered by a reamer on a workpiece is along the axis of the reamer, the mechanism for securing an insert in place on a reamer is markedly different than securing a threading insert on a milling tool. The functional distinction between reamers and thread milling tools is critical to stabilizing the cutting insert on the tool holder.
Numerous prior art patents are directed specifically to thread mills having multiple cutting inserts. U.S. Pat. No. 4,531,863 to Smith discloses a thread milling device with rotatable thread cutting inserts that are secured against four locating surfaces by two set screws angularly disposed through the cutting insert.
U.S. Pat. No. 4,360,297 to Weber also discloses a thread cutting insert and tool holder. The rotatable insert is secured to the tool holder by a clamp member that is connected to the tool holder and fits within a notch or depression on the insert for securing the insert against four adjacent walls of the tool holder.
U.S. Pat. No. 4,409,868 to Huddle et al. discloses a thread cutting tool having a multi-toothed first thread chaser secured between two adjacent walls by a top clamp and intermediate chip breaker. Also disclosed is a rotatable single tooth thread chaser insert secured within a pocket on the tool holder by both a locking screw passing through a central aperture in the insert into the threaded bore, and a top clamp secured to the tool holder by a clamp screw.
U.S. Pat. No. 4,575,888 to Muren discloses a thread cutting insert having a central aperture for mounting the insert to an indexable tool holder.
U.S. Pat. No. 5,098,232 to Benson discloses a thread milling tool having an insert which may be secured in a pocket of the thread milling tool by a screw extending through a hole in the insert and into a threaded hole in the bottom of the pocket.
E.P. No. 0062621 discloses a thread cutting tool having an indexable insert and shim plate supported against complimentary support surfaces of a recess in the thread cutting tool and secured jointly by a clamp consisting of two bores passing through the insert and shim plate into the thread cutting tool.
U.S. Pat. No. 4,913,604 to Zaengerle discloses a thread milling tool and trapezoidal milling plate secured against four surfaces of the thread milling tool by a countersunk clamping bolt passing through the center of the trapezoidal milling plate.
Numerous disadvantages are presented by the prior art relating to inserts that incorporate a plurality of cutting surfaces thereon, so that the insert can be rotated with respect to the holder when one cutting surface becomes worn, thus precluding the necessity of replacing the insert. Inserts with multiple cutting surfaces are typically secured to a holder by a single clamp or screw in order that the face of the cutting insert may be easily rotated to reveal new cutting edges with minimal delay. Consequently, the stability of the multi-cutting face insert during thread cutting operations is sacrificed. Conversely, once an insert with a single cutting face becomes worn, it must be replaced. The time required to replace the insert and securely remount the new insert on a tool holder is thus a disadvantage of tools with single cutting face inserts.
Disadvantages also exist when a single cutting face insert is secured to the tool holder by a single screw passing through a central axis perpendicular to the insert. For instance, stress may develops in the threaded connection between the screw, insert and tool holder during milling operations, thus reducing stability between the insert and tool holder and reducing the quality of the thread cutting operation.
Multiple screws have been used to secure an insert directly to the tool holder, as evidenced by U.S. Pat. No. 4,531,863 and E.P. No. 0062621, although significant disadvantages remain with these thread mills. Despite the fact that two or more screws are used, the force used to secure the insert to the tool holder is not consistently applied to the insert along the longitudinal axis of the cutting insert. Moreover, the inability to precisely position the cutting insert on the tool holder is increased by securing the insert with one or more screws. Finally, the time required to replace a cutting insert and reliably mount a new insert on a thread mill holder is a significant disadvantage of these prior art tools.
The disadvantages of the prior art are overcome by the present invention. An improved thread mill having multiple thread cutting inserts mounted thereon is hereafter disclosed which overcomes these and other difficulties experienced by prior art tools.

Thread mill having multiple thread cutters


A system for powering an electric device with power drawn from a telephone line in a telephone network includes an exchange connecting a telecommunication network to a subscriber apparatus through one telephone line. The system includes a control and feeding device located at the subscriber's premises, connected between the telephone line and subscriber apparatus, and further connected to the electric device to be powered, and a logic control unit in the exchange connected between the subscriber line interface circuit of the telephone line and the telecommunication network, and a bidirectional device connected between the logic control unit and subscriber circuit for recognising and applying to the logic control unit signals received by the subscriber circuit through the telephone line, and for sending to the subscriber circuit control information generated by said logic control unit and relating to the power drawing.

As it is known, in a telephone system a conventional subscriber line connecting the switching exchange (local Central Office) to the customer's equipment comprises a pair of (twisted) copper wires carrying both the telephone signals and a dc current to power the telephone electronics.
Most telephone companies in the world are bound to ensure continued telephone service to their customers for a given time duration in the event of a failure of the power distribution network (e.g. for 72 hours), and are equipped with backup generators so that under given circumstances a telephone line might be the only available source of (moderate) electrical power.
Drawing a fraction of such power for feeding the subscriber apparatus is usually allowed by the telephone companies and even the feeding of additional devices at the subscriber's premises is usually tolerated when the line is in use, i.e. in telephone jargon, when the line is in an off-hook condition.
On the other hand, the telephone companies prevent or limit the drawing of a dc power from a line in the off-hook condition for both avoiding a useless power consumption and an unauthorised feeding of other devices in the customer premises. Namely, after the subscriber has lifted the handset (or pushed a key) to be connected with the telephone exchange, a dial tone is sent to the customer apparatus and a predetermined delay is allowed for setting up the call. In case a proper selection number is not dialed and/or the call has not be set up within a given time, the line is "restrained" or set in a so called "park condition", in which the dc power supplied through the line is reduced to a very low level and a dialing is no longer allowed. Thus the user is compelled to hang up the handset, and return to an on-hook condition. The above procedure also applies in case of a misplaced handset.
The on-hook and off-hook conditions are recognised by the central office through the current circulating in the line. Under normal (on-hook) conditions the subscriber apparatus does not draw an appreciable current (e.g. lower than 1 mA) whereas in the off-hook condition an impedance depending on the particular handset, on the line length and on other factors is connected to the line and a given range of current (loop current) is admitted.
There have been suggested devices for drawing electrical power from a telephone line when the telephone line is in the off-hook condition.
For example, US 2002/0075038 A1 discloses a power supply circuit for powering an electrical device coupled to a telephone line, such as a modem using power drawn from said telephone line when this latter is in an off-hook condition.
U.S. Pat. No. 5,461,671 discloses a telephone line power utility circuit in which dc power supplied through a telephone line in an off-hook condition is utilised as a power source for a line terminal device.
U.S. Pat. No. 5,553,138 discloses a telecommunication unit requiring power even in an on-hook condition that employs a capacitor charged in the off-hook condition. When the capacitor charge becomes too low, the unit goes off-hook for a brief period of time to recharge the capacitor.
DE 10041521 discloses a power supply procedure for extracting power from a subscriber's line during a commercial power supply failure in which a failure detection signal is output during failure of the power network at the subscriber's premises and electric power is then supplied from the station to the subscriber's line to operate the telephone circuit.
The known devices have therefore a number of limitations and drawbacks, such as:                The current drawing for feeding additional devices, when tolerated, is not under the control of the telephone company.        The amount of power that can be delivered to a device is quite limited and requires the maintaining of a telephone call, i.e. an off-hook condition of the telephone line.        There is no way to modify the power drawing limits even under circumstances that would render desirable such a power drawing.        The current drawing interferes with the normal operation of the telephone service.
It is therefore an object of the present invention to overcome the drawbacks and limitations of the prior art devices and methods, and particularly to allow the drawing of not negligible amounts of electrical power from a telephone line for feeding electric devices.
It is another object of the invention to accomplish such current drawing in an on-hook condition of the telephone line and under the control of the telephone company running the utility.
It is a further object of the invention to realise a service available to authorised subscribers for controllably drawing a dc current from a telephone line in an on-hook condition.

Device and a method for feeding electric devices from a telephone line


The present invention is a process for producing organic esters wherein a dialkyl ether and a carboxylic acid are reacted in the presence of a solid phase acidic catalyst having an acidity factor of at least 0.30, preferably at least 1, under reaction conditions sufficient to form a reaction mixture comprising the desired organic ester and an alcohol and recovering the organic ester. For example, methyl acetate can be prepared by reacting dimethyl ether and acetic acid in the presence of montmorillonite, amorphous silica-alumina or .kappa.-alumina under conditions sufficient to form methyl acetate. While typical processes produce an azeotropic mixture of the desired organic ester and water, the claimed process utilizes a combination or reactants and catalysts wherein water is not produced in appreciable amounts. Therefore, the organic ester product can be separated conveniently thereby avoiding a cumbersome azeotropic distillation step as required in prior art processes.

Organic esters, represented by the generic formula, RCO.sub.2 R' wherein R and R' are independently selected from an organic functionality, are utilized in numerous applications. Recent data indicate that more than 600 esters are currently sold in the United States and more than 100 esters are available in medium and bulk lots. On the basis of bulk production, poly(ethylene rerephthalate) is prepared in greatest quantity and is used in manufacturing polyester fibers and thermosetting fibers. Poly(ethylene terephthalate) is typically prepared by reacting terephthalic acid and ethylene glycol or by transesterification of dimethyl terephthalate with ethylene glycol.
Numerous catalytic processes are known for producing organic esters including reacting an alcohol and either an acid anhydride, an acid chloride, an amide or a nitrile in the presence of a suitable catalyst under reaction conditions sufficient to form the desired product. For example, organic esters can be prepared by reacting a carboxylic acid and an alcohol in the presence of catalysts such as strong mineral acids, tin salts, organs-titanates, silica gel and cation-exchange resins. Unfortunately, these reactions proceed via a reversible equilibrium and can be driven toward completion only by removing the desired ester product or water.
Highly volatile organic esters such as methyl formate, methyl acetate and ethyl formate, typically have lower boiling points than their corresponding alcohols and can be readily removed from the product mixture by conventional methods. However, water cannot be easily separated by simple distillation from aliphatic alcohols and esters of medium volatility because the product mixture forms an azeotrope. Consequently, processes for making such esters are highly energy intensive because the water/ester azeotrope must be broken in order to recover the desired ester.
U.S. Pat. No. 3,510,511 discloses a process for preparing an ester by reacting a carboxylic acid and an alkyl ether. The process comprises continuously introducing an ether of an alkanol and a carboxylic acid simultaneously in a proportion, two moles acid to one mole ether, into a boiling mixture initially consisting of sulfuric acid and the ether in a proportion of 0.7 to 1.3 mol of sulfuric acid per mol of ether; continuously extracting the vapors evolved from the reaction mixture and isolating the ether product from water via fractional distillation.
Derevitskaya and coworkers, Tetrahedron Letters, 49 (1970) 4269 disclose a process for preparing alkyl esters by reacting an alkyl tert-butyl ether and a carboxylic acid in the presence of a catalytic amount of a proton-donating agent such as sulfuric acid or para-toluenesulfonic acid. The reaction is represented by the formula: EQU R--O-tert-C.sub.4 H.sub.9 +R'--CO.sub.2 H.fwdarw.R'--CO.sub.2 R+CH.sub.2 .dbd.C(CH.sub.3).sub.2 +H.sub.2 O
The driving force of the above-mentioned reaction results from evolution of isobutylene. The desired organic ester is separated from the reaction mixture by diluting the mixture with diethyl ether, washing with aqueous sodium hydrogen carbonate and water and drying over sodium sulfate or magnesium sulfate. Following removal of diethyl ether, the residue is distilled to yield the desired ester.
Considerable research is being conducted in order to develop a process for preparing organic esters which eliminates the shortcomings of the above-mentioned prior art processes. Those skilled in the art of producing organic esters are particularly interested in commercial processes wherein water is not produced in appreciable quantities.

Process for producing organic esters by reacting a carboxylic acid and a dialkyl ether


An apparatus for singulating and bonding semiconductor chips includes a singulating station and a mounting station. In the singulating station, a semiconductor chip is provided with a bonding wire by a bonding tool and lifted off a carrier film. Then, in the mounting station, the semiconductor chip is placed on a chip mounting surface and fixed in place. The bonding wire is guided to a contact-connection surface of the circuit carrier and bonded to this surface.

A system for producing semiconductor components provides a method for combining the semiconductor chip mounting method and the semiconductor chip wire bonding step when assembling a semiconductor housing. For this purpose, a conventional semiconductor chip mounting device and a semiconductor chip wire bonding device are integrated in a simplified, common machine system. A computer-monitored television camera system mounted independently observes and monitors the working steps of the semiconductor chip mounting process and the wire bonding process using feedback processes. A drawback is the use of a conventional singulating apparatus with a vacuum pipette, for example, as is known for large-area semiconductor chips. Vacuum pipettes of this type require a semiconductor chip to have a minimum surface area in order to be singulated, since otherwise the semiconductor chip cannot be picked up by the vacuum pipette and fed to a mounting station. Singulating and conveying of semiconductor chips with a surface area smaller than this minimum surface area is not possible.
However, there is a demand, in particular, in radiofrequency technology, to construct discrete RF semiconductor components, i.e., RF PIN diodes, in which the semiconductor chips are at least an order of magnitude smaller than the abovementioned minimum surface area required for semiconductor chips of this type to be handled in a singulating station of a semiconductor wafer divided into semiconductor chips.
An apparatus and a method which allow semiconductor chips with a surface area an order of magnitude smaller than the minimum surface area of semiconductor chips of conventional singulating apparatuses to be picked up and fed to a mounting device is desirable, for example, such that it is possible for radiofrequency semiconductor components and RF PIN diodes for radiofrequency applications to be installed in suitable radiofrequency housings at low cost.

Apparatus for singulating and bonding semiconductor chips, and method for the same


A plasma display panel is disclosed. The plasma display panel includes a front substrate on which a scan electrode and a sustain electrode are positioned, a first black layer positioned between the scan electrode and the front substrate and between the sustain electrode and the front substrate, a rear substrate on which an address electrode is positioned to intersect the scan electrode and the sustain electrode, and a barrier rib that is positioned between the front substrate and the rear substrate to partition a discharge cell. The first black layer includes cobalt (Co) material and ruthenium (Ru) material. The barrier rib including lead (Pb) equal to or less than 1,000 ppm (parts per million).

A plasma display panel includes a phosphor layer inside discharge cells partitioned by barrier ribs and a plurality of electrodes.
When driving signals are applied to the electrodes of the plasma display panel, a discharge occurs inside the discharge cells. In other words, when the plasma display panel is discharged by applying the driving signals to the discharge cells, a discharge gas filled in the discharge cells generates vacuum ultraviolet rays, which thereby cause phosphors positioned between the barrier ribs to emit light, thus producing visible light. An image is displayed on the screen of the plasma display panel due to the visible light.

Plasma display panel with improved contrast characteristics


An “accumulation buffer” process in a graphics processing system is carried out not by rendering each sub-frame making up the accumulated frame in its entirety in turn, but by subjecting each individual tile 2, 3, 4 and 5 making up the accumulated frame to the sequence of different rendering passes individually. Thus, for each individual tile making up the accumulated frame, several sub-tiles (e.g. 2′, 2″, 2′″ and 2″″) are generated in turn and accumulated together to provide a final accumulation tile (2ACC) that is output as the accumulated version of the tile in question. This is then repeated for each of the remaining individual tiles 3, 4 and 5 making up the accumulated frame 1, and the individual accumulated tiles 2ACC, 3ACC, 4ACC and 5ACC are combined together to provide the output accumulated frame 6.

1. Field
The technology described herein relates to graphics processing systems and in particular to the so-called "accumulation buffer" operation in graphics processing systems.
2. Description of the Related Art
As is known in the art, there is a process in graphics processing that is commonly referred to as the "accumulation buffer". This process is a well-known feature that is, for example, part of the desktop Open GL standard.
The "accumulation buffer" process basically involves rendering several different versions of a "frame", e.g. from several different viewing angles, and accumulating a desired weighted average of all the different rendered versions of the frame in a single buffer (the "accumulation buffer"). This resulting "accumulation buffer" averaged version of the different frames is then used as the output frame (e.g., and typically, as the frame to be displayed).
The "accumulation buffer" is typically used to emulate a number of different effects, such as depth of field, motion blur, soft shadows and anti-aliasing.
One drawback with the use of the accumulation buffer is that in existing implementations, it requires the use of an external (to the graphics processor) full-frame floating point buffer to act as the accumulation buffer. While this may be acceptable in the case of more powerful desktop graphics processing systems, the Applicants have recognised that such an arrangement is not desirable in lower-powered graphics processing systems, such as embedded graphics processing systems and/or systems for use in portable devices. Indeed, for this and other reasons, the Open GLES standard, for example, does not include the use of accumulation buffers.
The Applicants believe therefore that there remains scope for improvements to accumulation buffer operation and implementation in graphics processing systems.


A robot system and method for conditionally stopping a robot, wherein a maximum stopping time and/or distance are defined by a user or integrator through a user interface as safety limits based on the risk assessment. The method provides the continuous calculation of the time and/or distance, which the robot would need to stop under maximum motor torque and/or brake appliance. The robot is stopped or the speed of the robot is reduced, if the calculated time and/or distance exceeds the maximum limit values set by the user or integrator. The method may also be used to program or generate the trajectories of the robot as not to exceed the speed of the movement under the condition of keeping the set maximum stopping time and/or distance as defined by a use.

An important part of the installation of an industrial robot as part of an application is to perform a risk assessment to evaluate if the installation is sufficiently safe. A result of a risk assessment can be that given the distance from a safeguarding measure to a potential hazard in the robot workspace, and the estimated speed of motion of a human worker, the robot integrator needs to ensure that the robot is capable of stopping within a certain amount of time.
For the integrator, it is a tedious and time consuming process to evaluate the stopping time of the robot. This is usually based on tables for given speeds, payloads, extensions and joint motions provided by the robot manufacturer. However, the high degree of flexibility in industrial manipulators with multiple degrees of freedom makes it infeasible to provide tables for all possible motions and payloads, thus leading to a need for interpolating between the various tables and combining this with actual measurements to validate the results and often also being overly conservative in the estimates.
U.S. Pat. No. 7,664,570B2 describes a method for limiting the motions of a robot according to physical and virtual safety barriers. It does however not consider the stopping time and distance traveled by the robot while stopping. The focus is on assuring that the robot does not cross the virtual or physical barriers.
EP1901150B1 describes a method where the calculation of stopping time and distance travel is used for predicting collisions with objects. It does however not allow the user to define stopping time limits or stopping distance limits.
EP2364243B1 describes a safety system and a method for reducing risk of injury based on an impact. It does however not describe considerations to stopping time and stopping distances.
US2016/176049A1 discloses a method for the conditional stopping of at least one manipulator and a manipulator assembly. The manipulator travels along a path which has a stopping point. In order to be able to stop the manipulator at the stopping point, a braking point on the path is calculated as a function of a speed of the manipulator. If the status of a travel condition variable necessitates braking of the manipulator in the event of exceeding the braking point, the manipulator is braked. This manipulator and manipulator assembly requires knowledge of the desired stopping point along the predetermined traveling path.
DE10361132A1 discloses a method for monitoring the movement of a hazardous object such as the handling mass of a handling unit relative to objects in a workspace around it. The kinetic energy of the hazardous object is constantly calculated by means of a dynamic model of the handling device and the speed of the dangerous object is constantly readjusted and monitored so that at a braking request within a defined path or optionally within a defined time the speed is reduced to a to a predeterminable non dangerous value. It is difficult to determine the kinetic energy of a hazardous object handled by handling device such as a robot arm as in order to obtain speed of the hazardous object need to be obtained in order to calculate the kinetic energy of the hazardous object. In a handling device such as a robot the speed of the hazardous object is typically obtained based on absolute positions sensors at the output side of the robot joints and the resolution of such absolute position sensors are low resulting in an inaccurate instant speed of the hazardous object. Consequently, the kinetic energy will also be calculated inaccurately.

Robot comprising safety system ensuring stopping time and distance


An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.

1. Field of the Invention
The invention relates generally to access devices, semiconductor devices incorporating an access device, and methods of fabricating same. More particularly, the invention relates to an access device having a vertically oriented channel and related semiconductor devices and methods of fabrication.
2. Description of Related Art
The operation of modern electronics is largely predicated upon the performance capabilities of the individual elements arranged to form semiconductor devices. The dynamic random access memory (DRAM) is an excellent contemporary and historical example of a semiconductor device. The DRAM is widely used in computer systems and other consumer electronics to store data. Their data storage capabilities have increased dramatically over the years as the elements implementing the DRAM have been substantially reduced in size without loss of functionality.
A DRAM may be understood as a vast array of memory cells arranged at the respective intersections of a matrix of row-wise word lines and columnar bit lines. Each memory cell typically includes an access element such a field effect transistor (FET) coupled to a storage element such as a capacitor. The access element allows the transfer of electrical charge from/to the storage element during read/write operations according to control voltages applied to a gate region of the access element.
The storage capacity per unit size of a DRAM is dictated to a large extent by the maximum possible integration density for the memory cells forming the memory cell array. In turn, the size of (i.e., the area occupied by) the constituent access elements and storage elements determines the maximum possible integration density. Accordingly, research and development efforts have been constantly expended in attempts to minimize the size of access elements and storage elements and improve integration density.
As a practical matter the integration density of a semiconductor device is limited by the collection technologies used to fabricate it. That is, the constellation of available technologies applied to the fabrication of a semiconductor device defines the physical scale of the individual elements forming the semiconductor device. This scale or feature size "F" may be used to designate minimum relative geometries for the elements, and largely determines the maximum integration density for the resulting semiconductor device. For example, Figure (FIG.) 1 is a graph illustrating a relationship between shrinking design rules, as indicated by the descending plot of squares, and various DRAM design families, as indicated by the plots of triangles (an 8F2 family), inverted triangles (a 6F2 family), and circles (a 4F2 family).
Existing and extrapolated die counts per fabrication wafer are shown for each design family over a period of time ranging from year 2002 through year 2010. Clearly, a move towards the 4F2 family of semiconductor devices will result in a greater number of die yielded per fabrication wafer. Such yield increase has important consequences to the profitability of semiconductor manufacturing operations.
However, in order to fabricate reliable semiconductor devices at a 4F2 scale, considerable additional attention must be directed to minimizing the size of constituent elements without loss of functionality. In this vein, the area occupied in a memory cell matrix by individual memory cells has been reduced by replacing laterally oriented access elements (i.e., access elements having a principal channel formed in the X/Y plane) with vertically oriented access elements (i.e., access elements having a principal channel formed in the Z plane orthogonal to the X/Y plane). Of course, the designation of X, Y, and Z orientations is an arbitrary one typically made in relation to the principal working surface of a substrate, but for clarity of description relative to the related drawings such designations are quite helpful. So, in the description that follows a convention will be adopted that assumes the X and Y directions are consistent with the orientation of word and bits lines running across a principal surface of a substrate, and that the Z direction is orthogonally "vertical" relative to this "lateral" X/Y plane.
With this convention is place, FIGS. 2A, 2B and 2C are considered. FIG. 2C is a perspective illustration showing a portion of a conventional DRAM memory cell matrix incorporating individual memory cells including a vertically oriented access element. Each access element has a vertically oriented channel extending in the Z direction from a buried bit line (BBL) region 2 formed on an isolation region 1 of a substrate to a storage node 5 formed above a word line 4. The vertical channel is implemented as a silicon pillar extending upward from the substrate. The transfer of electrical charge through the vertical channel is controlled by a gate 3. The term "pillar" in this context assumes a similar convention to that described above which assumes a horizontally disposed substrate populated by columnar or pillar shaped structures extending vertically (in the Z direction) from the substrate. The term pillar subsumes vertical structures having any reasonable aspect ratio.
As may be seen from reference to FIGS. 2A and 2B, individual memory cells including this type of vertically oriented channel may be more densely grouped together in a memory cell array in comparison with conventional memory cells incorporating access elements including a laterally oriented channel. That is, FIG. 2A is a top down illustration of a memory cell array defined by pillar mask patterns having a 2F by 2F cell matrix layout. FIG. 2B further illustrates this memory cell array by showing constituent word lines, bit lines, and an insulating oxide spacer.
Unfortunately, conventionally formed access devices including vertically oriented channels suffer from a number of performance and fabrication issues. A first class of these issues relates to the formation of a connection line (e.g., a word line in the context of a semiconductor memory device connecting a row of memory cells). Conventionally, connection lines such as word lines and gate electrodes associated with a connected access element are separately fabricated. This approach not only requires the application of two separate fabrication processes, but also suffers from problems associated with elevated connection line resistance caused by the presence of natural oxides or other contamination layers between the connection line and the gate electrode.
Another class of issues relates to the contact resistance between a subsequently formed connection (e.g., a storage element in the context of a semiconductor memory device) and an access element having a vertically oriented channel. Here again, contamination and/or abuse from fabrication processes may result in the formation of natural oxides, other contamination layers or material layer damage that results in elevated contact resistance between a subsequently element and an upper end of the vertically oriented access element (e.g., an upper source/drain region).
At least in the context of a RAM devices, vertically oriented access elements frequently result in high levels of gate induced drain leakage (GIDL). GIDL has adverse consequences to the refresh rate and power consumption of a memory device incorporating the access element.
Another class of fabrication related issues plaguing vertically oriented access elements in the context of semiconductor memory devices concerns the nature and geometric orientation or alignment of a buried bitline (BBL) structure. For reasons well understood in the art, a lightly doped (LD) structures are often preferred for the formation of lower source/drain regions associated with BBL structures. However, the formation of a LD lower source/drain region has proven to be a difficult task, requiring numerous fabrication steps and often resulting in alignment problems.
Taken as a collection, these continuing issues and others related to the design and fabrication of semiconductor devices incorporating access elements having a vertically oriented channel have greatly impeded manufacturers' practical ability to fabricate such devices at acceptable cost points and reliability expectations.

Access device having vertical channel and related semiconductor device and a method of fabricating the access device


A needle bearing has an outer sleeve and a needle cage. The sleeve is punched out of a flat sheet of metal and is coiled to be cylindrical. It has a window, and the needle cage has a corresponding window. The needle cage is guided circumferentially and axially inside the sleeve in such a way that the windows are aligned relative to one another so that an actuating member can pass radially through both windows. The needle bearing may be used, for example, for guiding a pressure pin for a braking mechanism of a vehicle.

This invention relates generally to a needle bearing having a window in a sleeve that provides an outer raceway and, more particularly, to such a needle bearing having a corresponding window in a needle cage inside the sleeve.
The windows in the sleeve and the needle cage allow another component to engage in the needle bearing in the radial direction, for example in order to rotate the needle cage about its axis or for the engagement of the other component in a further construction element arranged inside the needle bearing. This may involve a shaft which is designed, for example, to be non-circular in cross section and which, when rotated inside the needle bearing, displaces the additional component radially relative to the needle bearing.
Such a needle bearing is known from practical application. It has a deep-drawn outer sleeve which may be hardened and which has, in particular, a round or oval window. The needle cage has a corresponding window, the needle cage naturally not being fitted with a full set of rollers, but having no rollers in the region of the window. In this case, the needle cage with the rollers is inserted into the sleeve which is subsequently flanged over the needle cage at its ends in order to form a commercial needle bearing. The invention is based on the object of designing such a needle bearing to be simpler in construction in order to simplify the manufacture and assembly of the needle bearing, but especially to prevent closure of the sleeve window as a result of rotation of the cage. Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter.


Devices, methods, and systems for determining pushback direction are described herein. One method includes receiving a video image of an aircraft during a pushback of the aircraft, determining a motion flow map associated with the video image during the pushback, determining a motion orientation histogram associated with the video image during the pushback, and determining a direction of the pushback based on the motion flow map and the motion orientation histogram.

In various airports, aircraft (e.g., airplanes) can undergo a pushback. A pushback can include, for example, the aircraft being moved (e.g., pushed and/or pulled) from a terminal gate (e.g., using external power). A pushback can include the aircraft being aligned towards a taxiway leading to a designated runway prior to departure, for instance. Aircraft pushback can be accomplished using various devices (e.g., tractors, tugs, trucks, etc.) and/or airport personnel (e.g., air traffic controller(s) (ATCs), ground crew(s), etc.).
A pushback strategy under previous approaches may include an aircraft crew (e.g., pilot(s)) receiving clearance information from an ATC and thereafter requesting a pushback in a particular direction (e.g., specified by the ATC) to ground crew(s). Ground crew personnel, in a tug truck, for instance, may respond to aircraft crew using a radio in the truck. In various airport scenarios, however, ATC and ground crews may not be able to directly communicate with each other and/or may use different communication frequencies, for instance.
Miscommunication under previous approaches may yield an incorrect (e.g., unintended and/or off-target) direction of aircraft pushback. An incorrect direction of pushback may pose safety risks to passengers and/or personnel. For example, an aircraft may move towards other (e.g., arriving, departing, taxiing and/or parked) aircraft due to an incorrect pushback direction. Monetary costs associated with collisions and/or flight delays, for instance, may additionally be incurred due to incorrect pushback directions.


Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.

This invention relates to integrated circuits and, more particularly, to configurable register circuitry with error detection and error recovery capabilities in integrated circuits.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which has led to performance increases. However, more recent technology nodes have seen a significant slow-down in the reduction of delays and thus to a slow-down in the performance increase.
Timing analysis is usually performed to determine the delay of paths between synchronous elements. The delay of the longest-delay path, which is sometimes also referred to as the critical path delay, determines the clock rate at which the synchronous elements in the integrated circuits are triggered. Timing analysis is required to account for the worst case scenarios and needs to take variability in combinational logic delays caused by manufacturing or environmental variations into account. In many cases, additional timing guard bands are required to ensure proper operation across manufacturing and environmental variations leading to overly pessimistic timing requirements and thus to slow clock rates.
Furthermore, some synchronous designs implemented in integrated circuits such as data paths in packet processing applications are tolerant of occasional timing faults caused by timing variability. Such timing variability tolerant designs are often able to handle the occasional timing fault, especially when the timing fault can be detected.

Configurable register circuitry for error detection and recovery


A film formation method for a semiconductor process performs a film formation process to form a silicon-containing insulating film doped with a metal on a target substrate, in a process field inside a process container configured to be selectively supplied with a silicon source gas and a metal source gas. The method includes forming a first insulating thin layer by use of a chemical reaction of the silicon source gas, while maintaining a shut-off state of supply of the metal source gas; then, forming a first metal thin layer by use of a chemical reaction of the metal source gas, while maintaining a shut-off state of supply of the silicon source gas; and then, forming a second insulating thin layer by use of the chemical reaction of the silicon source gas, while maintaining a shut-off state of supply of the metal source gas.

1. Field of the Invention
The present invention relates to a film formation method and apparatus for a semiconductor process for forming a silicon-containing insulating film doped with a metal on a target substrate, such as a semiconductor wafer. The term "semiconductor process" used herein includes various kinds of processes which are performed to manufacture a semiconductor device or a structure having wiring layers, electrodes, and the like to be connected to a semiconductor device, on a target substrate, such as a semiconductor wafer or a glass substrate used for an FPD (Flat Panel Display), e.g., an LCD (Liquid Crystal Display), by forming semiconductor layers, insulating layers, and conductive layers in predetermined patterns on the target substrate.
2. Description of the Related Art
In manufacturing semiconductor devices for constituting semiconductor integrated circuits, a target substrate, such as a semiconductor wafer, is subjected to various processes, such as film formation, etching, oxidation, diffusion, reformation, annealing, and natural oxide film removal. US 2006/0286817 A1 discloses a semiconductor processing method of this kind performed in a vertical heat-processing apparatus (of the so-called batch type). According to this method, semiconductor wafers are first transferred from a wafer cassette onto a vertical wafer boat and supported thereon at intervals in the vertical direction. The wafer cassette can store, e.g., 25 wafers, while the wafer boat can support 30 to 150 wafers. Then, the wafer boat is loaded into a process container from below, and the process container is airtightly closed. Then, a predetermined heat process is performed, while the process conditions, such as process gas flow rate, process pressure, and process temperature, are controlled.
Nonvolatile memory devices are known as semiconductor integrated circuits of this kind. The nonvolatile memory devices encompass floating gate type memory devices including a floating gate and SONOS type memory devices including an electric charge trap layer (Jpn. Pat. Appln. KOKAI Publication No. 2006-229233). Recently, SONOS type memory devices including an electric charge trap layer have attracted attention, because they are relatively well operated in writing and erasing. A SONOS type memory device has a structure in which a silicon oxide film, an electric charge trap layer formed of a silicon nitride film, and a silicon oxide film are interposed between a semiconductor substrate, such as a silicon substrate, and a gate electrode made of, e.g., poly-silicon.
The electric charge trap layer is formed of a metal-doped film, which is a silicon nitride film (SiN film) doped with a metal, such as aluminum. Where a memory device includes such a film doped with a metal, the memory device is improved in some of the operational characteristics, such as writing, erasing, and retention.
For example, as a method for forming a metal-doped film of this kind, there is a method using a CVD (Chemical Vapor Deposition) method arranged to simultaneously supply film formation gases for forming an SiN film and a gas containing the metal into a process container. Further, there is a method for forming a film having a predetermined thickness, by alternately and intermittently supplying film formation gases to repeatedly laminate very thin layers each having an atomic or molecular level thickness one by one (for example, Jpn. Pat. Appln. KOKAI Publications No. 6-45256 and No. 11-087341). In general, this film formation method is called ALD (Atomic layer Deposition) or MLD (Molecular Layer Deposition), which allows a predetermined process to be performed without exposing wafers to a very high temperature.
Incidentally, in metal-doped films of this kind, the metal concentration in the film and the concentration distribution in the film thickness direction exert large influences on some of the characteristics of the metal-doped films. However, conventional methods described above for forming a metal-doped film tend to cause the metal concentration to be relatively higher, and thus entails a difficultly in setting the metal concentration to be relatively lower with high controllability. In this case, the electrical characteristic of the metal-doped film cannot be sufficiently improved. Particularly, in recent years, owing to the demands of increased miniaturization and integration of semiconductor integrated circuits, the problem described above needs to be solved.

Film formation method and apparatus for forming silicon-containing insulating film doped with metal


A shift register unit includes a latch circuit and a transmission circuit. The latch circuit is configured to process a clock signal received by its first clock signal end and a low level signal by a NOR operation to obtain a signal and output the obtained signal when a selection signal is of a high level; during a first time period where the selection signal is of a low level, process a signal outputted by the latch circuit when the selection signal is of a high level by a NOT operation, then process the resultant signal with a feedback signal by a NOR operation to obtain a signal and output the obtained signal; output a low level signal during a time period where the selection signal is of a low level other than the first time period. The transmission circuit is configured to output a signal related to the clock signal received by its first clock signal end when the signal outputted by the latch circuit is of a high level; and output a corresponding signal when the signal outputted by the latch circuit is of a low level.

In a conventional Low Temperature Poly-Silicon (LTPS) shift register unit, D flip-flops consisted of inverters and transmission gates are adopted. In generally, the conventional LTPS shift register unit includes two D flip-flops. In the LTPS shift unit, an output signal is latched by the D flip-flop, and shift and transmission of the signal are controlled by a clock signal.
FIG. 1 illustrates a representative structure of the conventional LTPS shift register unit. As illustrated in FIG. 1, in the LTPS shift register unit, a first D flip-flop is consisted of a transmission gate TG1, a NAND gate Nand1, an inverter INV1 and a transmission gate TG2, and a second D flip-flop is consisted of a transmission gate TG3, a NAND gate Nand2, an inverter INV2 and a transmission gate TG4. When a clock signal CLK is of a low level and a reverse clock signal CLKB is of a high level so that the first D flip-flop is turned on, a signal outputted by a previous shift register unit enters into the first D flip-flop. At this time, the transmission gate TG3 at a front end of the second D flip-flop is in an OFF state, and thus the signal outputted by the NAND gate Nand1 cannot enter into the second D flip-flop. On the other hand, when the clock signal CLK is of a high level and the reverse clock signal CLKB is of a low level so that the transmission gate TG1 in the first D flip-flop is turned off, the state of the D flip-flop in a previous clock period is latched by the first D flip-flop. In other words, when the clock signal CLK is of a high level and the reverse clock signal CLKB is of a low level, the first D flip-flop latches the signal outputted by the first D flip-flop when the clock signal CLK is of the low level and the reverse clock signal CLKB is of the high level. At this time, the transmission gate TG3 in the second D flip-flop is turned on, and the signal outputted by the first D flip-flop enters into the second D flip-flop which then outputs this signal. Thus, a shift operation of the signal from a previous shift register unit to a next shift register unit is implemented. When the shift register unit operates, a reset signal RST is of a high level.
However, for the display apparatus, each shift register unit is used only once during a time period for displaying one frame of image. For example, in the display apparatus, if there are N rows of pixels and the time period for displaying one frame of image is T seconds, then one shift register unit may be used for merely T/N seconds during the time period for displaying one frame of the image. That is, during the time period for displaying one frame of image, each shift register unit is kept in an operation state for merely T/N seconds, but in a non-operation state for T−T/N seconds. In other words, during the time period of one frame, an operation period of each shift register unit is only T/N seconds, and a non-operation period thereof is T−T/N seconds.
In the conventional shift register unit, turning on and off of all the transmission gates are controlled by the clock signal CLK and the reverse clock signal CLKB. Even during a non-operation period, the transmission gates are still turned on and off by the clock signal CLK and the reverse clock signal CLKB. Each of the transmission gates is consisted of parallel connected complementary transistors. When the transmission gates are controlled to be turned on and off by the clock signal CLK and the reverse clock signal CLKB, the clock signal CLK and the reverse clock signal CLKB is required to be inputted to gate electrodes of the transistors. In each of the transistors, the gate electrode covers a gate insulation layer, which covers a substrate. Thus, a capacitor is formed between the gate electrode and the substrate, which may be called a gate capacitor. In this manner, the gate capacitor of the transistor will be charged by the signal inputted to the gate electrode of the transistor when the signal is of a high level, and will be discharged by the signal when the signal is of a low level. As a result, during the non-operation period, such charging and discharging of the circuit may cause meaningless power consumption. A contemporary display apparatus often includes hundreds or thousands stages of shift register units, and only one stage of the shit register unit circuit is operating at a same time, meanwhile the other shift register units are in the non-operation state. At this time, both the clock signal CLK and the reverse clock signal CLKB will be inputted to the transmission gates of the transfer register units which are in the non-operation state, which may cause meaningless but large power consumption.
It can be seen from above that, due to the fact that the transmission gates in the conventional shift register units are controlled to switch between being-turned-on and being-turned-off by the two complementary and reversed clock signals during the non-operation period, the gate capacitors of the transistors in the transmission gates are charged and discharged during the non-operation period, which causes meaningless but large power consumption.

Shift register unit, display panel and display apparatus

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.


The subject invention provides a simple sensor and an easy to handle biosensor measuring apparatus for the purpose of making measurements easily, rapidly and with high accuracy for specific components within a biological specimen such as blood.. The biosensor of the subject invention is provided with a protrusion or a depression in a portion of a base having at least a measurement electrode and an opposing electrode. Also, the biosensor measuring apparatus is so configurated to have a mating means in the main body of the measuring apparatus freely supporting this biosensor to contact the said sensor's protrusion or depression, and further having the activating switch of the driving power supply located in this mating means.. By means of these, it is possible to prevent wasteful measuring operations, as noted in the prior art biosensors, such as inserting the sensor backwards and making measurements with the sensor inserted backwards.

In the context that in recent years various biosensors utilizing singular catalytic action of enzymes have been developed and are undergoing clinical trial applications, demand exists for biosensors capable of making rapid and highly accurate measurements.
Taking glucose sensors as an example, today when there is a marked increase in the number of persons afflicted with diabetes, the measurement and management of blood sugar require extremely complicated steps if blood were to be centrifuged to make measurements of the plasma as done traditionally and there is a demand for a sensor capable of making measurements from whole blood.
As a simple type, there is one, similar to the test paper used in testing urine, of using a stick-shaped support and placing thereon a medium containing an enzyme reacting only to a sugar (glucose) and a dye which changes at the time of enzyme reaction or due to the products of enzyme reaction. The method is to drip blood on this medium and to measure changes in the dye after a given period of time, either with the naked eye or optically, but there is much hindrance from colored substances in the blood and the accuracy is low.
On one hand, there are proposals for devices which, including the electrodes, can be thrown away after each measurement, but while making measurement operations extremely simple, from the standpoint of electrode materials, such as platinum, and their structure, they cannot avoid becoming very expensive devices. Also, while sputtering method or vapor deposition method can be used for manufacturing the platinum electrodes, they will be very expensive to manufacture.
As a throw-away method including the electrodes, a biosensor was proposed in the Laid Open Patent Application SHO 61-294351. This biosensor, as shown in FIG. 9, has an electrode system 30 (30'), 31 (31') and 32 (32') formed from such material as carbon by a method such as screen printing upon an insulating base 37, and after forming an insulating layer 33, the electrode system is covered by a multi-apertured medium 35 holding an oxidoreductase and an electron receptor, and the whole is unitized with a support 34 and a cover 36.
When a sample fluid is dripped onto the multi-apertured medium the oxidoreductase and the electron receptor held by the multi-apertured medium are dissolved by the sample fluid, enzyme reaction proceeds between the substrates in the sample fluid and the electron receptor is reduced. After the reaction is completed, the reduced electron receptor is electrochemically oxidized and the substrate concentration within the sample fluid is obtained from the value of oxidization current at that time.
In the above noted measurement, a given voltage is provided to the sensor's electrode system, the current flowing between the electrodes is measured, and the substrate concentration in the sample fluid is calculated on the basis of this signal.
In prior art structure such as that given above, wasteful measuring work occurred such as inserting the throw-away sensors backwards and even making measurements with sensors inserted backwards. Hence, there is desire for a simple sensor and easily manipulated biosensor device to simply, rapidly and highly accurately measuring specific components within a biological specimen such as blood.

Biosensor and measuring apparatus using the same

Matsushita Electric Industrial Co., Ltd.


A method for fabricating a metallurgy system is described wherein a first level of metallurgy is formed, having a plurality of close uniformly spaced conductive line of a predetermined width, and wherein there are included larger gaps between the conductive lines. The areas in the larger gaps are filled with dummy lines, where the gap is equal to or greater than three times the feature size or alternatively the width of the conductive lines.

1. Field of the Invention
This invention relates to a method, and the resulting structure, of fabricating semiconductor devices, and more specifically to a method of fabricating a multilevel planarized interconnection metallurgy system for integrated circuit devices.
2. Description of the Prior Art
The feature size in the state of the art of very large scale integrated circuits (VLSIs) such as high density memory chips, microprocessors and the like, has shrunk to the submicron level.
As the metal lines of the interconnection metallurgy systems have decreased, it is important to maintain as great a degree of surface planarity as possible. Surface planarity is critical in order (1) to accommodate the very shallow depths of fields of optical apparatus used for exposing the resist layers necessary to produce the metallurgy patterns, (2) to maintain a uniform metallurgy stripe thickness and (3) to avoid metal stringers.
When the initial metallurgy stripe pattern is formed on the planar surface of a substrate, it is subsequently covered by a dielectric layer. If the layer is conformal in nature, the resulting dielectric surface will be non-planar, i. e. the surface of the dielectric layer will dip down between the metal strips and thus present a surface with different levels. When a plurality of metallurgy layers are deposited, and each covered with a dielectric layer, each successive layers will contribute to the non-planarity, since there may be areas where a plurality of metal stripes are aligned or overlapped, and other areas where there may be less or no overlapped stripes.
A great deal of progress has been made in depositing the dielectric layer, so that the areas between the stripes will be filled while maintaining a greater degree of planarity. Such techniques include spin-on-glass (SOG) techniques, atmospheric pressure chemical vapor deposition (APCVD) techniques, tetraethylorthsilicate deposition in an atmosphere that contains O.sub.3 (TEOS/O.sub.3), and the like. These techniques have the capability to completely fill and locally planarize submicron gaps. These deposition techniques may be followed by an etch back to further promote planarity. The techniques are explained in an article in January 1992 Microelectronics Manufacturing Technology, Pages 22-27, entitled "Improved Sub-Micron Inter-Metal Dielectric Gap Filling using TEOS/Ozone APCVD".
However, while the above techniques fill submicron gaps between closely spaced metal lines, they are generally incapable of filling gaps between more distantly spaced lines. The problem is more clearly illustrated in FIGS. 1-5. FIGS. 1-5 show a semiconductor substrate 10 having a field effect transistor including source and drain regions 12, and gate 14. The substrate 10 also has a field oxide layer 16, and a relatively thick borophosphosilicate glass (BPSG) layer 18. A first metallurgy level including closely spaced metal stripes 20, and a widely spaced stripe 22, are shown in cross section. This is a typical device cross section, which illustrates the planarity problem presented by non-uniformly spaced metal stripes.
The reason for the non-uniform spacing is that the interconnection system must join the devices in an operative circuit, and it is not possible to design such a circuit where all the lines are uniformly spaced and parallel. In FIG. 2, there is illustrated the deposition of environment. FIG. 3 shows a dielectric layer 26 deposited by spin-on-glass techniques. Note that the gaps between closely spaced metal lines 20 are filled, but the wide gap between lines 20 and 22 is not filled, because of the limitations of the prior art processing. The problem with this wide gap is for the following layer lithography. It causes poor planarity for this next layer.
In FIG. 4, layer 26 is etched back which tends to increase the planarity of the top surface over closely spaced stripes 20, but does nothing to increase it in the wide gap. In FIG. 5, there is shown a layer 28 deposited by PE/CVD techniques. This layer still does not provide a planar surface over the wide gap. In practice, a second metallurgy layer would be deposited on the surface, after forming via holes to the metal stripes. It is believed apparent that as the metallurgy layers are built up, the surface planarity will deteriorate.
U.S. Pat. No. 5,077,234 proposes a solution to increase planarity of a semiconductor, when the semiconductor contains trenches or the like. The solution proposed utilizes three resist layers, and is believed to be inappropriate to the problem addressed by this invention.

Planarized metallurgy structure for a semiconductor and process of fabrication

Taiwan Semiconductor Manufacturing Company


A hyperpolarized liquid contrast agent is for use in a MRT device. The liquid contrast agent passes through a conduit of a MW resonator in the magnetic field of the MRT device. A microwave with a frequency of at least 40 GHz couples into the MW resonator for polarizing the liquid contrast agent upon passage through the conduit in the MW resonator using DNP. The contrast agent is polarized in a continuous passage in the MW resonator and administered immediately. A MW mode is formed in the MW resonator which has an antinode in the magnetic field strength and a node in the electric field strength. The power of the introduced microwave and coupling of the microwave into the resonator are adjusted such that in the area of the line, an amplitude of the MW magnetic field strength

Magnet resonance tomography (MRT) is an imaging method, which is above all used in medical diagnostics for representing structures and functions of tissue and organs in the body. MRT is based on the principles of nuclear magnetic resonance NMR spectroscopy. For this method, the tissue to be examined is located in a strong static magnetic field, in which the spins of atomic nuclei in the examined tissue are aligned, which results in magnetization. Through resonant excitation with an electromagnetic alternating field in the radio frequency range, the magnetization can be deflected from the direction of the static field. Due to the excitation, the spins start to precess around the direction of the static magnetic field, and the precession of the overall magnetization can be measured as a voltage signal using a coil.
When the high-frequency alternating field is switched off, the spins relax back into their initial state. For this relaxation, they require a characteristic decay time, which is typical for various elements and various compounds and can be detected. Then, from this decay information, a tomographic image can be constructed.
Magnetization of the nuclear spins in the external magnetic field is a statistical process, which follows the Boltzmann distribution. Since the energy of the interaction between the nuclear spins and the static magnetic field as compared to the thermal energy at room temperature is relatively small, the overall magnetization by the static magnetic field is likewise relatively small, at the expense of the NMR signal.
One method to increase sensitivity of the NMR consists in increasing the strength of the static magnetic field, whereby a less uniform occupation of the nuclear spin states is achieved. However, there are technical limits to the strength of the magnetic field; typically, in state-of-the-art MRT devices, it is 1.5 T. With magnetic field strengths of more than 3.0 T, the patients can be moved into the magnet very slowly only, in order to minimize induced eddy currents, for example in the brain of the patient.
A further measure for increasing sensitivity consists in polarizing the sample more than what would correspond to the thermal occupation of the spin states in the given magnetic field. A sample, for which the occupancy of one or more spin states predominates compared to the other spin states clearly more than their energy difference according to the Boltzmann statistics would predict, is called hyperpolarized.
In MRT, it is known to administer a hyperpolarized fluid to a living being to be examined, i.e. a patient or an animal to be examined, which fluid generates NMR signals enhanced by several orders of magnitude. On the basis of the terminology from X-ray diagnostics, such hyperpolarized fluid is also designated as "contrast agent". Predominantly, gases are used as contrast agent. However, it is also known to inject hyperpolarized liquids into the living being to be examined.
A known technology to hyperpolarize the contrast agent represents the so-called dynamic nuclear polarization (DNP). For DNP, first, electron spins in an external magnetic field are polarized. With resonant excitations of the electron spins in the microwave range, the electron spin polarization can be transferred to the nuclear spins by means of a weak interaction between the electrons and the nuclei. The underlying mechanisms are known as Overhauser effect, solid effect, cross effect, and so-called "thermal mixing".
Herein, it is common that the contrast agent is polarized in its frozen state and in a relatively strong static magnetic field of, for example, 3.35 T. Under these conditions, the nuclear spins can be polarized considerably stronger than in the liquid state. However, in order to be able to administer the hyperpolarized contrast agent, first, it must be melted and transported to the patient. Then, the problem occurs that a substantial part of the hyperpolarization is lost due to relaxation processes upon transport. Furthermore, the method known from the state of the art is relatively complex.

Hyperpolarization apparatus and method for administration of a hyperpolarized liquid contrast agent

Abstract: B    1    ≥            1.5      ·              10                  -          2                          Ts              1              T                  1          ,          e                    results, wherein T1,e is the relaxation time of the DNP-active electrons.

Johann Wolfgang Goethe-Universität Frankfurt am Main


A method of on-press developing a thermosensitive lithographic printing plate with ink and/or fountain solution is described. The lithographic plate comprises on a substrate a thermosensitive layer soluble or dispersible in ink and/or fountain solution and capable of hardening upon exposure to an infrared radiation. The printing plate can be a pre-coated plate in the form of sheet or web, or can be prepared on press by coating a thermosensitive layer onto a substrate that is a sheet material or a seamless sleeve mounted on a plate cylinder or is the surface of a plate cylinder of the lithographic press.

Lithographic printing plate (after process) generally consists of ink-receptive areas (image areas) and ink-repelling areas (non-image areas); the image areas and the non-image areas are substantially on the same plane. During printing operation, ink is preferentially received in the image areas, not in the non-image areas, and then transferred, usually through a printing blanket, to the surface of a material upon which the image is to be produced.
At the present time, lithographic printing plates (processed) are generally prepared from lithographic printing plate precursors (also commonly called lithographic printing plates) comprising a substrate and a photosensitive coating deposited on the substrate, the substrate and the photosensitive coating having opposite surface properties (such as hydrophilic vs. oleophilic, and oleophobic vs. oleophilic). The photosensitive coating is usually a photosensitive material, which solubilizes or hardens upon exposure to an actinic radiation, optionally with further post-exposure overall treatment. Here, hardening means becoming insoluble in a certain developer. In positive-working systems, the exposed areas become more soluble and can be developed to reveal the underneath substrate. In negative-working systems, the exposed areas become hardened and the non-exposed areas can be developed to reveal the underneath substrate. The exposed plate is usually developed with a liquid developer to bare the substrate in the non-hardened areas.
On-press developable lithographic printing plates have been disclosed in the literature. Such plates can be directly mounted on press after exposure to develop with ink and/or fountain solution during the initial press operation and then to print out regular printed sheets. No separate development process before mounting on press is needed. Among the patents describing on-press developable lithographic printing plates are U.S. Pat. Nos. 5,258,263, 5,516,620, 5,561,029, 5,616,449, 5,677,110, 5,811,220, 6,014,929, 6,071,675, and 6,242,156.
Conventionally, the plate is exposed with an actinic light (usually an ultraviolet light from a lamp) through a separate photomask film having predetermined image pattern that is placed between the light source and the plate. While capable of providing plate with superior lithographic quality, such a method is cumbersome and labor intensive.
Laser sources have been increasingly used to imagewise expose a printing plate that is sensitized to a corresponding laser wavelength. This allows the elimination of the photomask film, reducing material, equipment and labor cost.
Among the laser imagable plates, infrared laser sensitive plates (also called thermosensitive plates or thermal plates) are the most attractive because they can be handled and processed under white light, at least for limited time. Various thermosensitive plates have been disclosed in the patent literature. Examples of thermosensitive plates are described in U.S. Pat. Nos. 4,054,094 and 5,379,698 (laser ablation plates), U.S. Pat. Nos. 5,705,309, 5,674,658, 5,677,106, 6,153,356, 6,232,038, and 4,997,745 (negative thermosensitive plates), U.S. Pat. Nos. 5,491,046 and 6,117,610 (both positive and negative thermosensitive plates, depending on the process), and U.S. Pat. Nos. 5,919,600 and 5,955,238 (thermosensitive positive waterless plate).
Despite the progress in conventional on-press developable plates and digital laser imagable plates, there is a desire for a on-press developable thermosensitive lithographic printing plate and method which utilize infrared laser or other infrared radiation, do not produce ablation debris, do not require a separate liquid development process, and are easy to use.

This patent is subject to a terminal disclaimer.

Method of on-press developing thermosensitive lithographic printing plate


Systems and methods are provided for filtering detected events to determine events of interest. A sensor data analysis system identifies a plurality of detected events from provided sensor data and evaluates the sensor data to determine at least one characteristic associated with each event. The sensor data analysis system reports the plurality of detected events and their associated characteristics. At least one affiliated event generator is operative to generate at least one affiliated event and produce at least one event report. A given event report provides at least one characteristic associated with an affiliated event. An event filtering system compares the at least one event report to the detected events to identify at least one affiliated event amongst the plurality of detected events.

Advances in sensor technology have made it possible for sensors to provide significant amounts of information concerning an area of interest. For example, wide-range sensors can be mounted to high-altitude aircraft or orbital satellites to provide a comprehensive view of the area. These sensors can provide continuous monitoring of events occurring within the area of interest, but generally, view so many events that it is not always easy to discern which events are of interest, or easily identify events caused by affiliated sources. In some applications, mobile short-range sensors, focused area sensors, or human investigators can be made available for further investigation of a given event, but the sheer number of events generally detected within a given area can make it difficult to allocate these resources effectively, or to provide adequate discernment thereby.
Under the prior state of the art, extraction of useful decision making information from the sensor data can be a difficult process. The various sensors work independently of other available information, making it difficult to distinguish (without significant human intervention) interesting events from events already known by decision makers. This intervention adds to the expense of collecting data, introduces the possibility of human error, and, most importantly, significantly delays the interpretation and enhancement of the collected data. Since the cause of an event may not be apparent even shortly after the occurrence of the event, it is important to quickly and decisively appreciate the importance of an event, and gather desired information while the information is available.
When dealing with these situations in the past, it has been the duty of human operators to determine meaning from provided sensor data. The sensor readings are analyzed by a staff of individuals in light of available knowledge of the area of interest, and sensor resources are allocated to further investigate events on an ad hoc basis. Amongst other problems, the decision-making staff is faced with the problem of optimizing the allocation of sensor resources to interesting events. The number of events occurring within an area of interest at any given time generally exceeds the available sensor resources, such that a desirable level of sensor resources can generally not be brought to bear on every detected event. As the number of sensor systems and detected events increase, such determinations become increasingly difficult.


An image forming apparatus includes a body, a cartridge, detachably mountable to the body, configured to form a toner image, an information recording portion provided in the cartridge and configured to record information, a control portion provided in the body and configured to electrically communicate with the information recording portion, and a connector provided in the body and configured to electrically connect the control portion with the information recording portion. The connector has a temperature detecting portion configured to detect temperature.

1. Field of the Invention
The present invention relates to an image forming apparatus configured to form an image.
2. Description of the Related Art
An image forming apparatus is configured to form a toner image by developing an electrostatic image formed on a photoconductive drum by a developing unit, to transfer the toner image thus formed to a recording medium directly or through an intermediate transfer body, and to fix an image on the recording medium by applying heat and pressure to the recording medium to which the toner image has been transferred. A cartridge is a replacement unit in which the photoconductive drum and the developing unit are integrated and is detachably mounted to the body of the image forming apparatus.
In response to a start of the image forming apparatus, developer is agitated and rubbed within the developing unit, and a temperature of the developer gradually increases and converges to a temperature corresponding to an ambient temperature of the developing unit. It is not preferable to expose the developer to high temperature because fluidity of the developer within the developing unit is hampered for example. To that end, a conventional image forming apparatus is provided with temperature sensors at predetermined positions within the image forming apparatus. Then, if the temperature sensors detect a final threshold temperature, e.g. 100° C., the image forming apparatus is prohibited from forming an image more than what has been formed and is required to be inspected and its part is replaced and is reset by a serviceman. Or, image forming apparatuses of Japanese Patent Application Laid-open Nos. 2003-5614 and H11-272147 are provided with a cooling fan therein and an output of the cooling fan is automatically controlled such that a temperature of a developing unit is kept within a predetermined temperature range.
If a temperature sensor is disposed within a developing unit (including a case where the developing unit is built in a cartridge) to directly measure a temperature of developer, the temperature sensor ends up being replaced in replacing the developing unit. Although the temperature sensor may be used even when the developing unit is replaced in a case where the temperature sensor is disposed outside of the developing unit as disclosed in JPA Nos. 2003-5614 and H11-272147, detected temperatures of the temperature sensor largely differ depending on a state of contact and a distance between the temperature sensor and the developing unit. Even if an increase or a drop of a temperature of the developer within the developing unit may be determined from an output of the temperature sensor, it is difficult to accurately estimate an actual temperature level of the developer within the developing unit.
Then, there is proposed an arrangement in which an engage part dedicated for a temperature sensor is provided on an outer wall of the developing unit and the temperature sensor suspended from a body side by bundled wires is attached to/removed from the engage part dedicated for the temperature sensor in replacing the developing unit. In this case, however, although reproducibility of the state of contact of the developing unit and the temperature sensor is high, this arrangement requires the engage part dedicated for the temperature sensor and the dedicated bundled wires and adds another work of attaching/removing the temperature sensor in replacing the developing unit.


A pen with light source comprises an upper case with a press-on turning device, an at least semi-transparent lower case, mounted on the upper case and containing a pen refill, and a lighting device, inserted inside the upper and lower cases, further comprising two end pins, two springs, a battery socket, batteries, a lamp socket, and a lamp, wherein the two end pins are electrically connected and disconnected by pressing on the press-on turning device, switching on and off the lamp, with above structural parts allowing for easy manufacturing and ensuring high luminosity.

1. Field of the Invention
The present invention relates to a pen, particularly to a pen with an integrated light source.
2. Description of Related Art
Stationery articles usually are made without integrated light sources. A pen with integrated light source is not only usable for writing, but also for illuminating, performing decorative functions, extending the range of application and enhancing fun of use.
China patent no. 02200769.5 "Pen with light source operated by pressing with soft coating" discloses a pen with an integrated light source, which is operated by thumb-pressing, and a soft coating. The pen has a pin in an eccentric position, an electric circuit and wires. A switch having two terminals controls switching on and off of light. Since the switch and a pen refill are mounted on a common axis, pressing down thereon will cause a ballpoint of the pen to project outward and simultaneously the light source to be switched on. The coating has protective as well as decorative functions. However, there are still structural parts that are required for improvement, like connecting wires, a conductive ring, a casing, a thread, the eccentric pin, a spring, end pins, and another spring. Terminals of a battery have too complicated structures, therefore are too expensive to manufacture and are prone to defects, so that the lifetime of the pen is limited. Furthermore, a case with a metal section is used, in which a lighting element is placed, so that luminosity is reduced.


The present invention provides a method and device for creating a relation-type form database, the method comprising: displaying an existing form as a background image on a screen; drawing frames on predetermined positions of the background image with an operation means to create multiple data areas; and creating parallel relations and/or cross relations among the multiple data areas to form a relation-type database of the existing form. The operations of the present invention are easy and low-cost, which enable widely spreading of the application of databases.

At the present, the technology of the common application software or databases, such as Oracle, Microsoft's SQL and Access etc., are based on the behindhand hardware environment of 1980's. At that time, there are no displays with high resolution, and scanners are not widespread either. Creation of a database structure has to be limited by a character terminal, since the database structure is described in words. With development of tens of years, however, the condition for creating the database structure remains unchanged, and the creation of all database structures have to be subjected to a series of complex definitions or assignments. A programmer has to program the inputs and outputs of data with programming languages. The database's maintenance needs the source codes of the programs provided by the original program designer so as to maintain or update the software of the database.
With spreading of computers, many enterprises have realized the importance of creating the company databases. The creation of a conventional database usually utilizes Oracle, MS SQL . . . , causing demands of purchasing specific database software, and the construction of the database and the maintenance in the course of system life must be performed by professionals. Thus, the cost is high, and it is a burden of the intermediate or small scale enterprises.
The conventional approach of creating a database continues to be used up to now, and the dramatic overheads result in requirements for database system with convenience, high efficiency and low cost.

Method and device for creating relation-type form database


A combine and corn harvesting head of the type for removing ears of corn from their associated stalks are disclosed herein. The harvesting head includes a row unit for each row to be harvested by the combine while following a path through a field of corn to be harvested. The row units each include a stationary vertical surface and a continuous belt rotatably supported to provide a moving surface parallel to the vertical surface. The row unit removes ears of corn from their respective stalks when the ears are engaged by both the moveable and the stationary surfaces. More specifically, the movement of the moveable surface relative to the stationary surface rotates the ears relative to the stalks (i.e. rolls the ears along the stationary surface) to remove the ears and to convey them to the conveying auger of the harvesting head. The ears are then conveyed into the combine where they are threshed to remove the kernels of corn from the cobs of the ears.

Typical combines are designed to harvest a variety of grain generating plants, such as, corn, wheat, oats, etc. Depending upon the type of plant to be harvested, the combine will be fitted with a harvesting head or header configured to harvest the desired plant. For example, the Case 2100 series combine can be used with a header for harvesting wheat, barley, milo, and flax, with a header for harvesting soy beans, and with a header for harvesting corn. However, as with most high quality and high durability agricultural implements as those of Case Corporation, such headers are relatively heavy and may require that the associated combine have four or six front tires to provide proper ground bearing pressures.
Turning to the corn harvesting head, attempts have been made to simplify and to reduce the weight of the components thereof. However, many such attempts have failed because the resulting header is not as effective in harvesting corn as the corn headers of the type sold by Case Corporation. Conventional headers which have been found to be relatively effective for harvesting corn typically include row units, each including two gathering chains, two snapping rolls, and a pair of associated stripper plates. In operation, the snapping rolls rotate to pull the corn stalks downwardly past the stripper plates. As the stalks are pulled downwardly, the ears of corn attached to the stalks are stripped from the stalks by the plates. The stripped ears are then conveyed into an auger of the header by the gathering chains.
In view of the current design of corn headers, it would be desirable to simplify and to reduce the weight of such headers. Furthermore, it would be desirable to reduce the energy required to remove such ears.

Corn head snapping and gathering row unit