A monitoring system monitors a laser process which delivers energy from a laser source to a workpiece along a process path while producing plasma at a beam delivery point along the path. An infrared radiation detector is positioned for receiving infrared radiation from a point behind and in close proximity to the beam delivery point. The detector provides a temperature signal having a value which varies with changes in the intensity of the received infrared radiation over a predetermined test interval. A plurality of temperature limits are established with each temperature limit having a different value. The temperature signal is compared with each temperature limit and a violation indication is provided each time the temperature signal violates one of the limits. The number of violation indications for each limit are counted over the predetermined test interval. The laser process is evaluated as a function of the number of violation indications during the test interval. An output indication is provided as to the result of the evaluation.

The T. Webber U.S. Pat. No. 4,663,513 discloses a system for monitoring a laser process in which a laser source is employed for delivering energy to a workpiece along a process path while producing plasma at a beam delivery point along the path. An infrared detector receives infrared radiation from a point behind and in close proximity to the location of the beam delivery point. The radiation detector provides an analog temperature signal having a value which varies over time with changes in the intensity of the received infrared radiation. The analog temperature signal is compared against a window range of acceptable temperatures including a fixed upper limit and a fixed lower limit. If the temperature signal is not within the window range, then the output of the laser process, such as a welding process, is rejected.
It is to be particularly noted that the system described in the aforesaid patent provides either a process rejection or acceptance depending upon whether the temperature signal has a value which is within the window range or which is outside of the window range. Consequently, this is a pass-fail test. No teaching is presented for determining relative quality of the laser process. There is no suggestion that a plurality of samples be taken of the temperature signal with each of the samples being compared with a plurality of different temperature limits, the results of such comparisons being used to calculate a quality factor.
Still further, the aforesaid patent provides a fixed upper limit. This does not allow for a laser process having ranges of different, but normal, temperature values. For example, in a laser weld process, there is a turn-on overshoot condition which has an increased temperature. There may also be a weld overlap region on a workpiece which may produce an increased temperature during the weld process as the laser beam passes over a previously welded area.
Moreover, the aforesaid patent does not provide for archival storage of information so that the data obtained from a laser process analysis may be reviewed at a later point in time.
Additionally, the aforesaid patent does not provide for differentiating between normal weld sparking and detrimental splatter conditions when evaluating a laser weld process.
The present invention is directed toward improvements over the process and apparatus of the aforesaid patent to satisfy the foregoing shortcomings.


An antenna device has a sheet-shaped support which is folded along various fold-lines. The support includes a first support plane adjacent to one of the fold-lines and a second support place adjacent to the same fold-line. The first and second support places have first and second antenna structures, respectively, each arranged for receiving or emitting electro-magnetic radiation. The second support plane is positioned at an angle with respect to the first support plane. The second antenna structure is sensitive to electro-magnetic radiation which differs in, e.g., polarization from that of electro-magnetic radiation to which the first antenna structure is sensitive.

1. Field of the Invention
The invention relates to an antenna device. The invention further relates to an antenna array, an intermediate product for an antenna device and a method for manufacturing an antenna device.
2. Description of the Prior Art
Antenna devices are generally known and used for receiving and emitting electro-magnetic radiation and may, for example, be employed in radar and other direction finding systems, astronomical observatories and satellite receiving equipment, for example. Often, an antenna device has to receive or emit electro-magnetic radiation with differing spatial properties, for example electro-magnetic radiation with different directions of polarization or electro-magnetic radiation stemming from different sources (and, accordingly, emitted from different positions).
For instance, for receiving electro-magnetic radiation with different polarizations dual polarized antenna devices are known. A dual polarized phased-array antenna is known, for example, from the European patent publication 0 349 069 A1. This prior art document describes a phased-array antenna having a plurality of antenna elements positioned in a matrix-shaped arrangement. The matrix comprises an assembly of two orthogonal sets of parallel insulating planar supports. Each of the insulating planar supports is provided with a conductive surface layer patterned to form a succession of tapered notch antenna elements. The tapered notch antenna elements are distributed along an outward facing edge of the planar support. Each of the tapered notch antenna elements has a polarization parallel to the planar supports. The phased-array antenna thus comprises two orthogonal sets of line-shaped arrangements of tapered notch antenna elements, of which sets each has a respective, orthogonal polarization.
In the phased-array antenna described in the above mentioned patent publication, the insulating planar supports of each set intersect and engage on the supports of the other set. To that end, the supports are provided with a slot extending from the edge of a planar support to half way across the support. The sets are positioned such that the supports of one set extend in the slots of supports of the other sets. The supports of one set thus intersect and engage with the supports of the other set to form a matrix-shaped support structure.
However, a draw-back of the antenna device described in said patent publication is that each planar support has to be provided with a multitude of slots, in which thereafter the supports of the other sets have to be positioned. Accordingly, manufacturing of the dual polarized phased-array antenna is complex. Furthermore, the planar supports have to be made of a rigid material in order to obtain a support construction with sufficiently high stiffness, which limits the choice of materials which can be used in the antenna device.

Dual polarised antenna device for an antenna array and method for manufacturing the same


An alligator clip holder is provided for supporting and retaining at least one fishing rod on a support device. The holder includes a first clip member and a second clip member pivotally connected to each other by a pivot pin. A resilient member is disposed about the pivot pin with two opposite ends in contact against respective surfaces of the first and second clip members so as to permit clamping attachment of the first and second clip members to a support device. A retaining bar assembly is rotatably and slidably positioned on a top end of one of the first and second clip members for supporting and retaining at least one fishing rod thereon.

When ice fishing, a fisherman will occasionally leave an ice fishing hole unattended with the result that a powerful strike by a fish will pull the entire fishing rod into and through the hole so that the fishing rod is lost. A similar result may occur in open water fishing to an unattended fishing rod lying on a pier or extending from a boat. Because the loss of one's fishing rod along with a lure can be a sizable expense to replace, it is desirable to provide a solution which will inexpensively and efficiently insure the security of one's fishing rod in various fishing environments.

Alligator clip holder for supporting a fishing rod


The present invention discloses an automatic pancreas CT segmentation method based on a saliency-aware densely connected dilated convolutional neural network. Under a coarse-to-fine two-step segmentation framework, the method uses a densely connected dilated convolutional neural network as a basis network architecture to obtain multi-scale image feature expression of the target. An initial segmentation probability map of the pancreas is predicted in the coarse segmentation stage. A saliency map is then calculated through saliency transformation based on a geodesic distance transformation. A saliency-aware module is introduced into the feature extraction layer of the densely connected dilated convolutional neural network, and the saliency-aware densely connected dilated convolutional neural network is constructed as the fine segmentation network model. A coarse segmentation model and the fine segmentation model are trained using a training set, respectively.

In the diagnosis and prognosis prediction of pancreatic diseases, a necessary task is to identify and segment pancreatic regions from medical images (such as magnetic resonance Imaging (MR), computer tomography (CT)). Accurate segmentation of the pancreas can provide a variety of important biomarkers, such as volume, three-dimensional shape features, three-dimensional curved surface features, and so on. For example, pancreatic volume can provide assistance for evaluating endocrine and exocrine functions of the pancreas, and predicting the occurrence of pancreatic fistula after pancreaticoduodenectomy. However, it is time-consuming and labor-intensive to delineate the pancreas boundary from the three-dimensional images layer by layer, and it is variable under different operators and different operations. Therefore, the study of fast and robust pancreas automatic segmentation algorithm has important clinical significance and value.
Automatic Pancreas CT segmentation is a challenging task because: 1) the pancreas occupies a very small proportion of entire CT, resulting in a huge gap between the foreground and the background of the image segmentation task; 2) the pancreas shares the gray-scale texture distribution with surrounding organs and tissues, and the boundary is blurred or there is no visible boundary; 3) the pancreas has an irregular shape, and there are great differences in location and size. These characteristics make traditional segmentation algorithms based on image information (such as level set, graph cut, threshold method) not suitable for automatic pancreas segmentation.
In recent years, deep learning methods have made great breakthroughs in the task of pancreas segmentation. Existing methods generally adopt a two-step or iterative segmentation method from coarse to fine, that is, first a coarse segmentation network model is trained to predict an initial segmentation area of the pancreas. Then, a region of interest of the pancreas image is cropped by using the position information of the initial segmentation, to obtain smaller image blocks as the input of the fine segmentation network, and a fine segmentation network model is trained to obtain the final segmentation result of the pancreas. Although reducing the detection difficulty caused by the small pancreatic area, the method does not make full use of the initial segmentation information and only uses the position information. On the other hand, in the current pancreas segmentation methods based on deep learning, the more commonly used network models are end-to-end U-Net, DenseNet, ResNet, etc., without special consideration of the characteristics of variable size of the pancreas.

Automatic pancreas CT segmentation method based on a saliency-aware densely connected dilated convolutional neural network


A switch device is provided that ensures formation of a communicable area by a coil antenna. The switch device includes an ignition switch operated by an operator for driving an engine starter, a decorative cap arranged to surround the ignition switch and having an ornamental surface, and the coil antenna arranged adjacent to the decorative cap for transmitting a transponder-driving radio wave. The decorative cap includes a transmittable area that can transmit the transponder-driving radio wave therethrough. The transmittable area is formed in a part of the decorative cap excluding the ornamental surface.

The present invention relates to a switch device, and in particular, to a switch device operated for driving a device.
To prevent vehicles from being stolen, portable devices, which transmit an ID code signal including an ID code, have recently been used instead of conventional mechanical keys. Such a portable device is held by a user (owner) of a vehicle. A "smart ignition" function has been proposed, which enables the engine of a vehicle to start based on an ID code signal wirelessly transmitted from the portable device. As one example, Japanese Laid-Open Patent Publication No. 2002-188505 discloses an engine controller for vehicles with the smart ignition function.
Normally, the portable device, held, for example, in a pocket of the user's clothing, mutually communicates with the vehicle by automatically transmitting an ID code signal to the vehicle. The engine of the vehicle is enabled to start by operating an ignition switch, when an ID code included in the ID code signal transmitted from the portable device matches an ID code preset for the vehicle. When, for example, a battery of the portable device is drained, the portable device does not automatically transmit an ID code signal. In this case, the user places the portable device in a communicable area where the portable device can receive a transponder-driving radio wave transmitted from the vehicle. A transponder built into the portable device receives a transponder-driving radio wave from the vehicle to generate electric power, and transmits a transponder signal using the electric power. In this way, the portable device mutually communicates with the vehicle, using a transponder signal transmitted from its transponder. When a transponder code included in the transponder signal transmitted from the portable device matches a transponder code preset for the vehicle, the engine of the vehicle is enabled to start by operating the ignition switch.
To realize this, a coil antenna for outputting a transponder-driving radio wave and the ignition switch are installed in the vicinity of the driver's seat in the vehicle. In recent years, however, vehicle systems have been rapidly computerized and have become provided with more functions. This has increased the number of electric and electronic components used in vehicles. This has created a demand for reducing the space occupied by each component mounted in a vehicle. To meet the demand, a switch device, in which a coil antenna and an ignition switch with a push button are integrally arranged, has been proposed.
In such a switch device, a decorative member whose surface is furnished with decorative plating is provided to surround the outer rim of the push button. This improves the appearance quality of the passenger compartment. Further, the push button stands out.
When, however, the coil antenna is arranged close to the decorative member, a transponder-driving radio wave output from the coil antenna is easily blocked by the decorative plating on the surface of the decorative member. This makes it difficult to form a communicable area where the vehicle is communicable with the portable device using a transponder-driving radio wave. Thus, the coil antenna fails to fully exhibit its communication function.

Kabushiki Kaisha Tokai Rika Denki Seisakusho


An electromagnetic relay includes a contact including a movable spring having a base end fixed to a bottom of a housing and a tip end provided with a movable contact, and a fixed spring having a base end fixed to the bottom of the housing and a tip end provided with a fixed contact. The movable contact is provided opposite to the fixed contact so as to come in contact with the fixed contact or move away therefrom. The housing has a protrusion protruding toward a side of the fixed contact opposite to a side facing the movable contact.

1. Field of the Invention
This invention relates to an electromagnetic relay.
2. Description of the Related Art
An electromagnetic relay which includes an electromagnet, an actuator which is actuated in response to a magnetic action of the electromagnet, a contact which opens and closes in response to the actuation of the actuator, and a housing for accommodating the electromagnet, the actuator and the contact is known (See JP 2008-210776 A.).
There is a need for an electromagnetic relay with improved reliability of an opening and closing operation of a contact part.


Methods and apparatus are provided for estimating the remaining state-of-charge of a non-rechargeable power source, such as a back-up battery for an electronic module normally connected to a primary power source. A processor within the electronic module implements a prediction algorithm, in order to monitor the temperature of the back-up attery, and to calculate various current draws of the back-up battery. The processor adjusts the nominal self-discharge rate of the back-up battery in accordance with the measured temperatures, and calculates an adjusted self-discharge quantity. The processor also accumulates current draw data and reduces the initial state-of-charge value of the back-up battery by the temperature-adjusted self-discharge quantity and the cumulative current draw quantities to determine a remaining state-of-charge of the back-up battery. At a predetermined state-of-charge threshold level, an indicator can be activated to advise a user to replace the back-up battery.

Recent developments in automotive technology have introduced various devices to enhance the safety and convenience of the driving experience. For example, air bags are now commonly deployed in vehicles to reduce the likelihood of injury in an accident, and on-board navigation systems are used to help the driver find his/her way to a destination. Another recent development is an on-board telematics system, such as the "OnStar" system. This type of telematics system enables the driver to access many types of services via a wireless communication from the vehicle to an affiliated call center. The call center can then respond to a driver's request for service, which typically includes navigation instructions, roadside assistance, emergency services, and other types of information.
In general, a telematics system is configured as an electronic module installed in a vehicle, and connected to a primary power source, which is typically the main vehicle battery. This type of system is generally intended to provide a driver with various types of call center services, and also to provide an automatic notification capability to a call center in the event of an emergency situation, such as the deployment of an air bag in the vehicle. Therefore, it is generally desirable that a back-up power source be available for the electronic module in the event of primary power disruption. The back-up power source is generally in the form of a relatively low power battery, designed to provide sufficient power to the electronic module to accommodate an emergency situation.
Over lengthy time periods, however, a back-up battery is typically subject to a gradual loss of power capability, even when it is not used to power an electronic module. For example, a typical battery will experience a nominal self-discharge rate (shelf life), and may also experience loss of charge due to various types of leakage currents when connected to any type of electronic circuitry. Therefore, it is desirable to monitor the state-of-charge of a back-up battery in order to implement a timely replacement if the state-of-charge falls below a predetermined threshold level.
Various techniques can be used to anticipate the state-of-charge replacement/threshold level, such as estimation calculations or periodic test sampling. Typically, a simple estimation calculation is based primarily on the nominal self-discharge rate, or shelf life, of the battery. However, this type of calculation may not take other factors into consideration, such as temperature changes and miscellaneous current drains. For example, according to the Arrhenius rate law, chemical reaction rates rise exponentially with reagent temperature. As such, a battery self-discharge rate would be related to temperature.
Another technique involves the periodic sampling of battery voltage, but this intrusive type of testing typically causes current drains from the back-up battery, which can further shorten the life of the battery. Moreover, this technique is generally not a reliable measure of state-of-charge because battery cells typically have a flat voltage curve until nearly discharged.
Accordingly, it is desirable to provide a method of predicting a replacement threshold level for a back-up battery that is minimally intrusive, and that adjusts the predicted self-discharge rate of the back-up battery in accordance with measured temperature values. In addition, it is desirable to provide a prediction method that approximates temperature values during periods when actual temperature measurements cannot be made, such as, for example, when the electronic module is turned off. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

Apparatus and methods for estimating the state-of-charge of a power source


A multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed thereon, having a second parallel conductor array oriented orthogonal to the first parallel conductor array, the first and second parallel conductor arrays being electrically interconnected by a first through conductor array; and a second stacked structure consisting essentially of a third insulating layer having a third parallel conductor array crossing at an angle of 30 to 60 degrees to the first parallel conductor array and a fourth insulating layer formed on top of the third insulating layer, having a fourth parallel conductor array orthogonal to the third parallel conductor array, the third and fourth parallel conductor arrays being electrically interconnected by a second through conductor array, wherein the second stacked structure is overlaid on the first stacked structure by interposing therebetween an intermediate insulating layer having a conductive layer, and the first or second parallel conductor array and the third or fourth parallel conductor array are electrically interconnected by a third through conductor array.

1. Field of the Invention
The present invention relates to a multilayered wiring board for use in an electronic circuit board or the like, and more particularly to a wiring structure of a multilayered wiring board on which a high speed operating semiconductor device is mounted.
2. Description of the Related Art
Conventionally, in the fabrication of a multilayered wiring board used as an electronic circuit board or the like for mounting thereon an electronic component including a semiconductor device such as a semiconductor integrated circuit device, interconnection conductors for internal wiring are formed by depositing layers of interconnections made of a high melting point metal such as tungsten (W), with an insulating layers made of a ceramic such as alumina formed between them.
In the conventional multilayered wiring board, of the interconnection conductors signal conductors are usually formed in a stripline structure, and above and below each layer of signal conductors is formed a large-area ground layer or power supply layer of the so-called solid pattern, with an insulating layer interposed therebetween.
With increasing speed of electrical signals handled by multilayered wiring boards, it has also been practiced to fabricate high-density, high-functionality multilayered wiring boards that can accommodate the high speed operation of semiconductor devices; that is, in the fabrication of such multilayered wiring boards, an insulating layer is formed using a polyimide resin or epoxy resin having a relatively low dielectric constant of 3.5 to 5 in place of an alumina ceramic whose dielectric constant is about 10, and an internal wiring conductor layer of copper is deposited on the insulating layer by thin film technology using vapor phase deposition such as evaporation or sputtering, and then forming microscopic conductor patterns by photolithography, the process being repeated to form multiple layers alternating between insulators and conductors.
On the other hand, for internal wiring structure within a multilayered wiring board, in order to reduce the impedance of wiring and cross talk between signal conductors and to achieve high density wiring, there has been proposed a wiring structure in which an array of parallel conductors is formed on the upper surface of each insulating layer and a plurality of such layers are stacked one on top of another with designated conductors electrically interconnected between the layers using through conductors such as via hole conductors or through hole conductors.
For example, Japanese Unexamined Patent Publication JP-A 63-129655 (1988) discloses a multilayer wiring structure in which a first conductive layer, having a plurality of first signal lines extending in a first direction and first power lines formed alternately with the first signal lines, and a second conductive layer, having a plurality of second signal lines extending in a second direction orthogonal to the first direction and second power lines formed alternately with the first signal lines, are formed in alternating fashion with an insulating layer interposed therebetween, wherein first and second power lines receiving a corresponding voltage are interconnected. According to this structure, it becomes possible to increase packing density, reduce power consumption, and increase operating speed by making effective use of the chip area of the semiconductor chips mounted thereon.
Further, Japanese Unexamined Patent Publication JP-A 1-96953 (1989) discloses a wiring structure comprising a plurality of sets of wiring planes, wherein each of the sets of wiring planes includes at least first and second wiring planes, each of the wiring planes supporting conductive wiring oriented in a principal wiring direction and further supporting a plurality of connection sites arranged at intersections of orthogonal lines, the principal direction of wiring on the first wiring plane lying at an acute angle to the principal direction of wiring on the second wiring plane. According to this structure, wiring length can be reduced, optimized, or minimized using one or several sets of standardized wiring planes.
Also, Japanese Unexamined Patent Publication JP-A 5-343601 (1993) discloses a connection system for integrated circuits, wherein conductor (wiring conductors) layers comprising no more than two layers of parallel conductor patterns are formed one on top of another with the conductor patterns arranged at right angles to each other, some conductors on the conductor layers are used as signal conductors and the other conductors as power conductors, and the conductors on the conductor layers are interconnected in such a manner that the power conductors shield the signal conductors from each other. According to this system, since a conductor grid is formed in such a manner that each signal pattern is flanked by a pair of power supply patterns, the spacing between signal patterns can be reduced and the signal patterns running in parallel can be formed over an extended length, so that effective use is made of the carrier surface, cross talk is reduced, and S/N ratio is improved.
Further, Japanese Unexamined Patent Publication JP-A 7-94666 (1995) discloses an electrical interconnection medium comprising at least first and second interconnection layers, each of the interconnection layers comprising a plurality of parallel conductive regions, the conductive regions of the second interconnection layer being oriented orthogonally to the conductive regions of the first interconnection layer, the conductive regions of the first and second interconnection layers being electrically interconnected such that at least conductive planes are substantially interdigitated on each interconnection layer and each conductive plane appears on both interconnection layers, and such that selective conductive regions can be electrically isolated from the two conductive planes to form at least one signal path. According to this interconnection medium, the number of interconnect layers is reduced while retaining the low inductance power distribution characteristics of parallel power and ground planes, as well as the high wiring density for signal interconnect wires characteristic of photolithographic fabrication techniques.
Furthermore, Japanese Unexamined Patent Publication JP-A-9-18156 (1997) discloses a multilayer printed wiring board comprising a first layer having a first signal conductor section, a first power conductor section, and a plurality of first ground conductor sections, and a second layer formed on top of the first layer and having a second signal conductor section, a second power conductor section, and a plurality of second ground conductor sections connected one for one to the plurality of first ground conductor sections, wherein the first signal conductor section of the first layer and the second signal conductor section of the second layer are twisted, that is, orthogonal, with respect to each other. According to this structure, since the total number of wiring layers can be reduced, and since the combined conductance value and combined resistance value can be held low even if the wiring width of the ground conductor sections is reduced, high density placement of ICs and other devices becomes possible and noise caused to transmission signals can be held low. Furthermore, since noise due to the mismatch of the characteristic impedance of the signal conductor sections can be reduced because of the shield effect of the ground conductor and power conductor sections, and since the first signal conductor section and the second conductor section are twisted with respect to each other, it becomes possible to control the effects of the cross talk noise caused by the electromagnetic and capacitive couplings between the two signal conductor sections.
In the multilayered wiring boards having parallel conductor arrays as described above, appropriate conductors are selected from each parallel conductor array in the multilayered wiring board in order to electrically connect an electronic component such as a semiconductor device mounted on the multilayered wiring board to the mounting board on which the multilayered wiring board is mounted, and connections between conductors of different wiring layers are made using through conductors such as via hole conductors.
Since these prior art multilayered wiring boards comprise the so-called x- and y-direction wiring planes with the wiring direction of one plane being oriented orthogonal to the wiring direction of the other plane, the prior art has the problem that when interconnecting desired connection terminals via the orthogonally arranged parallel conductor arrays, the interconnection cannot be made along the shortest route and the wiring length in the multilayered wiring board becomes long. That is, the resistance, capacitance, and inductance of signal conductors become larger than would be the case if the interconnection were made along the shortest route, thus resulting in the problem that the rise time of signals which should be operated at high speed increases and noise also increases.
On the other hand, Japanese Unexamined Patent Publication JP-A 59-86248 (1984), for example, discloses a multilayered wiring board comprising a first wiring layer having an array of conductors extending in a first direction, a second wiring layer having an array of conductors extending in a direction orthogonal to the first direction, a third wiring layer having an array of conductors extending in a third direction at an oblique angle to the first direction, and a fourth wiring layer having an array of conductors extending in a direction orthogonal to the third direction, the wiring layers being formed one on top of another in superimposing fashion with each layer separated by an insulating layer. According to this structure, since the two wiring layers having conductor arrays arranged orthogonal to each other and the two wiring layers having conductor arrays arranged orthogonal to each other but at an oblique angle to the first two conductor arrays are formed one on top of another in superimposing fashion with each layer separated by an insulating layer, the wiring length between any two terminals can be reduced compared with other prior art wiring grid structure and cross talk between adjacent connection lines can also be reduced. More specifically, by adding wiring layers having conductor arrays arranged obliquely to the x and y directions, greater freedom is provided in designing wiring connections and the connection wiring length can be reduced compared with multilayered wiring boards having conductor arrays arranged only in the x and y directions.
If the conductor array of a certain wiring layer is not arranged orthogonal to, but is arranged obliquely to, the conductor array of the wiring layer lying directly above or below that certain wiring layer, like the first and second wiring layers and the third and fourth wiring layers in the multilayered wiring board disclosed in Japanese Unexamined Patent Publication JP-A 59-86248 (1984), there arises the problem that unwanted electromagnetic coupling occurs between the conductors, causing cross talk noise between the upper and lower conductors.
The present invention has been devised in view of the above-enumerated problems, and its first object is to provide a multilayered wiring board that permits terminals to be connected efficiently over a distance close to the shortest distance using alternately stacked parallel conductor arrays and without compromising the freedom of wiring arrangement and, at the same time, can reduce cross talk noise between conductors, and that is advantageous for use as an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed.
In a multilayered wiring board for mounting thereon a semiconductor device, such as described above, and a semiconductor package using such a wiring board, it is practiced to connect a plurality of capacitors, for example, chip capacitors between the power conductors and the semiconductor device in order to reduce noise from the ground conductors or power conductors connected to the semiconductor device.
These capacitors are usually disposed near the semiconductor device, providing the shortest electrical connections to the power supply terminals of the semiconductor device to minimize the inductance and resistance due to the wiring between the capacitors and the semiconductor device, thus making maximum use of their noise suppression ability. The reason for this is that when a capacitor is interposed between a semiconductor device and a power supply conductor, since the charge is first stored on the capacitor and then supplied to the semiconductor device, noise from the power conductor is buffered and suppressed, ensuring stable power supply; if the distance from the capacitor to the semiconductor device increased, the inductance and capacitance would increase correspondingly, making the semiconductor device more susceptible to noise.
However, in the prior art multilayered wiring boards using parallel conductor arrays as described above, since the wiring direction of the parallel conductor array in each wiring layer is oriented only in the x or y direction, there arises the problem that when an array of parallel conductors extending only in the x or y direction is formed in the first wiring layer lying directly below the surface on which a semiconductor device is mounted, the position where a capacitor can be placed to achieve the shortest connection to the semiconductor device is limited to an area lying in a sideway direction (x direction) or in a crosswise direction (y direction) with respect to the semiconductor device.
That is, if the capacitors are placed in the four directions around the semiconductor device, of these capacitors the capacitors placed in the two directions coinciding with the oriented direction of the parallel conductor array of the first layer lying directly below the surface can achieve the shortest connection to the semiconductor device through the parallel conductor array, but for the other two directions, since the connection cannot be provided through the parallel conductor array of the first layer, the connection has to be made first to the parallel conductor array of the second layer underneath, and then to the semiconductor device via the parallel conductor array of the first layer. As a result, the inductance and resistance of the wiring between these latter capacitors and the semiconductor device increase by an amount equivalent to the parallel conductor arrays of the first and second layers and through conductors interconnecting them, the resulting problem being that, compared with the capacitors placed in the two directions providing the shortest connection via the parallel conductor array of the first layer, the effects of noise on the power supply conductors increase, making stable power supply difficult.
The present invention has been devised in view of the above-enumerated problems, and its second object is to provide a multilayered wiring board that is advantageous for use as a semiconductor package or an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed, and that is structured so that the capacitors arranged around the semiconductor device to ensure stable power supply can be placed in areas lying in the four directions around the semiconductor device where noise can be effectively suppressed, thus suppressing the effects of noise while permitting high density placement of the capacitor and achieving a reduction in the size of the board.
In the multilayered wiring boards having parallel conductor arrays as described above, as the operating speeds of electronic components such as semiconductor devices mounted thereon increase, EMI (electromagnetic interference) noise is becoming an important concern. EMI noise is produced when unwanted electromagnetic waves are emitted from electronic equipment and pass into electronic circuits within the electronic equipment or other electronic equipment located nearby, causing interference to the equipment by inducing noise in its electronic circuits. EMI noise may cause the affected equipment to malfunction.
Countermeasures for this EMI noise can be considered at the following three levels. First, the countermeasure at the system level of electronic equipment is to block the emission of electromagnetic waves, for example, by coating the inside of the housing of the equipment with an electromagnetic absorber. Second, the countermeasure at the electronic circuit board level is to use EMI suppression components such as EMI filters and capacitors in the electronic circuit.
Third, the countermeasure at the package level of electronic devices or semiconductor devices is to provide shielding by covering the internal wiring layers with large-area (so-called solid pattern) ground conductor layers.
However, in the prior art multilayered wiring boards as described above, the deficiency of the prior art is that the EMI countermeasure at the package level is not provided because no large-area ground conductor layers are included. Accordingly, there arises the problem that unwanted electromagnetic wave from other electronic equipment causes interference, causing the semiconductor device, etc. to malfunction, or unwanted electromagnetic wave is radiated from internal conductors, causing an ill effect on electronic equipment located nearby.
The present invention has been devised in view of the above-enumerated problems, and its third object is to provide a multilayered wiring board that has a wiring structure comprising orthogonally oriented parallel conductor arrays in multiple layers and capable of reducing cross talk noise between the conductors, that provides means for suppressing the effects of EMI without degrading its electrical characteristics, and that is advantageous for use as an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed.
Especially, in recent years, the operating frequencies of semiconductor integrated circuits represented by MPUs (microprocessing units) have been increasing, and semiconductor devices operating at several GHz are being realized. On the other hand, with increasing operating frequency and packing density of semiconductor devices, increasing EMI noise is becoming a matter of concern. This is because, in a digital device such as an MPU, a signal having a rise speed of several GHz contains harmonic components of frequencies several to ten-odd times the fundamental frequency, and one major cause of EMI noise is the emission of these harmonic components radiated as electromagnetic waves.
One possible measure to prevent the emission of such harmonic components is to provide shielding by completely covering the upper and lower surfaces of wiring layers with a large-area solid pattern ground conductor layer.
However, in the prior art multilayered wiring boards composed of stacked parallel conductor arrays as described above, the deficiency of the prior art is that the EMI countermeasure at the package level is not provided because no large-area ground conductor layers are included. Accordingly, there arises the problem that unwanted electromagnetic wave from other electronic equipment causes interference, causing the semiconductor device, etc. to malfunction, or unwanted electromagnetic wave is radiated from internal conductors, causing an ill effect on electronic equipment located nearby.
When a large-area ground conductor layer is formed above and below parallel conductor array as a countermeasure for EMI noise, since signal conductors disposed opposite the ground conductor layer across an insulating layer have capacitances with respect to the ground conductor layer, there arises the problem that the impedance of the signal conductors arranged by considering the impedance matching (for example, 50 xcexa9) between the signal conductors becomes lower than the intended value, causing an impedance mismatch between the signal conductors disposed opposite the ground conductor layer and the signal conductors of other wiring layers; this could cause noise or transmission loss of high frequency signals, or could result in malfunctioning of an electronic component such as a semiconductor device mounted on the wiring board.
The present invention has been devised in view of the above-enumerated problems, and its fourth object is to provide a multilayered wiring board which is capable of reducing cross talk noise between conductors in alternately stacked parallel conductor arrays, and advantageous for use as a semiconductor package or an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed, in which multilayered wiring board countermeasure against EMI noise is taken without degrading the electrical characteristics, and impedance matching of signal wiring is carried out in order to improve the transmission characteristics of high-frequency signals.
In recent years, with increasing operating speed and packing density of semiconductor devices, among others, semiconductor integrated circuits such as MPUs (microprocessing units), pin count (the number of input/output electrodes) has been increasing, and devices having operating speeds in the GHz band and, in terms of pin count (the number of input/output electrodes), 2000 or more pins are becoming available.
For such semiconductor devices, the prior art multilayered wiring boards having wiring layers of the stripline structure have the problems that since higher pin count means increased number of signals, the number of stacked layers increases because of the increase in the number of deployment layers required to accommodate the increased number of signals using signal conductors and, as a result, the thickness and size of the multilayered wiring board increase, and additionally that cross talk noise between signal wirings is increased with increasing operating frequency and wiring density.
On the other hand, according to the multilayered wiring boards having parallel conductor arrays as described above, by forming signal conductors and power or ground conductors within the same wiring layer, not only can the increase in the number of layers, resulting from increased pin count, be reduced, but cross talk between signal conductors can also be reduced.
However, as the number of input/output electrodes of semiconductor devices increases, electrode spacing decreases to 200 xcexcm or further to 150 xcexcm or less, and the spacing between conductors in parallel conductor arrays also decreases; furthermore, since there are a variety of design schemes for the placement of the input/output electrodes of semiconductor devices, it is becoming extremely difficult to electrically connect such input/output electrodes to the parallel conductor arrays in the prior art multilayered wiring boards having parallel conductor arrays, the problem being that it is difficult to provide good connections to semiconductor devices while making effective use of their excellent electrical characteristics.
The invention has been devised in view of the above-enumerated problems, and its fifth object is to provide a multilayered wiring board having alternately stacked parallel conductor arrays, and more particularly, a multilayered wiring board that permits efficient electrical connections to be made to a semiconductor device having high density input/output terminals while making effective use of its electrical characteristics, and yet permits reductions in the number of stacked layers, the multilayered wiring board thus being advantageous for use as an electronic circuit board or the like for mounting thereon a semiconductor device or the like.
In order to achieve the first object, the invention provides a multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed on top of the first insulating layer, having a second parallel conductor array oriented orthogonal to the first parallel conductor array, the first and second parallel conductor arrays being electrically interconnected by a first through conductor array; and a second stacked structure essentially consisting of a third insulating layer having a third parallel conductor array and a fourth insulating layer formed on top of the third insulating layer, having a fourth parallel conductor array oriented orthogonal to the third parallel conductor array, the third and fourth parallel conductor arrays being electrically interconnected by a second through conductor array, wherein the second stacked structure is overlaid on the first stacked structure by interposing therebetween an intermediate insulating layer having a conductive layer disposed opposite at least the first and second parallel conductor arrays, in such a manner that the third parallel conductor array is oriented at 30 to 60 degrees with respect to the first parallel conductor array, and the first or second parallel conductor array and the third or fourth parallel conductor array are electrically interconnected by a third through conductor array formed passing through the conductive layer.
In the invention it is preferable that each of the first to fourth parallel conductor arrays includes a plurality of signal conductors and a plurality of power conductors or ground conductors disposed adjacent to the signal conductors in alternating fashion.
The invention provides a multilayered wiring board comprising:
(a) a first stacked structure D1 including
(a1) a first insulating layer I1 on one surface of which is formed a first parallel conductor array L1,
(a2) a second insulating layer I2 on one surface of which is formed a second parallel conductor array L2 oriented orthogonal to the first parallel conductor array L1,
xe2x80x83the second insulating layer I2 being stacked on another surface of the first insulating layer I1, and
(a3) a first through conductor array T1 for electrically interconnecting the first and second parallel conductor arrays L1 and L2, the first through conductor array T1 passing through the first insulating layer I1 at positions where the first and second parallel conductor arrays L1 and L2 intersect;
(b) a second stacked structure D2 including
(b1) a third insulating layer I3 on one surface of which is formed a third parallel conductor array L3,
xe2x80x83a direction 1 in which the third parallel conductor array L3 is oriented being inclined at an angle xcex81, xcex82 of 30 to 60 degrees with respect to a direction 3 in which the first parallel conductor array L1 is oriented,
(b2) a fourth insulating layer I4 on one surface of which is formed a fourth parallel conductor array L4 oriented orthogonal to the third parallel conductor array L3, the fourth insulating layer I4 being stacked on another surface of the third insulating layer I3, and
(b3) a second through conductor array T2 for electrically interconnecting the third and fourth parallel conductor arrays L3 and L4, the second through conductor array T2 passing through the third insulating layer I3 at positions where the third and fourth parallel conductor arrays L3 and L4 intersect;
(c) an intermediate insulating layer I5 interposed between another surface of the second insulating layer I2 in the first stacked structure D1 and the one surface of the third insulating layer I3 in the second stacked structure D2, the intermediate insulating layer I5 having a conductive layer L5 formed on one surface thereof which one surface faces the other surface of the second insulating layer I2; and
(d) a third through conductor array T3 for electrically interconnecting the second and third parallel conductor arrays L2 and L3, the third through conductor array T3 passing through the intermediate insulating layer I5 at positions where the second and third parallel conductor arrays L2 and L3 intersect.
In the invention it is preferable that the multilayered wiring board further comprises a fourth through conductor array T4 for electrically interconnecting the first and third parallel conductor arrays L1 and L3, the fourth through conductor array T4 passing through the second insulating layer I2 and the intermediate insulating layer I5 at positions where the first and third parallel conductor arrays L1 and L3 intersect and where neither the first parallel conductor array L1 nor the third parallel conductor array L3 intersects the second parallel conductor array L2.
In the invention it is preferable that the multilayered wiring board further comprises a fifth through conductor array T5 for electrically interconnecting the first and fourth parallel conductor arrays L1 and L4, the fifth through conductor array T5 passing through the second insulating layer I2, the intermediate insulating layer I5, and the third insulating layer I3 at positions where the first and fourth parallel conductor arrays L1 and L4 intersect and where the first parallel conductor array L1 and the fourth parallel conductor array L4 intersect neither the second parallel conductor array L2 nor the third parallel conductor array L3.
In the invention it is preferable that each of the first to fourth parallel conductor arrays includes a plurality of signal conductors and a plurality of power conductors or ground conductors disposed adjacent to the signal conductors in alternating fashion.
According to the multilayered wiring board of the invention, since the first parallel conductor array and the second parallel conductor array in the first stacked structure and the third parallel conductor array and the fourth parallel conductor array in the second stacked structure are oriented orthogonal to each other in the respective stacked structures, cross talk noise between the conductors in the respective stacked structures can be reduced to a minimum. Further, since the third and fourth parallel conductor arrays in the second stacked structure are oriented obliquely at an angle of 30 to 60 degrees with respect to the first and second parallel conductor arrays in the first stacked structure, terminals from the first parallel conductor array in the first stacked structure to the fourth parallel conductor array in the second stacked structure can be interconnected over a distance close to the shortest distance without compromising the freedom of wiring arrangement between the terminals; as a result, compared with the prior art multilayered wiring boards comprising parallel conductor arrays only oriented orthogonal to each other, the interconnection wiring length can be shortened and the resistance, capacitance, and inductance of the wiring interconnecting the terminals from the first stacked structure to the second stacked structure can thus be reduced. Furthermore, because of the conductive layer formed by interposing the intermediate insulating layer between the first and second stacked structures, unwanted electromagnetic coupling not only between the second parallel conductor array and the third parallel conductor array but also between the first and second parallel conductor arrays and the third and fourth parallel conductor arrays can be blocked using the conductive layer, and cross talk noise between the first stacked structure and the second stacked structure can be virtually eliminated. Thus, according to the multilayered wiring board of the invention, electronic components such as semiconductor devices operating at high speed can be operated accurately and stably without malfunctioning.
As described above, according to the present invention, a multilayered wiring board can be provided that permits terminals to be connected efficiently over a distance close to the shortest distance using alternately stacked parallel conductor arrays and without compromising the freedom of wiring arrangement and, at the same time, can reduce cross talk noise between conductors, and that is advantageous for use as an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed.
In order to achieve the second object, the invention provides a multilayered wiring board comprising:
a stack composed of a plurality of insulating layers I11 to I14 and a plurality of wiring layers L11 to L14,
the plurality of insulating layers I11 to I14 and the plurality of wiring layers L11 to L14 being stacked on top of each other in alternating fashion;
a semiconductor device D mounted on a center region of a surface 11 of the stack; and
capacitors placed around the semiconductor device,
the capacitors being electrically connected to the semiconductor device via the wiring layer L11 which is disposed directly below the surface 11,
wherein in four quadrant regions 12 to 15 of each of the insulating layers with the semiconductor device as a center thereof, a first wiring layer which is the wiring layer L11 disposed directly below the surface 11 includes parallel conductor arrays each directed toward the center 16,
a second wiring layer which is the wiring layer L12 successive to the wiring layer disposed includes parallel conductor arrays oriented orthogonal to the respective parallel conductor arrays of the first wiring layer L11, and is electrically connected to the first wiring layer L11 via a through conductor array T12, and
the capacitors are placed above the parallel conductor arrays of the first wiring layer L11 which are opposite to the semiconductor device.
In the invention it is preferable that each of the parallel conductor arrays of the first and second wiring layers L11 and L12 includes a plurality of signal conductors and a plurality of power conductors or ground conductors disposed adjacent to the signal conductors in alternating fashion.
In the invention it is preferable that the insulating layers I11 to I14 are of a same rectangular planar shape, that the quadrant regions 12 to 15 are separated from one another by two straight lines 17 and 18 drawn along diagonals of each of the insulating layers I11 to I14 and that the capacitors C are placed in areas 35 and 36 each extending so as to have a width in a direction of one of two mutually orthogonal sides 27 and 28 and to be parallel to the other of the two sides 27 and 28.
In the invention it is preferable that the insulating layers I21 to I23 are of a same rectangular planar shape, that the quadrant regions 12 to 15 are separated from one another by straight lines 19 and 20 each extending so as to cross one of two mutually perpendicular sides 27 and 28 of each of the insulating layers I21 to I23 and to be parallel to the other of the two sides 27 and 28, and that the capacitors C are placed in areas 25 and 26 along the two diagonals of each of the insulating layers I21 to I23.
According to the multilayered wiring board of the invention, the first wiring layer lying directly below the surface for electrically connecting the semiconductor device mounted on the surface to the capacitors arranged around it is formed from parallel conductor arrays directed toward the center, each parallel conductor array arranged in one of four quadrant regions centered around the semiconductor device, each quadrant region being one of the four regions into which the plane of the wiring layer is divided by two straight lines intersecting at right angles on that plane at a point corresponding to the center of the semiconductor device, and the capacitors are placed above the parallel conductors leading to the semiconductor device, that is, the conductors lying in areas extending from the semiconductor device in directions parallel to the parallel conductor arrays; accordingly, the capacitor placement areas where the capacitors can be connected to the semiconductor device over the shortest distance can be provided in the four directions around the semiconductor device.
Further, since the second wiring layer lying directly below the parallel conductor arrays of the first wiring layer is formed from parallel conductor arrays oriented orthogonal to the parallel conductor arrays of the second wiring layer in the respective quadrant regions, cross talk noise between the upper and lower wiring layers can be reduced and the capacitors"" function of ensuring stable power supply can be further enhanced.
As a result, according to the multilayered wiring board of the invention, the capacitor placement areas where noise can be effectively suppressed can be provided in the four directions around the semiconductor device, and high density placement of the capacitors and a reduction in the size of the board can be achieved while suppressing the effects of noise.
As a result, according to the present invention, a multilayered wiring board can be provided that is advantageous for use as a semiconductor package or an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed, and that permits high density placement of the capacitors and achieves a reduction in the size of the board, while effectively suppressing the effects of noise.
In order to achieve the third object, the invention provides a multilayered wiring board comprising a stacked wiring structure including
a first insulating layer I31,
a first wiring layer L31 formed in the first insulating layer I31,
the first wiring layer L31 comprising parallel conductor arrays each directed toward a point of intersection of two to four straight lines by which the first insulating layer is divided into regions each of which has an approximately equal interior angle, which point of intersection is in a center portion of the first insulating layer;
a second insulating layer I32 stacked on the first insulating layer I31,
a second wiring layer L32 formed in the second insulating layer and comprising parallel conductor arrays which are orthogonal to the parallel conductor arrays of the first wiring layer in the regions, and
a through conductor array T13, passing through the first insulating layer I31, for electrically interconnecting the first and second wiring layers L31 and L32.
In the invention it is preferable that the second wiring layer has an encircling wiring structure in which the conductors of the parallel conductor arrays in the respective regions are connected together.
In the invention it is preferable that each of the parallel conductor arrays of the first and second wiring layers includes a plurality of signal conductors and power conductors or ground conductors disposed adjacent to the signal conductors.
Furthermore, in the invention it is preferable that an outermost encircling conductor of the encircling wiring structure of the second wiring layer is a ground conductor.
According to the multilayered wiring board of the invention, in the construction of the multilayer wiring structure comprising orthogonally oriented parallel conductor arrays in multiple layers, split regions are set by splitting the insulating layer plane by two to four straight lines intersecting at the center of the insulating layer so that each region has an approximately equal interior angle, the first wiring layer is formed from parallel conductor arrays oriented substantially parallel to directions directed toward the point of intersection, i.e., the center of the insulating layer, each parallel conductor array being arranged in one of the split regions, the second wiring layer is formed from parallel conductor arrays oriented substantially parallel to directions orthogonal to the parallel conductor arrays of the first wiring layer in the respective split regions, and the first and second wiring layers are electrically interconnected by a through conductor array; as a result, the power conductors and the ground conductors of the parallel conductor arrays forming the second wiring layer are arranged in a substantially encircling wiring configuration encircling the center portion of the insulating layer, and by optimizing these power conductors and ground conductors this structure has the effect of providing shielding to block the infiltration of external EMI noise as well as the emission of unwanted electromagnetic wave to the outside, thus providing an effective countermeasure against EMI while reducing cross talk noise between the conductors.
Furthermore, since the split regions are set by splitting the insulating layer plane by two to four straight lines intersecting at the center of the insulating layer so that each region has an approximately equal interior angle, the freedom of wiring arrangement can be enhanced and the wiring length reduced, reducing the resistance, inductance, and capacitance.
Furthermore, when each of the parallel conductor arrays of the first and second wiring layers is formed to include a plurality of signal conductors and a plurality of power conductors or ground conductors disposed adjacent to the signal conductors in alternating fashion, cross talk noise can be effectively reduced by electromagnetically shielding the signal conductors lying on the same plane, and the inductance of the power conductors and ground conductors can be reduced, effectively reducing power supply noise as well as ground noise.
When the second wiring layer is formed in an encircling wiring structure by interconnecting its parallel conductor arrays in the respective regions, by optimizing the power conductors and the ground conductors in the parallel conductor arrays, this encircling wiring structure serves to enhance the effectiveness of the EMI countermeasure, and thus provides more effective means for suppressing the effects of EMI.
Further, when the outermost conductor of the encircling wiring structure of the second wiring layer is a ground conductor, this encircling ground conductor provides very effective shielding means against EMI noise, and contributes to further enhancing the effectiveness of the EMI countermeasure.
Thus, according to the multilayered wiring board of the invention, the wiring structure comprises orthogonally oriented parallel conductor arrays in multiple layers and capable of reducing cross talk noise between the conductors, and the second wiring layer is structured to provide shielding against EMI noise to implement means for suppressing the effects of EMI without degrading its electrical characteristics, so that the electronic component such as a semiconductor device operating at high speed can be operated accurately and stably without malfunctioning.
As described above, according to the present invention, a multilayered wiring board can be provided that has a wiring structure comprising orthogonally oriented parallel conductor arrays in multiple layers and capable of reducing cross talk noise between the conductors, that provides means for suppressing the effects of EMI without degrading its electrical characteristics, and that is advantageous for use as an electronic circuit board or the like for mounting thereon an electronic component such as a semiconductor device operating at high speed.
In order to achieve the fourth object, the invention provides a multilayered wiring board comprising a stacked wiring structure including a first insulating layer having a first parallel conductor array including signal conductors, and a second insulating layer having a second parallel conductor array including signal conductors, the second insulating layer being stacked on the first insulating layer, the second parallel conductor array being oriented orthogonal to the first parallel conductor array, and a through conductor array for electrically interconnecting the first and second parallel conductor arrays; and a ground conductor layer with openings each of which is opposed to the signal conductors and has a width of 500 xcexcm or less, disposed on or under the stacked wiring structure.
The invention provides a multilayered wiring board comprising:
(a) a stacked wiring structure including
(a1) a first insulating layer I72 on one surface of which is formed a first parallel conductor array L71 including a first signal conductor S71 for carrying an electrical signal,
(a2) a second insulating layer I73 on one surface of which is formed a second parallel conductor array L72 which is oriented orthogonal to the first parallel conductor array L71 and includes a second signal conductor S72 for carrying an electrical signal, the second insulating layer I73 being stacked on another surface of the first insulating layer I72, and
(a3) a through conductor array T71 for electrically interconnecting the first and second parallel conductor arrays L71 and L72, the through conductor array T71 passing through the first insulating layer I72 at positions where the first and second parallel conductor arrays L71 and L72 intersect; and
(b) a ground conductor layer GL formed on another surface of the second insulating layer I73 and having an opening A which is opposed to the second signal conductor S72 and has a width of 500 xcexcm or less.
The invention provides a multilayered wiring board as shown in FIG. 14. In an embodiment in FIG. 14, the respective parts corresponding to those in FIG. 12 are denoted by the same reference characters as those in FIG. 12 for the purpose of providing a clear understanding. The multilayered wiring board of the invention comprises:
(a) a stacked wiring structure including
(a1) a first insulating layer I73 on one surface of which is formed a first parallel conductor array L73 including a first signal conductor S73 for carrying an electrical signal,
(a2) a second including layer I71 on one surface of which is formed a second parallel conductor array L71 which is oriented orthogonal to the first parallel conductor array L73 and includes a second signal conductor S71 for carrying an electrical signal, the second insulating layer I71 being stacked on another surface of the first insulating layer I73, and
(a3) a through conductor array T74 for electrically interconnecting the first and second parallel conductor arrays L73 and L71, the through conductor array T74 passing through the first insulating layer I71 at positions where the first and second parallel conductor arrays L73 and L71 intersect;
(b) a third insulating layer I74 one surface of which is overlaid on the one surface of the first insulating layer I73; and
(c) a ground conductor layer GL formed on another surface of the third insulating layer I74 and having an opening A which is opposed to the first signal conductor S73 and has a width of 500 xcexcm or less.
In the invention it is preferable that the opening A has an area equal to or more than 50% of an area of the signal conductor S72, S73 formed to be opposed to the opening A.
In the invention it is preferable that each of the first and second parallel conductor arrays L71, L72 and L73 includes a plurality of signal conductors S71, S72 and S73 and power conductors P71, P72 and P73 or ground conductors G71, G72 and G73 disposed adjacent to the signal conductors S71, S72 and S73 in alternating fashion.
According to the multilayered wiring board of the invention, since the stacked wiring structure constructed by interconnecting the orthogonally oriented parallel conductor arrays by a through conductor array, each parallel conductor array having a signal conductors, is provided on its upper or lower surface with a large-area ground conductor layer having openings arranged to be opposed to the signal conductors, an excess capacitive components hardly occurs between the signal conductors and the ground conductor layer. Accordingly impedance mismatching caused by adverse effect of the ground conductor layer thereon never occurs to the signal conductors, and the signal conductors will be in the state of impedance matching owing to electromagnetic connection with the adjacent conductors. Further, since each opening formed in the ground conductor layer is 500 xcexcm or less in width, the frequency of a high-frequency signal which passes through the opening can be sufficiently shifted to the high-frequency side, and there is no possibility of EMI noise entering or radiating through the opening, with the result that the ground conductor layer can be used as a shield layer having a sufficient shielding effect against EMI noise.
Further, when each opening is formed to have an area not smaller than 50% of the area of the signal conductor formed opposite the opening, though the capacitance of the signal conductor becomes correspondingly higher than would be the case if the opening area were made equal to 100% of the signal conductor area, its influence can be suppressed below a level that can cause a practical problem; therefore, if a capacitive component occurs on the signal conductor, the resulting impedance mismatching can be held within tolerable limits so as not to cause a detrimental effect to the transmission characteristics of a high frequency signal and, at the same time, the EMI noise shielding effect of the ground conductor layer can be further enhanced.
Further, each opening formed in the ground conductor layer is made to have an area not smaller than 50% of the area of the signal conductor formed opposite the opening, whereby the impedance matching of the signal conductors can be enhanced, while enhancing transmission characteristics of a high-frequency signal, and at the same time the EMI noise shielding effect of the ground conductor layer can be further enhanced.
Furthermore, when each of the first and second parallel conductor arrays is formed to include a plurality of signal conductors and a plurality of power conductors or ground conductors disposed adjacent to the signal conductors in alternating fashion, cross talk noise between adjacent signal conductors on the same plane can be effectively reduced by electromagnetically shielding the signal conductors on the same insulating layer, and power supply noise and ground noise can also be reduced effectively.
As described above, according to the present invention, in the multilayered wiring board, the alternatively stacked parallel conductor arrays can reduce cross talk noise between conductors, and the ground conductor layer having a prescribed opening can improve the transmission characteristics of high-frequency signals as well as providing countermeasure against EMI noise, with the result that electronic components such as semiconductor devices can be allowed to operate at high speed accurately and stably without malfunctioning. Thus, the multilayered wiring board of the invention is advantageous for use in a semiconductor package or electronic circuit board or the like.
In order to achieve the fifth object, the invention provides a multilayered wiring board comprising:
a plurality of insulating layers I82 to I84 and a plurality of wiring layers C82 and C83 stacked sequentially in alternating fashion;
a stripline section 71 disposed below a mounting region M of the semiconductor device D provided in a center portion of a surface 78, the stripline section 71 comprising an upper conductor layer C81, a line conductor layer C82 formed from a plurality of line conductors to which terminals of the semiconductor device are connected via a first through conductor array T81, and a lower conductor layer C83; and
a parallel conductor section 79 constructed by electrically interconnecting, through a second through conductor array T82,
a first wiring layer L81 formed in the same plane as the line conductor layer C82 in such a manner as to encircle the stripline section 71, and divided into split regions 74 to 77 by two to four straight lines 72, 73 intersecting at a point 16 within the mounting region M so that each split region has an approximately equal interior angle xcex811, xcex812, each split region containing a first parallel conductor array directed toward the point of intersection 16, and
a second wiring layer L82 formed in the same plane as the lower conductor layer C83, and comprising second parallel conductor arrays oriented orthogonal to the first wiring layer in the respective split regions,
wherein the semiconductor device is electrically connected to the first wiring layer L81 via the line conductor layer C82.
In the invention it is preferable that each of the parallel conductor arrays of the first and second wiring layers includes a plurality of signal conductors and a plurality of power conductors or ground conductors disposed adjacent to the signal conductors in alternating fashion.
The invention provides a wiring board comprising:
(a) a first insulating layer I81, I82 having a mounting region M for mounting a semiconductor device D formed substantially centrally on a surface 78 thereof;
(b) an upper conductor layer C81 formed on the other surface of the first insulating layer I81, I82 and underneath the mounting region M;
(c) a second insulating layer I82 formed to have a surface facing the other surface of the first insulating layer I81, I82 and the upper conductor layer C81;
(d) a line conductor layer C82 comprising a plurality of line conductors, the line conductor layer C82 being formed on the other surface of the second insulating layer I83 and underneath the mounting region M;
(e) a first through conductor array T81, passing through the first and second insulating layers I81, I82 and I83, for electrically connecting the semiconductor device D to the line conductors of the line conductor layer C82;
(f) a third insulating layer I84 formed to have one surface facing the other surface of the second insulating layer I83 and the line conductor layer C82;
(g) a lower conductor layer C83 formed on the other surface of the third insulating layer I84 and underneath the mounting region M, the lower conductor layer C83 forming a stripline section 71 together with the upper conductor layer C81 and the line conductor layer C82;
(h) a first wiring layer L81 interposed between the other surface of the first insulating layer I83 and the one surface of the third insulating layer I84,
the first wiring layer L81 having a plurality of first parallel conductor arrays,
each of the first parallel conductor arrays being formed in one of a plurality of split regions 74 to 77 formed around the stripline section 71,
the split regions 74 to 77 being separated by two to four straight lines 72, 73; 17, 18; 19, 20; 41 to 43; 53 to 56 intersecting at a point 16 within the mounting region so that interior angles xcex811, xcex812; xcex81, xcex82; xcex83; xcex84; xcex85 to xcex87; xcex881 to xcex884 are approximately equal, and
each of the first parallel conductor arrays being oriented in a direction parallel to a direction directed toward the point of intersection 16;
(i) a second wiring layer L82 formed on the other surface of the third insulating layer I84,
the second wiring layer L82 having a plurality of second parallel conductor arrays,
each of the second parallel conductor arrays being formed in one of the split regions 74 to 77, and
the second parallel conductor arrays being oriented orthogonal to the first parallel conductor arrays in the respective split regions 74 to 77; and
(j) a second through conductor array T82, passing through the third insulating layer I84, for electrically interconnecting the first and second wiring layers L81 and L82,
the second through conductor array T82 forming a parallel conductor section 79, together with the first and second wiring layers L81 and L82.
In the invention it is preferable that a ground or power conductor layer GL1 is embedded in the first and second insulating layers I81 and I82 over a range from the stripline section 71 to the parallel conductor section 79, and the ground or power conductor layer GL1 is electrically connected to at least either the upper conductor layer C81 or the lower conductor layer C83.
In the invention it is preferable that pitches W3 and W4 of the first and second parallel conductor arrays are each chosen to be greater than the pitch W2 of the line conductors of the line conductor layer C82 (W3 greater than W2 and W4 greater than W2).
Further, in the invention it is preferable that one or more devices are selected as the semiconductor device D from the group consisting of a microprocessing unit, an application specific integrated circuit, and a digital signal processor.
In the invention it is preferable that the insulating layers are formed of one or more materials selected from the group consisting of inorganic insulating material, organic insulating material, and composite insulating material made up of a mixture of inorganic insulating material and organic insulating material.
According to the multilayered wiring board of the invention, the stripline section having the line conductor layer to which the input/output terminals of the semiconductor device are connected via the first through conductor array is formed inside the multilayered wiring board directly beneath the semiconductor mounting region, and the parallel conductor section electrically connected to the line conductor layer and comprising parallel conductor arrays, one in each of approximately equal four to eight split regions separated by two to four straight lines intersecting within the mounting region, is formed encircling the stripline section, thereby electrically connecting the mounted semiconductor device to the first wiring layer of the parallel conductor section via the line conductor layer; accordingly, since the narrow wiring pitch (conductor spacing) of the line conductors connected to the input/output electrodes of the semiconductor device arranged at a very high density can be spread out in the stripline section 71, and the signal conductors, power conductors, and ground conductors are rearranged and expanded to wider pitches for connection to the parallel conductor section, the semiconductor device having high-density input/output electrodes can be electrically connected efficiently, while making effective use of the excellent electrical characteristics of the parallel conductor section. Furthermore, by using the stripline section, or by stacking a plurality of such stripline sections one on top of another, the signal conductors, power conductors, and ground conductors leading from the semiconductor device can be efficiently rearranged and expanded into optimum wiring arrangement for connection to the encircling parallel conductor section. Accordingly, when the number of layers has to be increased to accommodate a higher density semiconductor device, the number of stacked layers can be reduced by optimizing the wiring design.
Furthermore the invention provides a package for housing a semiconductor device comprising the above-mentioned multilayered wiring board.


A method of imparting oil repellency to flexible, fibrous, nonwoven substrates comprising contacting the substrate with an amphoteric fluorochemical copolymer composition prepared from polymerization of monomers in the following percentages by weight: (a) from about 60% to about 90% of a fluorinated (meth)acrylate monomer of Formula 1 which is Rf-Q-CO—CR═CH2, (b) from about 10% to about 25% of an amine substituted (meth)acrylate or (meth)acylamide monomer of Formula 2 which is CH2═C(R)COZ(CH2)q(CHR)rNR2R3, and (c) from about 1% to about 15% of a substituted (meth)acrylic acid monomer of Formula 3 which is CH2=CR(R5)e—COOH.

Perfluoroalkyl-substituted compounds are used to impart oil and grease repellency to textile and paper substrates. A stain or leak proof barrier is especially desirable for paper used in many food-packaging applications.
Most commercially available fluorinated polymers useful as treating agents for imparting repellency to substrates contain predominately eight or more carbons in the perfluoroalkyl chain to provide the desired repellency properties. Honda et al., in Macromolecules, 2005, 38, 5699-5705 show that for perfluoroalkyl chains of 8 carbons or greater, orientation of the perfluoroalkyl groups is maintained in a parallel configuration, while reorientation occurs for such chains having 6 carbon atoms or less. Such reorientation decreases surface properties such as receding contact angle. Thus, shorter chain perfluoroalkyls have traditionally not been successful commercially.
Raynolds in U.S. Pat. No. 4,147,851 disclosed imparting oil and water repellency to fabric and paper by treatment with copolymers comprising (i) units derived from a perfluoroaliphatic acrylate or methacrylate monomer, and (ii) units derived from a dialkylaminoalkyl acrylate or methacrylate, or the corresponding acrylamide or methacrylamide monomer in its amine salt, quaternary ammonium or amine oxide form.
Fitzgerald et al., in U.S. Pat. No. 5,919,527, described another copolymer for treating hard surfaces comprising (i) units derived from a perfluoroalkylalkyl acrylate or methacrylate, monomers, and (ii) units derived from a dialkylaminoalkyl acrylate or methacrylate, or the corresponding acrylamide or methacrylamide monomer in its amine salt, quaternary ammonium or amine oxide form. Optionally, units derived from additional monomers were included selected from the monomer group consisting of glycidyl(meth)acrylate, blocked isocyanatoalkyl(meth)acrylate, acrylamide, vinylidene chloride, (meth)acrylic acid, sulfatoalkyl(meth)acrylate, polyoxyethylene (meth)acrylate, styrene and vinyl toluene. The above copolymers were used to provide oil, water, and stain repellency to hard surface materials used primarily for building or construction purposes such as brick, stone, concrete, tile, glass, plaster, and similar materials. There is no disclosure that such compositions are suitable for use on paper.
It is desirable to improve the method of providing oil and water repellency to paper through use of fluorochemical copolymers which do not require the use of monomers which may create difficult to remove residual toxic by-products. It is also desirable to provide copolymers useful in providing oil repellency and grease repellency to paper having perfluorinated chains of eight carbon atoms or less, thus using lower amounts of expensive fluorine, without adversely affecting the repellency performance. The present invention provides such a copolymer, a process for its preparation, and a method of treating paper for repellency.


A floral lighting fixture for attachment to a wall and for decoratively lighting and displaying a floral arrangement, the floral lighting fixture including a light rack and a wall mount for mounting on the wall, the light rack including two extended arms, the two extended arms being joined to one another at approximately the midpoints thereof, each of the two extended arms having a plurality of light sources provided thereon, and each of the two extended arms having a bendable joint provided along its length.

1. Field of the Invention
The present invention relates to the field of floral lighting fixtures, such as are used for illuminating and displaying a floral arrangement.
2. Description of the Related Art
U.S. Pat. No. 5,057,981 relates to a decorative lighted configuration that includes a flexible conduit frame having a light source, for example, one or more strings of lights, disposed therein.
U.S. Pat. No. 3,711,696 discloses a decorative night light having a plurality of simulated flowers mounted around a light bulb.
U.S. Pat. No. 4,852,832 relates to a decorative light holder for displaying ornate lights along straight and curvilinear paths and having adhesive thereon for adhering the light holder to window frames, door frames, etc.
U.S. Pat. No. 4,855,882 discloses an apparatus for providing strip lighting on floors, walls, or the like, the apparatus lying flush with the adjacent surfaces and protruding only slightly therefrom.
U.S. Pat. No. 3,609,343 relates to a light display for use within a fish tank or the like having a plurality of optical fibers arranged with their light-emitting end faces aligned toward the viewing area.


A fish cultivation tank including a suction unit rotatable about the bottom of the tank in response to a falling of the water level within the tank. A combined weight and float assembly moves in response to movement of the water level and is operationally joined to the suction unit to rotatably drive the suction unit in response to a lowering of the water level. The lowering of the water level is effected by a siphoning of water and debris from the tank whereby the siphoning of the debris occurs simultaneously with rotation of the suction unit.

The invention concerns a device that is a cultivation tank for aquatic organisms.
Fish tanks are presently either made of plastic, steel, or concrete in a number of designs. The removal of excess feed, excrement and the like is usually done by emptying large volumes of water from the tank to allow technical staff to brush the bottom of the tank clean. If the water outlet and supply is forced to flow by means of a current, there is a better degree of self-cleaning. This however requires considerable amounts of water to be supplied.
Marine fish larva such as cod, turbot, halibut and plaice are too sensitive for such strong water current. Thus the cleaning of tanks for these species has to be done manually by technical staff vacuuming the bottom with a syphon that has a suitable nozzle fitted to the end. This operation is excessively time consuming. In cases where the water is recirculated it is disadvantageous to have a strong water current flowing through the tank.