A phase-locked pivot assembly includes a support component. A first shaft and a second shaft pivot relative to the support component. A first annular body is configured to rotate with the first shaft. The first annular body includes a first outer annular surface and a first sunken arc portion. A second annular body is configured to rotate with the second shaft and corresponds to the first annular body. The second annular body includes a second outer annular surface and a second sunken arc portion. The first sunken arc portion and the second outer annular surface are matched and selectively contact each other to lock the first shaft. The second sunken arc portion and the first outer annular surface are matched and selectively contact each other to lock the second shaft.

1. Field of the Invention
The present invention relates to a pivot assembly and, more particularly, to a phase-locked pivot assembly.
2. Description of the Prior Art
With advanced technology, the touch panel is disposed on the notebook computer, the tablet computer and the smart phone widespread. The notebook computer with the touch panel can be switched as the tablet computer mode. The notebook computer includes a first casing and a second casing. The first casing is an upper cover whereon the touch panel is disposed, and the second casing is a base whereon electronic components, the battery and the keyboard are disposed. The first casing can rotate to be reverse to the second casing to switch the notebook computer into the tablet computer mode. In the meantime, the screen of the first casing faces outward. The structural relation of the first casing and the second casing includes the following embodiments.
One of the embodiments disposes a first pivot portion on a middle of a lateral side of the first casing, and further disposes a second pivot portion on a middle of a lateral side of the second casing. The first pivot portion corresponds to the second pivot portion. The first casing can rotate relative to the second casing via an assembly of the first pivot portion and the second pivot portion, and an angle of the second casing relative to the first casing can be adjusted accordingly. The first casing can rotate relative to the second casing to 180 degrees, the back of the first casing contacts against the second casing, the screen of the first casing faces outward, and the notebook computer can be utilized as the tablet computer for handheld touch operation. However, the conventional pivot mechanism has drawbacks of weak strength and short service life.
Another embodiment disposes a biaxial pivot assembly between the first casing and the second casing. The biaxial pivot assembly includes a first shaft and a second shaft, which are respectively connected to the first casing and the second casing. The first casing can rotate relative to the second casing within a range of 0˜360 degrees. As the first casing rotates relative to the second casing to 360 degrees, the back of the first casing contacts against the second casing, and the screen on the first casing faces outward. The conventional biaxial pivot assembly has drawbacks of inconvenient operation and sluggish rotation due to asynchronous connection between the first shaft and the second shaft.


A semiconductor device includes a semiconductor substrate having an electrode and a conductive pad; a resin projection formed on the semiconductor substrate; and a wiring electrically connected to the electrode, the wiring having a first portion formed on the electrode, a second portion formed on the conductive pad and a third portion formed on the resin projection between the first portion and the second portion.

1. Technical Field
The invention relates to a semiconductor device.
2. Related Art
For the sake of down-sizing of electronic parts, a smaller contour of the semiconductor device is preferred. However, as a roll of the semiconductor device is diversified, high integration of an integrated circuit formed on a semiconductor chip advances. Accordingly, the number of pins for the semiconductor chip becomes large. In other words, such a semiconductor device that can concurrently satisfy two requirements such as the down-sizing of the semiconductor device and the high integration of the integrated circuit is currently under development.
The semiconductor device of a type including a wiring formed on the semiconductor chip is come under spotlight as the one which meets the above stated requirements. In this type of semiconductor device, since the contour of the semiconductor device can be made to have the generally same contour of the semiconductor chip, the down-sizing of the semiconductor device is achievable in comparison with the known semiconductor packages.
The above stated advantageous semiconductor device is also required for a reliability equal to or more than the known semiconductor device. Therefore, the semiconductor device may be subjected to various checks. In order to guarantee the reliability of the semiconductor device, it is important to conduct an electric property check that is highly reliable.
JP-A-02-272737 is an example of related art.


A system having a heat source, a component coupled to the heat source, and at least one thermistor coupled to the component and adapted to monitor temperature of the component, wherein the thermistor has a core-shell microstructure having a shell disposed about a core, the core comprising Cr2O3 and the shell comprising a rare earth element compound.

This invention relates generally to temperature measuring devices or thermistors and, more particularly, to material compositions for high temperature thermistors.
High temperature thermistors are often employed to measure the temperature in a hot water supply, the temperature of a heating furnace, the exhaust gas temperature of a heating furnace, or the exhaust gas temperature of a motor vehicle. In these applications, temperatures may range from about 100 degree Celsius to around 1000 degree Celsius. However, the performance of these thermistors generally degrades at higher temperatures.
In certain applications, the accuracy of these thermistors is particularly important for the overall operation of a system. For example, the performance of engines, catalytic converters, and other devices may depend largely on the accuracy of temperature measurements. In combustion engines, the fuel-air mixture, pressure, temperature, and other factors play an important role in the control of exhaust emissions, such as nitrous oxide (NOx), carbon monoxide (CO), and hydrocarbons (HCs). In addition, modern vehicles are often equipped with catalytic converters, which are disposed in an exhaust line coupled to the engine. These catalytic converters use agents or catalysts, such as reduction and oxidation catalysts, to convert emissions of environmentally unfriendly gases into more environmentally friendly gases. For example, a particular catalytic converter may convert nitrous oxide, carbon monoxide, and hydrocarbons into other forms, such as carbon dioxide and nitrogen. Again, accurate temperature measurements play an important role in the operation of these catalytic converters and the overall combustion engine.
A typical catalytic converter operates at temperatures well above 200 degrees Celsius. The performance of the catalytic converter can be monitored by the temperature differential across the converter. In certain applications, the operating temperature of a catalytic converter may be in the range of 300–600 degrees Celsius and the temperature differential across the catalytic converter may be on the order of 10 degree Celsius. Under certain conditions, the temperature endured by a catalytic converter can reach or exceed 1000 degrees Celsius, e.g., if unburned fuel is present in the exhaust line. Hence, thermistors should preferably withstand high temperatures to ensure reliable operation.
Existing thermistors include an unglazed thermistor, which has chromium (Cr) based oxides that have a negative temperature coefficient (NTC) of resistance. Unfortunately, the resistance values of these Cr-based oxides shift upon sufficient aging, e.g., at 1000 degrees Celsius for 1000 hours. This resistance shift is apparently caused by the loss of chromium oxide (Cr2O3) by volatilization over time.
There is a need, therefore, for an improved thermistor, which can reliably perform at high temperatures over time.

Temperature measuring device and system and method incorporating the same


The invention relates to guanidine derivatives of formula (I) where: A represents a chain of 3-6 carbon atoms, one of which can be replaced by —N(R′)— or —O— and R′ is H or a substituent; the ring skeleton only contains both double bonds of the thiazole component; the pharmaceutically-acceptable acid addition salts of basic compounds of formula (I), the pharmaceutically-acceptable salts of compounds of formula (I), comprising acid groups, with bases, the pharmaceutically-acceptable esters of hydroxy or carboxyl group containing compounds of formula (I) and the solvates or hydrates thereof, which exhibit a neuropeptide FF receptor antagonist effect. The above are suitable for the treatment of pain and hyperalgesia, withdrawal symptoms in alcohol, psychotropic and nicotine dependencies, for improvement or cure of said dependencies, for regulation of insulin excretion, food intake, memory functions, blood pressure, electrolyte and energy management and for treatment of urinary incontinence. The above can be produced using generally used methods and processed to give medicaments.

(i) Field of the Invention
The present invention relates to guanidine derivatives of the general formula
in which A represents a chain of 3-6 optionally substituted C atoms, one of which can be replaced by —N(R′)— or —O—; and R′ represents hydrogen or a substituent; the ring skeleton containing only the two double bonds of the thiazole component; pharmaceutically applicable acid addition salts of basic compounds of formula I, pharmaceutically applicable salts of acid group-containing compounds of formula I with bases, pharmaceutically applicable esters of hydroxy or carboxy group-containing compounds of formula I as well as hydrates or solvates thereof.
Guanidine derivatives of formula I which contain one or more asymmetric center can be present as optically pure enantiomers, as mixtures of enantiomers, such as for example racemates, or optionally as optically pure diastereomers, as mixtures of diastereomers, as diastereomeric racemates or as mixtures of diastereomeric racemates.
The products defined at the outset are partly known and partly novel, and they are characterized by valuable pharmacodynamic properties, acting as neuropeptide FF receptor antagonists.
In a first aspect the present invention relates to the use of the compounds described at the outset of Formula I as well as the salts, esters, hydrates and solvates likewise defined at the outset as neuropeptide FF receptor antagonists or for the preparation of corresponding medicinal products, in particular for the treatment of pain and hyperalgesia, withdrawal syndromes in the case of alcohol, psychotropic and nicotine dependences and for the improvement or elimination of these dependences, for the regulation of insulin secretion, food intake, memory functions, blood pressure, and of the electrolyte and energy balance and for the treatment of urinary incontinence or for the preparation of corresponding medicinal products.
The pains to be treated according to the invention can be chronic, acute, long-lasting or temporary, these pains being able to be of operative, traumatic, or pathological origin; an advantage achieved according to the invention consists in the prevention of opioid tolerance and/or opioid dependence.
(ii) Description of the Related Art
Back in 1985 neuropeptide FF (NPFF; H-Phe-Leu-Phe-Gln-Pro-Gln-Arg-Phe-NH2 [99566-27-5]), an octapeptide, and neuropeptide AF (NPAF; H-Ala-Gly-Glu-Gly-Leu-Ser-Ser-Pro-Phe-Trp-Ser-Leu-Ala-Ala-Pro-Gln-Arg-Phe-NH2 [99588-52-0]), a related octadecapeptide, were discovered as neurotransmitters of the central nervous system in cattle brains (Yang et al., Proc. Natl. Acad. Sci. USA 1985, 82(22), 7757-61) and originally characterized as anti-opioid peptides. The carboxy-terminal amidated neuropeptides were, because of their reactivity with anti-Phe-Met-Arg-Phe-NH2 antiserum, included among the FMRF-amide-like peptides. Both peptides have pain-modulating properties, the octapeptide having greater effectiveness. Both peptides play an important role both in opioid-dependent analgesia and in the development of tolerance to opioids (review article: Roumy and Zajac, Europ. J. Pharm. 1998, 345, 1-11; Panula et al., Prog. Neurobiol. 1996, 48, 461-87). Interestingly, in animal tests, NPFF shows, depending on the nature of the administration, both anti-opioid and pro-opioid actions. Thus NPFF can reverse the acute effects of opioids and an increased concentration in the brain is possibly responsible for the development of opioid tolerance and dependence. In rats, for example, the intracerebroventricular (i.c.v.) administration of NPFF lowers the nociceptive threshold and reduces the analgesia induced by morphine. Administration of NPFF to morphine-tolerant rats causes symptoms of withdrawal phenomena. The analgesic effect of morphine in morphine-tolerant rats was reproduced after i.c.v. injection of anti-NPFF IgG (Lake et al., Neurosci. Lett. 1991, 132, 29-32). Immunoneutralization of NPFF by intrathecally (i.t.) administered anti-NPFF antibodies increase the analgesia caused by endogenous and exogenous opioids. By direct injection of NPFF or NPFF-analogues into the spinal cord (i.t.) a pro-opioid effect with a long-lasting opioid-like analgesia and an increased pain-relieving effect of morphine was obtained (Gouardères et al., Eur. J. Pharmacol. 1993, 237, 73-81; Kontinen and Kaso, Peptides 1995, 16, 973-977).
According to other reports NPFF also appears to play a role in physiological processes such as insulin secretion, regulation of food intake, memory functions, regulation of blood pressure and electrolyte balance (Panula et. al., Prog. Neurobiol. 1996, 48, 461-487).
In various types of mammal, such as humans, rats, mice and cattle, the discovery was reported of a gene, which codes NPFF and NPAF as a common precursor protein, from which the two active peptides are finally split off (Perry et al., FEBS Lett. 1997, 409, 426-30; Vilim et al., Mol. Pharmacol. 1999, 55, 804-11). In humans the gene for this precursor is expressed both peripherally in various organs and in regions of the central nervous system, in particular in the cerebellum (Elshourbagy et al., J. Biol. Chem. 2000, 275 (34), 25965-71), while the expression in rats is restricted exclusively to specific regions of the central nervous system such as the hypothalamus, medulla, and dorsal horn of the spinal cord. On the basis of the demonstration of NPFF in human blood plasma it is presumed, that the peptides are peripherally also responsible for hormone-like effects (Sandblom et al., Peptides 1998, 19, 1165-70).
In tissue samples from humans and rats two G-protein coupled receptors (GPCR), NPFF1 and NPFF2 were identified (Bonini et al., J. Biol. Chem. 2000, 275 (50), 39324-31; Kotani et al., Br. J. Pharmacol. 2001, 133, 138-44), NPFF2 being identical to the receptor HLWAR77 originally described as an orphan (Elshourbagy et al., J. Biol. Chem. 2000, 275 (34), 25965-71). NPFF1 and NPFF2 were able to be characterized as specific receptors with affinities in the nanomolar and subnanomolar regions for the two neuropeptides FF and AF. NPFF binds to NPFF1 with a binding constant Kd=1.13 nM and to NPFF2 with Kd=0.37 nM. The identity of NPFF1 and NPFF2 is around 50%. The comparison of the amino acid sequences with known GPCRs shows a 30-40% similarity with human orexin-1, orexin-2, neuropeptide Y(NPY) Y2, cholecystokinin A, NPY Y1, prolactin-releasing hormone receptor and NPY Y4. The distribution of NPFF1 and NPFF2 in various tissue samples from humans and rats was determined by demonstrating the m-RNA using RT-PCR (reverse transcription-polymerase chain reaction). NPFF1 was demonstrated predominantly in the central nervous system (CNS). By contrast, NPFF2 was found predominantly in the spinal cord. These findings are supported by autoradiographic methods using selective NPFF1 and NPFF2 radioligands (Allard et al., Brain Res. 1989, 500, 169-176; Neuroscience 1992, 49, 106-116; Gouardères et al., Neuroscience 2002 115:2 349-61).
The neuropeptides SF (NPSF, 37 amino acids) and neuropeptide VF (NPVF, octapeptide) described as NPFF-related peptides, both located on the so-called NPVF-gene, bind with comparatively greater affinity and selectivity to the NPFF1 receptor than NPFF and NPAV. The NPVF peptides also block the morphine-induced analgesia in acute and inflammatory pain models more markedly than NPFF and emphasize the importance of the NPVF/FF1 system as part of an endogenous anti-opioid mechanism (Q. Liu et al., J. Biol. Chem. 2002, 276 (40), 36961).
The incidence of functional NPFF1 and NPFF2 receptors in adipocytes and the effect of NPFF and NPAF on key sites of signal transmission in the adipose metabolism suggest that the two peptides, alongside their original pain-modulating effects, could also have an influence on the storage and use of body energy (I. Lefrère et al., J. Biol. Chem. 2002, 277 (42), 39169).
The desamino-Tyr-Phe-Leu-Phe-Gln-Pro-Gln-Arg-NH2 peptide was described as the first NPFF-receptor antagonist counteracting the NPFF effects. After i.c.v. injection this peptide reduced the withdrawal syndromes in the case of morphine dependence (Malin et al., Peptides 1991, 12, 1011-1014). However, this peptide showed no bioavailability whatever in the central nervous system. Optimization of the tripeptide Pro-Gln-Arg-NH2 in a combinative approach led to dansyl-Pro-Gln-Arg-NH2, or dansyl-Pro-Ser-Arg-NH2, both with improved properties for passing through the blood-brain barrier, which, after systemic administration in rats led to an improved antagonistic effect of the anti-opioid symptoms caused by NPFF (Prokai et al. J. Med. Chem. 2001, 44, 1623-1626). The Arg-Tyr-amide peptoid BIBP3226 originally described as an NPY Y1 selective receptor antagonist showed a 10-60 times higher affinity to the human and rat-NPFF1 receptor than to the corresponding NPFF2 receptors (Bonini et al., J. Biol. Chem. 2000, 275 (50), 39324-31). From a series of compounds which originate from the NPY Y1 selective antagonist BIP3226, selective hNPFF1 receptor antagonists were obtained which showed affinities of 40-80 nM (Mollereau et al., Europ. J. Pharmacol. 2002, 45, 245-56).
The two neuropeptide FF analogues 1DME ([D-Tyr1,(Nme)Phe3]NPFF) and Nic-1DME (nicotinoyl-pro-1Dme) showed different pharmacological properties in the mouse tail-flick test, although both compounds bind to NPFF1 and NPFF2 with comparable affinity and selectivity. Both 1DME and Nic-1DME reinforce the morphine analgesia after i.t. and i.p. administration, but Nic-1DME cannot suppress morphine-induced analgesia after i.c.v. and i.p. administration (Quelven et al., Europ. J. Pharmacol. 2002, 449, 91-98).
In WO 02/24192 A1 synthetic NPFF ligands with a peptide structure, based on arginine as the central component, are described.

Guanidine derivatives and their use as neuropeptide FF receptor antagonists


A reusable sign/banner system which includes flexible static cling vinyl indicia and a sheet of flexible, smooth, non-porous, flaccid plastic material. The indicia are electrostatically adhered to the plastic sheet. The indicia are cut in a plurality of shapes and forms as to form letters, numbers and symbols for the purpose of creating signs and banners to communicate words, numerical expressions and directions. In use, the indicia are peeled from a plasticized paper backing sheet and applied to the flexible, smooth, non-porous plastic material in a variety of configurations. The banner material can be hung by grommets installed in the sheet of flexible, smooth, non-porous plastic material or displayed against any irregular or curved surface or hung across open spaces. Both the static cling vinyl and the flexible, smooth, non-porous plastic material can be provided in a variety of colors to facilitate visibility.

1. Field of the Invention
It has long been recognized that there is a need for temporary signs and banners that can easily be changed as the information contained on the sign changes. In addition, there is always a need for clear, well-constructed sign systems which can be managed by individuals with limited artistic skills. Further, there is a need for reusable sign/banner systems that are flexible to accommodate many display and storage constraints.
2. Description of the Prior Art
In this regard, U.S. Pat. No. 4,654,101 describes a method for affixing letters, numbers and the like onto a sign using magnetic attachment and letters that are tapered in order to make the sign look more like a continuous sign. Likewise, U.S. Pat. No. 3,440,746 describes a method for using a pressure sensitive adhesive to attach onto a backing material a clear film onto which individual letters or numbers have been printed, thereby to make custom-designed signs. In most instances, the ability of pressure sensitive adhesives to be reused over and over again is severely limited by the tendency of the adhesive to become irreversibly contaminated with dirt and debris. It is also known that various static cling materials can be used to affix images to surfaces, usually surfaces that are flat and rigid, such as glass or plastic. In this regard, U.S. Pat. No. 5,102,171 reveals a greeting card containing an image printed on a clear static cling material that can be removed from the card and placed upon a window or mirror and held in place by the static cling nature of the material. Likewise, U.S. Pat. No. 4,652,239 reveals the use of static cling images for space arranging and planning systems. U.S. Pat. No. 5,252,071 teaches the use of static cling drapery images to simulate the appearance of drapes on windows for easy visualization by designers and their potential clients. In addition, it is possible to purchase letters and numbers that have been printed onto clear static cling sheet for use on glass windows, etc.


The present invention relates to a multi-core optical fiber applicable to an optical transmission line of bi-directional optical communication and a bi-directional optical communication method. The multi-core optical fiber has plural cores in a common cladding. Signal light is transmitted in a first direction through an arbitrary core among the cores, whereas the signal light is transmitted in a second direction opposite to a first direction, through all the nearest-neighbor cores to the arbitrary core.

1. Field of the Invention
The present invention relates to a method of performing bi-directional optical communication by using a multi-core optical fiber as an optical transmission line, and relates to a multi-core optical fiber suitably used in the bi-directional optical communication.
2. Related Background of the Invention
As compared with optical communication which uses a standard single core optical fiber as an optical transmission line, in optical communication which uses a multi-core optical fiber as an optical transmission line, there is an advantage that a construction cost and maintenance cost per capacity are cheap since large amount of information can be transmitted/received by a smaller number of optical fibers.

Bi-directional optical communication method and multi-core optical fiber


This present invention brings to the multiprocessor what vectorization brought to the single processor. It provides similar tools to speed communication that have traditionally been used to speed computation; namely, the capability to program optimal communication algorithms on an architecture that can replicate their performance in terms of wall clock time. In addition to the usual complement of logic and arithmetic units, each processor contains a programmable communication unit that orchestrates traffic between the network and registers that communicate directly with comparable registers in neighboring processors. Communication tasks are performed out of these registers like computational tasks on a vector uniprocessor. The architecture is balanced and the hardware/software combination is scalable to any number of processors.

Since the advent of computing, the time required to access data from memory has steadily increased relative to the computational processing time. Vector processors were developed in the 1970s to minimize the load/store time between processors and memory for repetitive computations by performing the computation in an assembly line manner. With the advent of multiprocessor architectures in the late 80s, processor speed and local memory access were markedly faster than communication between processors, which completely dominated total compute time.
During the late 80s and 90s several companies were established to further the idea of combining the power of emerging microprocessors into a single "supercomputer." Of particular interest was the Connection Machine (CM) that was built by Thinking Machines Inc.; Hillis (U.S. Pat. No. 4,598,400), Theil, et al. (U.S. Pat. No. 4,805,091), (U.S. Pat. No. 4,814,973), Hillis (U.S. Pat. No. 5,535,408), Hillis (U.S. Pat. No. 5,590,283), and Wade et al. (U.S. Pat. No. 6,219,775). The CM demonstrated the feasibility of a supercomputer based on a massive number of processors but fell victim to what will be referred to as the "Communication Problem" that is discussed below. On paper the CM had a very impressive "peak" speed but in practice the machine would achieve less than single digit efficiency as measured by the ratio of computation to communication time. To date, efficiency has not improved for a number of reasons that will be discussed in further detail below. Primarily, this lack of efficiency is because communication speed has not kept pace with processor speeds. Consider the recent quote in the March 2006 issue of the High Performance Wire newsletter by the Chief Technical Officer (CTO) at Cray Inc.:                ". . . but as it is widely recognized, when scientific computing migrated to commodity platforms, interconnect performance, both in terms of bandwidth and latency, became the limiting factor on overall application performance and remains a bottleneck to this day."Steve Scott, CTO of Cray, In HPCwire, 24 Mar., 2006
This statement was made to explain Cray's shift to building special purpose computers outside the "commercial off-the-shelf" (COTS) framework. This is a remarkable shift by the company whose name has been synonymous with general purpose supercomputing. Nevertheless it is a reasonable shift considering the extent of the communication "bottleneck.".
Turning to the particular problems facing existing multiprocessor supercomputer systems, an understanding of the general nature and utilization of the systems is required. Multiprocessor systems are comprised of a number of interconnected processors. The largest and most powerful systems are often referred to as supercomputers. Supercomputers are used for the most computation demanding applications such as weather prediction. These applications are distributed across the interconnected processors by assigning a portion of the overall computation task to each processor. However, to complete even a portion of the overall computation, each processor must communicate intermediate results to other processors. The communication among the processors adversely affects the performance of a multiprocessor for a number of reasons. Specifically, a first issue arises even in the communication of a two processor system, wherein performance is adversely affected because the off-chip communication between the processors is generally much slower than on-processor computation.
A second issue relates to having an increased numbers of processors participating in the multiprocessor. Essentially, it rapidly becomes impractical to directly connect all processors to all other processors. As such, communication between any two or more processors is likely to be routed through intermediate processors, further degrading communication speed by at least a factor equal to the number of processors on the route.
A third issue relates to the fact that data must be routed to all processors in parallel to support the parallel computation for which such supercomputer systems are designed. That is, to compute in parallel, all processors must be able to receive data simultaneously. Simultaneous data receipt leads to further degradation of communication because of possible contention or the blocking of transmissions by other transmissions.
A fourth issue relates to blocking and other such contention for resources. To eliminate blocking and otherwise optimize performance, transmissions must be scheduled. Depending on the overall system design, transmission scheduling may require additional time. System software and protocols are utilized to implement schedules that require real time transmission and decoding of the schedule and destination addresses, further contributing to an overall degradation in performance.
A fifth issue relates to the shear number of processors in a particular multiprocessor system. As the number of processors increases, there is a corresponding increase in the physical system size. The physical size increase also increases signal distance and transmission time within the multiprocessor.
A sixth issue relates to system imbalances, which result in idle circuitry (i.e., an under utilization of all the available resources). Examples of imbalances include mismatched local and global communication speeds and/or mismatched communication and computation speeds. The effect of such imbalances is to delay or idle certain system components until the slower components complete their tasks.
A seventh issue further relates to the complexity of the network as processor numbers increase. Fixed off-chip bandwidth has to be shared between an increasing number of channels thereby reducing the individual channel bandwidth.
An eighth issue is that the use of cache and resulting coherency communication associated with shared memory can substantially increase the resources of the multiprocessor that are dedicated to communication.
In light of the issues discussed above, one can understand why it is possible for performance to decrease with increasing numbers of processors. The increased communication between the additional processors requires more time than the decrease in computation time. An architecture/computation that yields such results or effects is said to lack scalability.
The magnitude of the communication problem is evident in multiple processor supercomputers where communication likely consumes 90% or more of the total compute time, resulting in a decrease of overall computing performance of such supercomputers. As such, in light of the foregoing problems there exists a need for a system and method, to address the relatively poor performance of multiprocessor systems despite the increase in processor and memory speeds. Specifically, there exists a need to provide a solution to the communication delay among processors in a multiprocessor environment.
There exists a further need to provide a scalable multiprocessor system wherein overall performance of the multiprocessor system will increase in relative and direct proportion to the number of individual component processors. In sum, the magnitude of the communication problem as earlier described, justifies an effort in both circuitry and software that is comparable to the effort that has been made over the years to improve computation. Indeed, every multiprocessor computational task has an underlying communication task, thus a solution to the "Communication Problem" would have a wide spread and significant impact on future multiprocessor performance. It is intuitive that the performance we ultimately seek will come in the form of multiprocessors with truly massive numbers of processors.

System and method for vector-parallel multiprocessor communication


In the tree structure, a migrating node forms a connection with a parent node of a migration destination, the migrating node transmits a migration request to a root node, and the root node distributes a reply to the migration request according to the tree structure, upon receiving the reply, the parent node of the migration destination transmits a message, which is received later than the reply, to the migrating node via the formed connection, the migrating node stores in a queue messages which are received later than the reply received via the formed connection, upon receiving a reply distributed according to the tree structure, the migrating node reconstructs the distributed message, based on a message which is received earlier than the reply received from the parent node before migration and a message which is received later than the reply stored in the queue.

In an information processing system which includes a plurality of information processing devices, the plurality of information processing devices may be connected to a tree structure as nodes. For example, a database system in which a plurality of master nodes are hierarchically connected by a network is known (Japanese Patent No. 4951137).

Method for managing tree structure, information processing system, and medium


A virtual business mobile device can be provisioned on a personal mobile device, by binding a mobile application for provisioning the business mobile device to a privileged component of a host operating system of the personal mobile device, wherein the binding enables a software virtualization layer and a management service component of the mobile application to execute in a privileged mode. The mobile application is then able to download a virtual phone image for the business mobile device and security-related policy settings relating to use of the business mobile device from a mobile management server, wherein the software virtualization layer is able to launch a virtual machine for the business mobile device based on the virtual phone image. Once the virtual phone image has been downloaded, the management service component initiates a periodic attempt to establish a connection with the mobile management server to comply with the downloaded security-related policy settings.

Over the past decade, enterprises have experienced a substantial increase in the productivity of its workforce when providing them with business mobile devices. In the past, given their high cost, business mobile devices were mainly allocated to management and focused on providing employees with email access and cellular phone capabilities. However, recent improvements in the computing power, mobile display technologies and connection speeds of mobile devices, combined with the continued decreases in hardware costs, have made powerful mobile devices available even to the general public for personal use. More and more individuals personally own powerful mobile devices, such as smartphones, that, in addition to serving as a cellular phone, can be used in many of the same ways as a desktop or a laptop, such as accessing emails, browsing documents or the internet, game playing, listening to audio or viewing a video, and personal information management (PIM).
Due to the above trends in mobile devices, enterprises are currently experiencing an "invasion" of personal devices into the workplace. Given the sophisticated capabilities of their personal mobile devices, employees no longer desire possessing a separate personal and business mobile device and continually pressure information technology (IT) departments to support personal devices brought into the workplace. As such, IT departments struggle to maintain a proper balance between enabling a certain level of access to enterprise data (e.g., such as access to email, contacts, documents, and the like) on personal devices and ensuring adequate security measures to protect corporate intellectual property in such enterprise data. This phenomenon has led enterprises to investigate the viability of a "Bring Your Own Device" (BYOD) strategy to IT, where a personal mobile device is provisioned by IT departments with the capability of operating as a complete business mobile device in a secure fashion.
Such a BYOD strategy could significantly decrease IT costs (e.g., by eliminating or reducing the need to purchase and provision hardware devices) and provide mobile enterprise access to many more employees than was previously possible (e.g., due to cost concerns), thereby achieving greater increases in productivity than before. However, significant challenges arise in provisioning "work environment" on a personal mobile device that maintains adequate security and data partitioning between the employee's "personal world" and the employer's "business world."

This patent is subject to a terminal disclaimer.

Provisioning work environments on personal mobile devices


An elliptical exercise machine and methods for using the machine where the horizontal length of the stride of the ellipse can be adjusted by the user without the user having to alter the vertical dimension of the ellipse by an equivalent amount.

1. Field of the Invention
This disclosure relates to the field of elliptical exercise machines. In particular, to elliptical exercise machines which allow for alteration in the shape of the foot path.
2. Description of the Related Art
The benefits of regular aerobic exercise on individuals of any age is well documented in fitness science. Aerobic exercise can dramatically improve cardiac stamina and function, as well as leading to weight loss, increased metabolism and other benefits. At the same time, aerobic exercise has often been linked to damaging effects, particularly to joints or similar structures where the impact from many aerobic exercise activities causes injury. Therefore, those involved in the exercise industry are continuously seeking ways to provide users with exercises that have all the benefits of aerobic exercise, without the damaging side effects.
Most low-impact aerobic exercises have traditionally been difficult to perform. Many low-impact aerobic exercises (such as those performed in water) traditionally require performance either outside or at a gym. Cold weather, other undesirable conditions, and cost can make these types of aerobic exercise unobtainable at some times and to some people. In order to allow people to perform aerobic exercises without having to go outside or to gyms or the like, fitness machines have been developed to allow a user to perform aerobic exercises in a small area of their home.
Many of these machines, however, suffer from either being relatively high-impact, or from being complicated to use and understand. In either of these cases, the fitness machine often becomes a coat rack instead of being used for its intended purpose. Recently, a class of machines which are referred to as "elliptical machines" or "elliptical cross-trainers" have become very popular due to their ease of use and their provision of relatively low-impact aerobic exercise.
Generally in these types of machines, a user performs a motion using their legs that forces their feet to move in a generally elliptical motion about each other. This motion is designed to simulate the motion of the feet when jogging or climbing but the rotational motion is "low-impact" compared to jogging or climbing where the feet regularly impact a surface. In an elliptical machine, a user uses a natural walking motion to instead move their feet through the smooth exercise pattern dictated by the machine. This motion may also be complemented by them moving their arms in a reciprocating motion while pulling or pushing various arms on the machine whose motion is connected to the motion of the feet, and vice-versa.
Currently, the biggest problem with elliptical machines is that the dimensions of the ellipse made by the user's feet are generally severely limited in size and shape by the design of the machine. The ellipses generated by these machines are often created by the interaction of a plurality of different partial motions, and attempts to alter the motion of a user in one dimension generally also alters the motion in another. It is desirable that users have the option to arrange the machine so that the ellipse can be tailored to fit their stride, but with machines on the market today, that generally is not possible.
The problem is most simply described by looking at the elliptical motion the feet make when using an elliptical exercise machine. This elliptical motion can be described by the dimensions of the ellipse. Since users generally stand upright on elliptical machines, the user's feet travel generally horizontally relative to the surface upon which the machine rests. This represents the users stride length or how far they step. Further, the user's feet are raised and lowered relative to the surface as they move through the ellipse. This is the height to which the user's feet are raised. How a user steps depends on the type of action they are performing. A more circular ellipse will often correspond more to the motion made while climbing, a slightly more elongated ellipse is more akin to walking, while a significantly elongated ellipse can be more akin to the motion of running.
Even within this limited framework, however, each user's stride length is different. A very short person will generally want all the dimensions of the ellipse to be smaller than someone who is very tall or has particularly long legs. In an elliptical machine, it therefore desirable that the length of the machine's "stride" correspond to the particular stride length of that user. Further, as a user's speed on the machine increases or decreases or as the resistance imparted by the machine increases or decreases, it can be desirable for the machine to alter the type of stride the user is making (by elongating or shortening the stride) to better correspond to a more natural movement.
In elliptical machines currently, the size and shape of the ellipse is generally fixed by the construction of the machine. That is, the footrests (the portion of an elliptical machine that will traverse the same ellipse as the user's feet) are generally forced to proscribe only a single ellipse when the machine is used and that ellipse is generally unchangeable. Some machines allow for some alteration of this ellipse, but generally those machines increase both dimensions of the ellipse, not just the horizontal component. That is, the user can adjust the total size of the ellipse, but the ratio of the ellipse's components always remains relatively constant.
This arrangement means that many users are not comfortable with the stride of an elliptical machine as it is either too long or too short for their stride. Even if the stride is adjustable, the user may still be uncomfortable. For some users, the stride will be much too short compared to their normal stride and attempts to increase the stride length result in their feet being raised uncomfortably high (e.g. turning a walking or jogging exercise motion into more of a climbing motion), while for others the same machine's stride can be much to long (resulting in overstretching of their legs as if they are running all the time). Further, a user may desire to tailor the machine's motion for the general type of exercise they want to perform (e.g., more jogging motion or more climbing motion) and may wish to alter the motion during an exercise session to have a more varied workout.

Adjustable stride elliptical motion exercise machine and associated methods


Shortening setup and hold times by equalizing the signal propagation delay time between input buffer circuits and D-F/F circuit to which are supplied command control signals CSB, RASB, CASB, and WEB supplied from a plurality of external terminals, and synchronizing these command control signals with the internal clock signal ICLK, batch loading these into D-F/F circuit and holding this signal, sending it from decode circuits after decoding, and latching it with latch circuits by means of internal clock delay signal ICLKD generated and delayed by internal clock signal ICLK thus being capable of shortening setup time and hold time in a synchronous DRAM.

1. Field of the Invention
This invention relates to a semiconductor memory device for shortening setup time and hold time of command control signals used in synchronous DRAM (Dynamic Random Access Memory) for performing input of addresses and commands, and input and output of data synchronously with external clock signals.
2. Description of the Related Art
In recent years, synchronous DRAM devices have appeared which not only have high speed, but can synchronize with external clocks at frequencies in excess of 100 MHz. These high speed devices require even tighter specifications for setup time and hold time than is needed with conventional devices.
One example of the related art for a command decode method in a synchronous DRAM can be seen in Japanese Patent Laid-open Hei 7-141870. This synchronous DRAM is provided with a clock input terminal CLK, command input terminals CKE, CSB, RASB, CASB, WEB and DQM (Low enable signals are shown here with a B at the end of the signal name.) address input terminals A0-Ai, and data input/output terminals DQ0-DQj. Input of addresses and commands and input/output of data are triggered by the rising edge of the pulse of the external clock signal CLK.
FIG. 6 shows a block diagram of one example of the above-mentioned command decode method. A memory device 200 has an input buffer circuit 1 connected to an external clock signal CLK input terminal 21. This input buffer circuit 1 has a clock enable terminal to control whether or not to output the clock signal that was input. The output terminal is connected to serially connected drive buffers N1 and N2 in that order. The drive buffer N2 outputs the internal clock signal ICLK.
An input buffer circuit 2 is connected to an external clock enable signal CKE input terminal 22. The output terminal is connected to serially connected drive buffers N3 and N4 in that order. An output terminal of the drive buffer N4 outputs an internal clock enable signal ICKE and is connected to the enable terminal of the input buffer 1.
An input buffer circuit 3 is connected to a chip select signal CSB input terminal 23. An input buffer circuit 4 is connected to a row address select signal RASB input terminal 24 and an input buffer 5 is connected to a column address select signal CASB input terminal 25. An input buffer circuit 6 is connected to a write enable signal WEB input terminal 26. These input buffer circuits 3 through 6 are each connected to both of decode circuits 9 and 10 by means of output signal lines A1 through A4.
The output terminal of the command decode circuit 9 is connected to a latch circuit 11 by means of a decode output line C1 and the latch circuit is also fed with an internal clock delay skew signal ICLK1. This latch circuit 11 supplies the mode control signal MODE1 to internal circuits (not shown).
A output terminal of the command decode circuit 10 is connected to a latch circuit 12 by means of a decode output line C2 and the latch circuit is also fed by an internal clock delay skew signal ICLK2. This latch circuit 12 supplies a mode discriminator signal MODE2 to the internal circuits.
The operation of the memory device 200 is explained next. First, the external clock signal CLK is fed into the input buffer circuit 1. This input buffer 1 is fed with the internal clock enable signal ICKE, and is triggered by the internal clock enable signal ICKE outputted from the drive buffer N4. This input buffer circuit 1 is triggered when the internal clock enable signal ICKE is at a high logic level (hereafter called H level). The external clock signal CLK is input and the internal clock signal ICLK is fed to the internal circuits.
In this example, in order to shorten the time needed up to the decode timing and to simplify the circuit, the command control signals; chip select signal CSB, row address strobe signal RASB, column address strobe signal CASB and Write Enable signal WEB are inputted to the input buffers 3-6 and then transferred to the command decode circuits 9 and 10. The command decode signals which are the outputs from the command decode circuits 9 and 10, are latched with the edge of the rise pulse of ICLK1 and ICLK2 into the latch circuits 11 and 12.
The address signals are utilized for final mode discrimination but are omitted from the drawings for the sake of simplicity.
The timing chart for the command decode method is shown in FIG. 7. When the signal CKE is at H level, the external clock signal CLK is valid. The command control signals (CSB, RASB, CASB, WEB) are input so as to contain the setup time (tSE) and hold time (tHE) versus the external clock signal.
The output signals A1 through A4 change after the amount of time (t0) required to pass through input buffer circuits 3 to 6. The signal from the output lines C1 through C2 are delayed by the time caused by the wire length between the input buffer circuits 3-6 and the command decode circuits 9 and 10 and also by the times (t11 and t12) needed to pass through the command decode circuits 9 and 10. These delayed signals are latched with the edge of the rise pulse of the internal clock ICLK into the latch circuits 11 and 12, respectively. Here since the internal clock signal ICLK has skew .DELTA.t resulting from delay due to wire length, the internal clock signals fed into the latch 11 and 12 are listed as the internal clock skew signals ICLK1 and ICLK2.
Another example of a command decode method is shown in the block diagram of FIG. 8. In a memory device 300, the input buffer circuit 1 connected to the external clock signal CLK input terminal 21 has an enable terminal to control whether or not to output the clock signal. The buffer output is connected to the serially connected drive buffers N1 and N2 and to a delay circuit 7. The drive buffer N2 outputs the internal clock signal ICLK and the output of the delay circuit 7 is connected to serially connected buffers N3 and N4.
An input buffer circuit 2 is connected to a clock enable signal CKE input terminal 22. A output of input buffer circuit 2 is connected to serially connected drive buffers N3 and N4. The drive buffer N4 output a internal clock enable signal ICKE.
An input buffer 3 is connected to signal terminal CSB input terminal 23. A output from the input buffer circuit 3 is connected through the output line A1 to the flip-flop D-F/F 8a supplied with the internal clock skew signal ICLK1.
A row address select signal RAS input terminal 24 connects to an input buffer circuit 4. The output from this input buffer circuit 4 connects by means of output line A2 to the flip-flop D-F/F 8b to which is supplied the internal clock signal ICLK2.
A column address select signal CAS input terminal 25 connects to an input buffer circuit 5. The output from the input buffer circuit 5 connects by means of output line A3 to flip-flop D-F/F 8c to which is supplied the internal clock skew signal ICLK3.
A write enable signal WE input terminal 26 connects to an input buffer circuit 6. The output from this input buffer circuit 6 connects by means of output line A4 to flip-flop D-F/F 8a-8d to which is supplied the internal clock skew signal ICLK4. The outputs from these flip-flops D-F/F 8a-8d connect to both of the command decode circuits 9 and 10.
The output from the command decode circuit 9 is connected through a decode line C1 to a latch circuit 11 supplied with an internal clock delay skew signal ICLKD1. This latch circuit 11 supplies the mode control signal MODE1 to the internal circuits.
The output from the command decode circuit 10 is connected through a decode line C2 to a latch circuit 11 supplied with an internal clock delay skew signal ICLKD2. This latch circuit 12 supplies the mode discriminator signal MODE2 to the internal circuits.
In the operation of the semiconductor memory device 300, the external clock signal CLK is input through the input buffer circuit 1. This input buffer 1 is triggered by an internal clock enable signal ICKE in the same manner as given in the example previously related for semiconductor memory device 200. In this example, the command control signals CSB, ETSB, CASB, WEB are supplied through the input buffer circuits 3-6, synchronized with the rising edge of the internal clock signal ICLKi, and loaded and held by flip-flops D-F/F 8a-8d, respectively.
These now loaded signals are supplied to the command decode circuits 9 and 10. The decoded outputs from these command decode circuits 9 and 10 are supplied to the latch circuits 11 and 12 through the output lines C1 and C2, respectively, and latched with the rising edge pulse of internal clock delay signals ICLKD1 and ICLKD2. The latch circuits 11 and 12 which respectively output the mode discriminator signals MODE1 and MODE2. In this way, the latch circuits function to prevent noise and other interference from intruding into the mode discriminator signal.
A timing chart for this command decode method is shown in FIG. 9. When the external clock enable signal CKE is at H level, the external clock signal CLK from the buffer circuit 1 is valid. The input of command signals (CSG, RASB, CASB, WEB) are input so as to retain the setup time (tSE) and hold time (tHE) versus the external clock signal CLK in the same manner as previously related for the semiconductor memory device 200.
Here, the output lines A1-A4 are delayed and changed versus the command signals, by the time (t0) required to pass through the input buffer circuits 3-6. These signals are latched with the rising edge pulse of internal skew clock signals ICLK1 into flip-flops D-F/F 8a-8d, respectively.
The signal from the output lines C1-C2 change after the time caused by the wiring length from each of the flip-flops D-F/F 8a-8d to the command decode circuits 9 and 10, and the time (t11, t12) required to pass through the command circuits 9 and 10.
These changes in the output lines C1-C2 are latched with the rising edge pulse of internal clock delay signal ICLKD from the delay circuit 7, into the latch circuits 11 and 12.
The internal clock delay signal ICKLD has a skew factor just as the internal clock signal ICLK does, so these internal clock delay signals ICKLD are labeled as internal clock delay skew signals ICLKD1 and 2. The delay time provided by the delay circuit 7 is set to wait from the rise pulse of the internal clock signal ICLK by the change time (t21) in the output lines C1-C2, so that the internal clock delay signals ICLKD rise.
The sum (internal window width) of the setup time (tSI) and hold time (tHI) for the chip in the above-mentioned semiconductor memory devices 200 and 300 must be considered. In the case of the timing chart for the semiconductor memory device 200 as shown in FIG. 7 considered for simplicity as,
t11>t12, .DELTA.t (skew of ICLK2 versus ICLK1) and assuming EQU tSE+tHE=tSI+tHI+(t11-t12)+.DELTA.t (1)
then the problem occurs of the internal window width becoming smaller, {by the amount (t11-t12)+.DELTA.t} than the external window width.
Further, when the skew width, .DELTA.t=ICLK in the timing chart for the semiconductor memory device 200 as shown in FIG. 9 then, EQU tSE+tHE=tSI+tHI+.DELTA.t (2)
so that the problem occurs of the internal window width becoming smaller than the external window by an amount equal to the time .DELTA.t. In this case, this reduction of internal window width versus external window width was small enough to be ignored in conventional specifications for setup and hold times. However, with the appearance of high speed DRAM devices in recent years having high speed operation in excess of 100 MHz, the window width becomes narrower and narrower due to the smaller clock period. Consequently in the specifications for the newer high speed devices, the ratio of a reduced window versus the other window becomes a problem that cannot be ignored.

Semiconductor memory device for shortening the set up time and hold time of control signals in synchronous DRAM


The present invention relates to the field of three-dimensional face modeling, and provides a three-dimensional real face modeling method and a three-dimensional real face camera system. The three-dimensional real face modeling method includes the following steps: 1, projecting structured light to a target face, and taking a photo to acquire facial three-dimensional geometric data; 2, acquiring facial skin chroma data and brightness data; 3, triangulating the facial three-dimensional geometric data; 4, acquiring patch chroma data corresponding to each of triangular patch regions; 5, performing interpolation calculation to acquire patch brightness data corresponding to each of the triangular patch regions; and 6, calculating a reflectivity of a facial skin region corresponding to each of pixel points. The three-dimensional real face camera system includes: a standard light source, a control and calculation module and a three-dimensional portrait acquisition unit. By the adoption of the three-dimensional real face modeling method and system, three-dimensional real face information unrelated to a modeling device for three-dimensional modeling and an illumination environment on a modeling site can be acquired.

Biometrics recognition technology has been developed rapidly in recent years. Many technologies such as fingerprint recognition, iris recognition, palmprint recognition and face recognition have been relatively matured. Particularly, the face recognition technology has attracted extensive attention due to its wide adaptability and non-contact characteristics. At present, most of the matured face recognition technologies are based on a two-dimensional face recognition technology, which is greatly limited by the influence of angle, illumination, age, expression, decorations and the like.
A three-dimensional face recognition technology can greatly reduce the limitation of environment, posture, expression and other factors on the face recognition rate due to the combination of three-dimensional face structure information and facial texture features. The premise of rapid development and application of the three-dimensional face recognition technology is the acquisition of three-dimensional face data. A pure three-dimensional portrait model only contains facial geometric shape data, and does not contain material-related skin property information reflecting a facial skin color, a reflectivity and the like, and such incomplete information in the application will limit its using in certain fields, which restrains the application of the three-dimensional face recognition technology in some fields. In order to give full play to the advantages of the three-dimensional face recognition technology and adapt to a variety of application scenes and technical solutions, the three-dimensional face data should have the following characteristics: 180-degree face range from a left ear to a right ear or front face range, high-precision three-dimensional point cloud and containing of facial skin property information. The facial skin property information is composed of skin surface chroma information and skin surface reflection characteristics. At the present, three-dimensional modeling products on the market are not aimed at three-dimensional face modeling applications, and have defects or shortcomings such as low precision, low shooting speed, small face region and failure of measuring the facial skin property information, which are difficult to be promoted and applied on a large scale. At present, it has not been reported that three-dimensional real face cameras have the characteristics of high speed, high precision, accurate facial skin property information and the like. In response to this demand, researchers have researched and developed a three-dimensional real face modeling method and a three-dimensional face camera system.

Three-dimensional real face modeling method and three-dimensional real face camera system


An ansate oral prophylaxis device includes a hand engageable shaft having a bristle carrying head at one end. The head is configured for oral anti-carries and periodontal prophylaxis with simultaneous bristle contact against all accessible tooth and adjacent gingival surfaces on each reciprocal stroke. The head is configured with a spine and pair of generally planar side panels, each lying in a plane approximately 45.degree. from the plane of the spine. Bristles project perpendicularly from the spine for engagement against occlusal tooth surfaces, while bristles project perpendicularly from the side panels for engagement against buccal and lingual tooth side walls, gingival surfaces and tooth surfaces beneath the gum line. To assure softer bristle contact with gingival surfaces, the bristles of the side panels are progressively tapered in length with the longest bristles being furthest from the spine and the shortest bristles being adjacent the spine. The planes of the side panel bristle ends intersect at approximately 30.degree..

1. Field of the Invention
This invention relates generally to oral prophylactic and more particularly to a brush configured for simultaneous bristle engagement with occlusal, buccal and lingual tooth surfaces as well as adjacent gingival tissue.
2. Related History
The prior patents of the Applicant herein, patent Des. 273,153 issued Mar. 27, 1984 and patent Des. 315,450, issued Mar. 19, 1991 disclosed oral prophylactic configured with bristles for simultaneous engagement with occlusal, buccal and lingual tooth surfaces. Both of the aforementioned patents illustrated a toothbrush having a spine with bristles for contacting occlusal tooth surfaces and a pair of opposed side panels, each of which included bristles arrayed substantially along parallel axes which were also perpendicular to the axis of the spine.
Such arrangement assured simultaneous bristle contact with occlusal, buccal and lingual tooth surfaces, provided the brush head size, bristle length and gap between the opposed side panel bristle ends were anatomically configured to conform with the oral cavity and tooth dimensions of the intended user.
Brushes of the configuration shown in patent Des. 315,450 have been anatomically dimensioned for and commercialized in conjunction with the market comprising young children. Among the factors which influenced consumer acceptance were parental concerns that their children were not properly brushing. Such brush configuration assured thorough cleansing with the parent or child only required to employ a simple reciprocal stroke without twisting or rotating the brush.
It has been found, particularly with respect to adults, that improper brushing techniques lead to various maladies, not only relating to tooth structure, e.g. tooth decay, but, also periodontal diseases. Further, it was difficult to assure beneficial bristle contact against gingival tissue with the bristle configurations shown in patents Des. 315,450 and Des. 273,153.
When bristles of uniform length were utilized in toothbrushes configured for simultaneous engagement with multiple tooth and gingival surfaces, the stiffness of bristles contacting gingival tissue often resulted in trauma and concomitant bleeding. When soft bristles were employed, the requisite stiffness for tooth surface cleansing was not attainable.
It has been proposed in patent Des. 289,230 to employ bristles of different lengths in a single multi-sided brush, such construction required costly and difficult angular mounting of bristle bundles and commercial manufacture of such brush was apparently impractical. Other approaches required an awkward axial rotative manipulation in order to cleanse teeth such as exemplified by the toothbrush disclosed in U.S. Pat. No. 4,131,967 which comprised a brush head having two opposed sides projecting from a yoke.

Toothbrush for cleaning multiple sides of teeth


A soft, removable, protective restraint device for the arm or leg of a person, comprising:. (a) at least two bands including a wrist band having a circumference slightly greater than that of the person's wrist area, and an upper arm band having a circumference slightly greater than that of the person's upper arm area; PA1 (b) a plurality of lock and loop portions for removably fastening one end of each band to an opposite end of the same band; PA1 (c) between about one and ten longitudinally oriented bars attached at each end to the bands; each bar being parallel to the other and evenly spaced; PA1 (d) an equal number of lightweight stiffening members; each bar comprising an enclosed stiffening member; and PA1 (e) a soft, sturdy, washable fabric substantially covering the device is provided.. The restraint device has an open position and a cylindrical closed position when the loop portions are fastened to the corresponding lock portions on each band; and wherein the restraint device in the closed position fits comfortably but snugly in a generally cylindrical configuration around an arm or leg of the person.

Having a seriously ill or injured child is one of the great fears of parenthood. Seeing one's offspring, particularly an infant, laying in a hospital bed covered in bandages and surrounded by tubing and medical equipment is a terrible experience. One small thing that can be done to ease the discomfort of such pediatric patients is to create a restraint device which is effective, yet not oppressive in presence or appearance.
Restraints are often placed by hospital personnel on a pediatric or geriatric patient's arms to prevent him or her from pulling at the bandages and surrounding equipment. Many currently available restraint devices cover most of the patient's arm, and are stiff and uncomfortable. A child's skin underneath such devices often becomes sweaty and itchy. Some currently available one-piece restraints are generally cylindrical and have the same circumference at the top and bottom of the device, so the child's arm movements work the device off at the wrist. For that reason, some available two-arm devices have an uncomfortable strap attached to the tops of two cast-like arm restraints which extend over the wearer's shoulders and behind his or her neck. Some cast-like restraint devices extend down over the wearer's hand and have a very uncomfortable thumb hole. Some current restraint devices have string ties which are fastened around the device on the arm. These ties often loosen or untie and must frequently be retied. Many available devices are bulky and hard to put on the child. There is also a need for a restraint device that is easy to put on and take off, and does not slide around on the small arm of a baby. The device of the present invention solves these problems.
The present device is particularly well-suited for use on an infant's arms after cranial, facial or upper body surgery. The device prevents the infant's arm from bending at the elbow. It is particularly useful for infants who have had cleft lip and palate operations to keep the infant or older child from touching or inadvertently pulling out stitches, bandages, oxygen tubes, intravenous devices, and other medical aids. It also keeps the baby from putting objects into its mouth. It may be used for several days or weeks after surgery, and can be removed periodically for cleaning the device or the child. It can also be used on patients who have had eye surgery, tracheotomies, or who have burns on the head, face or upper body, to reduce infections and prevent removal of tubes or bandages.
In addition to post-surgical use, the present device can be used in intensive care units for restraining the arms of injured or ill patients, particularly those who are confused or delirious. It can be used in emergency situations for restricting the movement of frightened children with, for example, foreign items lodged in their eye or nose, or for flushing of small children's ears. The present device can be employed to restrict movement of a sprained or strained knee or elbow, or an arm or leg that has been otherwise cut or injured, for in- or out-patients of various ages. It can be used in the course of physical therapy for supporting the bones and muscles of the legs or arms, or to brace a young child's legs to assist in walking. It can be used to restrain arm or leg movement while X-rays are being taken. It can be used on the arms of children to restrict scratching of rashes such as chicken pox, thus minimizing scarring, or to help prevent thumb-sucking. With the addition of ties or loops on the wrist band, this device can be used on the arms and/or legs of a delirious, senile, or semi-conscious person for restraining him or her in bed in, for example, a hospital, nursing home, hospice or private home.


An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.

1. Field of the Invention
The present invention relates generally to an electrostatic discharge (ESD) device. More particularly, the present invention relates to an ESD device with a parasitic SCR structure having a controllable trigger voltage.
2. Description of Related Art
ESD devices have been widely used in integrated circuits to prevent damages caused by static electricity. Generally, the ESD device occupies a considerable chip area on which an integrated circuit (IC) is fabricated, which accordingly increases manufacturing cost. Furthermore, due to the transmission characteristic of conducting wires and generally a large dimension of the ESD device, current flowing through the ESD device is not uniform, which may affect the electric characteristics, such as a breakdown voltage of the ESD device.
The ESD devices with parasitic SCR structure are applied in many applications. How to achieve a stable and controllable trigger voltage of the parasitic SCR is still a main issue in the industry field.
Therefore, the ESD device having a controllable trigger voltage and improved electric characteristics is desired.

Electrostatic discharge device having controllable trigger voltage


A method of treatment of a fleon gas consisting only of carbon and fluorine is provided, wherein the fleon gas is exposed to a plasma to decompose and chemically activate the fleon gas. The fleon gas having been chemically activated is then made into contact with a reactant to form a reaction product.

The present invention relates to a method and an apparatus for treatment of exhaust gas having been generated in manufacturing processes for semiconductor devices, and more particularly to a method and an apparatus for treatment of unreacted PFC gas to avoid direct discharge of the unreacted PFC gas to an atmosphere.
In the semiconductor device manufacturing processes, a PFC gas or a freon gas comprising carbon and fluorine has been used. The PFC gas has been used, for example, as an etching gas in the dry etching process or a cleaning gas in the plasma CVD apparatus. The PFC gas is much higher in global warming power coefficient (GWP) by about a few thousands than that of carbon dioxide, for which reason if the used PFC gas is discharged directly to atmosphere, then a certain influence on the global atmospheric system is concerned. It has been required to control the direct discharge of the used PFC gas to the atmosphere.
In the conventional dry etching apparatus, PFC gases such as CF.sub.4, C.sub.2 F.sub.6 are used as etching gases. As illustrated in FIG. 1; a PFC gas is introduced as a source gas into a dry etching apparatus 1 before the PFC gas PFC gas is then decomposed by a radio frequency plasma whereby not only etching species or etchants but also unreacted PFC gas and etching reaction products are generated. The etching species or etchants are used for the dry etching process. On the other hand, the unreacted PFC gas and reaction products are discharged by a pump 2 from a reaction chamber in the dry etching apparatus 1. The discharged unreacted PFC gas and etching reaction products are fed to a removal apparatus 3 for removing the reaction products.
If the C.sub.2 F.sub.6 gas is used as an etching gas for etching a silicon oxide film, then etching reaction gases such as SiF.sub.4, COF.sub.2 are generated. In order to remove such undesired etching reaction gases, it is effective to use an adsorption removal method by use of adsorbents such as zeolite or activated carbon for removal thereof. Since, however, the unreacted PFC gas is chemically stable, the unreacted PFC gas is not adsorbed onto the adsorbents such as zeolite or activated carbon, for which reason conventionally the unreacted PFC gas is obliged to be discharged directly.
The plasma etching apparatus used for the manufacturing processes of the semiconductor device has a low decomposition ratio of 20%, for which reason the majority of the introduced PFC gas is discharged as the unreacted PFC gas. As described above, since the unreacted PFC gas is chemically stable, it is difficult to adsorb the unreacted PFC gas onto the adsorbent, for which reason the unreacted PFC gas is directly discharged to the atmosphere without any treatment or any process. The discharge of the unreacted PFC gas raises the serious problem with providing a great deal of influence to the global atmospheric system. In order to prevent this problem, an additional apparatus is required for compulsory treatment of the unreacted PFC gas to avoid direct discharge of the unreacted PFC gas into the atmosphere.
In order to decompose the unreacted PFC gas, it has been proposed to practice a combustion decomposition method, wherein the unreacted PFC gas is heated up to a high temperature of 1000.degree. C.-1200.degree. C. It has been concerned that this heat treatment at such high temperature may raise another serious problem with safety.
In the above circumstances, it has been required to develop a novel method and apparatus for treatment of the unreacted PFC gas to avoid direct discharge thereof to an atmosphere with safety and without substantial influence to a global atmospheric system.

Method and apparatus for treatment of freon gas


A system and method are provided for managing information in a wireless network. The information can be utilized during handoff of a client from an access point to an access point. The method includes a first frame being generated and transmitted by the client to the access point through the access point. The frame includes a request for the information, wherein the information includes at least a target beacon transmission time (TBTT) of the access point. The method also includes the client receiving a second frame containing the information from the access point through the access point.

In wireless networks, a handoff usually occurs when a user of a client moves from a current cell to another cell. Examples of the client include a laptop, a personal digital assistant (PDA), a mobile phone, and the like. Each cell is serviced by at least one access point. Handoff refers to the process of transferring an ongoing call or data session from a channel connected to the current cell to a channel connected to another cell. It is desirable to have low interference and a smooth transfer during the handoff. In order to achieve this, the time span of the handoff should be minimized.
The handoff process involves scanning access points that are adjacent to a first access point, while the client is associated with the first access point. This scanning involves analyzing the beacon frames broadcast by each access point adjacent to the first access point. These beacon frames are broadcast regularly by all the access points. The time at which an access point broadcasts the beacon frame is referred to as the target beacon transmission time (TBTT). Further, each beacon frame is broadcast after regular intervals called beacon intervals. Consider a case of a handoff of the client to a second access point. The scanning process can be hastened if the client is aware of the next target beacon transmission time of the second access point. The current TBTT and the beacon interval can be used to predict the next TBTT.
The scanning is followed by the authentication of the client by the second access point. The authentication server authenticates the client. This authentication is usually performed by using an Authentication, Authorizing and Accounting (AAA) protocol such as, for instance, Remote Authentication Dial-In Service (also known as the RADIUS protocol) as currently defined in Internet Engineering Task Force (IETF) Request for Comments (RFCs) 2865 and 2866. This is followed by a 4-way handshake between the client and the second access point.
Two known methods exist for collecting the TBTT and the beacon interval of access points of interest. The first method is mentioned above, which is by scanning the beacon frame of each access point adjacent to the first access point separately. However, a particular shortcoming of this method is that often, some of the access points adjacent to the first access point are hidden. One reason for an access point being hidden is the presence of an intercepting infrastructure such as a building. In such a scenario, the client is not able to receive the beacon frames of the hidden access points and is, therefore, unable to scan such beacon frames to determine the TBTT and beacon interval for the hidden access point.
The other method for learning the TBTT and the beacon interval is by using Institute of Electrical and Electronics Engineers (IEEE) standard 802.11k neighbor maps. Neighbor maps comprise a list of access points adjacent to the first access point, and their target beacon transmission times and beacon intervals. However, a shortcoming of this method is that it does not account for the effects of clock drifting. Clock drifting causes the TBTTs and the beacon intervals to change, thereby, making it difficult to determine whether the TBTTs and the beacon intervals recited in the neighbor maps are current.
In light of the above discussion, there is a need for a method for learning the TBTT and the beacon interval more efficiently.

Method and a system for managing information in a wireless network


A solid electrolytic capacitor of the present invention includes an anode element made of a sintered body of a valve-action metal; a dielectric coating, a solid electrolyte layer, and a cathode lead layer, sequentially formed on a surface of the anode element; and an anode lead member made of a conductive metal projecting from the anode element, the anode lead member having a base end thereof embedded in the anode element, the base end being formed such that a cross section thereof perpendicular to a direction extending inwardly of the anode element has a contour with four rounded rectangular corners.

1. Field of the Invention
The present invention relates to a solid electrolytic capacitor including an anode element made of a sintered body of a valve-action metal and an anode lead member projecting from the anode element, and to a manufacturing method therefor.
2. Description of Related Art
A solid electrolytic capacitor having a structure shown in FIG. 9 has been conventionally known. The solid electrolytic capacitor includes an anode element 31 made of a sintered body of powder of a valve-action metal (tantalum, niobium, titanium, aluminum, etc.). Sequentially formed on a surface of the anode element 31 are a dielectric coating 33 made by oxidizing the anode element surface, a solid electrolyte layer 34 made of a conductive inorganic material such as manganese dioxide or a conductive organic material such as TCNQ complex salt, a conductive polymer, etc., and a cathode lead layer 35 made of a carbon layer, silver layer, etc. An anode lead member 26 made of a conductive metal projects from the anode element 31 in one direction. As shown in FIG. 10, the anode lead member 26 is formed in the form of a flat quadrangular prism with a rectangular cross-sectional shape, and has a base end thereof embedded in the anode element 31.
As shown in FIG. 9, an anode lead frame 40 is connected to the anode lead member 26, while a cathode lead frame 41 is connected to the cathode lead layer 35 through a conductive adhesive 36. A periphery of the anode element 31 is coated and sealed by an enclosure resin layer 37 made of epoxy resin or the like. The anode lead frame 40 and cathode lead frame 41 are partly exposed from the enclosure resin layer 37.
As shown in FIG. 10, the anode lead member 26 formed in the form of a flat quadrangular prism with a rectangular cross-sectional shape can provide a larger joint area between the anode lead member 26 and the powder of the valve-action metal of the anode element 31 than a cylindrical anode lead member with a circular cross-sectional shape. Therefore, a resistance is reduced at a joint point between the anode lead member 26 and the valve-action metal powder of the anode element 31 to lower an equivalent series resistance (ESR). Furthermore, a large current can flow through the solid electrolytic capacitor by increasing the joint area between the anode lead member 26 and the valve-action metal powder of the anode element 31 (see JP 3535014, B).
The anode element 31 having the anode lead member 26 projected therefrom as shown in FIG. 10 is prepared by vacuum-sintering a molding of the valve-action metal powder having the base end of the anode lead member 26 embedded therein. However, the anode element 31 having the anode lead member 26 projected therefrom as shown in FIG. 10 has a problem of, as shown in FIG. 11, occurrence of a crack 30 from a boundary between the anode lead member 26 and anode element 31, in particular, from corners of the anode lead member 26 in a face 32 of the anode element 31 having the anode lead member 26 projected therefrom after the preparation of the anode element 31 by vacuum-sintering the molding of the valve-action metal powder.
Even if the anode element 31 and anode lead member 26 are of the same material, the anode element 31 can have a smaller density than the anode lead member 26, such that the anode element 31 can have a larger linear expansion coefficient than the anode lead member 26 due to the difference in density between the anode element 31 and anode lead member 26. This causes the anode element 31 to contract more greatly than the anode lead member 26 when the anode element 31 is cooled after the molding of the valve-action metal powder is vacuum-sintering to prepare the anode element 31. The thermal stress concentrates especially on the corners of the anode lead member 26 of the anode element 31. This is probably the cause of the occurrence of the crack 30.
The occurrence of the above-described crack 30 at the anode element 31 increases a leak current at the anode element 31, and therefore degrades the performance of the solid electrolytic capacitor to lower the yield.

Solid electrolytic capacitor and manufacturing method therefor


An exemplary embodiment of system, computer-accessible medium and method for comparing a first genome to a second genome. For example, a first genome may be compared to a second genome by building a first library for the first genome and a second library for the second genome, providing a plurality of matches between elements in the first library common to elements in the second library, ranking each match to determine a likelihood of similarity between the common elements in the first and second libraries; and associating matches having a predetermined likelihood. The association may be performed efficiently by a stable marriage procedure.

In the past decade, many genome projects have produced complete genomes for increasingly many organisms. Since 1999 many tools have proven effective in aligning large genomic sequences of two closely related organisms. Such tools include: MUMmer, which is described, e.g., in Delcher et al., "Alignment of whole genomes," Nucleic Acids Res., pages 2369-2376 (1999); GLASS, which is described, e.g., in Pachter et al., "Human and mouse gene structure: Comparative analysis and application to exon prediction," Genome Res., pages 50-958 (2000); AVID, which is described, e.g., in Bray et al., "Avid: A global alignment program," Genome Res., pages 97-102 (2003); DIALIGN, which is described, e.g., in Morgenstern et al., "Exon discovery by genomic sequence alignment," Bioinformatics, (6):777-787 (2002); LAGAN, which is described, e.g., in Brudno et al., "Lagan and multi-lagan: Efficient tools for large-scale multiple alignment of genomic dna," Genome Res., pages 721-731 (2003); BLASTZ, which is described, e.g., in Schwartz et al., "Human-mouse alignments with blastz," Genome Res., page 103-107 (2003); and BLAT, which is described, e.g., in Kent, "Blat—the blast-like alignment tool," Genome Res., (4):656-664 (2002).
Characteristics common to many of these programs include: (i) an assumption that conserved regions of the sequences being aligned appear in the same order and orientation, which may be particularly likely for closely related organisms; (ii) the construction of tables of scores for matches and mismatches between amino acids or nucleotides, which may incorporate penalties for insertions or deletions, and which may be used to obtain mathematically 'optimal' alignments; and (iii) the search for exact or spaced exact matches (e.g., in local alignment programs), and the extension of local similarities in both directions in passes directed by specified scoring functions.
However, certain shortcomings may limit the use of many of these programs. First, genomic order and orientation may not be conserved between species of interest. Second, the scoring matrix (e.g., a PAM or a BLOSUM matrix) which may be most appropriate for aligning a set of sequences should preferably be determined by the level of relatedness of sequences. Hence, a pre-estimate of a percentage of similarity between two genomes may be required to choose a proper scoring matrix. Third, a variation in the rate of evolution across the genome can make it impractical to pick a universal scoring matrix or a set of gap costs as described, e.g., in Frazer et al., "Cross-species sequence comparisons: A review of methods and available resources," Genome Res., pages 1-12 (2003). Finally, when using a "match and extend" strategy, many local procedures can pay a steep cost in extending short matches in both directions.
Thus, comparing vertebrate genomes can require efficient cross-species sequence alignment programs. It may be desirable to have a system and method for cross-species genome alignment which reduces the above-mentioned deficiencies.

System and method for rapid searching of highly similar protein-coding sequences using bipartite graph matching