A method of treating Influenza A is disclosed. The method includes the step of administering a pharmaceutical composition including an oligonucleotide complementary to a corresponding segment of the nucleotide sequence of microRNA-1290 (miR-1290) (SEQ ID NO: 1) to a subject suffering from Influenza A, wherein at least one of the nucleotides in the oligonucleotide is Thymidine phosphate.

Influenza A virus is a virus with high morbidity, high mortality and high contagion. Influenza A virus can use birds or pigs as reservoir hosts in order to continuously spread and exist among different species, produce antigenic shifts through genetic reassortment, and overcome the species barrier to infect humans. Moreover, antigenic drifts caused by quick and unpredictable mutations of the influenza A virus causes people who have been infected with the influenza A virus to be infected again. Because of these two antigenic evolutionary mechanisms, an epidemic or pandemic influenza occurs every few years or decades. Millions of people are infected every year, causing a tremendous burden to health and the economy.
A microRNA (abbreviated miRNA) is a small RNA molecule containing about 22 nucleotides. After transcription, a primary miRNA (pri-miRNA) is cleaved by RNase III enzyme Drosha in the nucleus, and RNase III enzyme Drosha can cleave the double stranded pri-miRNA near the stem-loop and produce a precursor-miRNA (pre-miRNA) having a stem-loop structure and 60-70 nucleotides. Pre-miRNA is exported out of the nucleus by Exportin-5. In the cytoplasm, the pre-miRNA hairpin is cleaved by the RNase III enzyme Dicer, yielding a miRNA:miRNA* duplex about 22 nucleotides in length, and one strand of the miRNA:miRNA* duplex is incorporated into the RNA-induced silencing complex (RISC). The function of the RISC is protein translation inhibition.
In recent years, substantial literature has indicated that miRNA can regulate viral replication. However, whether there exists a species-specific miRNA which can regulate influenza A viral replication remains unknown.


An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element B. In response to a single instruction, the circuit performs the comparison and outputs a condition field of at least one bits when the comparison of A and B is TRUE, or else the circuit outputs the ones-complement of the condition field when the comparison of A and B is FALSE. The circuit may be used in conjunction with a sequence of instructions to select bits from a first data element and bits from a second data element using the one or more condition field bits.

1. Field of the Invention
The invention relates to the field of microprocessors, and more particularly to instructions for evaluating conditions and moving data.
2. Art Background
Computer programs are comprised of multiple instructions which are decoded and executed by the microprocessor. When the program is "run", the microprocessor begins executing the instructions in the program in the sequence in which they appear. Not all of the instructions in the program are typically executed when the program is run. Rather, some instructions are conditional, that is, whether or not they are executed depends upon the outcome of a previous instruction in the program. That is, the microprocessor may skip the execution of some instructions if certain conditions are not met while the program is running.
Table 1a shows both a set of high-level instructions and a set of assembly-level instructions for implementing a conditional statement that moves data to a destination location inside a computer system. The instructions on the left side of the table are from a high-level programming language, in this example C language. The instructions are stored in a machine readable medium, such as computer memory. A high-level language compiler, such as a C language compiler, is used to compile the high-level instructions into assembly instructions compatible with the particular computer system on which the instructions are targeted to execute. After compilation, each high-level instruction typically corresponds to one or more assembly-level instructions, although it is possible for one assembly instruction to correspond to multiple high-level instructions. This process is well known in the art of microprocessors. In Table 1a, letters represent program variables which may be kept in registers within the microprocessor or in memory.
TABLE 1a ______________________________________ High-Level Instructions Assembly-Level Instructions ______________________________________ IF (Y>5) 100 CMP R1=(Y>5) A=2 110 CJMP FALSE R1, J1 ELSE 120 MOV A, 2 A=9 130 JMP J2 140 J1: MOV A, 9 150 J2: ______________________________________
As shown by the assembly-level instructions in Table 1a, a compare instruction 100 is executed to determine if the condition y>5 is TRUE. Following the compare instruction, a conditional jump instruction 110 is executed. If the condition y>5 evaluates to a value of logical TRUE, the conditional jump instruction 110 does not cause a jump, and a MOV instruction 120 is executed. The MOV instruction 120 moves the value 2 to the variable A. Upon completion of MOV instruction 120, a jump instruction 130 is executed to jump over a MOV instruction 140 to an address 150. If the condition Y>5 does not evaluate to logical TRUE, the conditional jump instruction 110 causes a jump to the MOV instruction 140. The MOV instruction 140 moves the value 9 to the variable A. Note that the implementation of what defines "TRUE" in a computer system will vary among computer systems, but typically involves the setting of a one or more bits in a register.
TABLE 1b ______________________________________ High-Level Instructions Assembly-Level Instructions ______________________________________ IF (Y>5) 155 CMP R1=(Y>5) A=2 156 CMOV R1, A=2 ELSE 157 CMOV !R1, A=9 A=9 ______________________________________
Table 1B shows both a set of high-level instructions and a set of assembly-level instructions for implementing a conditional move in a computer system. In Table 1b, as in Table 1a, letters represent program variables which may be kept in registers within the microprocessor or in memory. As shown by the assembly-level instructions in Table 1b, a compare instruction 155 is executed to determine if the condition y>5 is TRUE. Following the compare instruction, a conditional move instruction 156 is executed. If the condition y>5 evaluates to a value of logical TRUE, the conditional move instruction 156 causes the value 2 to be moved to the variable A. Upon completion of conditional move instruction 156, a conditional move instruction 157 is executed. Conditional move instruction 157 evaluates the complement of the value in register R1. If the condition Y>5 does not evaluate to logical TRUE, the conditional move instruction 157 causes the value 9 to be moved to the variable A.
In a pipelined computer, multiple functional units simultaneously execute multiple instructions from a computer program, leading to substantial performance increases. Each instruction in a typical pipelined computer goes through four stages: fetch, decode, execute, and writeback. In the fetch stage, the processor fetches an instruction from an instruction memory, which can be a cache memory, main RAM, flash memory, or other type of machine-readable medium. During the decode stage, the instruction is partially or fully decoded to determine the type of execution unit required to complete the instruction, and the instruction's operands are read from registers. During the execution stage, simple integer arithmetic and logic operations generally complete in one clock cycle on many pipelined processors. During the writeback stage the results of the instruction's execution are written back to registers or are written to other places in computer memory, such as cache memory or main RAM.
A pipelined computer operates most efficiently when the instructions are executed in the sequence in which they appear in memory. Unfortunately, conditional statements and the branch instructions they produce constitute a large portion of the executed instructions in a computer program. When a branch instruction is executed, execution continues either with the next sequential instruction, or with an instruction at a specified "target" address. A branch instruction is said to be "Taken" if execution continues at the target address, or "Not Taken" if execution continues with the next sequential instruction in memory. For example, in Table 1a the target of the branch instruction 130 is the address J2 150.
A branch instruction is either unconditional, meaning the branch is taken every time the instruction is executed, or conditional, meaning the branch is taken or not depending upon a condition. The instructions to execute following a conditional branch are not known with certainty until the condition upon which the branch depends is resolved. Prefetching and executing the instructions at the target address of the branch can lead to a significant performance hit when the branch is "Not Taken". Branches may also be forward, meaning the target address is greater than the address of the branch, or backward, meaning the target address is less than the address of the branch.
Conditional branch instructions such as the instruction 110 in Table 1a typically use a condition field. The value of this field is typically set by the compare instruction and indicates whether the condition evaluated by the compare instruction evaluated to TRUE or FALSE. Subsequent instructions examine the field to determine whether the condition evaluated TRUE or FALSE. For example, a subsequent jump instruction (e.g. CJMP instruction 110 in Table 1a) might examine the condition field and perform a jump only if the bits of the condition field are set. Otherwise, program execution continues with the next instruction after the jump instruction in the execution sequence (e.g. MOV instruction 120 in Table 1a). Note that the computer architecture may be defined to store the condition field in either a general purpose register or in a special purpose register such as a status register or flags register. The architecture may also be defined to incorporate the function of the compare instruction and the branch instruction into a single compare-and-branch instruction which does not make reference to any condition field. The present invention applies equally well to these alternative embodiments.
As stated above, branch instructions may cause a non-sequential change in the fetching of instructions, i.e. the next instruction to be executed may not sequentially follow the previously executed instruction. The direction of a branch instruction is not known until the branch is executed which typically occurs in the execute stage in a pipelined processor. While waiting for the branch instruction to reach the execute stage the intervening stages between the fetch stage and the execute stage are filled based upon a prediction as to the direction of the branch instruction. When branch direction is not correctly predicted, any fetched and partially executed instructions resulting from the incorrect prediction must be flushed from the pipeline. Even an incorrect prediction rate of 5 percent results in a substantial loss in performance due to the number of instructions incorrectly fetched/partially executed in reliance on the wrong prediction. Further delays are incurred while the processor fetches the correct instructions to execute following the branch. It is therefor highly desirable in pipelined computers to eliminate as many branch instructions as possible from the instructions of a computer program.
Another phenomenon which can degrade the performance of pipelined computers is data dependencies. A data dependency exists between two instructions if the execution of one depends upon the results of executing the other. Each instruction has the potential to stall later instructions that depend on it. The following table shows how data dependencies can cause pipeline stalls.
TABLE 1c ______________________________________ 160 ADD r1, r2, r3 161 LOAD [r3], r6 162 AND r5,r8,r7 163 ADD r6,r7,r1 164 SUB r3,r4,r5 ______________________________________
The instructions in Table 1c have an opcode, followed by two or three registers. Instructions that use three registers have two source registers followed by a destination register. An instruction using two registers has a source register followed by a destination register. When a register is enclosed in brackets, then the register is used to address memory. For example, the instruction LOAD [r3], r6 161 loads register r6 with the contents of the memory address in register r3.
In Table 1c, the ADD instruction 163 has a dependency on the preceding LOAD instruction 161. The dependency is on the contents of register r6, which the LOAD instruction 161 fills with the contents of the memory address specified in r3. In this example, the LOAD instruction 161 has not completed execution by the time the ADD instruction 163 is ready to execute, because the LOAD instruction 161 takes, for example, four clock cycles to complete. The ADD instruction 163 is ready to execute only two clock cycles after the LOAD instruction 161 begins execution. The ADD instruction 163 will stall execution in the pipeline for two clock cycles, until the LOAD instruction 161 updates the contents of register r6 so that the ADD instruction 163 can add the contents of register r6 with the contents of register r7. Note that the SUB instruction 164 following the ADD instruction 163 does not depend on the completion of the LOAD instruction 161, nor on the completion of the ADD instruction 163. Therefor, the SUB instruction 164 can be executed while waiting for the LOAD instruction 161 to complete.
Out-of-order (OOO) execution can be used to lessen or eliminate the effect of stalls due to instruction dependencies. Upon encountering an instruction that depends on an instruction still in execution, the OOO execution processor checks for later independent instructions in the program and executes these later instructions before the dependent instruction (such as in the case of the SUB instruction 164 in Table 1c). This reduces the impact of execution stalls because the execution of later independent instructions is overlapped with the execution of instructions requiring multiple clocks to complete.
There are three types of data dependencies which can occur in computer programs: read-after-write (RAW) dependencies, write-after-write (WAW) dependencies, and write-after-read (WAR) dependencies. RAW dependencies occur when an instruction requires the result of a previous instruction. WAW dependencies occur when two instructions write the same register and therefore the writes must occur in the order specified by the program to guarantee subsequent instructions receive the correct value. WAR dependencies occur when an instruction writes the same register that was read by a previous instruction, and therefore the write must occur after the read to guarantee that the correct value is read. Table 1d illustrates the three types of data dependencies.
TABLE 1d ______________________________________ 180 ADD r1, r2, r3 190 SUB r3, r4, r5 192 SHR r6, r7, r4 194 OR r8, r9, r3 ______________________________________
In Table 1d, the ADD instruction 180 writes R3 with the sum of the values in R1 and R2. Register R3 is subsequently read by the SUB instruction 190. A RAW dependency exists that prevents the SUB instruction 190 from being executed prior to the ADD instruction 180. The SUB instruction 190 reads register R4 which is subsequently written by the SHR instruction 192. A WAR dependency exists that prevents the SHR instruction 192 from being executed prior to the SUB instruction 190 even though the SHR instruction 192 does not use the result of the SUB instruction 190. Finally, the ADD instruction 180 writes register R3 which is subsequently written by the OR instruction 194. A WAW dependency exists that prevents the OR instruction 194 from being executed prior to the ADD instruction 180, even though the OR instruction 194 does not use the result of the ADD instruction 180.
Due to the limited numbers of registers in a processor, the same register will typically be written by multiple instructions during execution of a single program. In Table 1d above, because the OR instruction 194 writes register R3, a WAW dependency is created with the ADD instruction 180. If the OR instruction 194 uses a register other than R3 as a destination, for example register R10, then the WAW dependency is eliminated. The same reasoning applies to the SHR instruction 192; if the SHR instruction 192 uses a register other than R4 as a destination, then the WAR dependency with the SUB instruction 192 is eliminated. Thus WAR and WAW dependencies are "artificial" dependencies created by multiple instructions using the same register as a destination. Although impractical, WAR and WAW dependencies could be completely eliminated by constructing a program such that the same register is never written more than once.
A technique known as "register renaming", known in the prior art, can be used to eliminated WAR and WAW dependencies. Register renaming operates by changing the name of the destination register of all instructions from the name assigned by the high level language compiler (typically referred to as virtual registers) to a unique name in another namespace (typically referred to as physical registers). Table 1e depicts the instructions from Table 1d both before and after register renaming.
TABLE 1e ______________________________________ Before Renaming After Renaming ______________________________________ ADD r1, r2, r3 ADD r1, r2, rA SUB r3, r4, r5 SUB rA, r4, rB SHR r6, r7, r4 SHR r6, r7, rC OR r8, r9, r3 OR r8, r9, rD ______________________________________
The virtual register destination of each instruction is renamed to a unique (typically sequential) physical register name (for example rA, rB, etc.) and this new physical name is provided to all subsequent instructions which read the corresponding virtual register. Register renaming is commonly employed in OOO execution processors to eliminate WAR and WAW dependencies and therefore increase the number of independent instructions. Renaming is performed early in the pipeline, prior to execution, so that the instruction issue and execution logic do not see any WAR or WAW dependencies.
In the prior art conditional move (see Table 1b), the destination of the move instruction is conditionally modified, that is, if the condition evaluates to TRUE then the destination is modified, otherwise the destination is not modified. This conditional modification of the destination causes complications in the implementation of register renaming. At the time when register renaming is performed, the result of evaluating the condition is not known, in general, and therefore it is not known whether the destination register of the conditional move will be modified (and should therefore be renamed). Table 1f depicts two versions of an example code sequence, one in which the destination register of the conditional move is renamed and one in which it is not. It will be apparent to those skilled in the art that, in both situations, the name of the source register of the SUB instruction is ambiguous until the condition is resolved. The SUB instruction should read rA if the CMOVE instruction does not perform a move, or the destination of the CMOVE instruction if it does perform a move. Because of this ambiguity, register renaming is made more complex by the prior art conditional move.
TABLE 1f ______________________________________ Original Code CMOVE Renamed CMOVE Not Renamed ______________________________________ ADD r1, r2, r3 ADD r1, r2, rA ADD r1, r2, rA CMOVE r4, r5, r3 CMOVE r4, r5, rB CMOVE r4, r5, r3 SUB r3, r6, r7 SUB r?, r6, rC SUB r?, r6, rC ______________________________________
It is apparent from the preceding discussion that existing schemes for conditionally moving data in a computer system have several disadvantages. In particular, it would be advantageous to conditionally move data in a computer system without the use of conditional branch instruction. It would also be advantageous to conditionally move data without incurring the ambiguities and complexities of the prior art implementations when register renaming and out-of-order execution are involved.

Conditional move using a compare instruction generating a condition field


A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by connecting only one bit line within one sub-array to be connected to a sense amplifier, while the complementary bit line used for the reference voltage of the sense amplifier is selected from an adjacent sub-array, is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.

1. Field of the Invention
This invention relates to Dynamic Random Access Memories (DRAM) and more particularly to support circuitry and circuit configurations for such DRAM arrays for pre-charging bit lines and sensing the charge level representing digital data in a DRAM cell.
2. Description of Related Art
The sensing scheme of folded-bit-line DRAM as described in A. Bellaouar and M. Elmasry, "Low power digital VLSI design--circuits and systems", Kiuwer Academic, Chapter 6, section 6,2.13.1, p.381-383, 1995, and shown in FIGS. 1a and 1b is well known in the art. The pass transistor M.sub.p and the cell capacitor C.sub.c form the memory cells 100. The gates of the pass transistors M.sub.p are connected to the word lines WL.sub.1 115a, WL.sub.2 115b, WL.sub.3 115c, WL.sub.n-2 115d, WL.sub.n-1 115e, and WL.sub.n 115f. The sources of the pass transistors M.sub.p are connected to the primary and complementary bit lines BL 105 and BL 110. When the word line WL.sub.1 115a WL.sub.2 115b, WL.sub.3 115c, WL.sub.n-2 115d, WL.sub.n-1 115e, or WL.sub.n 115f is brought to a voltage level V.sub.h that is higher than the power supply voltage source V.sub.cc by approximately one threshold voltage V.sub.T level of the pass transistor M.sub.p, the pass transistor M.sub.p will be turned on to allow the charging and discharging of the cell capacitance C.sub.c without the voltage drop of the threshold voltage V.sub.T level of the pass transistor M.sub.p.
The N-type metal oxide semiconductor (MOS) transistors M.sub.3 and M.sub.4 form the negative sense amplifier 125a and the P-type MOS transistors M.sub.5 and M.sub.6 form the positive sense amplifier 125b. The negative sense amplifier voltage source 127, which is connected to the ground GND, and the positive sense amplifier voltage source 129, which connected to the power supply voltage source V.sub.cc, provide the necessary voltage to latch the negative sense amplifier 125a and the positive sense amplifier 125b.
The N-type MOS transistors M.sub.7, M.sub.8, and M.sub.9 form the pre-charge and equalization circuit 130. The gates of the MOS transistors M.sub.7, M.sub.8, and M.sub.9 are connected to the pre-charge and equalization control voltage source 132. The drains of the MOS transistors M.sub.7 and M.sub.8 are connected to the reference voltage source V.sub.cc /2 135. The sources of the MOS transistors M.sub.7 and M.sub.8 are connected respectively to the primary and complementary bit lines BL 105 and BL 110.
When the pre-charge and equalization control voltage source 132 is brought to a level sufficient to turn on the MOS transistors M.sub.7, M.sub.8, and M.sub.9, the primary and complementary bit lines BL 105 and BL 110 are pre-charged to the voltage level that is one half the voltage level of the power supply voltage source (V.sub.cc,/2), and the MOS transistor M.sub.9 will equalize any voltage difference between the primary and complementary bit lines BL 105 and BL 110. The pre-charging operation is the charging of the distributed capacitance of each of the primary and complementary bit lines BL 105 and BL 110 as represented by the capacitors CBL.sub.1a 107, CBL.sub.1b 108, CBL.sub.2a 112, CBL.sub.2b 113.
The MOS transistors M.sub.1, M.sub.2, M.sub.10, and M.sub.11 form the isolation circuits 120a and 120b that divide the primary and complementary bit lines BL 105 and BL 110 into segments so as to isolate the memory cells 100 from the negative and positive sense amplifiers 125a and 125b and the pre-charge and equalization circuit 130. The isolation voltage control circuit 122a is attached to the gates of the MOS transistors M.sub.1 and M.sub.2. The isolation voltage control circuit 122b is attached to the gates of the MOS transistors M.sub.10 and M.sub.11. The isolation voltage control circuit 122a and 122b will turn on or turn off the MOS transistors M.sub.1, M.sub.2, M.sub.10, and M.sub.11 selectively to connect the memory cells 100 to the negative and positive sense amplifiers 125a and 125b and the pre-charge and equalization circuit 130. The switches S.sub.1, S.sub.2, S.sub.3, and S.sub.4 are single pole single throw switches that are formed respectively by the MOS transistors M.sub.1, M.sub.2, M.sub.10, and M.sub.11. Typically, the isolation voltage control circuit 122a will turn on switches S.sub.1, S.sub.2. At the same time, the isolation voltage control circuit 122b will turn off switches S.sub.3, and S.sub.4. Or conversely, the isolation voltage control circuit 122a will turn off switches S.sub.1, S.sub.2. At this same time, the isolation voltage control circuit 122b will turn on switches S.sub.3, and S.sub.4. The isolation voltage control circuits 122a and 122b will not turn on or turn off switches S.sub.1 and S.sub.2 and switches S.sub.3, and S.sub.4 simultaneously.
FIG. 2 shows multiple rows of the DRAM cells as arranged in FIGS. 1a and 1b. The read operation begins by the isolation voltage control circuit 122a activating the switches S.sub.1 and S.sub.2 in the isolation circuit 120a to couple the segment of the primary and complementary bit lines BL 105 and BL 110 connected to the sub-array of DRAM cells 150. The isolation voltage control circuit 122b will maintain the switches S.sub.3 and S.sub.4 of the isolation circuit 120b open to isolate the segment of the primary and complementary bit lines BL 105 and BL 110 connected to the sub-array of DRAM cells 155 of the DRAM cells.
The equalization circuit 130 will be activated as described above to pre-charge the bit line capacitances 107 and 112 and equalize any voltage difference between the primary and complementary bit lines BL 105 and BL110.
A word line attached to the DRAM cells 100 that are to be read is activated. For instance, if the DRAM cells 100 attached to word line WL3 115c are to be read, the word line WL3 115c will be brought to a voltage level V.sub.h that is greater than the power supply voltage source by at least the one threshold voltage V.sub.T of the pass transistor M.sub.p of the DRAM cells 100. The voltage level V.sub.h will activate the pass transistor M.sub.p of the DRAM cells 100 of FIGS. 1a and 1b with the voltage drop that is equal to threshold voltage V.sub.T of the pass transistor M.sub.p of the DRAM cells 100. The charge present on the cell capacitor C.sub.c of the DRAM cell 100 of FIGS. 1a and 1b will flow to or from the bit line BL 105.
The latching sense amplifier 125 will be activated to sense the change in voltage on the bit line BL 105 due to the selection of the DRAM cell 100 on the word line WL3 115c. The latching sense amplifier 125 will drive the bit line BL 105 to either the voltage level of the power supply voltage source V.sub.cc or the voltage level of the ground GND. The level of the bit line BL 105 is dependent upon the level of charge present on the cell capacitor C.sub.c of the DRAM cell 100. The latching sense amplifier 125 further will drive the bit line BL 110 to either the voltage level of the power supply voltage source V.sub.cc or the voltage level of the ground GND that is opposite that of the bit line BL 105.
This forcing both primary and complementary bit lines BL 105 and BL 110 to the voltage level difference between the voltage level of the power supply voltage source V.sub.cc and the voltage level of the ground GND is a well known source of noise, as is described in M. Aoki, et al., "A 60 ns 16 Mb CMOS DRAM with a transposed data-line structure", IEEE Trans. Solid-state Circuits, SC-23, No.5, p. 1113, 1988. As semiconductor processing technology has improved, the size of the DRAM cell 100 has been decreasing. This has increased impact of the noise to a point that it is becoming a serious source of data errors.
U.S. Pat. No. 5,276,641 (Sprogis et al) describes an open/folded bit line sense amplifier arrangement and accompanying circuit for a DRAM array. The basic structure consists of two memory arrays, each with a plurality of memory cells. These memory arrays employ a special cell layout architecture in which each cell shares only one passing word line with an adjacent cell. The memory cells are interconnected by bit lines which are parallel to each other and word line which are perpendicular to the bit lines. Between the two memory arrays, arranged in a column, is a set of open sense amplifiers. Each open sense amplifier has a connector on either side for respectively accessing each of the two memory arrays. One of the connectors multiplexed to preferably three adjacent bit lines of on array while the other connector is multiplexed to preferably three adjacent bit lines of the opposite array. On the outer side of each memory array at the opposite ends of the bit lines is a set of folded bit line sense amplifiers, each having two connectors which are multiplexed to preferably three adjacent bit lines in the array one of the bit lines being common to each of these connectors. When data is to be input or output from the memory cells in an array, a word line is activated. In such a selected array, the connectors of each of the folded bit line sense amplifiers are connected by the multiplexing circuitry to one bit line in that array. An intervening bit line separates the two bit lines to which they are connected. Simultaneously, the connectors of an open bit line sense amplifier are activated, on being connected to a bit line in the selected array and the other being connected to a bit line in the unselected array, the later being surrounded on either side by bit lines clamped to AC ground, thus balancing the open sense amplifier capacitively and thereby greatly reducing bit-line coupling noise.
U.S. Pat. No. 5,625,585 (Ahn et al.) describes a bit line structure that has low power consumption. The bit line structure will allow reduced chip operating current without expanding the layout area. Further the sensing noise between bit lines can be reduced compared with the conventional methods.
The bit line structure has a plurality of sense amplifiers each connected to two pairs of bit lines BL and /BL through bit line selecting switches. A plurality of memory cells are connected to the bit lines BL and /BL. A first bit line pair BL and /BL and a second bit line pair BL and /BL are formed by dividing a bit line disposed within a same line respectively in a cell array. A first connecting bit line will connect the bit line BL of said second bit line pair to the sense amplifier, and a second connecting bit line will connect the bit line /BL of the second bit line pair to the sense amplifier. The second connecting bit line will have two crossing sections crossing with another second connecting bit line for connecting a bit line BL of a second bit line belonging to an adjacent sense amplifier. The bit line selecting switches connect the first bit line pair and the second bit line pair respectively to the sense amplifier. The number of memory cells connected to each bit line is reduced to 1/2 compared with the conventional technique. The bit lines are arranged 3-dimensionally to eliminate the area loss in carrying out the layout, and particularly, the connecting bit lines are made of a conductive material, which has a smaller resistance than a conductive material of the bit lines.
The second connecting bit line passes over the first bit line of the bit line BL of another sense amplifier, and among the two crossing points one of them is located between the sense amplifier and the bit line selecting switch. The first and second connecting bit lines are composed of a material different from that of the first and second bit lines.
U.S. Pat. No. 5,010,523 (Yamauchi) discloses a sensing circuit for a DRAM. The bit lines of the DRAM array that are the reference side are temporarily connected to a large load capacitance or to a pre-charge power source when a read operation is performed. This will prevent change in electric potential of the bit lines at the reference side occurring due to interference noises between the bit lines from effecting a read operation. Connecting the reference side of the bit lines to the large load capacitance or to the pre-charge power source will further prevent deterioration of a signal-to-noise ratio due to the change in electric potential of the bit lines.
U.S. Pat. No. 5,627,789 (Kalb, Jr.) describes a differential voltage memory apparatus, which includes one or more preliminary stages of differential amplifiers, which operate prior to triggering of a final stage of differential amplifiers. The preliminary stages of differential amplifiers include cross-coupled inverters that are closely coupled to bit lines connected to memory cells of the memory array. The final stage of sense amplifiers include cross-coupled inverters which are, when in use, substantially decoupled from the bit lines of the memory cells. The preliminary sense amplifiers are activated shortly after activation of corresponding memory cells and provide an initial stage of amplification of a voltage differential generated by the memory cells. The final stage sense amplifiers are triggered after a suitable time delay guaranteeing that a sufficient minimum voltage differential has been generated. The preliminary sense amplifier stages, which are closely coupled to the bit lines and are thereby subject to heavy capacitive loading. These capacitive loaded preliminary sense amplifier stages provide an initial stage of amplification which is substantially decoupled from noise effects, such as effects caused by alpha strikes and the like. The final stage of sense amplifiers, which are substantially decoupled from the capacitive bit lines, are coupled to the preliminary sense amplifier stages to quickly amplify the voltage differential to opposing rail voltages.

DRAM sensing scheme for eliminating bit-line coupling noise

Vanguard International Semiconductor Corporation


A method of screening for retinal disease including directing a first light at a first portion of the retina, directing a second light at a second portion of the retina, measuring a first pupillary response of the eye as a result of the first light and a second pupillary response as a result of the second light, and generating an indication of a severity level of the retinal disease using the first pupillary response and the second pupillary response. Also, an apparatus that implements this method including a light source for directing a first light at a first retinal portion and a second light at a second retinal portion, a pupil measuring device for measuring the pupillary response of the eye as a result of the first light and second light, a processor in electronic communication with the pupil measuring device, and a memory in electronic communication with the processor.

1. Field of the Invention
The present invention relates to a method and apparatus for screening for retinopathy, such as diabetic retinopathy, and in particular to a method and apparatus for providing an objective indication of the severity of retinal disease and disease features, such as diabetic retinopathy and retinal ischemia, using pupillometry and a plurality of light stimuli.
2. Description of Related Art
There is an epidemic of diabetes in this country. Diabetic retinopathy, which is a pathological disorder of the retina caused by diabetes, is a major health threat to diabetics. It is estimated that more than 80% of diabetics will develop diabetic retinopathy to some extent, with a large percentage requiring treatment. The most common cause of vision loss in diabetics is the failure to recognize and treat diabetic retinopathy. Thus, effective screening for diabetic retinopathy is essential for diabetics to maintain visual function and quality of life.
Diabetic retinopathy is the result of retinal capillary damage caused by diabetes. The progressive loss of retinal capillaries leads to areas of retinal ischemia, which is a decrease in blood supply to the retina, primarily in the midperipheral portion, and to a lesser extent in the central portion, of the retina. Retinal ischemia promotes angiogenesis, also called neovascularization, which is the growth of new blood vessels in the retina. When uncontrolled, angiogenesis can cause damage to normal retinal tissues because the new vessels are fragile and hemorrhage easily. In addition, ischemic changes promote increased permeability of the retinal blood vessels, which leads to a swelling and thickening of the central portion of the retina, a condition called macular edema (the macula is an area near the center of the retina), and reduced visual function. Midperipheral retinal ischemia, while primarily seen in diabetic retinopathy, is also seen in a number of other conditions, including sickle cell disease, retinitis pigmentosa, Eales disease, and radiation retinopathy, among others. An ischemic retina has reduced sensitivity to light in portions thereof, which is why diabetics with advanced forms of the disease are often night blind and have reduced peripheral vision.
In screening for diabetic retinopathy, a clinician thus needs to look for signs of both macular edema and midperipheral retinal ischemia. The extent of retinal thickening in the macula (macular edema) can be a quantitatively assessed using an existing technology known as optical coherence tomography (OCT). OCT provides actual dimensions of the thickness of the retina in the central 6 mm thereof, and thus can be used to detect macular edema that might adversely effect vision.
Unlike macular edema, there is currently no known quantitative screening method for retinal ischemia. Instead, current screening methods for retinal ischemia involve the subjective clinical observation of various physiological conditions including nerve fiber layer infarcts, arteriolar narrowing, venous bleeding and actual neovascularization. Studies have shown that clinical expertise has a great deal to do with the ability to recognize severe preproliferative diabetic retinopathy, and in particular retinal ischemia, through clinical examinations. This is due, in part, to the fact that the midperipheral portion of the retina is poorly visualized by routine clinical exams and most retinal photography systems. As a result, screening programs based on clinical examinations have a high no show rate, and many cases of diabetic retinopathy are not diagnosed until proliferative retinal changes are extensive.
A number of known screening systems have been devised that translate the clinical examination to an imaging effort. In such systems, images of the retina are transmitted to a reading center where they are examined by trained clinicians to assess disease features. Such systems have several disadvantages, including delays in determining patient status, since images must be transmitted to and reviewed by a remote clinician (such delays create a potential for loss of follow-up with the patient), the high manpower costs required to implement the systems, the limitations imposed by media opacities that affect the quality of the transmitted images, and the fact that such systems still rely on subjective clinical examinations and, as a result, present the same problems described above.
The most direct way to detect retinal ischemia is with a test known as a fluorescein angiogram. A fluorescein angiogram, however, is an invasive procedure that requires dilation of the eye, the injection of dye into the patient and highly specialized photography. As a result, fluorescein angiograms present the potential for numerous complications. In addition, reduced retinal light sensitivity, such as is caused by retinal ischemia, can be assessed through known techniques such as visual field testing and multifocal electrophysiology. These techniques have several disadvantages associated with them. In particular, visual field testing is subjective, time consuming, and relies on the active and accurate participation by the patient, and multi-focal electrophysiology is costly, time consuming, and requires dilation and significant patient cooperation.
Thus, there is a need for a screening approach for retinal disease and associated features, such as those that cause reduced light sensitivity in portions of the retina as is the case with retinal ischemia, that is objective, quantitative, requires minimal cooperation of the patient, requires limited technician skills, and that can provide an immediate clinical assessment.

Method and apparatus for screening for retinopathy

University of Pittsburgh - Of the Commonwealth System of Higher Education


A server computing device, including memory storing a knowledge graph. The server computing device may further include a processor configured to receive a natural language input and generate a tokenized utterance based on the natural language input. Based on the tokenized utterance, the processor may select a predefined intention indicating a target ontology entity type of the natural language input. The processor may identify at least one input ontology entity token included in the tokenized utterance and may identify at least one relation between the predefined intention and the input ontology entity token. Based on the predefined intention, the at least one input ontology entity token, and the relation, the processor may generate a structured query. Based on the structured query and the knowledge graph, the processor may output an output ontology entity token having the target ontology entity type.

Natural language search engines are used by a wide range of enterprises that work with large amounts of data. Natural language search engines aim to find targeted answers to user questions expressed in natural language rather than in more formalized query languages. Thus, natural language search functionality may allow users without specialized knowledge of query languages to search databases and receive desired search results. Natural language searching may allow the database to be used by a larger number of users and may reduce the amount of time needed to train users of a database. However, existing natural language search engines are typically expensive and time-consuming to customize to meet the needs of specific enterprises.

This patent is subject to a terminal disclaimer.

Querying knowledge graph with natural language input


Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.

Integrated circuit (IC) technology is often used to implement logic functions. Some ICs provide combinationatorial and sequential logic functions that are user-programmable. One class of such ICs uses programmable logic gates to implement desired functions and to drive the output. Another class of these ICs employs memory units, each of which utilizes the input signals as its memory address and outputs its stored content as the desired functional combination of the address bits. These devices are generally known as programmable logic devices (PLDs). Different methods of implementing PLDs abound in the literature of this field.
One type of PLD is known as a field programmable gate array (FPGA), which usually contains an array of modularized logic function generators and programmable interconnects. It is an array of uncommitted gates with uncommitted wiring channels. Each logic cell can be programmed to implement a particular logic function. A gate array circuit can be programmed to implement virtually any set of functions. FPGAs generally use look-up tables (LUTs) or universal logic modules (ULMs).
A look-up table is an addressable array or a matrix of memory units that contains data and can be searched by addressing and accessing individual memory units. Therefore, by programming predetermined values into the memory array, the LUT can implement any function of the input variables. FPGAs can be manufactured to allow a combination of LUTs to be grouped together to implement larger functions.
FIG. 1 shows a 2-input LUT according to the prior art. This LUT is disclosed in U.S. Pat. Nos. 4,642,487 and 4,870,302. The circuit contains four SRAM memory cells (M1 to M4), six NMOS pass gates n1-n6, and three inverters inv1-inv3. This implementation requires 24 NMOS and 6 PMOS devices. The NMOS pass gates cause a Vt drop, and thus, there is a need for a recovery circuit.
As process technology scales down to 0.13 micron, 90 nm, and beyond, the Vdd voltage is also scaled down to below 1.2V. Furthermore, the pass devices n1-n6 ineffectively pass Vdd due to the Vt drop of the NMOS. Thus, transmission gate devices are substituted by the ones shown in FIG. 2 (see also U.S. Pat. Nos. 5,719,507 and 6,809,552). However, this implementation also requires 24 NMOS and 16 PMOS devices, not including the buffer inverter inv3.
The prior art look-up tables, as illustrated above, use a relatively large number of devices, which result in LUTs that consume valuable silicon area. In addition, there is a high amount of power leakage, which may well become a serious limitation for FPGAs that are used in battery-operated applications.

Programmable logic function generator using non-volatile programmable memory switches


The invention provides compositions and methods for ameliorating, treating, reversing or preventing pathology or inflammation in the central nervous system (CNS), or the brain, caused or mediated by NFkB, IL-6, IL-6-R, NADPH oxidase (Nox), and/or superoxide and/or hydrogen peroxide production by a NADPH oxidase, including for example ameliorating, treating, reversing or preventing schizophrenia, psychosis, delirium, e.g., post-operative delirium, drug-induced psychosis, psychotic features associated with frailty syndrome (FS), aging, depression, dementias; traumatic war neurosis, post traumatic stress disorder (PTSD) or post-traumatic stress syndrome (PTSS), Amyotrophic Lateral Sclerosis (ALS, or Lou Gehrig's Disease), and/or Multiple Sclerosis (MS). The invention also provides methods for purifying a C60 fullerene, C3 (tris malonic acid C60) or malonic acid derivatives.

Schizophrenia, psychosis, delirium, drug-induced psychosis, psychotic features associated with depression and dementia, and dementias are increasingly prevalent and important medical condition. Although the neural circuitry changes that are believed to be responsible for these deficits have been well described in humans, and are reproduced in primate and rodent models of these same disorders, there are currently no therapies directed at the underlying causes of these neural circuitry changes.
Interleukin-6 (IL-6) is known to be elevated in patients with psychosis, schizophrenia, and many dementing disorders. Recently, a therapeutic humanized monoclonal antibody (tocilizumab, or ACTEMRA™ (F. Hoffmann-La Roche Ltd, Basel, Switzerland)) acting as a specific antagonist (is receptor-inhibiting) for IL-6 receptors was approved for the treatment of arthritis.
Frailty syndrome (FS) has become increasingly recognized as a major predictor of co-morbidities and mortality in older individuals. While definitions of FS vary, most experts agree this syndrome is characterized by reduced functional reserve, impaired adaptive responses resulting multi-system decline, which results in increased vulnerability to adverse events.

Methods for ameliorating and preventing central nervous system inflammation

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA


The present invention relates to self-adhesive labels, label sheet assemblies, and related methods. The label sheet assembly includes a release liner assembly having a detachable portion, and a label releasably coupled to the release liner assembly and overlying the detachable portion. Weakened separation lines, a U-shaped cut, and a transverse cut define the detachable portion. The detachable portion is configured to remain coupled to the label as the label is peeled from the release liner assembly in a first direction, and the detachable portion is configured to remain part of the release liner assembly and separate from the label as the label is peeled from the release liner assembly in a second direction.

Printable self-adhesive labels and label sheets having multiple self-adhesive labels are generally known. Label consumers and users often attach these self-adhesive labels around objects with non-planar surfaces, such as around cylindrical objects and the like. The standard method for attaching self-adhesive labels around non-planar surfaces is that a user bends back the label sheet somewhere in the vicinity of one of the edges or corners of the label to be removed. This causes a separation between the label and the liner of the label sheet. The user then grasps the label in the area where the separation has been created, and fully removes the label from the sheet and liner. With the entire adhesive backing exposed, the user then attaches a first portion of the label onto a first section of the non-planar surface and then continues to apply the label to the surface until the entire label is adhered to the surface. However, in some cases, especially where the label is flexible or conformable, it becomes difficult to attach a label around a non-planar surface using the standard method while maintaining a smooth label surface. Application of a label to a non-smooth surface can often make it difficult for any indicia printed or otherwise written on the surface of the label to be clearly or easily visible.

Labels, label sheet assemblies, and related methods


An apparatus for anchoring a boat to a bottom of a body of water is disclosed. The apparatus includes a base securely coupled to a transom of a boat and an elongated member having a proximal end hingably coupled to the base. The apparatus further includes a spear hingably coupled to a distal end of the elongated member, such that when the elongated member is positioned substantially horizontally, the spear is positioned substantially vertically so as to extend below a hull of the boat. The apparatus further includes a maneuvering arm hingably coupled to the elongated member for manually lowering the elongated member into a substantially horizontal position. The apparatus further includes a stopping member perpendicularly coupled to the distal end of the elongated member, so as to halt the spear from rotating beyond ninety degrees from the elongated member.

1. Field of the Invention
This invention relates to shallow water anchors and more particularly to manually operated shallow water anchors.
2. Description of the Related Art
Typical marine anchors for small boats comprise a heavy metal anchor with an irregular shape, which is attached to the boat via a long chain or rope. The anchor and chain/rope are usually stored on the deck of the boat or in a compartment on the deck. When use of the anchor is necessary, it is picked up and thrown into the water. The anchor subsequently rests on the floor or bottom of the body of water and secures the boat to a fixed location due to the weight of the anchor. Typical marine anchors, however, come with their share of drawbacks.
Because typical marine anchors have a long rope or chain attaching them to a boat, they can often become tangled or snagged on various items. This requires the user to untangle or un-snag the rope or chain before it can be deployed—a tedious and time-consuming process. Further, the heavy weight of the anchor requires the user to carefully pick up the anchor and throw it overboard so as to avoid hitting the fragile deck or hull of the boat and cause damage—a feat that requires strength, balance and agility. The user encounters a similar situation when retracting the anchor from the ocean or lake bottom. Additionally, when deploying or retracting the anchor, the unwieldy nature of the marine anchor often causes substantial noise that is distracting and can scare off fish, which is not desirable for a fisherman. Lastly, the heavy nature of the anchor can cause damage to the ocean or lake bottom since the anchor can be dragged or may move around. This is not desirable in areas where fragile ocean life resides, such as reefs and underwater vegetation areas.
Fishing in shallow or littoral waters brings up an additional set of requirements for an anchor. In shallow water, for example, fish are confined to a smaller area, thereby requiring that the fisherman be extra quiet when propelling and deploying/retracting an anchor. Further, during shallow water fishing, a fisherman typically moves around frequently as he attempts fishing in different spots. This requires frequent deployment and retraction of an anchor. As such, an anchor that requires substantial time and energy to deploy and retract can be burdensome to a fisherman in a shallow water environment.
One approach to this problem is a mechanized marine anchor system that automates the process of deploying and retracting an anchor. Mechanized marine anchor systems typically utilize electrical power to energize an electrical motor having a mechanical means for deploying and retracting an anchor. Although this type of system eliminates the need for manual operation, a mechanized marine anchor system requires an electrical system that is operational during deployment and retraction of an anchor. This is not always easily available in a small boat such as a flats boat. Furthermore, a motor may cause excessive noise, which is not desirable in a shallow water environment, as described above. Lastly, a mechanized marine anchor system comprises a complicated system with multiple moving parts and electrical terminals, which are prone to malfunctioning, especially in a saltwater environment.
Therefore, a need exists to overcome the problems with the prior art as discussed above, and particularly for a more efficient way for deploying and retracting an anchor in shallow water.


A blood lancing device for puncturing a skin has a lancet longitudinally displaceable in a first direction to puncture a skin of a patient and then into a second opposite direction out of the punctured skin, a spring having an active stroke, a toothed rack displaceable by the spring during its active stroke in the first direction; a toothed pinion engageable with and rotatable by the toothed rack when it moves in the first direction, and a lever having a first end connected with the toothed pinion and a second end connected with the lancet so that during the rotation of the pinion under the action of displacement of the toothed rack caused by the spring the second end of the lever moves the lancet successively in the first direction and in the second direction.

The present invention relates to a blood lancing device used for punturing a skin of a fingertip, preferably for home use.
Blood lancing devices are known in the art. A known blood lancing device has a lancet and a mechanism for its movement in two opposite longitudinal directions so as to puncture the skin of a patient and then to withdraw the lancet from the punctured skin. The known mechanisms have sone disadvantages in that during their operation the lancet is subjected to vibrations and chatter which results in pain inflicted to the patient. Some attempts have been made to reduce the vibrations and chatter; however, further improvements are desirable in this sense.


A three cycle, two-stroke internal combustion engine from which work can be extracted in two directions. In the preferred embodiment, the inventive two-stroke engine is constructed as a cylinder having a reciprocating piston slidably seated therein, with the piston defining a compression and combustion chamber between the cylinder wall and each side of the piston. The two-stroke engine can provide work in bi-directional fashion from the two combustion chambers acting in phase. A piston rod is provided with reciprocating linear motion, and a mechanical converter is used to change the linear movement to rotational motion providing torque from which rotational power can be extracted for machinery. In an alternative embodiment, the cylinder is shaped with a bottom portion which is split into two sections, in which a bifurcated piston is seated in reciprocating fashion. A piston rod extending through the space between the split cylinder sections is driven with conventional side-to-side linear motion, and is connected to a conventional offset crankshaft, to harness the useful work output of the engine. The two-stroke engine is compact in size and more powerful than a similar 4 or 2-cycle engine, since its dual action makes it equivalent to two combined standard engines. The engine also provides a reduction in overall weight, decreasing the weight-to-power ratio, with an increase in fuel efficiency. Recoil impulses from the torque produced are reduced, increasing the engine life.

There are known prior art engine designs featuring a two-stroke internal combustion engine, including those described in U.S. Pat. Nos. 3,283,752 and 4,385,597 to Stelzer, No. 4,831,972 to Barnwell, No. 5,036,667 to Thatcher, and No. 5,285,752 to Reed et al. The Reed patent features rotary valves for fresh air intake, and this requires conversion of the linear piston motion to rotary motion, introducing additional friction. The Thatcher patent returns a portion of the power developed to force return of the combustion piston motion, decreasing output.
The Barnwell patent and the Stelzer patents feature extremely long piston rods, a portion of which are exposed beyond the cylinder, making them vulnerable to more-than-usual wear due to friction on entering and exiting the reaction chamber at each stroke. Leaking of fuel across the entry/exit barrier can occur as well as pressure gradients causing "bubbles" which can "choke" the engine at worst, or reduce Its efficiency at best. Thus, the exposed extra-long piston rods of the previous designs act as weak points, reducing the overall strength of the engine.
In the Steizer design, the single operating cycle does not allow for full exhaust of combustion gases, and there is a mixture of burnt gas and the fresh fuel supply, which reduces efficiency. As mentioned above, a portion of the piston is exposed beyond the cylinder, and the O-ring used to seal the piston exits and returns into the cylinder with each cycle, causing a shock against the O-ring on each re-insertion.
An additional weakness of the previous designs is the connection between the piston rod and the crankshaft. The above designs do not permit direct connection with the conventional type of crankshaft, so this involves additional loss of efficiency for the engine.
The prior art two-stroke internal combustion engine designs, therefore, suffered from intrinsic flaws detrimental to their sturdiness and efficiency, and represented radical departures from the standard practice. This made their adaptation to the existing market difficult.
In addition, the prior art designs do not allow for operation as a Diesel engine, requiring high compression ratios.
Therefore, it would be desirable to overcome the disadvantages associated with the prior art designs, and provide a sturdy, lightweight internal combustion engine providing increased efficiency.

Three-cycle stroke two internal combustion engine

15/3 Havradim Street Ramot Yitzhak 36781


A vapor sensing device that is sufficiently small and lightweight to be handheld, and also modular so as to allow the device to be conveniently adapted for use in sensing the presence and concentration of a wide variety of specified vapors. The device provides these benefits using a sensor module that incorporates a sample chamber and a plurality of sensors located on a chip releasably carried within or adjacent to the sample chamber. Optionally, the sensor module can be configured to be releasably plugged into a receptacle formed in the device. Vapors are directed to pass through the sample chamber, whereupon the sensors provide a distinct combination of electrical signals in response to each. The sensors of the sensor module can take the form of chemically sensitive resistors having resistances that vary according to the identity and concentration of an adjacent vapor. These chemically sensitive resistors can each be connected in series with a reference resistor, between a reference voltage and ground, such that an analog signal is established for each chemically sensitive resistor. The resulting analog signals are supplied to an analog-to-digital converter, to produce corresponding digital signals. These digital signals are appropriately analyzed for vapor identification. The device can then subsequently transmit the digital signals over a computer network, such as the Internet, for analysis at a remote location.

This invention generally relates to the detection and transmission of sensory data. More particularly, the present invention relates to an apparatus for detecting and transmitting sensory data of analytes from one portable handheld electronic nose (e-nose) to another for analytic purposes.
Techniques and devices for detecting a wide variety of analytes in fluids such as vapors, gases and liquids are well known. As used herein the term "fluid" means gases, vapors and liquids. An electronic nose is an instrument used to detect vapors or chemical analytes in gases, solutions, and solids. In certain instances, the electronic nose is used to simulate a mammalian olfactory system. In general, an electronic nose is a system having an array of sensors that are used in conjunction with pattern-recognition algorithms. Using the combination of chemical sensors, which produce a fingerprint of the vapor or gas, the recognition algorithms can identify and/or quantify the analytes of interest. The electronic nose is thus capable of recognizing unknown chemical analytes, odors, and vapors.
In practice, an electronic nose is presented with a substance such as an odor or vapor, and the sensor converts the input of the substance into a response, such as an electrical response. The response is then compared to known responses that have been stored previously. By comparing the unique chemical signature of an unknown substance to "signatures" of known substances, the unknown analyte can be determined. A variety of sensors can be used in electronic noses that respond to various classes of gases and odors.
A wide variety of commercial applications are available for electronic noses including, but not limited to, environmental toxicology and remediation, biomedicine, such as microorganism classification or detection, material quality control, food and agricultural products monitoring, heavy industrial manufacturing, ambient air monitoring, worker protection, emissions control, and product quality testing. Many of these applications require a portable device because they are located in the field or because they have an inaccessible location for larger laboratory models. Conventionally, most of the electronic noses have been large cumbersome laboratory models incapable of being used in the field and pilot plant applications. If available, a portable or handheld device would provide the portability required for pilot plant and field locations. Unfortunately, the portable chemical detectors that have been developed thus far have many limitations that have kept them from being widely accepted.
For instance, U.S. Pat. No. 5,356,594, which issued to Neel et al., discloses a portable volatile organic monitoring system designed for use in detecting fugitive emissions. The device includes a bar code reader for inventorying the emission site. The device contains a single sensor responsive to ionized gas, however the device only detects the amount (i.e., concentration) of the volatile compound. The device is incapable of identifying the volatile organic compound. Thus, the device is merely a vapor amount logger and not a portable electronic nose. As such, the user is required to know the identity of the vapor being quantitated or this information must be stored elsewhere.
Another example of a portable device is disclosed in U.S. Pat. No. 4,818,348 issued to Stetter. Although this portable device is more sophisticated than the previous example, it still has many limitations. In this instance, the device is capable of identifying a gas or vapor, but the applications are quite limited because of sensor architectural limitations. The sensors making up the array are permanently fixed, and thus, the number and variety of analytes and gases that the device is capable of identifying is quite small. Moreover, because the analyte or vapor being identified interacts with each sensor of the array in a different amount, the reproducibility and stability of the device is quite limited. These limitations affect the device's accuracy in identifying unknowns.
Concurrent with the development of better detection techniques for detecting analytes, there is an emerging need to develop methods and devices to efficiently transmit the collected sensory data for swift analysis. Under some prior customary practices, the sensory data were first captured and then physically transported back to a laboratory or some other designated facility for subsequent analysis. Very often, analyses on these data would not be performed until a substantial period of time had elapsed and consequently their results would not be available for hours, days or even weeks.
Timely transmission and analysis of sensory data for detected analytes have tremendous applications in a variety of areas. There are many instances where it is desirable to obtain results on the analysis of the sensory data in a timely manner. For example, in a hospital/medical environment, it would be greatly beneficial if data collected from a patient can be transmitted quickly to a laboratory to determine the cause of the patient's ailments thereby allowing the doctors to prescribe the necessary treatment without any undue delay. In a similar example, medical and other related data from home monitoring devices can be collected and transmitted swiftly to the appropriate hospitals and/or authorities to allow them to provide better response to home emergencies. In another example, in environments where the presence of certain substances can potentially lead to dangerous conditions, such as a gas leak in a foundry or a home, the swift transmission of sensory data for analysis can very well preempt an impending disaster. Clearly, there are many other situations that one could think of where the efficient transmission of sensory data will generate tremendous benefits. Hence, it would be desirable and beneficial to create a method and system that is capable of timely transmitting sensory data for analysis.
In addition to the need to have timely transmission of sensory data, there is a need to provide easy access to the collective data compiled for the known analytes. The results of any detection analysis are only as good as the data that are available for comparison. At the present time, various analytes have been identified and data therefor have been compiled and stored all over the world. Perhaps, due to the voluminous amount of data that are available, these data are generally not centralized in any one particular depository but are instead separately stored at different facilities. The segregation of these data, therefore, renders a complete and accurate analysis more difficult. Hence, it would be desirable to have a method and system that is capable of providing better access to these available data thereby allowing more accurate analyses to be performed. The present invention fulfills these and other needs by providing a method and system of detecting, transmitting, storing and retrieving sensory information over a computer network.

Apparatus, systems and methods for detecting and transmitting sensory data over a computer network


A method of measuring a patient's systolic and diastolic brachial blood pressure non-invasively with a brachial cuff considers the shape of a patient's peripheral waveform (e.g., the cuff volumetric displacement waveform) to recalibrate the height of the waveform. The maximum and minimum values of the recalibrated waveform correlate to and closely estimate counterpart values for invasively measured brachial systolic and diastolic pressure.

Arterial blood pressure is a clinically important indicator of the status of the cardiovascular system, reflective of arterial and cardiac load and an early independent predictive marker of cardiovascular events and diseases. However, to measure the inter-arterial blood pressure accurately requires an invasive procedure to insert a catheter with a pressure sensor inside the artery. As a result, non-invasive methods were created to estimate pressure at the peripheral brachial artery.
One of the earliest non-invasive methods to estimate pressure in the brachial artery is the auscultatory method which requires inflating a cuff wrapped around the patient's upper arm and brachial artery until the brachial artery occludes (i.e., no blood flow). Then, the cuff is gradually deflated and blood starts flowing with "thumping" sounds that can be detected through a stethoscope. The first "thumping" sound should occur when the cuff pressure equals the patient's systolic pressure (maximum pressure during cardiac ejection) and the last "thumping" sound should occur when the cuff pressure equals the patient's diastolic pressure (minimum pressure during cardiac filling).
For decades, the auscultatory method was used for clinical hypertension diagnosis and had become the standard for non-invasive blood pressure measurement. However, the accuracy of the measured pressure value was dependent on the operator's acute detection of the heart sound and also dependent on the rate that the operator deflated the cuff. Because the accuracy of the auscultatory method is operator dependent, an automated method was established based on detecting oscillatory pulsations measured by the brachial cuff during cuff inflation or deflation. The height of the pulse oscillation increases when the cuff pressure decreases from systolic pressure to below systolic pressure and the height of the oscillation decreases when the cuff pressure decreases from above diastolic pressure to diastolic pressure and below. Based on this concept, current "oscillometric" devices apply different algorithms to detect oscillation heights related to systolic and diastolic pressure.
Oscillometric cuff devices are often called a non-invasive blood pressure devices or NIBP devices in the art. To be accepted for clinical use, an NIBP device has to show equivalence to the standard auscultatory method based on the American National Standard for Non-Invasive Automated Blood Pressure Devices, see, ANSI/AAMI/ISO 81060-2:2009, "Non-invasive sphygmomanometers—Part 2: Clinical validation of automated measurement type," Section 18.104.22.168.2 Part a—Criterion 1, page 20 (which states that the mean error for determination of all subjects in the test "shall not be greater than 5.0 mmHg with a standard deviation no greater than 8 mmHg.") Accordingly, any oscillometric cuff device can pass the validation requirements if the average difference with the auscultatory method for systolic and diastolic pressure is not more than 5 mmHg and the standard deviation is not more than 8 mmHg. This means that approved oscillometric devices can register a difference with the standard auscultatory method reaching above 20 mmHg for some data points.
Oscillometric automated blood pressure devices have been standard in clinical practice for many years, and have also been used in medical research to assess cardiovascular risk. Even though non-invasive blood pressure (NIBP) measurement identifies a percentage of the general population at risk of cardiovascular diseases, a large group is not identified by NIBP measurement to be at risk even though they may be at risk. The main reason is that measured blood pressure varies among different NIBP devices due to the different devices having different propriety algorithms for detecting systolic and diastolic pressure. Furthermore, when compared to invasive pressure values, NIBP devices have been shown to underestimate systolic pressure and overestimate diastolic pressure, see, Sharman et al, "Validation of non-invasive central blood pressure devices: Artery Society task force consensus statement on protocol standardization", European Journal of Hypertension 2017; Cloud et al, "Estimation of central aortic pressure by SphygmoCor® requires intra-arterial peripheral", Clinical Science (2003) 105, 219-225.Shoji et al, "Invasive validation of a novel brachial cuff-based oscillometric device (SphygmoCorXCEL) for measuring central blood pressure", Journal of Hypertension 2016, 34. Accordingly, since measuring brachial pressure invasively is the gold standard, non-invasive measurements that closer estimate the invasive pressure and overcome the errors inherent in cuff NIBP devices would be a significant improvement in the field of blood pressure measurement and its clinical importance.

Non-invasive brachial blood pressure measurement


A method and system for flexible resource control for a wireless transmit/receive unit (WTRU) is disclosed. The WTRU may monitor a first control channel region and receive a first control channel transmission in the first control region indicating boundaries of a plurality of numerology blocks of a carrier. The WTRU may then receive a second control channel transmission in a second control channel of a second control region, wherein the second control channel transmission indicates one or more numerology parameters for at least one of the plurality of numerology blocks. The WTRU may then transmit or receive data based on the one or more numerology parameters of the one or more numerology blocks.

In mobile communication, there are generational advancements in wireless technologies. For instance, in 1980 the first generation of wireless technology was established. By the late 1980s, a second generation followed. This pattern, albeit at varying paces of development, continues. Some generations of technology have been retired, while others are still being developed concurrently with other generations. All generations of wireless technology require standards, protocols, hardware, and other related developments. With each new generation, these same concerns must be addressed.


A flossing device has an internal supply of floss, a pair of tines between which a length of the floss is strung, and a vibration source that causes the floss to vibrate at a frequency of least 10 Hz. In another aspect, a dental cleaning device has three separable parts—a handle, a neck section, and a plurality of interchangeable cleaning heads. The handle has a power source that is in electronic communication with the neck section, and the neck section houses a vibration source that is received by the interchangeable cleaning heads.

Motor powered toothbrushes have been known for many years. While such brushes can certainly provide more brushing movements over a given period of time, and therefore at least arguably "better brushing", the earliest electric toothbrushes were deficient in that they merely reciprocated in an up and down fashion.
U.S. Pat. No. 3,183,538 disclosed a significant improvement in toothbrush technology through the use of vibration instead of reciprocation. Among other things, vibration provided superior cleaning because the bristles of the toothbrush moved in all directions.
U.S. Pat. No. 3,466,689 took the concept of cleaning using vibration one step further by teaching a "sonic" dental cleaning device. In devices according to the '689 patent, the vibration was produced by an eccentric weight revolving about an axis at a frequency of 90–100 cycles per second. That frequency was apparently high enough to cause a sensation known as "acoustic streaming", i.e., localized high velocity streams of fluid created by high frequency sound in a liquid.
One problem with the '689 devices is that they failed to adequately clean the interproximal surfaces of the teeth. That problem was addressed in reissued U.S. Pat. No. Re.35,712, in which a vibrating toothbrush is combined with dental floss to clean interproximal surfaces of teeth. As it turned out, the idea was good but the execution was poor. The '712 patent taught the use of sonic frequencies between 2,000 and 20,000 cycles per minute, which were produced by an eccentrically mounted disc are in the handle. That arrangement imparted a significant amount of vibration to the hand of the user. An arrangement that imparts a significant amount of vibration to the hand of the user is inefficient, because the user's hand dampens the vibration causing less vibratory energy to be imparted to the dental floss. Such an arrangement is also uncomfortable because the user's hand is vibrating significantly.
Another problem is that devices according to the '712 patent had no supply of floss for restringing between the tines. In retrospect, that failure was entirely predictable from the way in which toothbrushes and dental floss evolved. The dental floss attachment was merely an "add-on" to a handle designed to vibrate a toothbrush. Since the toothbrush attachment was quite small, it was natural to provide a dental floss attachment that was also quite small, and therefore had no provision to store a supply of floss. In addition, since it was contemplated that a user would replace the toothbrush and flossing attachments during each use, it was natural to assume that the user would not object to utilizing an entirely new flossing attachment at each cleaning session.
U.S. Publication No. US 2002/0106607 does provide a vibrating flosser that has on-board supply of replacement floss. In that publication the inventor contemplated the supply as an externally mounted reel of floss, which is of course consistent with the prevailing notion of minimizing the size of the flossing attachment, and using the handle to enclose a relatively large motor and battery. But an external supply of floss has its own problems. Among other things an external supply of floss is aesthetically unappealing, and can readily accumulate toothpaste and other fluids. Thus, there is still a need to provide a vibrating flosser that has an internal supply of replacement floss.


A machine has an outer housing that receives a drive shaft. A bearing housing supports a bearing. The drive shaft is mounted within the bearing and the outer housing. Attachment members extend between the outer housing and the bearing housing. A selected damping includes an elastomeric ring attached to a surface of a bearing housing and an outer housing. A selectively moveable plate is connected to the outer housing and the bearing housing. The plate is selectively moveable from a position at which it engages the elastomeric ring to a point at which it is spaced from the elastomeric ring.

This application relates to a damping system for a test equipment housing that can be selectively engaged.
A known piece of test equipment is utilized for operating a gas turbine engine compressor section such that the section can be tested. Generally, an input shaft is driven by a source of rotation, and is connected to the compressor rotor, and drives the compressor rotor to rotate. Sensors, or other test equipment sense conditions and operation of the compressor rotor.
In the known piece of test equipment, there are two roller bearings which mount the shaft within a housing. A bearing housing associated with one of the bearings is bolted to an outer housing. The bolted connection transmits vibration between the bearing housing to the outer housing.

Test equipment with housing damping system


A liquid crystal display includes a lower substrate, an upper substrate positioned parallel with the lower substrate, and a plurality of pixel units between the lower substrate and the upper substrate. Each pixel unit includes an upper transparent electrode, a liquid crystal layer, a lower transparent electrode, and a color filter with recess structures.

1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to an LCD comprising color filters with recess structures.
2. Description of the Prior Art
Due to low prices and high quality of liquid crystal displays (LCDs), the LCD is widely applied in notebooks, PDAs, mobile phones, and so on.
Please refer to FIG. 1. FIG. 1 shows a sectional view of a conventional color LCD 11. The color LCD 11 comprises a lower glass substrate 9, an upper glass substrate 2 positioned parallel to and above the lower glass substrate 9, and a plurality of pixel units (not shown in FIG. 1) positioned between the lower glass substrate 9 and the upper glass substrate 2, each of the pixel units including a red color filter 3R, a green color filter 3G, or a blue color filter 3B. An inner surface of the upper glass substrate 2 includes an upper transparent electrode 4, and an inner surface of the lower glass substrate 9 includes a lower transparent electrode 8 and a plurality of thin film transistors (not shown in FIG. 1) for controlling the pixel units. Furthermore, a liquid crystal layer 6 is positioned between the upper glass substrate 2 and the lower glass substrate 9, and an exposed portion of an outer surface of the upper glass substrate 2 and an exposed portion of another surface of the lower glass substrate 9 respectively include an upper polarizer 1 and a lower polarizer 10. The above-mentioned color LCD 11 is a transmissive color LCD. A reflective color LCD similar to the transmissive color LCD further comprises a reflection layer (not shown in FIG. 1) positioned between the color filters 3R, 3G, 3B and the lower glass substrate 9. Additionally, a transflective color LCD comprises a diffusion layer (not shown in FIG. 1) positioned between the upper polarizer 1 and the lower polarizer 10.
Since the transmissive LCD is a passive luminous device, a backlight source (not shown in FIG. 1) positioned behind the lower glass substrate 9 is required for the color LCD 11. A white light is radiated from the backlight source and passes through the color filters 3R, 3G, 3B so as to enable each of the pixel units to respectively display a red light, a green light, and a blue light. However, only portions of the white light with specific wavelengths can pass through the color filters. For the reflective color LCD, the white light radiated from the backlight source has to pass through the color filters and reach a surface of the reflection layer, then the light is reflected by the reflection layer and again passes through the color filters for respectively displaying a red light, a green light, and a blue light. Consequently, comparing to the transmissive color LCD, the color deepness of the reflective color LCD is greater, and the problem of the reflective color LCD having insufficient brightness is more serious.
For solving the above-mentioned problems, a conventional color LCD 15 comprises light transmitting holes 18 respectively formed in the color filters 16R, 16G, 16B of each pixel unit, as shown in FIG. 2. Therefore, the transmittance of the color filters 16R, 16G, 16B can be increased for improving a brightness of a transmissive color LCD or a reflective color LCD, and a color deepness of the transmissive color LCD or the reflective color LCD is also regulated. However, the method of forming holes 18 in the color filters 16R, 16G, 16B results in a non-uniform cell gap 19, and an overcoating layer 17 is required for covering the color filters 16R, 16G, 16B. Because the gap 19 caused by the formation of the holes 18 is great, the overcoating layer 17 formed for planarization is not so effective, and a stability and a quality of the LCD 15 is reduced.

Liquid crystal display having color filters with recess structures


Process for the production of aqueous solutions of alkali metal, alkaline earth metal, ammonium and/or amine salts of sulfonated fatty acid glycerides by sulfonation of unsaturated fatty acid glycerol esters with gaseous sulfur trioxide, neutralization with aqueous bases and subsequent heating with phase separation, and to the aqueous solutions produced thereby.

1. Field of the Invention
This invention relates to a process for the production of aqueous solutions of alkali metal, alkaline earth metal, ammonium and/or amine salts of sulfonated fatty acid glycerides by sulfonation of unsaturated fatty acid glycerol esters with gaseous sulfur trioxide, neutralization with bases and subsequent heating with phase separation and to their use as surfactants.
2. Description of Related Art
Sulfonation products based on unsaturated fatty acid glycerol esters have long been known. As long ago as 1834, Runge obtained sulfonated oils by the action of sulfuric acid on olive oil or castor oil. These oils are still in use today as auxiliaries, so-called "Turkey red oils", in the dyeing of textiles (H. Stache, H. Grossmann, "Waschmittel", Springer-Verlag, Berlin-Heidelberg, 1985). Other sulfonated oils are used in the wet finishing of textiles, in hand-washing pastes, as thickeners in paints, as hydrotropes for liquid detergents, corrosion inhibitors or emulsifiers for mineral oils (Soap. Cosm. Chem. Spec. (1975) 39).
The two patent applications PL 120 511 and SU 475 391 describe processes for reacting unsaturated triglycerides, for example from the oleic-acid-rich fraction of tall oil, with sulfuric acid. The addition of H.sub.2 SO.sub.4 onto the double bond of unsaturated fatty acid glycerol esters leads to the formation of sulfates which are characterized by --C--O--S-- bonds and hence are labile to the aggressive effect of acids. Accordingly, the use of products such as these is confined to the neutral to mildly alkaline range.
Alternatively, the sulfonation reaction also be carried out with oleum, i.e. with sulfur trioxide which is dissolved in sulfuric acid in a concentration of up to 65% by weight. Although, in addition to the formation of sulfates, this process leads mainly to the formation of sulfonates having an acid-stable --C--S-- bond, it is attended by the serious disadvantage that the sulfuric acid used as solvent has to be neutralized together with the sulfonic acids obtained so that the products are burdened by an undesirably high electrolyte content which is problematical in many applications.
German patent application DE 12 46 717 describes the sulfonation of unsaturated fatty acid glycerol esters with gaseous sulfur trioxide in admixture with an inert gas. However, since undesirably strong discoloration of the products is observed in addition to sulfonation with increasing reaction temperature and quantity of SO.sub.3 and can lead to carbonization in cases where the sulfonating agent is used in relatively large quantities, the process is confined in its application to temperatures in the range from 0 to 20.degree. C. and to ratios of fatty acid ester to sulfur trioxide of 1:0.5 to 1:1.7. Accordingly, it is only possible in this way to obtain sulfonation products of unsaturated fatty acid glycerol esters which have a low content of organically bound sulfur.
Finally, German patent application DE 34 37 443 Al describes a process for reacting both unsaturated fatty acid glycerol esters and saturated fatty acid esters with gaseous sulfur trioxide. However, the disadvantage of this process is that the production of homogeneous mixtures of both components involves considerable outlay on equipment, in addition to which the sulfonation products have a high percentage content of .alpha.-fatty acid methyl ester sulfonates.

Process for the sulfonation of unsaturated fatty acid glycerol esters

Henkel Kommanditgesellschaftr auf Aktien


An embodiment of the invention provides a telecommunications method performed by a second telecommunications device. According to the embodiment, the second telecommunications device first tries to use a received part of a data block to decode the data block, wherein the received part is received from a first telecommunications device. Next, the second telecommunications device determines whether a code metric derived based on the received part indicates that the data block is decodable. If the code metric indicates that the data block is decodable, the second telecommunications device further determines whether a set of confirmation criteria is satisfied.

1. Technical Field
The invention relates generally to telecommunications, and more particularly, to telecommunications methods that increase the reliability of early termination of transmission.
2. Related Art
Telecommunications channels are frequently noisy and unreliable. As a result, if a first telecommunications device transmits M bits of data to a second telecommunications device without using any protection, where M is a positive integer, the second telecommunications device may fail to recover some of the M bits correctly.
To deal with this and other problems, the two telecommunications devices may use some methods to protect the data. For example, the first telecommunications device may encode the M bits of data into N bits of data that permits error correction, where N is a positive integer greater than M. Then, the first telecommunications device may transmit the N bits of data, rather than only the M bits of data, to the second telecommunications device. Even if the second telecommunications device recovers some of the N bits incorrectly, it may still decode the M bits of data accurately through error correction.
The N bits of data may be contained in a data block and correspond to a specific transmission time interval (TTI). For example, for speech data, the TTI may be 20 ms long and contain 30 slots; each of the slots may contain 2,560 chips. One of the first and second telecommunications devices may be a base station (BS) or a Node B while the other may be a mobile station (MS) or a piece of user equipment (UE). The aforementioned transmission may be uplink or downlink transmission.
As long as the second telecommunications device has at least P bits of the N bits of data correctly, where P is a positive integer equal to or greater than M and equal to or less than N, the second telecommunications device should be able to successfully decode the M bits of data. In other words, it's possible for the second telecommunications device to not receive the whole data block but still recover the M bits of data correctly. Therefore, if the second telecommunications device determines that it can decode the data contained in a data block not yet fully received, the second telecommunications device may disregard a remaining part (i.e. a not yet received part) of the data block. This may help the second telecommunications device save some energy and time. In addition, the second telecommunications device may transmit a positive early termination indicator (ETI) to the first telecommunications device, advising the first telecommunications device to not transmit a remaining part (i.e. a not yet transmitted part) of the data block. This may help the first telecommunications device to save energy and reduce interference to other second telecommunications devices.

Telecommunications methods for increasing reliability of early termination of transmission