A power supply system for supplying power to a system load is described. The power supply system includes a plurality of power supply modules. Each power supply module includes a power-generating module, a unidirectional device, and a fan. When the power-generating module is in normal operation, the power generated by the power-generating module is sent in one direction to the system load through the unidirectional device. When the power-generating module fails, the fan is powered from a terminal connected to the system load.

1. Field of Invention
The present invention relates to a power supply system. More particularly, the present invention relates to a power supply system having greater cooling ability.
2. Description of Related Art
An electronic system usually has a power supply for supplying power to the electronic system. Because the speed and complexity of electronic devices are increasing rapidly, the power consumed by electronic devices is getting higher and higher. Due to the large power consumption, heat generated by electronic devices has become a main problem for the stability and the life span of an electronic system. If an electronic device is working under an overly high temperature, it may suffer from the heat and may result in device failure. The life span may also be reduced.
Therefore, an electronic system that generates a large amount of heat usually uses fans to dissipate the heat. The fans can generate an air stream to carry the heat out of the electronic system and thus cool down the whole system. A larger electronic system, such as a file server, usually uses more than one power supply. A fan is usually powered by its corresponding power supply. If the power supply fails, the fan will not function. Then other fans have to increase their speed and performance to compensate for the loss of cooling capability. Increasing the rotation speed of a fan will cause large acoustic noise. Furthermore, speeding up a fan may reduce the life span of it. Therefore, there is a great need for having a new power supply system that can keep the fans operating even if one of the power supply modules fails.

Power supply system with high cooling capability


An electrode for an electric double layer capacitor in which resin is used as a starting material and the manufacturing cost is low and a method of manufacturing the same are disclosed. A method of manufacturing an electrode for an electric double layer capacitor containing carbonized resin includes heating resin at a temperature equal to or higher than the temperature for finishing endothermic reaction of the resin upon melting (softening to be fluidized) of the resin and equal to or lower than the temperature for starting oxidizing reaction in an atmosphere of a pressure range of 0.01 to 10 kg/cm2, cooling the temporarily baked resin to a normal temperature and powdering it, and manufacturing a molded carbon by heating the powdered resin at a temperature equal to or higher than the temperature for starting the oxidizing reaction of the resin after pressure molding or heating the powdered resin at a temperature equal to or higher than the temperature for starting the oxidizing reaction while pressurizing the temporarily baked powder resin. The electrode contains 10% or less of the ratio of the pores each having a pore size of 20 Angstrom or more to the entire surface area of the pores of the electrode.

1. (Field of the Invention)
This invention relates to an electrode for an electric double layer capacitor and a method of manufacturing the same and, more particularly, to an electrode for an electric double layer capacitor optimum for obtaining a large electrostatic capacity and a method of manufacturing the same.
2. (Description of the Prior Art)
Recently, an electric double layer capacitor using the storage of charge based on an electric double layer, i.e., a principle of an electric double layer has been developed and manufactured. Since this capacitor can obtain a large electrostatic capacity, the small-sized capacitor has been used for a back-up power source of a semiconductor memory for an electronic equipment and the large-sized capacitor has been used for the part of the utilization of an on-vehicle lead battery.
A method of manufacturing a molded unit of activated carbon comprising the first step of pressurizing carbon powder mixed with water under pressure of 50 kg/cm2 while heating the carbon powder to obtain powder activated carbon, and the second step of pressure molding the resultant powder activated carbon under the pressure of 50 to 800 kg/cm2 at a temperature of 700.degree. to 1,000.degree. C. to obtain the molded unit of the activated carbon as an electrode material for the electric double layer capacitor of this type was disclosed in Japanese Patent Application Laid Open No. 3-201,520(1991) by the same assignee as the present invention.
As a result of the research and development of an electrode for an electric double layer capacitor, the applicant of the present invention has also developed an electrode material in which pores are formed by heating polyvinylidene chloride resin in a non-oxidizing atmosphere and thereby generating atomic and molecular defects, and filed Patent Application Laid Open No. 7-24955 (1994). This material showed in the above Laid Open document is formed of a porous carbon material having very fine pores, which is an electrode material of much higher capacity than that of the conventional activated carbon.
Since the carbon powder is used as a starting material in the molding method disclosed in the above-described Japanese Patent Application Laid Open No. 3-201520 (1991), its volatile component which contributes to its solidification has been evaporated in the step of carbonizing, and hence difficult to be solidified. Thus, in the case of molding, large power or large energy is required. Hence, its manufacturing cost is high. Further, this method also has a problem of difficulty of increasing the molding density. In order to solidify the carbon powder, when binder is used, its electric capacity is reduced that much of the binder in the case of manufacturing the capacitor. When the resin of the material of the carbon is pulverized as it is, then molded and thereafter sintered, its volatile component is excessively much, and hence its shape cannot be maintained. Because the volatile component is evaporated in a large quantity at the time of baking, and its shape is collapsed by its evaporative power.
In other words, according to the conventional method, the volatile component is excessively much or little and not suitable, and hence the carbon powder cannot be sufficiently solidified.

Method for forming electrode using heating and pressurizing of a resin material and the electrode thus formed


Embodiments of the present disclosure relate to a binary clustered forward error correction encoding scheme. Systems and methods are disclosed that define binary clustered encodings of the media packets from which forward error correction (FEC) packets are computed. The different encodings specify which media packets in a frame are used to compute each FEC packet (a frame includes M media packets). The different encodings may be defined based on the quantity of media packets in a frame, M≤floor(2N), where each bit of the binary representation of N is associated with a different cluster pair encoding of the media packets. Each cluster pair includes a cluster for which the bit=0 and a cluster for which the bit=1. Computing FEC packets using at least two cluster pair encodings provides redundancy for each media packet, thereby improving media packet recovery rates.

Packet loss impairs multimedia streaming performance. Forward error correction (FEC) is a technique that may be used to mitigate network packet loss by enabling recovery of the lost packets. Conventional XOR-based FEC techniques often do not provide adequate redundancy to recover any packet in a frame (a frame includes M media packets). Redundancy may be improved by covering more media packets in a single FEC packet and/or computing (and transmitting) more FEC packets. Conventional techniques often provide limited coverage when multiple lost packets belong to the same media frame. Also, conventional techniques may simply transmit duplicate media packets to improve media packet recovery. There is a need for addressing and improving these issues and/or other issues associated with the prior art.

Forward error correction encoding using binary clustering


Provided is an optical information reading device that can reduce an installation load on a user, and can accurately read a code provided to each of various workpieces. A polarized illumination light source includes light emitters that irradiate the workpiece with illumination light through a polarization filter. A non-polarized illumination light source includes light emitters that irradiate the workpiece with illumination light without through a polarization filter. An imaging element is provided with a polarization filter having a polarization direction different from a polarization direction of the polarization filter of the light emitters. Either of the polarized illumination light source and the non-polarized illumination light source is used in accordance with the workpiece.

1. Field of the Invention
The present invention relates to a fixed optical information reading device of optical information reading devices that optically read information.
2. Description of Related Art
There are a handy-type optical information reading device that reads a code in a state where an operator holds the device in his or her hand, and a fixed optical information reading device that is fixed and reads information by moving an object with a code attached. A two-dimensional code reader (hereinafter, referred to as a reader) that reads a two-dimensional code such as a barcode, and a QR code (registered trademark) has been widely spread. One example of the above-described reader is described in JP 2011-76519 A. In JP 2011-76519 A and JP H7-282175 A, provision of a polarization filter in each of an illumination optical system and an imaging optical system is described.    Patent Literature 3: JP H10-287873 A
When a reader is downsized, an optical axis of an imaging element and an optical axis of an illumination system cannot but be made parallel to each other. This is because a distance between the optical axis of the imaging element and the optical axis of the illumination system cannot but be shortened. In the above-described reader, illumination light reflects at a surface of a workpiece (an inspection object product), and regular reflected light enters the imaging element, which makes it hard to read a two-dimensional code. Consequently, the reader needs to be installed with an optical axis of the reader inclined to a normal line of the surface of the workpiece so that the normal line and the optical axis do not coincide with each other. This is referred to as oblique attachment. The attachment of the reader in which the normal line of the surface of the workpiece and the optical axis of the reader are parallel is referred to as front attachment. If the surface of the workpiece is almost planar, inclining the optical axis to the normal line only by a recommended angle enables the two-dimensional code to be read accurately.
In recent years, the two-dimensional code has been printed on a surface (a casting surface) of a casting such as an engine block by laser marking or the like (so-called direct part marking (DPM)). Since as known well, minute irregularities exist on the surface of the casting, the front attachment brings about higher reading accuracy than the oblique attachment. Moreover, since the two-dimensional code is printed in various parts such as a surface (milled surface) of a workpiece subjected to milling, black resin, and a substrate, a proper reading method differs in the respective parts. Thus, a user needs to search for an installation angle suitable for each workpiece.
Moreover, in the oblique attachment, an image obtained by reading the two-dimensional code is distorted, which may cause a reading error. Thus, the front attachment makes it unnecessary to search for the installation angle, thereby reducing an installation load on the user. Moreover, the front attachment has an advantage that the image is not distorted.
As described in JP 2011-76519 A and JP H7-282175 A, the provision of the polarization filters can reduce influence of the regular reflected light even in the front attachment. However, the provision of the polarization filters disables the reader from reading a code provided by the direct part marking on the casting surface. While it can be considered to make the polarization filters detachable, labor for detachment newly occurs.


Silicone tube structures are formed having a particular dimensional accuracy. In one embodiment, a silicone tube structure can include an extruded hollow body having an inner bore. The extruded hollow body can have an inner diameter, an outer diameter, and a length of at least approximately 20 m. The extruded hollow body can also have a dimensional accuracy that is measured by the standard deviation of the inner diameter being no greater than approximately 0.8% of an average inner diameter of the extruded hollow body over the length. In an embodiment, the silicone tube structure can be cut to form a number of silicone tubes.

Many industries utilize tubing to dispense fluid or remove fluid. For example, in the medical industry, tubing is used to deliver fluid containing nutrients or medication to patients. Tubing can also be used in medical applications to remove fluid from patients and to drain fluid produced during some procedures. In certain applications, a specified amount of fluid is expected to be delivered or removed over a particular period of time.
In many cases, the medical and pharmaceutical industries utilize silicone tubing for the delivery and removal of fluids because silicone tubing is non-toxic, flexible, thermally stable, has low chemical reactivity, and can be produced in a variety of sizes when compared with tubing made from other materials. For example, silicone tubing may be used with enteral pumps and infusion pumps to provide nutrients, medication, fluids, and the like to patients.
Medical devices utilizing silicone tubing are expected to deliver or remove fluids at a specified rate. To illustrate, an enteral pump can be expected to deliver a selected amount of nutritional fluid to a patient in a particular period of time, such as 50 mL/hour. The dimensions of the silicone tubing coupled to medical devices can affect the flow rate of fluid pumped by the devices. Consequently, medical and pharmaceutical industries would benefit from cost effective tubing solutions that provide a high level of dimensional accuracy.
Typically, silicone tubing is formed by one of two processes, extrusion or molding. During extrusion, a flowable raw material is forced through a die and is then solidified. Existing extrusion processes have limited process control, and while they can achieve limited lengths of dimensionally accurate tubing, extended runs cannot be achieved.
Another approach to tube formation is molding. However, molded tubes have physical artifacts that can be undesirable, such as parting lines and/or knit lines that form when mold components meet. Additionally, the processes used to form molded tubes can be expensive and lack flexibility. Accordingly, manufacturers of tubing can be reluctant to utilize molding processes to produce silicone tubing due to the expense and lack of flexibility of these processes and/or the undesirable appearance of visible artifacts produced by these processes. Additionally, molding cannot generally form long lengths of tubing, such as on the order of several meters and above.
Some previous attempts to provide dimensionally accurate tubing are described in the following patents and patent applications.
US Patent Application Publication No. 2001/0022411 describes catheters or other structures, such as hoses, balloons, etc., that are formed by immersing a mandrel into a number of baths. The structures can be made of silicone rubber and may have multiple layers. This application describes catheters having an overcoat layer with a preferred thickness of 0.35 mm±0.06 mm (0.0175 in.±0.0025 in.) and preferred inner layer dimensions of 0.89 mm±0.1 mm (0.035 in.±0.004 in.).
US Patent Application Publication No. 2003/0030165 describes medical catheters and tubing that are produced for intravascular procedures. The materials are preferably thermoplastics. Proximal and distal portions of the tubing have a differing stiffness and may be formed from different materials. The catheters are formed through extrusion with a melt pump that is preferably a displacement pump. Outside diameters of the tubing are to be minimized while maximizing the inside diameter. Desired dimensional tolerances for the inside diameter are about 0.0005 inches and about 0.001 inches for the outside diameter.
US Patent Application Publication No. 2003/0132552 describes tubing formed from a system that compares measured dimensions against stored target dimensions to generate feedback to adjust process variables. The melt is composed of a thermally extrudable material. Error tolerances of ±1 micron are based on the number of measurements taken by a laser gauge per second and the extrusion speed.
US Patent Application Publication No. 2006/0255497 describes thermoplastic tubing formed from an extrusion process. Tolerances for the tubing are produced by exerting pressure on the tube using rollers situated at an entry to a sizing device. A fluctuation in thickness is described as 0.1 mm for a tube having a diameter of 100 mm.
US Patent Application Publication No. 2011/0005661 describes medical tubing formed from a number of ring-shaped elements that are fused together. The process includes wrapping a stainless steel wire around a mandrel. A silicone tube may be placed around the wound coil outer diameter. Tolerances on the inner diameter can be held to 0.001 in. or less with a comparable tolerance for the outer diameter. The inner diameter may be from 0.026 in. to 0.75 in.
U.S. Pat. No. 5,759,647 describes a tubular article formed by injection molding a thermoplastic synthetic resin. The tube may have a length from several cm to more than one meter and a wall thickness ranging from less than one mm to several cm. In some cases, tubes can have a wall thickness of 2 mm with a maximum difference of wall thickness of 0.1 mm or 0.2 mm.
U.S. Pat. No. 6,508,972 describes rubber tubing formed via extrusion with a gear pump. The tubing is cut to form gaskets. A goal of the system is to produce a gasket with outer diameters and inner diameters deviating by ±0.005 in.
U.S. Pat. No. 5,948,332 describes thermoplastic material extruded to form tubing. Heating elements are provided that modify the temperature of the tubing during the extrusion process. The regulation of the temperature can exert a particular pressure on the tubing as it moves over the mandrel to produce a preferably uniform wall thickness.
U.S. Pat. No. 5,820,607 describes a multilayered tube having a hollow inner layer surrounded by a pharmacologically active substance. One or more of the layers may comprise silicone. The pharmacologically active substance may be suspended in one layer and migrate to the outer surface of the tube, the inner surface of the tube, or both. The tube may be extruded or molded and control of the overall diameter of the device is preferred. Examples of outer diameters include 3.175 mm and 1.7 mm, examples of inner diameters include 1.981 mm and 0.8 mm, and examples of layer thickness range from 0.1 mm to 3 mm.
US Patent Application Publication No. 2008/0248226 describes multi-layered tubes that are formed with a heat-shrinkable fluoropolymer liner and extruding an elastomeric cover, such as a cover having a silicone formulation, over the liner. The liners are paste extruded. A total thickness of the tube may be between 3 mils to about 50 mils and a thickness of the liner can be between 1 mil to about 20 mils The tubes are tested for length of life and tensile modulus.
Although some of the above-described documents describe a desired tolerance for certain dimensions, the prior art does not fully enable a high level of process control. Additionally, the technologies described in the foregoing prior art documents do not achieve certain dimensional tolerances over extended lengths of tubing or with respect to a specified number of tubes, and certainly not over extended lengths of tubing or tube segments therefrom.
The use of the same reference symbols in different drawings indicates similar or identical items.

Silicone tubing and method for making and using same

SAINT-GOBAIN PERFORMANCE PLASTICS CORPORATION


A staple or nail gun assembly includes a staple or nail gun, a cap feeding device and a cap having a peripheral rim disposed on its underside, a marginal edge on its upper side adjacent a central portion having the shape of a truncated cone. The staple or nail gun and the cap feeding device are generally disposed at opposite ends of the handle of the staple or nail gun. The cap feeding device includes a base, a cap container and a shuttle, and feeds caps sequentially as they are affixed by the gun. The caps are coaxially stacked by means of a coaxial plastic cord or wire with retaining means at the respective ends or in a tubular container with a flanged end. The caps may also be stacked on a rod or held together by melting.

Automatic nail guns, powered by compressed air or electricity, are used, for example, to attach roofing material, such as tarpaper, to the roof of a house. A generally flat cap is often used with each nail. A nail penetrates the cap and the tarpaper and protrudes into the underlying roof structure, attaching the roofing material to the roof surface.
Typically, an operator must manually place and hold a cap under the nose of a nail gun and then trigger the gun to drive a nail through the cap into the roof structure. The manual placement of caps presents a serious safety hazard to the operator because the operator's hand is close to the nose of the gun when a nail is driven through the nose of the gun. In addition, manual placement of caps is time-consuming and inefficient.
A cap feeding device may be employed to reduce the risk associated with manual placement of caps and to improve the efficiency of roofing operation. The cap feeding device automatically places a cap under the nose of a nail gun, and then the nail gun drives a nail through the cap and into the underlying roof structure.
A conventional cap feeding device generally includes a cap container and a base having a channel. The base extends between the cap container and a position under the nose of the nail gun. Caps are fed into the channel of the base from the cap container and pushed to the position under the nose of the nail gun. When the gun is triggered, a nail penetrates and dislodges the cap under the nose of the nail gun and protrudes into the underlying roof structure. The feeding of the caps under the nose of the nail gun is coordinated with the ejection of the nails through the nose of the nail gun, so that a cap is placed under the nose of the gun before the gun is triggered to expel a nail.
Conventional cap feeding devices have a number of drawbacks. For example, conventional cap feeding devices are generally heavy, putting additional stress on the operator's hand holding the nail gun. Also, many conventional cap feeding devices can only be installed close to the front end of a nail gun, making the nail gun not only heavy but also unbalanced with most of the weight placed at the front end of the gun. This makes the nail gun difficult to handle and may put stress on the operator's hand and wrist. In addition, with so many components placed near the nose of the gun, it is difficult to see the position of the nose of the gun, making a precise placement of a nail difficult.
The conventional cap feeding devices are installed close to the front end of the gun because designers need to place a conventional cap container close to the nose of the gun to reduce the weight of the cap feeding device. The reason is that in many devices a cap is pushed directly from the cap container to a position under the nose of the nail gun. Thus, if the cap container is far from the nose of the gun, a long shuttle is needed to push a cap from the container to the position under the nose of the nail gun through the channel of the base. In addition, an actuator, such as an air cylinder, with a long displacement is also needed to drive the shuttle. The displacement of the actuator should be about the same as the distance between the cap container and the nose of the nail gun. A long shuttle and actuator increase the weight and size of the cap feeding device. With the cap feeding device placed near the nose of the gun, the shuttle and actuator, thus the cap feeding device can be made lighter, smaller and less expensive.
Caps for automatic nailing guns are available in a wide variety of shapes and packaging. Most caps for felt roofing products are sold in bulk and must be applied singularly with each nailing operation. Automatic nailers for roofing including magazines containing caps are available, however, for a variety of reasons, have not found wide usage. Most of the disadvantages of nailers including magazines of roofing caps are related to the unwieldiness of the apparatus, and somewhat to the lack of reliability or uniformity of operation. Automatic nailing machines adapted for installing roofing caps are illustrated in such as U.S. Pat. No. 5,947,362 to Omli; U.S. Pat. Nos. 5,445,297; 5,184,752; and 5,042,142. None of these prior automatic roofing nailers provide the versatility and ease of usage, incorporate the use of an inventive roofing cap or disclose a convenient packaging of stacked caps which may be readily inserted into the magazine of an automatic roofing nailer. Not only does the cap of the present invention lend itself to convenient packaging, but it also provides superior reliability in its ability to be routinely fed through the magazine chamber of the nailing machine for reliable operation, but the configuration which provides the fit, reliability and stackability also provides a cap which delivers superior performance in holding the material to be attached such as roofing felt to the roof or siding materials.


Selective antagonists of A2A adenosine receptors like those of formula I are provided, wherein Y forms a ring.

Parkinson's disease is the second most common neurodegenerative disorder and affects over 1 million people in North America.2 The pathological process, degeneration of the dopaminergic neurons in the substantial nigra, causes profound depletion of striatal dopamine and motor impairment. This insight led to the introduction of L-dopa as a dopamine-replacement treatment for PD.3 Today, L-dopa continues to be the "Gold Standard" treatment for the motor symptoms of PD.4,5 Despite the considerable symptomatic relief it affords, long-term treatment with L-dopa has major limitations.6 After five to ten years of treatment with L-dopa, up to 60% of patients experience loss of L-dopa effectiveness and some debilitating complications,7,8 notably, an "on" and "off" motor fluctuation and involuntary choreic or dystonic movements, dyskinesia. This has become the limiting factor in management of patients in the later stages of PD.9 The development of dyskinesia might reflect desensitization of dopamine receptors.10 Most importantly, there is no clear evidence that L-dopa slows or halts the degeneration of dopaminergic neurons. In fact, in vitro cell culture studies suggested that dopamine and its oxidative metabolites are toxic to dopaminergic neurons, and raised the concern that L-dopa may actually accelerate the degeneration of dopaminergic neurons. Because of this concern, many clinicians avoid prescribing L-dopa early in the course of PD.11
These major limitations of L-dopa therapy are linked to the activation of dopamine receptors. This has prompted a search for alternative treatment for PD not targeting the dopaminergic system.12 Striatal neuromodulators and transmitters other than dopamine are increasingly appreciated as critical regulators of motor function and offer new therapeutic opportunities to complement dopamine-replacement.
Over the last 10 years, the A2A adenosine receptor (A2AAR) has received increasing attention as a treatment for PD.13,14 This contention is based on our understanding of the role of the A2AAR in the basal ganglia and on the recent development of new, more selective A2AAR antagonists. Anatomical, neurochemical and behavioral evidence of adenosine-dopamine interactions underlie this new therapeutic approach.15-17 Anatomically, A2AAR density is high in the striatum, where receptor mRNA is co-expressed with D2 receptor mRNA in the striatopallidal neurons.18-20 This unique cellular distribution of A2A receptors suggests that A2A receptor antagonists can selectively modulate the "indirect" striatopallidal pathway to affect motor activity. At the neurochemical level, activation of the A2AAR reduces the binding affinity of D2 receptors in the striatum,21 and antagonizes many neurochemical and cellular changes brought about by the activation of striatal D2 receptors, including release of acetylcholine and GABA and expression of c-Fos. Furthermore, behavioral studies have demonstrated that the unselective adenosine antagonists caffeine and theophylline stimulate locomotor activity22,23 whereas the unselective agonist NECA24 inhibits spontaneous locomotor activity as well as motor activity induced by dopamine agonists. Thus, A2AAR agonists and antagonists function as dopamine antagonists and agonists, respectively, in modulating motor activity. The three possible mechanisms have been proposed to explain for motor enhancement by the A2A antagonists: (1) a direct receptor-receptor (A2A-D2) antagonistic interaction,25,26 (2) an opposing but independent of A2A and D2 receptor signaling27-29 or (3) A2AAR modulation of GABA release in the basal ganglia.30-32 These receptors also form A2AAR-D2 heterodimers,33 but how dimerization affects receptor function is unclear.
A2A Receptor Antagonists May Offer Multiple Therapeutic Benefits for PD Patients
First, A2A antagonists stimulate motor activity in normal as well as dopamine-depleted animals. In rodent models of PD, unselective adenosine antagonists (caffeine and theophylline)22,34 and the A2AAR-selective antagonists SCH58261, KW6002 and CSC can reverse motor deficits induced by MPTP, 6-hydroxydopamine, haloperidol or reserpine35-41 as well as by genetic deletion of D2 receptors.42 More recently, the A2A antagonists KW6002 reversed motor deficit in MPTP-treated non-human primates.43,44 Furthermore, A2A antagonists can stimulate motor activity when combined with sub-threshold doses of dopaminergic agents such as L-dopa or D1 and D2 agonists such as aporphormine or quinpirole.45 For example, combining KW6002 with L-dopa reduces the dose of L-dopa, thereby reducing the complications associated with L-dopa. In contrast to some non-specific adenosine antagonists or some dopamine agonists, motor stimulation was observed after acute treatment and persisted following treatment continued for 15 days.44,46,47 Thus, tolerance to the motor stimulant effect of A2A antagonists did not develop.
Second, studies of the MPTP-treated monkey model of PD revealed a novel feature of A2A antagonists, namely, stimulation of motor activity without dyskinesia.43,44,48 In contrast to L-dopa, repeated treatment with KW6002 reversed the motor deficit but did not induce dyskinesia, even in monkeys primed with L-dopa. Further, our recent findings in A2AAR knockout mice suggest that development of behavioral sensitization by chronic treatment of L-dopa requires activation of the A2AAR. Genetic inactivation of the A2A receptor attenuated L-dopa-induced rotational behavior.49 This is consistent with a recent study showing that co-administration of KW6002 with apomorphine to MPTP-treated monkeys completely abolished the development of apomorphine-induced dyskinesia.50 Further studies are warranted to explore the molecular mechanism underlying this novel aspect of A2AAR function.
Third, accumulating evidence suggests that the specific inactivation of A2AARs consistently attenuates brain damage induced by ischemia51,53 and excitoxicity,54,55 as well as in animal models of Huntington's disease56 and Alzheimer's disease.57 The neuroprotection by A2AAR antagonists has been recently extended to a rodent model of PD. Co-administration of A2AAR antagonists, such as CSC, DMPX, SCH58261 and KW6002 (but not the A1AR antagonist DPCPX) attenuated dopaminergic neurotoxicity in several neurotoxin models of PD.58 A2AAR antagonists provided not only functional protection (such as reduced dopamine content and expression of molecular markers for the dopaminergic terminals), but also reduced the loss of dopaminergic neurons in substantia nigra in both MPTP- and 6-OHDA models of PD.59,60 Likewise, knockout of A2AARs attenuated MPTP-induced dopaminergic neurotoxicity in mice.59 Together with the demonstration of neuroprotection by A2AAR antagonists against a wide range of neuronal injury models. These results raise the possibility that A2A antagonists may offer a neuroprotection, slowing or even halting degeneration of dopaminergic neurons.
Finally, in contrast to the widespread distribution of other neurotransmitter receptors, for example, glutamate receptors, the expression of the A2AAR is almost exclusively in striatum, which might allow selective modulation of dopamine-mediated motor pathways without serious side effects due to drug actions outside the basal ganglia (a serious problem for drugs such as glutamate antagonists). It is important to emphasize that ambient adenosine levels and A2AAR density are normal in PD patients,61 indicating that A2A antagonists might remain effective, even in the later stages of PD.
The prospective use of A2AR antagonists as potential neuroprotective agents against dopaminergic neuron degeneration was markedly enhanced by a May 2000 report of an epidemiological study of the relationship between caffeine and PD. Ross et al described a large prospective study with a 30-year follow-up of 8004 Japanese-American men that showed that in this population there is an inverse relationship between caffeine consumption and the risk of developing PD.62 Two other ongoing, large-cohort studies (Heath Professional Follow-up Studies and Nurse's Heath Study) involving 47,351 men and 88,565 women also showed that moderate caffeine consumption (3–5 cups/day) reduced their risk of developing PD.63 Thus, the inverse relationship of caffeine consumption and the risk of developing PD seem firmly established by these two large, prospective epidemiological studies. These results are consistent with the animal studies showing neuroprotection by A2AAR antagonists and strongly argue that A2A antagonists including caffeine may offer an opportunity to slow down or halt the degeneration of dopaminergic neurons.
Initial clinical trial results of KW6002 indicated that (20–80 mg/day) enhanced motor activity in one study and potentiated a motor stimulant effect by low (but not high) doses of L-dopa in another study.64,65 KW6002 was well tolerated and had few side effects. Unfortunately, trials with KW6002 have been stopped because this compound was found to produce a long-term toxicity in rats. Hence, there is a pressing need to develop alternative molecules that lack toxicity.
The first relatively selective A2AAR antagonists, the 8-styrylxanthines, appeared about ten years ago. This class includes KW-6002, which has low nanomolar affinity for the A2AAR and >100-fold selectivity for the A2AAR over the A1AR. KW-6002, entered clinical trials in 2002 as an agent for the treatment of PD.1,66 SCH58261, a pyrazolo[4,3-e]-1,2,4triazolo[1,5-c]pyrimidine was a prototype for a series of second-generation derivatives that appeared over the next several years. These, too, had low nanomolar affinity and good selectivity for the A2AAR in vitro.67 The third class of antagonists to appear, the 1,2,4-triazolo[4,5-e]-1,3,5-triazines, was typified by ZM241385, which was active at the A2AAR in the sub-nanomolar range but less selective, interacting with A2BAR as well.68 These potent A2A antagonists have been important research tools, greatly facilitating pharmacological investigations of A2AAR function in vitro as well as in vivo significantly enhancing our understanding of the neurobiology of the A2AAR. However, each of these antagonists has important drawbacks. KW-6002 is light-sensitive, undergoing photoisomerization from the active E-isomer to the 800-fold less active Z-isomer.69 SCH58261 is very poorly soluble and even its second-generation derivatives have marginal bioavailability.70 As mentioned above, ZM241385 is unselective and, additionally, has poor bioavailability. Other nitrogen heterocycles such as the 1,2,4-triazolo[4,3-a]quinoxalin-1-ones71 and the oxazolo[4,5-d]pyrimidines from ICI are also unselective, and their bioavailability is unknown. Therefore a continuing need exists for compounds that are selective A2A AR antagonists.

Abstract: The novel A2A blockers are useful for the treatment of Parkinsons disease and other diseases.


A method includes: obtaining a signal strength sequence of signals detected by a user terminal during a travel route. The detected signals are originated from signal sources disposed at different locations in the travel route, and the different location includes one or more vehicles or one or more stops. The method further includes: extracting, from the signal strength sequence, a first sequence fragment corresponding to a signal transmitted by a signal source disposed at a vehicle; determining a travel time duration of the user riding on the vehicle according to a signal strength value and time stamp information of the first sequence fragment.

Vehicles such as buses and subway trains proliferate in cities with the development of vehicle technologies and progressive city planning. As vehicles grow in number, how to schedule vehicles in time to alleviate traffic congestion becomes an important research topic.
Scheduling is inevitably inaccurate when vehicles are scheduled according to people's historical experience, for example, when it is determined according to historical experience whether it is necessary to schedule more buses. Therefore, it is necessary to provide a technical solution to accurately determine a vehicle scheduling strategy.

Method and apparatus for determining vehicle scheduling strategy


A control system controls adaptively an operation of a vapor compression system. The control system includes a memory for storing a mapping relationship between control inputs of the vapor compression system, and a processor for executing a supervisory controller and an optimization controller. The supervisory controller controls the operation of the vapor compression system using a set of control inputs selected according to the mapping relationship. The optimization controller modifies the mapping relationship in response to the operation of the vapor compression system.

Vapor compression systems, such as heat pumps, refrigeration and air-conditioning systems, are widely used in industrial and residential applications. The introduction of adjustable actuators such as variable speed compressors, variable position valves, and variable speed fans to the vapor compression cycle has greatly improved the flexibility of the operation of such systems. It is possible to use these new components to improve the efficiency of vapor compression systems by controlling the components correctly.
An operation cycle of the vapor compression system starts by compressing the refrigerant to a high-temperature, high-pressure vapor state, after which the refrigerant flows into a condenser. Because the air flowing over the condenser coils is cooler than the refrigerant, the refrigerant cools to form a high-pressure, low-temperature liquid when exiting the condenser.
Then, the refrigerant passes through a throttling valve that decreases the pressure. The low-pressure refrigerant boils at a lower temperature, so the air passing over the evaporator coils heats the refrigerant. Thus, the air is cooled down, and the low-pressure liquid refrigerant is converted to a low-pressure vapor. This low-pressure, low-temperature vapor then enters the compressor, and the operation of the vapor compression system is continues to cycle.
The operation of the typical vapor compression system is affected by a set of environmental parameters, such as thermal load on the system as well as air temperatures at an evaporator and a condenser. Some of these environmental parameters, such as the indoor temperature, have a desired value, i.e., a setpoint, for users of the vapor compression system. For example, the setpoint can be one variable, e.g., the indoor temperature. Also, the setpoint can be a set of multiple variables, such as the temperature and relative humidity of the indoor air.
The operation of the vapor compression system is also defined by a set of thermodynamic parameters of the refrigerant, such as an evaporating pressure, the amount of superheat at the evaporator outlet, condensing pressure, and the amount of cooling at the condenser outlet. The setpoint can be provided for both the environmental and the thermodynamic parameters.
FIG. 1 shows a conventional vapor compression system 100 including an evaporator fan 114, a condenser fan 113, an expansion valve 111, and a compressor 112. The system can be controlled by a controller 120 for accepting setpoints 115, e.g., from a thermostat, and inputs from a sensor 125, and outputting a set of control signals for controlling operation of the components. The controller 120 is operatively connected to a set of control devices for transforming the set of control signals to a set of specific control inputs for corresponding components. For example, the controller is connected to a compressor control device 122, to an expansion valve control device 121, to an evaporator fan control device 124, and to a condenser fan control device 123.
The controller controls operation of the vapor compression system such that the setpoint values are achieved for a given heat load. For example, a speed of the compressor 112 can be adjusted to modulate a flow rate of a refrigerant. The speed of the evaporator fan 114 and the condenser fan 113 can be varied to alter heat transfer coefficients between air and heat exchangers. The change in the expansion valve 111 opening can directly influence a pressure drop between the high-pressure and the low-pressure in the vapor compression system, which, in turn, affects the flow rate of the refrigerant, as well as superheat at the corresponding evaporator outlet.
In most vapor compression systems, the controller 120 issues commands to various control devices such as the condenser fan control device 123, the compressor control device 122, the expansion valve control device 121, or the evaporator fan control device 124. The objective of the controller is to cause the vapor compression system to track the setpoints 115 such as a desired room temperature or superheat temperature. The controller uses information from sensors 125.
Vapor compression systems are known to consume large quantities of energy, and therefore are costly to operate. Accordingly, it is desired to determine the set of control inputs that optimizes a performance of the vapor compression system. A number of methods for controlling operations of the vapor compression system are known.
For example, one method determines optimal energy consumption by comparison of operation of the vapor compression system controlled by modulating the speed of the condenser fan. However, large changes in the cooling load might result in suboptimal energy consumption because the system does not apply sufficient adjustments to the speed to determine the optimal value of the speed.
Another method for controlling a vapor compression system considers the possibility of sudden change in the environmental or thermal load requirements, monitors the vapor compression system in real-time, and determines, based on these real-time measurements, a set of parameters to enable the system to operate at maximum coefficient of performance. However, that method is time consuming, and requires substantial real time computational resources.
Another method first determines amount of heat flow across an evaporator or a condenser. Next, the amount of heat flow is used to determine the set of optimal control inputs. As the amount of heat flow is directly related to the operation of the vapor compression system, the determination of the heat flow is difficult to avoid. However, there are applications in which it is desired to determine the optimal set of control inputs without determining the amount of heat that the vapor compression system needs to transfer in accordance with a desired setpoint.
Yet another method reduces energy consumption of cold water or hot-water in the air conditioner by measuring the room temperature, and retrieving a value of a valve opening from a valve opening table using the room temperature as an index. However, conventional vapor compression systems typically have number of different components, including but not limited to the valve, which need to be controlled concurrently. Moreover, that method determines the valve opening based on an outside environment conditions only, which are not always optimal.
Accordingly, there is a need for a control system and a method for controlling operation of the vapor compression system such that heat load of the operation is met and a performance of the system is optimized.
Also, vapor compression systems are widely deployed in many environments. Therefore it is desirable to adapt the control system to maintain optimal efficiency of the vapor compression system for various thermodynamic environments and conditions.
Furthermore, it is well known that the characteristics of the vapor compression system vary over time. The refrigerant can slowly leak out of the system, and accumulation of debris on the heat exchangers can significantly alter the heat transfer. Therefore, it is also desirable to provide such control system that optimizes the performance of the system adaptively in consideration of those changes in system behavior.

Adaptive control of vapor compression system

Mitsubishi Electric Research Laboratories, Inc.


[PROBLEMS] To provide a reconfiguration controller of an optically reconfigurable gate array for correctly and reliably writing various types of logical operation circuits of an optically reconfigurable gate array and performing high-speed logical operation by quickly starting up the circuits. [MEANS FOR SOLVING PROBLEMS] A reconfiguration controller comprises a laser array (1) for producing a laser beam (1a) to serve as a reproducing beam and applying the laser beam (1a), a hologram memory (2) for outputting an optical pattern (2a) when receiving the laser beam (1a) according to pre-stored recording information and outputting a control signal light (2b) relating to optical reconfiguration by the optical pattern (2a), an optically reconfigurable gate array (3) for reconfiguring arrayed logical operation cells into various logical operation circuits according to the outputted optical pattern (2a), and outputting an optical control signal (S3) from the control signal light (2b), and a reproduction light application control means (4) for controlling the application of the laser beam (1a) emitted from the laser array (1) according to the optical control signal. Therefore, optical pattern application can be performed according to the optical control signal at a reconfiguration time adapted to any of various logical operation circuits sequentially reconfigured by the optically reconfigurable gate array. Consequently, correct and reliable write of any one of various types of logical operation circuits can be performed without any write error, and such various types of logical operation circuits can perform logical operation sequentially at high speed.

Conventionally, there is this kind of reconfiguration controlling apparatus for the optically reconfigurable gate array as disclosed in JP-2002-353317 A (which is referred to as Patent Document 1 hereinafter), JP-2005-051059 A (which is referred to as Patent Document 2 hereinafter) and Article "Improvement of Reconfiguring Speed of ODRGA Using Plural VSSEL's by Motoji Miyano, Minoru Watanabe and Fuminori Kobayashi" in the Institute of Electronics, Information and Communication Engineers (which is referred to as Non-Patent Document 1). FIG. 12 shows a schematic arrangement view of the reconfiguration controlling apparatus for the optically reconfigurable gate array, as disclosed in the aforesaid Patent Documents 1 and 2; FIG. 13 shows an operational flowchart of the reconfiguration controlling apparatus for the optically reconfigurable gate array, as disclosed in the aforesaid Patent Documents 1 and 2; and FIG. 14 shows a prior art schematic arrangement view of the aforesaid. Non-Patent Document 1.
In an arrangement of the reconfiguration controlling apparatus for the optically reconfigurable gate array according to the invention disclosed in the aforesaid Patent Document 1, when an optical reconfiguration type gate array 3, in which logical arithmetic operation cells and light receiving elements for setting an arithmetic program to the logical arithmetic operation cells are mounted on a planar chip, is reconfigured, a hologram memory 2 serving as an optical memory means, which is opposed to the optical reconfiguration type gate array 3, is irradiated with laser lights 1a to thereby emit reproduction lights therefrom, and the reproduction lights are simultaneously projected on the light receiving elements of the optical reconfiguration type gate array 3 as a light pattern 2a of optical signals according to the arithmetic program.
Like this, by simultaneously projecting the light pattern 2a of the optical signals on the plurality of light receiving elements mounted on the planar chip of the optical reconfiguration type gate array 3, it is possible to reconfigure the logical arithmetic operation cells of the optical reconfiguration type gate array 3 as a logical arithmetic operation circuit.
Also, the reconfiguration controlling apparatus for the optically reconfigurable gate array according to the invention disclosed in Patent Document 2 includes a hologram memory 2 serving as an optical memory means, which is placed above an upper surface of an optically reconfigurable gate array 3, a laser array 1 such as a planar light emission laser, which serves as a reproduction-light-causing irradiation means, to thereby irradiate the hologram memory 2 with laser lights 1a serving as reproduction-light-causing irradiation lights, and a reproduction-light-causing irradiation control means 4 such as a reproduction-light-causing irradiation control circuit for controlling the laser lights 1a of the laser array 1, which serve as the reproduction-light-causing irradiation lights.
The laser array 1 is a light source for generating the reproduction-light-causing irradiation lights to reproduce a piece of information regarding the optical pattern 2a which is recorded in the hologram memory 2. An irradiation angle control section 50 is provided on an irradiation face of the laser array 1 to control an irradiation angle of the reproduction-light-causing irradiation lights to the hologram memory 2. The irradiation angle of the laser lights 1a serving as the reproduction-light-causing irradiation lights is varied over time in synchronization with an operation of the optical reconfiguration type gate array 3. A control of the irradiation angle of the laser lights la, i.e., the reproduction-light-causing irradiation lights, is carried out by controlling the irradiation angle control section 50 with the reproduction-light-causing irradiation control means 4.
The laser lights 1a serving as the reproduction-light-causing irradiation lights, with which the hologram memory 2 is irradiated by the laser array 1, pass through the hologram memory 2 so as to be transformed into the optical pattern 2a of reproduction lights. Namely, a mask pattern, which is recorded as a hologram in the hologram memory 2, is reproduced, and the reproduced lights define the optical pattern 2a. Then, the optical pattern 2a is projected on the optical reconfiguration type gate array 3. The optical reconfiguration type gate array 3 carries out a photoelectric conversion to the optical pattern 2a to thereby reconfigure a logical arithmetic operation circuit in correspondence to the optical pattern 2a.
Next, an operation of the reconfiguration controlling apparatus for the optically reconfigurable gate array as disclosed in the aforesaid Patent Documents 1 and 2 will now be explained on the basis of FIG. 13. In this drawing, when it is determined that a boot-up signal of the reconfiguration controlling apparatus for the optically reconfigurable gate array is input to the reproduction-light-causing irradiation control means 4 (step 11), the reproduction-light-causing irradiation control means 4 outputs a light emission control signal S41 to the laser array 1 (step 12). The light emission control signal S41 is constituted so as to have a data content of a reconfiguring time which is set as the maximum reconfiguring time which is required of one of logical arithmetic operation circuits to be reconfigured by the hologram memory 2.
The laser array 1, to which the aforesaid light emission control signal S41 is input, emits laser lights 1a according to the reconfiguring time specified by the light emission control signal S41, and the hologram memory 2 is irradiated with the emitted laser lights 1a (step 13). Due to the irradiation of the hologram memory 2 with the laser light 1a, the hologram memory 2 projects an optical pattern 2a on the optical reconfiguration type gate array 3 based on a piece of record information previously stored therein (step 14).
The reproduction-light-causing irradiation control means 4 counts a projection time of the optical pattern 2a from the start of the projection of the optical pattern 2a (step 15), and then it is determined whether the counted projection time has exceeded the maximum value among the optical reconfiguring times which is set by the light emission control signal S41 (step 16). When it is determined that the counted projection time has not exceeded the maximum value, the control returns to step 13, and then the routine comprising the steps concerned is repeated.
At step 16, when it is determined that the counted projection time has exceeded the maximum value, a logical arithmetic operation circuit on the optical reconfiguration type gate array 3, which corresponds to the reconfigured circuit pattern concerned, is driven, and a logical arithmetic operation is executed upon inputting input data S1 to the driven logical arithmetic operation circuit, so that output data S2 is output as a result of the logical arithmetic operation from the optical reconfiguration type gate array 3 (step 17). Then, it is determined whether the logical arithmetic operation concerned has been completed in the driven logical arithmetic operation circuit (step 18). When it is determined that the logical arithmetic operation has been completed, it is further determined whether all logical arithmetic operations have been completed in logical arithmetic operation circuits, which would be optically reconfigured by the reproduction-light-causing irradiation control means 4 (step 19). At step 19, when it is determined that all the logical arithmetic operations have not been completed, the control returns to step 12, and then the routine comprising the steps concerned is repeated to optically reconfigure a next logical arithmetic operation circuit.
The projection of an optical pattern 2a is carried out over the sufficient period of time, during which each of all logical arithmetic operation circuits can be reconfigured in the optical reconfiguration type gate array 3, i.e., over the reconfiguring time which is set by the light emission control signal S41.
On the other hand, the invention described in Non-Patent Document 1 has an arrangement in which laser light beams are emitted from two planar emission lasers 21 and 22 defining a quasi hologram memory 2, and are made incident on an optical reconfiguration type gate array 3 formed by a single VLSI, through the intermediary of an optical system 23, thereby carrying out an optical reconfiguration. With this arrangement, it is possible to improve a reconfiguring speed because photodiodes on the optical reconfiguration type gate array 3 can be illuminated with a large amount of laser light.
In the invention having the above-mentioned arrangement, the optical reconfiguration type gate array 3 is defined as the VLSI having an 4-bit up/down counter mounted thereon. A case where the 4-bit up/down counter was driven with the irradiation using only the single planar emission laser 21 (or 22) was compared with a case where the 4-bit up/down counter was driven with the irradiation using both the planar emission lasers 21 and 22. When only the single planar emission laser 21 (or 22) was used, the counted value was 580 [μ sec.] (or 1340 [μ sec.]). In contrast, when both the planar emission lasers 21 and 22 was used, the counted value was 340 [μ sec.]. It was confirmed that the optical reconfiguring speed could become higher when both the planar emission lasers 21 and 22 was used.
In each of the above-mentioned reconfiguration controlling apparatuses for the optical reconfiguration type gate array, it is possible to carry out a highly quick writing in parallel in the VLSI of the optically reconfigurable gate array 3, and there is an advantage that the hologram memory 2 can store a large number of circuit patterns to be reconfigured (for example, on the order of 100).                Patent Document 1: JP-2002-353317 A        Patent Document 2: JP-2005-051059 A        Non-Patent Document 1: Article "Improvement of Reconfiguring Speed of ODRGA Using Plural VSSEL's by Motoji Miyano, Minoru Watanabe and Fuminori Kobayashi" in the Institute of Electronics, Information and Communication Engineers

Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof


A linear regulator for outputting a regulated voltage with improved rejection of high frequency components in the power supply. The linear regulator includes an op-amp connected in a linear feedback loop to drive first and second current legs based on a voltage reference. An output driver includes a load capacitance across which the regulated voltage is output, and further includes a ratio-driven current mirror having a mirror ratio defined by relative sizes of active devices in the first and second current legs, as compared with relative sizes of active devices in the output driver. Because the output driver and its load capacitance are provided outside the linear feedback loop, large values for the load capacitance can be selected without destabilization of the feedback loop. Thus, the value of the load capacitance can be chosen at any value according to frequency rejection requirements.

Linear regulators are widely deployed for providing a regulated output voltage based on an inputted reference voltage, such as a reference voltage that might be provided by a bandgap reference. A simplified example of a conventional linear regulator is depicted in FIG. 1.
As shown in FIG. 1, linear regulator 10 includes op-amp 1 connected in a linear feedback loop based on voltage reference Vref. Op-amp 1 drives the gate of NMOS transistor 2, which is connected in series with a resistor-capacitor network of load resistor 3 (RL) and load capacitor 4 (CL). Because of the linear feedback loop in which op-amp 1 is connected, output voltage 5 is equal to the reference voltage, i.e., Vo=Vref.
The FIG. 1 linear regulator 10 effectively attenuates low frequencies in the power supply, and at low frequencies the relationship of Vo=Vref is accurate. However, for higher frequencies in the power supply, the effect of parasitic capacitance becomes more pronounced. Specifically, the parasitic capacitance Cds between source and drain of NMOS transistor 2 affects the ability of the linear regulator 10 to reject high frequencies in the power supply. In particular, at high frequencies, the ability of linear regulator 10 to achieve high power supply rejection is determined by the ratio of Cds to CL.
As a consequence, for good power supply rejection at high frequencies, it is preferable that CL be as large as possible. However, large values for CL are not easy to fabricate, and in addition large values of CL tend to destabilize the linear feedback loop.
Thus, conventional linear regulators suffer from an inability to achieve good rejection of high frequency components of the power supply.

Linear regulator with improved power supply rejection


A workpiece fixing method capable of machining a workpiece with high accuracy by firmly fixing the workpiece with no necessity of using a special freezing chuck device is provided. For this purpose, a macromolecular freezing agent having the freezing point hither than that of water and represented by silicone oil is interposed at least between the workpiece and the surface of a fixing jig under which a fluid at a temperature lower than the freezing temperature of the macromolecular freezing agent is operated on the fixing jig during a time period of machining the workpiece whereby the macromolecular freezing agent is cooled and frozen and the workpiece is adhered and fixed.

In machining a workpiece, the workpiece needs to be fixed firmly to a working machine. Although, conventionally, a magnetic chuck, a vacuum chuck, a vice or the like has generally been used as means for fixing a workpiece, the workpiece may not be fixed firmly and stably when the workpiece is thin, easy to destruct or provided with a complicated shape where restrictions are imposed on material, shape or the like of the workpiece.
As a counter measure therefor, a freeze chuck process and device with ice as an adhesion medium has been proposed. According to the related art, a freezing plate comprising a material excellent in the thermal conductivity such as copper or the like and a freeze chuck device are used, water is coated on the freezing plate in spray, a workpiece is mounted thereon, the freezing plate is placed on the freeze chuck device under this state, and electricity is conducted in a thermoelement of the freeze chuck device by which temperature of a top face of the freezing plate is cooled down to 0.degree. C. or lower to thereby freeze water and fix the workpiece by a film of ice.
However, there have been posed the following problems in such a related art.
(1) The device cost is higher than that of a generally-used workpiece fixing process and the efficiency of attaching and detaching a workpiece is poor.
Although according to the related art, water is frozen and a workpiece is fixed by a film of ice, actually, a sufficient fixing force cannot be provided unless the temperature of the top face of the freezing plate is lowered to temperatures lower than -5.degree. C., for example, about -10.degree. C. Further, the workpiece cannot be taken out unless the temperature is elevated to 0.degree. C. or higher after the machining operation. Therefore, an expensive and complicated device is needed, the working cost is increased and the operational efficiency is poor since a long period of time is required in fixing and detaching the workpiece on the freezing plate.
(2) It is extremely difficult to carry out machining operation by using a machining fluid and a workpiece may be detached from a fixing face or detached from a table during machining operation. Further, even when the machining operation can be carried out, burr or defect may be caused and high accuracy working cannot be performed.
That is, it is appropriate to use a machining fluid for removing heat of working generated between a workpiece and a tool during the machining operation, lubricating the tool, evacuating chips and so on. However, the temperature of the machining fluid is generally higher than the temperature of ice fixing the workpiece. Therefore, when the machining fluid is supplied to a working face, the film of ice is melted, the machining operation cannot be carried out since the workpiece is detached from the fixing face and further, the workpiece jumps out of a table, which is extremely dangerous.
Even when a water-soluble machining solution including an antifreezing solution is used and the machining solution is cooled down to a freezing point or lower as a counter measure therefor, since ice is provided with strong affinity for water, the machining solution is liable to melt ice fixing the workpiece and the workpiece is liable to release from a fixed state. Therefore, the method in the related art is actually applicable only to a dry machining process where a machining solution is not used.
(3) The movement of a tool is liable to hamper by lamination of ice on a workpiece during the machining operation and therefore, high accuracy machining in respect of dimensions and shape is difficult to perform.
For example, when a workpiece is cut or diced, during the machining operation, a water-soluble machining solution or moisture in air are frozen and laminated on the workpiece. The ice is brought into contact with a flange, a mandrel or the like of the tool by which the movement of the tool is hampered and therefore, precision machining is difficult to perform or accident of destructing the tool or a main spindle is liable to cause.
Therefore, when an object of a thin film is machined, diced or sliced, a workpiece is fixed not by a freezing process but by using wax or the like, however, according to this process, a long period of time (normally 30 minutes or more) is required in adhering the workpiece, and a long period of time is required in removing the wax after machining, which is very poor in the operational efficiency and the operational performance. Furthermore, the fixing force is weak and insecure in respect of the wax or the like and therefore, the machining accuracy is deteriorated and deformation of the workpiece is caused by heat generation since the workpiece cannot be applied with a machining solution. Particularly, machining of cutting or the like in respect of a fine ceramics group, a boron group, a cobalt group and the like is almost impossible since certainty in fixing a workpiece is deficient.
(4) Restriction is imposed on a shape of a workpiece, for example, when a product having a donut-like shape and a thickness of 0.5 mm or smaller is sliced from a cylindrical workpiece, the fixing force of the workpiece is deficient and chipping cannot be prevented and therefore, high accuracy machining cannot be carried out.
The present invention has been created by carrying out researches in order to resolve the above-described problems and it is a basic object of the present invention to provide a workpiece fixing method capable of machining a workpiece with high accuracy by firmly fixing the workpiece without using a special freeze chuck device and yet capable of detaching the workpiece swiftly and simply after machining or the like at low cost.
Further, it is other object of the present invention to provide a workpiece fixing method capable of carrying out highly accurately and simply a slicing operation for obtaining a donut-like product of a thin layer from a cylindrical workpiece, a polishing or slicing operation of inner and outer faces of a cylinder and a polishing or cutting operation of end faces of a cylinder.


A deep format filter element has a peripheral frame with outwardly protruding mounting flanges. The mounting flanges simulate the periphery of a shallow format filter element to allow the deep format filter element to replace the shallow format filter element in many situations. The frame design allows the entire frame to be formed of cardboard and still provide adequate rigidity and strength. The frame includes at least a first cardboard sheet forming individual sides of the frame and panels of the mounting flange. The first cardboard sheet includes for each mounting flange at least two inside folds defining edges of the mounting flange's end panel and first and second side panels. An outside fold defines the second side panel of the mounting flange.

It is customary to filter the air provided to occupied spaces by heating, ventilating, and air conditioning (HVAC) equipment. A typical HVAC system for a residence for example, has a fan that while operating draws air present within the occupied space through a return air intake opening and into a plenum or air duct leading to a furnace or air conditioner (generically, air processor) for reprocessing.
HVAC systems frequently cause the reprocessed air to pass through a filter to remove particulate contamination. One convenient and effective way to do this is to filter the air as it enters the return air intake opening in the plenum or duct leading to the air processor. This prevents dirty air from reaching heat exchanger surfaces.
The filter may be a simple mechanical filter with a disposable or renewable element, or may be electronic. The following description pertains to mechanical filters that collect these particles on or within the filter material through which the filtered air passes.
It is helpful at this point to define terms applying to mechanical air filters that will be frequently used in the description to follow. The medium of an air filter is the actual material that performs the filtering function. The air filter element is the entire disposable unit including the medium and any support structure that is installed in a filter housing and is discarded after the medium material has become clogged with air contaminants.
In residential systems, the medium is usually formed in a nominally one inch (2.5 cm.) thick rectangular shape. The filter element usually includes a frame forming the periphery of the filter element as a support structure. The medium is typically either a woven glass fiber mat, or pleated paper or other sheet-type medium material. The breadth and width dimensions of these filter elements vary to conform to the dimensions of the opening in which the element is to be installed, but typically are each on the order of two feet (61 cm.).
In a common design, the frame comprises flexible cardboard edging having a U-shaped cross section enclosing the medium's edges and a small portion of the medium's periphery adjacent the edges. The frame provides stiffness for the filter element and seals the edges against most air leakage around the filter element. This filter format will be referred to hereafter as a shallow filter element or shallow format filter.
The return air intake openings in which these filters are installed typically have annular or inwardly projecting sheet metal or plastic flanges around the entire interior periphery of the opening. The flanges' outer surfaces all lie in a common plane and are set back from the opening a short distance.
The filter's frame is pressed against the flange's outer surface by force from a grille cover having an internal ridge bearing against the filter frame's outer surface to thereby create a tight seal between the outer intake flange surfaces and the inwardly facing filter frame surface. This tight seal forces most all of the air entering the plenum to pass through the filter element medium.
As one would expect, different types of air filters have different efficiencies. "Efficiency" in this context refers to the percentage of the total number of particles in the air stream within a given size range entering the filter that the filter element can catch. The efficiency of filters varies with different particle size ranges. For example, a high efficiency filter medium can catch a significant percentage of particles whose size is on the order of 0.3 micron, where a low efficiency medium catches relatively few of them.
There is also the consideration of overall efficiency as opposed to filter medium efficiency. Overall efficiency takes into account the air leakage around a filter element mounted in its housing. Leaking air is of course completely unfiltered. Its particle load pollutes the stream of filtered air, resulting in an overall efficiency lower than the medium efficiency.
But efficiency is not the only measure of medium quality. It is also important that a filter not create a large pressure drop in the air passing through it. A large pressure drop requires a more powerful fan to force the required air volume through it. And if the pressure drop is too great, the medium will deflect and perhaps even burst or tear as the load of trapped debris obstructs the air passages through the medium.
The amount of pressure drop presented by a particular medium depends largely on the number of voids or openings per unit area of the medium, on the average minimum cross section area of the pores, and of course on the total area of the medium through which the air flows. To a lesser extent, pressure drop is also dependent on the medium thickness, in the same manner that a long duct creates more resistance to air flow through than does a short duct, other things being equal.
Obviously, as a filter element loads up with debris during use, its pressure drop increases. This leads into a further consideration for filters, that of carrying capacity and filter element life. "Carrying capacity" refers to the number of particles the filter element can catch or hold per unit area projected to the air stream before clogging up to a point where the ability to remove particles is impaired and/or the pressure drop across the filter element becomes unacceptable. ("Dust-holding" capacity is an industry term that we intend to be substantially equivalent to carrying capacity.) Other things being equal, carrying capacity is directly related to total medium area. The capacity of mat filters which trap some of the particles within their volume may also depend to some extent on their thickness. Carrying capacity is one factor in determining the life of the element and thus the cost of filtering the air.
Filter technology advances have led to improvements in each of these characteristics. Nevertheless, it is still true that there are tradeoffs between efficiency, pressure drop, and carrying capacity. For example, as a filter medium becomes more efficient, its pressure drop typically increases because the individual passages through the medium become smaller, other things being equal. Of course, it may be possible to add more passages per unit area, but this is not a trivial problem.
Increasing the filter efficiency will often reduce the carrying capacity of the tilter element. Often, higher efficiency produces a higher initial pressure drop. Thus as the filter element loads up with particles, the pressure drop reaches an unacceptable level more quickly.
An easy way to minimize pressure drop and maximize capacity is to increase total medium area. This fact has led to the development of the pleated filters mentioned. These pleated filters are made from a long strip of sheet filter medium which is folded back and forth on itself accordion-fashion to form a series of pleats. So long as the adjacent pleat panels do not touch each other the air can easily flow through the individual pleats.
In order to maintain spacing of adjacent pleats from each other under the force created by the normal pressure drop across the medium, it is possible to insert combs on the downstream side of the medium that have individual teeth between each pair of adjacent pleat panels. The teeth prevent adjacent pleats from collapsing against each other.
Improved filter media have been developed whose pressure drop and carrying capacity is superior to that of shallow format mat and pleated filters. These media typically have relatively deep pleats (4–5 in. or 10–12.5 cm.) to provide a relatively large medium area providing lower pressure drop and better carrying capacity. These deep pleat elements are intended for use in return air ducts having intake openings capable of receiving such filter elements.
In one design the filter elements collapse into a relatively small volume for shipping. They have relatively rigid cardboard or plastic end strips or panels that detachably mate with reusable side panels to form a reasonably rigid rectangular filter element. See U.S. Pat. No. 5,840,094 issued on Nov. 24, 1998 to Osendorf, et al. ('094) for an example of such a collapsible filter medium which can be assembled into a deep format pleated filter element using a pair of special side panels. The filter element assembly is mounted in the return air intake, placing the filter element directly in the return air stream.
Collapsible filter media have the distinct advantage of compactness during shipping. But the time and effort required for assembling collapsible filter media for use is one disadvantage of them. The many pleats each require a tooth of the comb, whose insertion between each pair of pleats is time-consuming. And overall filtering efficiency suffers because of difficulty in providing a total air seal between the intake flanges of the return air duct and the cardboard sides of the filter element.

Deep filter element suitable for replacing a shallow filter element and having a support frame made from thin stock


An apparatus (30) for eliminating gaps (20) in a door of an airplane has an elastaueric bladder (32) bonding along an edge (24) of a door gap (20). The elastomeric bladder (32) includes a port providing for access to an interior cavity (34). A pneumatic actuator is coupled to the port.

Modern aircraft have a number of exterior access doors such as landing gear doors, avionics access doors and bomb bay doors. Due to the large stresses and temperature variations modern aircraft encounter during flight, these doors have to accommodate changes in size and shape of the structural member forming the doors. Gaps form around the edges of the doors as a result of these changes in size. These gaps can cause turbulence that increases the drag of the aircraft. The gaps allow dirt and contaminants to enter the aircraft, including electromagnetic emissions. The turbulence and contaminants reduce the aircraft's mission effectiveness.
Thus there exists a need for an apparatus to eliminate (reduce) gaps in aircraft, so that the gaps do not result in turbulence or allow dirt and contaminants into the aircraft.

Apparatus for eliminating gaps in an aircraft


A flash EPROM memory array which operates at lower voltage power supply with no disturbance during operation. The memory circuit comprises a plurality of memory elements in a matrix fashion with each element including a semiconductor substrate, a drain region, a source region, a floating gate, a control gate, and a select gate. The low voltage power supply operation capability is achieved by a special arrangement on the said memory array such that the programming of the memory cell is achieved by high efficient hot electron injection which allows lower drain voltage during programming. No disturbance during program and erase occurs due to a control gate line running in parallel with the drain line. No disturbance access during read operation because of alternating drain and source lines such that the memory device can be read from the source side.

1. Field of the Invention
This invention relates to a flash EPROM memory array architecture, and more particularly the invention relates to a memory array which can be operated at a low voltage power supply with minimal gate and drain disturbance during operation.
2. Field of Prior Art
FIG. 1A is a section view of a prior art flash EPROM device in which an N+ source 10 and N+ drain 12 are formed in the surface of a P- semiconductor substrate 14. A floating gate 16 is provided between a control gate 18 and the surface of the substrate 14, and between the source 10 and the drain 12. The device is programmed to a high threshold voltage state by applying high voltage (about 6.5 to 7 volts) on the drain and high voltage (about 12-13 volts) on the control gate so that hot electrons are injected into the floating gate near the edge of the drain junction. The programming efficiency of the device in FIG. 1A strongly depends on the channel length, channel doping concentration, doping profile of the drain junction, and especially, the drain voltage since the programming occurs at the drain side of the floating gate transistors, referred to herein as drain side programming.
The typical drain voltage for drain side programming is about 6.5 to 7 volts and the typical programming current is in the range of 500 uA to 1 mA per bit. The 6.5 to 7 volts of programming voltage usually is obtained by reducing it from a separate 12 volts power supply. Thus, the memory circuit operation needs two power supplies: a 5 volts power supply and a 12 volts power supply. To use a single low voltage power supply (e.g. 5 volts) operation, either a very large charge pump is needed to supply the large programming current which is in the range of several milliamperes for one byte (8 bits) of programming, or a heavily doped channel concentration with specially designed drain junction is needed so that enough programming speed is provided and at the same time soft-write during read operation (read disturb) is avoided. Both of the approaches are difficult to achieve.
Erase of the device in FIG. 1A is achieved either by applying a high voltage (about 12 to 13 volts) on the source 10 and ground to the control gate 18, or by applying 5 volts on the source 10 and a negative voltage (about -11 volts) on the control gate 18. One big problem of this device during erase operation is that is cannot be over-erased. If the device is over-erased to become a depletion transistor, it will conduct leakage current during the read operation of the other memory cells, for the same accessed bit line.
Read operation of the device is achieved by applying a low voltage (about 1 volt) on the drain 12 and 5 volts on the control gate 18. The low threshold voltage cell (non-programmed cell) will conduct current and is read as a `1` state, and the high threshold voltage cell (programmed cell) will not conduct current and will be read as a `0` state.
A typical memory array architecture using the device in FIG. 1A is shown in FIG. 1B. In this array architecture, the control gates extend in one direction to form word lines and the drains extend in another direction to form bit lines with the bit lines perpendicular to the word lines. Usually, 8 or 16 bit lines share one common source line. The access of a certain memory cell is achieved by selecting one bit line and one word line, and the cell at the cross point of the selected bit line and word line is selected. During the programming of the selected cell A, selected bit line B1 is at 6.5 to 7 volts and selected word line W1 is at 12 volts and all the other unselected lines are at 0 volt. In this situation, cell A will be programmed to high threshold voltage. However, the memory cell B which is connected to the selected bit line but on an unselected word line is stressed at high drain voltage with gate grounded as shown in FIG. 1C. This condition is usually called drain disturb. For the case of 100 .ANG. first gate oxide thickness and 15% of drain coupling, the electric field between the drain and the floating gate is about 5.5 to 6 MV/cm under the drain disturb condition as shown in FIG. 1C.
The drain disturb on cell B occurs not only during the programming of the cell A but also during the programming of the rest of the cells connected to the same bit line B1. If cell B has been programmed to high threshold voltage prior to cell A and the rest of the cells connected to bit line B1, this high drain voltage may discharge the floating gate charge of the cell B by the electric field between the floating gate and the drain. As described above, the programming of the memory cell in this array architecture is achieved by drain side hot electron injection. The drain voltage during programming cannot be too low otherwise the programming speed will be too slow. But, the drain voltage during programming cannot be too high because of the drain disturb condition that limits the drain voltage during programming for this array architecture. The limitation on the drain voltage necessitates very high channel doping for optimizing the programming performance. However, high channel doping creates other disturbance problems such as read disturb, and also reduces the bit line junction breakdown voltage which makes the erase junction difficult to optimize. Thus, the drain disturb during programming imposes a limitation on the process window and scaling of the array.
Besides the drain disturb, this array architecture also has gate disturb problems during programming. For example, during programming of the selected cell A, the memory cell on the unselected bit line and on the selected word line such as cell C is under the stress condition as shown in FIG. 1D, which is called gate disturb. The 12 volts on the control gate and 0 volt on both drain and source will result in about 6 MV/cm of electric field between the floating gate and the substrate surface if 50% of control gate coupling is used and may cause electron tunneling from the substrate into the floating gate through the thin dielectric (typically 100 .ANG.) during the program operation of cell A and any other cell connected to word line W1. The gate disturb condition limits the maximum voltage that can be used on the control gate for programming such that the programming performance cannot be optimized by increasing the word line voltage. This also burdens the optimization of the programming performance. Both the drain disturb and the gate disturb conditions in this array architecture narrow the process window and reduce the design margin.
Assume the memory array as shown in FIG. 1B is separated into small blocks with several word lines as a memory block. During erase of the memory cell of the selected memory block such as cells A and C by employing the negative gate erase scheme, a -11 volts will be applied on the selected word line W1 and 5 volts will be applied on the common source line such that the charge on the floating gates of cells A and C can be discharged by the electric field between the floating gate and the source. However, the source of the unselected cells B and D will also have 5 volts on it since cell B and D share the same source with cells A and C. Considering the situation that cells A and C are programmed and erased for 10,000 cycles with typically erase time of 1 second for each erase cycle, the source of the cells B and D will be stressed by 5 volts for at least 10,000 seconds. Charge on the floating gate can be easily discharged by this stress condition. Usually this erase disturb is prevented by adding a pass transistor which can be selectively turned off to block the source voltage for the unselected cells. However, this adds some overhead on the chip size and complicates the circuit design.
Besides the disturb conditions during program and erase, the memory architecture as shown in FIG. 1B also suffers from the read disturb during read operation if the memory cell is not optimized. The read operation on cell A is achieved by applying a low voltage about 1 volt on the bit line B1 and 5 on the word line W1. The bit line voltage cannot be too high because the high bit line voltage on the drain of cell A and 5 volts gate voltage is under a programming condition, albeit slow programming. Since the channel doping is usually very high for optimizing the programming speed, channel doping also enhances the programming of the cell during a read condition. Thus, optimization of the channel doping and special designed drain junction are usually needed for this type of array architecture.
To summarize, all the above disturbance conditions are caused by the array architecture in which a word line is arranged to be perpendicular to both the drain and the source lines such that all the unselected cells will be stressed either by high control gate voltage or high drain/source voltage with all other terminals grounded. The common source architecture also creates disturbance during the erase operation and cannot prevent the disturbance during a read operation. All of these disturb conditions narrow the process window and make the optimization and scaling of the memory cell difficult.
FIG. 2A is a section view of a prior art memory device again having N+ source 20 and N+ drain 22 in a surface of P-substrate 24 with floating gate 26 between a control gate electrode 27 and the surface of the substrate 24, both of which overlap the source and a portion of the channel region. An addressing gate electrode 28 is formed on the control gate electrode, and extends to a portion of the channel region not covered by the floating gate and the control gate electrodes. Erase of the device in FIG. 2A is achieved by applying about 50 volts on the control gate to remove electrons from the floating gate through the dielectric between the floating gate and the control gate by Fowler-Nordheim tunneling. Due to the presence of the addressing gate, this device will not leak current even if the floating gate transistor is over-erased because the addressing gate can still turn off the device. The structure as shown in FIG. 2A effectively includes a floating gate transistor and an addressing gate transistor in series and is referred to a split gate structure.
Programming of this device is done by applying 25 volts on the control gate 27 and by applying 10 volts on both the drain 22 and the addressing gate 28. The high drain voltage is transferred by the addressing gate to the drain side of the floating gate transistor. The electrons moving through the channel cause an impact ionization near the drain side of the floating gate transistor due to a high electric field and thereby produce hot electrons with the high energy. Part of the hot electrons are injected into the floating gate 26 due to the high voltage coupling from the control gate 27 such that the device assumes a high threshold voltage state. Since the hot electrons are generated near the drain edge of the floating gate transistor, this programming mode is drain side injection and is the same as the device in FIG. 1A. Thus, the device in FIG. 2A still needs high drain voltage for programming and operating voltage is difficult to reduce.
The memory array architecture of the device in FIG. 2A is shown in FIG. 2B. In this array architecture, the control gate line runs perpendicular to the drain lines, and the addressing gate runs parallel with the control gate. This architecture does not have the drain disturb problem since its drain is not overlapped with the floating gate. However, the source region is self-aligned and overlapped by the floating gate. During programming of the cell 92-1, 10 volts are applied to the V.sub.D1 and V.sub.AG1 and 25 volts are applied to the V.sub.CG. Since all the control gates are at 25 volts and all the sources of the unselected cells 92-2 92-3, and 92-4 are at 0 volt, the unselected cells will have the gate disturb problem since the electrons may tunnel from the source into the floating gate through the thin dielectric between the floating gate and the source. One way to prevent this is to use thicker dielectric between the floating gate and the substrate. This necessitates that the memory cell be erased by electron tunneling through the dielectric on top of the floating gate instead of erased through the dielectric underneath the floating gate. However, erase through the dielectric on top of the floating gate usually is not uniform because the quality of the dielectric on the floating gate (oxide grown from polysilicon) is not as good as that grown from the substrate which is single crystalline silicon.
FIG. 3A is a section view of another prior art device which overcomes the over-erase problem by a split gate structure and can be programmed with lower drain voltage (5 volts instead of 6.5 to 7 volts) by using a different mechanism for hot electron injection. The advantage of using 5 volts on the drain for programming is the extra 12 volts power supply is not needed for this memory circuit operation and only a single low voltage (5 volts or 3 volts) power supply is needed. The device of FIG. 3A use a triple polysilicon structure including a floating gate 36, a control gate 38 and a select gate 39. The control gate 38 and the floating gate 36 overlap a portion of the channel region adjacent to the drain 32, and the select gate overlies another portion of the channel region adjacent to the source 30. Erase of the device is by applying a high voltage on the drain 32 and 0 volt on the control gate 38. Since it is a split gate structure, this device also does not have the over-erase concern.
Programming of the device is achieved by applying 5 volts on drain, 15 volts on the control gate, and about 1.5 to 2 volts on the select gate. The high control gate voltage heavily turns on the floating gate transistor and transfers the 5 volts drain voltage to the source side of the floating gate transistor. A high potential drop occurs at the substrate surface near the source edge of the floating gate transistor. The electrons in the channel are accelerated by this high potential drop and become hot electrons which can inject into the floating gate by high control gate voltage coupling. Since the hot electrons are generated and injected into the floating gate at the source side of the floating gate transistor, this programming mode has been referred as source side injection. It has been demonstrated that the source side injection can be 1000 times more efficient than the drain side injection. This is the reason why the device in FIG. 3A can be programmed with a lower drain voltage compared to the devices in FIG. 1A and FIG. 2A in which drain side injection is used. Moreover, since the select gate transistor is only slightly turned-on, the programming current is determined by the select transistor which can be less than 20 uA per bit. If further reduction of power supply is needed such as V.sub.cc =3 volts, the 5 volts drain voltage for programming is easily obtained by a charge pump circuit due to this small programming current. This indicates that it is possible to reduce the power supply voltage by implementing the source side injection method.
A typical memory array architecture of the device in FIG. 3A is shown in FIG. 3B. In this array architecture, the select gate 39 is formed by anisotropic etch of a third layer of polysilicon to form a sidewall gate structure adjacent to the control gate such that the orientation of the select gate line needs to be the same as the control gate. This requires that the select gate line be in parallel with the control gate line. Also, in this array architecture, the control gate and the select gate need to be perpendicular to the drain lines such that the access of a particular memory cell is achieved at the location where the bit line crosses with the control gate line and the select gate line. Since the selected bit line is perpendicular to the selected control gate line, it has the drain disturb and gate disturb concerns as described previously for the array architecture in FIG. 1B. Further, since the select gate 39 in FIG. 3A is formed by a sidewall etchback technique, it is difficult to apply silicide to form a silicide sidewall structure. Consequently, the RC delay along the select gate line will be large and degrade the speed performance of the memory circuit.
Thus, it is possible to use a single low voltage power supply for memory circuit operation if a source side injection mode is used. However, the array architecture as shown in prior art FIG. 3B will have both drain and gate disturb problems because the control gate line is arranged perpendicular to the drain lines, and the access of the memory cell is achieved at the location where the bit line crosses with both the control gate line and the select gate line. All these disturbances will reduce the endurance and degrade the reliability of the circuit. For major applications of flash memory such as for data storage, both the endurance and the reliability are critical. The only way to prevent these disturb conditions is to have a new array architecture such that the control gate line is in parallel with the drain lines and make the select gate line perpendicular to both the control gate and the bit line. The access of the memory cell is achieved at the location where the select gate line crosses with both the control gate line and the bit line. All the high voltage during program and erase is applied only to the control gate and the bit line, and the select gate line voltage is always kept as low as 0-2 volts.
It is therefore the main object of this invention to provide a new memory array architecture having the advantages of using source side injection for programming and with minimal disturbance during operation of the memory circuit.

Flash eprom memory circuit having source side programming