A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode can be a schottky contact or an insulated metal contact. Two ohmic contacts can be provided to form a rectifier device with nominally off characteristics. The recesses formed with the electrode can have sloped sides. The electrode can be formed in a number of geometries in conjunction with current carrying electrodes of the device. A nominally on device, or pinch resistor, is formed when the electrode is not recessed. A diode is also formed by providing non-recessed ohmic and schottky contacts through an insulator to an AlGaN layer.

1. Field of the Invention
The present invention relates generally to a class of field effect current control devices, and relates more particularly to rectifiers and current limiting devices constructed in the III-Nitride material system.
2. Description of Related Art
III-nitride semiconductors are presently known that exhibit a large dielectric breakdown field of greater than 2.2 MV/cm. III-nitride heterojunction structures are also capable of carrying extremely high currents, which makes devices fabricated in the III-nitride material system excellent for power applications.
Development of devices based on III-nitride materials has generally been aimed at high power-high frequency applications such as emitters for cell phone base stations. The devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFETs), high electron mobility transistors (HEMTs) or modulation doped field effect transistors (MODFETs). These types of devices are typically able to withstand high voltages such as in the range of 100 Volts, while operating at high frequencies, typically in the range of 2-100 GHz. These types of devices may be modified for a number of types of applications, but typically operate through the use of piezoelectric polarization fields to generate a two dimensional electron gas (2DEG) that allows transport of very high current densities with very low resistive losses. The 2DEG is formed at an interface of AlGaN and GaN materials in these conventional III-nitride HEMT devices. Due to the nature of the AlGaN/GaN interface, and the formation of the 2DEG at the interface, devices that are formed in the III-nitride materials system tend to be nominally on, or depletion mode devices. The high electron mobility of the 2DEG at the interface of the AlGaN/GaN layers permits the III-nitride device, such as a HEMT device, to conduct without the application of a gate potential. The nominally on nature of the HEMT devices previously fabricated have limited their applicability to power management. The limitations of nominally on power devices is observed in the need to have a control circuit be powered and operational, before power can be safely controlled by a III-nitride HEMT device. Accordingly, it would be desirable to create a III-nitride HEMT device that is nominally off to avoid current conduction problems during start-up and other modes.
A drawback of III-nitride HEMT devices that permit high current densities with low resistive losses is the limited thickness that can be achieved in the strained AlGaN/GaN system. The difference in the lattice structures of these types of materials produces a strain that can result in dislocation of films grown to produce the different layers. This results in high levels of leakage through a barrier layer, for example. Some previous designs have focused on reducing the in-plane lattice constant of the AlGaN layer to near where the point of relaxation occurs to reduce the dislocation generation and leakage. However, the problem of limited thickness is not addressed by these designs.
Another solution is to add insulation layers to prevent leakage problems. The addition of an insulator layer can reduce the leakage through the barrier, and typical layers used for this purpose are silicon oxide, silicon nitride, sapphire, or other insulators, disposed between the AlGaN and metal gate layers. This type of device is often referred to as a MISHFET and has some advantages over the traditional devices that do not have an insulator layer.
While additional insulator layers can permit thicker strained AlGaN/GaN systems to be constructed, the confinement layer produced by the additional insulator results in lower current carrying capacity due to the scattering effect produced on electrons at the GaN/insulator interface. Also, the additional interface between the AlGaN layer and the insulator results in the production of interface trap states that slow the response of the device. The additional thickness of the oxide, plus the additional interfaces between the two layers, also results in the use of larger gate drive voltages to switch the device.
Conventional device designs using nitride material to obtain nominally off devices rely on this additional insulator to act as a confinement layer, and may reduce or eliminate the top AlGaN layer. These devices, however, typically have lower current carrying capacity due to scattering at the GaN/insulator interface.
Accordingly, it would be desirable to produce a heterojunction device or FET that has a low leakage characteristic with fewer interfaces and layers that can still withstand high voltage and produce high current densities with low resistive losses. Presently, planar devices have been fabricated with GaN and AlGaN alloys through a number of techniques, including MOCVD (metal organic chemical vapor deposition) as well as molecular beam epitaxy (MBE) and hydride vapor phase epitaxy (HVPE).
Materials in the gallium nitride material system may include gallium nitride (GaN) and its alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) and indium aluminum gallium nitride (InAlGaN). These materials are semiconductor compounds that have a relatively wide direct bandgap that permits highly energetic electronic transitions to occur. Gallium nitride materials have been formed on a number of different substrates including silicon carbide (SiC), sapphire and silicon. Silicon substrates are readily available and relatively inexpensive, and silicon processing technology has been well developed.
However, forming gallium nitride materials on silicon substrates to produce semiconductor devices presents challenges that arise from differences in the lattice constant, thermal expansion and bandgap between silicon and gallium nitride. The problems attendant with the lattice mismatch between GaN and traditional substrate materials are also prevalent in material layer structures involving GaN and GaN alloys. For example, GaN and AlGaN materials have lattice structures that differ significantly enough to produce interface strain between the layers, contributing to piezoelectric polarization. In many previous devices, the fields generated by the piezoelectric polarization are controlled to improve the characteristics of the devices. Variations in the content of aluminum in the AlGaN/GaN layer structures tends to vary the lattice mismatch between the materials to achieve different device characteristics, such as improved conductivity or isolation barriers.
A particular application that would benefit from a semiconductor structure with a low forward resistance or voltage drop is a rectifier. Conventionally, rectifiers in power applications are often controlled as synchronous rectifiers, where a diode performs the voltage blocking function of the rectifier, and a synchronous switch across the diode performs current conduction when the diode is forward biased to avoid the ON resistance and forward voltage drop of the diode. This type of configuration requires a switching control for the switch so that it is turned on when the diode is to be operated in forward conduction mode. This type of conventional synchronous rectifier is often used in power applications to avoid the drawbacks of diodes used as rectifiers, such as a forward voltage drop that reduces power efficiency and may also contribute to thermal operating issues. However, because the synchronous switch used with the diode to construct a synchronous rectifier is typically a power switch, a gate driver is used to operate the switch in high power applications. It would therefore be desirable to obtain a rectifier device that does not require additional control operations, but also maintains a low forward voltage drop.
Another type of device that can limit the amount of current flowing through it is a pinch resistor. A pinch resistor is typically fabricated in a semiconductor material with two different types of conductivity material. For example, a P-type conductivity material is disposed in an N-type region, and an N+-type region is formed partially over the P-type material. The resistance of the pinch resistor is determined by the sheet resistance of the P-type material under the overlapping N+-type region and the dimensions of the overlapped P-type material. The current in the device is conducted in a channel that is "pinched" by the opposite semiconductor material. Through these types of designs, very high resistances can be formed in a very small area to effectively limit current in a given power range. However, these types of devices are often imprecise due to processing techniques used during their manufacturing. According to some designs, the current through the device is effectively limited by the voltage generator across the device, which can serve to control the channel to limit the current. In conventional devices, the current values that can be carried in pinch resistors is relatively low, so that power applications tend to be somewhat complicated.
It would be desirable to provide a high current rectifier device such as a diode or pinch resistor that can block significant voltages while obtaining a low forward voltage drop.

Method of forming a III-nitride selective current carrying device including a contact in a recess


A system for energy recovery from a rod pump includes a reversible hydraulic pump; a variable speed reversible motor-generator connected to the reversible hydraulic pump; and a variable speed drive that operates the motor-generator to rotate the reversible hydraulic pump in a forward direction to pump hydraulic fluid to the rod pump during an upstroke, and to operate the motor-generator in a generator mode in which a weight of a rod string lowers a piston in the rod pump during a downstroke to pump hydraulic fluid to rotate the hydraulic pump in reverse such that the motor-generator generates electricity, and the variable speed drive modulates a speed of the motor-generator during the downstroke to modulate a speed of the reversible hydraulic pump to control a rate of flow of hydraulic fluid through the reversible hydraulic pump and thereby modulate a rate of downward motion of the rod string.

When the fluid in a well, which may be water or oil, lacks sufficient pressure to be forced up the well bore, it is necessary to employ a pump to retrieve the fluid from the well bore. Oil fields in which subsurface oil remains in an oil-bearing zone but lacks pressure to be forced from the well bore utilize down hole pumps. A type of down hole pump used in oilfields is a rod pump, also known as a pump jack. A rod pump includes an outer cylindrical cement sleeve that lines the well bore (typically a vertical shaft from the surface to the fluid to be pumped) and is perforated at its lower end, a casing lining the inner wall of the cement sleeve and a tubing inside the casing. A long sucker rod extends from the surface to the bottom of the well where it is connected to a traveling valve that opens and closes within a pump barrel of fluid in response to the reciprocating upward and downward movement of the sucker rod to pump fluid to the surface. At the surface, a tee connects the tubing to a line that conveys the fluid away from the well.
The top of the sucker rod terminates in a stuffing box and is connected to a polished rod that extends upwardly from the stuffing box. The top of the polished rod is connected to a prime mover system that imparts reciprocating upward and downward movement to it. During the upstroke of the polished rod and sucker rod, fluid is lifted from the bottom of the well; and during the downstroke of the polished rod and the sucker rod the traveling valve opens to allow more fluid to enter the tubing.
A type of prime mover system employs an electric motor that drives a hydraulic pump. The pump is connected between a reservoir of hydraulic fluid and a hydraulic cylinder. The polished rod is connected to the rod of the piston in the cylinder. The hydraulic pump pressurizes the cylinder to make an upstroke of the piston, polished rod, and sucker rod, and the combined weight of the polished rod and sucker rod pull the piston downward to force hydraulic fluid from the cylinder back to the reservoir. The sucker rod can be built up of segments of 25 to 30 feet in length, which may be threaded together and combined can extend for hundreds of feet or more. The considerable combined weights of the sucker rod, the polished rod, and the column of fluid extending up the bore hole require significant energy input during the upstroke. Such energy is lost unless the pumping system employs a mechanism to recover the potential energy stored in the polished rod and sucker rod during the downstroke.
Systems have been designed to utilize the fluid flow from the hydraulic cylinder during the downstroke both to regulate the speed of the polished and sucker rods during the downstroke and recover the energy from the falling polished and sucker rods. Some systems employ energy storage components such as hydraulic accumulators, batteries, or capacitors that are charged during the downstroke. Other systems utilize pivoting swash plate hydraulic pumps that accommodate reverse fluid flow. Accordingly, there is a need for an energy recovery system for a rod pump that is relatively reliable and simple in construction.

This patent is subject to a terminal disclaimer.

Rod pump having a hydraulic cylinder and a variable speed reversible motor-generator


A technique enables maintenance of sufficient clearance between a wellhead and, for example, a mobile rig. The technique facilitates support of a cable, e.g. an antenna suspension cable, at the wellhead without detrimentally affecting the desired clearance. According to an embodiment, a flange system is used in combination with a cable clamp assembly at a wellhead. The flange system may comprise a flange having a connector portion configured for coupling with the wellhead. The flange also comprises a cylinder portion coupled to the connector portion such that the cylinder portion extends into a corresponding bore of the wellhead. The cable clamp assembly is configured to clamp around and support a cable extending down through the wellhead. The cable clamp assembly is supported within the cylinder portion of the flange such that the cable clamp assembly is at least partially disposed within the wellhead.

Wells are drilled at great expense to access oil and natural gas below the surface of the earth. Such wells may be drilled on dry land or in a subsea environment. Because of the great expense in drilling wells, sensors often are placed in a well to monitor the condition of the well. Monitoring may occur over the life of the well and may include monitoring after the well is no longer producing oil and/or natural gas. Communication with the sensors can be difficult due to, for example, substantial distance between the sensors and the receivers. To facilitate communication with the downhole sensors, an antenna may be lowered into the well and placed in closer proximity to the sensors. Data communicated from the sensors is received by the antenna and then transmitted from the antenna through a cable to a receiver which may be located at the surface. The receiver is part of a telemetry system which is attached to a wellhead. However, components or systems attached to the wellhead can limit the clearance otherwise available above the wellhead.


An electrical contact avoidance device comprises an inductor plate directly or capacitively coupled to the user and coupled to a detector circuit which derives a DC signal corresponding to a voltage induced in the user's body by a radiated high voltage electrostatic field. A comparator compares the DC signal with a reference signal representing the potential difference between the inductor and reference plates, and activates an alarm if the detected signal exceeds a preselected reference level.

A number of safety devices of this general type are available, such as that described in U.S. Pat. No. 4,714,915 (Hascal et al) issued Dec. 22, 1987. Such a device may be installed on a safety helmet worn by the user. However, such devices pose significant disadvantages in practise.
These devices employ the principle of electrostatic induction on parallel plates, in which one plate is an inductor plate, or antenna, and a floating reference voltage is produced in a parallel plate. The antenna is connected to the input of a detector circuit which derives a DC signal corresponding to the intensity of the electrostatic field at the position of the antenna. A comparator compares the DC signal with a selected reference signal, and produces an output signal when the derived DC signal exceeds the reference signal, sounding an audible alarm.
A main disadvantage to this system is that the antenna, typically comprising a stripline antenna mounted on or around the user's helmet, can be shielded from the electrostatic field by the user. Thus, depending upon the position and orientation of the user relative to the energized conductor, the electrostatic field intensity at the position of the user may exceed the selected limit without sounding the alarm, if any portion of the user's body is interposed between the field source and the antenna. On the other hand, in certain orientations the alarm will sound when the user himself is not within the selected minimum distance of the high voltage conductor, as determined by the selected maximum intensity of the electrostatic field, if any part of the antenna strays within that distance. The latter situation can be an annoyance, while the former situation can be dangerous.
The present invention overcomes this disadvantage by providing an electrical contact avoidance system in which the body of the user forms the antenna. Since it is ultimately the user, and not the device, which must avoid contact with the high voltage conductor, by utilizing the user's body as the antenna the alarm will not sound unless part of the user's body approaches the field source too closely; nor can the user stray within the minimum selected distance from the field source without triggering the alarm. The electrical contact avoidance device of the present invention thus avoids the annoyance of false alarms and at the same time ensures that whenever any part of the user strays within the selected minimum distance from the conductor the alarm will sound, regardless of his or her orientation.
The system of the present invention further provides a support basket for a powered aerial access device which may be coupled to ground or to a high voltage conductor being serviced, or allowed to assume a floating voltage reference, a platform insulated from the basket to which the lineman is directly or capacitively coupled, and a monitoring circuit connected between the platform and the basket. Where the basket is grounded, or electrically isolated from the conductor, the monitoring device will sound an alarm if the lineman approaches a high voltage conductor too closely. Alternatively, the basket and lineman may be coupled or "bonded" to the high voltage conductor, enabling the lineman to work hands-on with the conductor, and the alarm will sound if the lineman approaches a grounded conductor or a different phase or voltage conductor. In either case, the lineman is protected from electrical shock by avoidance of any conductor energized to a voltage or phase different from that of the lineman's body.
The subject invention is based on the premise that an electrostatic field produced by a high voltage conductor induces a detectable voltage in a person's body, as in any other conductor. This induced voltage is directly related to the intensity of the electrostatic field, and thus the proximity of the person to the field source, i.e. the high voltage conductor.


An air conditioning system for cooling or heating an air, and for feeding the heated or cooled air to predetermined portions is characterized by comprising: a first circulating circuit for circulating a first heating medium; a second circulating circuit for circulating a second heating medium; a control unit for controlling the heat for executing heat exchange between the first heating medium and the second heating medium to flow through either the heat exchanger or the first heat storing device. Moreover, an air temperature is controlled by heat of the second heating medium.

An air conditioning system for a vehicle is generally constructed to regulate a room temperature by a refrigeration cycle for circulating a refrigerant. The air conditioning system of this kind is disclosed in Japanese Patent Laid-open No. 2000-142078. According to an air conditioning system for a vehicle disclosed in the Laid-open, a compressor, a condenser, a receiver, an expansion valve, an evaporator and so on are arranged in a circulating circuit of the refrigerant. In a casing of the air conditioning system, a blower fan and an evaporator are arranged. Moreover, an air inlet and an air outlet are formed on the casing.
Here will be explained an operation example according to the aforementioned air conditioning system. First of all, when the blower fan is driven, air is inhaled from the air inlet into the casing. On the other hand, when the compressor is driven by an engine power, the refrigerant is compressed by the compressor and made into a high-pressure refrigerant. The compressed and high-pressured refrigerant is then condensed by the condenser and passes through the receiver. The refrigerant is consequently made into a high-temperature and high-pressure liquid refrigerant. This liquid refrigerant is expanded by the expansion valve, and conveyed to the evaporator in the form of a low-temperature and low-pressure liquid refrigerant. In the evaporator, heat in the air is transferred to the refrigerant due to the temperature difference between the air in the casing and the refrigerant, thereby evaporating the liquid refrigerant. The low-temperatured (cooled) air is then fed from the discharging port to the vehicular room. The refrigerant passed through the evaporator flows into the compressor again. Thus, the temperature is regulated in the vehicular room.
"Flow rate of refrigerant" is any one of the conditions which affect the heat transferring capacity of the refrigerant in the circuit. According to the air conditioning system disclosed in the aforementioned Laid-open, since the compressor is driven to transport the refrigerant, the air conditioning function thereof is easily affected by the operating condition of the compressor. This makes it probable that necessary air conditioning function cannot be obtained.


A Redundant Array of Independent Disks (RAID) card is coupled to a baseboard management controller (BMC) of an electronic device. The BMC is coupled to a host device, and includes a storage unit for storing data of RAID level. A method can include obtaining a boot command from the host device, and generating a control signal according to the stored RAID level in response to the boot command. The method further includes transmitting the control signal to the RAID card, to direct the RAID card to set the stored RAID level, testing whether the stored RAID level is correctly set, and storing data indicative of the tested result in a register of the RAID card. The method further includes determining whether the stored RAID level is correctly set in the RAID card according to the data in the register, and storing the determined result in the storage unit.

Many computers or servers often include a RAID card, which has an ability to combine multiple disks into a disk array for the purposes of data redundancy and performance improvement. Data is distributed across the multiple disks according to the disk array arrangements of the RAID card, referred to as RAID levels. The simplest RAID level 1 includes one or more disks for storing data and an equal number of additional "mirror" disks for storing copies of the data written to the disks. Other RAID levels, identified as RAID levels 2, 3, 4 and 5, segment the data into portions for storage across the multiple disks.
Before shipment, a test is needed to check whether a preset RAID level is correctly set in the RAID card.

Electronic device and method for testing redundant array of independent disks level

HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.


The present invention relates to growing and testing eukaryotic cells (e.g., animal or plant cells) in a multi-test format. In particular, the present invention provides methods and kits for obtaining a complex metabolic profile of animal cells. In addition, the present invention provides tools for assaying the effects of candidate compounds (e.g., hormones) on substrate utilization by mammalian cells.

In biological research, drug development research, and other areas of clinical, evolutionary, and basic research in microbiology and cellular biology, there remains a need for methods and compositions suitable for the characterization of cells, including but not limited to microbial cells, animal cells, and plant cells. Indeed, methods and compositions are needed for the characterization of cellular properties that may or may not change, depending upon genetic changes and changes in the intracellular and extracellular environment, including exposure of cells to biologically active chemicals.
In addition to the need for identification and characterization methods for microorganisms and other cells, there remains a need for pharmaceuticals for treatment of infectious, as well as non-infectious disease. Indeed, there is a need for methods and compositions to assess cellular phenotypes and the reaction of cells to the environment. Typically, the process of developing pharmaceuticals involves the steps of defining drug targets and testing potentially active chemicals to find the ones that specifically interact with the target to produce the desired effect without undesirable side effects. Although much work has been done in this area, there remains a need for improvements in the efficiency and effectiveness of the testing and evaluation of these chemicals.
In response to the pressures to generate more promising drug candidates, pharmaceutical and biotechnology companies have turned toward rapid, high-throughput methods to find and evaluate lead compounds. These lead compounds are typically selected by testing large libraries of compounds compiled from a wide variety of sources, using collections of extracts, chemicals synthesized by combinatorial chemistry approaches, or through rational drug design.
However, these methods have been a mixed blessing. Technologies such as combinatorial chemistry allow for rapid generation and testing (e.g., screening) of libraries of compounds against potential drug targets. Unfortunately, these technologies only look at the effect of the drugs on the proposed target, and they do not measure the effect on other cellular processes. A chemical may be an excellent candidate based on its interaction with the target protein, but it may also interact with other proteins in the cell and cause side effects. Thus, a major problem remains, in that the drug developer must sort through promising drug candidates to see how they effect other aspects of cell function, as well as how the drug candidates interact with other drugs that may be used simultaneously. Despite advances in these fields, there remains a need for highly sensitive and specific, yet cost-effective and easy-to-use methods for the identification and development of compounds (e.g., biologically active compounds) that are effective in the treatment of infectious and non-infectious diseases.

Methods and kits for obtaining a metabolic profile of living animal cells


An optical harmonic generating device is provided with reverse polarization layers which are made of non-linear optical crystal polarized in a lower direction and are periodically arranged at regular intervals, a non-reverse polarization layer which is made of the non-linear optical crystal polarized in the upper direction and is arrange to surround the reverse polarization layers, a wave guide penetrating through alternate rows of the reverse and non-reverse polarization layers, a first electrode arranged on the wave guide, and second electrodes arranged on both ends of the alternate rows. Electric field is induced between the first and second electrodes through the wave guide to change a refractive index of the reverse and non-reverse polarization layers. A part of the fundamental wave passes through the alternate rows to be converted to the harmonic wave, and another part of the fundamental wave passes through the non-reverse polarization layer positioned under the reverse polarization layers to change the refractive index for the fundamental wave.

1. Field of the Invention:
The present invention relates to an optical harmonic generating device in which a harmonic wave of laser is generated from a fundamental wave of the laser and a shorter wavelength generating apparatus in which laser generated in a laser source is converted to a harmonic wave thereof by utilizing the optical harmonic generating device to produce coherent light utilized in a photo information processing field and a photo applied measuring control field.
2. Description of the Related Art:
An optical harmonic generating device has been conventionally developed to convert a fundamental wave of laser to a harmonic wave. The laser such as semiconductor laser is generally composed of the fundamental wave and a plurality of harmonic waves such as a second harmonic wave. The intensity of the laser is almost occupied by the fundamental wave. A wavelength .lambda..sub.f of the fundamental wave is longer than those of the harmonic waves, and each of wavelengths .lambda..sub.h of harmonic waves is defined as a multiple of the wavelength .lambda..sub.f. For example, the wavelength .lambda..sub.h of the second harmonic wave is half of the wavelength .lambda..sub.f. Therefore, the conversion of the fundamental wave to the harmonic wave means that the wavelength of the fundamental wave is shortened.
The harmonic wave is generally produced in a shorter wavelength generating apparatus. That is, a fundamental wave of laser generated in a laser source is converted to a harmonic wave in the shorter wavelength generating apparatus. Because the harmonic wave has a shortened wavelength, the harmonic wave is useful in a photo information processing field. That is, the harmonic wave is utilized as a data signal, and information consisting of a large number of data signals is processed in the field. Also, the harmonic wave is useful in a photo applied measuring control field. That is, a length of a subject is measured by utilizing the harmonic wave.
2.1. Previously Proposed Art:
A conventional optical harmonic generating device is described with reference to drawings. For a detailed description on the conventional optical harmonic generating device, see E. J. Lim, M. M. Fejer, R. L. Byer and W. J. KoZlovsky, "Blue Light Generation by Frequency Doubling in Periodically-Poled Lithium Niobate Channel Waveguide", Electronics Letter, Vol. 27, P731-732, 1989.
FIG. 1 is a diagonal view of a conventional optical harmonic generating device.
As shown in FIG. 1, a conventional optical harmonic generating device 11 is provided with a substrate 12 made of non-linear optical crystal LiNbO.sub.3 which is dielectrically polarized in an upper direction, a plurality of reverse polarization layers 13 which are periodically arranged in an upper side of the LiNbO.sub.3 substrate 12 at regular intervals and are dielectrically polarized in a lower direction, a plurality of non-reverse polarization layers 14 which are periodically formed in the upper side of the LiNbO.sub.3 substrate 12 between the reverse polarization layers 13 and are dielectrically polarized in the upper direction, and a wave guide 15 for guiding a fundamental wave P1 of laser from one side of the LiNbO.sub.3 substrate 12 to another side through the non-reverse polarization layers 14 and the reverse polarization layers 13.
The reverse and non-reverse polarization layers 13, 14 are also made of the non-linear optical crystal LiNbO.sub.3.
The wave guide 15 penetrates alternate rows of the non-reverse and reverse polarization layers 13, 14.
In the above configuration, an operation of the conventional optical harmonic generating device 11 is described.
A beam of laser almost occupied by a fundamental wave P1 of which a wavelength is 820 nm is radiated from a laser source (not shown) to one side of the wave guide 15. The fundamental wave P1 radiated to one side of the wave guide 15 transmits through the waveguide 15. At this time, because the fundamental wave P1 passes through the alternate rows of the reverse and non-reverse polarization layers 13, 14, the fundamental wave P1 is converted to a second harmonic wave P2 of which a wavelength .lambda..sub.h is 410 nm in the reverse polarization layer 13. The phase of the harmonic wave P2 converted is inverted while passing through the reverse polarization layer 13. Thereafter, the harmonic wave P2 of which the phase is inverted passes through the non-reverse polarization layer 14. In this case, because the polarization direction of the non-reverse polarization layer 14 is opposite to the reverse polarization layer 13, the harmonic wave P2 passing through the non-reverse polarization layer 14 is amplified without attenuating. Therefore, the second harmonic wave P2 is radiated from the another side of the wave guide 15 in place of the fundamental wave P1.
Accordingly, mismatching between a propagation constant of the fundamental wave P1 and a propagation constant of the harmonic wave P2 can be compensated by a periodical structure consisting of the alternate rows of the reverse and non-reverse polarization layers 13. As a result, the harmonic wave P2 can be efficiently amplified.
FIG. 2 graphically shows an intensity variation of the second harmonic wave P2 radiated from the another side of the wave guide 15, in comparison with another intensity variation of another harmonic wave P3 radiated from another wave guide 16 in which the reverse polarization layers 13 are replaced with the non-reverse polarization layers 14.
As shown in FIG. 2, in cases where the reverse polarization layers 13 are replaced with the non-reverse polarization layers 14 in another wave guide 16, the intensity of another harmonic wave P3 is periodically increased and decreased at the regular intervals of the non-reverse polarization layers 14 even though a length L of the wave guide 16 is prolonged. Accordingly, the harmonic wave P3 are not amplified.
In contrast, in cases where the alternate rows of the reverse and non-reverse polarization layers 13, 14 are periodically arranged in the wave guide 15 at the regular intervals, the intensity of the harmonic wave P2 is increased in proportion to a squared value L.sup.2 of the length L of the wave guide 15.
In this case, a pseudo-phase matching condition is satisfied to amplify the harmonic wave P2. The pseudo-phase matching condition is formulated by an equation. EQU .LAMBDA.1=.lambda..sub.f /{2*(N2.omega.-N.omega.)} (1).
Wherein, the symbol A1 denotes a pitch between the reverse polarization layers 13, the symbol .lambda..sub.f denotes a wavelength of the fundamental wave P1, the symbol N2.omega. denotes an effective refractive index of the wave guide 15 for the harmonic wave P2 of the wavelength .lambda..sub.h =.lambda..sub.f /2, and the symbol N.omega. denotes an effective refractive index of the wave guide 15 for the fundamental wave P1 of the wavelength .lambda..sub.f. The effective refractive index of the wave guide 15 is defined as an average value of those of the reverse and non-reverse polarization layers 13, 14.
Next, a method for manufacturing the conventional optical harmonic generating device 11 is described with reference to FIGS. 3A to 3C.
FIGS. 3A to 3C are respectively a sectional view of the LiNbO.sub.3 substrate, showing processes for manufacturing the conventional optical harmonic generating device 11.
As shown in FIG. 3A, a patterned film 17 made of Ti is deposited on the LiNbO.sub.3 substrate 12 according to a lift-off process. In this case, a plurality of rectangular openings 18 surrounded by the Ti film are formed at the pitch A1 on the LiNbO.sub.3 substrate 12. The pitch A1 is several micrometers.
Thereafter, as shown in FIG. 3B, surfaces of the LiNbO.sub.3 substrate 12 exposed to the openings 18 are heated at a temperature of almost 1050.degree. C. Therefore, the LiNbO.sub.3 substrate 12 exposed to the openings 18 is changed to the reverse polarization layers 13. Thereafter, The Ti film 17 is taken off.
Thereafter, as shown in FIG. 3C, the LiNbO.sub.3 substrate 12 with the reverse polarization layers 13 is immersed in a hot benzoic acid and is heated for twenty minutes at a temperature of 200.degree. C. After the LiNbO.sub.3 substrate 12 is taken up from the hot benzoic acid, the surface of the LiNbO.sub.3 substrate 12 is annealed for three hours at a temperature of 350.degree. C. so that the wave guide 15 is produced in the LiNbO.sub.3 substrate 12.
Because the LiNbO.sub.3 substrate 12 is immersed in a hot benzoic acid, an electric power of the harmonic wave P2 is 940 nW on condition that the length of the wave guide 15 is 1 mm and an electric power of the functional wave P1 is 14.7 mW.
2.2. Problems to be solved by the Invention:
However, a half band width of the fundamental wave P1 is only 0.1 nm on condition that the length of the wave guide 15 is 5 mm. That is, as shown in FIG. 4, in cases where the wavelength .lambda..sub.f of the fundamental wave P1 varies by 0.05 nm, the electric power of the harmonic wave amplified in the conventional optical harmonic generating device 11 is reduced to half of a maximum value. Therefore, the permissible variation of the wavelength .lambda..sub.f of the fundamental wave P1 is small.
Also, the wavelength of semiconductor laser generated in a semiconductor laser source is easily changed in cases where the temperature of the semiconductor laser source is changed according to environmental conditions such as ambient temperature.
Accordingly, in cases where semiconductor laser generated in the semiconductor laser source is radiated to the conventional optical harmonic generating device 11 in a conventional shorter wavelength generating apparatus, the harmonic wave P2 is not radiated from the device 11, or the electric power of the harmonic wave P2 is considerably reduced because the temperature of the semiconductor laser source is changed.
For example, as shown in FIG. 4, in cases where the wavelength of the semiconductor laser almost occupied by the fundamental wave P1 is 820 nm, the electric power of the harmonic wave P2 is maximized because the pseudo-phase matching condition is completely satisfied. Also, in cases where the temperature of the semiconductor laser source is 20.degree. C., the wavelength of the semiconductor laser is maintained at a value 820 nm. However, in cases where the temperature of the semiconductor laser source is changed from 20.degree. C. to 21.degree. C., the wavelength of the semiconductor laser is changed from 820 nm to 820.2 nm. Therefore, the electric power of the harmonic wave P2 becomes zero.

Optical harmonic generating device for generating harmonic wave from fundamental wave and shorter wavelength laser generating apparatus in which fundamental wave of laser is converted to harmonic wave with the device

Matsushita Electric Industrial Co., Ltd.


A local coil arrangement for magnetic resonance applications has an acquisition coil for acquisition of a magnetic resonance signal excited in an examination subject by means of a transmission coil; and a transponder. The transponder is coupled to the acquisition coil such that it can be fed with electrical energy via the acquisition coil The transponder is fashioned to send a transponder signal on a transponder frequency when and as soon as an excitation signal induced in the acquisition coil by means of the transmission coil exceeds a threshold. When the control device receives the transponder signal, it adjusts the further operation of the transmission antenna or operates it only with reduced power.

1. Field of the Invention
The present invention concerns a local coil arrangement for magnetic resonance applications of the type having an acquisition coil for acquisition of a magnetic resonance signal excited in an examination subject by means of a transmission coil; and a transponder.
The present invention furthermore concerns an operating method for a magnetic resonance system of the type wherein a temporally static, spatially homogeneous basic magnetic field is generated in an examination region of the magnetic resonance system by means of a basic magnet of the magnetic resonance system, the examination region is charged with a spatially homogeneous radio-frequency transmission signal by means of a transmission antenna of the magnetic resonance system, and a control device of the magnetic resonance system checks whether it receives a transponder signal from a transponder of a local coil arrangement of the type described above.
2. Description of the Prior Art
Local coil arrangements and operating methods of the above general type are known. For example, the transponders are used in order to detect the presence of the local coil arrangement in the examination region of a magnetic resonance system. DE 101 30 617 A1 describes an example of such a system.
Magnetic resonance signals excited in an examination subject (normally a person) are very weak. They can be detected by means of a whole-body coil (which is normally the same as the transmission coil) only with a relatively low SNR. The local coil arrangement therefore is used in order to acquire an excited magnetic resonance signal with better SNR from a spatially limited region.
The examination subject is charged with a relatively strong transmission signal by means of the transmission coil to excite the magnetic resonance signal. A current and/or a voltage are also induced in the acquisition coil of the local coil arrangement. In some cases it can occur that the current and/or the voltage are so high that a risk to the examination subject exists.
In the prior art it is known to provide a fuse to avoid such an endangerment of the examination subject in the AC coil. If too strong a field is induced by the transmission coil, the fuse melts. Although the examination subject is protected by this procedure, the acquisition coil is destroyed. A further disadvantage of the use of fuses is that these negatively influence the SNR.
Furthermore, it is known to use elaborate electronic circuits and conductors that, however, introduce a certain uncertainty factor. It is in particular possible that sheath waves are induced in the conductors.

Magnetic resonance local coil arrangement and method for communicating an overload occurrence


A sintering method for a W--Ni--Mn type heavy alloy, including controlling the deoxidization of tungsten and nickel under an inert atmosphere, changing to a hydrogen atmosphere at above a temperature at which manganese is deoxidized and simultaneously deoxidizing tungsten, nickel and manganese, and sintering by raising the temperature, resulting in the fabrication of a sintered heavy alloy having a 100% relative theoretical density.

1. Background of the Invention
The present invention relates to a sintering method for a tungsten-nickel-manganese (hereinafter, called "W--Ni--Mn") type heavy alloy, and in particular, to an improved sintering method for fabricating a W--Ni--Mn type heavy alloy which has no pores and a 100% theoretical density.
2. Description of the Conventional Art
A W--Ni--Mn type heavy alloy is composed of 90 weight % tungsten, and more than 0.5 weight % manganese and nickel.
The W--Ni--Mn type heavy alloy is composed of almost globular tungsten particles and a matrix phase of a W--Ni--Mn type heavy alloy into which a part of the tungsten is melted as shown in FIG. 1.
In a W--Ni--Mn type heavy alloy, an adiabatic shear band is maximized by adding manganese the thermal conductivity of which is low, instead of the iron(Fe) and copper(Cu) contained in a conventional W--Ni--Fe type and W--Ni--Cu type heavy alloys, and the heavy alloy can suitably be used as a material for a penetrant of a kinetic energy penetrator in the munitions field.(A Belhadjhamida and R. M. German, "The Effects of Atmosphere, Temperature, and Composition on the Densification and properties of W--Ni--Mn," compiled by J. M. Capus and R. M. German, VOL. 3, MPIF, Princeton, N.J., 1992, pp 47-55.)
A correlation between the penetrating force of a kinetic energy penetrator and an adiabatic shear band can be explained according to the schematic diagrams in FIGS. 2 and 3.(L. S. Magness and T. G. Farrand, "Deformation Behavior and its Relationship to the Penetration Performance of High Density Penetration Materials", Proc. 1990 Army Science Conf., Durham, N.C., May 1990, pp 149-164.) As shown in FIG. 2, when a penetrator of a material on which an adiabatic shear band does not occur collides with an object as shown in FIG. 2, it is easily transformed into a mushroom shape(,which is called "mushrooming") and the kinetic energy is dispersed across a relatively broad region. On the other hand, as shown in FIG. 3, when an adiabatic shear band occurs easily, the kinetic energy is concentrated into a narrow region. Since such a difference in energy concentration degree relates to the penetration force, the development of a penetrant material in which an adiabatic shear band occurs easily is of essential interest.
Factors which influence an adiabatic shear band are the specific heat, the strain hardening exponent, the thermal softening, the melting point and the thermal conductivity. The most important factor of all is known to be the thermal conductivity, since an adiabatic shear band is closely related to the heat transfer phenomenon.(A. Bose, H. Couque, J. Lankford, Jr., "Influence of Microstructure on Shear Localization in Tungsten Heavy Alloys," ed. by A. Bose and R. J. Dowding, Proc. Tungsten and Tungsten Alloys, MPIF, Princeton, N.J., 1992, pp 291-298.) Therefore, recently much attention has been focused on a W--Ni--Mn heavy alloy containing manganese the thermal conductivity of which is extremely low, and in which the adiabatic shear band occurs easily.
W--Ni--Mn type heavy alloys are fabricated by means of a powder metallurgy, as in W--Ni--Fe type and W--Ni--Cu type heavy alloys. Such a conventional sintering method as shown in FIG. 4 will now be described in detail.
As shown in FIG. 4, conventionally, W--Ni--Mn type heavy alloys are fabricated by a liquid phase sintering under a hydrogen atmosphere.
That is, the reason for keeping the heavy alloy at 800.degree. C. for 60 minutes during the sintering process is for the purpose of deoxidizing the oxides of tungsten, nickel and manganese existing on the surface of the material powders of W--Ni--Mn type heavy alloys under a hydrogen atmosphere.
However, according to the thermodynamic data concerning oxidation/deoxidation of each element, while tungsten and nickel are easily deoxidized at the above temperature range, but manganese is not deoxidized, but rather the oxides are set in a more stable condition. This means that the oxygen separated in the deoxidation of tungsten and nickel reacts with the manganese, resulting in a formation of manganese oxide. Since this manganese oxide becomes stable thermodynamically and is not easily deoxidized, residual porosity is disadvantageously formed during the sintering, as in the fine microstructure as observed through a SEM shown in FIG. 5.
These residual pores lower the mechanical strength of W--Ni--Mn type heavy alloys and consequently limit their use as a penetration material for a kinetic energy penetrator.
Therefore, to utilize W--Ni--Mn type heavy alloys as a kinetic energy penetrator, the formation of pores should be minimized. Therefor, studies have been conducted using a VHF (vacuum hot press) method instead of a liquid phase sintering, and studies are being conducted to reduce porosity through such a process as HIP (hot isostatic pressing) or by a thermal mechanical treatment carried out after performing a liquid phase sintering. But, in spite of such efforts, the reality is that alloys of greater than 98% relative theoretical density have not been obtained and the VHP or HIP process performed after a liquid phase sintering are undesirably costly.

Sintering method for tungsten-nickel-manganese type heavy alloy


A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.

The present invention, in some embodiments thereof, relates to a memory cell and, more particularly, but not exclusively, to a 4-transistor memory cell.
In accordance with Moore's Law, the size, density, and power consumption of static random-access memories (SRAMs) has grown exponentially over the past four and a half decades. This trend is expected to continue, as SRAMs occupy over 50% of the total area and static power consumption of high performance microprocessors and are one of the primary components of most types of modern ASICs. Traditionally, the primary goals of SRAM design were density and high performance, whereas power was a secondary concern and stability was easily achieved. However, at deep sub-micron technologies, frequency has been replaced by power and stability as the primary factors in SRAM design. As device dimensions continue to scale, conventional SRAM memories experience poor read and write stabilities, resulting in an ever growing error rate. This results of higher process variations and device mismatch, lowering the static noise margins of SRAM memories, resulting in a higher susceptibility to noise. Furthermore, embedded memory arrays are often operated at highly scaled supply voltages in order to reduce their power consumption, which results in even lower noise margin and a much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEUs).
SEUs occur when an energetic particle passes through a silicon substrate and its energy is transferred into the creation of electron-hole pairs along its path, as illustrated in FIG. 1. When such a particle hits a reversed-biased junction inside a storage node, the resulting transient current pulse may inject enough charge into the junctions to cause a data flip of a memory cell.
Embedded memory errors are typically handled at an architectural level using redundancy schemes, such as error correcting codes (ECCs) and triple modular redundancy (TMR). However, these solutions are extremely costly in terms of area overhead, while also adding complexity and delay, and are incompatible with sub-threshold operating memories. Furthermore, conventional error correction codes (ECCs) can only detect two errors and correct a single bit, otherwise requiring an even larger area overhead and complexity. Circuit level techniques such as DICE and Quatro 10T may efficiently increase SEU tolerance, however they require a much higher transistor-count, resulting in an even larger area and power consumption of these memory arrays.
Virtually all of the previously proposed solutions for error tolerant embedded memories are based on SRAM technology, adding additional devices and area consumption to the standard six transistors (6T) that are at the core of these memory arrays. One increasingly popular alternative to SRAM is gain cell embedded DRAM (GC-eDRAM), which offers much smaller area, lower leakage, and the option of low voltage operation. The main drawback of GC-eDRAM is the need for periodic refresh cycles to ensure data retention. However, it has been shown that its retention power, which is the sum of leakage and refresh power, may be lower than the leakage power of a conventional 6T SRAM cell.
State of the art error tolerant solutions can be divided to two approaches, circuit and architectural levels. Circuit level solutions are implemented by modification of the memory cell with increased noise margins, resulting in higher robustness to failures. In addition, SEUs tolerance may be improved by multiplication of the storage nodes and increased critical charge, thus enabling the recovery of the data following SEUs. Architecture level solutions include various error correcting schemes, mostly implemented by error correction codes. ECCs may be integrated without any modification to the memory array and are capable of correcting several errors according to the ECCs scheme used. In fact, ECCs are integrated in most embedded memories today.
Circuit Level Solutions
The conventional 6T SRAM memory cell utilizes an active feedback loop between cross-coupled inverters in order to retain its stored data value. This circuit is very sensitive to SEUs, as any upset that causes one of the data nodes to cross the switching threshold of the adjacent inverter will result in a bit flip. This failure risk increases with process scaling, where the critical charge of the memory cell decreases resulting in a higher soft error rates (SERs). Furthermore, static noise margins decrease significantly and therefore the memory cell is more susceptible to read and write errors. In addition, SRAM design for low-voltage operation has become increasingly popular over the past few years. However, when operating at low voltages, the switching threshold decreases, thereby increasing the circuit's error susceptibility. Various bitcell designs have been proposed to improve the noise margins of the cell in order to be compatible with low-voltage operation at scaled CMOS nodes. These designs generally incorporate the addition of a number of transistors into the bitcell topology, trading off density with robust, low-voltage functionality. However they do not offer self error detection and correction capability.
Many alternative error-tolerant SRAM circuits have been proposed in recent years. These solutions are directly aimed at improving the soft error susceptibility. Recently proposed error tolerant designs include the temporal latch, DICE, the Quatro-10T and 12T bitcells, the 13T sub-threshold bitcell, and SHIELD. These solutions may be fabricated in commercially available state-of-the-art manufacturing processes at the expense of an increase in the silicon area of the bitcell. The following three solutions reported high error tolerance and incorporate low-voltage operation.
1) DICE: The dual interlocked storage cell (DICE) is the best known SEU hardened bitcell. The concept of the DICE design is using the dual modular redundancy (DMR) of its internal circuit nodes to achieve immunity to errors affecting a single node. This is achieved with 12 transistors, implementing a dual node feedback control mechanism, as seen in FIG. 2A. The storage element utilizes four internal circuit nodes to store one memory bit. When a single event temporarily upsets one of these four nodes, only one additional node is affected by the upset through positive feedback. In this way a single node upset (SNU) will not propagate the error to the other nodes, and the unaffected nodes can correct the circuit value. However, it still remains sensitive to multi-node upsets (MNU) and also suffers from high power consumption, due to its many transistors and leakage paths. Additionally, the cell recovery time severely increases with supply voltage scaling, making the DICE bitcell inefficient for ultra low power (ULP) operation.
2) The 13T and SHIELD: While all of the previously proposed rad-hard bitcells were designed for error resilience under nominal supply voltages, the circuits proposed in "A 13T radiation hardened SRAM bitcell for low-voltage operation," by L. Atias, A. Teman, and A. Fish [25] and in "A novel low power bitcell design featuring inherent seu prevention and self correction capabilities," by O. Chertkow, A. Pescovsky, L. Atias, and A. Fish [26] specifically target ULP space applications, operated at scaled voltages. The 13T bitcell, shown in FIG. 2B, achieves radiation hardening by employing a dual-feedback, separated storage mechanism to overcome the increased vulnerability due to supply voltage scaling. By driving the acute data level with a pair of equipotentially driven, but independent, inverters, a strong, dual-driven feedback mechanism is applied with node separation for SEU protection. This setup effectively protects Q from an upset on QB1 or QB2, while achieving a high critical charge at node Q. The 13T bitcell was shown to be fully functional at sub-threshold voltages in [25] for a 0.18 μm implementation.
Another approach to ULP rad-hard operation is taken by the SHIELD bitcell [26], shown in FIG. 2C. This bitcell uses a pair of gated inverters (M5-M1-M2-M6 and M7-M3-M4-M8) to mitigate SEUs. These inverters incorporate an additional input gate that dynamically latches the previous output state when the primary and secondary inputs are different. A pair of these gated inverters is cross-coupled through a cutoff network (M11-M12 and M13-M14) to provide radiation tolerance. This results in two sets of separate dual-data nodes, which exhibit high SEU tolerance under scaled supply voltages.
Architectural Solutions
The main approach to error mitigation over the past two decades has been to provide full immunity to errors through circuit redundancy. The simplest way of error detection is using an additional parity bit, indicating whether a single error has occurred by comparing the parity of the stored data in the word to the parity bit. While this method is simple and requires minimal area cost, it can only detect up to one error per word and cannot correct it. For large memory arrays, ECCs can be used to detect and correct data errors in the memory array. They are typically implemented by the addition of extra bits per word and encoding the data to be able to detect and correct several bits, based on the used code. The number of bits which can be corrected comes in the expense of complexity and area overhead. One of the mostly used ECCs is single error correcting (SEC) Hamming code, which has the ability to correct single upsets with a reduced area and performance overhead. However, single error correcting ECCs may not be sufficient to meet reliability goals. Extended Hamming codes enable a single error correction-double error detection (SECDED). However, multiple errors occurring in a single word cannot be corrected. More advanced ECCs schemes include Reed-Solomon encoding and decoding, which enables the error correction and detection of multiple errors. Although this code copes with multiple errors, it does not correct double faults located in two adjacent blocks; which requires the use of Reed-Solomon code with double block correction capability. The cost of double block correction code is too high compared to the single block correction code, which makes this alternative inappropriate for hardware implementation.
The most popular technique in use today involves replicating a storage node three times and adding a three-input majority gate to filter out unwanted SEUs. This technique assumes that the probability of an error at two separate places on the chip within a defined time span is extremely low. When a single error occurs at any of the three storage nodes, a three-input majority gate acts as a voting circuit to recover the correct value. TMR is popular among ASIC and FPGA designers, since it does not introduce any new circuit elements to the existing standard cell library. However, TMR requires an increase in both area and power of at least 3×. In addition, TMR institutes a non-negligible delay overhead, due to the triplication of the sequential cells and the addition of the delay elements and majority gate.
Additional Background Art Includes:
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Complementary dual-modular redundancy memory cell


A water heating system has a tank, a heating element, a temperature sensor, and a controller. The heating element is mounted on the tank, and the temperature sensor is mounted on the heating element. The controller is coupled to the temperature sensor and is configured to detect a dry fire condition associated with the heating element based on the temperature sensor.

Devices such as hot water heaters, furnaces, and other appliances commonly include one or more heating elements that are controlled by a controller such as a thermostat. The heating element is placed in an on-state when heat is needed and turned to an off-state when heat is not required. The change of states normally occurs when a control signal turns a power relay on or off. Power relays have a pair of contacts capable of meeting the current requirements of the heating element. In a typical home-use hot water heater, approximately 220 volts AC is placed across the heating element and a current of about 10 to 20 amperes flows. If the heating element fails, then the water heater may be unable to heat water to a desired temperature until the failed element is repaired or replaced.
A heating element is typically associated with an upper temperature threshold, referred to as the "upper set point," and a lower temperature threshold, referred to as the "lower set point," that are used for control of the heating element. When the temperature of water in a tank exceeds the upper set point, as measured by a thermal sensor mounted on a wall of the water heater, the heating element is transitioned to the off-state. If the water temperature drops below the lower set point the heating element is placed in the on-state. As heated water is repeatedly withdrawn from the water tank and replenished with cold water, the heating element goes through on/off cycles.
One problem associated with water heaters having electrical heating elements is the destruction of the elements caused by a dry fire condition. A dry fire condition exists when a heating element of a water heater is not submerged in water. Such a condition may exist due to improper installation or operation of the water heater. If power is applied to a heating element when the element is not covered with water, then the heating element can quickly heat to an extremely high temperature resulting in damage to the heating element and/or other components of the water heater. Hence, there is a need for preventing damage resulting from operation of a heating element during a dry fire condition.

Water heating system and method for detecting a dry fire condition for a heating element


A method of producing a silicon-on-insulator article, the method including: forming a first aluminum nitride layer thermally coupled to a first silicon substrate; forming a second aluminum nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminum nitride layers of the first and second substrates together so that the first and second aluminum nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminum nitride layers.

The term "silicon-on-insulator" or "SOI" generally refers to a composite semiconductor article or product consisting of a thin layer of silicon attached to and supported by an insulating layer or substrate, and also to technologies based on such products. In view of their role as starting materials for subsequent processing, such articles are often referred to in the art as "substrates" and are typically provided in standard wafer form so that they can be used with standard semiconductor manufacturing equipment and processes.
SOI substrates can be manufactured by a variety of different methods, including the direct deposition or epitaxial growth of a thin layer of silicon on a compatible electrically insulating (e.g., sapphire) substrate, the in situ formation of a buried layer of SiO2 under a single-crystal silicon layer by implanting oxygen into a bulk silicon wafer in accordance with the SIMOX (separation by implantation of oxygen) method, and methods based on wafer bonding, including BE-SOI (bond-and-etch-back SOI), and layer transfer methods such as the Smart-Cut™ method described in U.S. Pat. No. 5,374,564. Although SOI wafers are more expensive than monolithic or bulk silicon wafers, they provide a number of technical advantages, particularly when high speed electronic devices are formed in the thin silicon layer, including reduced junction capacitance, low standby power, radiation tolerance, and freedom from latchup.
The standard form of SOI substrate is a 'sandwich' structure wherein a buried silicon dioxide (SiO2) layer provides the desired electrical isolation between the thin silicon layer and a thick supporting silicon base or substrate. However, this buried dielectric layer is also a barrier to heat flow from the devices fabricated in the silicon layer, due to the relatively poor thermal conductivity of SiO2. Consequently, the temperature of the channel of a MOSFET device formed in the thin silicon layer inevitably increases during operation to temperatures that are substantially higher than the corresponding temperatures of an equivalent device formed in a bulk silicon wafer, thereby degrading the performance and possibly the lifetime of the device.
To address this issue, a number of researchers have fabricated SOI substrates in which a buried layer of aluminium nitride (AlN), rather than the conventional SiO2, is used as the insulating material. This arrangement greatly reduces the often severe self-heating problem of conventional SOL since the thermal conductivity of AlN is ˜100 times that of SiO2, (136 W/mK vs. 1.4 W/mK) and is roughly equal to that of silicon itself 145 W/mK. In addition, AlN has excellent thermal stability, high electrical resistance and a coefficient of thermal expansion close to that of silicon.
For example, as described in M. Zhu et. al., Formation of silicon-ion-aluminum nitride using ion-cut and theoretical investigation of self-heating effects, Materials Letters 59 (2005) 510-513, and in C. Men et. al., Fabrication of SOI structure with AlN film as buried insulator by Ion-Cut process, Applied Surface Science 199 (2002) 287-292, an AlN layer can be formed on a standard (100) silicon wafer by metal plasma immersion ion implantation deposition (Me-PIIID), or by ion beam enhanced deposition (IBED) with the electron beam evaporation of Al and simultaneous bombardment of nitrogen ion beam. Then the deposited film can be directly bonded to a standard (100) silicon wafer that has previously been implanted with high energy hydrogen ions to form a buried layer. The bonded wafers can then be heated to strengthen the bond between the wafers and to cause the surface layer of the implanted wafer to split off using an ion-cut or Smart-Cut™ method. The result is a silicon-on-aluminum nitride or 'SOAN' substrate.
Despite the promise of SOAN substrates, they have not progressed beyond the research phase and are not commercially available. The inventors of the present invention believe this is likely to be caused by poor bonding between the silicon and aluminum nitride surfaces, due not only to common factors such as surface roughness and wafer flatness, but also to inherent poor bonding strength between these two materials. The rather poor quality of the deposited AlN layer may also play a role.
It is desired to provide a silicon-on-insulator article and a method of forming a silicon-on-insulator article that alleviate one or more difficulties of the prior art, or that at least provide a useful alternative.

Method of producing a silicon-on-insulator article


A lever bender includes a first handle pivotally attached to a second handle. The first handle includes a forming mandrel around which a pipe is bent and a stop member for receiving and substantially holding the pipe in place prior to bending. The second handle includes a forming head that engages and bends the pipe around the forming mandrel. The stop member includes a pipe-engaging member that receives a pipe and a locking member adjacent to the pipe-engaging member. The locking member includes a retaining member moveable between a projecting position where the retaining member secures the pipe between the pipe-engaging member and the locking member and a retracted position permitting a pipe to either be received within the pipe-engaging member or removed from the pipe-engaging member.

Manual pipe bending is common in the plumbing, piping, heating, ventilation, air conditioning and refrigeration ("HVACR") fields. For example, soft/annealed copper tubing is commonly used in fluid systems (liquid and gaseous), and must be bent on site into the necessary configuration. An HVACR technician, for example, will often use a manual pipe bender, e.g., a lever bender, to bend a piece of tubing rather than solder or braze a curved fitting onto the tubing. Manual tube/pipe bending allows a technician to bend the tubing to desired angles that may not be available with available fittings and is often also more time efficient and less costly.
A typical lever bender has two handles that are pivotable with respect to one another to bend a pipe placed into the bender. Two hands are needed to operate the two handles, in order to pivot them with respect to one another and bend the mounted pipe. The pipe is preferably held in place within the bender while bending, in order achieve a smooth and accurate bend at the desired location along the pipe. Accordingly, the user must stabilize the pipe in place within the bender, and also engage and operate the handles. This can be a cumbersome task. Thus, one drawback of currently available lever benders is the difficultly for a user to maintain a pipe in place in the bender prior to initiating the bending, and then bend the pipe.
Previous attempts to solve this problem include lever benders having different types of stop members for stabilizing the pipe during setup and/or while bending the pipe. However, none of the known stop members adequately maintain the pipe position in all directions during setup and while bending. Therefore, additional stabilization, e.g., by the user, is still required, or there is a risk of movement and/or inaccuracy in the resulting bend.


A liquid ejecting head includes a nozzle formation face with a nozzle; a pressure chamber communicated with the nozzle; and a pressure generator changing pressure in the chamber so as to eject liquid from the nozzle. An adjuster adjusts a distance between the nozzle formation face and the target medium so as to be at least a first distance, and a second distance that is longer than the first distance. A driving signal generator generates a driving signal that includes a first pulse having at least a first expansion element and a first ejecting element, and a second pulse having at least a second expansion element and a second ejecting element. A pulse supplier selectively supplies a pulse to the pressure generator. The pulse supplier selects the first pulse when the distance is the first distance, and selects the second pulse when the distance is the second distance.

The present invention relates to a liquid ejecting apparatus of an inkjet printer and so on, and more particularly, to a liquid ejecting apparatus which drives a pressure generating element using a driving signal including various kinds of ejecting pulses in an ejecting period such that dots having different sizes can be formed on a target object.
A liquid ejecting apparatus includes a liquid ejecting head which can eject liquid as a liquid droplet, and ejects various kinds of liquid from the liquid ejecting head. As a representative example of the liquid ejecting apparatus, there is an image record device of an inkjet printer and so on, which includes, for example, an inkjet record head (hereinafter, referred to as record head) as a liquid ejecting head and ejects/impacts liquid ink as an ink droplet from a nozzle orifice of the record head onto a target object such as a record sheet to form a dot and perform record. In addition, recently, the liquid ejecting apparatus applies to various kinds of manufacturing apparatuses such as a color filter manufacturing apparatus of a liquid crystal display and so on, in addition to the image record device.
In the inkjet printer (hereinafter, referred to as printer), for example, a driving signal, in which various kinds of ejecting pulses having different amounts of the ejected ink are connected to each other in series, is generated, and the ejecting pulses of the driving signal are selectively supplied to a pressure generating element such as a piezoelectric vibrator to drive the pressure generating element, thereby forming dots having different sizes on the target object such as the record sheet. For example, in a printer disclosed in JP-A-10-193587, a single driving signal is formed by a first waveform and a third waveform which are ejecting pulses for forming a middle dot and a second waveform and a fourth waveform which are ejecting pulses for forming a small dot, the waveform according to ejecting data is selected from the driving signal to be supplied to the pressure generating element, thereby forming the dot having a desired size. In addition, the printer disclosed in JP-A-10-193587 is configured by supplying all the first waveform and the third waveform to the pressure generating element to form a large dot.
Accordingly, in this kind of printer, when relatively large amount of ink is ejected onto the record sheet, such as full print, a cockring phenomenon that the record sheet is bent by the absorption of the large amount of ink may be caused. When the cockring is generated, a distance from the nozzle orifice of the record head (a nozzle formation face that is formed with the nozzle orifice) to the record surface of the record sheet (paper gap or platen gap) is reduced. Accordingly, the flight distance of the ink droplet is changed and thus record unevenness is generated or the record sheet contacts the record head and thus the record sheet is contaminated.
Since the record sheet called a dedicated sheet has an ink receiving layer and the ink is absorbed into the ink receiving layer, the cockring is not easily generated. Accordingly, when the record is performed using the dedicated sheet, the paper gap is reduced to some extent. On the contrary, when a general sheet which does not have the ink receiving layer is used, since the paper itself absorbs the ink, the cockring tends to increase. Thus, generally, when the general sheet is used in the printer, the paper gap is set to be larger than that of the dedicated sheet in consideration of looseness of the paper due to the cockring.
However, if the paper gap is large, since the flight time for ejecting and impacting the ink droplet becomes longer, the flight bending of the ink droplet is apt to be affected. As the result, a position in which a dot is formed is deviated from an adequate position and thus image quality is deteriorated. Furthermore, the ink droplet may extend in an ejecting direction by an ejecting force such that the tail thereof is separated, thereby generating a minute ink particle called satellite ink droplet. At this time, if the paper gap is large, the satellite ink droplet is not impacted onto the target object and floats in the air as mist. If the mist floats in the air, the inside of the printer is contaminated.
In order to solve the above-mentioned problems, a method of suppressing an ejecting speed (flight speed) of the ink droplet and suppressing the ink droplet from extending in the ejecting direction such that the satellite ink droplet is not generated may be considered. However, if the flight speed of the ink droplet is suppressed, since the flight time becomes longer while the vicinity of the nozzle orifice is wet or shape unevenness is apt to be affected, the flight bending becomes larger. As the result, impact accuracy is deteriorated and thus the image quality is deteriorated. Particularly, if the dedicated sheet is used, since a user requires higher image quality of the record image, the deterioration of the image quality must be suppressed, if possible.


A direct type backlight modulus lamp replacement device with each lamp respectively being fixed in a replacement device, the replacement device being provided at the bottom of the lampshade in relation to a slot of the lamp, a recess being formed in the device to place the lamp, a positioning part being each extended from both sides of the recess to secure the device at the bottom of the lampshade so to replace the lamp only by removing it from the lampshade without removing the entire reflection lampshade.

(a) Field of the Invention
The present invention is related to a lamp replacement device, and more particularly to one for the replacement of lamp in a direct type backlight modulus.
(b) Description of the Prior Art
As illustrated in FIG. 1 of the accompanying drawings for a sectional view of a direct type backlight modulus generally available in the market, the entire direct type backlight modulus is comprised of a reflection lampshade, multiple light sources, a diffuser plate 30, a diffuser film 40, a prism 50, a reflection deflector 60 and a LCD 70 arranged in sequence inside out. Wherein, each of those sources may be provided in a form of a straight strip, U-shape or other continuously curved lamp 20, arranged at a proper spacing at where between the reflection lampshade and the diffuser plate 30 and fixed to the reflection lampshade 10 to emit lights for the display effects by the liquid crystal modulus. Those multiple films provided between the diffuser plate 30 and the LCD 70 can be also comprised of 1˜2 diffusers, 0˜2 prisms, and 0˜1 reflection deflectors to diffuse the light for eliminating possible brighter or darker area on the LCD due to the absence of light emission from the spacing between two light sources 20.
However, the lamp has a given service life and requires service or replacement to maintain consistent light emissions to the LCD. In replacing the lamp of the direct type backlight modulus of the prior art, first all the diffuser plate 30, the diffuser film 40, the prism 50, the reflection deflector 60 and the LCD 70 on the top of the reflection lampshade 10 must be removed one by one; or alternatively, the entire reflection lampshade 10 is removed from the back of the LCD, then the lamp to be replaced is removed from the reflection lampshade 10 to be replaced with a new lamp, the new lamp is fixed into the reflection lampshade 10, and finally, all the diffuser plate 30, the diffuser film 40, the prism 50, the reflection deflector 60, and the LCD 70 are assembled one by one in sequence to where below the reflection lampshade 10, or the reflection lampshade 10 is assembled to the back of the LCD 70 to complete the replacement of the lamp for a direct type backlight modulus.
The replacement of a lamp for a direct type backlight modulus of the prior art can only be done by having first removed the devices on the reflection lampshade or the entire reflection lampshade. The replacement involves multiple steps and becomes too complicate disregarding how many lamps to be replaced. Furthermore, both of the reflection lampshade and the lamp itself are comparatively heavy, any act of omission during the handling would result in damaged direct type backlight modulus or the LCD.


A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving code, an operating system program and user data for the computer system; and an interface unit communicating with the system controller through the system bus in the first interface mode and communicating with the NAND flash memory in a second interface mode, the interface unit being synchronized with a clock signal generated therein in response to predetermined command and operating information. The NAND flash memory may be used for the system bootstrap, and data transmission to the system controller during reading or programming operations is performed successively to reduce the latency time on the read operation and the data loading time on the programming operation.

1. Technical Field of the Invention
This disclosure relates to a computer system with a NAND flash memory for booting and storage.
2. Description of the Related Art
In a system such as a general PDA, a mobile phone, a set top box, or the like, ROM or NOR flash memory is mainly used for the system drive memory and NOR flash memory is used as the data storage memory. Flash memory is suitable for data storage because it has a volatility in which data can be written and erased and no refresh is needed. In particular, NOR flash memory is widely being used for booting and storage in systems that do not require a high speed interface.
With the growth of the system market, a memory capable of supporting high speed access, having large capacity, as well as being cost-effective due to service variety and high functionality has been requested. However, the conventional NOR flash memory does not fulfill such a request. Although conventional DRAM meets such a request at present, it is a volatile memory and is not suitable for data storage.
In the meantime, since the NAND flash memory is easy to realize, has a large capacity, and is cost-effective compared with the NOR flash memory, it is widely used as a large capacity memory. Also, since the NAND flash memory is easy to fabricate and has a good integrity, its use as a booting memory has been proposed.
In U.S. Pat. No. 5,535,357, issued to Moran et al., entitled "Flash memory system providing both BIOS and user storage capability", an example of a flash memory used as a booting memory is disclosed. Referring to FIG. 1, in order to use a NAND flash memory as the booting memory, a flash controller 8 performs an interfacing between a NAND flash memory 4 and a system bus 2. Here, the NAND flash memory 4 has to store a separate emulation means. The emulation means is indicative of means for using a region of the NAND flash memory as the hard disk. The flash controller 8 intercepts the BIOS booting process and installs the emulation means in a system memory 3. In the construction of FIG. 1, the system booting is performed as follows.
First, a jump address for a BIOS region BS (located at block 1) is stored in a file system region FS (located at block 0) of a NAND flash memory 4. A memory mapping to the BIOS block BS is performed using a memory mapping circuit (or window circuit) arranged in the flash controller 8. With the memory mapping, an operating system region OS is moved to the system memory 3 to subsequently perform the system booting.
However, in order to use the NAND flash memory as the system booting memory by the aforementioned conventional method, the NAND flash memory 4 should be partitioned into the file system region FS, the BIOS region BS, the operating system region OS and the user data region UD as shown in FIG. 1. Also, the NAND flash memory 4 must have the emulation means which allows the NAND flash memory 4 to be recognized as the hard disk. In addition, the flash controller 8 must have the functionality to intercept the BIOS operating process and means for performing an address mapping to the BIOS region BS.
In the aforementioned conventional method, preparing to use the NAND flash memory and the flash controller as a booting memory and the necessary operational steps are complicated. Consequently, it is not easy to apply the conventional method to a general computer system.
Embodiments of the invention address these and other disadvantages of the conventional art.

Computer system with NAND flash memory for booting and storage


In a booster circuit which is operated with a two-phase clock and in which a plurality of (M≧4) lines of boosting cells constitute a unit, a boosting cell in the K-th line (1≦K≦M) is controlled, depending on the voltage of the input terminal of a boosting cell in the KA-th line (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). As a result, a charge transfer transistor can transition from the conductive state to the non-conductive state before a clock input to the boosting cell in the K-th line transitions from low to high and then boosting operation is performed. As a result, the backflow of charge via the charge transfer transistor can be reduced or prevented.

The present disclosure relates to booster circuits.
In recent years, for flash memories, which are a type of non-volatile storage devices, there has been a demand for data read operation and data rewrite operation which are performed with a single power supply voltage or low power supply voltages. To meet the demand, an on-chip booster circuit may be required which supplies a positive or negative boosted voltage when each operation is performed.
The booster circuit is also becoming a key technology to ensure an operating margin of a non-volatile storage device or an analog circuit in a CMOS process.
FIG. 14 shows a configuration of a conventional booster circuit (see, for example, U.S. Pat. No. 7,176,746). The booster circuit 900 performs boosting operation in accordance with two input clock signals CLK1 and CLK2 having different phases. Reference characters 901a-901e each indicate a charge transfer cell which transfers charge from the preceding stage to the succeeding stage, and reference characters 902a-902d each indicate a boosting capacitor which boosts the output of a charge transfer cell.
FIG. 15 is a diagram showing details of the charge transfer cells 901a-901e. A reference character 903 indicates a charge transfer transistor. Reference characters 904 and 905 indicate switching transistors provided in each of the charge transfer cells 901a-901e, which switch between the input voltage of a charge transfer cell in the preceding stage and the output voltage of the each charge transfer cell, depending on an input to the each charge transfer cell.
Next, operation of the booster circuit 900 of FIG. 14 will be briefly described with reference to FIG. 16.
Initially, at time T1, the clock signal CLK1 transitions from low to high, so that the voltages of the boosting capacitors 902a and 902c are boosted. As a result, the voltages of the output terminals OUT of the charge transfer cells 901a and 901c are boosted, so that the switching transistors 905 of the charge transfer cells 901a and 901c transition to the conductive state, and therefore, the charge transfer transistors 903 are set to the non-conductive state. At the same time, the switching transistors 904 of the charge transfer cells 901b and 901d transition to the conductive state, and therefore, the charge transfer transistors 903 transition to the conductive state. By the aforementioned operation, charge on the output terminals having the boosted voltages of the charge transfer cells 901a and 901c is transferred to the output terminals of the charge transfer cells 901b and 901d.
At time T2 (a period of time Ttrans after time T1), the clock signal CLK2 transitions from low to high, so that the voltages of the boosting capacitors 902b and 902d are boosted. As a result, the voltages of the output terminals OUT of the charge transfer cells 901b and 901d are boosted, so that the switching transistors 905 of the charge transfer cells 901b and 901d transition to the conductive state, and therefore, the charge transfer transistors 903 are set to the non-conductive state. At the same time, the switching transistors 904 of the charge transfer cells 901c and 901e transition to the conductive state, and therefore, the charge transfer transistors 903 transition to the conductive state. By the aforementioned operation, charge on the output terminals having the boosted voltages of the charge transfer cells 901b and 901d is transferred to the output terminal of the charge transfer cell 901c and the output terminal of the booster circuit 900.
Thereafter, at time T3, boosting operation similar to that which is performed at time T1 is repeated.


Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.

Flash memory is used in a wide variety of electronic applications. Some flash memory cells utilize a floating gate field-effect transistor (FET), which stores one or more bits of data in the form of an electric charge within a "floating" gate. The floating gate resides above a channel of, and below a control gate of, the FET, but is electrically-isolated from both by an oxide layer. The memory cell stores charge when the FET is in an "on" state (i.e., when current flows between the source and drain) by applying a voltage to the control gate, which causes electrons to tunnel from the channel into the floating gate. Because the floating gate is electrically-isolated from the channel and the control gate, electrons that tunnel into it will remain there indefinitely.
Electric charge trapped within the floating gate screens the electric field from the control gate within the channel, which selectively changes the threshold voltage (Vt) of the FET. For flash memory devices that use an array of memory cells, the stored data can be read out of the array by measuring which cells have a higher Vt (e.g., store a "1") and which have a lower Vt (e.g., store a "0"). Multi-bit cells are also possible, where a single memory cell has more than two discrete Vt states corresponding to more than two data states.

Well controlled conductive dot size in flash memory

Taiwan Semiconductor Manufacturing Co., Ltd.