A light-emitting structure includes a package substrate and a light emitter disposed on the package substrate. The package substrate includes a carrier substrate and a plurality of metal units disposed on the carrier substrate. A distance between two arbitrary points on a periphery of the metal unit is defined as a peripheral endpoint distance. The light emitter includes a first electrical metal and a second electrical metal that have different electrical polarities and are separate from each other. A shortest distance between the first electrical metal and the second electrical metal is defined as an electrical metal interval. The electrical metal interval between the first electrical metal and the second electrical metal is greater than the longest peripheral endpoint distance of the metal unit.

A light-emitting diode (LED) is a light-emitting element formed by a semiconductor material. In an LED, a photon is emitted by combining an electronic and a hole in the semiconductor to generate a spectrum having different frequencies. Offering features of having good color purity and a long life cycle as well as being mercury-free and power-saving, LEDs have gradually gained popularity in applications of illumination and backlight sources of display devices.
The packaging and bonding of an LED can be performed by two main methods—a wire bonding method, and a flip chip method. In the wire bonding packaging technique, a chip is placed on a substrate, and is combined to connecting points on the substrate by wire bonding. In the flip-chip packaging technique, bumps are grown on connecting points of a die, and the chip is flipped over to directly connect the bumps with a substrate. More specifically, during a packaging process for a flip-chip package structure, electrodes of a flip chip need to be aligned with a circuit pattern on a substrate to form electrical connection.
Further, metal adhesion for an LED chip is performed by two main methods—an all-surface metal adhesion method and a wafer-level flip-chip adhesion method. In the all-surface metal adhesion technique, a metal layer of a chip and a metal layer of a substrate are adhered to each other. In the wafer-level flip-chip adhesion method, metal bumps are grown on a chip, and the chip is flipped over to directly connect the metal bumps with metal on a substrate. The growth substrate is then removed to proceed to die manufacturing. More specifically, in the wafer-level flip-chip adhesion method, the metal bumps of the flip chip need to be aligned with the metal of a circuit pattern on a substrate to form electrical connection.
For both of the flip-chip package technique of dies and the wafer-level flip-chip adhesion technique, even a slightly error during the alignment procedure may result in short circuits. Further, manufacturing costs can be significantly increased as high-precision alignment apparatuses are extremely expensive.


Systems for extended depth frequency domain optical coherence tomography are provided including a detection system configured to sample spectral elements at substantially equal frequency intervals, wherein a spectral width associated with the sampled spectral elements is not greater than one-half of the frequency interval. Related methods are also provided herein.

Optical coherence tomography (OCT) is a noninvasive imaging technique that provides microscopic tomographic sectioning of biological samples. By measuring singly backscattered light as a function of depth, OCT fills a valuable niche in imaging of tissue ultrastructure, providing subsurface imaging with high spatial resolution (˜2.0-10.0 μm) in three dimensions and high sensitivity (>110 dB) in vivo with no contact needed between the probe and the tissue.
In biological and biomedical imaging applications, OCT allows for micrometer-scale imaging non-invasively in transparent, translucent, and/or highly-scattering biological tissues. The longitudinal ranging capability of OCT is generally based on low-coherence interferometry, in which light from a broadband source is split between illuminating the sample of interest and a reference path. The interference pattern of light reflected or backscattered from the sample and light from the reference delay contains information about the location and scattering amplitude of the scatterers in the sample. In time-domain OCT (TDOCT), this information is typically extracted by scanning the reference path delay and detecting the resulting interferogram pattern as a function of that delay. The envelope of the interferogram pattern thus detected represents a map of the reflectivity of the sample versus depth, generally called an A-scan, with depth resolution given by the coherence length of the source. In OCT systems, multiple A-scans are typically acquired while the sample beam is scanned laterally across the tissue surface, building up a two-dimensional map of reflectivity versus depth and lateral extent typically called a B-scan. The lateral resolution of the B-scan is approximated by the confocal resolving power of the sample arm optical system, which is usually given by the size of the focused optical spot in the tissue.
The time-domain approach used in conventional OCT, including commercial instruments, such as Carl Zeiss Meditec's Stratus® and Visante® products, has been successful in supporting biological and medical applications, and numerous in vivo human clinical trials of OCT reported to date have utilized this approach.
An alternate approach to data collection in OCT has been shown to have significant advantages in increased signal-to-noise ratio (SNR). This approach involves acquiring the interferometric signal generated by mixing sample light with reference light at a fixed group delay as a function of optical wavenumber. Two distinct methods have been developed which use this Fourier domain OCT (FD-OCT) approach. The first, generally termed Spectral-domain or spectrometer-based OCT (SDOCT), uses a broadband light source and achieves spectral discrimination with a dispersive spectrometer in the detector arm. The second, generally termed swept-source OCT (SSOCT) or optical frequency-domain imaging (OFDI), time-encodes wavenumber by rapidly tuning a narrowband source through a broad optical bandwidth. Both of these techniques may allow for a dramatic improvement in SNR of up to 15.0-20.0 dB over time-domain OCT, because they typically capture the A-scan data in parallel. This is in contrast to previous-generation time-domain OCT, where destructive interference is typically used to isolate the interferometric signal from only one depth at a time as the reference delay is scanned.
FDOCT systems are discussed below with respect to FIGS. 1 through 3. Referring first to FIG. 1, a block diagram illustrating a Fourier domain OCT system in accordance with some embodiments of the present invention will be discussed. As illustrated in FIG. 1, the system includes a broadband source 100, a reference arm 110 and a sample arm 140 coupled to each other by a beamsplitter 120. The beamsplitter 120 may be, for example, a fiber optic coupler or a bulk or micro-optic coupler without departing from the scope of the present invention. The beamsplitter 120 may provide from about a 50/50 to about a 90/10 split ratio. As further illustrated in FIG. 1, the beamsplitter 120 is also coupled to a wavelength or frequency sampled detection module 130 over a detection path 106 that may be provided by an optical fiber.
As further illustrated in FIG. 1, the source 100 is coupled to the beamsplitter 120 by a source path 105. The source 100 may be, for example, a SLED or tunable source. The reference arm 110 is coupled to the beamsplitter over a reference arm path 107. Similarly, the sample arm 140 is coupled to the beamsplitter 120 over the sample arm path 108. The source path 105, the reference arm path 107 and the sample arm path 108 may all be provided by optical fiber.
As further illustrated in FIG. 1, the sample arm 140 may include scanning delivery optics and focal optics 160. Also illustrated in FIG. 1 is the reference plane 150 and a representation of an OCT imaging window 700.
Referring now to FIG. 2, a block diagram of an FDOCT retinal imaging system will be discussed. As illustrated in FIG. 2, in an FDOCT retinal imaging system, the reference arm 110 may further include a collimator assembly 280, a variable attenuator 281 that can be neutral density or variable aperture, a mirror assembly 282, a reference arm variable path length adjustment 283 and a path length matching position 250, i.e. optical path length reference to sample. As further illustrated, the sample arm 240 may include a dual-axis scanner assembly 290 and a variable focus objective lens 291.
The sample in FIG. 2 is an eye including a cornea 295, iris/pupil 294, ocular lens 293 and retina 296. A representation of an OCT imaging window 270 is illustrated near the retina 296. The retinal imaging system relies in the optics of the subject eye, notably cornea 295 and ocular lens 293, to image the posterior structures of the eye.
Referring now to FIG. 3, a block diagram illustrating a FDOCT cornea imaging system will be discussed. As illustrated therein, the system of FIG. 3 is very similar to the system of FIG. 2. However, the objective lens variable focus need not be included, and is not included in FIG. 3. The anterior imaging system of FIG. 3 images the anterior structures directly, without reliance on the optics of the subject to focus on the anterior structures.
In both spectrometer-based and swept-source implementations of FDOCT, light returning from all depths is generally collected simultaneously, and is manifested as modulations in the detected spectrum. Transformation of the detected spectrum from wavelength to wavenumber (or frequency), correction for dispersion mismatches between the sample and reference arms, and Fast Fourier transformation typically provides the spatial domain signal or "A-scan" representing depth-resolved reflectivity of the sample. The uncorrected A-scan may also include a strong DC component at zero pathlength offset, so-called "autocorrelation" artifacts resulting from mutual interference between internal sample reflections, as well as both positive and negative frequency components of the depth-dependent cosine frequency interference terms. Because of this, FDOCT systems typically exhibit a "complex conjugate artifact" due to the fact that the Fourier transform of a real signal, the detected spectral interferogram, is typically Hermitian symmetric, i.e., positive and negative spatial frequencies are not independent. As a consequence, sample reflections at a positive displacement, relative to the reference delay, typically cannot be distinguished from reflections at the same negative displacement, and appear as upside-down, overlapping images on top of genuine sample structure, which generally cannot be removed by image processing.
The maximum single-sided imaging depth available in SDOCT is governed by the spectral sampling interval. The maximum single-sided imaging depth is inversely proportional to the spectral sampling interval. With a fixed number of sampled spectral elements, there is an inverse relationship between the maximum imaging depth and the minimum axial resolution of the imaging system. In commercial FDOCT systems at 830 nm and 1300 nm reported to date, the single-sided imaging depth has been limited to approximately 4 mm. Time domain imaging has been used for greater imaging depths.
The finite spectral resolution of any real FDOCT system, whether governed by the linewidth of a swept laser source in SSOCT, or the geometric optical performance of the spectrometer convolved with the finite pixel size of the detector array in SDOCT, gives rise to a sensitivity "falloff" with imaging depth into the sample. It is common to have greater than 6 dB degradation in signal-to-noise from the position of zero reference delay to the position of maximum single-sided depth. This sensitivity "falloff" limits the portion of the single-sided depth useful for imaging.
To reduce the impact of these limitations in FDOCT imaging, imaging is commonly performed with the entire sample either above or below the reference position, limiting the available imaging depth to between 2 mm and 4 mm, and placing the sample region of interest close to the zero reference delay position.
Each of these constraints poses limitations on the application of FDOCT to clinical ophthalmology. Imaging systems have generally been dedicated to imaging of specific anatomy, such as retina or cornea, where the mirror image artifacts do not fold over onto images of the region of interest. Utility to image deeper anatomic structures, such as the choroid, has been limited by sensitivity "falloff".
Addressing these limitations opens significant new application areas for FDOCT, particularly in ophthalmology. Full range volumetric anterior segment imaging (cornea to lens) for improved diagnosis of narrow angle glaucoma is enabled at speeds 20 times greater and resolutions four times finer than time domain implementations. Real-time image guided surgery, for anterior chamber, cataract, or retina, is enabled by allowing placement of a deep imaging window at any position within the sample, without concern for confounding mirror image artifacts or signal "falloff." Images of the entire eye may be acquired, enabling for the first time modeling in three dimensions the entire optical structure of the eye and enabling whole-eye biometry.

This patent is subject to a terminal disclaimer.

Systems for extended depth frequency domain optical coherence tomography (FDOCT) and related methods


Methods, apparatus, and processor-readable storage media for evaluating cyber attacker behavior using machine learning to identify anomalies are provided herein. An example method includes obtaining, based on events associated with changes in one or more of a registry and a computer process, baseline models comprising a user context representing normal behavior for a first subset of features associated with the events with respect to a given user, an inverse context that represents normal behavior for at least one feature with respect to a particular value of one or more features in the first subset, and a global context representing a behavior of the features across the plurality of users; detecting a new event attributable to the given user; calculating a score for the new event using one or more of the baseline models; and determining that the new event is an anomaly in response to the score satisfying a threshold.

Computer networks, such as corporate Information Technology (IT) networks, are becoming more vulnerable as they evolve. Traditional perimeter defenses for corporate IT networks are failing at an increasing rate such that many cyber security practitioners assume that skilled attackers can easily infiltrate and gain an initial foothold in a modern corporate network. Additionally, attackers are now leveraging existing controls available in commercial products to execute "file-less" attacks (also referred to as "living-off-the-land" attacks), wherein the attackers gain control and manipulate systems remotely without installing any malicious files.
A need exists for improved techniques for evaluating cyber attacker behavior and for identifying anomalies based on the evaluation.

Anomaly detection based on evaluation of user behavior using multi-context machine learning


Systems and methods which utilize low performance circuitry to provide received signal power detection without unacceptably impacting operation of a receiver circuit are shown. Circuitry utilized to provide received signal power detection according to embodiments comprises circuitry dedicated for use with respect to received signal power detection. Performance of the circuitry of the detection path may be lower than that required of circuitry of the signal processing path. However, performance parameters are selected to provide power detection of desired accuracy (e.g., flat gain) and to meet other performance metrics. Embodiments provide a low performance power detection circuit comprising a low performance tuner configuration. Further embodiments provide a low performance power detection circuit comprising a low performance data converter configuration.

Broadband transmission of signals has been in used for a number of years. For example, cable television systems utilize broadband transmission of signals to deliver various content (e.g., video, audio, and data) using a plurality of discrete channels. Many modern cable systems transmit a large number of discrete channels (e.g., 155 channels), each occupying a predetermined bandwidth (e.g., 6 MHz or 8 MHz channel bandwidth), using broadband spectrum (e.g., approximately 50 MHz-1 GHz). Accordingly, various content including broadcast content (e.g., television programs, movies, and audio programs), controlled delivery content (e.g., pay-per-view programs), on-demand content (e.g., individually requested/initiated program delivery), session content (e.g., individual data communication sessions), etc. may be provided through a cable system for selective use by subscribers and/or other receiver points.
Directing attention to FIG. 1, an exemplary cable system is illustrated as cable system 100. Cable system 100 includes cable transmission node 101 coupled to transmission media 102. Cable transmission node 101 may comprise a cable plant head-end, a repeater, or various other nodes utilized in transmission of cable system signals (e.g., 155 channels transmitted in the spectrum from approximately 50 MHz-1 GHz). Although referred to as a transmission node, it should be appreciated that cable systems may be bi-directional (e.g., providing some up-link capability such as for data sessions, interactive programming, etc.) and thus cable transmission node 101 may accommodate transmission and reception of signals. Transmission media 102 couples cable transmission node 101 to a plurality of receiver points, shown here as subscriber premises 111-113. Various devices, such as amplifier 103, may be provided in the cable system to facilitate desired signal communication.
Receiver circuitry may be utilized at the subscriber premises to select particular signals of the broadband transmission and to obtain content there from. Receiver circuit 200 of FIG. 2 shows a receiver circuit configuration which may be utilized at any or all of subscriber premises 111-113 to select a desired signal and obtain content carried by the selected signal. Circuit input 201, such as may be coupled to a tap or "drop" from transmission media 102, provides the signals of the broadband transmission to receiver circuit 200. Filter 211, such as may comprise a band-pass filter, provides signal filtering to substantially exclude signals outside of the spectrum of the broadband transmission (e.g., <50 MHz and/or >1 GHz). Amplifier 221, such as may comprise a low noise amplifier (LNA), provides signal amplification and/or buffering to compensate for noise and facilitate an acceptable noise figure with respect to receiver circuit 200. Mixer 231 provides frequency translation from a radio frequency (RF) used for converting a selected signal (or a contiguous block of signals) to a baseband frequency used in demodulating the selected signal. Filter 212, such as may comprise a low-pass filter, provides signal filtering to substantially exclude signals above the frequency translated selected signal (narrow-band demodulating receiver) or block of signals (wide-band demodulating receiver). Data converter 214, such as may comprise an analog to digital converter (ADC), converts the selected signal or block of signals to a digital representation for digital processing by digital signal processor (DSP) 251.
It should be appreciated that operation of cable system 100 introduces undesired attributes to the transmitted signals. For example, noise, signal distortion, and group delay may be introduced to signals transmitted by cable system 100. Transmission media 102 may provide a frequency response whereby different portions of the broadband transmission spectrum are affected differently by distortion. For example, coaxial cables typically utilized in cable transmission systems such as cable system 100 provide a frequency response in which higher frequencies are attenuated more so than lower frequencies. That is the transmission media rolls off at the high frequencies and thus higher frequencies experience greater attenuation as they propagate through the transmission media than do low frequencies. Broadband transmission in such a system experiences frequency response "tilt". Such frequency response tilt can be significant over a wide frequency range, such as the approximate gigahertz range common to cable transmission systems.
Various components of cable system 100 may be adapted to compensate for and/or mitigate the introduction of undesired attributes to the transmitted signals. For example, cable transmission node 101 and/or amplifier 103 may be adapted to provide offsetting tilt with respect to the broadband transmission in order to compensate for the aforementioned high frequency attenuation. As shown by graph 121 of FIG. 1, the amplitude of the broadband transmission signal may receive a positive amplitude tilt such that signals at the higher frequency end of the spectrum are transmitted at a greater amplitude. This positive amplitude tilt may be utilized to offset frequency response tilt, at least to some extent, associated with broadband transmission of signals. Nevertheless, transmission through media of sufficient length may overcome the positive amplitude tilt, resulting in a negative amplitude tilt of the broadband transmission signal, as shown by graph 123 of FIG. 1.
As illustrated by graphs 121 and 123 of FIG. 1, receiver circuits of subscriber premises disposed at different points in the cable system may experience appreciably different received signals. For example, receiver circuit 200 of subscriber premise 111, disposed nearest to cable transmission node 101, may experience received signals (graph 121) having not only relatively little attenuation from propagation through the cable transmission system, but also having the positive amplitude tilt provided to compensate for frequency response tilt of transmission media 102. In contrast, receiver circuit 200 of subscriber premise 113, disposed furthest from cable transmission node 101, may experience received signals (graph 123) having not only appreciable attenuation from propagation through the cable transmission system, but also having negative amplitude tilt resulting from the frequency response tilt of transmission media 102.
Accordingly, measurement of signal levels as received at various locations, such as subscriber premises, may be utilized by devices of cable system 100. For example, cable transmission node 101 may obtain power reports from subscriber premises devices for use in controlling aspects of the broadband transmission of signals to improve or optimize operation of cable system 100. Thus, DSP 251 may operate to provide power measurement processing with respect to a digital representation of a signal provided thereto for reporting to cable transmission node 101 and/or other devices of cable system 100.
In order to provide information regarding the power level of the channels of the broadband transmission of signals as received by receiver circuit 200 (i.e., the channel power level at circuit input 201), DSP 251 of typical prior art embodiments operates to correct the channel power level as measured by DSP 251 to account for the effects of components (e.g., filter 211, amplifier 221, mixer 231, filter 212, and data converter 214) of receiver circuit 200. For example, DSP 251 may operate to correct a channel power measurement to subtract a gain factor of a receiver circuit amplifier, add a signal loss amount associated with a receiver circuit filter, etc.
The specifications for many cable transmission systems impose relatively precise requirements upon the measurement of received signal power levels. For example, some DOCSIS specifications impose a ±3 dB measurement requirement for received signal power level reporting. Thus, manufacturers must generally provide extensive calibration with respect to receiver circuits, such as to measure the frequency response for many receiver circuit components over all or substantially all of the broadband spectrum, in order to facilitate accurate correction of the channel power level as measured by a receiver circuit. A lookup table, for example, may be generated through such calibration for use by DSP 251 in applying appropriate corrections to a power level measurement for a particular channel in order to provide a received signal power level report of sufficient accuracy. Such extensive calibration and its attendant lookup table present a significant cost, time, and resource utilization challenge with respect to providing acceptable received signal power level measurement in the prior art.
Additional challenges are posed in the heretofore prior art implementations. For example, DSP 251 of receiver circuit 200 is operable to provide signal demodulation of selected signals provided thereto for utilization of content by a user or termination device. Accordingly, where a power level measurement is needed for a signal of a channel other than that currently selected for demodulation (i.e., translated to baseband by mixer 231 and passed by filter 212), interruption of demodulation of a desired channel may be necessary in order to perform received signal power level measurement. This may be true even where multiple signals (e.g., a contiguous block of channels) are converted to baseband.
The need for interruption of desired channel demodulation is illustrated in FIG. 3A (illustrating the received channel profile at subscriber premise 111) and 3B (illustrating the received channel profile at subscriber premise 113), wherein channel 301 is a currently selected channel being demodulated by DSP 251 and channel 302 is a channel for which received signal power level measurement is desired. Where receiver circuit 200 provides for baseband processing of a single channel, as indicated by pass-bands 310a and 320a, demodulation of channel 301 must be interrupted in order to provide channel 302 to DSP 251 for power measurement processing. Similarly, even where receiver circuit 200 provides for baseband processing of multiple channels (e.g., a contiguous block of 4 channels), as indicated by pass-bands 310b and 320b, demodulation of channel 301 must be interrupted in order to provide channel 302 to DSP 251 for power measurement processing. However, interruption of channel demodulation may result in loss of data, interruption in service, and other undesirable and/or unacceptable consequences.

Systems and methods providing signal power detection using low performance circuitry


A method and apparatus for processing data packets in flow-aware network nodes is disclosed for storing flow data without altering transmission data throughput for a limited cost. The method and apparatus for processing data packets in flow-aware network nodes includes alternate usage of a fast access internal memory and a slower speed access external memory which provides low latency yet comprehensive flow-awareness. The method for processing data packets in flow-aware network nodes is particularly useful for overcoming requiring extensive usage of fast access memory of flow-aware network nodes known in the art.

The present invention relates to the field of communication networks and more precisely of data packet processing in packet routers.
Data packet routers are located in the network nodes. In the case of flow aware packet networks, said routers and particularly the ones corresponding to nodes located at the edges of the network have to keep a memory of the state information of the flows entering the system. Such recording has to be achieved for all the flows received by the network nodes. In the case of high speed channels (≧10 Gb/s), said flow state information associated with flow IDs needs to be available as fast as possible to prevent delays during packet processing.Besides, the flow size may vary from a "mouse" flow comprising a few (a dozen for example) packets to "elephant" flows comprising hundreds of packets. The memory capacity needs therefore to be large enough to cover any situation.Thus, flow-information storage needs to combine large capacity memory with reduced latency access of the stored data such that transmitted packets can be processed according to the data bitrate of the transmission. Moreover, the cost of such memory has to remain as low as possible to be widely used.

Method for processing data packets in flow-aware network nodes


A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

U.S. Patent Application Publication No. 2011/0050334 (referred to as "Patent Document 1") discloses a semiconductor device including a package board in which some or all of passive elements, such as inductors or capacitors, are embedded, and a voltage control device (hereinafter, also referred to as a "voltage regulator") including active elements such as switching elements. In the semiconductor device of Patent Document 1, a voltage regulator and a load to be supplied with a power supply voltage are mounted on a package board. The DC voltage adjusted by a voltage adjustment unit is smoothed by a passive element in the package board and supplied to a load.
Semiconductor devices having the above-described voltage regulator are applied to, for example, electronic devices such as a mobile phone and a smartphone. In recent years, size reduction and thinning of electronic devices have been promoted, and accordingly, size reduction of the semiconductor devices themselves has been desired.
In the semiconductor device of Patent Document 1, the inductor and the capacitor are laid out and embedded in the same layer of the package board. In this case, when the area of the mounting face of the package board is reduced to reduce the size of the semiconductor device, the inductance of the inductor and the capacitance of the capacitor formed in the package board cannot be secured sufficiently, and, consequently, desired characteristics cannot be implemented.

Semiconductor composite device and package board used therein


A guide convex portion is formed on a base plate in parallel to an illumination optical axis. Further, a fixed-side supporting member is provided in the base plate. A first opening is formed in an upright portion of the fixed-side supporting member. A slide supporting member can be provided on the base plate. A second opening is formed in the upright portion of the slide supporting member. By inserting a tapered rod into the second opening at its light incidence side and by moving the slide supporting member along the aforementioned guide convex portion, the slide supporting member is stopped at a predetermined position and, at this position, the slide supporting member is fixed.

1. Field of the Invention
The present invention relates to a rod integrator holder for holding a tapered rod integrator and a projection type video display including the same.
2. Description of Related Art
In recent years, attempts have been made to mount, on projection type video display, an illuminating system employing tapered rod integrators for reducing the divergence angles of light emitted from light sources such as LEDs and for reducing the luminance non-uniformity within the light illumination surfaces. Further, there have been proposed rod integrator holders for holding the tapered rod integrators (refer to Japanese Unexamined Patent Publication No. 2004-94115).

Rod integrator holder and projection type video display


The present invention suppresses noise that is possibly generated due to threshold processing during frequency conversion. The image processing device 100 includes: a threshold processing unit 110 for executing threshold processing, by using a first parameter for conversion coefficients of respective frequency components that are obtained by frequency conversion of a block consisting of multiple pixels; a calculation unit 120 for calculating feature quantities of the constituent multiple pixels of the block; a determination unit 130 for determining a second parameter on the basis of the calculated feature quantities; and a correction unit 140 for correcting, by using the determined second parameter, the threshold-processed conversion coefficients of the respective frequency components.

It is necessary to reduce noise contained in an image for reproducing an image more crisply as well as for suppressing emphasis of noise caused by image processing. The noise includes, for example, the additive white Gaussian noise or Poisson noise.
There are techniques to reduce noise contained in an image. One example of the techniques is the Redundant Discrete Cosine Transform or Redundant DCT, hereinafter also referred to as the RDCT, which is a type of the Discrete Cosine Transform, hereinafter also referred to as the DCT (refer to NPL 1, for example). The RDCT obtains an image with less noise by correcting a conversion coefficient (amplitude) obtained through the DCT on each block by using Soft Shrinkage or Hard Shrinkage and executing inverse conversion of the corrected conversion coefficient.
Assuming that noise contained in an input image is additive white Gaussian noise having a mean 0 and a variance σ2, components of the noise component diffuse to all conversion coefficients that have undergone the DCT processing. On the other hand, according to the sparse representation theory for image signals, energy generally tends to concentrate on a particular frequency component of a noise-free image signal after the DCT processing. Accordingly, a noise-free image signal may be represented by a relatively small number of conversion coefficients. Based on this property, it is possible to maintain the components of an original signal while reducing a noise component by executing threshold processing that rejects a conversion coefficient having a small absolute value and that maintains a conversion coefficient having a large absolute value. Note that frequency conversion techniques used for noise reduction may include the DCT as well as the Hadamard transform and the wavelet transform.

Image processing device, image processing method, and recording medium


A light source assembly includes a heat interception portion disposed between a light source unit and an optical member. The heat interception portion may be extended from the light source unit. Alternatively, the heat interception portion may be extended from a receiving container that receives the light source unit and the optical member. The heat transferred from the light source unit to the optical member may be reduced. Thus, deformation of the optical member may be prevented and the display quality of the image from the liquid crystal display apparatus using the light source assembly may be improved.

1. Field of the Invention
The present invention relates to a light source assembly, a backlight assembly having the light source assembly and a liquid crystal display apparatus having the light source assembly. More particularly, the present invention relates to a light source assembly that emits a heat generated in a light source unit, a backlight assembly having the light source assembly and a liquid crystal display apparatus having the light source assembly.
2. Description of the Related Art
Generally, liquid crystal has a physical property of interstate that is between solid state and liquid state. The arrangement of the liquid crystal is changed in accordance with the direction of electric field applied thereto, and then the light transmittance of the liquid crystal varies in accordance with the liquid crystal arrangement.
A liquid crystal display (LCD) apparatus displays an image containing information by adjusting the arrangement of the liquid crystal. The LCD apparatus is generally light and thin, and may be employed in various fields such as a notebook computer, a mobile telecommunication device or a liquid crystal television receiver, etc.
The LCD apparatus has a liquid crystal controlling part and a light supply part. The liquid crystal controlling part controls the arrangement of the liquid crystal, and the light supply part provides a light to the liquid crystal of the liquid crystal controlling part.
The liquid crystal controlling part generally includes a first substrate having a pixel electrode, a second substrate having a common electrode, and a liquid crystal layer interposed between the first and second substrates. The liquid crystal controlling part has a plurality of pixel electrodes in accordance with resolution of the liquid crystal display apparatus, and one common electrode corresponding the pixel electrodes. Each of the pixel electrodes is electrically connected to a thin film transistor, and a reference voltage is applied to the common electrode. The pixel electrode and the common electrode are generally transparent when the liquid crystal display apparatus has a light supply part.
The light supply part provides a light to the liquid crystal layer. The light passes through the pixel electrode, the liquid crystal layer and the common electrode. The quality of an image from the light controlling part depends on the brightness and brightness uniformity of the light supply part. As the brightness and the brightness uniformity of the light from the light supply part increase, the quality of the image is improved.
A conventional light supply part includes a cold cathode fluorescent lamp (CCFL) having a cylindrical shape. The CCFL has relatively high brightness and long lifetime. Further, the CCFL generates little heat compared to an incandescent lamp. Although the CCFL generates less heat than that of the incandescent lamp, the heat may induce problems.
Surface temperatures of the CCFL in the conventional liquid crystal display apparatus are shown in Table 1 below.
TABLE 1Surface Temperatures of the CCFL in Conventional LCD ApparatusLamp current (mA)4.04.55.05.56.06.45Lamp temperature (° C.)9093.597.6102106.9111.2Holder temperature (° C.)81.684.788.592.396.5100.2
In the conventional CCFL, light intensity increases in proportional to the lamp current. In addition, the surface temperatures of the holder and the lamp increase in proportional to the lamp current. In Table 1, when the CCFL has a lamp current of 6.45 mA, the lamp has a surface temperature of 111.2° C. and the holder has a surface temperature of 100.2° C.
Since the holder undergoes a deformation at a temperature greater than about 240° C., the holder may not be damaged by the lamp current of about 6.45 mA. However, an optical member that is in contact with the holder such as a light guide plate may be deformed or damaged at a temperature greater than about 100° C. Additionally, optical sheets disposed on the light guide plate may also be deformed or adhere to a light guide plate at a temperature greater than about 100° C.
The heat generated in the CCFL may deform optical members such as a light guide plate or an optical sheet. The heat also liquidizes the liquid crystal in the LCD panel, thereby deteriorating the displaying quality of the LCD apparatus.

Light source assembly, backlight assembly and liquid crystal display apparatus having the same


A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

As microelectronic devices become highly integrated, problems associated with degradation characteristics may arise. Examples of these problems for a transistor may include short channel effects, Drain Induced Barrier Lowering, subthreshold swing, increased leakage current, as well as increased parasitic capacitance between the junction region and the substrate.
Non-planar transistors, that is, transistors where the channel is defined on surfaces of a three dimensional body, typically in the form of a fin (such as, for example, the fin in a FinFET transistor including either a double-gate, an independent gate, or a trigate transistor), have been proposed in order to address many of the above integration problems. However, the introduction of non-planar transistors has introduced its own particular problems, such as, for example, corner effects, the difficulty of fabricating fins with high aspect ratios, floating body effects related to a fin built on an SOI substrate, and self-heating for non-planar transistors built on an SOI substrate, to name just a few.
In addition to the above-mentioned problems sometimes associated with non-planar transistors, one particular issue concerns fringe effects associated with unwanted capacitance between the gate electrode and the fin in a non-planar transistor built on a bulk silicon substrate. In this respect, reference is made to FIG. 1, where a conventional trigate transistor 100 is depicted. As shown in FIGS. 1a and 1b, trigate device 100 includes a substrate body 102 including a fin 104 and a substrate base 106. A device isolation layer 105 is provided on the substrate base 106 of substrate body 102 in order to isolate portions of the substrate body from a gate electrode 110 extending over the fin 104 as shown. Fin 104 includes a device portion 108, which corresponds to the portion of fin 104 extending above dotted indicator line A-A Device portion 108 includes an upper surface 112, and side walls 114 and 116, which together contribute to provide the channel regions of trigate device 100. Surfaces 112,114 and 116 are covered by gate dielectric layer 119, a function of which is to control a capacitance between gate electrode 110 and device portion 108 to thereby control charge flow in the channel region. Dotted indicator line A-A has been provided. on FIGS. 1a and 1b to mark an upper surface of device isolation layer 105 corresponding to a lower demarcation line for device portion 108.
As seen in FIGS. 1a and 1b, disadvantageously, the provision of device isolation layer 105 onto substrate body 102 by way of etching typically results in the formation of side recesses 118 on each side of fin 104 below device. portion 108 as shown. It is noted that FIG. 1b shows a partially cut-off version of the trigate transistor 100, that is, a version where the source and drain portions are not fully shown by virtue of the device portion as having been cut off at the source and drain portions to show the recesses 118. However, general regions of device portion 108 corresponding to the source and drain portions are indicated by arrows as the source and drain regions S and D, respectively. The recesses 118 typically result from an etch process to etch the material of isolation layer 104 to the level of line A-A. When the gate electrode 110 is provided over fin 104, in the presence of recesses 118, the material of the same typically disadvantageously fills recesses 118 forming unwanted recess. electrode portions 120 as shown. The recess electrode portions 120 extending along the sides of fin 104 along a length thereof disadvantageously generate unwanted capacitance with regions of fin 104 extending below the device portion 108. In the presence of such fringe capacitance, fringe effects are disadvantageously observed according to which control of charge flow within the channel region becomes compromised, thus negatively impacting an electrical performance of the device as a whole.
The prior art has failed to provide a simple and effective manner of controlling fringe effects brought about as a result of recess electrode portions in non-planar microelectronic devices built on bulk substrates.

Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same


This disclosure discloses a print label producing apparatus comprising an apparatus main body, and a cutting blade receiving member, the apparatus main body comprising a feeder, a printing head, a cutting blade configured to press and cut a print-receiving tape, and a holding portion configured to attach and detach the cutting blade receiving member, and the cutting blade receiving member comprises a first cutting blade receiving member comprising at least one concave portion configured to receive at least a part of the print-receiving tape, and a first contact portion configured to receive and stop the cutting blade, disposed at the adjacent position from the concave portion, and a second cutting blade receiving member comprising a second contact portion configured to receive and stop contact of the cutting blade, and the holding portion is configured to permit selective mounting of one of the first and second cutting blade receiving member.

1. Field
The present disclosure relates to a print label producing apparatus that produces print labels, and a cutting blade receiving member used in the same.
2. Description of the Related Art
There are known print label producing apparatuses that feed a print-receiving tape, cut the tape at a desired length, and produce a print label. According to this print label producing apparatus of prior art, a print-receiving tape on which printing was performed by printing means is fully cut in a thickness direction by a cutter, thereby producing a print label. According to this print label producing apparatus of prior art, in order to perform cutting of a desired mode other than the full cutting (hereinafter suitably referred to as "desired cutting"; half cutting in this example), a half-cutter capable of partially cutting the print-receiving tape in the thickness direction is provided.
According to the prior art, both means (a cutter) for performing regular full cutting and means (a half-cutter) for performing desired cutting are separately provided, leading to problems such as difficulties in decreasing the apparatus size and increases in manufacturing costs.

Print label producing apparatus and cutting blade receiving member


Recombinant cells and an improved method utilizing them is disclosed for the preparation of an optically pure, L-amino acid from its D and D,L isomer forms. The process utilizes cell cultures that possess high aminotransferase activity that exhibits moderate selectivity in the conversion of D and L amino acids to their respective 2-keto acids as well as absolute stereospecificity in the conversion of the 2-keto acids to the L isomer alone.

It is well recognized that all amino acids exist in one of two isomer forms, known as the L-form and its mirror image, the D-form. The aromatic amino acid phenylalanine, for example, has two optically active enantiomers, L-phenylalanine and D-phenylalanine. In its major application, a component of aspartame the popular low calorie sweetener, it is preferred to separate the two isomers or convert a racemic mixture of the two to obtain one of the enantiomers that is relatively free of contamination by the other. Aspartame itself is a dipeptide comprised of two amino acids, aspartic acid and phenylalanine. It has been known for quite some time that the sweetening property of the dipeptide is dependent upon the stereochemistry of these individual amino acids.
Since both of these amino acids can exist in either the D (dextro) or L (levo) form, it has been determined that L-aspartyl-L-phenylalanine esters are sweet while the corresponding D-D, D-L and L-D isomers are not. Combinations of the isomers which contain the L-L dipeptide, DL-aspartyl-L-phenylalanine, L-aspartyl DL-phenylalanine and DL-aspartyl-DL-phenylalanine are sweet, but only half as sweet since the racemate contains 1/2 of the L-L moiety. Hence, in the manufacture of aspartame, it is most desirable to have a starting material of phenylalanine that is comprised of purely the L-isomer form.
Phenylalanine is conventionally made either through chemical synthesis, enzymatic synthesis or fermentation. Most of these methods result in a racemic mixture of the D and L isomers which must either be separated or resolved, to yield a pure L-phenylalanine fraction. Ideally, a method or process whereby the D isomers could be converted to the L isomer would not only do away with the need for the additional and costly separation or resolution steps, but it would also increase the final yield of the desired product.
Biocatalytic processes resulting in the formation of a specific isomer are known in the art. For example, L-phenylalanine can be produced via enzymatic synthesis from cinnamic acid and ammonia using the enzyme phenylalanine-ammonia lyase. L-alanine may also be produced in a pure fraction by the enzymatic decarboxylation of L-aspartic acid. See U.S. Pat. Nos. 3,458,400 and 3,463,704. Wood et al., U.S. Pat. No. 4,600,692 also utilized transaminases in the preparation of L-phenylalanine and oxaloacetate from phenylpyruvic acid, pyridoxal-5-phosphate and an amine donor such as L-glutamate or L-aspartate in a reversible reaction.
Of particular interest is Rozzell, J., U.S. Pat. No. 4,518,692. A process is disclosed therein whereby L-amino acids are produced by transamination. The process comprises reacting an alpha-keto acid or a racemic mixture of an amino acid with L-aspartic acid in the presence of a transaminase enzyme to produce an alpha amino acid corresponding to the alpha keto-acid and oxaloacetate which must be subsequently decarboxylated. The transamination reaction requires a multi-enzyme system comprising the addition of oxaloacetate decarboxylase, D-amino acid oxidase and pyridoxal-5-phosphate which are not needed in the process of the present invention. D-amino acid oxidase is a mammalian enzyme extracted from hog kidney. A byproduct of this reaction is hydrogen peroxide which has been shown to inactivate enzymes and can cause decomposition of 2-ketoacids. The enzyme is also expensive and thereby increases the cost of the overall process.
Also of interest to the background of the present invention is U.S. Pat. No. 4,745,061 to Aretz et al. which discloses a D-amino acid transaminase that has been isolated from Bacillus licheniformis. The enzyme is shown to be useful in the preparation of D-amino acids from .DELTA. keto acids and is suitable for resolving racemates of D,L amino acids by converting the D-amino acid to its corresponding .alpha.-keto acid which is then separated. The recovery of pure L-amino acid would thus require costly purification and separation steps not necessary in the practice of the present invention.
It is an object of the present invention to provide a process for the production of L-amino acids using a transaminase that is stereospecific in the synthesis of L-amino acids. More specifically, it is an object of the present invention to provide a process for the production of optically pure L-phenylalanine from a D, L racemic mixture using a transaminase from a culture without the required addition of aspartate, D-amino acid oxidase, oxaloacetate decarboxylase or catalase.

Racemic conversion of using a transaminase


A welding apparatus includes a first welding element, a second welding element and a support on which the first welding element and the second welding element are mounted and which is movable relative to the welding apparatus. The support is configured to move the first welding element and the second welding element respectively from a first start position to a first end position and from a second start position to a second end position as the support is moved such that welding points of the first welding element and the second welding element are altered. The first welding element and the second welding element are oriented to mirror one another at the first start position and at the second start position. The first welding element and the second welding element are oriented to mirror one another at the first end position and at the second end position.

The present disclosure relates to manufacturing apparatuses and processes and, more specifically, to welding apparatuses and processes.
When components are manufactured in mass, it is commonplace to use a single manufacturing apparatus for variations of a single component. For example, the manufacturing apparatus may be equipped with features that allow certain parameters to be adjusted in accordance with the specifications for a given variation of the component. However, there may be a variation of the component that cannot be manufactured by manipulation of the adjustable parameters and it may be necessary to design a mechanism that alters the single manufacturing apparatus specifically for this variation of the component.


A non-foaming, non-viscous, alcohol-free, water-based pressurized hair-fixative spray product for use as the total fill in an aerosol container by delivery from an actuated-valve of predetermined dimensions, particularly the vapor tap and stem orifice sizes.

1. Field of the Invention
This invention relates to hair sprays, and more particularly to an alcohol-free, water-based pressurized hair-fixative spray product.
2. Description of the Prior Art
Almost all commercial hair spray compositions contain ethanol as a solvent for the film-forming hair fixative resin. However, ethanol is disfavored because it is a volatile organic compound (VOC) which can pollute the air; also it can give beauticians upper respiratory infections and irritations of the nose and skin; and it is a flammable substance. Accordingly, it is desired to provide a hair spray product which is alcohol-free, i.e., it is a water-based formulation, and which can perform as effectively in commercial use as an ethanol-based product.
Shernov, in U.S. Pat. No. 5,053,218, described a hair spray product including a non-alcohol, one-liquid phase, hair spray composition of shellac, water and dimethyl ether. However, the disclosed system therein produced a hard spray onto the hair of the user, which was considered objectionable because it ruffled the hair. Moreover, it was difficult to maintain a spray of a uniform particle size and composition during evacuation of the entire fill contents of the aerosol can.
Sramek, J., in U.S. Pat. No. 5,068,099, disclosed an aerosol hair spray package having a low delivery rate. However, the hair spray composition used therein was an alcohol-based formulation, there being no more than 10% by water present.
Accordingly, it is desired herein to provide new and improved water-based hair care product for use with a predetermined valve-actuator aerosol packaging system, which combination provides the advantageous performance properties necessary for commercial acceptance of such water-based composition.

Non-foaming, non-viscous, alcohol-free, water-based, pressurized hair spray product


Automatically aligning virtual blocks of partitions to blocks of underlying physical storage is disclosed. In some embodiments, a starting offset of a partition included in a logical container is detected. In some embodiments, a misalignment correction amount for a partition included in a logical container is detected. In some embodiments, a misalignment associated with a partition included in a logical container is corrected.

In typical systems, a partition within a virtual disk can start at an offset that is not a multiple of the block size used by the physical underlying storage subsystem that stores the virtual disk. As a result, inefficiencies are created in accessing data stored on the storage subsystem. For example, a single block access at the virtualization level (e.g., the access is made to a virtual disk block of a virtual disk partition) may map to multiple physical blocks or straddle multiple physical blocks (e.g., instead of a single physical block) at the underlying storage subsystem. Accessing multiple physical blocks may require reading more data than is needed and discarding the unneeded data, which could be undesirable.

Automatically aligning virtual blocks to physical blocks


An ATM switch contains several interface units (including a source interface unit), several virtual-channel (VC) switches (including a source and destination VC switch), and several virtual-channel identifiers (VCI) for each ATM cell. Configuring the ATM switch causes the source interface unit to assign a starting VCI to a cell to indicate an intended destination for the cell within the ATM switch and to pass the cell to a source VC switch. If the intended destination is an interface unit not directly coupled to the source VC switch, the source VC switch converts the starting VCI to an intermediate VCI that reflects the intermediate and destination locations relative to the intermediate VC switch. A destination VC switch receives the ATM cell and converts the intermediate VCI to a final VCI that reflects the source and the destination locations relative to the destination VC switch, and delivers the ATM cell to the destination.

The present invention relates generally to a technique for configuring an asynchronous transfer mode (ATM) switch or set of switches and switching ATM cells, and specifically to a method and apparatus for routing ATM cells with a generic addressing scheme that operates transparently to the physical location of the source and destination.
ATM offers an advantageous transport structure for digital communications by using a high-bandwidth multiplexing scheme for packet-based transmission of messages. ATM systems communicate information using fixed-size cells of relatively short length. FIG. 1 is a diagram of one such cell. Each cell 10 contains a 5-octet label 12, also called a header, that identifies the cell and the cell's connections. A 48-octet payload 14 follows the header in the ATM cell and carries information intended for a recipient. Switching networks rely on information stored in the header of ATM cells to switch and multiplex the cells along appropriate routes.
ATM header 12 includes a virtual path identifier (VPI) and a virtual connection identifier (VCI) label, referenced collectively as 16, together with other error detection fields 15 and functions 17. VPI-VCI 16 indicates the transport connection for user information within payload 44 and other information.
A switched ATM network will include several nodes, connected together via an ATM switch. A node may comprise a circuit board having electronics for transmitting, receiving, and processing information carried within the payload of the ATM cells. The ATM switch establishes virtual connections between the nodes such that one node can communicate with another node in the ATM network only by way of the ATM switch.
An ATM switch may include a set of virtual channel switches and at least one virtual path switch. A virtual channel switch deciphers the VCI from the VPI-VCI of a received ATM cell and routes the cell locally to nodes coupled to it. A virtual path switch couples virtual channel switches together and routes the ATM cell to an appropriate virtual channel switch based on the VPI of the VPI-VCI field 16.
The VPI-VCI for an ATM cell has a maximum length of 16 bits. Using all 16 bits for the VPI-VCI permits the addressing of 2.sup.16, or 65,536, destinations, and using fewer bits decreases the number of destinations. For example, if a switched network is configured to use only 12 bits in the VPI-VCI for addressing, the network can send an ATM cell to only 2.sup.12, or 4,096, unique interface units. On the other hand, using all 16 bits of the VPI-VCI permits the addressing of more destinations but restricts the use of those bits for other purposes.
Also, the use of unique addressing locations for each possible connection in an ATM switch limits the flexibility of adding or deleting subsystems within the switch. Each replacement module within such an ATM switch must be specially configured with the unique addresses, which increases maintenance and installation efforts. In addition, replacing or adding interface units within a conventional ATM switch may require reconfiguring the entire switch with unique addresses for the interface units.
In light of the foregoing, a need exists for an addressing structure for an ATM switched network that permits using fewer than the entire VPI-VCI field for routing ATM cells, while both allowing an increased number of connections between sources and destinations and decreasing installation and maintenance requirements.

ATM switch having location independent virtual-connection switches


An apparatus and method for firing a projectile in which one part of the projectile rotates and the other part of the projectile does not rotate where is it used for delivering a line. The projectile firing apparatus includes a projectile having a part that rotates and a part that does not rotate, and further a barrel with a bore having spiraled grooves and at least two channels for the nonrotating part of the projectile to travel through when the projectile is fired. A line dragging system is mounted on the front of the barrel and engages to the nonrotating part of the projectile. The line dragging system is made of a wire frame including a cylindrical portion, engaging members, frame sides, and engaging locks. Upon firing the projectile, the rotating part moves through the bore of the barrel while the nonrotating part moves through the channels of the barrel. The nonrotating part of the projectile engages the line dragging system on its engaging members after exit of the barrel and delivers the line in flight. The rotational motion of the projectile allows the projectile to be stabilized in flight for better precision and range, while the nonrotational motion of the projectile allows a balanced and untangled line to be delivered to its destination.

This invention relates to firing projectiles, and more particularly to an apparatus and method for firing a projectile in which one part of the projectile is rotating and the other part is not rotating. Also, the nonrotating part of the projectile is attached to a line to be delivered upon firing of the projectile.
Previous projectiles to be fired would include using smooth bore launch tubes and firing a projectile with fins attached for stabilizing means, and where the line would be attached asymmetrically to the top of the projectile or on its side. The problem with this type of launcher and projectile is that it does not have the best accuracy and range, and the line attached would not be balanced in flight. Other methods have employed a self-stabilizing spinning projectile where the projectile is rapidly rotating around its central axis while being pushed through a rifled barrel. Although the rotating action of the projectile increases accuracy and range, the line attached to the projectile would also be rotating thereby twisting the line creating drag during the projectile""s flight.
U.S. Pat. No. 4,996,924 to McClain discloses aerodynamic projectiles in which the projectiles have helical grooves and lands to promote spinning action of the projectile. A particular projectile is described wherein the projectile includes two parts, a conical nose and a main body, both with helical grooves, however the grooves of each part are oppositely oriented to create counter rotational action between the two parts at the same time upon firing. Ball bearings allow the two parts to rotate relative to each other while being connected. This projectile is not connected to a line, nor is one of the parts of the projectile not rotating during flight.
The present invention provides an apparatus and method for firing a projectile. The present invention provides an apparatus and method for firing a projectile in which one part of the projectile rotates while the other part is not rotating. The present invention reduces drag by stabilizing the flight of the projectile using a self-stabilization spinning technique, while the nonrotating part of the projectile moves through the barrel and can then be symmetrically connected to a line upon leaving the barrel. By rotating one part of the projectile and keeping the other part from rotating, the present invention is able to rotate a projectile and is able to carry a straight and untangled line for high accuracy and long range. Further, by symmetrically attaching the line upon firing, the projectile will maintain a balanced flight pattern also adding to accuracy and range.
One embodiment of firing a projectile in accordance with the principles of the present invention includes a projectile with two parts. Upon firing the projectile, one part is simultaneously rotating and the other part is not rotating. A barrel, which includes a bore having spiraled grooves, is used to fire this projectile wherein at least two straight symmetrical channels run along the inside of the barrel. The rotating part of the projectile will move along this bore having spiraled grooves in the barrel upon firing, while the nonrotating part of the projectile will move along the symmetrical channels of the barrel. A wire frame with a line connected is attached to the nonrotating part of the projectile and moves with this nonrotating part of the projectile through the channels inside of the barrel as the whole projectile is fired. Before the projectile leaves the barrel the frame and line are pointed forward and the projectile is pushing the frame connected to the nonrotating part through the channels inside of the barrel. After the projectile leaves the barrel the frame is pulled backward and locked into a position so that it is behind the projectile during flight. The projectile, in flight, is stabilized by its rotating portion while keeping the line untangled and balanced with its nonrotating portion.
A preferred embodiment of firing a projectile in accordance with the principles of the present invention includes a projectile having a part that rotates and a part that does not rotate and a barrel including a bore having spiraled grooves and at least two symmetrical grooves that form straight channels along the length and inside the barrel. Further, a line dragging system is mounted to the front end of the barrel, which is made of a wire frame, and includes an attached line, and engaging members connectable to the nonrotating part of the projectile. The wire frame is positioned at the inner diameter of the front end of the barrel. The engaging members of the line dragging system are symmetrically in line with the exit openings of the barrel channels. The engaging members contain an engaging lock for the nonrotating part of the projectile to travel into the engaging members and connect the entire line dragging system. As the projectile is fired, the rotating part of the projectile is pushed through the bore of the barrel while rotating. The nonrotating part of the projectile moves through the channels of the barrel, not rotating, and after leaving the barrel it travels into the engaging members and engages the lock contained in the engaging members. The line dragging system is now symmetrically attached to the projectile while in flight. The attached line is connected to the frame sides of the line dragging system. The rotation of one part of the projectile allows for stabilization of the flight pattern thereby attaining high accuracy and range. Also, the symmetrical attachment of the line dragging system to the nonrotating part of the projectile balances the projectile, during flight, increases accuracy and range, and further delivers a straight untangled line.
These advantages and features of the novel apparatus and method characterizing the invention are pointed out with particularity in the claims annexed hereto and forming a part thereof. However, for a better understanding of the inventive method, its advantages and objectives attained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying description, in which there is described a preferred embodiment of the invention.

Apparatus and method for firing a projectile


The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies.

The conventional approach to electronic packaging and interconnection has been to package individual integrated circuit (IC) chips in a single package and to attach these packages to a printed circuit board to provide interconnection between the individual IC chips. In recent years, this approach has met with problems of speed, size, and interconnection density due to ever constant demands for reduced size and increased performance from such integrated circuit packages.
One solution to many of the above problems is the multichip module (MCM). In an MCM, bare (unpackaged) IC chips are interconnected by means of a miniature printed circuit board whose interconnection pitch may match the pitch of the IC chip. There are presently two main classes of MCM. These are the "chips last MCM" and the "chips first MCM". In the chips last MCM, the miniature circuit board is fabricated first and then the bare IC chips are attached and interconnected to the circuit board. The method of interconnection is usually wire bond or solder bump. In the chips first MCM, the chips are placed and bonded to a substrate, and a miniature circuit board is then built above the chips. The method of interconnection, usually entails forming IC chips as an integral part of the processing of the circuit board. Currently, the industry uses build-up technology to interconnect IC chips in the chips first MCM. Build-up technology to interconnect IC chips in the chips first MCM is generally known. One such technique that is relevant to the present subject matter is discussed in U.S. Pat. No. 6,159,767.
As mentioned above, the chips first MCM requires placing the IC chips first relative to each other on a substrate. It is generally difficult to maintain consistency during placement and bonding of the IC chips onto a substrate. The inconsistencies in placing and bonding IC chips onto a substrate generally result in coplanarity and alignment problems between the IC chips and the substrate.
Generally, a thicker dielectric layer is required in forming the miniature circuit board over the IC chips to overcome the above-described inconsistency problems. The thicker the dielectric layer, the higher the thermal buildup and the mechanical stress generated during post-processing operations of the multichip module. In addition, the thickness of the dielectric layer formed over the IC chips can vary substantially due to coplanarity problems between the upper surfaces of the IC chips and the dielectric layer. In addition, the cost of raw material used in forming the dielectric layer increases due to its increased thickness. Further, variations in the thickness of the dielectric layer can cause changes in the dielectric properties, such as capacitance. Furthermore, variations in the thickness of the dielectric layer can cause post-processing problems, such as metal deposition rate, varying etch rate, metal coverage, and so on, which can ultimately result in a lower yield.
Thus, there is a need in the art for a technique to form MCMs using build-up technology that can overcome the above-described problems.

Semiconductor substrate for build-up packages


A disk 100 has an electronic circuit 10 for executing predetermined signal process and/or an electronic function part having a function of generating, writing or preserving some electronic data and at least one electrical conductive part 20 electrically connected to the electronic circuits and/or electronic function part. The disk 100 is to be set on the turntable 210, clamped by the clamp and driven for rotation for reading or writing data. The clamp has an electrical conductive part formed on locality corresponding to the electrical conductive part 20 of the disk 100.

This application claims benefit of Japanese Patent Application Nos. 2004-004301, 2004-013995 and 2004-027685 filed on Jan. 9, 2004, Jan. 22, 2004 and Feb. 4, 2004, respectively, the contents of which are incorporated by the reference.
The present invention relates to disk drive devices, disk drive systems and disks capable of signal transmission and/or receipt between disk and disk drive device with a simple arrangement.
Optical disks, although made of very inexpensive materials such as polycarbonate or like resins, are capable of recording very great amounts of data quantities and also very advantageous in view of the cost performance. Thus, the optical disks are most promising as future recording medium.
For reading out and writing data from and in an optical disk (data read/write), a disk drive device is used. The disk drive device is arranged such that an optical disk is set on a turntable, clamped by a clamp and driven for rotation by a spindle motor that the disk in this state is irradiated by a laser beam, and that a reflected beam from the disk surface is received and demodulated, thereby reading out the recorded data. Typical examples of such disk drive device arrangement are disclosed in Literatures 1 to 3 (see Japanese Patent-Laid Open Heisei 11-353749, Japanese Patent-Laid Open 2000-100031 and Japanese Patent-Laid Open 2000-100032).
Recently, such optical disks have been proposed that not only a recording area but also an electronic circuit or like electric circuit is formed thereon. However, due to the fact that the optical disk and the disk dive device are operable in a state of being perfectly electrically insulated from each other and also that the optical disk is driven for rotation at a high speed it is not so easy to carry out signal transmission and/or receipt between the electronic circuit formed on the optical disk and an internal circuit formed on the side of the disk drive device.
What utilizes radio signal as signal transmitted and received between the disk side and disk drive side, has been proposed as disk drive device of the pertaining type for driving the optical disk. As an example, the optical disk surface and the disk drive surface are each formed with an antenna for radio signal transmission and/or receipt via these antennas.
It has also been conceived to form each of the optical drive side and the disk drive with a light emitting/receiving circuit for optical signal transmission and/or receipt via these light emitting/receiving circuits.
In a further proposed arrangement, signal transmission and/or receipt between the electronic circuit and the disk drive side is carried out in a state that the disk drive is held stationary (see Literature 4: U.S. Pat. No. 5,119,353).
As shown above, in the prior art the transmission and/or receipt of signals between the electronic circuit formed on the disk surface and the internal circuit in the disk drive device, is carried out as the radio signal transmission and/or receipt via the antennas formed on the disk surface and the disk drive side, respectively. However, such antennas should be formed with shape parameters fitted for the radio signal frequency, and also the formation of the antenna on the disk surface requires a highly accurate etching (forming) technique. Furthermore, it is necessary to form a frequency converter circuit for frequency conversion to and from the radio frequency. These facts are significant problems for the optical disk, the low cost of which is greatly beneficial. Furthermore, the radio frequency transmission and/or receipt characteristic is easily influenced or deteriorated by metal materials close to the transmission/reception means such as the reflected metal layer in the disk.
In the case of the arrangement adapted for optical signal transmission and/or receipt via the light emitting/receiving circuits formed on the optical disk side and the disk drive device side, respectively, it is necessary to form an optical/electric signal converter circuit on each disk, which is a significant problem likewise for the optical disk featuring utmost preference in cost.
In the case of carrying out the signal transmission and/or receipt between the electronic circuit and the internal circuit on the disk drive device side in the state that the disk drive device is held stationary, the signal transmission and/or receipt between the disk circuit and the disk drive device side can not be obtained while the disk is driven for rotation, and real-time signal processing is impossible.
In the meantime, it is presumed to form not only a single but plurality of electronic circuits on the disk. In the prior art, it is impossible to cope with transmission and/or receipt of signals with respect to the disk drive device under such presumption. Foe example, it is very difficult to supply the electric power to the electric circuit on the disk.

Disk drive device, disk drive system and disk


The present invention relates to oral care compositions comprising Liquid Polyoxyalkylene Compounds as Solubilizers/Gelling Agents.

Polyoxyalkylene block copolymers have been used as non ionic surface active agents for many years. In general they have both hydrophobic and hydrophilic blocks which in combination give these compounds their surfactant properties. These products have been described before in numerous references. For example, Lunsted was the first to describe them in U.S. Pat. No. 2,674,619. Heterization of both the hydrophobic and hydrophilic blocks of nonionic block copolymer surfactants is well known in the art of surfactant chemistry. Lunsted, et.al. in U.S. Pat. No. 3,022,335, discloses surface active polyoxyalkylene compounds having plurality of heteric polyoxypropylene-polyoxyethylene chains, more specifically a heteric oxyalkylene-oxyethylene chain or chains as a hydrophobic nucleus to which oxyethylene chains were attached as the hydrophilic block. Patton, et. al., in U.S. Pat. No. 3,101,374, discloses surface active mixtures of polyoxyalkylene compounds composed of hydrophobic oxyalkylene chains or blocks which are condensed with a plurality of heteric oxyethylene-oxyalkylene chains. Patton also discloses that the resultant products were liquefied by addition of alkylene oxide, in a large enough percentage, to the heteric hydrophilic block. Otten & Schoene in U.S. Pat. No. 5,187,191, disclose an aqueous pesticide dispersion composed of a water insoluble pesticide, a liquid polyoxyalkylene compound having a plurality of heteric polyoxypropylene polyoxyethylene chains and water.
The aqueous gel properties and uses of solid polyalkylene/polyoxyethylene block polymers are well documented. U.S. Pat. No. 3,639,574 (Schmolka) assigned to BASF discloses polyoxyethylene/polyoxypropylene block copolymers as gelling agents for hydrogen peroxide compositions. In Lutz, U.S. Pat. No. 4,011,309, dentifrice compositions are disclosed which are composed of aqueous gel formulations that incorporate polyoxyethylene-polyoxypropylene block copolymers as the main gel component. Schmolka, in U.S. Pat. No. 4,343,785, discloses an aqueous gel dentifrice comprising polyoxybutylene-polyoxyethylene block copolymers. Schmolka also discloses mouthwash compositions which utilize polyoxybutylene-polyoxypropylene block copolymers as solubilizers.
Further, U.S. Pat. No. 3,740,421 (Schmolka) assigned to BASF discloses aqueous gels prepared using a triblock copolymer of polyoxyethylene/polyoxypropylene/polyoxyethylene suitable for pharmaceutical and personal care compositions at approximately 20-25% by weight. U.S. Pat. No. 4,465,663 (Schmolka) assigned to BASF discloses polyoxybutylene/polyoxyethylene block copolymers as gelling agents for aqueous gels useful in personal care and pharmaceutical applications. Some of these compounds are sold by the BASF Corporation under the PLURONIC.RTM. tradename.
Additionally, U.S. Pat. No. 4,272,394 and U.S. Pat. No. 4,411,810 disclose the use of polyoxyalkylene block copolymers in machine dishwashing applications. U.S. Pat. No. 4,925,988 discloses a nonionic surfactant employing a specific combination of alkanol, ethylene oxide and propylene oxide useful in an automatic dishwashing application. U.S. Pat. No. 5,374,368 describes the use of liquid EO/PO/EO triblock co-polymers (PLURONIC.RTM. L 31 and L 35 surfactants) in stable hydrogen peroxide releasing dental care compositions at levels of 55-90% by weight of the dental care composition. U.S. Pat. No. 3,867,533 discloses aqueous gel compositions containing solid EO/PO/EO triblock copolymers, having a molecular weight of 6,450-20,000 useful at levels of approximately 20% by weight. Said compositions are useful in preparing cosmetic formulations. U.S. Pat. No. 5,035,880 discloses a stable dentifrice compositions containing a cetylpyridinium bactericide and EO/PO/EO solid triblock copolymers (PLURONIC.RTM. F 127 surfactant), and polyethylene glycol at levels of 15-80% by weight. U.S. Pat. No. 4,476,107 discloses a mouthwash containing EO/BO (butylene oxide)/EO triblock copolymers at levels of 0.5-5.0% by weight. U.S. Pat. No. 5,057,307 discloses oral hygiene gels containing non-ionic surfactants, coating substances; and viscosifiers. Said non-ionic surfactants are PLURONIC.RTM. F 108 and F 127 surfactants available from BASF Corporation, Mt. Olive, N.J. U.S. Pat. No. 5,256,396 discloses a topical composition comprising an EO/PO/EO solid triblock copolymer (PLURONIC.RTM. F 127 surfactant) used at a level of more than 10% to about 17% by weight. EPO-546-627A discloses mouthwash compositions comprising solid EO/PO/EO triblock copolymers such as PLURONIC.RTM. L 108, F 88 surfactants at levels of 0.5-3% by weight. U.S. Pat. No. 5,073,368 discloses mouthwashes containing solid EO/PO/EO triblock copolymers such as PLURONIC.RTM. F 87 surfactant at levels of 0.1-3% by weight. WO 93/13750 discloses an ocular cleansing composition comprising solid PLURONIC.RTM. F 87 and paste PLURONIC.RTM. P 85 EO/PO/EO triblock copolymers. PLURONIC.RTM. P 85 surfactant is 4-9% by weight of the cleansing composition, PLURONIC.RTM. F 87 surfactant is 0.5-2% by weight of the cleansing composition. U.S. Pat. No. 5,096,698 discloses a dental creme composition containing a non-ionic triblock liquid EO/PO/EO copolymer or a solid triblock EO/PO/EO copolymer at levels of 0.1-5% by weight. Said copolymers help to prevent phase separation. PLURONIC.RTM. F 108 surfactant (solid) is most preferred, followed by PLURONIC.RTM. F 87, PLURONIC.RTM. F 127, and PLURONIC.RTM. L 72 surfactants. U.S. Pat. No. 4,272,394 discloses novel, low-foaming nonionic surfactant for machine dishwashing compositions. U.S. Pat. No. 4,411,810 discloses a low foaming, low cloud point, nonionic surfactant for machine dishwashing compositions. Finally, JP 47-48366 B4 discloses a process for producing tasteless, liquid, heteric polyoxyalkylene compounds of molecular weight 1000 or higher. U.S. Pat. No. 5,187,191 discloses polyoxyalkylene block copolymers in agricultural formulations. U.S. Pat. No. 5,496,542, U.S. Pat. No. 5,374,368, and U.S. Pat. No. 5,424,060 disclose the use of a polyoxyalkylene compound for formulating a stable percarbonate formulation as well as a dentifrice composition.
Clearly, it is known to those ordinarily skilled in the art that solid block copolymers of ethylene oxide and propylene oxide are useful in aqueous dentifrice compositions. However, a typical disadvantage with the solid block copolymers is their physical form. Triblock copolymers of ethylene oxide and propylene oxide, wherein the ethylene oxide content in the copolymer is over 70%, are typically solids above a MW of 3000. Solid, triblock copolymers of ethylene oxide and propylene oxide can pose handling problems during the manufacture of aqueous dentifrice compositions. Such difficulties typically arise due to their high melting points. In many cases, the solid triblock copolymers have to be converted to their molten state during processing.
The Applicants have surprisingly discovered that when the solid triblock copolymers are rendered liquid via a carefully controlled addition of a heteric mixture of ethylene oxide and propylene oxide to the hydrophobic propyleneoxide block, the resulting product essentially retains the properties of the solid block copolymer and has the benefit of ease of handling in formulating personal care formulations. Specifically, the Applicants' invention overcomes the problems in the art by preparing a liquid copolymer useful in aqueous oral care compositions while essentially retaining the properties of the solid block copolymer. Thus the liquid copolymer of the invention affords ready solubility in aqueous oral care compositions, increased ease of handling and pumping, and utility as gelling or solubilizing agents for such compositions.
Additionally, the references listed hereinabove describe methods of preparation for many different polyoxyalkylene polyether surfactants. However, an undesirably broad distribution of molecular weights is obtained both in the hydrophobe and hydrophile portion of the polymer. The broad distribution of molecular weight products, which result from the anionic living polymerization, may be narrowed to some extent by reduction of a side reaction which develops during propylene oxide additions. Some of the side reactions may result in terminal unsaturation. Cuscurida in U.S. Pat. No. 3,393,243, discloses a method for preparation of propylene oxide based polyether polyols with reduced content of terminal unsaturation by using CsOH as a catalyst. Ott in U.S. Pat. No. 4,764,567, discloses a method of preparation for narrow molecular weight distribution products by using CsOH during the ethylene oxide addition. Finally, Otten in U.S. Pat. No. 4,902,834, discloses an improved process for the preparation of capped polyoxyalkylene block polyethers using CsOH.
Further, the Applicants have also discovered that the use of cesium hydroxide as a catalyst in the synthesis of the liquid polyoxyalkylene block copolymers of the present invention resulted in further improvement in the gel characteristics of the liquid polymer relative to a potassium hydroxide catalyzed material.

Oral care compositions comprising liquid polyoxyalkylene compounds as solubilizers/gelling agents


Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer having a contact hole therein, on a face of a semiconductor substrate and then forming a polysilicon contact plug in the contact hole. A first capacitor electrode is then formed in electrical contact with the polysilicon contact plug. The first capacitor electrode may be formed by etching a composite of a diffusion barrier metal layer containing a nitride material (or silicide material) and a first electrically conductive layer. Alternatively, the first capacitor electrode may be formed by etching the diffusion barrier metal layer without the first electrically conductive layer thereon. The diffusion barrier metal layer inhibits parasitic migration of silicon from the polysilicon plug to the first electrically conductive layer. A protective layer of a preferred material is then electroplated onto an upper surface and on sidewalls of the first capacitor electrode. The protective layer is designed to protect exposed sidewall portions of the barrier metal layer from being oxidized during subsequent process steps. Next, a capacitor dielectric layer is formed on the protective layer, opposite the upper surface of the first capacitor electrode. The capacitor dielectric layer is preferably formed of a high dielectric material such as a material selected from the group consisting of Ta.sub.2 O.sub.5, SrTiO.sub.3, BaTiO.sub.3, SrTiO.sub.3, (Ba, Sr)TiO.sub.3, Pb(Zr, Ti)O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT), (Pb,La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12.

It is generally desirable to make memory cells as small as possible so that more memory cells can be integrated into each chip. Higher capacitance storage capacitors also provide better definition when reading the memory cell, lower soft error rate, and enable lower voltage operation. Therefore, if memory cells can be made smaller and with higher capacitance, semiconductor memory devices can become more highly integrated.
Capacitors having three-dimensional structures have been proposed in an attempt to increase cell capacitance. These types of capacitors usually have a lower electrodes in the shape of a fin, a box, or a cylinder. However, the manufacturing processes for forming capacitors with three-dimensional electrode structures are complicated and defects may be easily generated during the manufacturing processes. Accordingly, research into the use of high dielectric materials for increasing the capacitance of capacitors is actively being conducted to avoid the need for forming capacitor electrodes having three-dimensional structure. However, when polysilicon doped with impurities is used as the lower electrode of a capacitor, the high dielectric layer may become susceptible to reaction with the polysilicon and this reaction may cause the formation of a parasitic dielectric layer having a relatively low dielectric constant at an interface between the lower electrode and the high dielectric layer. Accordingly, new electrodes which are less susceptible to reaction with high dielectric layers are required.
FIGS. 1 through 3 are sectional views illustrating a conventional method for manufacturing a capacitor of a semiconductor device. FIG. 1 shows the step of forming an interlayer dielectric layer pattern 20, a contact plug 30, a diffusion barrier layer 40 and a lower conductive layer 50. First, the interlayer dielectric layer pattern 20 having a contact hole therein for exposing a predetermined region of a semiconductor substrate 10, is formed on the semiconductor substrate 10. Then, a polysilicon layer is formed on the interlayer dielectric layer pattern 20 to fill the contact hole. The polysilicon layer is etched-back to expose the interlayer dielectric layer pattern 20, thereby forming the contact plug 30 filling the contact hole. Next, a diffusion barrier layer 40 and a lower conductive layer 50 are sequentially formed on the resultant structure. At this time, the diffusion barrier layer 40 is formed of titanium nitride, and the lower conductive layer 50 is formed of platinum (Pt) to inhibit the likelihood of reaction with a subsequently formed dielectric layer 60 (see FIG. 3). In particular, the diffusion barrier layer 40 is formed in order to prevent reaction between the contact plug 30 and the lower conductive layer 50 during the performance of a subsequent heat treatment process for forming the dielectric layer 60.
FIG. 2 shows the step of forming a diffusion barrier pattern 40a and a lower conductive layer pattern 50a. In detail, the lower conductive layer 50 and the diffusion barrier layer 40 are patterned to expose the interlayer dielectric layer pattern 20, and accordingly the diffusion barrier pattern 40a and the lower conductive layer pattern 50a which are sequentially stacked on the contact plug layer 30, are formed. This sequence of steps completes the lower electrode of the capacitor which consists of the contact plug layer 30, the diffusion barrier pattern 40a and the lower conductive layer pattern 50a.
FIG. 3 shows the step of completing the capacitor by forming a dielectric layer 60 and an upper conductive layer 70. In detail, the dielectric layer 60 (which may be formed of Pb(Zr, Ti)O.sub.3) and the upper conductive layer 70 are sequentially formed over the completed lower electrode, to complete the capacitor. At this time, the dielectric layer 60 is formed in an oxygen atmosphere in order to prevent oxygen deficiency in the dielectric layer 60. If there is no diffusion barrier pattern 40a, during the heat treatment process for forming the dielectric layer 60 the contact plug 30 and the lower conductive layer pattern 50a may react with each other to form a platinum silicide layer. The dielectric layer 60 and the silicon in the platinum silicide layer may then react with each other to form a parasitic dielectric layer (having a low dielectric constant) between the dielectric layer 60 and the platinum silicide layer. Accordingly, the total capacitance may be reduced. Therefore, the diffusion barrier pattern 40a is typically necessary for inhibiting any interface reaction between the contact plug 30 and the lower conductive layer pattern 50a. However, during formation of the dielectric layer 60, the sidewalls of the diffusion barrier pattern 40a are exposed to an atmosphere of oxygen and may become oxidized. Accordingly, the resistance of the diffusion barrier pattern 40a may be substantially increased.
According to the conventional method for manufacturing a semiconductor device, the diffusion barrier pattern 40a prevents reaction between the contact plug 30 and the lower conductive layer pattern 50a. However, oxidation which may occur during the process of forming the dielectric layer 60 typically increases the electrical resistance of the diffusion barrier pattern 40a. Accordingly, the total resistance of the lower electrode of the capacitor may be greatly increased and therefore the possibility of high speed operation of devices containing the above described storage capacitors may be limited. Also, when the diffusion barrier pattern 40a is oxidized, a dielectric material having a low dielectric constant may be formed in series with the dielectric layer 60 to reduce the total capacitance.

Methods of forming integrated circuit capacitors having protected diffusion barrier metal layers therein