A semiconductor method includes thermally treating at least a portion of a substrate so as to generate a plurality of vacancies in a region at a depth substantially near to a surface of the substrate. The substrate is then quenched so as to substantially maintain the vacancies in the region substantially near to the surface of the substrate.

1. Field of the Invention
The present invention relates generally to methods for forming semiconductor structures, and more particularly to methods for forming field effect transistors (FETs) and epi-substrates.
2. Description of the Related Art
With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets, in order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements. In order to achieve high-speed performance, dimensions of transistors have been shrinking. Salicidation technology has been widely applied in manufacturing transistors in order to reduce resistances of transistor gates and source/drain (S/D) contacts.
FIG. 1 is a schematic cross-sectional view showing a traditional field effect transistor (FET).
Referring to FIG. 1A, a gate oxide layer 110 and a polysilicon gate 120 are sequentially formed over a substrate 100. Spacers 130 are formed on sidewalls of the gate oxide layer 110 and die polysilicon gate 120. Lightly doped drain (LDD) regions 150 and source/drain (S/D) regions 160 are formed within the substrate 100 and adjacent to the gate oxide layer 110. Salicide layers 140 are formed on the polysilicon gate 120 and the S/D regions 160. Due to the salicide layers 140, which include metallic constituents, resistances of the polysilicon gate 120 and the S/D regions 160 are desirably achieved.
As the channel dimension of transistors is reduced, the thickness of the gate oxide layer 110 is also reduced. The thin gate oxide layer 110, however, is vulnerable to a voltage applied to the polysilicon gate 120 and may be damaged by the voltage. In order to mitigate the breakthrough effect of the gate oxide layer 110, a high dielectric constant material layer such as nitride or oxynitride is used such that the thickness of the gate dielectric layer 110 can be increased to sustain the voltage applied the polysilicon gate 120.
Based on the foregoing, improved methods for forming FET structures are desired.

Methods for forming field effect transistors and EPI-substrate

Taiwan Semiconductor Manufacturing Co., Ltd.


The invention relates to wireless Internet access points, and in particular to providing a mobile wireless access point for use with high-speed wireless devices. In particular, the system allows client devices configured for short-range, high-speed wireless Internet access to use said system to access the Internet while in a mobile environment, such as a passenger vehicle.

Telecommunications technology has advanced dramatically in recent history. The era of cost effective mobile data connectivity, "anytime, anywhere" is rapidly approaching. With the growing popularity of the Internet and increasing mobility demands from end users, there has recently been increased interest in wireless public Internet access.
Public Internet access (e.g. Internet Café) has been around for many years. In the last couple of years, a new wireless data technology based on the IEEE 802.11 standard has been gaining momentum. Of particular interest is the deployment of 802.11-based access points—so called "Hotspots"—in public spaces, e.g. coffee shops, hotels, conference centers, and airports. Users with client devices such as laptops and personal digital assistants (PDAs) use an 802.11 network interface card that enables them to connect to the Internet without any physical cables. Once an association is established with the Wireless LAN (WLAN) Access Point (AP) or Hotspot, the user is able to surf the Internet as if they were on a LAN.
The existing Hotspots provide good Internet connectivity. The major challenge with this type of wireless solution is coverage. The 802.11 standard makes use of an unlicensed frequency spectrum and is therefore limited to low power transmissions. As a result, a typical Hotspot has a range of no more than 150 feet indoors and 1000 feet outdoors under ideal conditions. Even with large companies such as T-Mobile planning to install thousands of these Hotspots in the coming years, it will be very difficult to achieve sufficient coverage throughout a city to satisfy a large population of mobile workers.
To address the need for wide area wireless coverage, many cellular operators have been deploying new generation (known as 2.5G or 3G) wireless data networks. For example, the PCS Vision network from Sprint PCS is already providing substantially improved performance over previous generations of wireless technology. With speeds averaging 50-70 kbps and peaking at 144 kbps the PCS Vision network is much slower than its 802.11 counterpart but has the advantage of a large coverage area and support for vehicular mobility (e.g. 0-300 km/h). 3G networks provide a service that is closer to the "anytime, anywhere" objective.
There are drawbacks with 3G networks, chief among them being cost. 3G interface cards are expensive and so are the associated service plans. There are also several competing and evolving standards (1xRTT, 1xEV-DO, 1xEV-DV, GPRS, EDGE, etc.). A given interface card typically supports only one of these standards, the consumer is faced with a difficult decision, compounded by the knowledge he will likely have to upgrade to yet another expensive option within 18-36 months. High cost, confusing choices and poor performance relative to home Internet services such as DSL and cable modems all inhibit the wide acceptance of 3G.
Today, ground transportation is a part of nearly everyone's life. Be it airport transfers, customer visits, or daily commuting, more and more of the workforce is becoming mobile. Mobile workers are continually looking for cost effective solutions that allow them to stay in touch with their customers, co-workers, suppliers and shareholders electronically using standard computer equipment while "stuck" in transit using public transportation including limousines, taxis, buses, ferries or trains.
It is an object of this invention to provide a mobile wireless hotspot that allows client devices equipped with short-range wireless Internet capability (e.g. 802.11) to access the Internet from a mobile vehicle through a long-range wireless Internet system (e.g. a 3G network).


An image processing apparatus suitable for three-dimensional high speed image processing can be realized by improving the memory address control and the access method, that is, by improving the data transfer speed between the image memory and the other unit. The image processing apparatus comprises the pixel forming unit (1) for forming frame data for each pixel; an image memory (2) constructed by a plurality of banks (3, 4) to which row addresses are inputted through a row address input system (6) and column addresses are inputted through a column address input system (7); and the DRAM controller (5) for controlling the image memory (2). The DRAM controller (5) controls the image memory (2) in such a way that the screen is divided into a plurality of rectangular regions so that the frame data of one rectangular region can be stored in one page of the image memory (2); the frame data in the adjoining rectangular regions are allowed to correspond to the two different banks (3, 4) of the macro cell; and the column addresses can be generated continuously when any of the banks is being accessed, so that any addresses can be accessed continuously in the same page. Further, the DRAM controller (5) controls the address sequence predicting circuit (8) in such a way that the banks to be accessed in the future can be accessed immediately after the bank to be accessed is switched.

1. Field of the Invention
The present invention relates to an image processing apparatus, and more specifically to a construction of an image memory and its control system for forming picture at high speed on the basis of three-dimensional image data.
2. Description of the Prior Art
In the three-dimensional image processing apparatus, frame data (i.e., color data at each pixel) and Z value data (i.e., depth data) are generated by projecting an apex of a solid body defined in a three-dimensional space onto a screen space and by rasterizing image data on the basis of the projected apex data.
Further, these data are stored temporarily in an image memory during the arithmetic process of the image processing apparatus. In this case, the frame data and the Z value data are both stored in a prepared memory.
Now, as a method of storing the frame data, there are two methods of line buffer method and frame buffer method. In the case of the three-dimensional image processing, however, the frame buffer method is usually adopted because of its advantage that the access time is long as compared with when the line buffer method is adopted. Further, in the case of this frame buffer method, two buffers are often used. In this double buffer method, two frame buffers are prepared for storing data for one picture; that is, one frame buffer is used to display image data and the other frame buffer is used to write the same image data. When used, these two frame buffer memories are switched in accordance with the refresh rate of the picture.
In the three-dimensional image processing, in order to improve the polygon rate, that is, to increase the number of the polygons displayable in a unit time, it is necessary to increase the data transfer speed to a memory. One of the methods considered to improve the data transfer speed is to widen the bit width of the memory data bus.
When one region on a screen is allocated to a memory column, since the band width can be increased, the region to be accessed once can be widened, so that the data transfer speed can be increased and thereby the pixel rate can be improved.
In this case, however, in the vicinity of the polygon edges, there exists the case where an area other than the polygon region is included in the access region. In this case, there exists a problem in that a part of the data bus is used wastefully. To reduce this wasteful use of the data bus, it is necessary to change the region to be accessed into a flexible access region.
Conventionally, a DRAM having a burst transfer mode has been sometimes used as an image memory. When this DRAM is used in interleave method, it is possible to enable a continuous access, on condition that the banks are switched whenever a page to be accessed is switched, by RAS-activating the bank to be next accessed, simultaneously when the columns arranged in a predetermined direction in the memory are accessed continuously by burst transfer. In the conventional method, however, since the addresses for both the row system and the column system are inputted through only a single system, when non-continuous columns are accessed, there exists a problem in that the succeeding bank cannot be activated. In other words, in the case where the screen is divided into a plurality of regions and further the divided region is allocated to the column in one-to-one correspondence, although the continuous access in one predetermined direction can be made on a screen conveniently, when the continuous access is made in the other direction, the access in the other direction has inevitably an overhead.
In the conventional image processing apparatus which can execute the Z buffering, the frame data and the Z value data for each pixel are usually stored in each dedicated macro cell. In this method, however, the memory capacity used for the frame data or the Z value data is limited by the respective macro cell capacity. For instance, when one of both needs a large capacity but the other of both needs a relatively small capacity, although it is possible to use the limited memory capacity effectively by using the unnecessary and remaining memory capacity as the other memory capacity, since the memory is used dedicatedly, the above-mentioned method of using the memory capacity is strictly limited.
As described above, in the prior art image processing apparatus, since the data transfer efficiency is low in the region rear the polygon edges and further since the address input is made for each row system and each column system, there exists a problem in that the memory availability is low, because the overhead access cannot be eliminated and further the frame data and Z value data are both allocated to each dedicated memory.

Image processing apparatus having improved memory access for high speed 3-dimensional image processing


A method for forming a dual gate of a semiconductor device includes the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and second gate patterns that include the semiconductor layer and the low resistance metal layer on the substrate corresponding to the first and second wells, forming sidewall spacers at sides of the first and second gate patterns, and exposing the first well and the first gate pattern, implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern to form a first source and a first drain, exposing the second well and the second gate pattern, implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern to form a second source and a second drain; and diffusing the impurity ions from the low resistance metal layer into the semiconductor layer to form first and second gate electrodes.

This application claims priority to Korean Patent Application No. 570/1999, filed on Jan. 12, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a dual gate of a semiconductor device, which simplifies process steps and improves reliability of the semiconductor device.
2. Background of the Related Art
Generally, in fabrication of MOS devices, a single poly gate structure requires a buried PMOS transistor, which increases a short channel effect. In this case, it is difficult to fabricate a device having a gate length of 0.25 xcexcm or less. A dual gate structure has been proposed, in which a P-poly gate is used in a PMOS transistor and an N-poly gate is used in an NMOS transistor. FIGS. 1A to 1F show cross-sectional views iliustrating a related art method for forming a dual gate of a semiconductor device.
As shown in FIG. 1A, an isolation region 12 is partially formed in a semiconductor substrate 11 by a local oxidation of silicon (LOCOS) process or a trench isolation process. Thereafter, a P well region 13 and an N well region 14 are selectively formed in the semiconductor substrate 11 by impurity ion implantation.
The N well region 14 is masked during the formation of the P well region 13, while the P well region 13 is masked during formation of the N well region 14. (These steps are not illustrated in the figures).
As shown in FIG. 1B, a gate insulating film 15 is formed on the semiconductor substrate 11. Subsequently, an undoped polysilicon layer 16 is deposited on the gate insulating film 15. A first photoresist 17 is then selectively deposited on the polysilicon layer 16. The first photoresist 17 is then patterned by exposure and developing processes to mask the polysilicon layer 16 of the N well region 14. N-type impurity ions are then implanted into the exposed polysilicon layer 16 of the P well region 13.
As shown in FIG. 1C, the first photoresist 17 is removed and then a second photoresist 17a is deposited on an entire surface of the semiconductor substrate including the polysilicon layer 16, into which the N-type impurity ions were implanted. The second photoresist 17a is patterned by an exposure and developing processes to mask the polysilicon layer 16 (into which the N-type impurity ions are implanted) of the P well region 13. P-type impurity ions are implanted into the exposed polysilicon layer 16. The P-type the impurity ion implantation may also be performed prior to the N-type impurity ion implantation.
As shown in FIG. 1D, the second photoresist 17a is removed, and a tungsten silicide (WSi2) or a tungsten (W) layer 18 is formed on the polysilicon layer 16. Subsequently, a third photoresist is deposited on the tungsten suicide layer 18. The third photoresist is patterned by exposure and developing processes to form a photoresist pattern 19. As shown in FIG. 1D, the photoresist pattern 19 is formed on the tungsten silicide layer 18.
As shown in FIG. 1E, the tungsten silicide layer 18, the polysilicon layer 16, and the gate insulating film 15 are selectively removed by an etching process using the photoresist pattern 19 as a mask, to form a first gate electrode 20 and a second gate electrode 20a. The first gate electrode 20 is for an NMOS transistor and the second gate electrode 20a is for a PMOS transistor.
As shown in FIG. 1F, an oxide film or a nitride film is deposited on the entire surface of the semiconductor substrate including the gate electrodes 20 and 20a, and then etched back to form sidewall spacers 21 at both sides of the gate electrodes 20 and 20a.
Thereafter, the N well region 14 is masked, and then impurity ions are implanted into the P well region 13 at both sides of the first gate electrode 20 to form first source/drain impurity ion diffused regions 22.
Subsequently, the P well region 13 is masked, and then impurity ions are implanted into the N well region 14 at both sides of the second gate electrode 20a to form second source/drain impurity ion diffused regions 22a.
The second source/drain impurity ion diffused region 22a may also be formed Prior to the first source/drain impurity ion diffused region 22.
The related art method for forming a dual gate of a semiconductor device has several problems.
First, ion implantation is performed twice in order to dope impurity ions into the undoped polysilicon layer 16. Also, ion implantation is performed twice when forming source/drain impurity ion diffused regions 22, 22a corresponding to each of the transistors. This complicates process steps and increases the number of masks, thereby increasing cost.
Second, during ion implantation into the polysilicon layer 16, the impurity ions pass through the polysilicon layer 16 if the polysilicon layer 16 is thin. This damages the gate insulating film 15, thereby deteriorating its insulating characteristics.
Moreover, during boron ion implantation when forming a gate electrode for the PMOS transistor, the boron ions act to vary the threshold voltage of the device because its fast diffusion speed affects a channel region of the FET.
Third, since the tungsten silicide layer 18 formed on the polysilicon layer 16 has resistivity of about 100 xcexcxcexa9cm, it is impossible to reduce sheet resistance to 10 xcexa9/sq or less, even though the polysilicon layer 16 is deposited to a thickness at 1000 xc3x85 or more.
Fourth, if a tungsten layer having resistivity lower than that of the tungsten silicide layer 18 is deposited on the polysilicon layer 16 to reduce resistance, titanium nitride (TiN) film or WN (tungsten nitride) film must additionally be formed to avoid reaction with silicon. This complicates process steps.
Fifth, a reoxidation process is required to restore damage caused to the gate insulating film 15 during the etching process for the formation of the gate electrode. However, selective reoxidation is required because the tungsten is likely to react with ambient O2. Therefore, selective oxidation should exactly satisfy possible oxidation conditions, such as a ratio of H2/O2, and oxidation temperature. In this case, there is a problem in that redundancy of the selective oxidation is low.
Finally, if a cell region and a logic region are formed in a single chip, the logic region requires a salicide process so that the logic region has a gate electrode material different from that of the cell region.
Accordingly, the present invention is directed to a method for forming a dual gate of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a dual gate of a semiconductor device, which improves reliability of the device and simplifies process steps by forming the same gate electrode material in both a cell region and a logic region.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in accordance with a first aspect of the present invention there is provided a method for forming a dual gate of a semiconductor device including the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and second gate patterns that include the semiconductor layer and the low resistance metal layer on the substrate corresponding to the first and second wells, forming sidewall spacers at sides of the first and second gate patterns, and exposing the first well and the first gate pattern, implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern to form a first source and a first drain, exposing the second well and the second gate pattern, implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern to form a second source and a second drain, and diffusing the impurity ions from the low resistance metal layer into the semiconductor layer to form first and second gate electrodes.
In another aspect of the present invention, there is provided a method for forming a dual gate of a semiconductor device, including the steps of selectively forming an isolation region on a semiconductor substrate, forming a P well region and an N well region in the semiconductor substrate, sequentially forming a gate insulating film, an undoped polysilicon layer, and a cobalt silicide layer on an entire surface of the semiconductor substrate, forming first and second gate patterns from the undoped polysilicon layer and the cobalt silicide layer on the substrate at the P well region and the N well region, respectively, forming sidewall spacers at sides of each of the first and second gate patterns and exposing the P well region including the first gate pattern, implanting N-type impurity ions into an upper portion of the first gate pattern and the P well region to form a first source and a first drain, exposing the N well region and the second gate pattern, implanting P-type impurity ions into an upper portion of the second gate pattern and the N well region to form a second source and a second drain, and doping the undoped polysilicon layer of the first and second gate patterns by diffusing the P-type and N-type impurity ions implanted into upper portions of the respective gate patterns to form first and second gate electrodes each including the cobalt silicide layer and the doped polysilicon layer, and at the same time forming source and drain impurity regions in the semiconductor substrate at both sides of the respective gate electrodes.
In another aspect of the present invention, in forming a gate electrode of embedded DRAM in which DRAM and a logic circuit are on a single chip, there is provided a method for forming a dual gate of a semiconductor device including the steps of dividing a semiconductor substrate into a DRAM region and a logic circuit region, and forming a P well region and an N well region in the DRAM region, sequentially forming a gate insulating film, an undoped polysilicon layer, and a low resistance metal layer on the semiconductor substrate, forming first and second gate patterns in the DRAM region and a third gate pattern in the logic circuit region by etching, forming sidewall spacers at sides of each of the first, second and third gate patterns, masking the N well region and second gate electrode pattern, implanting N-type impurity ions into a surface of the semiconductor substrate, exposing the N well region and second gate electrode pattern and then implanting P-type impurity ions into the surface of the semiconductor substrate, doping the undoped polysilicon layer of the first, second and third gate patterns by impurity ion diffusion, and at the same time forming source and drain impurity regions in the semiconductor substrate at sides of the gate patterns, and masking the DRAM region, and forming a second metal layer of the same material as the low resistance metal layer over the third gate pattern and on the substrate at sides of the third gate pattern.
In another aspect of the present invention, there is provided a method for forming a dual gate of a semiconductor device including the steps of forming a gate insulating film on a substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming a semiconductor layer on the gate insulating film, forming a metal layer on the semiconductor layer, partially removing the gate insulating film, the semiconductor layer and the metal layer to form first and second gate patterns over the first and second wells, respectively, forming sidewall spacers at sides of the first and second gate patterns, exposing the first well and the first gate pattern, forming a first source and a first drain by implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern, exposing the second well and the second gate pattern, forming a second source and a second drain by implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern, and diffusing the impurity ions from the metal layer into the semiconductor layer to form first and second gate electrodes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Method for forming dual gate in DRAM embedded with a logic circuit


A system for interrogating sensors in a fiber optical sensor network includes groups of sensors. The sensors in one group operate at different wavelengths, and the sensors of other groups may have overlapping wavelengths. A light source generates a broadband light signal, input and output means for guides the broadband light to the fiber optical sensor network for illuminating the sensors and for coupling the light signal coming from the sensors of the fiber optical sensor network to the detection system, and a detection system detects the received light signal, during a detection integration time. The system is arranged for selecting pre-dominantly the received light coming from the different sensors of a selected group of sensors using a code-division multiplexing technique and simultaneously detecting sensors of the selected group of sensors using a wavelength-division multiplexing technique.

In present days, networks of optical sensors gain a lot of attention. In terms of "smart structures", where high numbers of sensors are required to monitor the condition of a material or system, optical fiber sensor networks are an essential part of the system. By means of these networks that are small and light, and independent of electro-magnetic interference, it is possible to implement sensors measuring strain, temperature or other parameters into a setup. To achieve a high spatial measurement resolution, the density of sensors needs to be as high as possible, preferably in a single optical fiber. In the following example, optical sensors are referred to as Fiber Bragg Gratings (FBGs). Addressing each individual FBG requires special multiplexing techniques.
State of the art considering interrogation of optical fiber sensor networks are time-division multiplexing (TDM), wavelength-division multiplexing (WDM), optical frequency domain reflectometry (OFDR) or code-division multiplexing (CDM). Many of them are methods used in communication standards.
Time-division multiplexing (TDM) makes use of the propagation speed of light in a fiber. Each FBG is located at a different location in an optical network wherein each location results in a different time delay due to different propagation lengths. A light source emits short pulses that travel through the network and a part of the wavelength spectrum of these pulses are subsequently reflected by each sensor. Thus, the density of sensors is limited to the pulse length as not more than one sensor can be radiated on the same time. The pulse length itself is limited to the required power of light to obtain a sufficient signal to noise ratio (SNR). The shorter the pulse, the lower the transmitted optical power. At the interrogator, a series of pulses arrives where each pulse contains the wavelength information of a single FBG. Hence, all FBGs in a network have a distinct time slot. Since the interrogator has to wait for a full pulse round trip time before launching a new pulse the major disadvantages of TDM are the measurement time and the low energy received by the interrogating equipment.
Wavelength-division multiplexing (WDM) is currently the standard for monitoring FBG arrays. Each sensor has a distinct spectral slot wherein it can operate. As FBGs change their reflected wavelength when strain or temperature is applied, the wavelength slot needs to suit their operating wavelength region because overlapping spectra are not allowed. This limits the number of sensors in an array drastically and depends on the spectral width of the light source and the interrogator, e.g. a spectrometer. However, the spatial distance between the FBGs is not limited by the interrogator, it only depends on the fabrication technology of the FBGs. For instance, Draw Tower Gratings (DTG®s) may provide a very high sensor density, whereby the spatial distance between FBGs can be as small as 1 cm or even lower.
Optical frequency domain reflectometry (OFDR) is a method to interrogate numerous sensors in an optical fiber. It is based on the interferometry of light waves. This requires an additional reference reflector. The location of an optical fiber sensor is determined by a different optical path length compared to the reference. This method has a good spatial resolution but is limited to short fiber lengths of around 10 to 70 m.
Code-division multiplexing (CDM) is based on orthogonal codes modulated on incident light (resulting into a sequence of pulses, called chips) and at the receiving site. Similar as with TDM, each FBG has a different length of optical path and therefore its reflected light reaches the interrogator on different time slots. Each FBG can have the same operating wavelength. The reflected light is modulated using a second modulator and a spectrometer collects the throughput of optical power. Mathematically, an autocorrelation of the code is performed when using the same code on both modulators but with a differential time delay. Orthogonal codes have an autocorrelation that contains a peak for no time shift and zeros for all others. The time shift is adjusted at the second modulator so that the time shift corresponds to the reflected light of a distinct FBG. All other reflections are cancelled out by the correlation of an orthogonal code. The advantage over TDM, where only one pulse per roundtrip is received, is that much more optical power is collected which can be adjusted by the length of the code. This leads to a better SNR that is required for proper measurements. Nevertheless, a synchronization on each individual FBG is required like with TDM. Moreover, as in TDM, the minimum distance between the individual FBGs is linked to the pulse width.
Consequently, there is still room for improvement for obtaining fast and efficient multiplexing techniques for reading out optical fiber sensor networks.

Interrogation of optical fiber sensor networks


Multilayered polyamide composite articles comprising at least three layers that comprise aliphatic and semi-aromatic polyamides and that is better able to retain its mechanical properties at high temperatures and over long times are disclosed. Layers comprising aliphatic polyamides may optionally contain oxidation stabilizers. The articles may be in the form of tubes incorporated into a heat exchanger. Processes for their preparation are also provided.

Polyamides are attractive materials to use in many demanding applications because of their mechanical properties and chemical resistance. Many of these applications involve use at high temperatures. For example, components used in the automotive engine compartment such as ducts, fans and fan shrouds, manifolds, tubes, etc. require operation at high temperatures. There is ample evidence in the patent literature directed to the use of plastic tubes, panels, and other structures for fabrication of heat exchangers that can operate at high temperatures. Heat exchangers can take a variety of forms; one such construction takes the form of a plurality of tubes arranged in a parallel fashion and secured at their free ends, such that fluid can flow through channels formed therein. In all of these applications, it is desirable that the structures and components retain their mechanical properties such as stiffness, strength and creep resistance at high temperatures.
The change in properties of a polymer with temperature is governed by its glass transition temperature. This is a temperature characteristic of a polymer's molecular architecture, when molecules undergo a transition from a glassy state to a rubbery state. The mechanical properties such as stiffness and strength exhibited by a polymer in the glassy state are generally significantly higher than those in the rubbery state.
Another issue with the use of plastic components at high temperatures is that the rate of oxidative degradation is higher, leading to loss of mechanical properties at a faster rate. During oxidative degradation, oxygen diffuses into the exposed polymer surface, and reacts with the polymer molecules. The degradation is thus initiated, and is more concentrated near the surface of an exposed part, and causes surface embrittlement. Surface embrittlement has a severe effect on the physical properties of the whole part since external bending and flexing loads typically give rise to high stress concentrations at the surface.
A common approach to retarding oxidative degradation of polymers is to use anti-oxidation additives. These are used at low levels, and often tailored for use in a particular polymer. They are normally dispersed throughout the polymer matrix, and a uniform distribution is used to provide overall stability.
The oxidation stabilizers used in polyamides generally fall into three groups: (i) organic stabilizers based on aromatic amines, (ii) organic stabilizers based on hindered phenols sometimes in combination with phosphorous based compounds, and (iii) inorganic stabilizers based on copper and halogen compounds. The organic stabilizers are often not suitable for incorporation into polyamides that need to be processed at temperatures close to 300° C. or higher, as they tend to volatilize or decompose. Copper based inorganic stabilizers are also not suitable because they lead to degradative reactions at these high temperatures. This is especially true in processes such as extrusion, blow molding, casting, film blowing etc. that involve exposure of the polymer melt to atmospheric conditions.
U.S. Pat. No. 5,258,213 describes a multilayered thermoplastic composite comprising a polyamide layer, a polyester layer, and an adhesion promoter. This composite does not have any particular thermal or oxidative stability. U.S. Pat. No. 5,425,817 describes a multilayered plastic pipe that comprises an inner and outer layer of at least one polyamide and at least one intermediate layer comprising a crystalline polyester. Again, no particular advantages in thermal or oxidative stability are attributed to this pipe. EP Patent Application 0 470 605 discloses a pipe with low-temperature impact resistance consisting of at least three layers of mutually compatible polyamides, at least one of which is glass-reinforced. No advantages in oxidative stability and long-term property retention at continuous exposure to high temperatures are described. U.S. Pat. No. 5,219,003 discloses a tube with low-temperature impact resistance that is suitable for conveying motor vehicle engine fuel and that comprises three layers that are made from at least two mutually compatible polyamides. The inner and outer layers contain impact modifiers and the middle layer contains substantially none.
It is seen that articles fabricated from polyamides that simultaneously offer improved retention of mechanical properties at high in-use temperatures and stabilization against oxidative degradation are not available. The object of the present invention is to provide multi-layered composite articles comprising a plurality of layers of polyamides and process for the manufacture of these articles such that the problems associated with the incorporation of commonly available oxidation stabilizers into the article and retention of the article's mechanical properties at high in-use temperatures are simultaneously averted. This and other objects, features and advantages of the invention will become better understood upon having reference to the detailed description of the invention herein.

Multilayered composite polyamide articles and processes for their preparation


This invention provides devices and apparatuses comprising the same, for efficient pumping and/or mixing of relatively small volumes of fluid. Such devices utilize nonlinear electrokinetics as a primary mechanism for driving fluid flow. Methods of cellular analysis and high-throughput, multi-step product formation using devices of this invention are described.

The ability to transport fluids in micron-sized channels is essential for many emerging technologies, such as in vivo drug delivery devices, micro-electro-mechanical systems (MEMS), and micro-total-analysis systems (μTAS). New methods for the rapid mixing of non-homogeneous fluids in micron-scale devices are also required, since the absence of turbulent mixing on these small length scales implies that mixing occurs by molecular diffusion alone. This typically takes from seconds to minutes—far too slow for envisioned applications. New technologies are thus required for the manipulation, transport and mixing of fluids on these small length scales.
Microfluidics is a growing area of science and technology with important applications in biomedical devices and portable electronics. Traditional pressure-driven flows do not scale well with miniaturization, due to large viscous stresses, so other pumping techniques have been explored. An attractive alternative is electro-osmosis, the effective slip of a liquid electrolyte past a solid surface in response to an applied electric field, since it does not involve any moving parts, is unaffected by miniaturization, and integrates well with standard microelectronics and fabrication methods. The standard technique of (capillary) electro-osmosis involves a DC electric field applied down a microchannel made of insulating material to generate a plug flow. The electric field acts on the equilibrium surface charge in the diffuse-part of the double layer, and the resulting electro-osmotic flow is linear in the applied field.
Various methods have been described to alter the surface charge in linear electro-osmosis to allow some degree of local flow control. For example, one method applies "field-effect electro-osmosis" to control capillary electro-osmosis by applying voltages at secondary electrodes just outside the channel surface, to alter the equilibrium surface charge (or "zeta potential") driving steady flow at the insulating channel wall and another controls liquid flow down a traditional insulating capillary by the same effect.
Capillary electro-osmosis, with or without field-effect flow control, however, is not ideal for certain microfluidic applications, since the electric field is applied down the channel, a large voltage is required, e.g. 100 Volts across a 1 cm device to generate typical fields of 100 V/cm. Since electro-osmosis is linear in the applied field, a direct current must be sustained through Faradaic electrochemical reactions at the electrodes generating the field, which can produce gas bubbles, electrode degradation/dissolution, hydrodynamic instability, and sample contamination. Further, the typical fluid velocity is fairly small (e.g. 100 micron/sec for a 100 Volt/cm field) and only increases linearly with the voltage. It would be preferable to drive flows with low-voltage alternating currents in many microfluidic applications, while somehow increasing the flow rate for the same applied field.
Microfluidic devices based on nonlinear electro-osmotic flow have also been developed. For example, nonlinear electro-osmotic flow, varying as the square of the applied voltage, termed "AC electro-osmosis" (ACEO), over a pair of flat, parallel-stripe microelectrodes on a flat insulating surface, has been described.
While existing ACEO pumps operate at much lower power (mA) and lower voltage (Volt) than microfluidic pumps based on linear electro-osmosis, nonetheless, current ACEO devices are somewhat inefficient for long-range pumping, and more general flow topologies for simultaneous mixing and pumping have not been developed.

Induced-charge electro-osmotic microfluidic devices


Disclosed are a laser radar system and a method for acquiring an image of a target, and the laser radar system includes: a beam source to emit the laser beam; a beam deflector disposed between the beam source and the target, and configured to deflect the laser beam emitted from the beam source in a scanning direction of the target as time elapses; and an optical detector configured to detect the laser beam reflected from the target, which is provided a plurality of beam spots having a diameter DRBS; and a receiving optical system disposed between the target and the optical detector and configured to converge the laser beam reflected from the target, and the optical detector includes a detecting area having a diameter DDA that satisfies an equation of √{square root over (2)}×PRBS+2×DRBS≦DDA≦2×Dlens and an equation of (4/π)×λ×F_number<DRBS<Dlens.

A 3-D imaging system can be used for a product such as a 3-D display TV, or the like, and can be used in order to secure a 3-D imaging for a distant military target, a 3-D imaging for monitoring a natural environment such as a landslide, or the like, and various 3-D imaging around a vehicle required for driving an unmanned autonomous vehicle.
In recent years, a ladar system has gotten the spotlight because high-quality 3-D image is required even under various environments.
A ladar system in the related art, which is used to acquire a 3-D image, includes a panoramic scan ladar (PSL) and a forward looking ladar (FLL). The PSL is disclosed in U.S. patent application publication No. 2011/0216304 (Title: HIGH DEFINITION LIDAR SYSTEM) [hereinafter, referred to as 'Related Art 1'] and the FLL is disclosed in U.S. Pat. No. 6,414,746 (Title: 3-D IMAGING MULTIPLE TARGET LASER RADAR) [hereinafter, referred to as 'Related Art 2'′].
Related Art 1 includes a plurality of laser generating modules and a plurality of optical detectors, for example, four laser generating modules and a '4×1' optical detector array. In the case of driving of Related Art 1, the laser generating module and the optical detector array may be configured to operate at different times or at the same time.
However, in Related Art 1, it is difficult to align the respective laser generating modules and respective pairs of optical detectors corresponding thereto so that the plurality of laser generating modules and the optical detector array are scanned in one line form or in a predetermined form. That is, an operation of examining a spatial viewing range of signals detected by the respective optical detectors and modifying a layout of the plurality of laser generating modules and the optical detector array to conform with a specification is required. This process may influence the price of the module and negatively influence mass production.
Further, in Related Art 1, a 2-D image (in general, distance information from a vertical-direction line) can be secured without rotation of the module. In order to acquire the 3-D images, however, an entire transmission/reception module including the plurality of laser modules and the optical detector array may be rotated.
Related Art 2 is constituted by a plurality of optical detectors that irradiates an optical signal generated by a laser generating module to a wide region and thereafter, detects light reflected on and returned from a target, that is, an 'M×N' optical detector array. In detail, a pulse laser generating device generating a short pulse evenly irradiates a laser to a wide surface at a predetermined diffusion angle through a diffuser, or the like. In this case, it is characterized that an irradiation region is extended depending on a distance and repeated light pulse irradiation surfaces are generated. The light pulse irradiation surfaces are hit and reflected on the target, reflected optical signals are collected through a light receiving lens, and the collected optical signals are detected through the optical detector array. In this case, the respective detectors of the optical detector array individually operate, measure time differences and magnitudes of the reflected optical signals at every positions of respective pixels, and a 3-D image of an object that reflects the optical signal may be formed by collecting the information.
However, since Related Art 2 requires comparatively high laser pulse power, it is difficult to implement a pulse laser module having a high pulse repetition frequency, and as a result, it is difficult to secure a high frame rate.
Further, In Related Art 2, pixel readout circuits that perform processing such as detecting an optical signal, which is reflected on the object and is incident independently as a pixel signal, are required to detect the signals of the respective optical detectors without influences from neighboring detectors in implementing an optical detector array, the pixel readout circuit parts are arranged in a 2-D array pattern, parts, which transfer and process signals generated from the insides of the pixels, are provided on outer edges thereof, and finally, a readout IC (ROIC), which can transmit the signals to the outside through an interface pad positioned around an edge of a chip, is required.
This type of ROIC includes both digital and analog ROICs. Since a sufficient signal to noise ratio needs to be secured even in a narrow pixel region, it is difficult to implement ROIC and manufacturing cost of the ROIC is high. Further, since the ROIC and the optical detector array are generally implemented by using different substrates, the ROIC and the optical detector array cannot be manufactured at the same time and are connected by a flip-chip method which is comparatively high in terms of cost. Consequently, since a video system having a complicated structure uses a short laser pulse on a wide surface, the video system has a characteristic (flash video) to acquire a still video with respect to an object (for example, rotating wings of a helicopter) which moves at a high speed, and as a result, the video system is used for a military purpose, but in general, total manufacturing cost of the system is high, and as a result, it is difficult to popularize the system.

Laser radar system and method for acquiring 3-D image of target

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


Power supply switching apparatus comprising an output switch for supplying power from a power supply to a load connected to an output terminal, a driver for controlling turn-on of said output switch, and a control signal generator for controlling said driver to produce a desired progressive turn-on characteristic. The apparatus also includes overload detection means responsive to a parameter of the load relative to a reference signal to provide a fault signal in case of detection of an overload condition after a turn-on phase of said output switch. The control signal generator is responsive to the reference signal to activate said overload detection means to provide a fault signal during the turn-on phase of the output switch even in presence of a severe overload condition at the output terminal.

Power supply switching apparatus with overload detection, also referred to as a 'smart power switch', is used in many applications, including automotive equipment, especially to control vehicle lighting, for example. It is particularly important to protect automotive wire harness and printed circuit boards (PCB) during the turn-on of the power supply, as well as switch components of the power supply itself, even in the event of severe short-circuits. The overload detector responds to an overload by providing a fault signal that can be used to limit or avoid damage. The present invention is particularly, but not exclusively, usable in such applications. Power switches with overload detection are disclosed in Patent Applications PCT/EP2004/014895, PCT/EP2005/005208, PCT/EP2005/005211 and PCT/EP2005/005212.
Such smart power switches are subject to stringent power consumption limits during their quiescent operational mode and it is desirable to avoid powering and activating overload detection before the load is to be turned on. Conveniently, the overload detector or sensor is powered and activated by the same control signal as turns on the load. Certain conventional overload protection circuits use a sensor comprising a sense resistor or Field Effect Transistor ('FET') and have a significant settling time of a few hundred microseconds (μsecs) when they are turned on; this already poses some issues for timely protection and prolongation of the reaction time should be minimised.
Moreover, power supply apparatus of this kind may be arranged to provide a progressive build-up of output current during turn-on, known as round-shaping, which is implemented to meet Electro-Magnetic Compatibility ('EMC') requirements, notably to reduce radio frequency emissions. In order to achieve EMC requirements, the output slew-rate, that is to say the progressive turn-on of the output switch of the power supply, is conveniently made dependent on the output voltage (Vout), which enables the use of a passive filter component to be avoided, for example. The round-shaping can be achieved by sensing the output voltage to obtain a progressive variation of the control signal applied to the output switch, turning the output switch on progressively. However, this progressive turn-on also tends to prolong the overload detection reaction time.
The overload detector responds to the load impedance by providing a fault signal that can be used to limit or avoid damage. Overload detectors exist that function well to detect typical resistive overloads, that is to say where the load impedance still presents a significant resistance even if it is an order of magnitude less than the normal load, for example, at least after an acceptable initial time delay while the energisation of the detector itself builds up. However, in severe overload conditions, known overload detectors may not respond adequately to a severe short-circuit condition at the power supply output. For example, if the overload detector is responsive to Vout, a severe short-circuit at the load will pull Vout down and keep it relatively low during a prolonged turn-on time in spite of rapidly increasing power supply output current. The overload sensor will not be energised to detect an abnormal condition during the turn-on phase fast enough to prevent the power dissipation damaging the power supply output switch and/or also the load supplied with power (wire harness and/or PCB).
A need exists for power supply apparatus with rapid overload detection during the turn-on phase, especially against severe overload conditions.

Power supply switching apparatus with severe overload detection


The present invention provides a hard coat film in which the generation of interference fringes can be reliably prevented. The hard coat film 1 of the present invention includes a transparent film 2 and a hard coat layer 3 provided on the transparent film 2, wherein an interface 5 that can be detected to form by a reflection spectrum analysis exists between the transparent film 2 and the hard coat layer 3, and a refractive index continuously varies in the thickness direction in a region 31 from the interface 5 to a thickness-wise middle part of the hard coat layer 3 without forming an interface that can be detected by the reflection spectrum analysis.

Conventionally, in order to prevent scratches or light reflection on screens of image display devices, touch panels, or other members, a hard coat film is sometimes provided on such a member.
The hard coat film includes a transparent film and a hard coat layer provided on the transparent film. The hard coat layer is usually formed of a thin coating film obtained by forming a film of about 2 μm to 10 μm from a hard coat layer-forming material containing an ionizing radiation-curable resin such as a heat-curable resin or a UV-curable resin.
In the former hard coat film, a refractive index difference exists between a transparent film and a hard coat layer. Therefore, there is a problem in that the presence of slight irregularities in the surface of the hard coat layer leads to the generation of interference fringes. In addition, "interference fringes" means a striped appearance caused by the reflection of light from a three-wavelength source, such as a fluorescent lamp, on the surface of the hard coat layer, etc. Such interference fringes cause a decrease in the visibility of the surface of the hard coat film.
In a known hard coat film, in order to prevent the generation of interference fringes, the surface of the transparent film is swollen by a hard coat layer-forming material to eliminate an interface between the hard coat layer and the transparent film, whereby the refractive index near the interface continuously varies (Patent Documents 1 and 2).
In another known hard coat film, in order to prevent the generation of interference fringes, an optical adjustment layer is provided between the transparent film and the hard coat layer to eliminate the interface between the transparent film and the hard coat layer (Patent Document 3).
However, the former hard coat films mentioned above do not sufficiently prevent the generation of interference fringes. Further, the hard coat film of Patent Document 3 requires an additional step of providing an optical adjustment layer during its production.
Meanwhile, in a hard coat film, it is necessary that the hard coat layer has high hardness for the purpose of preventing scratches, and, in addition, it is also necessary that the hard coat layer and the transparent film are sufficiently attached to each other.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2004-263082
[Patent Document 2]
Japanese Unexamined Patent Publication No. 2003-131007
[Patent Document 3]
PCT International Publication No. WO 2006/098363
It is an object of the present invention to provide a hard coat film in which the generation of interference fringes can be further suppressed and which has high hardness and excellent adhesion.
It is another object of the present invention to provide a polarizing plate and an image display device using the hard coat film.
It is another object of the present invention to provide a method for producing a hard coat film in which the generation of interference fringes is suppressed.
It is considered that in the hard coat films of Patent Documents 1 and 2 mentioned above, interference fringes due to the interface that separates a transparent film from a hard coat layer can be suppressed.
However, in such a hard coat film, as a whole, interference fringes are still present.
The present inventors have presumed that this is attributable to the presence of a new additional interface in addition to the interface that separates a transparent film from a hard coat layer. Specifically, the hard coat films of Patent Documents 1 and 2 are obtained by applying a hard coat layer-forming material, which contains a curable resin and a solvent, onto a transparent film, and then curing the coating film. The solvent swells the surface of the transparent film, and therefore, a transparent film-forming component elutes into the coating film. Then, it is presumed that the transparent film-forming component that has diffused and penetrated into the coating film causes the formation of the new additional interface mentioned above. Because of the presence of the new additional interface, practically, the former hard coat film is not capable of sufficiently suppressing the generation of interference fringes. Particularly in the case where the hard coat layer has a small thickness, interference fringes are likely to occur due to the additional interface. Such interference fringes are prominently visible in the appearance particularly when an antireflection layer is provided on the surface of the hard coat layer.
Based on this knowledge, inventors of the present invention solved the problems with the following methods.
A hard coat film according to a first aspect of the present invention includes a transparent film and a hard coat layer provided on the transparent film, wherein an interface that can be detected by a reflection spectrum analysis exists between the transparent film and the hard coat layer and a refractive index continuously varies in the thickness direction in a region from the interface to a thickness-wise middle part of the hard coat layer without forming an interface that can be detected by the reflection spectrum analysis.
A hard coat film according to a second aspect of the present invention includes a transparent film and a hard coat layer provided on the transparent film, wherein an interface that can be detected by a reflection spectrum analysis exists between the transparent film and the hard coat layer and a transparent film-forming component and a hard coat layer-forming component are present in a region from the interface to a thickness-wise middle part of the hard coat layer, and the transparent film-forming component in the region decreases toward a surface of the hard coat layer without forming an interface that can be detected by the reflection spectrum analysis.
In a preferable hard coat film of the present invention, the hard coat layer has a thickness of 3 μm to 15 μm.
In a preferable hard coat film of the present invention, an antireflection layer is further provided on a surface of the hard coat layer.
In a preferable hard coat film of the present invention, a transparent film-forming component and a hard coat layer-forming component are present in a region from the interface to a thickness-wise middle part of the transparent film, and the transparent film-forming component in the region decreases toward a surface of the hard coat layer.
According to another aspect of the present invention, a polarizing plate is provided.
The polarizing plate includes the hard coat film mentioned above.
According to another aspect of the present invention, an image display device is provided.
The image display device includes the hard coat film mentioned above.
According to another aspect of the present invention, a method for producing a hard coat film is provided.
The method for producing a hard coat film of the present invention includes a coating film-forming step of applying a hard coat layer-forming material onto a transparent film to form a coating film having a predetermined thickness, the hard coat layer-forming material including a curable compound containing a low molecular-weight component with a molecular weight of 800 or less and a solvent containing a good solvent for the transparent film, and a curing step of curing the coating film to form a hard coat layer on the transparent film, wherein the low molecular-weight component and good solvent contained in the hard coat layer-forming material and the thickness of the coating film satisfy the relationships of the following formulae 1 and 2, Formula 1: Y≧−4.274 ln (X)+11.311 and Formula 2: Y≦−4.949 ln (X)+15.474. In the formula, the "Y" represents b×t, the "X" represents a×t, the "a" represents the content ratio of the low molecular-weight component based on the total amount of the curable compound taken as 1, the "b" represents the content ratio of the good solvent based on the total amount of the hard coat layer-forming material taken as 1, and the "t" represents the thickness μm of the coating film.
In a preferable method for producing a hard coat film of the present invention, the "a" is 0.3 or more and 1 or less and the "b" is 0.05 or more and 0.5 or less.
In a preferable method for producing a hard coat film of the present invention, the low molecular-weight component is a UV-curable resin monomer or oligomer.
The hard coat film of the present invention is resistant to scratches and also is capable of further suppressing the generation of interference fringes. Further, the hard coat film is also excellent in terms of adhesion between the transparent film and the hard coat layer and thus has excellent durability.
The polarizing plate and an image display device including the hard coat film have excellent scratch resistance, durability, and visibility.
The production method of the present invention makes it possible to easily produce a hard coat film in which the generation of interference fringes is suppressed.

Hard coat film, polarizing plate, image display device, and method for producing hard coat film


A measurement pickup includes at least four measuring tubes for conveying media to be measured. Each measuring tube has a first in-/outlet end and a second in-/outlet end. During operation, the measuring tubes vibrate, at least at times, especially simultaneously. The measurement pickup further includes an electromechanical exciter mechanism causing the measuring tube to vibrate, as well as a sensor arrangement reacting at least to local vibrations of the measuring tubes for producing at least one measurement signal influenced by vibrations of the measuring tubes. Of the at least four measuring tubes, two measuring tubes are, at least at times, inserted into the course of a first medium-line such that each of these two measuring tubes simultaneously conveys, in each case, a partial volume of a medium flowing through the first medium line, and two other measuring tubes of the at least four measuring tubes are, at least at times, inserted into the course of a second medium line such that each of these two measuring tubes simultaneous conveys, in each case, a partial volume of a second medium flowing through the second medium line. The measurement pickup can thus, on the one hand, have two media flowing through it, which differ measurably from one another in at least one physical property, for example mass flow rate, medium density and/or medium temperature, while having, on the other hand, despite the different media, a good zero-point stability.

For measuring, or registering, a process variable of media flowing in lines, especially pipelines, especially for registering flow-dynamic and/or Theological, measured variables, often such inline measuring devices are applied, which utilize a vibration-type, i.e. vibratory, measurement pickup inserted into the course of the medium-conveying pipe, tube or hose line, and a measuring and operating circuit connected thereto, to cause, in the medium flowing through the pickup during operation, reaction forces, such as e.g. Coriolis forces corresponding to the mass flow rate, inertial forces corresponding to the density or frictional forces corresponding to the viscosity and to produce, derived from these forces, a measurement signal representing the particular mass flow rate, viscosity and/or density of the medium. The measurement pickup is, in such case, connected e.g. by means of flanges, medium-tightly, especially pressure-tightly, and mostly also permanently, with the line conveying the medium.
For operating the measurement pickup, especially also for the further processing or evaluating of the at least one measurement signal, such is, furthermore, connected with an appropriate measuring device electronics. In the case of inline measuring devices of the described kind, the measuring device electronics is, in turn, usually connected, via an attached data-transmission system, with other measuring devices and/or with an appropriate central computer, to which it sends the measured-value signals, e.g. via a digital data bus. Serving as data-transmission systems in such case are often, especially serial, bus systems, such as e.g. PROFIBUS-PA, FOUNDATION FIELDBUS, as well as the corresponding transmission protocols. The central computer can process the transmitted measured-value signals and visualize them as corresponding measurement results e.g. on monitors and/or convert them into control signals for corresponding actuators, such as e.g. magnetic valves, electromotors of pumps, etc. To accommodate the measuring device electronics, such inline measuring devices further include an electronics housing, which, as e.g. proposed in WO-A 00/36379, can be arranged remotely from the measurement pickup and connected therewith only over a flexible cable or which, as e.g. shown in EP-A 1 296 128 or WO-A 02/099363, is arranged directly on the measurement pickup, especially on a measurement pickup housing which houses the measurement pickup.
Especially, such inline measuring devices having a vibration-type measurement pickup are suited for the direct measuring of a mass flow rate balance, especially a mass flow rate difference, of two simultaneously flowing media conveyed in different medium-lines. Such balance measurements serve mostly to monitor the content of and/or the lack of leaks in, a container with connected system of lines by simultaneous measurement of the incoming flow of medium and the outgoing flow of medium. Corresponding cases of application for such balance measurements are to be found, for example, in the area of medical technology, especially in the areas of blood transfusion or dialysis, or in the area of paint technology, especially in the mixing of colors. Suitable balance measuring systems, which measure balances of two mass flows using inline measuring devices of the described kind, especially Coriolis mass flow measuring devices, are described e.g. in EP-A 441 328, EP-A 244 692, U.S. Pat. No. 6,457,372, U.S. Pat. No. 6,138,517 or U.S. Pat. No. 4,252,028.
For conveying the medium, the vibration-type measurement pickups disclosed therein all include two measuring tubes held in a frame of, for example, tubular or box shape. Each of these tubes is caused to vibrate—driven by an electromechanical exciter mechanism—for producing, during operation, the above-mentioned reaction forces. One of the measuring tubes is, in each case, intended for insertion into the course of a first medium-line conveying the, in the above sense, incoming medium, while the other measuring tube is provided for the, in the above sense, outgoing medium conveyed in a second medium-line. For registering, especially inlet-end and outlet-end, vibrations of the measuring tubes, the measurement pickups each have, furthermore, a physical-electrical sensor arrangement reacting to movements of the oscillating measuring tubes.
In the case of Coriolis mass flow measuring devices, the measurement of the mass flow rate of a flowing medium rests, in known manner, on allowing the medium to flow through each of the measuring tubes, which oscillate during operation laterally to an oscillation axis, whereby Coriolis forces are induced in such medium. These, in turn, cause inlet and outlet regions of the relevant tube to oscillate with phases which are shifted relative to one another, with the size of these phase shifts being a measure of the instantaneous mass flow rate in the measuring tube. The oscillations of each of the measuring tubes are, therefore, locally registered and converted into oscillation measurement signals by means of two oscillation sensors of the aforementioned sensor arrangement displaced from one another along the relevant measuring tube. The mass flow rate can then be derived from the relative phase shift.
In the case of balance measuring systems of the described kind, the measurement pickups have during operation, at least at times, two media simultaneously flowing through them and of character differing in at least one physical property, for example mass flow rate, density, viscosity and/or temperature. As a result of this, the measuring tubes can, during operation of the inline measuring device, significantly deviate from one another as regards their mechanical characteristics of oscillation, for example as regards the instantaneous oscillation amplitudes and/or the instantaneous oscillation frequencies, although they are constructed nominally practically identically. This can, as a result of the mechanical coupling between the individual measuring tubes, lead to considerable errors in the measured balance of the two medium streams, for example, thus, the measured mass flow rate difference, as discussed, for example, also in the already mentioned U.S. Pat. No. 6,457,372. For preventing or eliminating such measurement errors typical for balance measuring systems of the described kind, it is, furthermore, proposed in U.S. Pat. No. 6,457,372, to determine the oscillation amplitudes of the two, differently oscillating measuring tubes always separately, and, based on the individually measured oscillation amplitudes of each of the measuring tubes, to perform a suitable correction of the measured phase differences.
However, such a predominantly calculations-based compensation, which essentially only subsequently eliminates the measurement errors caused by the different oscillation amplitudes, leads, on the one hand, to an increased technical complexity as regards the construction of the exciter mechanism and sensor arrangement, as well as also regarding the construction of the measuring device electronics processing the measurement signals, as well as regards the hardware and also the software. Furthermore, it has been found, that the imbalances unavoidably associated with the non-uniform changes of the oscillation characteristics of the measuring tubes can lead to significant problems as regards the zero-point stability of the measurement pickup, which then are scarcely manageable any more by compensation measures limited essentially to measurement signal processing.

Vibration-type measurement pickup for measuring media flowing in two medium-lines, and inline measuring device having such a pickup


A retaining ring 1 for a shaft 2a usable with a bearing 3 having an outer ring 3a and an inner ring 3b fixed on the shaft, wherein the inner ring 3b and the outer ring 3a are rotatable relative to each other, and the retaining ring 1 is provided on the shaft 2a adjacent to the bearing 3 in a thrust direction to restrict a position of the bearing 3 in the thrust direction, the retaining ring 1 includes a protrusion 1a protruding in the thrust direction from a surface opposing the inner ring 3b in the thrust direction to contact the inner ring 3b so that the retaining ring 1 is out of contact from the outer ring 3a.

Conventionally, there has been known a technique in which a shaft retaining ring such as an E-ring (E-shaped retaining ring) is mounted to an annular groove formed on a shaft to suppress displacement or disengagement of a bearing in a thrust direction relative to the shaft.
Here, in the case that the shaft retaining ring contacts both an inner ring and a outer ring of the bearing, when the inner ring of the bearing and the retaining ring for the shaft rotate integrally, and the outer ring of the bearing and the retaining ring for the shaft rub against each other. This results in various problems such as rubbing noise, heat production, production of abrasion powder, and increase in required rotational load.
On the other hand, Japanese Utility Model Laid-Open Hei 5-19640 discloses a structure in which a gap is provided by a spacer such as a washer or a collar so that the outer ring of the bearing does not contact the retaining ring for the shaft.
In addition, instead of using standard bearings with the same width in the thrust direction between the inner ring and the outer ring, there is a technique in which an wide inner ring bearing having an inner ring wider than the outer ring is used, thus keeping the outer ring of the bearing and the retaining ring for the shaft out of contact with each other to suppress the displacement and the disengagement of the bearing in the thrust direction.

Shaft retaining ring and image forming apparatus


Polynucleotides encoding the human IL-11 receptor and fragments thereof are disclosed. IL-11 receptor proteins, methods for their production, antibodies to human IL-11 receptor, inhibitors of binding of human IL-11 and its receptor and methods for identification of their receptor are also disclosed.

A variety of regulatory molecules, known as cytokines, have been identified including interleukin-11 (IL-11). The various protein forms of IL-11 and DNA encoding various forms of IL-11 activity are described in Bennett, et al., U.S. Pat. No. 5,215,895 (Jun. 1, 1993); McCoy, et al., U.S. Pat. No. 5,270,181 (Dec. 14, 1993); and McCoy, et al., U.S. Pat. No. 5,292,646 (Mar. 8, 1994), all incorporated herein by reference. Thus, the term "IL-11" includes proteins having the biological activity described in these patents, whether produced by recombinant genetic engineering techniques; purified from cell sources producing the factor naturally or upon induction with other factors; or synthesized by chemical techniques; or a combination of the foregoing.
IL-11 is a pleiotropic cytokine that has been implicated in production of several biological activities including: induction of multipotential hematopoietic progenitor cell proliferation (Musashi et al. (1991) Blood, 78, 1448–1451); enhancement of megakaryocyte and platelet formation (Burstein et al. (1992) J. Cell. Physiol., 153, 305–312); stimulation of acute phase protein synthesis (Baumann et al. (1991) J. Biol. Chem., 266, 20424–20427); inhibition of adipocyte lipoprotein lipase activity (Kawashima et al. (1991) FEBS Lett., 283, 199–202); and effects on neurotransmitter phenotype (Fann et al. (1994) Proc. Natl. Acad. Sci. USA, 91, 43–47).
IL-11 may be used in a pharmaceutical preparation or formulation to treat immune deficiencies, specifically deficiencies in hematopoietic progenitor cells, or disorders relating thereto. Treatment of the other disorders or stimulation of the immune systems of cells thereof may also employ IL-11. IL-11 may also be employed in methods for treating cancer and other disease. Such pathological states may result from disease, exposure to radiation or drugs, and include, for example, leukopenia, bacterial and viral infections, anemia, B cell or T cell deficiencies such as immune cell or hematopoietic cell deficiency following a bone marrow transplantation. IL-11 may also be used to potentiate the immune response to a variety of vaccines creating longer lasting and more effective immunity. Therapeutic treatment of cancer and other diseases with IL-11 may avoid undesirable side effects caused by treatment with presently available drugs.
Like most cytokines, IL-11 exhibits certain biological activities by interacting with an IL-11 receptor (IL-11R) on the surface of target cells. It would be desirable to identify and clone the sequence for the human receptor so that IL-11R proteins can be produced for various reasons, including production of therapeutics and screening for inhibitors of IL-11 binding to the receptor and receptor signalling.

Antibodies to human interleukin-11 receptor


A facsimile machine in conformity with an information services digital network (ISDN) basic interface having a single signal channel and two information channels, includes a communication circuit, which has a first device of exchanging transmission and reception image signals with an ISDN through one of the two information channels (B-channels), a second device of exchanging the transmission and reception image signals with the ISDN through the other information channel, a third device of separately establishing the two information channels through the single signal channel, and a fourth device of controlling the first and second devices to independently exchange the transmission and reception image signals with the ISDN in parallel.

The present invention generally relates to a facsimile machine and more particularly, to a facsimile machine which uses an ISDN (Integrated Services Digital Network) basic interface as a communication means.
Recently, ISDNs have been put in good condition, and data terminal equipment has been in practical use. A facsimile machine which performs image information transmission through an ISDN is a group-4 (G4) facsimile machine. Standard equipment functions thereof have been recommended by CCITT.
According to the CCITT recommendation to a group-4 facsimile machine, a single signal channel (D channel) for a line exchange processing to one subscriber line, and two information channels (B channels) for data transmission are multiplexed.
However, a conventional group-4 facsimile machine is equipped with only one transmission function. Therefore, it is impossible to perform image information transmission in which the two information channels are used at the same time or in parallel. Further, broadcast transmission which employs the group-4 facsimile machine is executed by the following procedure. First, a document image to be transferred is read and then stored in a memory. Second, a plural number of designated designations is serially called out, and the stored image is serially transferred to the called-out designations. Thus, it takes long to complete broadcast transmission.

Facsimile machine using ISDN basic interface


The slackline balance board is for use during slacklining It includes an elongated deck having an upper surface and a bottom surface. The deck includes opposite first and second end sections, and a medial cambered section interposed between the first and second end sections. The medial cambered section is arched upwards with reference to a longitudinal axis. Two spaced-apart slackline guides are secured to the bottom surface of the deck.

Slacklining is a sport or physical activity that takes place on a narrow strip of flat webbing extending between two anchor points, such as large trees, rocks or any other suitable anchor points. The webbing is stretched to support the weight of a user standing thereon, although the webbing is not necessarily stretched so as to be rigidly taut like a tightrope.
The webbing on which slacklining is practiced is referred to as a "slackline". It can be made of synthetic fibers, such as nylon or others, woven to form a strong fabric. A slackline is generally about 1 to 2 inches (2.5 to 5 cm) in width. A slackline is thus considerably larger than a tightrope and this allows the weight of a user to be distributed over a much larger area. A slackline is often positioned horizontally and relatively close to the ground surface, for instance at a height of about 12 to 24 inches (30 to 60 cm). The section extending between the two opposite anchor points is often about 10 to 12 feet (305 to 365 cm) in length. Variants exist. For instance, some users can practice slacklining higher from the ground surface and/or using longer slacklines. Some slacklines may not be set horizontally.
When slacklining, users may be simply standing on the slackline. Others may combine various movements such as walking, standing on only one foot, pivoting, etc. Acrobatic moves or stunts can be done by experienced users. Users may adjust the tension in the slackline to vary the amplitude of the sagging, the bouncing effect and other characteristics. The tension can be adjusted using a ratchet mechanism or the like. Variants are possible as well.
A slackline may be installed outdoors or indoors. Although slacklining is mostly practiced above a ground surface on which the user can stand, a slackline can also extend over a water surface.
Slacklining is currently a sport where users interact with the slackline either with shoes or barefooted. This limits the number of possible actions that can be accomplished on a slackline. More specifically, no additional piece of equipment specifically designed for use between the slackline and the user's feet during slacklining is available.
Some sports or physical activities are part of a category that can be referred to as boardsports. Boardsports involve specialized boards as primary pieces of equipment and their users stand in an upright position above these boards. Surfing, skateboarding, windsurfing and snowboarding, to name just a few, are examples of boardsports. Other examples exist as well. The feet of the users may or may not be strapped onto the board, depending on the kind of boardsport and/or the kind of boards chosen by a particular user.
Balance boards also involve a board as a primary piece of equipment. Balance boards are designed for use on cylindrical or spherical objects. Thus, unlike in boardsports such as surfing, skateboarding, windsurfing and snowboarding, the user does not travel over a given distance but remains essentially at the same location throughout the entire duration of the physical activity. The user's body must stay balanced enough to keep the board's tips from touching the ground surface and to prevent the user from falling off the board. Balance boards are often used for leisure, balance training, athletic training, brain development and physical therapy, to name just a few.
Using a balance board on a slackline has not been suggested yet, even if such equipment would represent a breakthrough in slacklining Also, using a balance board on a slackline has its own challenges since the board must have certain characteristics and features to interact with a slackline, as well the ground surface, in a proper way. For instance, a slackline balance board would need to be relatively stable when the user is on the slackline, easy to use and to position with reference to the slackline, and have a relatively simple and inexpensive construction. It must also be able to engage the ground surface and withstand impacts, if applicable. These desirable characteristics have not been found hitherto. Moreover, one cannot simply use an existing board, for instance one designed for other boardsports, and use it on a slackline as a balance board. The same is also true for existing balance boards. Since they are designed for use on cylindrical or spherical objects, they cannot address the challenges specific to slacklining


A method may include heating a substrate in a first chamber to a platen temperature, the heating comprising heating the substrate on a platen; measuring the platen temperature in the first chamber using a contact temperature measurement; transferring the substrate to a second chamber after the heating; and measuring a voltage decay after transferring the substrate to the second chamber, using an optical pyrometer to measure pyrometer voltage as a function of time.

Processing of substrates at high temperatures often entails preheating of a substrate before processing. As an example, a substrate may be preheated in a first chamber, a preheat chamber or station, of a process tool, and subsequently transferred to a second chamber (a process chamber) or station, for performing a given operation, such as ion implantation, chemical vapor deposition (CVD), physical vapor deposition (PVD), substrate etching, or other suitable process.
Often, heating of a substrate in a preheat chamber (or preheat station) involves different heating apparatus than heating in the process chamber. For example, a process chamber may employ resistive heating or similar heating, where a platen is heated and heat is transferred to the substrate through a combination of conduction, convection, and/or radiation. A preheat chamber may be heated by heat lamps or other non-contact method.
Likewise, substrate temperature measurement may be performed by different techniques in different chambers. For example, substrate temperature measurement may be performed by a contact approach, such as using a thermocouple (TC) to directly measure heat (TC contact approach) conducted from the substrate or platen to the thermocouple. This TC contact approach requires good thermal conductivity between the surface of a substrate or wafer and the TC. In a high vacuum environment, microscopic gaps between the surface of the TC and the wafer can significantly reduce this conductivity. This reduction can result in a large offset between the TC temperature and the wafer surface temperature during contact. The offset between the TC and wafer temperature can vary according to the contact pressure, which variation, in turn, can necessitate a more complex system to control the TC contact force.
The thermal conduction offset may be reduced by flowing gas (e.g., N2) between the TC and wafer surface. Notably, this use of flowing gas increases system complexity and cost by introducing a system to deliver and control the gas flow.
Additionally, unexpected variations in this TC contact offset may occur when a user changes the thickness or material coating the backside of process wafers. These coatings may be customer-specific, and may not be disclosed to a tool (process equipment) manufacturer responsible for setting substrate temperature controls. Consequently, the manufacturer may have difficulty in helping the customer resolve temperature offsets related to changes in a backside coating on a substrate.
Moreover, in a process tool including a preheat chamber or station, process protocol may call for heating the substrate to a temperature close to the desired or target substrate for processing the substrate, which temperature may be referred to herein as a "process temperature." Meanwhile the substrate temperature of a substrate holder or platen in the process chamber may be set to the process temperature in the process chamber, using measurement tools, such as a thermocouple to establish the process temperature. Notably, the actual substrate temperature may change while the substrate is transferred between a preheat chamber and a process chamber. Additionally, using contact approaches to measure substrate temperature in a preheat stage may introduce unwanted damage, such as scratches, to a substrate. For example, mechanically pressing a TC into a wafer usually requires an additional motor and mechanism which apparatus can increase the cost and complexity of the preheat station. In addition, the operation of pressing a TC into the wafer surface during calibration may cause microscopic scratching of the wafer surface which damage can result in particles contaminating process wafers after calibration.
Additionally, tradeoffs in the results depending upon the mass of the TC itself may also need to be taken into consideration. A heavier TC will result in more stable, accurate temperature, but usually results in a slower response, which response can reduce the overall throughput of the machine. A lighter TC has a faster temperature response but may have a noisier and less stable signal.
With respect to these and other considerations, the present disclosure is provided.

Method and apparatus for calibration of substrate temperature using pyrometer


An apparatus is provided for approximating the jaw structure of surgical instrumentation. The apparatus includes a first jaw structure and a second jaw structure. The second jaw structure is disposed in spaced relation to and connected with the first jaw structure. The first and second jaw structure are interconnected for measurement of body tissue. An elongated endoscopic section extends proximally from the first and second jaw structure. A remote actuation member is connected to the proximal end of the elongated endoscopic section and is provided for relative movement of the first and second jaw structure. The apparatus further includes at least one indicating device which exhibits movement of the jaw structure.

1. Field of the Invention
The present invention relates generally to approximating apparatus for surgical instrumentation and more particularly to surgical apparatus for measuring body tissue which includes scissor-like approximation of jaw structure.
2. Description of the Related Art
Measuring body tissue during surgical procedures requires precise tissue thickness readings with definitive results under demanding time restraints. In these procedures accuracy and precision are important. Further, measurement indication should be visually accessible to ensure speed and accuracy of tissue measurement. The ease and efficiency of the tissue capturing step is also extremely important if the surgical procedure is to be carried out in an predetermined manner meeting surgical requirements.
Generally, tissue measuring devices for surgical procedures include a jaw structure. Manipulation of the jaw structure is necessary to capture the desired tissue. A typical surgical tissue measuring device is disclosed in U.S. Pat. No. 4,312,363 (Rothfuss et al.). The Rothfuss et al. device may be inserted into the body cavity through a surgical opening. The design and size of the tissue measuring device necessitates a surgical opening that is substantially large, or a body cavity made accessible during extensive surgical procedures. The device further includes jaw structure for capturing tissue. The jaw structure is actuated by a handle portion which may include a scaled portion for indicating tissue thickness.
One disadvantage to typical tissue measuring devices is they require a substantially large surgical opening to access the desired tissue and are therefore incapable and/or undesirable for use in endoscopic or laparoscopic procedures where accessibility is extremely limited. Moreover, due to limited accessibility, manipulation of the jaw structure may be problematic.
Accordingly, there is a defined need for a tissue measuring device that is applicable for endoscopic and/or laparoscopic procedures. It would also be desirable to provide a tissue measuring device which provides ease of operation during endoscopic and/or laparoscopic procedures. It would also be desirable to provide pivotal jaw structure which provides substantially problem free operation of the device. It would further be desirable to provide a tissue measuring device which is capable of controlled approximation of jaw structure. It is also desirable to provide a tissue measuring device that surely and accurately measures body tissue endoscopic and/or laparoscopically. It would further be desirable to provide positive and visually accessible indication of such tissue measurement during endoscopic and/or laparoscopic use of the device.

Surgical apparatus for measuring body tissue


The group of inventions relates to the technology for purifying liquids and gases by removal of contaminating multicomponent ingredients. The device comprises a housing comprising at least one hollow spiral element with a conical shape, with separation openings being formed in at least some of the turns of the spiral element, each of the openings communicating with a corresponding separation chamber. Arranged opposite the separation opening is a nozzle, which is intended for compensating for the mass and centrifugal moment of the fluid medium. A guide element around which a flow passes is mounted on the wall of the nozzle. The cross-sectional area and the radius of each successive turn is selected from the condition for maintaining an estimated value for the centrifugal moment of the substance to be purified. The method consists in that a flow of medium to be purified is spun by the above-described device. Contaminating components in each turn are positioned by coaxial layers. Layer-by-layer removal of the contaminating components via the separation openings is performed. A reduction in the centrifugal moment of the flow to be purified is compensated for by a clean layer of fluid medium being injected. Technical result: as complete purification of fluid media as possible.

In industrial countries, pollution of the environment is growing proportionally to the rise of production.
To recover some contaminating ingredients from liquids and gases (hereinafter fluids), depending on their properties and those of the fluid media to be purified, use is made of apparatuses with different constructions and operation principles. In most cases, no needed purification degree can be achieved in one apparatus, and one has to purify fluid media in two or more apparatuses placed downstream. Nevertheless, the gas purifying means recover only a part of atmosphere contaminating substances contained in the gases removed from technological units with a gas purification system.
I was established that the whole world yearly rejects into atmosphere more than 200 million tons of carbonic oxide, more than 50 million tons of various hydrocarbons, about 148 million tons of sulfur dioxide, 53 million tons of nitric oxides and other harmful substances (M. Ya. Yudashkin, "Dust collecting and purification of gases in ferrous metallurgy", Moscow, "Metallurgia", 1984, 320 p.).
Similar situation characterizes industrial and domestic sewage.
A trap separator comprising a separation conduit composed of two counter bends is known. The first bend is provided with a regulated aperture through which a coarse fraction is separated under the effect of centrifugal forces to be returned for grinding. In the second bend, additional purification of the gas flow is carried out, the fractions being additionally separated by sizing (specification of USSR author's certificate No. 1369764, Cl. B01D 45/12, published on Jan. 30, 1988).
However, said trap separator is characterized by a very narrow range of solid fractions that it traps from a gas flow, which highly reduces the gas purification degree.
As the closest prior art to the claimed invention is a spiral separator comprising a housing, a spiral separation conduit, the wall outer surface of which presents longitudinal ribs, and a porous screen under the form of tubes in a porous material is arranged between the last (specification of USSR author's certificate No. 1264963, Cl. B01D 45/12, published on Oct. 23, 1986).
The known spiral separator is designed mainly to separate liquids from a gaseous flow.
When the flow to be separated moves in the separation conduit of this known separator, the liquid separated under the effect of centrifugal forces falls onto the walls of tubes, penetrates both into the last and onto the outer surface facing the separation conduit wall and is removed from the separation area via the outer and inner surfaces, as well as via the capillaries of the tube porous material. The longitudinal tubes provide for uniform distribution of the flow in the separation conduit section and for smoothing out cross-sectional fluctuations.
The main drawback of said spiral separator is the narrow range of contaminants removed from the gaseous flow, in the considered case it is only liquid, said range being limited by the size of the porous material capillaries.

Method and device for purifying fluid media by removal of contaminating multicomponent ingredients