In a communication network where multiple bus systems are interconnected by a bus bridge, a first node attached to a first bus system acquires a first channel for transmission of packets to a first multicast address and broadcasts a first message pertaining to the first channel and the first multicast address. A second node attached to a second bus system acquires a second channel for transmission of packets to a second multicast address and broadcasts a second message pertaining to the second channel and the second multicast address. In response to receipt of the first and second messages, the bus bridge establishes a connection between two channels respectively identified by the received messages if the multicast addresses contained in the received messages are equal to each other.

1. Field of the Invention
The present invention relates generally to serial bus networks, and more specifically to a standardized serial bus network such as IEEE Std 1394-1995 or IEEE Std 1394a-2000 (hereinafter IEEE 1394 standard) in which bus bridges are used to interconnect serial buses and TCP/IP protocol is used for inter-bridge communications.
2. Description of the Related Art
Recent attentions have increasingly been focused on the high speed transport capability of the IEEE 1394 serial bus network to promote multimedia communications. One such effort has culminated in the IP over IEEE 1394 protocol (RFC 2734) developed by the IETF (Internet Engineering Task Force) to support the Internet Protocol. The IP over IEEE 1394 protocol defines a method in which IP packets are transmitted in unicast, multicast and broadcast modes. According to the IP over IEEE 1394 protocol, "asynchronous packets" are used for transmitting unicast messages and "asynchronous stream channels" are used for transmitting multicast and broadcast messages. Multicast channel allocation protocol is also defined for allocating an asynchronous stream channel to a number of nodes attached to a common bus.
The Serial Bus architecture supports multiple bus networks via bus bridges. A bus bridge normally eavesdrops on the bus, ignoring all transactions between local addresses but listening for remote transactions. When the bus bridge receives a packet for a remote address, it forwards the packet to an adjacent bus. After initialization, the bus bridges are transparent to the system. Bus bridges are also used to segment a large system into a number of small bus systems.
However, the multicast channel allocation protocol limits the reachable extent of multicast transmissions to only one bus system. While unicast and broadcast messages can be transmitted between multiple bus system via bus bridges, the bus bridges allow no inter-bridge multicast transmissions.
Therefore, there exists a need to provide bus bridges capable of retransmitting multicast packets from a multicast group of one bus system to a multicast group of another bus system. If a multiple bus network has three or more bus systems, intermediate bus systems must be capable of acquiring an asynchronous stream channel for retransmitting multicast messages from source to destination bus systems. In addition, such intermediate bus systems must also be capable of acquiring an asynchronous stream channel for multicast transmission even if their nodes are all receive-only nodes which are currently not designed to acquire an asynchronous stream channel.

Method and network for interconnecting separate multicast channels acquired for separate bus systems


A method and apparatus for actively controlling the gram load on a disk drive suspension assembly and to a disk drive using the present disk drive suspension assembly. The gram load can be actively changed by changing the applied voltage to one or more multi-layer piezoelectric actuators attached to the head suspension. The active gram control system allows the gram load to be changed on a non-permanent basis and to control the gram load to a much finer scale than can be accomplished using conventional techniques. The disk drive suspension that uses a piezoelectric actuator having two or more layers. Each layer of the multi-layer piezoelectric actuator is poled in such a fashion that when energized, some piezoelectric layers contract while others expand, resulting in a curling motion. By attaching the first and second ends of the piezoelectric actuator to discrete locations on the load beam, while the portion of the piezoelectric actuator between the first and second ends remains unattached to the load beam, a force non-parallel to the load beam can be applied to the head suspension.

The present invention relates to a method and apparatus for actively controlling the gram load on a disk drive suspension assembly and a disk drive using the present disk drive suspension assembly.
Head suspension assemblies are commonly used in rigid magnetic disk drives to support magnetic heads in close proximity to the rotating disk surfaces. Head suspension assemblies of this type typically include an air bearing head slider assembly mounted to a suspension. The suspension includes a load beam having a mounting region on its proximal end and a gimbal or flexure on its distal end. When incorporated into a disk drive, the mounting region is mounted to an actuator or positioning arm, which supports the suspension assembly over the rotating disk. A baseplate is typically welded to the mounting region to increase the rigidity of the mounting region and to provide a mechanism for securely mounting the suspension assembly to the positioning arm.
The load beam is an elongated and often generally triangularly shaped member that includes a spring region adjacent to the mounting region, and a rigid region that extends from the spring region. The flexure can be manufactured as a separate member and welded to the distal end of the load beam, or formed as an integral member in the distal end of the load beam.
The air bearing head slider assembly contains a magnetic head and is typically bonded to the flexure by adhesive. The flexure allows the head slider assembly to move or xe2x80x9cgimbalxe2x80x9d(about rotational pitch and roll axes) with respect to the distal end of the load beam and thereby follow variations in the surface of the spinning disk. To enable the pivotal flexure movement, the surface of the flexure to which the head slider assembly is bonded is typically spaced from the adjacent surface of the load beam by structures known as load point dimples or formed offsets.
Suspensions are commonly manufactured by chemically etching flat or unformed load beam blanks from thin sheets of stainless steel. Flat and unformed flexure blanks are etched in a similar manner from sheets of stainless steel. During subsequent manufacturing operations, side rails, load point dimples and any other structures that extend upwardly or downwardly from the web or generally planar surface of the load beam are formed on the load beam blanks by mechanical bending procedures. Any dimples, offsets or other structures on the flexures requiring deformation of this type are formed in a similar manner. After forming, the flexures are welded to the distal end of the load beams. Baseplates are also welded to the suspensions following the forming operations.
The product of these etching, welding and forming operations are generally flat suspensions (i.e., the mounting region, spring region and rigid region of the load beam are generally coplanar and at the same height. During subsequent manufacturing operations, at least a portion of the spring region of the load beam is rolled around a curved mandrel or otherwise bent in such a manner as to plastically bend or permanently deform the spring region. The rolling operation imparts a curved shape to the spring region and causes the flexure to be offset from the mounting region when the suspension is in its unloaded or free state.
As noted above, the suspension supports the slider assembly over the magnetic disk. In one embodiment, air pressure at the surface of the spinning disk creates a positive pressure air bearing that causes the slider assembly to lift away from and xe2x80x9cflyxe2x80x9dover the disk surface. In another embodiment, a negative pressure air bearing pulls the slider assembly toward the disk surface. To counteract these hydrodynamic forces, the head suspension assembly is mounted to the disk drive with the suspension in a loaded state so the bent spring region of the suspension biases the head slider assembly either toward or away from the magnetic disk. The height at which the slider assembly flies over the disk surface is known as the xe2x80x9cfly height.xe2x80x9dThe force exerted by the suspension on the slider assembly when the slider assembly is at fly height is known as the xe2x80x9cgram load.xe2x80x9d
By controlling the gram load of the head suspension, the force applied to the read/write head at a constant flying level can be determined. Current suspensions have a gram load that is determined by a bend radius in the suspension arm. The accuracy of this type of gram loading method is typically about +/xe2x88x920.1 grams. Once bent into position, the suspension arm has no way of changing the gram load, unless subsequently bent or altered in a permanent way.
U.S. Pat. No. 5,898,541 (Boutaghou et al.) discloses a bi-morph piezoelectric bending motor mounted on the head slider. The bending motor cooperates with a tab surface on the flexure to rotate the slider.
U.S. Pat. No. 5,719,720 (Lee) discloses a load beam of a head suspension mechanism that has a non-load bearing, single layer of piezoelectric material on at least one surface of a resilient portion of the load beam. A controller apparatus provides a control signal to the piezoelectric material that induces expansion or contraction of the piezoelectric material to cause the load beam to raise the head slider from the surface in the disk drive. Since the piezoelectric material of the ""720 patent is limited to compression and expansion forces, it must be attached directly to the surface of the load beam. Consequently, the compression or expansion of the single layer piezoelectric material occurs along the length of the load beam and must overcome the stiffness of the load beam to produce a bending or curving motion of the resilient portion of the load beam. That is, the forces generated by the compression or expansion of the piezoelectric material are parallel to the surface of the load beam. Directing the forces from the piezoelectric material parallel to the load beam limits the amount of deflection and load applied to the load beam.
The present invention is directed to a method and apparatus for actively controlling the gram load on a disk drive suspension assembly and to a disk drive using the present head suspension. The gram load can be actively changed by changing the applied voltage to a multi-layer piezoelectric material attached to the head suspension. The active gram control system of the present invention allows the gram load to be changed on a non-permanent basis and to control the gram load to a much finer scale than can be accomplished using conventional techniques. The present active gram control system may also be used for active vibration damping, lifting the read/write head, a shock sensor, and for contact recording.
The present invention is directed to a disk drive suspension assembly that uses at least one piezoelectric actuator having two or more layers. In a two-layer embodiment, each layer of the multi-layer piezoelectric actuator is poled in such a fashion that when energized, one piezoelectric layer contracts while the other expands, resulting in a curling motion. In an embodiment with more than two layers, the piezoelectric actuator is poled to achieve a curling motion. By attaching the first and second ends of the piezoelectric actuator to discrete locations on the load beam, while the portion of the piezoelectric actuator between the first and second ends remains unattached to the load beam, a force that is non-parallel to the surface of the load beam can be applied to the head suspension. In one embodiment, the force is normal to the load beam.
In one embodiment, the load beam may include a compliant region located between the first and second attachment locations for the piezoelectric actuator. Consequently, the piezoelectric actuator in an unactuated state supports a portion of the gram load. By arranging the multi-layer piezoelectric to span across the compliant region, a greater range of motion and a greater range of gram loading can be achieved. Compliant region refers to a partial etch, a hole, a recess, a narrowing of the load beam, one or more lines of weakness extending generally laterally across load beam, or other features in the load beam that create a location of flexibility greater than elsewhere along the load beam.
The present invention is also directed to a disk drive using the present disk drive suspension assembly. The disk drive includes a rigid magnetic disk and a positioning arm attached to the actuator arm mounting region. The head mounting region on a distal end of the load beam includes at least one transducer head positioned opposite the rigid magnetic disk. The piezoelectric actuator has at least two layers. First and second ends of the piezoelectric actuator are attached to the load beam at first and second attachment locations, respectively, so that a force non-parallel to the load beam is applied to the head suspension in an actuated state. In one embodiment, the force is normal to the load beam.
The multi-layer piezoelectric actuator can be used to determine precisely the flying height of the read/write heads on the disk drive suspension. Moreover, the gram load can be changed with changing drive conditions. The multi-layer piezoelectric actuator can eliminate the need for an active head lifter and landing zones on the fixed disk, while protecting the read/write heads during periods of inactivity. Since the layers of the multi-layer act as both actuators and transducers, the various layers produce a voltage when deflected. In one embodiment, these voltages are extracted to dampen gram changing vibrations and deflections. In another embodiment, the extracted voltages can be actively counteracted to reduce gram changing vibrations.
The present invention is also directed to a method of making a disk drive suspension assembly in accordance with the present invention. A load beam is formed having a distal end, an actuator arm mounting region on a proximal end, a rigid region, and a spring region between the rigid region and actuator arm mounting region. A compliant region is formed in the load beam. A head mounting region is formed on a distal end of the load beam for receiving a transducer head. A piezoelectric actuator having at least two layers is assembled. First and second ends of the piezoelectric actuator are attached to first and second attachment locations on opposite sides of the compliant region of the load beam so that the piezoelectric actuator supports a portion of the gram load in an unactivated state. The method may include the step of applying a voltage to one at least one of the piezoelectric actuators to perform one or more of controlling the flying height of the head mounting region, modifying the gram load, raising or lowering the head mounting region, measuring vibrations and deflections of the load beam, dampening vibrations of the load beam, controlling attitude of the head mounting region, and applying a lateral force on the load beam.

Disk drive suspension with multi-layered piezoelectric actuator controlled gram load


A 3D printed display panel includes two opposing substrates and a black matrix formed on one of the substrates. The light proof areas of the black matrix include multiple first portions, multiple second portions and multiple third portions arranged to form a grid structure. The first portions and the third portions are alternately arranged in a direction of the scanning lines, the second portions and the third portions are alternately arranged in a direction of the data lines. Meshes of the grid structure are aperture zones of the black matrix. The aperture zones are in one-to-one correspondence with the pixel units. A vertical projections of the scanning lines and the data lines on the second substrate are located in the lightproof areas; where a minimum width of one first portion is X, a minimum width of one second portion is Y, and |X−Y|≤2 μm.

The rapid prototyping (RP) technology (also referred as rapid prototyping manufacturing (RPM)), also known as 3D printing, is a high-tech manufacturing technology based on material stacking. Specifically, based on three-dimensional (3D) model data of desired parts or objects, a physical object or a physical model may be manufactured by a prototyping device in a manner of material accumulation. The 3D printing technology has gradually grown popular and has been rapidly developed in recent years from its advantages including largely reduced production costs, improved utilization rate of raw materials and energy, easy customization according to demands, and great saving of production time.
At present, a conventional liquid crystal display panel is generally applied to 3D printing. Specifically, a resin is coated on a pallet in advance, and the conventional display panel is used as a photomask, so that the ultraviolet light is controlled to pass through the display panel and enter the resin to cure the resin. In such a way, according to the pattern to be printed, the deflection angle of the liquid crystal molecules in each pixel unit of the display panel is controlled, and thus the ultraviolet light transmission in each pixel unit is controlled, so that the resin may be patterned accordingly. However, configuration of the existing display panel does not match the new printing design, leaving failed dark spaces outside light spots formed on the resin after the ultraviolet light transmits through the display panel mask. Therefore, the light may not sufficiently cover the patterned resin, resulting insufficient curing of resin in those failed spaces. The failed spaces occur as pits on the final 3D printed product, failing to meet the users' demands.

SHANGHAI AVIC OPTO ELECTRONICS CO., LTD.


An image scanning apparatus has such a configuration that an item and a content of additional information such as previously set character information, sound information recorded in the image scanning apparatus and character information inputted in the image scanning apparatus are displayed unitarily and a user selects and updates freely the displayed item and the content of the additional information.

1. Field of the Invention
The present invention relates to an image scanning apparatus such as a digital camera and a digital movie.
2. Description of the Prior Art
Generally, in an image scanning apparatus such as a digital camera and a digital movie, a various of proposals have been made with respect to a technology for adding character data as an additional information to image data of a photographed image. For example, if a photography is performed by a digital camera, it is considered that a various of information are recorded together with a photographed image, the information recorded with the photography are transmitted to a personal computer (PC) or the like and are used as information for carrying out various after-processing.
Additionally, there is listed Japanese Patent Laid-Open 2002-158953 proposed by the Applicant or the like as prior art. The reference discloses that a digital camera inputs a photographic list including one or more cut names of a recorded object to be recorded, through an inputting means for inputting the photographic list, displays the cut name included in the photographic list on a displaying part and takes a photograph while confirming the cut names of the photographic list, and the inputting means includes web browsing means for brewing a home page of a web server to be connected and for down-loading the photographic list on the home page.
However, there is a problem in the operationality in the conventional digital camera for the reason that an item and a content of the additional information such as previously set character information, sound information recorded in the digital camera and character information inputted in the digital camera cannot be displayed unitarily and cannot be selected and updated.


Complex-valued sensitivity data structures corresponding to respective candidate survey settings are provided, where the sensitivity data structures relate measurement data associated with a target structure to at least one parameter of a model of the target structure. Based on the sensitivity data structures, a subset of the candidate survey settings is selected according to a criterion for enhancing resolution in characterizing the target structure.

Survey operations can be performed to acquire measurement data for characterizing content of a subterranean structure. Examples of survey operations include seismic survey operations and electromagnetic survey operations. Survey operations can be performed using survey equipment deployed at or above an earth surface that is above the subterranean structure of interest. Alternatively, at least part of the survey equipment can be deployed in wellbore(s).
Once survey data is acquired, the survey data can be analyzed to characterize the subterranean structure, such as by developing an image or other representation of the subterranean structure, where the image or other representation contains properties of the subterranean structure.

Selecting a survey setting for characterizing a target structure


The present utility model provides a digital multi-meter that can not only; generate warning signal when the test probe is misplugged but also indicate the assigned socket before the probe is plugged in. The multi-meter contains a socket indicating a misplug warning circuit whose micro-control unit is connected with each measurement function switch via its terminals respectively. When any measurement function switch is closed and its corresponding socket is unclosed, the micro-control unit switches on the relevant LED to emit light via connected terminal in order to indicate the assigned docket. On the contrary, the micro-control unit switches off the LED to stop emitting light in order to indicated the proper operation. The multi-meter can indicate not only mis-operation after the probe has been plugged in but also the assigned socket before it so that it decreases the possibility of mis-operation and avoids damage effectively and elongates its working life.

During the use of a multi-meter or other electronics test equipment, if the test leads are incorrectly inserted, this will damage the equipment. Based on experience in repairing damaged meters, over 50% of the cases are caused by the incorrect insertion of the test leads. As a result, some manufacturers added warning buzzers or other sound devices to alert the user that the meter has been damaged. Unfortunately, these warning devices are activated only after the equipment has been damaged, therefore it cannot prevent the meter from being damaged.

Digital multi-meter with operational error prevention technology using LED and microprocessor with input sockets


A system for generating software applications for a plurality of heterogeneous computing devices. Each computing device has different capabilities. The system outputs device-specific versions of a software application each tailored to the capabilities of the associated computing device in response to receiving device-independent modeling information characterizing the software application. The system includes a framework, a plurality of object types, a modeling tool, and a plurality of device-specific code generators. The framework defines common services on the computing devices. Each object type has a functional relationship to the common services provided by the framework. The modeling tool defines instances of the plurality of object types based on modeling information received as input, outputting a metadata structure describing the behavior and functionality of a software application. From the metadata, the code generators generate device-specific application code tailored to the capabilities of the associated devices.

Information and computer technology comprises an essential component for modern business operations. The utility of computer technology has been enhanced by the coupling of computers with information networks such as the Internet and World Wide Web ("WWW"). Successful business operations in the global marketplace require a synergetic relationship between local and distributed operations. For example, localized operations may include research and development, inventory management, customer service, strategic planning, etc. Distributed operations are conducted, for example, by sales personnel in the field who interact with customers and perform such tasks as order generation, customer relations, customer support, etc. Field personnel utilize mobile devices such as laptop computers for customer information, intake of customer orders, communication with one or more centralized databases at the home office etc. Field personnel demand accurate and timely information regarding the state of business operation in order to effectively perform their jobs. For example, sales personnel typically require up to the minute information regarding current inventory levels, product availability and customer data. Conversely, the enterprise can operate more effectively through centralized management of information regarding the operations of field personnel and information collected in the field.
One model for providing the requisite computing environment involves a plurality of mobile devices operating in an offline mode, which is transparent to the users. That is, the mobile devices run applications in offline mode, yet the user interacts with the mobile applications as if they were running in an online mode. This transparency of operation presents significant challenges both from runtime and development perspectives. In particular, runtime challenges include providing accurate and lossless synchronization of data between a centralized database typically located at the enterprise location and the mobile devices.
Development challenges involve efficiency for rapid creation of applications for a disparate array of mobile devices and platform environments. With conventional systems, it would typically be necessary to develop a separate application for each mobile device. This scenario is highly inefficient since code reuse is not encouraged, therefore requiring significant development time.
Another challenge relates to the fact that mobile users would often desire to utilize smaller footprint devices in the field such as PDAs rather than laptop computers. However, due to the fact that these devices are often limited in processing power and storage capabilities, it becomes impossible to run a full business application on these devices. The advantage of PDA types of devices is their small footprint and weight making these devices ideal for gathering data in the field. Thus, it would be desirable for an offline runtime environment to provide the capability for the use of PDA devices, while preserving the fundamental qualities of the transparency of the offline mode. From the development perspective, it would be desirable for a development environment to provide maximum code reuse and automated generation of applications, which are adapted to the specific properties of particular PDA devices.

Cross-platform development for devices with heterogeneous capabilities


A tire uniformity machine includes an apparatus for receiving and rotating a tire. The apparatus includes opposed spindles for receiving, inflating and rotating a tire, and a load wheel applied to the rotating tire to obtain tire test results. A spindle alignment assembly is associated with the opposed spindles to align the spindles with one another each time a tire is received. At least one characterizing device is associated with components of the apparatus to characterize forces of the opposed spindles and the characterized forces are used in adjusting tire test results.

Ideally, a tire is desirable to be a perfect circle, and interior stiffness, dimensions and weight distribution and other features thereof should be uniform around the circumference of the tire. However, the usual tire construction and manufacturing process make it difficult to mass produce such an ideal tire. That is, a certain amount of nonuniformity in the stiffness, dimensions and weight distribution and other features occur in the produced tire. As a result, an undesirable exciting force is produced in the tire while the vehicle is running. The oscillations produced by this exciting force are transmitted to the vehicle chassis and cause a variety of vehicle oscillations and noises including shaking, fluttering, and sounds of the tire vibrations being transmitted inside the vehicle.
Industry standards are available for evaluating nonuniformity of a tire. In one method, a rotating drum, which serves as a substitute for the road surface, presses against a rotatably held tire with a predetermined pressing force (several hundred kilograms), or the tire is pressed against the rotating drum with the predetermined pressing force. The tire and the rotating drum are capable of rotating around their respective rotational axes, in such a way that when either one rotates, the other is also caused to rotate.
In this condition, the tire or the rotating drum is rotatably driven so that the tire rotates at 60 revolutions per minute. As the tire rotates, the exciting force produced by nonuniformity of the tire occurs. This exciting force is measured by one or more force measuring devices (such as a load cell) mounted on a bearing which rotatably supports the tire or the rotating drum, or mounted on a member attached to this bearing. From the measured value, an index that serves to evaluate the nonuniformity of the tire is computed. This measurement is referred to as a uniformity measurement.
Tires on which measurements were performed are classified into those for which the nonuniformity obtained from the index is within tolerable limits and those for which it is not. To the extent possible, tires for which the nonuniformity is outside of the tolerable limits are subjected to processing to decrease the nonuniformity. Tires that have been processed are then subjected to uniformity measurement again; those for which the nonuniformity is within tolerable limits are separated from those for which it is not. Through the procedure described above, only tires judged to have "nonuniformity within tolerable limits" are selected and shipped to customers (or sent to the next step in the tire evaluation procedure).
Although current tire uniformity machines are believed to be effective, it is believed that further improvements can be obtained. Current tire uniformity machines provide test results that are sometimes inconsistent. In determining whether a uniformity machine is reliable, a same tire will be tested five times to ensure that the machine consistently detects and measures any nonuniformities in the tire. An additional sampling of tires are also then subjected to the same uniformity tests. From this collection of test results, various filters can be generated and applied to production tires to filter actual results. As skilled artisans will appreciate, filtering the test results undesirably adds time to the test procedure. Filtering also raises concerns that the filters may be set to exclude tires that are acceptable and, more problematically, tires that are not acceptable may be passed to allowance.
One approach is to generate characterization plots of components of the tire uniformity machine that adversely affect the true uniformity of the tire under test. It has been determined that the forces applied by components of the uniformity machine each have their own unique characteristic that varies from machine to machine. For example, the rotating drum on one uniformity machine has a different characteristic than another rotating drum on a different machine. It is believed that each rotating drum that contacts the tire's surface and each upper and lower spindle and chuck assembly that engages the tire's bead has a unique force characteristic that contributes errors into the uniformity measurements detected by the machine It is also believed that prior attempts to adequately characterize the load wheel and the spindle characterization are deficient. In particular, prior methods did not adequately consider differences between the angular alignment or rotational position of the upper and lower spindle and chuck assemblies. As a result, different angular alignments of the spindle and chuck assemblies result in force contributions to a tire uniformity measurement that are not adequately filtered or that distort the filtered measurements in a way that does not accurately represent a tire uniformity measurement. Therefore, there is a need in the art to generate an accurate characterization of the spindle and chuck assemblies and a need in the art to consistently align the upper and lower chuck assemblies so that the characterization can be consistently applied to tires being tested.

System for characterizing tire uniformity machines and methods of using the characterizations


A method of dividing, in a micro computer unit (MCU), a first binary number (N), having a first number of significant bits, by a second binary number (D), having a second number of significant bits, produces an integer result (Y). The method includes: determining the difference (K) between the first and second numbers of significant bits; aligning the most significant bits (MSBs) of N and D by shifting the bits of D, by K bit positions, such that its MSB occupies the same relative bit position as the MSB of N; repeating K times: multiplying Y by 2; dividing D by 2; and, if N is greater than or equal to D: increasing Y by 1; setting N equal to N−D.

1. Field of the Invention
The present invention relates to a method and apparatus for performing division of two binary numbers in a digital system. The division may be performed using a microprocessor (μP), a microcomputer (μC), a Digital Signal Processor (DSP) or other similar digital processing device. The term Micro Computer Unit (MCU) will be used throughout this description to refer to any or all such processing devices.
2. Description of the Related Art
MCUs are typically used in a variety of devices requiring some form of digital processing capacity. Such devices cover a diverse range of uses ranging from washing machines to industrial control equipment, and televisions to central heating thermostats. A particular application for MCUs is in the field of telecommunications. MCUs are to be found in portable telephones and the associated base stations which allow the telephones to communicate with other users via a communication network.
MCUs used in telecommunication equipment are frequently employed to implement certain algorithms which are used e.g. to enhance the transmission of data, to encrypt data or to process control signals used to set up and control a communication channel. These algorithms are often carefully chosen so that they can be implemented in a straightforward fashion using existing MCUs.
In particular, prior art MCUs are generally not able to perform division operations particularly efficiently. Simple addition, subtraction and multiplication operations may be able to be performed in single instruction cycles, whereas division operations may occupy the MCU for many cycles. As such, algorithms are chosen or devised so that division is limited as far as possible to division by a factor of 2n only, which equates to a simple bit-shift operation.
MCUs which are capable of performing division operations in a relatively short number of clock cycles, or even a single clock cycle, require the provision of very many custom logic gates to perform this function. As such, the overall complexity of the MCU is increased along with its size and power consumption. This is particularly undesirable in handheld communication equipment where physical size and battery life are two important design factors.
Given integer numbers Numerator (N) and Denominator (D), the prior art teaches a number of different ways to perform the divide operation N/D. A first simple method is to repeatedly subtract D from N, noting the number of times this process is repeated in a counter Y. The number of times this is possible before N becomes less than D gives the integer value of the result in Y. The remainder is held in N. Of course, such a simplistic system can require many clock cycles if N is many times larger than D, and as such is unsuitable for all but the simplest and least speed-critical of systems.
A particular problem arises when trying to configure an MCU for use with the UTRA (Universal Terrestrial Radio Access) FDD (Frequency Division Duplex) W-CDMA (Wideband—Code Division Multiple Access) communication standard. This particular standard specifies a particular division operation for use in calculating the parameters for rate matching/puncturing in the channel coder rate matching algorithm.
In designing a custom MCU for use with the UTRA FDD W-CDMA standard, it is not expected that the division operation will be called by the algorithm so frequently that it will require a specific block of custom hardware to perform a division in one clock cycle, but on the other hand, a balance must be struck between complex custom hardware and an over-lengthy division process occupying too much MCU time.


There is described a device for controlling an amount of current within a power distribution network by manipulating the amount of magnetic flux in the device and thus the impedance experienced by the power distribution network across the device. This is achieved by winding a plurality of coils about a magnetically permeable core and by providing the device with a magnetically permeable bridge element that is movable between a fully-open position at which the net magnetic flux generated in the core by alternating currents in each coil is zero, and a fully-closed position at which a net magnetic flux is present in the core.

Electrical power systems are used to generate and supply electrical power. An example of such a system is an electrical grid that generates and provides power to an extended area. Smaller electrical power systems can also be implemented on aircraft and marine vessels etc.
An electrical power system typically includes a generator set and a power distribution system that feeds the generated power to nearby electronic components of the overall power system. The distribution system typically comprises a plurality of distribution lines for supplying alternating-current (AC) or direct-current (DC) to the electronic components and one or more return lines used as a return path for the current.
A known problem with electrical power systems is that the distribution system can occasionally experience faults, which may be the result of crossed or downed distribution lines, for example. Faults in the distribution system can cause an excessive current (which is to be referred to herein as "overcurrent" or "fault current") to flow through the wider electrical power system, which is particularly problematic to upstream critical loads that often become damaged as a result.
It is known to protect electrical power systems from fault currents by using a device referred to as a fault current limiter (FCL), which limits the fault current without complete disconnection of the current. An FCL typically operates by providing a low impedance at normal current levels but a high impedance during a fault when excessive current levels tend to exist. An FCL is typically in the form of a "superconducting" FCL which is configured such that when a fault develops, its resistance rises sharply (through a process known as "magnet quenching") and the fault current is diverted to a parallel circuit having higher impedance.
A problem in such systems, however, is that they are bulky in size (e.g. in that they have a parallel circuit) and often require servicing and replacement of constituent parts after a fault occurs. Accordingly, it would be desirable to provide a device for controlling a current in an N-phase power distribution system during a fault condition which is less bulky and includes less parts to be replaced after a fault, amongst other things.


An image sensor includes a pixel unit and a pixel readout circuit. The pixel unit includes an image pixel array including a plurality of image pixel columns, respectively; a first reference pixel array including a plurality of first reference pixel columns; and a bias circuit, coupled to the image pixel columns for generating a plurality of column sensing signals, coupled to the first reference pixel columns for generating a plurality of first reference signals, and further for generating a first average reference voltage signal according to the plurality of first reference signals. The pixel readout circuit generates a plurality of reset values and a plurality of sampling values according to the column sensing signals and the first average reference voltage signal, wherein the plurality of reference pixel rows is less than the plurality of image pixel rows.

1. Field of the Invention
The present disclosure relates to an image sensor, and more particularly, to an image sensor in which one or more reference pixel rows are shared to eliminate row noises from different image pixel rows and to reduce reference pixel area, thereby preventing from the drop of frame rate when eliminating the row noises by a digital approach or avoiding extra noises and reducing circuit area when eliminating the row noises by an analog approach.
2. Description of the Prior Art
In general, in an image sensor, a pixel readout circuit such as a correlation double sampling (CDS) is utilized to read image pixel rows row by row so as to generate reset values and sampling values. Consequently, when different image pixel rows are read, even though the patterns of the different image pixel rows are actually identical, pixel readout circuit may still read different reset values and sampling values owing to random noises, more specifically, because external electrical potential like system voltages, grounded electrical potential and bias reference voltages are disturbed by the random noises. In this case, the conventional image sensor is usually equipped with a reference pixel array in order to eliminate the row noises caused by the random noises.
Please refer to FIG. 1, which is a schematic diagram illustrating a conventional image sensor 10. As shown in FIG. 1, the image sensor 10 comprises a pixel unit 100, a pixel readout circuit 102, a control circuit 104, a row control circuit 106, a column decoder 108, a differential amplifier 110, an analog-to-digital converter 112 (ADC) and an image signal processor 114. The pixel unit 100 further comprises an image pixel array 116 and an optical-black-area pixel array 118 and optionally comprises a reference pixel array 120. The reference pixel array 120 is disposed after the last pixel (or before the first pixel) of each row of the image pixel array 116.
In short, after photodiodes of each of the pixels in the image pixel array 116 are exposed to light during an image sensing process, charges are induced by the photodiodes and stored in the corresponding sensing capacitors. Subsequently, the control circuit 104 controls the row control circuit 106, the column decoder 108 and the pixel readout circuit 102, such that the pixel readout circuit 102 samples the image pixel array 116 row by row and generates the reset values and the sampling values of each pixel. Then, the difference between the reset values and the sampling values is amplified, converted from analog to digital form and processed by the differential amplifier 110, the analog-to-digital converter 112 and the image signal processor 114. During the image sensing process, the optical-black-area pixel array 118 and the reference pixel array 120 are shielded against light in order to respectively provide dark current and the information of random noises when the pixel readout circuit 102 performs sampling; therefore, the pixel readout circuit 102 or the image signal processor 114 can respectively suppress dark current and random noises by analog or digital approaches.
To be more specific, please refer to FIGS. 2A to 2C. FIG. 2A is a schematic diagram illustrating an image sensor 20 which embodies the image sensor 10 shown in FIG. 1 in the prior art. FIG. 2B is a schematic diagram illustrating a pixel 202 shown in FIG. 2A. FIG. 2C is a timing schematic diagram illustrating the signals shown in FIGS. 2A and 2B. In short, as shown in FIGS. 2A to 2C, the image pixel array 116 comprises the image pixel rows R1-Rn and the image pixel columns C1-Cm. The pixel 202 may be any pixel in the image pixel array 116. For example, the pixel 202 can be located at a point of any intersection of the image pixel rows R1-Rn and the image pixel columns C1-Cm. The pixel readout circuit 200 comprises the sample-and-hold circuits SHC1-SHCm, which respectively correspond to the image pixel columns C1-Cm.
In this structure, during the image sensing process, a photodiode 204 exposed to light generates charges and the charges are stored in a sensing capacitor 206 to serve as a sensing signal. When a bias reference voltage BIAS is high and after a row selecting signal chooses the image pixel row with the pixel 202 and hence a row switch RS is switched on, a pixel reset switch RST and a reset switch SHR are turned on in sequence. Subsequently, according to a system voltage VDD, which is not the sensing signal stored by the sensing capacitor 206, a transistor 208 is conducted so that charges are stored in a reset capacitor CR to serve as a reset value. Then, a pixel transmission switch TX and a sampling switch SHS are turned on in sequence, such that the transistor 208 is conducted according to the sensing signal and the charges are stored in a sampling capacitor CS to serve as a sampling value. When the reset values and the sampling values are read, an average reference voltage signal switch set ARVS may respectively control a terminal of the reset capacitor CR and the sampling capacitor CS to respectively connect a reference voltage VREF with the switches SW2 and SW1, thereby eliminating non-ideal factors such as dark current. Finally, a switch CB is conducted and a column selection circuit CSC controls a switch in the corresponding column to be turned on, such that the difference between the reset values and the sampling values stored in the corresponding reset capacitor CR and the corresponding sampling capacitor CS are transmitted to the differential amplifier 110 for the following processes.
However, because the image sensor 20 does not comprise the reference pixel array 120 for the pixel readout circuit 200 or the image signal processor 114 to compensate for random noises, and because merely a capacitor CB is added at an input terminal of the bias reference voltage BIAS within a bias circuit 210 of the pixel readout circuit 200 to prevent the random noises of the bias circuit 210 from entering the pixel readout circuit 200, row noises may still remain if any other external electrical potential brings random noises into the image.
Besides, please refer to FIG. 3, which is a schematic diagram illustrating an image sensor 30 which embodies the image sensor 10 in the prior art. Since the image sensor 30 is partially similar to the aforementioned image sensor 20, the same numerals and symbols denote components and signals of similar functions in FIG. 3 and the following description. The main difference between the image sensor 30 and the image sensor 20 is that the image sensor 30 further comprises the reference pixel array 120, which comprises the reference pixel rows RR1-RRn and the reference pixel columns Cm+1-Cm+k. A pixel readout circuit 300 further comprises the sample-and-hold circuits SHCm+1-SHCm+k respectively corresponding to the reference pixel columns Cm+1-Cm+k in the reference pixel array 120. The reference pixel columns Cm+1-Cm+k are disposed after the last pixels of the image pixel columns C1-Cm—namely, the reference pixel rows RR1-RRn are disposed after the image pixel rows R1-Rn. The pixel 202 may also be any reference pixel of the reference pixel array 120, only that the reference pixel is shielded against light and does not sense light during the image sensing process. The sample-and-hold circuits SHCm+1-SHCm+k and the sample-and-hold circuits SHC1-SHCm have identical structure.
In this structure, during the image sensing process, the image pixel array 116 is exposed to light and the optical-black-area pixel array 118 and the reference pixel array 120 are shielded against light or set as the non-light-sensing pixel. The pixel readout circuit 300 then utilizes the sample-and-hold circuits SHC1-SHCm and SHCm+1-SHCm+k to respectively read the image pixel rows R1-Rn and the reference pixel rows RR1-RRn row by row, such that the corresponding reset values, the corresponding sampling values, the corresponding reference reset values and the corresponding reference sampling values are obtained by means of the method similar to that of the pixel readout circuit 200 mentioned above. Then, the differences between the reset values and the sampling values and the differences between the reference reset values and the reference sampling values are amplified, converted from analog to digital form and processed by the differential amplifier 110, the analog-to-digital converter 112 and the image signal processor 114. In this case, when the image signal processor 114 performs image signal process, the average of the differences of the reference reset values and the reference sampling values of the pixels corresponding to the specific reference pixel row in the corresponding reference pixel rows RR1-RRn is subtracted from the differences of the reset values and the sampling values of the pixels of the corresponding specific image pixel row in the image pixel rows R1-Rn by the digital approach so as to eliminate the disturbance of external electrical potential owing to random noises.
Moreover, in the U.S. Pat. No. 8,310,569, each of the sample-and-hold circuits further comprises an amplifier, and the corresponding average capacitor replaces the corresponding sample-and-hold circuit of the reference pixel column. The average capacitors may store charges by means of the method similar to that of reading the reset values and the sampling values illustrated above and generate an average reference voltage by averaging the charges to each amplifier so as to directly provide the average reference voltage to another terminal of the reset capacitor and the sampling capacitor by the analog approach, thereby eliminating the disturbance of external electrical potential owing to random noises.
In addition, in the U.S. Pat. No. 8,310,569, the reference pixel array merely further comprises reference pixels, and each of the reference pixels respectively corresponds to one of the image pixel columns. Subsequently, the pixel readout circuit may directly generate each of the corresponding reference voltages by means of the method similar to that of reading the reset values and the sampling values illustrated above so as to directly provide the reference voltages respectively to another terminal of the reset capacitor and the sampling capacitor by the analog approach, thereby eliminating the disturbance of external electrical potential owing to random noises.


An image projection system that communicates an image into the air includes screen material particles, a screen generation device, a delivery device and a light projecting system. The screen generation device disperses the screen material particles from the screen generation device at a targeted screen location, thereby forming a projection screen. The delivery device launches the screen generation device from a launch location to the targeted screen location in the air. The light projecting device projects light from a projection location onto the screen to form the image on the screen so as to be visible from an observation location of a viewer.

Several methods for producing images in the air are known. In skywriting, typically one or more airplanes disperse smoke from behind the airplane as it maneuvers. This trail of smoke forms the image as viewed by an observer. Atmospheric conditions will cause the smoke to disperse, limiting the complexity (e.g., size, shape, color) of images that may be formed using this technique. In addition, images formed from skywriting are not visible in the dark. The efficiency of a system is defined as the total time and cost necessary to display an image at a targeted location. Skywriting is relatively inefficient since it requires an airplane to take off, fly to an intended message position, and then create the image.
Cloud painting offers an alternative to skywriting. In cloud painting, typically a high-powered light is used to project an image onto an existing cloud where light reflects off the cloud toward the observer. Since the light source and observer are both on the same side of the imaging surface, we refer to this herein as front-projection. This technique is more efficient than skywriting and increases the complexity of the image that can be displayed. However, cloud painting can only project an image onto an existing cloud and therefore is not functional when the sky is clear. The ability to project an image at any location is defined as the flexibility of the system. An airplane can be used to produce a smoke cloud at an ideal location, thereby increasing flexibility, but at the expense of efficiency.
In addition, the brightness of the image is reduced as the light beam travels through the atmosphere due to scattering effects. Brightness is inversely proportional to the distance the beam traverses from the source to the observer. Therefore, the higher the altitude of the cloud, the dimmer the image will appear. Also, the higher the altitude of the cloud, the larger the projected image needs to be to appear as the same size when projected on a lower altitude cloud. To form a larger image, the light source must be spread over a larger area, resulting in a further reduction of brightness. Available light sources are not bright enough to compete with direct sunlight, and therefore cloud painting is typically not possible during daylight conditions.
An alternative to cloud painting is image projection onto a water screen. In general, a water screen is produced by spraying a controlled stream of water droplets or water vapor into the air to form a thin screen. To maintain the screen, a continuous supply of water is necessary, along with an apparatus to control the size and position of the water droplets. Water screens suffer from similar flexibility and efficiency constraints as cloud painting.

Apparatus for and method of delivering visual image into air

Alion Science and Technology Corporation


A processor execution pipeline that includes, a stage latch circuit and a stage latch circuit provided at an input stage of a first processing stage for holding a first processing data SOURCE1 and a second processing data, respectively; an operator provided at the first processing stage for executing a processing by using the first processing data SOURCE1 and the second processing data; a stage latch circuit provided between the first processing stage and a second processing stage for holding an output value of the operator; an operator provided at the second processing stage for executing the processing by using a value of the stage latch circuit when an instruction has been decoded; and an instruction decoder that decodes the instruction to the operator as a through instruction to pass the value of the stage latch circuit through this operator.

As microprocessors that achieve high-speed processing, pipeline operators that use pipeline processing have been used. The pipeline processing employs a method of overlapping the processing of a plurality of instructions by delaying the starting time of the execution of each instruction one clock by one clock, thereby achieving the execution of the instructions at an equivalent high speed. Before installing a pipeline operator into a computer system, the installation area, power consumption, and price of the pipeline operator are important factors that need to be examined. The pipeline operator must meet compactness, low power consumption, and low price as essential conditions.
FIG. 27 is a diagram that shows a structure of a conventional pipeline operator. The pipeline operator shown in this drawing has two processing stages of a first processing stage and a second processing stage. An operator 221 and an operator 122 to be described later are provided at the first processing stage and the second processing stage respectively. A processing-data register 10 is provided corresponding to a pipeline path P10, and holds a first processing data (source operand). A processing-data register 20 is provided corresponding to a pipeline path P20, and holds a second processing data (source operand). An instruction register 30 is provided corresponding to an instruction pipeline path P30, and holds an instruction INST1 and an instruction INST2. The instruction INST1 is a processing instruction dispatched to the operator 221, and the instruction INST2 is a processing instruction dispatched to the operator 122.
Further, according to the conventional pipeline operator, a plurality of stage latch circuits for temporarily holding data and instructions are provided at an input stage of the two processing stages, between the first processing stage and the second processing stage (inter-processing stage), and at an output stage of the two processing stages, respectively. Specifically, a stage latch circuit 111, a stage latch circuit 211 and a stage latch circuit 311 are provided in parallel at the input stage. A stage latch circuit 112, a stage latch circuit 212 and a stage latch circuit 312 are provided in parallel between the processing stages, and a stage latch circuit 113 is provided at the output stage. The stage latch circuit 111 and the stage latch circuit 112 are sequentially driven in one clock cycle in such a order of the input stage→the processing stage→the output stage.
At the first processing stage, the stage latch circuit 111 is provided corresponding to the processing-data register 10, and holds the first processing data from the processing-data register 10. The stage latch circuit 211 is provided corresponding to the processing-data register 20, and holds the second processing data from the processing-data register 20. The stage latch circuit 311 is provided corresponding to the instruction register 30, and holds the instruction INST1 and the instruction INST2 from the instruction register 30. The instruction decoder 32, decodes the instruction INST1 from the stage latch circuit 311. When the instruction INST1 has been decoded, the operator 221 executes the processing according to the instruction INST1 by using the value (the first processing data) of the stage latch circuit 111 and the value (the second processing data) of the stage latch circuit 211. Then, the operator 221 outputs the result of the processing to the stage latch circuit 212 through the pipeline path P20.
At the second processing stage, the stage latch circuit 112 is provided corresponding to the processing-data register 10, and holds the value of the stage latch circuit 11, (the first processing data). The stage latch circuit 212 is provided corresponding to the processing-data register 20, and holds the result of the processing by the operator 221. The stage latch circuit 312 is provided corresponding to the instruction register 30, and holds the values of the stage latch circuit 311 (instruction INST1 and the instruction INST2). The instruction decoder 322 decodes the instruction INST2 from the stage latch circuit 312. When the instruction INST2 has been decoded, the operator 122 executes the processing according to the instruction INST2 by using the value (the first processing data) of the stage latch circuit 112, and outputs the result of the processing through the pipeline path P10.
A multiplexer 402 is a two-input and one-output type changeover unit whose changeover is controlled by the instruction decoder 322. The multiplexer 402 outputs one of the processing result of the operator 122 and the value of the stage latch circuit 212 (the processing result of the operator 221). Specifically, the multiplexer 402 outputs the processing result of the operator 122 when the instruction INST2 has been decoded by the instruction decoder 322. On the other hand, the multiplexer 402 outputs the value of the stage latch circuit 212 when the instruction other than the instruction INST2 (for example, the instruction INST1) has been input to the instruction decoder 322. The stage latch circuit 113 holds the processing result of the operator 122 or the value of the stage latch circuit 212 (the processing result of the operator 221) according to the changeover state of the multiplexer 402. A processing-result register 50 holds a value of the stage latch circuit 113, that is, a processing result (a destination operand) of the pipeline operator.
The operation of the conventional pipeline operator will be explained here. The operation when the instruction INST1 has been dispatched will be explained first. At the first clock, the first processing data, the second processing data and the instruction INST1 are held in the processing-data register 10, the processing-data register 20 and the instruction register 30 respectively. At the next clock, the first processing data, the second processing data and the instruction INST1 are held in the stage latch circuit 111, the stage latch circuit 211 and the stage latch circuit 311 respectively. Then, the instruction decoder 321 decodes the instruction INST1 from the stage latch circuit 311. The operator 221 executes the processing according to the instruction INST1 by using the value (the first processing data) of the stage latch circuit 111 and the value (the second processing data) of the stage latch circuit 211.
At the next clock, the value (the first processing data) of the stage latch circuit 111, the processing result of the operator 221 and the value (the instruction INST1) of the stage latch circuit 311 are held in the stage latch circuit 112, the stage latch circuit 212 and the stage latch circuit 312 respectively. In this case, as the value (instruction INST1) of the stage latch circuit 312 is irrelevant to the instruction according to the operator 122, the instruction decoder 322 makes the multiplexer 402 select the stage latch circuit 212.
At the next clock, the value (the processing result of the operator 221) of the stage latch circuit 212 is held in the stage latch circuit 113 through the multiplexer 402. As a result, the processing-result register 50 holds the processing result of the operator 221 as the processing result of the pipeline operator.
The operation when the instruction INST2 has been dispatched will be explained next. At the first clock, the first processing data, the second processing data and the instruction INST2 are held in the processing-data register 10, the processing-data register 20 and the instruction register 30 respectively in the similar manner to that of the above operation. At the next clock, the first processing data, the second processing data and the instruction INST2 are held in the stage latch circuit 111, the stage latch circuit 211 and the stage latch circuit 311 respectively. In this case, as the value (instruction INST2) of the stage latch circuit 311 is irrelevant to the instruction according to the operator 221, the instruction decoder 321 does not decode the instruction. Therefore, the operator 221 executes no processing in this case.
At the next clock, the value (the first processing data) of the stage latch circuit 111 and the value (the instruction INST2) of the stage latch circuit 311 are held in the stage latch circuit 112 and the stage latch circuit 312 respectively. In this case, the instruction decoder 322 decodes the instruction INST2 from the stage latch circuit 312, and at the same time, makes the multiplexer 402 select the operator 122. As a result, the operator 122 executes the processing according to the instruction INST2 by using the value (the first processing data) of the stage latch circuit 112.
At the next clock, the processing result of the operator 122 is held in the stage latch circuit 113 through the multiplexer 402. As a result, the processing-result register 50 holds the processing result of the operator 122 as the processing result of the pipeline operator.
As explained above, as shown in FIG. 27, the conventional pipeline operator is provided with the stage latch circuit 112 for holding the first processing data (source operand) from the processing-data register 10. Furthermore, the pipeline operator is provided with the stage latch circuit 212 for holding the processing result of the operator 221, independent of the stage latch circuit 112. In this structure, the first processing data held in the processing-data register 10 is input to the operator 122 through the stage latch circuit 111 and the stage latch circuit 112. On the other hand, the processing result of the operator 221 is input to the multiplexer 402 through the stage latch circuit 212.
According to the conventional pipeline operator, because the stage latch circuit 11, and the stage latch circuit 212 are provided independent of each other between the first processing stage and the second processing stage, as explained above, the circuits (the stage latch circuits, the wiring and the control circuits) have redundant structures. Accordingly, the conventional pipeline operator poses a problem because it requires a large scale of hardware, and as a result has high power consumption.

Processor execution, pipeline sharing instruction, and data source path


An engine of a vehicle is provided with an engine control device including an idle speed control (ISC) device provided for an intake bypass passage connecting an upper side and a lower side of a throttle valve installed in an intake passage so as to control an idle speed of the engine by adjusting an amount of air flowing through the intake bypass passage at a time of idling of the engine. The engine control device includes a throttle opening degree sensor disposed in the intake passage and configured to detect a degree of opening of the throttle valve, an intake pressure sensor disposed in the intake passage and configured to detect an intake negative pressure at the lower side of the throttle valve, and a control unit configured to control an output of the engine. The control unit is configured to perform an engine output suppression control of suppressing the output of the engine after determining that an ISC valve of the ISC device is abnormal in a case where the degree of opening of the throttle valve detected by the throttle opening degree sensor is within a predetermined range and when the intake negative pressure detected by the intake pressure sensor is low compared with a threshold value.

1. Field of the Invention
The present invention relates to a device for controlling an engine including an ISC (idle speed control) device for controlling the idle speed of the engine and also relates to a method of controlling such engine.
2. Description of the Related Art
As a conventional engine, there is known an engine including an ISC device that controls the idle speed to be at a target speed by having an upper side and a lower side of a throttle valve installed in an intake passage connected by an intake bypass passage. The ISC device includes an ISC valve disposed in the intake bypass passage so as to adjust the amount of air flowing through the intake bypass passage by the ISC valve at the time of idling.
With a vehicle on which an engine including such an ISC device is mounted, an ISC valve of the ISC device may become fixed (adheres) at an open state due to a short circuiting of wirings, carbon deposit or the like on the ISC valve. In a state where the ISC valve is fixed, the amount of intake air into the engine increases compared to a normal state (non-fixed state), and thus, the idle speed of the engine increases. As a result, there is a possibility that an automatic centrifugal clutch is connected even if the throttle valve is completely closed, and that the vehicle is unintentionally started.
Accordingly, as described, for example, in Patent Document 1 (Japanese Patent Laid-Open Publication No. 60-11648), a technique is proposed of calculating in advance the basic amount of air that is based on the degree of opening of a throttle valve and the engine speed, and determining an abnormality in an ISC valve when a measurement value of the amount of actually measured engine air intake exceeds the basic amount of air.
Furthermore, as described in Patent Document 2 (Japanese Patent Laid-Open Publication No. 8-86266), there is provided a technique of calculating the actual amount of intake air flowing through an ISC valve by calculating the amount of intake air flowing through a throttle valve based on the degree of opening of the throttle valve and deducting the amount of intake air flowing through the throttle valve from the amount of intake air (a measurement value) of the entire mechanism, and determining an abnormality in the ISC valve in a case where there is a predetermined or greater deviation between the actual amount of intake air and the amount of intake air calculated based on a set degree of opening of the ISC valve.
The conventional techniques described in Patent Documents 1 and 2 are suitable when applied to a so-called L-jetronic fuel injection device that detects the amount of intake air into the engine by an air flow sensor, but are not suitable for a D-jetronic fuel injection device that detects an intake air pressure (an intake negative pressure) and decides the amount of fuel injection, because an air flow sensor has to be separately provided.
Generally, the D-jetronic fuel injection device is said to be more advantageous compared to the L-jetronic fuel injection device in a viewpoint such that, since the air flow sensor is unnecessary, an increase in the intake resistance can be prevented.
Furthermore, in contrast to the L-jetronic fuel injection device that decides the optimal amount of fuel injection after measuring the actual amount of intake air, the D-jetronic fuel injection device decides the amount of fuel injection by measuring a change in the intake negative pressure that causes a change in the amount of intake air, and thus, it is also advantageous in that it has good responsiveness for the output change with respect to a throttle operation.
For these reasons, the D-jetronic fuel injection device is widely used in motorcycles and all terrain vehicles and, accordingly, it is difficult to apply the conventional technique described in Patent Document 1 or 2 to motorcycles and all terrain vehicles.

Engine control device and engine control method


A process for working up the hydrogen fluoride phase of reaction mixtures from fluorination reactions comprising contacting the hydrogen fluoride phase with oleum in order to obtain dried hydrogen fluoride, which can be recycled to the fluorination reaction.

The present invention relates to a process for working up the hydrogen fluoride phase of reaction mixtures from fluorination reactions.
Fluorine-containing hydrocarbons are produced on a large scale by reacting halogenated hydrocarbons with hydrogen fluoride. Usually one starts with chlorine-containing hydrocarbons. In addition to fully halogenated carbon compounds, compounds which also contain hydrogen in addition to fluorine (and optionally chlorine) may of course also be used or produced. Alkenes may for instance also be used as starting materials for the preparation of fluorine-containing hydrocarbons, so that hydrogen fluoride addition also takes place. Compounds of this type have become important as replacements for fully halogenated carbon compounds.
A process of this type is described in published German Patent Application No. DE 4,005,945. Ethane derivatives containing trifluoromethyl groups, such as CF.sub.3 CHCl.sub.2, are prepared from halogen-containing alkenes or alkanes, with a halogen-fluorine exchange and optionally addition of hydrogen fluoride. In the course of working-up the reaction mixture, volatile reaction products are first collected in a phase separator. In so doing, two separate phases are obtained. The heavy phase contains predominantly organic compounds, in particular the desired reaction product. The lighter phase contains predominantly hydrogen fluoride and water. The hydrogen fluoride phase is recycled to the fluorination reaction. Any readily volatile constituents released in the phase separator are passed through a gas scrubber. The disadvantage of this process is that the water contained in the hydrogen fluoride phase is recycled.

Process for working up a hydrogen fluoride phase from a fluorination reaction mixture


The present invention relates to a method and an apparatus for a loading test of a pile using a self-repulsive force. The loading test is separately performed in two stages, a first stage to estimate the ultimate peripheral skin friction force and a second stage to estimate the ultimate tip end bearing capacity. The loading test apparatus of the present invention has simple construction capable of reusing, which results in carrying out the loading test with ease and in cost effective manner.

1. Field of the Invention
The present invention relates to a method and an apparatus for a loading test of a pile using a self-repulsive force, i.e. the peripheral skin friction between the pile wall and the surrounding ground as the force required to cause the pile tip settlement, and more particularly to a method and an apparatus to carry out the loading test in which both a peripheral skin friction resistance and a tip end bearing capacity can be determined with ease and in a cost-effective manner.
2. Description of the Prior Arts
In general, there have been known three types of loading test methods, one type is to apply the load directly to a test pile, another type is to apply a load box or a load frame onto a test pile by means of a hydraulic jack, and a third type is to utilize a peripheral skin friction of the neighboring piles as the load causing the test pile settlement.
FIG. 1 illustrates a first method that a load is applied directly to a test pile 11. As shown in FIG. 1, a load box 12 is laid on an upper end of a test pile 11 filled with soil, sand, cement, wire, or given material. Balks 13 and I-shaped beams 14 are laid down sequentially under the load box 12, and then a loading test is carried out.
Referring to FIG. 2, a second method is carried out in such a manner that a load box or a load frame 22 supported by balks 23a and 23b is laid on a test pile 21, and I-beams 24 are disposed between the balks 23a and 23b. A test load more than expected maximum design load is applied to the load box 22. And then, a hydraulic jack 25 provided with a pressure gauge (not shown) is inserted between an upper end of the test pile 21 and the load box 22 to apply a load to the test pile 21 during a loading test.
Referring to FIG. 3, a third method for a loading test is carried out in such a manner that two reaction piles 33a and 33b or more are driven into the ground with a prescribed depth from the test pile 31. A reaction beam 34 having a stength enough to endure the axial force and the bending moment during the loading test is fixedly mounted on the upper ends of the reaction piles 33a and 33b. And then, a hydraulic jack 35 provided with a pressure gauge (not shown) is inserted between the upper end of the test pile 31 and the lower surface of the reaction beam 34 to apply a test load to the test pile 31 during the loading test.
However, in such conventional loading test methods, there have been raised some problems that it is difficult to use such methods because numerous structural components are required for the loading test and further they should be assembled one by one. Also, it needs prescribed time for curing the concrete in case that a concrete pile is used as a test pile. Furthermore, according to the conventional methods as mentioned above, only the combined forces i.e., summation of tip end bearing capacity and peripheral skin friction force can be measured. According to the known behavior of a pile, the majority of the applied load is supported by the peripheral skin friction force at the early stage of loading test, whereby it is impossible to apply the concept of the safety factor based on the actual load transferring mechanism of the pile in the conventional methods.

Method and apparatus for a loading test of a pile using a self-repulsive force


Electronic messages are sent from a sending system to an identified recipient and are encoded using information contained in a certificate. A key store is accessed by a messaging application to determine if a certificate associated with the recipient is present. If no certificate is present in the key store the messaging application accesses one or more certificate services to obtain a certificate. Where validation of the retrieved certificate is required, the messaging application invokes a certificate validation process. One or more further certificates are obtained by the messaging application where the retrieved certificate is invalid.

1. Technical Field
The present invention relates generally to the field of communications, and in particular to a system and method for sending secure messages.
2. Description of the Related Art
Messages sent over communications networks are typically encoded in order to provide one or more cryptographic services such as authentication, encryption and non-repudiation. A message sender may digitally sign a message prior to transmission to a message recipient in order to authenticate the sender to the recipient, and to prove to the recipient that the message was not tampered with during transmission. The sender may also encrypt the message in order to prevent unauthorized viewing of the message by a party other than the recipient. In known systems, certificates are issued to users in order to support such cryptographic services. The certificates comprise information that may be used in algorithms that provide cryptographic services. For instance, the certificate may comprise information such as a public key for a user and a validity period for the certificate.
When the sender sends the message to one or more recipients, a messaging application, such as Microsoft Outlook™ or Lotus Notes™, retrieves the certificates for the recipients, and encodes the message to each recipient using information extracted from the certificates. As an example, the messaging application may use public key information extracted from the certificate in order to encrypt the message to the recipient.
Certificates may be stored in a Key Store that applications access in order to retrieve the certificates. If the certificate is not available in the Key Store, the sender may not be able to send the message until the certificate is made available. In order to do this, the sender has to retrieve the required certificates prior to sending the message. If the message has already been composed, the sender has to invoke a secondary application in order to retrieve the certificates, and then return to the messaging application in order to send the message.
The certificates may also become invalid over time. For instance, they may be revoked if certain information, such as the private key associated with the certificate, becomes compromised. They may also simply expire. If the message is encoded with an invalid certificate, recipients may not be able to authenticate the sender or be able to decrypt the message if it was signed or encrypted with a private key that is associated with an invalid public key.

System and method for sending secure messages


When data read by a scanner or the like is to be displayed on the screen of a display device, the present invention is an electronic filing apparatus that uses either simple decimation processing or OR decimation processing depending upon whether the image data is images of character and line images, or dither images such as photographs, and performs the multiple processing suitable for the type of image, and uses a method whereby the multiple processed image data is stored in an optical disk or the like, a method where only the data compressed source image data is preserved in an optical disk, specifies the type of data of the image data from a keyboard for the type of data stored in the storage device and performs read from the storage device, multiple processing depending upon the type of data, transfers the converted data to a video memory, decodes that image data in accordance with the necessity of referral and display, and displays it on the display apparatus.

The present invention relates to an improved electronic filing apparatus provided with a multiple (reduction and enlargement) processing function for when various types of image data are displayed in personal computers, office computers, word processors, desk type publishing, data processing and the like.
In particular, the present invention judges whether source image data is a character and line image or a dither image such as a photograph and the like when source image data read by an image scanner into a CRT (cathode ray tube) or the like having a different degree of resolution, is multiplied and displayed and performs multiple processing using an optimum decimating method, and relates to an electronic filing apparatus for displaying an image by means of an optimum multiple processing method corresponding to the type of simultaneously read source image data.
An image data processing system for a conventional personal computer or the like uses an image scanner or the like to read image data of documents that are the object for filing display. The source data is image data that has given data compression processing and converted into binary image data. The converted image data is stored in a storage device such as an optical disk or the like and is read from the storage device in accordance with the necessity of referral or display, and is displayed on the display screen of a display means such as a CRT or the like after processing to decode the data.
The binary image data that has been read by an image scanner is stored in an image memory, and at the same time, multiple processing is performed so as to correspond to the degree of display resolution so that it can be displayed on the display screen of a display means such as a CRT or the like and transferred to the video memory.
The reason for the multiple processing described above is because it is necessary to have multiple processing corresponding to respective display devices when all binary image data read by an image scanner is to be displayed by a display means such as a CRT or the like.
The following is a description of an electronic filing apparatus using a conventional method. In this example, the description will include using a personal computer to perform read of image data from a document, the reading of the image data, the performing of multiple processing for the read image, and the final display on a CRT.
FIG. 1 is a functional block diagram showing the configuration of the major portions of an electronic filing apparatus using a conventional method. The major portions described here are an image scanner 1, an image data processing portion 2 and a display portion 3. Of these, the image data processing portion 2 comprises an image memory 2a, a multiple processing portion 2b, a video memory 2c and a disk apparatus 2d.
The image scanner 1 reads the image data into the image data processing portion 2. The image data is stored in the image memory 2a of the image data processing portion 2.
Here, for example, the degree of resolution of binary image data read by the image scanner 1 is 300.times.300 (dpi: dots per inch). When this image data is output to the display portion 3 (CRT), it is necessary to perform multiple processing to 1/(3.times.3). The multiple processing of this image data is performed by the multiple processing portion 2b. The image data for which multiple processing has been performed is transferred to the video memory 2c. This data is then displayed on the display portion 3. FIG. 2 is a flowchart for the multiple processing when there is image data display for a conventional electronic filing apparatus.
First, the (300 dpi) document image data is read by an image scanner 1 (step 201). The read image data is then stored in an image memory 2a of a image data processing portion 2 (step 202). Then, the 300 dpi image data stored in the image memory 2a is multiple processed to a display resolution of 100 dpi by either the simple decimation method or the OR decimation method (step 203). The image data that is multiple processed in step 203 is transferred to the video memory 2c and stored (step 204). It is then displayed on the CRT of the display portion 3 (step 205). The image data multiple processing of the steps 201 through 205 described above then ends.
In conventional multiple processing, either the simple decimation method or the OR decimation method is used to perform the multiple processing. In the case of simple decimation processing, when the degree of resolution is reduced by a multiple of 1/n, the n (dots).times.n (lines) of the source image data is created as data where single dots (or lines) of the image data are sampled and multiple processed to create the data. This simple decimation processing has simple multiple processing and has the merit that it can be executed in a short time. However, when the source data is continuous data such as characters or line images, fine portions are chopped and there is the problem that there are portions which are not displayed on the screen of the CRT.
On the other hand, with OR decimation processing, the data having n (dots).times.n (lines) of the source image data has single dots (or single line) calculated by OR arithmetic and multiple processing performed to create the data. This processing method differs from the simple decimation processing described above in that there is no chopping of the fine portions of characters or line images. However, when photographic images (dither images) in which the source image data uses the dither method, all of the image data for display after OR decimation processing becomes blacker (as the image is destroyed) and so it is not suitable for display on a screen.
Each of the processing methods therefore has its respective disadvantages and normally only one of the two types of multiple processing is suitable for a single electronic filing system. It is only possible for a device to be designed so that it can use only one multiple processing method. Since only one decimation processing method can be used whether the image data read by an image scanner is character, line image or some other image, or whether it is a photograph (dither image) and so it is not possible to obtain the optimum display corresponding to the type of the read image data.

Electronic filing apparatus provided with a multiple processing function when image data is displayed


A motor driving apparatus has first, second, and third positive-side driving transistors having drains which are supplied with a power supply voltage, first, second, and third negative-side driving transistors having sources which are grounded and drains which are connected to sources of the first, second, and third positive-side driving transistors, respectively, a power supply monitoring circuit which monitors the power supply voltage and outputs a driving mode switching signal which has a first value if the power supply voltage is not less than a predetermined value and has a second value if the power supply voltage is less than the predetermined value, and an output PWM control section which switches a mode of driving from synchronous rectification PWM driving to one-way PWM driving on the basis of a change of the driving mode switching signal from the second value to the first value.

1. Field of the Invention
The present invention relates to a motor driving apparatus, a brushless motor, and a method for driving the brushless motor.
2. Related Art
In a brushless motor widely used in electrical apparatuses as a motor, the position of a rotor which includes a permanent magnet is detected by a plurality of position detectors (e.g., Hall elements) which are arranged at regular intervals near the rotational orbit of the rotor, and the rotor is rotatively driven by switching the energization statuses of a plurality of driving coil windings in synchronism with changes in detected signals between the on and off states. For example, a three-phase brushless motor is generally configured to include three coil windings and generate a rotational torque by repeating switching of the energization statuses of two of the three coil windings.
As a motor driving apparatus which switches the energization statuses (voltage application statuses) of three driving coils of a three-phase brushless motor, there is proposed one including a power supply, a switching circuit which is provided between power supply lines and connected to driving coils, a PWM control section which switches the mode of driving between synchronous rectification PWM driving and one-way PWM driving using a decelerating signal for speed control, a pulse width modulating section, a position detecting section, and an energization switching section (see, e.g., Japanese Patent Laid-Open No. 2002-272162).
In the switching circuit, series circuits of an upper transistor and a lower transistor are provided as switching elements corresponding to three phases. A diode for protection against counter electromotive force is connected in parallel with each transistor. One ends of three driving coils are respectively connected to connection points between the upper transistors and the lower transistors, and the other ends are commonly connected. Drains of the three upper transistors are commonly connected, and sources of the three lower transistors are commonly connected.
The position detecting section detects the positional relationship between a rotor magnet and the driving coils. The energization switching section outputs an energization switching signal to the driving coils on the basis of an output from the position detecting section. The pulse width modulating section outputs a frequency signal with a pulse width corresponding to a torque command signal for controlling a torque generated by a brushless motor. The PWM control section performs on/off control of the transistors of the switching circuit on the basis of an energization switching signal and a signal output from the pulse width modulating section.
The operation of the aforementioned motor driving apparatus will be described. The three driving coils will be referred to as driving coils A, B, and C. The upper transistor, to which one end of the driving coil A is connected, will be referred to as a transistor TAu while the lower transistor, to which the one end of the driving coil A is connected, will be referred to as a transistor TAd. Similarly, the upper and lower transistors, to which one end of the driving coil B is connected, will be referred to as transistors TBu and TBd, respectively, while the upper and lower transistors, to which one end of the driving coil C is connected, will be referred to as transistors TCu and TCd, respectively.
When the driving coils A and B are energized, the transistor TAu is turned on, the transistor TAd is turned off, and the transistors TBu and TBd perform on-off operation in synchronous rectification PWM driving, except during a torque command-based decelerating period such as when in a steady state. PWM stands for Pulse Width Modulation and is a method for controlling power by changing the duty ratio (the ratio of the on time) of pulses for driving a motor. To cause both the upper and lower transistors to perform PWM operation is referred to as synchronous rectification PWM driving. When the transistor TBu is on, the transistor TBd is off. On the other hand, when the transistor TBu is off, the transistor TBd is on.
During a torque command-based decelerating period, turning on or off of the transistor TBd does not cause the transistor TBu to be turned on or off. Accordingly, when the transistor TBd is off, a regenerative current flows through the diode connected in parallel with the transistor TBu. This is referred to as one-way PWM driving. In the case of synchronous rectification PWM driving, during a decelerating period, the pulse width (duty ratio) for PWM driving decreases. A current flowing backward from the driving coils to a power supply may increase a power supply voltage and cause device breakdown. Switching of the mode of driving to one-way PWM driving in accordance with a decelerating signal for speed control makes the driving efficiency lower than that in synchronous rectification PWM driving but makes it possible to prevent device breakdown.
As described above, except during a torque command-based decelerating period such as when in a steady state, the motor driving apparatus prevents a current from flowing through the diodes for protection against counter electromotive force and can implement low-loss driving. During a decelerating period, the motor driving apparatus prevents a current from flowing backward to the power supply and prevents device breakdown.
A rise in power supply voltage caused by a current flowing backward to a power supply varies depending on the impedance of the power supply. A rise in voltage decreases with a decrease in power supply impedance. If another circuit is connected to the power supply, and the power supply impedance apparently becomes low, a rise in voltage becomes small. A rise in voltage also becomes small depending on a decrease in the speed or the number of revolutions of a motor and may not lead to device breakdown. However, the aforementioned motor driving apparatus switches between synchronous rectification PWM driving and one-way PWM driving using a decelerating signal for speed control. Accordingly, whenever a deceleration command is issued, the motor driving apparatus switches to one-way PWM driving even if a rise in voltage stops short of leading to device breakdown, and the driving efficiency decreases.

Motor driving apparatus, brushless motor, and method for driving the same