The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

The use of programmable variable resistance materials in electronic devices is known in the art. The chalcogenides are an important class of programmable variable resistance materials. The principles of operation of chalcogenide (and phase change) materials and devices are described in U.S. Pat. Nos. 5,296,716, 5,341,328, 5,359,205, and 7,227,170, all to Ovshinsky et al., which are incorporated herein by reference. These patents are believed to evidence the state of the prior art and to represent current theory of operation and function of phase change materials and chalcogenide-based memories known to those skilled in the art.
Briefly, variable resistance materials are materials that can be caused to change physical or electronic state, and therefore resistivity level, in response to an electrical input stimulus. By way of example, phase-change materials (many chalcogenide) may be electrically stimulated to transform among structural states ranging from a predominantly crystalline state to a predominantly amorphous state. By controlling the amount of electrical energy applied to a chalcogenide phase-change material, the relative proportions of crystalline and amorphous phase content can be continuously varied from a low crystalline phase volume fraction to a high crystalline phase volume fraction. The resistivity of a chalcogenide phase-change material correlates with the crystalline phase volume fraction and progressively decreases as the crystalline phase volume fraction increases. A chalcogenide phase-change material may be predictably placed in a particular resistivity state by running a current of a certain amperage for a certain duration through it. The resistivity state so fixed will remain unchanged unless and until a current having a different amperage or duration within the programming range is run through the material.
Because of these unique characteristics, variable resistance memory materials may be used in memory cells for storing data in binary or higher-based digital systems. Such memory cells will normally include a memory element that is capable of assuming multiple, generally stable, states in response to the application of a stimulus. In most cases, the stimulus will be a voltage differential applied across the element so as to cause a predetermined current to flow through the memory element. A chalcogenide-based memory cell will typically include a chalcogenide memory element utilizing a chalcogenide phase-change material for storing data and an access element, coupled to the memory element, for use in programming and sensing the stored data. The access element may be, in one embodiment, a diode.
To achieve high density storage of data, memory arrays comprising a multitude of chalcogenide memory elements may be fabricated. In a memory array, a grid of conductive row lines (wordlines) and column lines (digit lines or bit lines) is formed in which a series combination of an access element and a chalcogenide memory cell is located at each junction of a row line and column line. The row lines and columns lines are connected to external circuitry (such as drivers or sense amplifiers) and individual memory cells are programmed or read by selective application of voltages to the row line and column line between which the memory cell is interconnected. Selection of the row line and column line of a particular memory cell produces a voltage differential that activates the access element, thus enabling current to pass through the memory element. Access elements at non-selected junctions of the array prevent stray current from altering the state of memory elements located at non-selected junctions.
Because of the unique operating characteristics of memories based on variable resistance memory elements, control of current flow is crucial to facilitate programming. Programming of chalcogenide phase-change materials, for example, requires high current densities. In this regard, it is desirable that a chalcogenide-based memory cell include a diode or other access element capable of permitting a large current flow in the forward direction to program the memory cell. Conventional junction diode structures that are capable of supplying the necessary current require a significant number of complex processing steps to create compared to a deposited thin film diode. Accordingly, there is a need for a stable and easily manufactured access device that can meet the performance requirements of chalcogenide-based memory cells, while permitting fabrication of small footprint devices with minimal added processing steps to achieve a cost effective high density memory arrays.

Self-aligned memory cells and method for forming


A light emitting diode (“LED”) lighting apparatus has vents to cool the LED lighting apparatus. The LED lighting apparatus comprises one or more strips, a base having vents, and one or more glass tubes. Each strip has LEDs and a transparent backing. The vents comprise a central vent and side vents, were the central vent and certain ones of the side vents are connected to allow for gas flow. The one or more strips and the one or more glass tubes are coupled to the base, where the one or more glass tubes encapsulate the one or more strips. The central vent is disposed adjacent to the one or more glass tubes, and a heat transfer medium within selected ones of the one or more glass tubes flows out of the selected ones of the one or more glass tubes for cooling.

A light emitting diode ("LED") is a semiconductor light source, which has a longer lifetime, faster switching, smaller physical size, greater durability and higher energy efficiency than current day lighting devices, e.g., fluorescent lights bulbs or incandescent light bulbs. When an LED is forward biased, electrons (negative charges) recombine with holes (positive charges), releasing energy in the form of photons. The energy difference between the electrons and holes of the LED produces photons of different wavelengths. Certain wavelengths provide for specific visible colors. Thus, the LED does not require color filters to produce any specific colors.
Generally, LEDs are solid state devices, and if operated at low currents and at low temperatures, are subject to limited device wear and tear. Lifetimes of LEDs are anywhere from around five to fifty times longer than fluorescent light bulbs and incandescent light bulbs. LEDs are also less susceptible to damage than fluorescent and incandescent light bulbs.
LEDs produce more light per watt than incandescent bulbs, and are ideal for use in applications that are subject to frequent on-off cycling, unlike fluorescent lamps that burn out more quickly when cycled frequently. LEDs can very easily be dimmed continuously unlike fluorescent lamps which require a certain threshold voltage to maintain illumination.
LEDs have been found to have significant environmental benefits compared to other alternatives. For instance, a building's carbon footprint from lighting can be significantly reduced by exchanging all incandescent bulbs for LED light bulbs. LEDs are also non-toxic compared to fluorescent light bulbs, which contain traces of mercury.
Performance of LEDs is temperature dependent, and LED light output can actually increase at lower temperatures. LEDs do not generate as much heat as incandescent bulbs, but LEDs do produce internal heat which must be dissipated if the LED is to maintain good performance and low temperatures. Conversely, over-heating LEDs can lead to major device failure.
In order to combat overheating of LEDs, LED lights have incorporated heat sinks to dissipate heat generated by the LEDs. Heat sinks are widely available for LEDs, but any improvement in cooling can increase device operations and reliability. Some heat sinks are made by simply having a number of cooling fins connected to the LEDs. However, these designs are bulky, aesthetically unpleasing, and expensive to build LED light bulbs.
Therefore, it is desirable to develop new methods, systems, and apparatuses for cooling LED lighting (e.g., LED light bulbs, LED lamps, and other LED lighting apparatuses) to increase performance and maintain a long lifespan for the LEDs.


A CT scanner and method are designed to scan a preselected portion of a patient's lower abdomen. The scanner may include a source and detector array designed to rotate about a rotation axis oriented substantially parallel to or coincident with the hips of the a patient so that a scanning plane does not pass through the patient's pelvic bones Higher-resolution image CT images can be achieved by using a detector array of the type used for digital radiography. The presence of prostatic cancer can be detected by first injecting the patient with a material including a high contrast material for X-ray imaging and a material for binding the high contrast material to a specific biological site if present in the preselected portion of the lower abdomen of the patient; and generating a CT image of the preselected portion of the lower abdomen.

The invention relates generally to non-invasively imaging a preselect portion of the lower abdomen and groin area of a patient with X-rays, at relatively lower radiation dosages than currently used in, and improved resolution than currently achievable with, conventional Computed Tomography (CT) scanning.
Various physiological changes can occur in the lower abdomen region of a patient requiring diagnostic and imaging approaches to aid medical personnel in diagnosing, prognosticating, and managing or otherwise treating these changes.
For example, as described in U.S. Pat. No. 6,171,796 (An, et al.) entitled Biomarkers and Targets for Diagnosis Prognosis and Management of Prostate Disease, carcinoma of the prostate (PCA) is the second-most frequent cause of cancer related death in men in the United States (citing Boring et al., CA-Cancer J. Pract., 43:7-26, 1993; and Wingo et. al., CA Cancer J. Clin., 47(4):239-242, 1997). The increased incidence of prostate cancer during the 1980s has established prostate cancer as the most prevalent of all cancers (citing Carter and Coffey, Prostate, 16:39-48, 1990). Although prostate cancer is the most common cancer found in United States men, (approximately 210,000 newly diagnosed cases/year), the molecular changes underlying its genesis and progression remain poorly understood (citing Boring et al., CA-Cancer J. Pract., 43:7-26, 1993). According to American Cancer Society estimates, the number of deaths from PCA is increasing in excess of 8% annually.
An unusual challenge presented by prostate cancer is that most prostate tumors do not represent life threatening conditions. Evidence from autopsies indicate that an estimated 11 million American men have prostate cancer (citing Dbom, Cancer Res. Clin. Oncol., 106:210-218, 1983). These figures are consistent with prostate carcinoma having a protracted natural history in which relatively few tumors progress to clinical significance during the lifetime of the patient. If the cancer is well-differentiated, organ-confined and focal when detected, treatment does not extend the life expectancy of older patients.
Unfortunately, the relatively few prostate carcinomas that are progressive in nature are likely to have already metastasized by the time of clinical detection. Survival rates for individuals with metastatic prostate cancer are quite low. Between these two extremes are patients with prostate tumors that will metastasize but have not yet done so. For these patients, surgical removal of their prostates is curative and extends their life expectancy. Therefore, early detection and determination of which group a newly diagnosed patient falls within is critical in determining optimal treatment and patient survival.
The most commonly utilized current tests for prostate cancer are digital rectal examination (DRE) and analysis of serum prostate specific antigen (PSA). Although PSA has been widely used as a clinical marker of prostate cancer since 1988 (citing Partin and Oesterling, J. Urol., 152:1358-1368, 1994), screening programs utilizing PSA alone or in combination with digital rectal examination have not been successful in improving the survival rate for men with prostate cancer (citing Partin and Oesterling, J. Urol., 152:1358-1368, 1994). While PSA is specific to prostate tissue, it is produced by normal and benign as well as malignant prostatic epithelium, resulting in a high false-positive rate for prostate cancer detection (citing Partin and Oesterling, J. Urol., 152:1358-1368, 1994).
Other markers that have been used for prostate cancer detection include prostatic acid phosphatase (PAP) and prostate secreted protein (PSP). PAP is secreted by prostate cells under hormonal control (citing Partin and Oesterling, J. Urol., 152:1358-1368, 1994). It has less specificity and sensitivity than does PSA. As a result, it is used much less now, although PAP may still have some applications for monitoring metastatic patients that have failed primary treatments. In general, PSP is a more sensitive biomarker than PAP, but is not as sensitive as PSA (citing Huang et al., Prostate, 23: 201-212, 1993). Like PSA, PSP levels are frequently elevated in patients with benign prostatic hypertrophy or hyperplasia (BPH) as well as those with prostate cancer.
Another serum marker associated with prostate disease is prostate specific membrane antigen (PSMA) (citing Horoszewicz et al., Anticancer Res., 7:927-936, 1987; Carter et al., Proc. Nat'l Acad. Sci. USA 93: 749-753, 1996; and Murphy et al., Cancer, 78: 809-818, 1996). PSMA is a Type II cell membrane protein and has been identified as Folic Acid Hydrolase (FAH) (Carter et al., Proc. Nat'l Acad. Sci. USA 93: 749-753, 1996). Antibodies against PSMA react with both normal prostate tissue and prostate cancer tissue (citing Horoszewicz et al., Anticancer Res., 7:927-936, 1987). In the cited Murphy et al. publication (Prostate, 26:164-168, 1995) Murphy et al. used ELISA to detect serum PSMA in advanced prostate cancer. As a serum test, PSMA levels are a relatively poor indicator of prostate cancer. However, PSMA may have utility in certain circumstances. PSMA is expressed in metastatic prostate tumor capillary beds (citing Silver et al., Clin. Cancer Res., 3: 81-85, 1997) and is reported to be more abundant in the blood of metastatic cancer patients (citing Murphy et al., Cancer, 78: 809-818, 1996). PSMA messenger RNA (mRNA) is down-regulated 8-10 fold in the LNCAP prostate cancer cell line after exposure to 5-.alpha.-dihydroxytestosterone (DHT) (citing Israeli et al., Cancer Research, 54:1807-1811, 1994).
A relatively new potential biomarker for prostate cancer is human kallekrein 2 (HK2) (citing Piironen et al., Clin. Chem. 42: 1034-1041, 1996). HK2 is a member of the kallekrein family that is secreted by the prostate gland. In theory, serum concentrations of HK2 may be of utility in prostate cancer detection or diagnosis, but the usefulness of this marker is still being evaluated.
U.S. Pat. Nos. 6,171,796 (An, et al.) and 6,090,559 (Russell, et al.) describe other biomarkers and targets for diagnosis prognosis and management of prostate disease.
As described in U.S. Pat. No. 6,136,311 (Bander), at the time of clinical diagnosis, as many as 25% of patients have bone metastasis demonstrable by radionuclide scans. Murphy, G. P., et al., "The National Survey Of Prostate Cancer In The United States By The American College Of Surgeons," J. Urol., 127:928-939 (1982). Accurate clinical evaluation of nodal involvement has proven to be difficult. Currently available imaging techniques such as computed tomography ("CT") or magnetic resonance imaging ("MRI") are unable to distinguish metastatic prostate cancer involvement of lymph nodes by criterion other than size. More specifically, current conventional, high resolution, CT scanners provide pixelated images limited to about 15 to 20 line pairs/cm, corresponding to imaged areas of about 500 to 1000 microns/pixel. Therefore, by definition, to date these imaging modalities are inherently insensitive in the detection of small volume (<500-1000 microns) disease as well as non-specific in the detection of larger volume adenopathy. A recent study assessed the accuracy of MRI in patients with clinically localized prostate cancer. Rifkin et al., "Comparison Of Magnetic Resonance Imaging And Ultrasonography In Staging Early Prostate Cancer," N. Engel. J. Med., 323:621-626 (1990). In this study, 194 patients underwent a MRI and 185 of these patients had a lymph node dissection. 23 (13%) patients had pathologically involved lymph nodes. MRI was suspicious in only 1 of these 23 cases resulting in a sensitivity of 4%. Similar results have also been noted with conventional CT scans. Gasser et al., "MRI And Ultrasonography In Staging Prostate Cancer," N. Engl. J. Med. (Correspondence), 324(7):49-495 (1991).
While resolution is a key drawback with current imaging techniques, current CT scanners require a gantry supporting the x-ray source and detectors to rotate around the patient, and in particular his hips and pelvic bones, requiring radiation at levels sufficient to transmit through dense bone in order to acquire adequate information to image the prostate and its soft tissue environs.
One diagnostic tool that has proved helpful in the detection of diseased tissue in the body is referred to as in vivo imaging. The term "in vivo imaging" refers to any method which permits the detection or measurement of a biological process using an imaging modality. It is usually accomplished in connection with cancer cells by using a biological agent administered to a patient, the agent being of the type that is localized to the tumor bearing the antigen with which the biological agent reacts, and is detected or "imaged" using an appropriate imaging modality. The prior art in vivo imaging modalities include known techniques such as radionuclear scanning using e.g., a gamma camera or emission tomography. See e.g., A. R. Bradwell et al., "Developments in Antibody Imaging", Monoclonal Antibodies for Cancer Detection and Therapy, R. W. Baldwin et al., (eds.), pp. 65-85 (Academic Press 1985), which is hereby incorporated by reference. Alternatively, a positron emission transaxial tomography (PET) scanner has been used where the radiolabel is a constrast agent that emits positrons. A more general discussion of molecular imaging is described in Weissleder, et al., "Molecular Imaging", Radiology, (Vol. 219, No. 2), May 2001, pp 316-333.

CT scanner for and method of imaging a preselected portion of the lower abdomen region of a patient


An image taken by an imaging device is displayed on a display unit. When a confirmation instruction is inputted through an input unit, image teaching is performed while the image displayed on the display unit is set to a setting object image. A measurement item which is of a candidate of a measurement process including specification of a reference position is displayed as the measurement process to accept selection. Specification of cutout area which constitutes one measurement target region is accepted, a measurement point including a local region or a feature point which is used for the measurement is automatically set in the measurement target region based on pieces of information on the set measurement process and reference position.

1. Field of the Invention
The present invention relates to a displacement sensor which utilizes an optical cutting method to measure a displacement of an object.
2. Description of the Related Art
Conventionally, there are known sensor devices for measuring the displacement, a length, and an angle of various measurement objects. For example, a conventional displacement sensor includes a floodlighting unit, a light acceptance unit, calculation means, and output means. The floodlighting unit irradiates a measurement object with a line beam by driving a floodlighting element such as a laser diode. The light acceptance unit accepts slit light which is reflected by the measurement object after emitted from the floodlighting unit. The calculation means calculates a distance to the measurement object. The output means outputs the distance to the measurement object, which is calculated by the calculation means (refer to, for example, Japanese Patent No. 3599239).
The conventional displacement sensor can measure a sectional outline shape irradiated with the line beam on the measurement object. The use of the conventional displacement sensor can check whether or not a product falls within a specification range in a production line. Generally, in the case of a product inspection, a determination is seldom made by comparing a whole shape of a product to be inspected to that of a good product from the viewpoints of hardware necessary for processing and a processing time. However, the inspection is performed by measurements of a position and a height of a point which becomes important in the shape and a distance between the points. For example, in the case where the height and depth of a step are measured, a user separately sets an area including a step surface used in calculating the step from the sectional outline shape by a user. Which height and depth are measured from a reference position in the sectional outline shape is set by the area even in a top and bottom measurement instead of the step. In the case of the measurement of a step edge position on the measurement object, the area including the step edge position is set to perform the measurement.
However, in the conventional displacement sensor, a place which the user measures is specified and set in each time when a measurement process is performed based on plural local regions or feature points. Therefore, a setting operation is obscure and setting work is troublesome.


A diode parallel-plate plasma CVD system has semiconductor wafers are mounted with each of the front surfaces thereof being downwardly directed. The plasma CVD system includes an insulating wafer holder and conductive upper electrodes each being adapted to cover back surface of the semiconductor wafer, thereby forming a film to reduce internal stress and improve energy efficiency.

1. Field of the Invention
The present invention relates to a diode parallel-plate plasma CVD system forming a thin film constituting a semiconductor device and a method for producing the semiconductor device using the same.
2. Description of the Related Art
To form a thin film constituting a semiconductor device, a diode parallel-plate plasma CVD system has been used. The plasma CVD system of this type has such a construction wherein wafers are mounted with the surfaces thereof being downwardly directed for reducing particles (for example, as disclosed in Japanese Patent Laid-open No. sho 62-172732).
FIGS. 4a to 4c show a plasma CVD system of the conventional type having the above described structure: FIG. 4a is a side view; FIG. 4b is an enlarged view of the 4(b) portion shown in FIG. 4a; and FIG. 4c is a plan view of a wafer holder.
Referring to FIG. 4a, a reaction gas 8 is fed within a vacuum vessel 10 while an exhaust gas is discharged from gas exhaust ports 4, and thus the degree of vacuum in vessel 10 is kept at several Torr. In such a state, a low frequency power supply (50 KHz) applies a low frequency electric power across a diode parallel-plate type opposed electrodes composed of a wafer holder 2 serving as an upper electrode (ground electrode) and a lower electrode (power supply side electrode) 3, thus generating a plasma 9 therebetween to form a film on each of the wafers 1. In this case, a heater 12 supplies sufficiently stable heat to the back surface of the wafer 1. The heating plays an important role in forming a film having sufficient thickness and the preferable crystal structure on the front surface of the wafer 1.
However, the plasma CVD system mentioned above has a disadvantage in that sticking of the insulating film 11 on the peripheral portion of each wafer 1 often occurs, as shown in FIG. 4b, which makes the film formation slow and unstable. Namely, the insulating film 11, stuck on the peripheral portion of the wafer 1, insulates the wafer 1 from the wafer holder 2 serving as the upper electrode, thus potentially causing a defect in the film formation.
Taking this into consideration, see FIGS. 5a to 5e, which corresponds to the subject matter of Japanese Patent Laid-open hei 2-105527 and which proposes such a technique, i.e., covering the back surface of each wafer 1 mounted on a wafer holder 2 with a conductive material 16, and connecting the conductive material 16 to the wafer holder 2 (upper electrode) thereby securing the stability of the film formation. However, this technique has the following disadvantage. Since the wafer holder 2 serving as the upper electrode has a large area (e.g., a diameter of 700 mm), the use of a high frequency power supply (e.g. 13.56 MHz) allows the current to flow on the front surface of the electrode due to the skin effect or the like, thereby reducing the electric power contributing to film formation. Further, as shown, the electric power for generating plasma is spread across the whole area of the wafer holder 2, which causes the electric power to be dispersed thereby weakening the electric field distribution in the vicinity of each wafer (bringing about the tendency of reducing the plasma density in each wafer region). This lowers the generation amount of plasma in the vicinity of the wafer, which remarkably reduces the film formation rate. Therefore, in practical application, the diode parallel-plate plasma CVD system has used only a low frequency power of approximately 50 KHz.
However, the film formation using a low frequency power supply has the disadvantage of generating a compressive stress as an internal stress within the film, and of enlarging damage to an element due to ions, thereby deteriorating the reliability of the semiconductor device.

Plasma CVD system comprising plural upper electrodes


A methanol-utilizing bacterium selected from the group consisting of Methylophilus KISRI 5 (NCIB 12135), Methylophilus KISRI 6.1 (NCIB 12136), Methylophilus KISRI 512 (NCIB 12137), Methylophilus KISRI 5112 (NCIB 12138) and mutants and variants thereof. Also, bacterial cultures comprising these novel strains of Methylophilus and a method of producing single cell protein comprising culturing one or more of the Methylophilus strains of the invention in a methanol-containing aqueous culture medium, preferably in the culture medium of the invention which has been optimized for culturing these novel Methylophilus strains. The culture method preferably further comprises the recycling of spent culture medium.

This invention relates to growing bacteria to produce large quantities of single cell protein. More specifically, it relates to a process for efficiently and economically producing large quantities of single cell protein by culturing four novel strains of the genus Methylophilus in an optimized aqueous, methanol-containing culture medium.
As used herein, "single cell protein" is defined to mean an isolated mass of non-viable, dried cells of microorganisms produced by cultivating such microorganisms on substrates such as alkanes, lower hydrocarbons, lower alcohols or industrial and agricultural waste products which is destined to be used as a protein source.
Indigenous food production in many countries of the world does not meet the demand for food in those countries. In particular, due to sparse agricultural resources, food production in the hot, arid regions of North Africa and the Middle East is severely limited. Despite the production of intensive chicken, egg and meat production schemes, food production still does not meet the total consumption requirement. Since these chicken, egg and meat production schemes require protein-containing feeds, the production of single cell protein by growing microorganisms could relieve the foreseen shortage of food, particularly protein, in these countries.
For industrial-scale microbial processes to be used successfully in hot, arid regions, such processes must be capable of being both cooled economically and operated without the requirement for inordinately high quantities of drinking quality water. In addition, the process should have a high level of productivity.

Process and microorganisms for producing single cell protein

Kuwait Institute for Scientific Research


A segmented SCR ESD protection circuit for discharging an external electrostatic stress on a semiconductor integrated circuit is formed over a semiconductor substrate. The protection circuit includes an SCR device and a number of resistors. The SCR device is separated into a plurality of SCR segments for suppressing the occurrence of the secondary breakdown. Each of the resistors is connected to one of the SCR segments. The resistors can be in the form of parasitic resistances of the SCR device or in the form of additional electronic components formed on the semiconductor substrate.

1. Field of the Invention
The present invention relates to a protection circuit in a semiconductor integrated circuit, and more specifically, to a silicon-control-rectifier (SCR) electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit.
2. Description of Related Art
Progress in semiconductor technology has decreased the dimensions of many semiconductor devices. With this decrease in semiconductor device dimension, has come an increase in the sensitivity of the device to external signals. For example, most complementary metal-oxide-semiconductor (CMOS) devices have very thin gate oxide layers and shallow junctions to reduce the dimensions of the device and increase the device density in a semiconductor chip, thus increasing the product value of the semiconductor integrated circuit. However, these thin gate oxide layers and shallow junctions cannot withstand high stress. When certain external signals, such as an electrostatic stress, are applied to the CMOS devices, the thin oxide layers and the shallow junctions may be damaged, thereby affecting the performance of the CMOS devices. Therefore, in an integrated circuit which consists of CMOS devices, the input portion must be provided with an ESD protection circuit to prevent electrostatic damage. An ESD protection circuit that includes a silicon-control-rectifier (SCR) is considered to have very good electrostatic discharge performance. Since the SCR ESD protection circuit has a low snap-back holding voltage of about 1-5 volts and a low effective resistance of about 1-3 Ohms, it provides a very good discharge condition for the electrostatic current. However, a secondary breakdown effect occurs in the SCR device when the electrostatic current reaches a certain level. This secondary breakdown effect will damage the SCR device, thus affecting the ESD performance.
Although the SCR protection circuit suffers from the above problem, it discharges the ESD current better than other protection circuits. Therefore, it is very important to prevent the occurrence of the secondary breakdown so as to optimize the ESD performance of the SCR ESD protection circuit.
The secondary breakdown effect in a conventional SCR device will now be described and a new design which can abate the effect can then be provided.
Referring to FIG. 1 in which the top view of a conventional lateral SCR (LSCR) is illustrated, the device includes a cathode which consists of a P-type diffusion region 12 and an N-type diffusion region 14 both in a P-type substrate 10, and an anode which consists of a P-type diffusion region 22 and an N-type diffusion region 24 both in an N-type well 20. The cross-sectional view of the device in FIG. 1 along line II--II is illustrated in FIG. 2. When an electrostatic stress occurs in the anode, a electrostatic discharge path can be formed from the diffusion regions 22 and 24 of the anode diffusion regions to the diffusion regions 12 and 14 of the cathode, through the N-type well 20 and the substrate 10. The discharge path is supposed to be a band path in which the current density distributes uniformly. However, because the substrate material is not perfect and may contain defects, certain positions between the N-type well 20 and the substrate 10 are much weaker than other positions. That is, these positions have lower breakdown voltages. Therefore, if the discharge current density becomes high enough to trigger the breakdown mechanism, the discharge current will concentrate at the certain breakdown positions and increase the current density thereof, as shown in FIG. 1. The abrupt increase in current density tends to result in the secondary breakdown. Moreover, since almost all of the electrostatic current flows through the weak positions of the SCR device in an effect known as the thermal run-away, the device is damaged.
There are various forms of SCR devices, including the LSCR as shown in FIG. 1 and FIG. 2, an MLSCR in which an additional diffusion region is formed between the well and the substrate as shown in FIG. 3, and an LVTSCR in which a transistor is formed between the additional diffusion region and the cathode as shown in FIG. 4. Each of these SCR devices suffers from the same thermal run-away problems and secondary breakdown. As mentioned above, the secondary breakdown occurs when a very high current density exists in the SCR device. In other words, if the electrostatic current in the SCR device is uniformly discharged, the probability that a secondary breakdown will occur can be reduced, thus improving the electrostatic discharge performance.

Segmented silicon-control-rectifier (SCR) electrostatic discharge (ESD) protection circuit


A patterned perpendicular magnetic recording medium of the type that has spaced-apart pillars with magnetic material on their ends and with nonmagnetic trenches between the pillars is made with a method that allows use of a pre-etched substrate. The substrate has a generally planar surface at the trenches and comprises material that when heated will diffuse into the magnetic recording layer material and chemically react with one or more of the elements typically used in the recording layer. The pillars are formed of material that will not diffuse into the recording layer. After the recording layer is formed over the entire substrate so as to cover both the pillar ends and the trenches, the substrate is annealed. This results in the destruction or at least substantial reduction of any ferromagnetism in the recording layer material in the trenches so that the trenches are nonmagnetic. The annealing does not affect the recording layer on the ends of the pillars because the pillars are formed of material that will not diffuse into the recording layer.

1. Field of the Invention
This invention relates generally to patterned perpendicular magnetic recording media, such as disks for use in magnetic recording hard disk drives, and more particularly to patterned disks wherein the data bits are stored on elevated magnetic data islands isolated from one another by recessed nonmagnetic regions.
2. Description of the Related Art
Magnetic recording hard disk drives with patterned magnetic recording media have been proposed to increase data density. In patterned media the magnetic recording layer on the disk is patterned into small isolated data islands arranged in concentric data tracks. Patterned-media disks may be longitudinal magnetic recording disks, wherein the magnetization directions are parallel to or in the plane of the recording layer, or perpendicular magnetic recording disks, wherein the magnetization directions are perpendicular to or out-of-the-plane of the recording layer. To produce the required magnetic isolation of the patterned data islands, the magnetic moment of the spaces between the islands must be destroyed or substantially reduced to render these spaces essentially nonmagnetic. In one type of patterned media, the data islands are elevated, spaced-apart pillars that extend above the disk substrate surface to define troughs or trenches on the substrate surface between the pillars. This type of patterned media is of interest because substrates with the pre-etched pattern of pillars and trenches can be produced with relatively low-cost, high volume processes such as lithography and nanoimprinting. The magnetic recording layer material is then deposited over the entire surface of the pre-etched substrate to cover both the ends of the pillars and the trenches. It was believed that because the trenches were recessed they would be far enough from the read/write head to not adversely affect reading or writing. This type of patterned media is described in U.S. Pat. No. 6,440,520, and by Moritz et al., "Patterned Media Made From Pre-Etched Wafers: A Promising Route Toward Ultrahigh-Density Magnetic Recording", IEEE Transactions on Magnetics, Vol. 38, No. 4, July 2002, pp. 1731-1736. This type of patterned media with perpendicular magnetization on the pillar ends is believed to provide opportunity for ultra-high density magnetic recording. However, it has been discovered that the magnetic material in the trenches creates noise in the readback signal and also adversely affects writing the individual data bits (i.e., magnetizing the recording material on the pillar ends).
What is needed is a patterned perpendicular magnetic recording medium with pillars having magnetic material on their ends and with trenches that have essentially no magnetic moment, and a manufacturing process for the medium that allows use of pre-etched substrates.

This patent is subject to a terminal disclaimer.

Perpendicular magnetic recording system with patterned medium and manufacturing process for the medium

Hitachi Global Storage Technologies Netherlands B.V.


An improved amphibious all terrain vehicle having a subtantially rectangular body or shell and is constructed of a light-weight durable metallic material. A combustion gas engine is coupled to a dual hydraulic pump system which is centrally mounted within the length direction of the cavity for easy access and removal for repairs. An oil tank serves also as a seat base and is disposed within a central portion of the shell. Six-independent wheel motors are symmetrically disposed in series, three on each side of the shell and are plumbed in series for ground based mobility respectively. The wheels coordinate with a propeller disposed in the rear for amphibious propulsion. A fan is mounted on the under side of a front hood, near a dual lever, and switch controls for respective propulsion systems, and night-lights mounted on the hood respectively.

1. Field of the Invention
The present invention relates generally to motor vehicles. More specifically, the invention is a six-wheel independent drive amphibious all terrain vehicle which operates by a dual pump hydraulic system that delivers power to the wheels on both sides of the vehicle. The power of the vehicle is generated and translated to the system by an internal combustion gas engine.
2. Description of the Related Art
Various all terrain vehicles have been devised as utility vehicles for access to land areas having marsh and rugged terrains. The problem, however, with the conventional all terrain vehicles is that most include the complexities of gear and pulley systems which are highly prone to failure as a means for translating power from an engine to other respective moving parts, namely the wheels and other propulsion systems. For example, U.S. Pat. No. 3,385,255 issued to Raymond et al. discloses a track type amphibious vehicle which utilizes conduits or fluid lines for transmitting fluid power to a link chain and chain and sprocket drive which subsequently transmits power to the wheels. The amphibious all terrain vehicle of the instant invention does not require a chain and sprocket drive nor tracks as herein described.
U.S. Pat. No. 3,444,837 issued to Donofrio discloses a utility vehicle having structural features directed to a self supporting powered chassis comprising a clutch mechanism which functions by the principal use of planetary gear systems. In addition, the wheels are driven by a series of belts. This system of belts is completely different from that of the instant invention. U.S. Pat. No. 3,450,089 issued to Lippincott discloses similar gear features for transmitting power to a four-wheel vehicle. The power is transmitted through an axle laterally disposed across both wheels. This vehicle has weight requirements beyond that specified by the instant invention, due to the mandatory axles for each set of wheels. U.S. Pat. No. 4,821,825 issued to Somerton-Rayner also discloses similar structural requirements to that of Lippincott.
Other structural features which are generally relevant to the instant invention are represented in the following U.S. Pat. Nos. by Tanaka et al. (4,457,525), Furukawa (4,796,901), Divito (4,842,326), Ushioda et al. (4,907,735), Savage (5,466,034) and Davies et al. (5,480,189) . These particular patents disclose general features related to the frame structure of conventional all terrain vehicles including elements such as removable panels. However, there is no teaching nor suggestion for a six-wheel independent drive vehicle as herein described.
U.S. Pat. No. 5,117,936 issued to Nakamura discloses a vehicle propelling apparatus which converts between two wheel and four wheel drive systems, utilizing a hydraulic propulsion system including the requirement for a differential between the front right and left wheels. The British Patent document (GB 2 002 884) by Friedrich discloses similar features to the vehicle taught by Nakumura, however, the system requires a complex clutch and valve system for free wheeling and avoiding cavitation respectively. The amphibious all terrain vehicle according to the instant invention is completely different in that a differential between the front right and left tires and/or the requirement for the respective clutch system at least are not required as herein described. Other Foreign Patent documents such as the Australian document (AU 120,859) and the Japanese document (JP 6 166,342) have been cited as generally relevant to the instant invention.
The amphibious all terrain vehicle according to the instant invention is different to that of the prior and related art in that it is an improved light-weight utility vehicle which operates on a unique six-wheel independent drive system which reduces mechanical failure attributed to complex clutch and valve systems.
Therefore, none of the above inventions and patents, taken either singularly or in combination, is seen to describe the instant invention as claimed. Thus, an amphibious all terrain vehicle solving the aforementioned problems is desired.


A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.

Semiconductor devices such as insulated gate power transistor devices, e.g., power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), are widely used as electronic switches in various types of electronic applications. In many applications the reliability of such semiconductor devices is a critical aspect. For example, semiconductor devices that are used in automotive applications have to meet requirements with regard to specified ASIL (automotive safety integrity level) classifications, in accordance with international functional safety standards.
In some applications, destructive junction temperatures may be generated inside the semiconductor device during high SOA (safe operating area) switching, ringing or short-circuit events. Furthermore, the packaging volumes of semiconductor devices are being more and more reduced. Therefore, temperature monitoring has become imperative to protecting semiconductor devices from overheating. It is usually crucial that a sensor provide accurate temperature measurements and have a fast reaction time.
It is desirable to provide a temperature sensor and a method for producing a temperature sensor that has a fast reaction time while providing reliable measurement results.

Method for producing a semiconductor arrangement

Infineon Technologies Dresden GmbH & Co. KG


A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a virtual channel identifier ("VCI") table in order to schedule cells for virtual channels. The transmit scheduler calculates a location in the scheduler table in which to schedule a cell for a current virtual channel and determines whether a cell for a prior virtual channel is scheduled in the calculated location in the scheduler table. The transmit scheduler then schedules the cell for the current virtual channel at the calculated location in the scheduler table. If a cell for a prior virtual channel was scheduled in the calculated location in the scheduler table, the transmit scheduler writes a pointer into a next pointer field of a record for the current virtual channel in the VCI table, where the pointer provides a link to a record for the prior virtual channel in the VCI table. The transmit scheduler is thereby operable to build linked lists beginning at each location in the scheduler table in which cells for more than one virtual channel are calculated to be scheduled.

Networks interconnecting end stations increasingly use asynchronous transfer mode (ATM) schemes for transmission of information. In an ATM network, transmitting end stations send information using cells or packets placed in available slots that are then extracted from those slots by the recipient end station. Each end station can include transmission and receiving units for sending and receiving cells on the ATM network. Generally, end stations can be personal computers, computer work stations, or other computer systems that use adapter cards to provide an interface between a native bus on the end station and the ATM network, or otherwise implement adapter functions. End stations can also be devices or systems that provide interworking adapter functions between ATM and other networking technologies such as ATM end stations that bridge to other networks. The adapter functions performed by end stations often establish and manage numerous virtual channels (VC's) that are identified by virtual channel identifiers (VCI's) in order to structure the transmission of cells or packets.
When transmitting cells or packets on an ATM network, a transmission unit of an adapter card or other adapter element can use a scheduler in order to schedule when cells corresponding to the active virtual channels should be sent. The scheduler thereby provides the transmission unit, for example, with information about which cells to retrieve from end station memory for packaging and transmission across the ATM network. Conventional schedulers generally use a fixed and statically-loaded scheduler table to schedule cells for a fixed number of virtual channels. These conventional schedulers advance a single pointer in sequence through the scheduler table in order to determine, for example, which cell for which virtual channel should be packaged and sent.

Transmit scheduler for an asynchronous transfer mode network and method of operation


A programmable logic device can include a logic core in low power mode, a source input/output (I/O) bank including at least one source I/O pin, wherein the source I/O bank operates in normal operating mode, and a destination I/O bank including at least one destination I/O pin, wherein the destination I/O bank operates in normal operating mode. The programmable logic device also can include a bypass routing bus coupled to the source I/O bank and the destination I/O bank, wherein the bypass routing bus detects an I/O signal from the source I/O pin, responsively generates a bypass signal that is provided to the destination I/O bank and, responsive to the bypass signal, generates an output bypass signal on the destination I/O pin.

Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more "function blocks" connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include but are not limited to these exemplary devices, as well as devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
PLDs have become commonplace within a variety of different types of systems. Often, the PLD is incorporated into a system that includes a primary processor, e.g., a microprocessor, as well as one or more peripheral devices. The PLD, for example, may be disposed within the system as an interface linking the peripheral devices with the primary processor. When not in use, the PLD may be powered down or placed in a low power mode. When in a low power mode, signals passed into the PLD, e.g., from a peripheral device, the processor, or another source, are not passed back out to other devices. This means that when placed in low power mode, the PLD no longer functions as an interface. The PLD effectively becomes an open circuit in that signals are not passed in, out, or through the device
In illustration, consider the case where signals from a peripheral device are coupled to the PLD. The PLD functions as an interface between the peripheral device and another processor. Signals from the peripheral device that are coupled to the PLD may also be used to "wake-up" the processor from a low power mode. When the processor is in a low power mode, power consumption can be further reduced if the PLD is also placed in a low power mode. When placed in a low power mode, however, the PLD cannot pass the signals needed to "wake-up" the processor. Accordingly, alternate channels external to the PLD must be provided to allow such signals to propagate to the processor when the PLD is in a low power mode.
In other examples, it may be desirable to place the PLD in a low power mode and, under certain circumstances, provide a signal to another device, e.g., a processor. While the PLD is placed in a low power mode, the processor may or may not be operating in a low power mode. In any case, the signals to be provided to the processor would not be passed through the PLD. Further, as noted, an alternate channel that is external to the PLD would have to be provided to couple the peripheral device with the processor when the PLD is in low power mode.

Input/output programmable routing in a programmable logic device


A torque wrench is provided that includes a force measuring mechanism that enables the wrench to display the force exerted by the wrench and to perform a check of the calibration of the force measuring mechanism. The mechanism can perform the calibration check and can provide feedback to the user regarding the need, if any, for the calibration of the force sensing mechanism prior to further use of the device.

Torque wrenches are utilized to drive fasteners into a substrate while allowing the user to control the amount of force exerted on the fastener, such as to avoid damage to the fastener and/or the substrate.
When utilizing electronic types of these devices or tools, the electronics portion of the tool, or wrench in a particular embodiment, operates to measure and/or calculate and display or otherwise illustrate the amount of force or torque that is being applied by the tool to the fastener as it is driven into the substrate. In the particular embodiment where the tool or wrench is being used in a medical procedure, the amount of force utilized to drive the fastener into the substrate is important to monitor closely, as the fastener can damage the substrate, e.g., the bone, into which the fastener is being driven if excessive force is utilized. Additionally, excess torque can cause a fastener to cold fuse or weld to another component of the surgical process, such as a surgical plate, causing damage to the plate, and potentially requiring additional procedures. Conversely, if insufficient torque is applied to the fastener, the fastener can come loose after the procedure, requiring an additional procedure to correct the issue.
However, even when highly accurate electronic force measuring devices, systems, mechanisms or other electronic force measuring units are employed, the electronics unit can be rendered inaccurate for any number of reasons, which require the calibration/re-calibration of the electronics unit. As surgeons or other hospital staff are normally unable to perform calibration procedures on site, they rely on the quality control of the manufacturer with regard to the accuracy of the tool or device.
One significant issue with this situation is that it is often difficult to determine when the electronics unit has become inaccurate. Most often, devices or tools of this type include a schedule according to which the device is required to be calibrated, such as after a certain number of hours of use. Nevertheless, this calibration schedule cannot cover all of the instances where the electronics unit, as the schedule may not be done with sufficient frequency, such that the device may be providing inaccurate force or torque measurements to the user.
Thus, it is desirable to develop a torque wrench including an electronic force measurement unit that can provide a self-check aspect to the force measurement function performed by the electronics unit of the device such that the device can indicate to the user when the measurement unit/device requires calibration prior to being able to be used to provide inaccurate force measurement results.

Electronic torque wrench with transducer check function


In a traffic control method and system for an ATM switching apparatus, which is adapted to control traffic by restraining inflow cells on the basis of an amount of cells remaining in a queuing buffer that receives a varying amount of inflow cells and outputs a constant amount of outflow cells, a residual cell amount in the queuing buffer is monitored at intervals of unit times. The cell variation amount of cells remaining in the queuing buffer is monitored per unit time. It is determined, on the basis of the residual cell amount monitoring result and the cell variation amount monitoring result, whether a residual cell amount after the lapse of a predetermined period of time exceeds a cell residue limit amount in the queuing buffer. Inflow cells to the queuing buffer are restrained when it is determined that the residual cell amount exceeds the cell residue limit amount.

The present invention relates to a traffic control method and system for an ATM switching apparatus and, more particularly, to a traffic control method and system for an ATM switching apparatus, which control a traffic on the basis of a predetermined transmission capacity in an ATM switching apparatus for performing switching connection of fixed-length packets called cells.
In general, in an ATM switching apparatus for performing switching connection of fixed-length packets called cells on the basis of the Asynchronous Transfer Mode (ATM), the flow rate of cells, i.e., the traffic, in each virtual communication channel is monitored to control the traffic within an assigned transmission capacity.
FIG. 5 shows a conventional ATM switching apparatus traffic control system like the one disclosed in Japanese Patent Laid-Open No. 3-218143. Referring to FIG. 5, reference numeral 1 denotes a queuing buffer; 2, a cell held in the queuing buffer 1; 3, an inflow cell; 4, an outflow cell; 5, a residual amount monitoring section for monitoring the amount of cells 2 held in the queuing buffer 1, i.e., the residual amount of cells 2, on the basis of a predetermined residue threshold; 6, a residual amount monitor output from the residual amount monitoring section 5; and 7, an inflow cell restraint determining section for outputting an inflow cell restraint output 8 for designating an inflow restraint of the inflow cells 3 on the basis of the residual amount monitor output 6.
A conventional traffic control system will be described next with reference to FIGS. 6A to 6C. FIG. 6A shows the residual amount of cells in the queuing buffer 1. FIGS. 6B and 6C respectively show the residual amount monitor output 6 and the inflow cell restraint output 8. The residual amount monitoring section 5 monitors the amount of cells 2 held in the queuing buffer 1, i.e., a residual cell amount 41 (FIG. 6A) at intervals of unit times T, i.e., time t.sub.n-2, time t.sub.n-1, . . . Before time t.sub.n the residual cell amount 41 is below a residue threshold 42. The residual amount monitor output 6 is set at "L" level, as shown in FIG. 6B, and the inflow cell restraint output 8 from the inflow cell restraint determining section 7 is also set at "L" level, as shown in FIG. 6C. No restraint is therefore imposed on inflow cells.
Assume that the residual cell amount 41 exceeds the residue threshold 42 after time t.sub.n. In this case, the residual amount monitoring section 5 recognizes this state at time t.sub.n+1 and sets the residual amount monitor output 6 at "H" level (FIG. 6B). When the inflow cell restraint determining section 7 sets the inflow cell restraint output 8 at "H" level in response to this operation without any delay (FIG. 6C), a restraint on the inflow cells 3 to the queuing buffer 1 is started at time t.sub.n+1. If the inflow of cells is completely stopped in performing this restraint, the residual cell amount 41 of cells 2 in the queuing buffer 1 decreases in accordance with the amount of outflow cells 4. Thereafter, the residual amount monitoring section 5 monitors at time t.sub.n +3 that the residual cell amount 41 becomes smaller than the residue threshold 42. As a result, both the residual amount monitor output 6 and the inflow cell restraint output 8 are set at "L" level to resume the inflow of cells.
In this conventional traffic control system for an ATM switching apparatus, when the residual cell amount 41 of the queuing buffer 1 exceeds the predetermined residue threshold 42, the inflow cells 3 are restrained. The restraint on the inflow cells 3 is delayed because of the offset between the residual amount monitor timing and the traffic variation. As a result, a large amount of loss cells 43 are generated. With an increase in transmission capacity, in particular, the amount of loss cells increases.

Traffic control method and system for ATM switching apparatus


A method of fabricating a transient semiconductor based on a single-wall nanotube includes stacking a thermal oxide layer on a silicon substrate and depositing a nickel thin layer on the thermal oxide layer, depositing an oxide layer on the nickel thin layer, depositing a metallic layer on the oxide layer, and patterning the metallic layer to form a gate electrode, depositing a gate insulating layer on the gate electrode, changing a surface of the gate insulating layer into a hydrophilic surface, and washing and drying the gate insulting layer, coating a single-wall nanotube on the hydrophilic surface of the gate insulating layer, forming source and drain electrodes by forming a contact opening with respect to the gate insulating layer, attaching a thermal release tape after removing a surrounding single-wall nanotube, performing a transfer onto a polyvinyl alcohol thin layer after etching the nickel thin layer, and releasing the thermal release.

1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor, and more particularly to a method of fabricating a transient semiconductor based on a single-wall nanotube, capable of fabricating a low-voltage, high-gain, and full-swing transistor by transferring a semiconductor, which has a single-wall nanotube electron structure having a physically transient property that all components are decomposed under water, into a polyalcohol thin layer having a predetermined molecular weight.
2. Description of the Related Art
In general, transient electronics refers to a technology of designing included devices to be physically lost partially or entirely under the control after the devices have provided intrinsic functions thereof.
The applications of the transient electronics range from a bio-degradable implant to a hardware security memory system, the loss of an environmental sensor, or a household appliance having a reduced waste steam.
The technology has created opportunities of studies on an electronic material and a device design and studies on a breakthrough micro/nano-technology.
Meanwhile, a silicon nano-membrane requires different materials, such as zinc oxide (ZnO6) and organic/bio-polymer. On the contrary, the silicon nano-membrane has an advantage in the above studies since the dissolution characteristic by hydrolysis, a stable reproduction characteristic, and a superior electrical characteristic are represented in bio-liquid, ground water, seawater
Accordingly, the need for the manufacturing of a transient semiconductor based on a single-wall nanotube by utilizing the transient electronics is emerged, in which the transient electronics is utilized based on controlled dissolution and decomposition with an ability of forming a field effect transistor (FET) in a single wall nanotube network, an ability of forming a percolating network having a low area range in a nano-scale dimension of the single-wall nanotube, and an ability of forming a superior electrical characteristic and capacitance for network distribution due to the loss of a support substrate.
However, although the single-wall nanotube network has been extensively studied in an individual device and an integrated circuit, the single-wall nanotube network has never been studied as a transient material for a transient electronic system.
Therefore, the present inventor has invented a method of fabricating a transient semiconductor by combining a single-wall carbon nanotube with a substrate including water-soluble dielectric and metal and a transient boot strap single-wall carbon nanotube inverter, to represent an improved noise margin and logic swing when comparing with a non-transient inverter.
Meanwhile, a full-swing electrical characteristic based on DC and pulse mode schemes produces the intrinsic effect thereof as well as the effect of a contact formed using a transient metal.
However, according to the related art, when one and two dimensional materials are formed in contact with an insulating layer, traps having various energies are formed, so that device performance and reliability may be significantly degraded. In addition, according to the related art, when a diode-connected load is used, threshold voltage drop may not remarkably reduce a logic swing and a noise margin at a source terminal.
Therefore, in order to solve the problems occurring when a nanomaterial makes contact with an insulating layer according to the related art, the present inventor suggests a method of fabricating a transient semiconductor based on a single-wall nanotube, enabling an inverter including a transistor having the high mobility and on/off rate to perform full swing with a high gain under low voltage by transferring a semiconductor, which has a single-wall nanotube electron structure decomposed under water, into a polyalcohol thin layer having a predetermined molecular weight.
As prior arts, there are KR 10-2010-0120295 A1 and KR 10-2007-0030661 A1.

Method of fabricating transient semiconductor based on single-wall nanotube

Incheon University Industry Academic Cooperation Foundation


A method for forming a patterned photoresist layer. There is first provided a substrate. There is then formed over the substrate a blanket photoresist layer. The blanket photoresist layer is then implanted with a first ion beam to form an ion implanted blanket photoresist layer. The first ion beam employs a first ion having a first energy and a first dose sufficient such that an ion implanted patterned photoresist layer formed from the ion implanted blanket photoresist layer will not substantially outgas when the ion implanted patterned photoresist layer is exposed to a second beam. The ion implanted blanket photoresist layer is then patterned to form the ion implanted patterned photoresist layer. The method may be employed in selective high energy beam processing of the substrate. The method is particularly suited to selective high energy ion implant processing of semiconductor substrates employed within integrated circuit microelectronics fabrications.

1. Field of the Invention
The present invention relates generally to photoresist layers employed within microelectronics fabrications. More particularly, the present invention relates to methods for attenuating outgassing of photoresist layers employed within microelectronics fabrications.
2. Description of the Related Art
Known in the art of microelectronics fabrication, such as but not limited to integrated circuit microelectronics fabrication, is the use of patterned photoresist layers as masking layers within photolithographic methods employed to define patterned layers and patterned structures within microelectronics fabrications. Similarly, it is also known in the art of microelectronics fabrication that patterned photoresist layers when employed as masking layers with respect to microelectronic fabrication processes which employ high energy beams employed within low pressure reactors, such as but not limited to high energy ion implantation beams employed within low pressure ion implantation reactors, often exhibit significant outgassing which compromises the low pressure reactor operating pressure desired or required for the microelectronic fabrication process which employs the high energy beam. Often the low pressure reactor operating pressure is sufficiently compromised such that there is simultaneously also compromised other desired operating parameters of the microelectronic fabrication process which employs the high energy beam thus simultaneously precluding formation of an operable or optimal microelectronics fabrication.
Therefore, it is towards the goal of providing for use within microelectronics fabrication a method for attenuating patterned photoresist layer outgassing when a patterned photoresist layer is exposed to a high energy beam within a low pressure reactor that the present invention is generally directed.
Various aspects of interactions of photoresist layers with high energy beams employed within microelectronics fabrications, such as but not limited to integrated circuit microelectronics fabrications, have been disclosed in the art.
For example, Daniel in U.S. Pat. No. 5,037,767 discloses a method for manufacturing a semiconductor device wherein there is implanted through a blanket ion beam sensitive photoresist layer a dopant ion into a semiconductor substrate upon which is formed the blanket ion beam sensitive photoresist layer. There is thus formed within the semiconductor substrate doped regions, along with an ion beam exposed portion of the blanket ion beam sensitive photoresist layer and an ion beam unexposed portion of the blanket ion beam sensitive photoresist layer. The ion beam unexposed portion of the blanket ion beam sensitive photoresist layer is then developed to leave remaining upon the semiconductor substrate a self aligned mask formed from the ion beam exposed portions of the blanket ion beam sensitive photoresist layer, where the self aligned mask is employed within further integrated circuit processing when forming a semiconductor device within the semiconductor substrate.
In addition, and more pertinent to the present invention, Hanley in U.S. Pat. No. 4,851,691 discloses a pretreating method for attenuating outgassing of a patterned photoresist layer formed upon a substrate prior to processing the substrate within a high energy ion beam. Through the method, the patterned photoresist layer is first bombarded with ions which are electrically inactive with respect to the substrate prior to processing the substrate within the high energy ion beam comprised of ions which are electrically active with respect to the substrate.
Desirable in the art are additional methods through which patterned photoresist layer outgassing incident to exposing patterned photoresist layers to high energy beams within low pressure reactors may be attenuated. More particularly desirable in the art are additional methods through which patterned photoresist layer outgassing incident to exposing patterned photoresist mask layers to high energy ion implantation beams within low pressure ion implantation reactors may be attenuated. It is towards the foregoing goals that the present invention is more specifically directed.

Method for attenuating photoresist layer outgassing

Taiwan Semiconductor Manufacturing Company


A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.

When a vertical conduction MOSFET is in a blocking mode, the inherent P/N body diode depletes toward the source. If there is insufficient charge in the channel (or body) region, punch-through occurs before avalanche breakdown is reached.
In a low voltage VDMOS device (Vertical Conduction Double Diffused MOS), this premature punch-through is normally prevented by using a higher channel dose and/or a deeper channel drive than might be otherwise required for a given avalanche breakdown value.
However, the higher channel dose results in a correspondingly higher threshold voltage VTH; while a deeper channel drive increases channel length and thus channel resistance. The deeper channel drive also increases the depth of the JFET region between adjacent channel regions, thus reducing the optimum utilization of the epitaxial silicon receiving the diffusions.
A process and structure which prevents punch-though without increasing channel dose or channel depth would be very desirable before avalanche voltage is reached.


A window operator handle securable to a casement window operating drive shaft is described. The handle is movable between an operating position to a folded position. The handle has a body housing that has a cavity which includes an operating mechanism. The operating mechanism has an assembly body secured to the housing, a pivotal member positioned in a first section of the assembly body and a sliding member positioned in at least a second portion of the assembly body. The pivotal member is adapted to pivot from a first position to a second position as the handle is moved from a first position to a second position. The pivotal member is held in one position and the other position by the sliding member. The sliding member is retained in contact with the pivotal member by a spring means in said assembly body.

Casement windows are manually operated windows where, in order to open and close them, it is necessary to rotate a handle attached to a drive mechanism of such window. A handle is attached to a rotating shaft of the window, which in turn, allows the window to be closed and opened through, for example, a rack that connects a window and a rotating shaft. Therefore, a manual handle is an important part of most casement windows. Because casement windows have become more and more popular among home owners because of their practicability, reliability and attractive appearance, a manual handle that operates such windows must follow a growing popularity of windows and respond to demands to be more technologically advanced.
When a window handle is not in use, i.e. when a window is not operated, the handle, which usually is attached to a window frame and extends outward from such window frame, causes many inconveniences; it may cause certain restraint for user's movement near the window or positioning of window's curtains, blinds etc., Therefore, it is preferable that when not in use, a handle is folded toward the window. First, it helps to create more attractive look. Secondly, a folded handle reduces the amount of inconvenience that such handle produces if projecting outward from a window. Unlike any other similar existing devices, the present handle's design allows the operator move the handle's position to either an "operating" or a "folded" position only. The present invention is compact and cost efficient. The design also has a construction that is wear-resistant that provides for prolonged use without breaking and a need for replacement.


In the method of fabricating a nitride-based semiconductor optical device by metal-organic chemical vapor deposition, a barrier layer is grown at a first temperature while supplying a gallium source to a reactor. The barrier layer comprises a first gallium nitride-based semiconductor. After the growth of the barrier layer, a nitrogen material and an indium material are supplied to the reactor without supply of the gallium source to perform a preflow of indium. Immediately after the preflow, a well layer is grown on the barrier layer at a second temperature while supplying an indium source and the gallium source to the reactor. The well layer comprises InGaN, and the second temperature is lower than the first temperature. The gallium source and the indium source are supplied to the reactor during plural first periods of the step of growing the well layer to grow plural InGaN layers, respectively. The indium material is supplied to the reactor without supply of the gallium source during the second period of the step of growing the well layer. The second period is between the first periods. The well layer comprises the plural InGaN layers.

Nonpatent Literature 1 (Journal of Crystal Growth, 264 (2004), pp. 53-57) discloses a quantum well structure grown on a c-plane sapphire substrate. The supplying of TMIn is performed to before growing an InGaN layer.
Nonpatent Literature 2 (Japanese Journal of Applied Physics, Vol. 47, No. 2 (2008) pp. 829-842) discloses an InGaN/GaN multiple quantum well structure grown on a c-plane sapphire substrate. In the formation of the multiple quantum well structure, after growing a GaN barrier layer at a first growth temperature, the substrate temperature is lowered to a second growth temperature for the well layer. After the substrate temperature has been lowered, indium is supplied onto the GaN barrier layer at the second growth temperature, and then an InGaN well layer is grown thereon. Just after having growing the InGaN well layer, a GaN cap layer is grown on this well layer. The growth of the GaN cap layer is performed while the temperature is raised from the second growth temperature to the first growth temperature. After growing the GaN cap layer, the growth is interrupted at the first growth temperature. Then, another GaN barrier layer is grown on the GaN cap layer. The supply of indium does not affect the indium content and abruptness at the surface boundary in the InGaN/GaN structure. This process, i.e., the supply of InGaN, ensures a decrease in density of V-shaped defects in the InGaN/GaN quantum structure.
Nonpatent Literature 3 (Applied Physics Letters, Vol. 92 (2008) 161113) discloses an InGaN/GaN quantum well structure grown on a c-plane sapphire substrate. A quantum well layer and a barrier layer are grown at a temperature of 780° C. In the growth of the quantum well structure, TMIn and ammonia are supplied to a reactor after the growth of the InGaN well layer and before the growth of the GaN barrier layer. This step reduced the density of V-shaped defects from 3.9×108 to 2.9×108 cm−2 in a single quantum well structure, and from 7.8×108 to 4.7×108 cm−2 in a multiple quantum well structure.

Method of fabricating nitride-based semiconductor optical device


A deposition chamber for forming a deposited layer on a wafer having a mixing chamber is disclosed having a wafer support device for supporting the wafers in the mixing chamber, a nozzle located above the wafer support device which can eject the gas/particle mixture into the mixing chamber toward the wafer, a gas outlet device at the bottom end of the chamber from the gas nozzle which allows the gas to exit the chamber and a deionizing device located above the wafer support device and below the nozzle to deionize the gas/particle mixture thereby encouraging uniform deposition of the particles on the wafer. This deposition chamber may also comprise an exhaust fan below the gas outlet device.

Semiconductors are manufactured to close tolerances on very clean surfaces. These surfaces, typically silicon or gallium arsenide, are in the form of wafers that are manufactured in standard sizes of 2, 3, 4, 5, 6, 8, and 10 inches in diameter. Industry standards dictate that these pure crystalline wafers be of a certain thickness, resistivity, etc. These wafers are handled from the backside only by the means of a vacuum wand. They are kept sealed until they are used and can only be opened in a clean room environment to ensure that they are not contaminated by particles and other foreign materials that affect yield levels.
Many companies use optical surface inspection machines that use a laser or other technique to scan these wafers for particle contamination that cannot be seen without the use of a microscope or a SEM (Scanning Electron Microscope). Wafers are scanned for certain particle count levels and, if acceptable, they are used to build semiconductors on. If they are dirty, the wafers are cleaned and reinspected for contamination. If the wafers cannot be cleaned, they are scrapped because the cost of further processing exceeds the value of the wafer yield(s).
To guarantee accurate count estimates, optical surface inspection systems must be calibrated with standard particle size artifacts, such as polystyrene latex (PSL) spheres. A surface particle sizing standard is created when monosized PSL spheres that are traceable to the National Institute of Science and Technology are deposited onto the substrate of interest, e.g., bare silicon, silicon with a thin film coating, a patterned silicon wafer, a photomask or a disk.
In these systems, the sizing standard or wafer is scanned by a surface inspection instrument to determine the optical light scattering of the spheres deposited on the specific substrate. The amount of light scattered is then related to the size of the sphere deposited. When many substrates, such as wafers, are deposited with many different sphere sizes, one may calibrate the inspection machine across its entire dynamic range for that specific substrate type. The dynamic range of an instrument is the range over which particle sizes can be resolved from each other for a given substrate type. The ability to measure and resolve particles on substrates is important in the manufacture of many substrate types, but particularly in the production of semiconductors. The geometry of a given integrated circuit design dictates the sensitivity of a device to particles during manufacturing. The more integrated and dense the geometry, the smaller the particle size that can cause device failure, or functional yield loss. A 10:1 design rule is often used to identify particle sizes which can cause device failure, i.e., particles 1/10th the size of the geometry.
Most integrated circuit manufacturers produce several different device geometries and integration levels, thus each has different contamination limits. Surface inspection systems must therefore be set up with substrate particle sizing standards for each device type to provide relevant process control information to decision-makers and to provide an adequate return-on-investment in the inspection system itself.
One technique to apply monosized PSL sphere artifacts on the wafer (or other) surface incorporates chemical vapor deposition (CVD) principles. Typically, in such a deposition scheme, a colloidal suspension of PSL spheres of a known size distribution is made from concentrated spheres and surfactants diluted with ultra-pure deionized water. This suspension is atomized with an atomizer to produce an aerosol. The atomizer is typically designed for sizes of spheres from 0.005 micron to 1.0 micron in diameter. Such atomizers are designed to produce droplets of water that ideally contain one sphere per drop. Next, the atomized droplets leave the atomizer and flow through a line or tube to a glass expansion air dryer comprised of a connected series of four glass bulbs. The output of the glass dryer is a dry air/sphere mixture that is either reprocessed through the dryer if any visible moisture is evident or continues on to an optional electrostatic classifier. The classifier uses electrostatic forces to separate all incoming particles based on the electric mobility of each individual particle.
The dry air/sphere mixture then enters the deposition chamber and is dispersed by a nozzle at the top of the deposition chamber. The PSL spheres are pushed by the constant output from the nozzle toward the wafers which are positioned on deposition plates at the bottom of the chamber.
Existing deposition systems including systems for the deposition of these latex spheres have a number of drawbacks making them unsuited to commercial or research applications. For example, the available deposition plates for latex sphere deposition do not allow for batch processing, i.e., only one wafer fits in the deposition chamber at a time. Moreover, when only one half of the wafer is to be processed, the space between the wafer and the mask covering the half of the wafer is so large that some of the deposition material (latex spheres) can rebound off the uncovered portion of the wafer and land in the covered portion, thereby destroying the value of the wafer. Additionally, the devices covering one half the wafer are not adjustable for wafers already having layers of material on them from previous processing.
Yet another problem with existing deposition plates is the lack of means on the deposition plate to remove the wafer with a vacuum wand
Another drawback of existing deposition chambers relates to the inability of existing chambers to ensure uniform distribution of the particles being deposited on the wafer. One attempt to overcome this problem is seen in U.S. Pat. No. 4,989,541 to Mikoshiba et al. Mikoshiba et al incorporates a separate nozzle for a "control gas" which encircles the material gas flow and forcibly reorients laterally expanding portions of the material gas flow. The use of such a control nozzle and gas is both expensive and difficult. Moreover, it does not address problems faced when the ionized particles attach to the side walls of the mixing chamber.
Still another drawback relates to the time needed between the processing of each wafer in order to remove previous particles from the chamber. A lengthy amount of time is required between when the particles exit the nozzle and when they reach the base of the deposition chamber.

Deposition chamber for deposition of particles on semiconductor wafers


In an RF communication system, aspects of constant or proportional to absolute temperature biasing for minimizing transmitter output power variation may comprise configuring at least one current source to provide a temperature dependent current, where the current may be constant with temperature or vary proportionally to absolute temperature. A control voltage that may be generated by an operational amplifier may be fed back to control the current source. An input reference voltage may also be generated for the operational amplifier by utilizing PN junction characteristics of at least one bipolar junction transistor. Resistance may be adjusted to allow operation of the current source at a plurality of different supply voltages, including the different supply voltages that may be less than 1.2 volts, for example. Additionally, adjusting the resistance may also allow the current to be constant with temperature or vary with temperature.

In some conventional systems, a transmitter may broadcast radio frequency (RF) signals. Generally, RF signals are generated by upconverting baseband signals to intermediate frequency (IF) signals, and then further upconverting the IF signals to RF signals. The RF signals may be amplified by power amplifiers before being transmitted by a transmit antenna. Because of a plurality of transmitters, for example, mobile communication handsets, wireless telephones, walkie-talkies, wireless home computer networks, etc., a strong transmitted signal may cause interference with other nearby transmitted signals.
In some instances, a transmitted signal may cause interference with a system that may be utilizing frequency re-use technique. With frequency re-use technique, multiple transmitters may be assigned a frequency to use, as long as the transmitters are far enough away from each other that their transmitted signals do not interfere with each other. The most common example of frequency re-use today may be cellular communication networks utilizing time-domain multiple access (TDMA) standard. The network operators take much care in ensuring that various frequency bandwidths are spread out among the plurality of cells such that transmitted signal in one cell does not overpower other transmitted signals in other cells of the same frequency bandwidth. Other frequency re-use examples are radio stations and television stations. The Federal Communications Commission (FCC) strictly regulates the broadcasting frequencies of the radio and television stations in order to keep neighboring stations from interfering with each other. The FCC also regulates the power output of the transmitting stations in order to keep distant stations from interfering with local stations that may be broadcasting at the same frequency.
In other instances, all transmitters may transmit in the same frequency bandwidth, but, still, care must be taken to ensure that no "rogue" transmitter transmits at too high power to "drown out" other transmitted signals. Code division multiple access (CDMA) system is an example where all transmitters transmit over the same frequency bandwidth. In CDMA, special algorithms are used to code and/or decode a specific signal of interest to a transmitter and/or a receiver. Although all receivers receive all signals transmitted, when a receiver's specific decoding code is utilized by a receiver, all other signals except the desired signal appears as random noise. However, if a transmitter transmits too much power, then that signal would appear as too much noise to other receivers, and the desired signals at other receivers may be drowned out by the noise. Therefore, a transmitted signal must be transmitted with enough power to be able to be received and decoded by a receiver, and yet must not have too much power that it interferes with other signals.
Generally, controlling output power of a transmitter is extremely important to minimize interference with other transmitted signals while still providing enough transmitted signal strength to be able to be received and processed by a receiver. In addition, a transmitter of limited power source, for example, mobile communication handset with a small battery, may need to accurately control power output in order to maximize battery life. However, a problem is that performance of various electronic devices, for example, resistors or semiconductor devices on integrated circuits (ICs or chips), etc., may be affected by temperature. As temperature rises, a resistor's resistance may increase, thereby affecting current and voltage, and vice versa as temperature decreases. Similarly, the current that a transistor conducts may vary as temperature changes. These changes may affect the power output of the transmitter.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Method and system for constant or proportional to absolute temperature biasing for minimizing transmitter output power variation


A method of analyzing factor responsible errors in a wafer pattern which enables detection of an error ascribable to a difference between mask patterns and an error ascribable to another reason while distinguishing between the errors. A mask pattern is formed by etching a first mask at a first position within an etching chamber. Another mask pattern is formed by etching a second mask at a second position within the etching chamber. A wafer pattern is formed by single shot of exposing radiation through use of the first mask, and another wafer pattern is formed by single shot of exposing radiation through use of the second mask. The size of the wafer pattern formed through use of the first mask and the size of the wafer pattern formed through use of the second mask are compared with each other, thereby detecting a dimensional difference ascribable to a difference between mask patterns and a dimensional difference ascribable to another reason while distinguishing between the dimensional differences.

1. Field of the Invention
The present invention relates to a method of analyzing a factor responsible for an error in a wafer pattern and an apparatus for producing a photolithographic mask. More particularly, the present invention relates to a method of analyzing a factor (hereinafter referred to simply as a xe2x80x9cfactor analysis methodxe2x80x9d) for detecting an error in a wafer pattern ascribable to a tolerance of mask patterns and an error in a wafer pattern ascribable to another reason while distinguishing between them, as well as an apparatus suitable for producing a mask for use with the factor analysis method.
2. Description of the Background Art
In a process of manufacturing a semiconductor device, a wafer pattern is transferred onto a semiconductor wafer through use of a photolithographic mask (hereinafter referred to simply as a xe2x80x9cmaskxe2x80x9d). A wafer pattern transferred onto a semiconductor wafer includes an error ascribable to a tolerance of mask patterns (hereinafter referred to as a xe2x80x9cmask pattern errorxe2x80x9d) and an error ascribable to a factor other than a mask pattern error, for example, an error in a stepper, a variation in the thickness of a photoresist film, and a variation in resolution.
It is useful to determine a cause for inducing an error in a wafer pattern for promoting the development of a semiconductor device. However, it has been difficult to ascertain a ratio between a mask pattern error and an error ascribable to another reason.
The present invention has been conceived to solve such a problem and is aimed at providing a factor analysis method for detecting an error in a wafer pattern ascribable to a mask pattern error and an error in a wafer pattern ascribable to another reason while distinguishing between them.
The above objects of the present invention are achieved by a method of analyzing factor responsible for errors in a wafer pattern formed on a semiconductor wafer. In the factor analyzing method, a first mask is placed in a first position within an etching chamber. A mask pattern is formed by etching the first mask. A second mask is placed in a second position within the etching chamber such that an overlap region exists between a portion of the first mask and a portion of the second mask, provided that the first mask is set in the first position. A mask pattern is formed by etching the second mask. A wafer pattern corresponding to a single shot region is formed on the semiconductor wafer by exposing the semiconductor wafer through use of the first mask. A wafer pattern corresponding to a single shot region is formed on the semiconductor wafer by exposing the semiconductor wafer through use of the second mask. Finally, there are detected a dimensional difference ascribable to a difference between mask patterns and a dimensional difference ascribable to another reason while distinguishing the dimensional differences from each other, by comparison between the size of the wafer pattern which is included in an area (first overlap region) within the single shot region formed through use of the first mask and which corresponds to the overlap region and the size of the wafer pattern which is included in an area (second overlap region) within the single shot region formed through the second mask and which corresponds to the overlap region.
The above objects of the present invention are also achieved by an apparatus for producing a mask pattern by etching a photolithographic mask. The apparatus includes an etching chamber for etching a mask pattern. The apparatus also includes a mask table which retains a mask within the etching chamber and can hold the mask at a first position and a second position such that an overlap region exists between a portion of the mask set in the first position and a portion of the mask set in the second position, provided that the masks are set in the first position and the second position simultaneously.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

Method of analyzing factor responsible for errors in wafer pattern, and apparatus for producing photolithographic mask