A fuel delivery module for an automotive fuel delivery system includes a reservoir and a fuel pump. The fuel pump delivers fuel from the tank to the reservoir via a fuel tank inlet and reservoir outlet and from the reservoir to the engine via a reservoir inlet and engine outlet. The reservoir is formed with a plurality of contaminant traps for collecting contaminants contained in the fuel as the fuel is pumped through the reservoir such that the contaminants settle unto said contaminant traps thereby reducing the amount of contaminants entering the reservoir inlet.

The present invention relates generally to fuel delivery modules for automotive fuel systems, and, more particularly, to fuel delivery modules having contaminant collection traps.
Automotive fuel systems typically include a reservoir in the fuel tank and a primary fuel pump submerged in the reservoir to supply fuel to the engine. The purpose of the reservoir is to. keep the primary pump inlet submerged under operating conditions which could otherwise expose the inlet, such as when the vehicle is parked on an incline with an almost empty fuel tank or during cornering maneuvers wherein fuel moves away from the fuel inlet. A secondary pump is dedicated to filling the reservoir. In such systems, the primary pump delivers fuel from the reservoir to the engine and the secondary pump delivers fuel from the tank to the reservoir. In addition, filters may be used in cooperation with the inlet to the pumps to filter any contaminants in the fuel. The reservoir, fuel pumps and other components are typically, collectively referred to as a fuel delivery module, which will be used herein.
The inventors of the present invention have recognized certain disadvantages with these systems. For example, because the inlets to the primary and secondary pumps may require a filter, the fuel delivery module may include a large number of associated component parts resulting in a relatively large size to accommodate the components and filters. In addition, the filters may become prematurely occluded with contaminants due to the relatively large amount of contaminants that may be contained within the fuel, thereby decreasing the service life of the filter. Also, these filters may not be effective in filtering relatively small contaminants, which may prematurely wear the components of the primary pump, such as the fuel pump impeller, as well as adversely effect the fuel system. Thus, it is desirable to collect and trap contaminants in the fuel prior to the contaminants reaching the inlet to the primary pump.
An object of the present invention is to reduce the amount of contaminants entering a primary fuel pump. This object is achieved, and disadvantages of prior art approaches are overcome, by providing a novel fuel delivery module for an automotive fuel system. In one particular aspect of the invention, the fuel delivery module includes a reservoir having a bottom and a side. The reservoir stores a portion of the fuel stored in the fuel tank. A fuel pump is disposed within the reservoir and has a fuel tank inlet, a reservoir outlet, a reservoir inlet and an engine outlet. The fuel pump pumps fuel from the tank to the reservoir via the fuel tank inlet and reservoir outlet and pumps fuel from the reservoir to the engine via the reservoir inlet and engine outlet. The fuel delivery module also includes a plurality of contaminant traps formed in the bottom of the reservoir for collecting contaminants contained in the fuel as fuel is pumped through the reservoir such that the contaminants settle into the contaminant traps thereby reducing the amount of contaminants entering the reservoir inlet of the fuel pump. In a preferred embodiment, the contaminant traps have an oblong-shaped cross-section for enhancing retention of the fuel contaminants within the traps.
Also, in a preferred embodiment, the fuel delivery module includes a deflector disposed within the reservoir for directing contaminants away from the reservoir inlet of the fuel pump and toward the contaminant traps.
An advantage of the present invention is that the number of fuel filters used for the fuel delivery module is reduced.
Another advantage of the present invention is that the service life of the primary pump filter is increased.
Still another advantage of the present invention is that small contaminants are collected and contained so that it is unlikely that they will pass through the primary pump filter.
Other objects, features and advantages of the present invention will be readily appreciated by the reader of this specification.

Fuel delivery module for an automotive fuel system


Disclosed is a magnetoelectric (ME) composite including both a piezoelectric material and a magnetostrictive material, wherein a piezoelectric single crystal material having high piezoelectric properties is used as the piezoelectric material, and a metal magnetostrictive material having high magnetostrictive properties is used as the magnetostrictive material, thus achieving an ME composite having a layered structure via adhesion. When the ME layered composite is manufactured such that a <011> crystal orientation of the piezoelectric single crystal material is set to a thickness direction, high ME voltage coefficient, which is at least doubled, compared to a conventional <001> crystal orientation, can be obtained, and such an effect is further maximized in the resonance of the composite.

1. Field of the Invention
The present invention relates to a magnetoelectric composite and, more particularly, to a layered composite in which the orientation of a piezoelectric material layer is controlled such that a <011> orientation is set to a thickness direction.
2. Description of the Related Art
A magnetoelectric (ME) effect is a material property and is widely found in composite structures comprising magnetostrictive and piezoelectric materials.
The ME effect means that, when any material having properties in response to both a magnetic field and an electric field is exposed to a magnetic field, an electric voltage is generated, whereas when the material is exposed to an electric field, it is magnetized. Thus, in order to impart an ME effect to a material, the material should essentially have both ferromagnetic, ferrimagnetic, or antiferromagnetic properties in response to an external magnetic field, and ferroelectric, ferroelectric or antiferroelectric properties in response to an external electric field.
In order to successfully commercialize magnetic-electric sensors, magnetic sensors, electric sensors, photoelectronic devices, microwave electronic devices, magnetic-electric or electric-magnetic transducers, etc., which are recently studied, development and research into materials having both ferromagnetic and ferroelectric properties at room temperature and having ME effects at room temperature or higher corresponding to the actual usage temperature of devices is ongoing.
A typical example of a material having both ferromagnetic and ferroelectric properties at room temperature is bismuth manganate (BiMnO3). However, the ferromagnetic phase transition temperature and the ferroelectric phase transition temperature (Tc) of bismuth manganate are about 100K and 450K, respectively, and this material has both ferromagnetic and ferroelectric properties only at 100K or more (N. A. Hill, K. M. Rabe, Physical Review B vol 59 pp 8759 (1999)). When a predetermined material has both ferromagnetic and ferroelectric properties only in such a very low temperature range, it cannot be applied to a variety of devices useful at room temperature, making it impossible to achieve commercialization. On the other hand, yttrium manganate (YMnO3), which has antiferromagnetic and ferroelectric properties, has been developed as a material similar to bismuth manganate, but the antiferromagnetic phase transition temperature and the ferroelectric phase transition temperature of yttrium manganate are 70˜130K and 570˜990K, respectively, and this material has both antiferromagnetic and ferroelectric properties only at a temperature equal to or lower than 70˜130K, making it impossible to achieve commercialization, as in condensers using bismuth manganate (A. Filippetti, N. A. Hill, Journal of Magnetism and Magnetic Materials vol 236 pp 176 (2001)). On the other hand, in the case of a condenser composed of Bi4Ti3O12 having a layered perovskite structure, only ferroelectric properties are exhibited at room temperature, and ferromagnetic properties are not, and thus it cannot be applied to devices requiring both ferromagnetic and ferroelectric properties.
Since the 1890s, many attempts have been made to develop homogeneous materials having magnetoelectric effects, and thereby homogeneous materials such as Cr2O3, Pb(Fe1/2Nb1/2)O3, BaMeO4 (Me=Mn, Fe, Co, Ni), Cr2BeO4, BiFeO3, etc., have been found to have magnetoelectric effects (G. Smolenskii and V. A. Ioffe, Colloque International du Magnetisme, Communication No 711958; G. A. Smolenskii and I. E. Chupis, Problems in Solid State Physics (Mir Publishers, Moscow, 1984; I. H. Ismailzade, V. I. Nesternko, F. A. Mirishli, and P. G. Rustamov, Phys. Status Solidi 57 99 (1980)). However, such materials are inappropriate for use in actual devices because the magnetoelectric coefficient is very low to the level of 0.001˜0.02 volt/cm·Oe and the temperatures at which magnetoelectric effects are shown are mostly as low as 0° C. or less.
In order to increase the very low magnetoelectric coefficient of single-phase materials as mentioned above, research has been conducted on developing composite materials having high magnetoelectric coefficients at room temperature or higher by mixing a material in response to a magnetic field with a material in response to an electric field. A typical composite material, which exhibits an magnetoelectric effect at room temperature or higher, is exemplified by Terfenol-D (a magnetostrictive metal in response to a magnetic field)/PZT (a ferroelectric oxide in response to an electric field)/Terfenol-D.
The Terfenol-D/PZT/Terfenol-D composite material is very unfavorable in terms of price because Terfenol-D is an expensive rare earth metal compound, and the magnetoelectric effect of the Terfenol-D/PZT/Terfenol-D composite material may considerably vary depending on the adhesion properties.
Also, the maximum magnetoelectric coefficient of the Terfenol-D/PZT/Terfenol-D composite material is about 10 volt/cm·Oe, which is higher than the magnetoelectric coefficients of single-phase magnetoelectric materials developed to date, but has to be further increased so that such a composite material can be applied to actual devices (J. G. Wan, J.-M. Liu, H. L. W. Chand et al. Journal of Applied Physics, Vol 93, No 12, pp 9916˜9919 (2003); Jungho Ryu, Shashank Priya, Kenji Uchino, and Hyoun-Ee Kim, Journal of the American Ceramic Society Vol 84, No 12, pp 2905˜2908 (2001)).
FIG. 1 illustrates a voltage generation principle of a conventional ME (MagnetoEletric) particulate composite, FIG. 2 illustrates the maximum magnetoelectric coefficient (αME) and the structure of the conventional ME particulate composite, FIG. 3 illustrates a voltage generation principle of an ME layered composite, and FIG. 4 illustrates the Terfenol-D/PZT/Terfenol-D composite. The layered composite of FIG. 4 is configured such that the piezoelectric material whose orientation is not taken into consideration because of the use of the piezoelectric ceramic PZT is layered with the metal magnetostrictive material Terfenol-D.
As illustrated in FIGS. 1 to 4, when a magnetic field is applied, the magnetostrictive material is deformed, and voltage is generated from the piezoelectric material due to generation of stress resulting from such deformation. As mentioned above, in the case of the Ni or Co-ferrite/PZT particulate composite, the maximum magnetoelectric coefficient (αME) is about 100 mV/cm·Oe. The layered composite such as Terfenol-D/PZT/Terfenol-D has a maximum magnetoelectric coefficient (αME) of about 10 volt/cm·Oe, which is increased by about 100 times compared to that of the ME particulate composite, not enough to apply it to actual devices.

KOREA INSTITUTE OF MACHINERY AND MATERIALS


Security apparatus is provided for the display of battery operated hand-held electronic devices. It includes a electronic recoiler device that combines the function of tethering the displayed devices while at the same time providing the power required by each of the displayed devices by means of a continuous electrical connection from a power supply to each displayed device. It also provides wire and wireless alarm functions, as well as visual perpetrator identification. The apparatus also provides specific product information and comparative product information to the potential customer by visual and audible means.

1. Field of the Invention
The present invention relates to an apparatus for securely displaying, marketing and recharging battery operated, hand-held electronic devices. In particular, the present invention relates to a display apparatus that interactively delivers product information about a device selected by a potential customer from the display, collects and transmits marketing information about the selected device, while allowing the potential customer to hold the device at a limited distance from a display which automatically retracts and correctly positions the hand-held device on the display after its release, and more particularly, to such a display apparatus that is capable of charging the battery of the device while at the same time protecting the device against pilferage with wired and wireless alarms controlled by the display apparatus.
2. Description of Prior Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
With the growth of electronic devices in general, and the ability to miniaturize such devices in particular, light weight, battery operated, hand-held devices have become pervasive. Such devices include mobile phones, digital cameras, global positioning systems and hand-held computers, as well as music recording/playback units, and are sold to the public in a wide range of retail stores.
To properly market such devices, research indicates that consumers need to assure themselves that the device can be used comfortably and easily manipulated in the hands of the prospective consumer. In other words, the consumer must be free to hold and handle the device to make sure it is suitable. However, by allowing a consumer to inspect the item in that manner, the retailer is subjected to the possibility of substantial loss through theft and other forms of shrinkage and breakage. Currently, the shrinkage of small portable electronic devices is estimated to be as much as about 20%.
It is also important for the marketing of such devices that the devices be displayed in the proper orientation, that is, the devices must always be presented to the potential consumer in an upright position. That requirement is successfully dealt with in U.S. Pat. No. 6,659,382, entitled "Security Device For Display of Hand Held Items" issued to Richard Ryczek on Dec. 9, 2003 and owned by the assignee of the present application, which is herein incorporated by reference in its entirety.
In the apparatus described in that patent, the displayed device is attached to a support by a tether such that it can be moved away from the support and held by the potential consumer. A positioning system is provided so that when the hand-held device is retracted, the male component of the clamp that engages the device can be received in the female component on the support in only a single relative orientation. That or a similar positioning system may be used with the present invention, as explained below.
Various attempts have been made to make retail displays which allow manipulation of displayed devices while attempting to prevent theft. For example, U.S. Pat. No. 5,246,183 issued on Sep. 21, 1993 to Leyden discloses a tethering device for use in locations such as motel rooms that allows a remote control to be used but prevents its removal from the room. A spring in combination with a spool and cable allows a user to pull the hand-held remote control from a fixed position and automatically returns the hand-held remote control back to its original location. However, the Lyden apparatus is not a display device for marketing. It does not guide the displayed item after release into a desired upright display position.
While there have been a number of holders for hand-held telephones, hand-held computers and the like, they have been designed to facilitate carrying and using the device rather than for security in display and marketing. Prior to the device disclosed in the aforementioned Ryczek patent, there was no apparatus designed for securing a mobile phone on a display. There were, however, various devices that achieve the reverse. Such devices come with a variety of quick release mechanisms. See for example U.S. Pat. No. 5,903,645 issued on May 11, 1999 to Tsay and U.S. Pat. No. 5,555,302 issued on Sep. 10, 1996 to Wang.
U.S. Pat. No. 6,002,921 issued on Dec. 14, 1999 to Pfahlert discloses a lockable cradle for holding a radiotelephone for use in vehicles that is released by a radio signal. That vehicle mounted apparatus must be of a special construction and size to mate with the security system having grooves. Moreover, that apparatus is not designed for use in display systems, with existing devices, nor does it include a retracting and positioning system of the present invention.
The apparatus disclosed in the aforementioned Ryczek patent was the first apparatus of its type to fulfill the above noted requirements. The apparatus disclosed in that patent was designed specifically for displaying mobile phones and other hand-held devices. It includes three major components: a clamping system, a retracting system and the positioning system briefly described above.
The clamping system consists of two parts which are fastened together around a fitting attached to the end of a cord. The fitting has a hole drilled through it to allow such a fastening. A single security screw or bolt holds the two parts together with a key required to turn the head of the bolt or screw. The clamping system is locked onto the fitting and cannot be removed without the proper key. The clamping system has a lip on two opposite sides which prevents a person from removing the hand held device when the clamping system is fastened to the fitting and the hand held device is within the lips of the clamping system and attaches to a cable with a device also having a positioning guide to assure proper orientation of the hand-held device on display.
The retracting system includes a coil spring, a spool and a cord mounted in a common decorative support on which the displayed device rests. One end of the coil spring connects to the spool and the other end is attached to the support. The cord is wrapped around the spool with one end attached to the spool and the other end attached to the mobile phone. When the displayed device is removed from the support, the spool is turned and the coil spring is placed in tension. When the displayed device is released, the coil spring returns the spool to its original position.
The positioning system is provided to bring the displayed device back to its desired display position. The cord attached to the spool and the displayed device is made from a relatively stiff material such as braided steel wire or cable. Thus, if the cord is pulled from the display unit and the displayed device is twisted or turned, the cord will develop a counter force to return the displayed device, upon release, to the original, upright position.
To guide the device back into the proper position, the cord has on the end that emerges from the support a first half of a positioning system which connects to the clamping system. The positioning system comprises interlocking or complementary male and female fittings. The fitting attached to the end of the cord may be either male or female with a corresponding mating fitting mounted on the support. The cross-section of the male-female fitting pair may be of any shape other than circular with ovoid shapes preferred and cross-sectional ovoid shapes having guiding ribs contained within the ovoid female cross-section or on the exterior of the male ovoid cross-section most preferred. A non-circular shape, such as an ovoid, along with the ribs will assure that when the male fitting enters its female counterpart, the orientation of the fitting at the end of the cord will be the same as when the fitting, clamping system, or any device held within the clamping system, was pulled. The ribs assist with the guidance of the male fitting into the female fitting and assure that the fitting will return to its intended display orientation. Thus, the security display apparatus of the patent meets the needs of consumers and merchants by enabling a potential purchaser to conveniently examine a hand-held device while preventing its theft and guaranteeing its return to a suitable display position when released after examination.
The aforementioned display apparatus of the Ryczek patent does not address the issue of providing an alarm to alert store and security personnel if a displayed electronic device is removed from the clamping device or if the tether connecting the electronic device to the display apparatus is cut or if the electronic device is removed from the store or display area. Nor does it address the issue of providing an audible alarm if a displayed electronic device is tampered with by removal of the power plug from the device or removal of the device itself from the means used to secure it to the security tether or if the electronic device is removed from the store or display area. It does not have the capability of wirelessly transmitting an alarm signal to security personnel at a location remote from the display or of displaying a visual alert on a video display that forms part of the display apparatus. All of the above are addressed by the apparatus of the instant invention.
In addition, the Rycek display apparatus does not provide a means of interactively providing product information relating to a particular device of interest to a potential customer or of interactively providing information for training sales personnel, as is provided by the apparatus of the instant invention.
Due to the high rate of shrinkage of hand-held consumer electronics stocks, there is a need not only to deter pilferage of such items on display by tethering and clamping the device but also for alerting store and security personnel by alarm and visual means if the device is removed from the clamp, or if the tether or power supply cord are severed.
Because the areas in which such hand-held consumer electronic devices are displayed are often crowded there is also a need to visually identify the perpetrator of a theft or attempted theft of the displayed devices.
Because of the manifold features of the many models and brands of hand-held consumer electronic devices such as cellular phones, digital cameras, global positioning systems and hand-held computers, as well as music recording/playback units, there is a need to conveniently, effectively and interactively provide product information and comparisons about a device selected by a potential customer from the display apparatus.
There is, in addition, a need to interactively train sales personnel on the features and comparative features of the many models and brands of handheld consumer electronic devices such as cellular phones, digital cameras, global positioning systems and hand-held computers, as well as music recording/playback units.
There is a further need to immediately obtain information on customer preferences, for use in marketing these devices, for any one or all of the displayed handheld consumer electronic devices.

Apparatus for secure display, interactive delivery of product information and charging of battery-operated hand held electronic devices


A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.

This invention is directed generally to digital systems, and in particular to a semiconductor memory system in the form of a wafer scale integrated array of substantially identically formed memory-containing cells.
Digital systems of virtually every type use some form of secondary memory (primary memory being typically random access memory that form main, cache, and other memory from which operating systems and applications programs are run). Preferred secondary memory would be semiconductor of one form or another due to such advantages as speed of operation and small size. But, due the fact that the quantity of data to be stored is often very large, that it be retained for long periods of time, and with some permanence (i.e., be impervious to power loss/outages), other forms of secondary storage are used. Often these other forms of secondary storage are of the type using magnetic media (e.g., disk or tape). The principal differences between the primary and secondary storage are two: access speed and capacity. Thus, secondary storage often provides the advantage of very high storage capacity, accompanied by the relative disadvantage of undesirable access times. This is among the reasons, as will be evident to those of ordinary skill in this art, that such schemes as virtual memory have been implemented to take advantage of the high storage capacity offered by secondary storage, while masking the relatively slow data access speeds encountered.
There have been attempts to construct secondary storage systems using solid state, semiconductor memory devices by placing more and more memory circuitry onto each chip, thereby increasing circuit size and complexity. However, as circuit size increases, the chances of flaws forming in the circuit also increases, tending to reduce the yield of useable chips from a wafer. Yet other approaches propose mechanically interconnecting integrated circuit memory devices to construct a large scale memory system. However, the necessary chip-to-chip connections in such systems which tend to reduce circuit speed, introduce noise, and give rise to reliability problems caused by mechanical failure. Also, driver circuits are often needed to provide the necessary drive current for signals that are brought off-chip, at the expense of circuit area. There are also economic considerations: Memory systems developed from multiple chips, in addition to being labor intensive, are subject to higher packaging and manufacturing costs than if implemented in fewer (or, ideally, one) chips. Thus, these latter approaches, albeit successful to an extent, are accompanied by problems that make them attractive mostly when other available forms of secondary storage (i.e., disk systems) are, for whatever reason, not acceptable for the particular application. In sum, all these, and other, reasons combine to make the prospect of a memory system capable of being formed on an entire semiconductor wafer very attractive.
Since commercial introduction of integrated circuitry, there has been a continuing trend toward putting more and more circuitry onto smaller and smaller areas of integrated circuit chips. It is not too surprising, therefore, to see that very large scale integration (VLSI) techniques are giving way to wafer scale integration as a response to the increasing demand for higher integrated circuit density. Wafer scale integration provides a large density advantage over VLSI.
Wafer scale integration seeks to assemble an entire system on a single wafer, rather than partition the wafer into chips that each carry smaller portions of a system, and thereby requires the expense of individual packaging. However, yield has been one problem that works against successful wafer scale integration. Fabrication flaws must be overcome in order to effectively and economically use wafer scale integration techniques.
There are a number of wafer scale techniques known today aimed at overcoming the yield problem. One such technique utilizes redundant copies of a digital system formed on a wafer, and provides selection circuitry integrated in each of the systems. The selection circuitry intercouples portions of each copy of the system in a manner that results in one, flaw-free, working version of the desired digital system. An example of this technique can be seen in U.S. Pat. No. 4,621,201. Other approaches can be found in W. R. Moore, "A Review of Fault Tolerant Techniques for the Enhancement of Integrated Circuit Yield," Proc. of the IEEE, Vol. 74, May, 1986, pp. 684-698; W. Chen, et al., "A WSI Approach Towards Defect/Fault Tolerant Reconfigurable Serial Systems," IEEE Journal of Solid State Circuits, Vol. 23, June, 1988, pp. 639-646; J. Trilhe and G. Saucier, "WSI--The Challenge of the Future"; Proc. IEEE Conference on VLSI and Computers, May, 1987. These interconnecting techniques can tend to use more wafer area, create more complex circuitry, and pose a routing problem for signal lines.
Yet another, more simplified approach, is to have bi-directional busses connecting each rectangular cell to its four adjacent neighbors. The input to the cell is selected from one of the four neighbors, and the output driven to a different neighbor. The main problem with such a structure is that every cell must have two operating neighbor cells in order to be included in a linear array or "chain" of such cells. Also, it is difficult to configure a chain in such a way that both the beginning and end are on a wafer periphery where they may be connected to bonding pads.
A more practical cell interconnection approach has been to provide separate inputs and outputs between a cell and each of its neighbors to increase interconnection flexibility. In this approach, the cell carries a logic function whose input may be selected from any one of the four neighbors, and whose output is, in turn, communicated to the selection logic associated with each boundary (which also receives inputs from each of the other boundaries). Although this structure provides sufficient paths to connect around many defective cells, there are several drawbacks: The delay between the logic functions of any two cells depends upon the number of individual selection logic elements between them. Since this is not known at the outset, the delay is unbounded. Also, the amount of logic to implement the selection logic (e.g., multiplexers) may take up a significant area of the cell, and particularly so when the information is communicated in parallel instead of bit serial form. Further, the routing of the necessary signal lines tends to be irregular and confused; since every side must connect to every other side, it is possible that interference with logic routing lines will be encountered. Further still, it is difficult to find an acceptable configuration algorithm that allows connection to any reachable cell. This and similar structures are discussed in T. Leighton and C. E. Leiserson, "Algorithms for Integrating Wafer Scale Systolic Arrays," Systolic Signal Processing Systems, Dekker, 1987, pp. 299-326; M. J. Shute and P. E. Osman, "COBWEB--A Reduction Architecture," Wafer Scale Integration; Adam Hilger, 1986, pp. 169-178; and M. G. H. Katevenis and M. G. Blatt, "Switch Design for Soft-Configurable WSI Systems"; Proc. IFIP Int'l Workshop on WSI, Elsevier Science Publishers, 1986, pp. 255-270.
A modification of the foregoing approach is implemented in a wafer-scale integrated memory system. Each cell carries a pair of shift registers that are used, when connected to neighbor cells, to form a spiral, consisting of a single, long shift register chain. The first half of the path through the shift register chain is formed by one of the shift registers of each cell; the return path contains the second shift register of each cell. There are two inputs to the cell from each neighbor cell; one input (from each neighbor) is multiplexed to the input of one of the shift registers, the other input (from each boundary) to the other shift register. In similar fashion the outputs of each shift register are multiplexed to one of two outputs to each neighbor. While this scheme may simplify the multiplex circuitry used in the connection techniques discussed above, it still requires more than is believed needed. Further, known implementations of the approach use a cell-to-cell connection scheme that lacks flexibility, resulting, it is believed, in a less than optimum harvest of those cells available for inclusion in the chain. (As used herein, "harvest" is used to refer to those cells that are actually included in any interconnection of the cells, relative to the number of cells on the wafer that operable.) An example of this approach is found in U.S. Pat. No. 3,913,072.
There have been also approaches that have amplified the aforementioned basic structure, adding connections to additional neighbors (hexagonal arrays--see M.J. Shute, supra) or neighbors that are not edge-adjacent (i.e., corner neighbors). These designs, however, tend to suffer from the same general problems as the rectangular approach, both offer some increased harvest at the expense of extra cell area and layout difficulties.

Memory system using linear array wafer scale integration architecture


Compositions of angiostatic agents for treating GLC1A glaucoma and methods for their use are disclosed.

1. Field of the Invention
This invention is directed to the use of angiostatic agents for treating glaucoma or ocular hypertension resulting from altered expression of the GLC1A gene (hereinafter GLC1A or 1q glaucoma) in an individual.
2. Description of Related Art
The glaucomas are a heterogeneous group of optic neuropathies characterized by cupping of the optic nerve head, thinning of the retinal nerve fiber layer due to loss of retinal ganglion cells, and specific pathognomonic changes in visual fields. Elevated intraocular pressure (IOP) is a very important risk factor for the development of most common forms of glaucoma (Sommer A, et al., "Relationship Between Intraocular Pressure and Primary Open Angle Glaucoma Among White and Black Americans," Arch. Ophthalmol., 109:1090-1095, (1991)).
A family history of glaucoma also is an important risk factor for the development of glaucoma. It appears that a significant portion of glaucoma is inherited (or at least the risk for developing glaucoma is inherited) although it is often difficult to establish clear inheritance patterns for most of the glaucomas because of the disease onset late in life and the slowly progressive clinical manifestations of the disease. Despite these problems, a number of families with heritable forms of glaucoma have been identified and these families have been used to map a variety of glaucoma genes (Sheffield, et al., "Genetic Linkage of Familial Open Angle Glaucoma to Chromosome 1q21-q31," Nature Genetics, 4:47-50 (1993); Sarfarazi, et al., "Assignment of a Locus (GLC3A) for Primary Congenital Glaucoma (Buphthalmos) to 2p21 and Evidence for Genetic Heterogeneity," Genomics, 30:171-177 (1995); Akarsu, et al., "A Second Locus (GLC3B) for Primary Congenital Glaucoma (Buphthalmos) Maps to the 1p36 Region," Human Molecular Genetics, 5(8):1199-1203 (1996); Stoilova, et al., "Localization of a Locus (GLC1B) for Adult-Onset Primary Open Angle Glaucoma to the 2cen-q13 Region," Genomics, 36:142-150 (1996); Wirtz, et al., "Mapping a Gene for Adult-Onset Primary Open-Angle Glaucoma to Chromosome 3q," Am. J Hum. Genet., 60:296-304 (1997); Andersen, et al., "A Gene Responsible for the Pigment Dispersion Syndrome Maps to Chromosome 7q35-q36," Arch. Ophthalmol, 115:384-388 (1997). The first glaucoma gene mapped (GLC1A) was in a large family with autosomal dominant inherited juvenile glaucoma (JG). This disease is characterized by an early disease onset (late teens to early 20s), relatively high IOPs, and general resistance to conventional pharmacological IOP lowering therapy. The GLC1A gene was mapped by positional cloning and linkage analysis to chromosome 1q22-q25 (Sheffield et al, Id), and a number of other groups have confirmed the 1q location of this juvenile glaucoma gene (Richards, et al., "Mapping of a Gene for Autosomal Dominant Juvenile-Onset Open-Angle Glaucoma to Chromosome 1q," Am. J. Hum. Genet., 54:62-70 (1994); Morissette, et al., "A Common Gene for Juvenile and Adult-Onset Primary Open-Angle Glaucomas Confined on Chromosome 1q," Am. J. Hum. Genet., 56:1431-1442 (1995); Wiggs, et al., "Genetic Linkage of Autosomal Dominant Juvenile Glaucoma to lq21-q31 in Three Affected Pedigrees," Genomics, 21:299-303 (1994); Meyer, et al., "Age-Dependent Penetrance and Mapping of the Locus for Juvenile and Early-Onset Open-Angle Glaucoma on Chromosome 1q (GLC1A) in a French Family," Hum. Genet., 98:567-571 (1996); Graff, et al., "Confirmation of Linkage to 1q21-31 in a Danish Autosomal Dominant Juvenile-Onset Glaucoma Family and Evidence of Genetic Heterogeneity," Hum. Genet., 96:285-289 (1995). Glaucoma due to the GLC1A gene is often referred to as 1q glaucoma.
The GLC1A gene was identified as encoding a 57 kD protein expressed in the trabecular meshwork (TM) (Stone, et al., "Identification of a Gene That Causes Primary Open Angle Glaucoma," Science, 275:668-670 (1997). The expression of the GLC1A gene, and the encoded TM protein, is up-regulated by glucocorticoids (Polansky, et al., "Eicosanoid Production and Glucocorticoid Regulatory Mechanisms in Cultured Human Trabecular Meshwork Cells," The Ocular Effects of Prostaglandins and Other Elcosanolds, pp. 113-138 (1989); Polansky, et al., "In Vitro Correlates of Glucocorticoid Effects on Intraocular Pressure," Glaucoma Update IV (1991); and Polansky, et al., "Cellular Pharmacology and Molecular Biology of the Trabecular Meshwork Inducible Glucocorticoid Response Gene Product," Ophthalmologica, 211:126-139 (1997)). This TM protein is also known as TIGR (trabecular meshwork inducible glucocorticoid response) (Polansky, Id). The glucocorticoid-induction of this TM protein has been suggested to be involved in the generation of glucocorticoid-induced ocular hypertension and glaucoma (Polansky, Id).
The GLC1 A gene is expressed in other ocular tissues such as the ciliary epithelium (Ortego, et al., "Cloning and Characterization of Subtracted cDNAs from a Human Ciliary Body Library Encoding TIGR, a Protein Involved in Juvenile Open Angle Glaucoma with Homology to Myosin and Olfactomedin," FEBS Letters, 413:349-353 (1997)) and the retina (Kubota, et al., "A Novel Myosin-like Protein (Myocilin) Expressed in the Connecting Cilium of the Photoreceptor: Molecular Cloning, Tissue Expression, and Chromosomal Mapping," Genomics, 41:360-369 (1997)). The gene is referred to by several names including GLC1A (Sheffield, supra, Sunden, et al., "Fine Mapping of the Autosomal Dominant Juvenile Open Angle Glaucoma (GLC1A) Region and Evaluation of Candidate Genes," Genome Research, 6:862-869 (1996); Stone, et al., supra), TIGR (Polansky supra, Ortego, supra), and myocilin (Kubota, supra). Mutations GLC1A are not only responsible for juvenile glaucoma, but also a significant subset of adult onset primary open angle glaucoma (Stone, et al., supra, Adam, et al., "Recurrent Mutations in a Single Exon Encoding the Evolutionarily Conserved Olfactomedin-Homology Domain of TIGR in Familial Open-Angle Glaucoma," Human Molecular Genetics, 6(12):2091-2097 (1997)). The 1q glaucoma gene (GLC1A, TIGR) is the subject of Nguyen, et al., U.S. Pat. No. 5,606,043, issued Feb. 25, 1997.
Glucocorticoids have been associated with the development of ocular hypertension and primary open angle glaucoma (Kass, et al., "Corticosteroid-Induced Glaucoma, In Ritch, R., Shields, M. B., Krupin, T. (eds.)," The Glaucomas, The C. V. Mosby Company, St. Louis, Mo., pp. 1161-1168 (1989); DeSantis, et al., Dexamethasone-Induction of Ocular Hypertension in the Primate, ARVO Abstracts. Invest. Ophthalmol Vis. Sci., 31(Suppl.):99 (1990); Knepper, et al., "Intraocular Pressure and Glycosaminoglycan Distribution in the Rabbit Eye: Effect of Age and Dexamethasone," Exp. Eye Res., 27:567-575 (1978); Francois, et al., Ultrastructural and Morphometric Study of Corticosteroid Glaucoma in Rabbits, Ophthalmic Res., 16:168-178 (1984); Lorenzetti, O. J., "Effects of Corticosteroids on Ocular Dynamics in Rabbits," J. Pharmacol Exp. Therap., 175:763-772 (1970); and Zhan, et al., "Steroid Glaucoma: Corticosteroid-Induced Ocular Hypertension in Cats," Exp. Eye Res., 54:211-218 (1992)). Glaucoma patients have also been reported to have higher levels of the endogenous glucocorticoid, cortisol (Rozsival, et al., "Aqueous Humour and Plasma Cortisol Levels in Glaucoma and Cataract Patients," Current Eye Research, 1:391-396 (1981); Ray, et al., "Plasma Cortisol in Glaucoma," Ann. Ophthalmol., 9:1151-1154 (1977); and Schwartz, et al., "Increased Plasma Free Cortisol in Ocular Hypertension and Open Angle Glaucoma," Arch. Ophthalmol., 105:1060-1065 (1987)).
It is known that trabecular meshwork cells have glucocorticoid receptors and that glucocorticoid binding with these receptors causes a change in trabecular meshwork cell gene expression. Known manifestations of this change include a reorganization of the cytoskeleton (Wilson, et al., Dexamethasone Induced Ultrastructural Changes in Cultured Human Trabecular Meshwork Cells, Cur. Eye Res., 12:783-793 (1993), and Clark, et al., "Glucocorticoid-Induced Formation of Cross-Linked Actin Networks in Cultured Human Trabecular Meshwork Cells," Invest. Ophthalmol. Vis. Sci., 35:281-294 (1994)) and increased deposition of the extracellular matrix material in trabecular meshwork cells. As a result, the trabecular meshwork becomes "clogged" and unable to perform one of its most critical functions, that is, serving as a gateway for aqueous humor flow from the anterior chamber of the eye. When the aqueous humor flow out of the eye via the trabecular meshwork is diminished, the intraocular pressure of the eye rises. If this state of elevated intraocular pressure is maintained or frequently occurs, the optic nerve head can be damaged resulting in the loss of visual field. Loss of visual field is the hallmark symptom associated with glaucoma.
Endogenous glucocorticoids may be responsible for producing the changes in the trabecular meshwork that lead to ocular hypertension and glaucoma.
In summary, the GLC1A gene product can lead to the development of ocular hypertension and glaucoma in one of two ways: (1) mutations in GLC1A are responsible for most forms of juvenile glaucoma and a subset of adult onset POAG or (2) exposure of some individuals to glucocorticoids leads to increased GLC1A expression in the TM which causes increased aqueous humor outflow resistance and the development of ocular hypertension. The precise mechanism(s) responsible for GLC1A effects on IOP are currently unknown.
Steroids functioning to inhibit angiogenesis in the presence of heparin or specific heparin fragments are disclosed in Crum, et al., "A New Class of Steroids Inhibits Angiogenesis in the Presence of Heparin or a Heparin Fragment," Science, 230:1375-1378 (Dec. 20, 1985). The authors refer to such steroids as "angiostatic" steroids. Included within the new class of steroids found to be angiostatic are the dihydro and tetrahydro metabolites of cortisol and cortexolone. In a follow-up study directed to testing a hypothesis as to the mechanism by which the steroids inhibit angiogenesis, it was shown that heparin/angiostatic steroid compositions cause dissolution of the basement membrane scaffolding to which anchorage dependent endothelia are attached resulting in capillary involution; see, Ingber, et al., "A Possible Mechanism for Inhibition of Angiogenesis by Angiostatic Steroids: Induction of Capillary Basement Membrane Dissolution," Endocrinology, 119:1768-1775 (1986).
A group of tetrahydro steroids useful in inhibiting angiogenesis is disclosed in International Patent Application No. PCT/US86/02189, Aristoff, et al., (The Upjohn Company). The compounds are disclosed for use in treating head trauma, spinal trauma, septic or traumatic shock, stroke and hemorrhage shock. In addition, the patent application discusses the utility of these compounds in embryo implantation and in the treatment of cancer, arthritis and arteriosclerosis. The compounds are not disclosed for ophthalmic use.
Tetrahydrocortisol (THF) has been disclosed for its use in lowering the intraocular pressure (IOP) of rabbits made hypertensive with dexamethasone alone, or with dexamethasone/5-beta-dihydrocortisol; see Southren, et al., "Intraocular Hypotensive Effect of a Topically Applied Cortisol Metabolite: 3-alpha, 5-beta-tetrahydrocortisol," Investigative Ophthalmology and Visual Science, 28 (May, 1987). The authors suggest THF may be useful as an antiglaucoma agent. In U.S. Pat. No. 4,863,912, issued to Southren et al. on Sep. 5, 1989, pharmaceutical compositions containing THF and a method for using these compositions to control intraocular pressure are disclosed. THF has been disclosed as an angiostatic steroid in Folkman, et al., "Angiostatic Steroids," Ann. Surg., 206(3) (1987) wherein it is suggested angiostatic steroids may have potential use for diseases dominated by abnormal neovascularization, including diabetic retinopathy, neovascular glaucoma and retrolental fibroplasia.

Angiostatic agents and methods and compositions for controlling ocular hypertension


A screw-shaped anchoring fixture for anchoring a prosthesis in the skull bone. The anchoring fixture comprises a main body configured to be implanted into the bone and a flange configured to function as a stop to prevent the main body from completely penetrating through the bone. The main body comprises a distal tapered apical portion, a first portion, and a second portion. The inner diameter of the second portion is greater than the inner diameter of the first portion. The method for inserting the anchoring fixture includes providing the anchoring fixture, drilling a hole, and inserting the anchoring fixture into the hole until the flange contacts the skull bone, wherein the hole has a diameter that is greater than the inner diameter of the first portion and less than the outer diameter of the second portion.

1. Field of the Invention
The present invention relates generally to hearing devices and, more particularly, to anchoring elements for bone anchored hearing devices.
2. Related Art
For persons who cannot benefit from traditional, air conduction hearing aids there are other types of hearing aids on the market commonly referred to as bone anchored hearing aids. Bone anchored hearing aids mechanically transmit sound information to a person's inner ear via the skull bone by means of a vibrator. Such hearing aid devices are typically connected to a percutaneous implant in the form of a titanium screw implanted in the skull bone behind the external ear so that sound is transmitted via the skull bone to the cochlea (inner ear). This enables the hearing aid to be effective regardless of whether there is disease or damage in the middle ear. Moreover, penetration of the skin makes the vibratory transmission very efficient.
Bone anchored hearing aids were initially developed to rehabilitate certain types of hearing-impaired patients. They may also be utilized for other indications such as stuttering and for certain non-medical applications. A bone anchored hearing aid may be connected to an implant by means of a bayonet coupling, a snap-in coupling, a magnetic coupling or the like. One example of this type of hearing aid device is the BAHA® bone anchored hearing aid, described in U.S. Pat. No. 4,498,461 and commercially available from Cochlear Bone Anchored Solutions AB (previously Entific Medical Systems AB) in Göteborg, Sweden.
The implant connecting the hearing aid to the skull generally comprises two components: a bone attachment piece that is attached or implanted directly into the skull bone and a skin penetrating piece coupled to the bone attachment piece. The reason for this two-piece design is that installation of the implant is occasionally performed in two steps. In the first step, the bone attachment piece is installed and the surrounding issue is allowed to heal for a period of time that may last up to a few months. In the second step, the skin penetrating piece is coupled to the bone attachment piece. In the event that the skin penetrating piece becomes damaged, it may be replaced without removing the anchoring fixture from the skull. Moreover, the hearing aid may be changed or upgraded if necessary, without removing the bone attachment piece from the skull.
Although conventional fixtures normally provide a certain degree of osseo-integration, a more effective integration between the implant screw and the skull bone is desired, for example, for patients having impaired bone quality. Moreover, loading of the implant at an earlier stage would also be desired.

Bone anchor fixture for a medical prosthesis


For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.

1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device including a latency counter that delays an internal command signal.
2. Description of Related Art
A synchronous memory device, represented by a synchronous DRAM (Dynamic Random Access Memory), has been widely used for a main memory of a personal computer and the like. The synchronous memory device inputs or outputs data in synchronization with a clock signal supplied from a controller. Therefore, the use of a higher-speed clock leads to an increase in data transfer rate.
However, even in the synchronous DRAM, a DRAM core still operates in an analog mode, requiring a sense operation to amplify extremely weak electric charges. As a result, it is not possible to reduce the time required to output the first data after a read command is issued. Therefore, after a predetermined delay time has passed since the issuing of the read command, the first data are output in synchronization with an external clock signal.
The delay time in the read operation is usually referred to as "CAS latency," and is set to the integral multiple of a clock cycle. For example, when the CAS latency is five (CL=5), the first data are output in synchronization with an external clock signal that appears five cycles after a read command is captured in synchronization with an external clock signal. That is, five clock cycles later, the first data are output.
Such a delay is necessary even for a write operation. In the write operation, after a predetermined delay time has passed since the issuing of a write command, data need to be input sequentially in synchronization with external clock signal. The delay time in the write operation is usually referred to as "CAS write latency," and is set to the integral multiple of a clock cycle. For example, when the CAS write latency is five (CWL=5), the first data need to be input in synchronization with an external clock signal that appears five clock cycles after the write command is captured in synchronization with an external clock signal.
Moreover, what is employed by a DDR2 (Double Data Rate 2) or later model SDRAM is a Posted CAS method, which enables a controller to issue a read or write command to a synchronous memory device at an earlier timing than an original issuing timing. How far the command issuing timing is moved forward, i.e. the difference between the original timing at which the read or write command should be issued and the actual, earlier timing at which the read or write command is issued, is referred to as additive latency (AL). Therefore, in the read operation for example, the period required to start outputting read data after the read command is issued is defined as AL+CL.
When the Posted CAS method is employed, a semiconductor device (synchronous memory device) does not start a column-system control circuit immediately after a memory controller issues a read or write command. The semiconductor device needs to wait to start the column-system control circuit until the additive latency has passed. What is used for the above purpose is a FIFO circuit that delays a read or write command, which is supplied from the outside, in the semiconductor device. Such a FIFO circuit is generally referred to as a "latency counter" The most commonly used latency counter is a shift register.
An inventor of the present invention has previously proposed a new latency counter (Japanese Patent Application Laid-Open No. 2010-3397). The latency counter disclosed in Japanese Patent Application Laid-Open No. 2010-3397 uses a circuitry section, which selects whether a latency is an odd or even number, and a circuitry section, which gives a delay to an internal command signal at intervals of two clock cycles; the circuitry sections are connected in parallel to make circuits smaller in size and reduce power consumption. In recent years, the pace at which the wiring pitch is reduced has not kept up with the pace at which transistors become smaller in size. As a result, a new issue has arisen that as a circuit is made smaller in size, sufficient numbers of lines of the circuit cannot be formed on the top of the circuit.

This patent is subject to a terminal disclaimer.

Semiconductor device including latency counter


A permanent magnet material has a principal phase of TbCu7 type crystal structure and improved magnetic properties. This permanent magnet material is represented by the general formula: R1.sub.x R2.sub.y B.sub.z N.sub.u M.sub.100-x-y-z-u, wherein R1 is at least one rare earth element including Y, R2 is at least one element selected from the group consisting of Zr, Hf and Sc, M is at least one element selected from Fe and Co, x, y, z and u are atomic percents individually defined as x.gtoreq.2, y.gtoreq.0.01, 4.ltoreq.x+y.ltoreq.20, 0.ltoreq.z.ltoreq.10, and 0<u.ltoreq.20. The permanent magnet material has a principal phase of a TbCu.sub.7 type crystal structure. The permanent magnet material satisfies the relation of t.ltoreq.60 and .sigma./t.ltoreq.0.7, wherein t(nm) is an average crystal grain size of the principal phase and .sigma.(nm) is a standard deviation of the crystal grain size.

The invention relates to a permanent magnet material and a bonded magnet.
Hitherto, as a type of high-property permanent magnets of rare earth elements, Sm--Co magnets and Nd--Fe--B magnets and the like have been known. These high-property magnets are used in electric appliances such as a speaker, a motor and a measuring tool. As the demand for miniaturizing various electric appliances is elevated in recent years, the demand for developing a higher property permanent magnet is raised.
In compliance with such a demand, the inventors suggested a TbCu.sub.7 type compound and a nitride thereof which have a high saturation magnetization and excellent magnetic properties in Jpn. Pat. Appln. KOKAI Publication No. 6-172936 and Jpn. Pat. Appln. KOKAI Publication No. 9-74006.
The magnet material having the TbCu.sub.7 type crystal structure as a principal phase is generally produced via a rapid quenching process such as a melt spun process and a mechanical alloying process. However, magnetic properties of resulting magnet material are often changed by a condition of the above-mentioned process, so as to make it difficult to produce a high property magnet material stably.

Permanent magnet material and bonded magnet


The present invention provides an endless belt for an image forming apparatus having at least two layers of an inner layer and an outermost layer, in which the average regular reflectance of the surface of the outermost layer is 5.0% or more and the fluctuation of the regular reflectance of the surface of the outermost layer is kept within ±10%, and an image forming apparatus having the endless belt for an image forming apparatus.

1. Field of the Invention
The present invention relates to an endless belt for an image forming apparatus and the image forming apparatus having the endless belt. Particularly, the present invention relates to an intermediate transfer belt used for an image forming apparatus such as a copying machine, laser beam printer or facsimile, endless belt such as a transfer material carrying belt and image forming apparatus having the endless belt.
2. Description of the Related Art
First, a case of using an endless belt for an image forming apparatus as a transfer material carrying belt is described below.
FIG. 1 is an illustration showing a schematic configuration of an image forming apparatus (color image forming apparatus) having a transfer material carrying belt.
The color image forming apparatus having the configuration shown in FIG. 1 is provided with four drum-shaped photosensitive members (photosensitive drums) (photosensitive drums 1a, 1b, 1c and 1d) serving as image bearing members.
Moreover, charging means (charging units 2a, 2b, 2c and 2d) for uniformly charging the surfaces of the photosensitive drums, exposing means (laser scanners 3a, 3b, 3c and 3d) for irradiating the surfaces of the photosensitive members with laser beams the photosensitive drums in accordance with image information and forming an electrostatic latent image on surfaces of the photoconductor drums, developing means (development units 4a, 4b, 4c and 4d) for attaching toner to the electrostatic latent image and visualizing the image as a toner image, transfer means (transfer rollers 5a, 5b, 5c and 5d) for transferring the toner image to a transfer material (paper or OHP film) S and cleaning means (cleaners 6a, 6b, 6c and 6d) for removing transfer-residual toner left on surfaces of the photosensitive drums after transfer are arranged around the photosensitive drums 1a, 1b, 1c and 1d, in that order in the rotational direction (counterclockwise rotation in FIG. 1) of the photoconductor drums to constitute image forming portions of respective colors.
Furthermore, the photosensitive drums 1a, 1b, 1c and 1d, charging units 2a, 2b, 2c and 2d, development units 4a, 4b, 4c and 4d, and cleaners 6a, 6b, 6c and 6d are integrally formed into cartridges as shown in FIG. 1 to constitute process cartridges (process cartridges 7a, 7b, 7c and 7d).
The transfer material S is carried sequentially to the image forming portions of respective colors by a transfer material carrying belt 9, toner images of respective colors are transferred and sequentially superimposed, and a synthetic toner image is formed. Then, the synthetic toner image is fixed by fixing means (fixing unit 10) and discharged to the outside of the apparatus.
Next, a case of using an endless belt for an image forming apparatus as an intermediate transfer belt is described below.
FIG. 2 is an illustration showing a schematic configuration of an image forming apparatus (color image forming apparatus) having an intermediate transfer belt.
A color image forming apparatus having the configuration shown in FIG. 2 is provided with four drum-shaped photosensitive members (photosensitive drums) (photosensitive drums 1a, 1b, 1c and 1d) serving as image bearing members.
Moreover, charging means (charging units 2a, 2b, 2c and 2d) for uniformly charging the surfaces of the photosensitive drums, exposing means (laser scanners 3a, 3b, 3c and 3d) for irradiating the surfaces of the photosensitive drums with laser beams in accordance with image information and forming an electrostatic latent image on the surfaces of the photosensitive drums, developing means (development units 4a, 4b, 4c and 4d) for attaching toner to the electrostatic latent image and visualizing the image as a toner image, primary transferring means (primary transfer rollers 5pa, 5pb, 5pc and 5pd) for primarily transferring the toner image to an intermediate transfer belt 11 and cleaning means (cleaners 6a, 6b, 6c and 6d) for removing transfer-residual toner left on surfaces of the photosensitive drums after primary transfer are arranged around the photosensitive drums 1a, 1b, 1c and 1d in that order in accordance with the rotational direction (counterclockwise rotation in FIG. 2) of the photoconductor drums to constitute image forming portions of various colors.
Furthermore, the photoconductor drums 1a, 1b, 1c and 1d, charging units 2a, 2b, 2c and 2d, development units 4a, 4b, 4c and 4d, and cleaners 6a, 6b, 6c and 6d are integrally formed into cartridges as shown in FIG. 1 to constitute process cartridges (process cartridges 7a, 7b, 7c and 7d).
Toner images of respective colors are transferred and sequentially superimposed on the intermediate transfer belt 11 and a synthetic toner image is formed in the image forming portions of respective colors.
The transfer material S is carried to a portion between the intermediate transfer belt 11 and secondary transfer means (secondary transfer roller 5s) and a synthetic toner image is transferred and fixed by fixing means (fixing unit 10) and discharged to the outside of the apparatus.
As described above, the color image forming apparatus forms a color image (full color image) by superimposing images of four colors in total from first color to fourth color (generally, yellow, magenta, cyan and black) on a transfer material or intermediate transfer belt. Therefore, when writing start positions of four colors in the sub-scanning direction (moving direction of the transfer material or intermediate transfer belt) do not coincide with each other, a problem in images referred to as a color shift occurs. Moreover, as other factors for creating a color shift, there are a shift of writing start position in the main scanning direction (a direction vertical to the moving direction of a transfer material or an intermediate transfer belt) and a color shift due to the fluctuation of the primary scanning line width.
In order to rectifying the color shift in the sub-scanning direction or main scanning direction, it has been known to form a pattern for detecting a color shift on the transfer material carrying belt or intermediate transfer belt for each color, detect the pattern by a pair of optical sensors set on both sides of the downstream portion of the transfer material carrying belt or the downstream portion of the intermediate transfer belt and perform various adjustments such as exposure timing adjustment of an image forming portion and speed adjustment of a plurality of photoconductor drums, transfer material carrying belt or intermediate transfer belt.
FIG. 3 is an illustration for explaining color shift detecting means. Though the case of a transfer material carrying belt is used as an example, the same may be applied to the case of an intermediate transfer belt.
In FIG. 3, reference numeral 20 denotes a color shift detecting means which is constituted of a light emitting element and a light receiving element. Reference numeral 21 denotes a light emitting element which is an LED for emitting, for example, light with a wavelength of an infrared region. Reference numeral 22 denotes a light receiving element (such as a photosensor). Reference numeral 9 denotes a transfer material carrying belt and 23 denotes a pattern for detecting a color shift. Reference numeral 24 denotes a light emitting optical path extended from the light emitting element 21, and 25 denotes a light receiving optical path through which reflected light from the transfer material carrying belt 9 or color shift detecting pattern 23 is received by the light receiving element 22. A light emitting portion and light receiving portion are constituted of a regular reflection optical system using the transfer material carrying belt 9 as a reflection plane to detect the position of a color shift detecting pattern in accordance with the difference between reflectances of regularly reflected lights of the transfer material carrying belt 9 and color shift detecting pattern 23, i.e., the difference between regular reflectances.
Therefore, in the case of an endless belt used for an image forming apparatus, it is necessary that the regular reflectance of the surface is high in order to increase a difference in regular reflectance with reference to toner, and moreover it is necessary that abrasion resistance is high in order to minimize a lowering in the regular reflectance of the surface due to long time use.
From such a point of view, as an endless belt for an image forming apparatus, an endless belt made of polyimide and endless belt of a multilayer configuration using a hard coat material for the outermost layer has been proposed (see Japanese Patent Application Laid-Open Nos. H11-161036 and H11-024428).
However, when using polyimide for an endless belt, cost is liable to be raised because the reaction process is long. Moreover, the surface hardness is as low as the maximum pencil hardness of 2H. Therefore, when using the endless belt for a long time, the surface is shaved by a photosensitive member, roller and transfer material, irregularity occurs and the regular reflectance of the surface of the endless belt is lowered. When the regular reflectance of the endless belt is lowered, a difference in regular reflectance with reference to toner is reduced and thereby sufficient color-shift detecting performance cannot be obtained.
Moreover, some conventional endless belts of a multilayer configuration using a hard coat material for the outermost layer use fluorocarbon resin for the outermost layer in order to improve the releasability of toner. However, because the fluorocarbon resin is a low-refraction-index material, when detecting a color shift by using regular reflection on the surface of the endless belt, the difference between regular reflectances of toner and the surface is reduced. Therefore, an error factor such as noise is increased and it is difficult to exhibit stable color-shift detecting performance.
Furthermore, when using a conventional endless belt of a multilayer configuration, the color shift detecting performance may be particularly lowered. This is because the incident light of a color shift detecting sensor passes through the outermost layer of the endless belt of a multilayer configuration and reflects on the interface between the outermost layer and the inner layer, and the reflected light on the outer surface of the outermost layer interferes with the reflected light from the interface between the outermost layer and the inner layer. Particularly, when the thickness of the outermost layer is fluctuated around integral multiples of ¼ of the wavelength of the incident light of the color shift detecting sensor, the incident light entering the photosensor of the color shift detecting sensor is greatly fluctuated and the color shift detecting performance is lowered.

Endless belt for image forming apparatus and image forming apparatus having the endless belt


An A/F sensor outputs a linear air-fuel ratio detection signal proportional to the oxygen concentration in an exhaust gas from an engine upon application of a voltage. A computer controls the applied-voltage in a stoichiometric control region, a lean burn control region, an atmosphere detection region and a rich control region to have a fixed value such that the change rate of the applied-voltage is reduced to be less than that in other regions. In addition, when changing the voltage applied to the A/F sensor, the computer variably sets the voltage change speed sequentially. Thus, the influence of the capacitive characteristic of the A/F sensor is eliminated.

1. Field of the Invention
The present invention relates to air-fuel ratio detection using a current limited (limit-current) type air-fuel ratio sensor which outputs a current signal corresponding to an air-fuel ratio in a detection object gas upon application of a voltage to the sensor.
2. Related Art
In recent years, in air-fuel ratio control for vehicle engines, there are needs for increased control precision and lean burning. To respond to these needs, a linear air-fuel ratio sensor which widely and linearly detects the air-fuel ratio of the gaseous mixture (oxygen concentration in an exhaust gas) supplied into an engine, and an air-fuel ratio detecting apparatus using this sensor are employed. As such air-fuel ratio sensor, in a limit-current air-fuel ratio sensor, its limit-current detection region shifts in accordance with an air-fuel ratio (oxygen concentration), as it is well known. More specifically, in the known V-I characteristic graph, the limit-current detection region comprises a linear segment parallel to the axis V, and the region shifts to the positive voltage side as the air-fuel ratio moves toward the lean side, while it shifts to the negative voltage side as the air-fuel ratio moves toward the rich side. Accordingly, if a voltage applied to the sensor has a fixed value when the air-fuel ratio changes, it is impossible to perform precise air-fuel ratio detection using the limit-current detection region (the linear segment parallel to the axis V) in the entire air-fuel ratio detection range.
Accordingly, a technique to variably set a voltage applied to the air-fuel ratio sensor in accordance with the air-fuel ratio (sensor current) is desired. As this type of prior art, Japanese Patent Publication No. 7-18837 discloses "air-fuel ratio detecting apparatus" which instantly cuts off the voltage applied to the air-fuel ratio sensor to detect sensing element internal-resistance from an electromotive force and current at that time, and variably sets the applied-voltage based on the sensing element internal-resistance. Further, the "air-fuel ratio sensor" disclosed in Japanese Patent No. 2509905 uses a technique to stepwise change an applied-voltage in accordance with whether the air-fuel ratio is on the rich side or the lean side.
However, since a zirconia sensor, which is generally used as a linear air-fuel ratio sensor, has a capacitive (condenser) characteristic, the above conventional techniques cause the following problem. FIG. 27 shows an equivalent circuit of the air-fuel ratio sensor. In the equivalent circuit, reference symbol Rg denotes a particle resistance of solid electrolyte (zirconia sensing element) with respect to oxygen ions; Rh and Ch, respectively a boundary resistance and a boundary capacitance of the surface of the particle of the solid electrolyte; Rf and Cf, respectively an electrode surface resistance and an electrode surface capacitance. In this case, as shown in FIG. 28, when the voltage applied to the air-fuel ratio sensor is changed, the current of the sensor causes a peak current immediately after voltage change due to the influence of electric charge on the above values Ch, Cf, which, as a result, prolongs the time required until the current converges into a predetermined current value.
This situation is especially regarded as a serious problem for realizing high-precision air-fuel ratio feedback control, however, the techniques disclosed in the above publications have not solved this problem. As a result, in a region, where an air-fuel ratio should be detected with high precision, such as a stoichiometric control region (a region having air-fuel ratio=about 13 to 17), air-fuel ratio detection precision is degraded, and further, air-fuel ratio control precision might be lowered to cause inconveniences such as degradation of emission.

Air fuel ratio detection using current-limited sensor with different timing and/or magnitude of incremental changes in applied sensor voltage


An overlaid DQ type DRAM of a clock synchronous type is provided with a column address transition detector circuit, to control pre-charging and equalizing of pairs of DQ lines. An address for selecting a DQ line muptiplexer in a stage prior to a DQ buffer is set to a predetermined column address, and a transition of a column address is detected in a first pipeline stage of a column access path. When only the bit of the predetermined column address changes with the other column address bits kept unchanged, DQ lines are pre-charged and equalized.

The present invention relates to a semiconductor memory device, and particularly, to a DRAM (Dynamic Random Access Memory) of a clock synchronous type having an Overlaid DQ structure and pre-charging of data lines of the DRAM.
This application is based on Japanese Patent Application No. 9-37630, filed on Feb. 21, 1997, the contents of which is cited herein by reference.
FIG. 1 explains a conventional semiconductor memory device and is a block diagram showing a schematic structure of a clock synchronous type 4M-bit DRAM having an overlaid DQ structure. The DRAM comprises a memory cell array 11, a row address buffer 12, a row address buffer controller 13, a row pre-decoder 20, a circuit block 21, a DQ buffer 22, a data I/O buffer 23, a DQ pre-charge/equalize controller 24, and a DQ buffer controller 25.
The memory cell array 11 of 4M-bit consists of two 2M-bit arrays 11A and 11B, and the 2M-bit arrays 11A and 11B respectively consist of eight 256K-bit cell array blocks 11A-0 to 11A-7 and eight 256K-bit cell array blocks 11B-0 to 11B-7. Each of the cell array blocks 11A-0 to 11A-7 and 11B-0 to 11B-7 is constructed in a structure of 256 rows.times.1K columns in which dynamic type memory cells are arranged in a matrix consisting of rows and columns. The row controller 13 receives a /RAS signal and controls the row address buffer 12. The sign "/" of the /RAS signal means this signal is an inverted or a bar of a RAS signal. Hereinafter, in the present specification, "/" is used to indicate an inverted signal. When the /RAS signal is at a low level, the row address buffer 12 latches a row address signals AR0 to AR10 in synchronization with a clock signal CLK, under control of the row controller 13, and generates interpolation signals X0 to X10 and /X0 to /X10. The interpolation signals X0 to X10 and /X0 to /X10 are supplied to the row pre-decoder 14 and pre-decoded. Thereafter, the interpolation signals are supplied to the row decoder 15 provided between the 2M-bit arrays 11A and 11B and are decoded. Selection and activation are made with respect to sixteen 256K blocks 11A-0 to 11A-7 and 11B-0 to 11B-7, with use of interpolation signals X8 to X10 and /X8 to /X10 generated from upper three bits of 11 bits of the row address signals AR0 to AR10. Two blocks which sandwich the row decoder 15 are simultaneously activated (as shown in FIG. 1 in which block 11A-7 and 11B-7 marked with oblique lines are activated). Rows of memory cells are selected in the blocks selected with use of interpolation signals X0 to X7 and /X0 to /X7 generated from the other remaining 8 bits of the row address signals.
The column address buffer 16 latches a column address signal AC0 to AC2 of 3 bits in synchronization with a clock signal CLK when the signal /CAS goes to a low level under control by the /CAS buffer 18. The column address buffer 16 performs a flip-flop operation (waveforms of which will be described later) synchronized with the clock signal CLK. The column address buffer 16 converts the column address signals AC0 to AC2 into interpolation signals Y0F to Y2F and /Y0F to /Y2F. The interpolation signals Y0F to Y2F and /Y0F to /Y2F are supplied to the flip-flop 19 and are converted into Y0S to Y2S and /Y0S to /Y2S. In this step, eight selection signals (/X8.multidot./X9.multidot./X10, X8.multidot.X9.multidot.X10, . . . , and X8.multidot.X9.multidot.X10 which are abbreviated and indicated as X8.multidot.X9.multidot.X10 in the figure) of cell array blocks generated by the row pre-decoder 14 are also converted into signals X8S.multidot.X9S.multidot.X10S by the flip-flop 19. Those column address signals are supplied to the column pre-decoder 20 and column switch selection signals CSW0 to CSW3 are generated. The column switch signals CSW0 to CSW3 are generated by obtaining a logical product of upper two bits of Y1S, /Y1S, Y2S, and /Y2S and a signal X8S.multidot.X9S.multidot.X10S, as expressed in the following logic.
CSW0=/Y1S.multidot./Y2S.multidot.X8S.multidot.X9S.multidot.X10S PA1 CSW1=Y1S.multidot./Y2S.multidot.X8S.multidot.X9S.multidot.X10S PA1 CSW2=/Y1S.multidot.Y2S.multidot.X8S.multidot.X9S.multidot.X10S PA1 CSW3=Y1S.multidot.Y2S.multidot.X8S.multidot.X9S.multidot.X10S
One of the column switch signals CSW0 to CSW3 corresponding to a selected cell array block is activated by the above logical calculation.
In addition, interpolation signals Y0S and /Y0S output from the column pre-decoder 20 are supplied to a circuit block 21. The circuit block 21 consists of first and second circuit blocks 21A and 21B respectively corresponding to 2M-bit arrays 11A and 11B, and each of the first and second circuit blocks 21A and 21B is provided with a DQ multiplexer, a DQ pre-charger a DQ equalizer, and the like. Likewise, a DQ buffer 22 consists of first and second buffer sections 22A and 22B respectively corresponding to the 2M-bit arrays 11A and 11B, and outputs of the buffer sections 22A and 22B are supplied to the data I/O buffer 23 respectively through RWD busses 26A and 26B each consisting of 128 lines (i.e. total 256 lines). The data I/O buffer 23 is supplied with clock signal CLK and an output signal from a /WE buffer 17, and controls inputs/outputs of data.
The /WE buffer 17 is controlled by an output signal from the /CAS buffer 18, and latches a /WE signal. A DQ pre-charge/equalize controller 24 receives a clock signal CLK, /CAS signal, and an output signal from the /WE buffer 17 and generates a pre-charge signal /PRCH. The DQ pre-charge/equalize controller 24 uses the pre-charge signal /PRCH to control the first and second circuit blocks 21A and 21B, so that pre-charging and equalizing of DQ lines are controlled. The DQ buffer controller 25 is supplied with a clock signal CLK described above and an output signal from the /WE buffer 17, and controls the first and second buffer sections 22A and 22B of the DQ buffer 22.
256 pairs of DQ lines are provided on the 2M-bit cell arrays 1A and 11B and are connected to the DQ buffers 22A and 22B through the DQ multiplexer, the DQ pre-charger, and the DQ equalizer. In this respect, FIG. 2 shows more details. 1K columns (or a pair of bit lines) of each of the blocks 11A-0 to 11A-7 and 11B-0 to 11B-7 are connected with 1024 sense amplifiers (S/A) 27-0 to 27-1023. Outputs of the sense amplifiers are supplied to multiplexers (4:1 MUX) 28-0 to 28-255, in units of four outputs. Output ends of the multiplexers 28-0 to 28-255 are respectively connected to 256 pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255. By four column switch selection signals CSW0 to CSW3 output from the column decoder 20, one is selected from output signals of four sense amplifier, supplied to each of the multiplexers 28-0 to 28-255, and is output to pairs of DQ lines 29-0 and /29-0 to 29-255 to /29-255. The pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255 are connected with PMOS transistors 30-0 to 30-255 which serve as DQ equalizers, and with PMOS transistors 31-0 to 31-255 and 32-0 to 32-255 which serve as DQ pre-chargers. The current paths of the PMOS transistors 30-0 to 30-255 is connected between the DQ lines 29-0 to 29-255 and a power source Vcc. The current paths of the PMOS transistors 31-0 to 31-255 are connected between the DQ lines /29-0 to /29-255 and the power source Vcc. The gates of the PMOS transistors 30-0 to 30-255, 31-0 to 31-255, and 32-0 to 32-255 are supplied with a pre-charge signal /PRCH output from the DQ pre-charge/equalize controller 24 to perform ON/OFF control.
The 256 pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255 are connected to 128 DQ multiplexers (2:1 MUS) 33-0 to 33-127, in units each consisting of two pair of DQ lines. Each of the DQ multiplexers 33-0 to 33-12 selects one pair of two pairs of DQ lines connected thereto, in accordance with interpolation signals Y0S and /Y0S (or the lowermost bit of the column address) output from the column pre-decoder 20. Specifically, when the signal /Y0S is at a high level, pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . ., and 29-255, and /29-255 are selected, and data on these DQ lines is supplied to the DQ buffers 22-0 to 22-127, so that read data is amplified. Output signals of the DQ buffers 22-0 to 22-127 are respectively supplied to RWD busses 26-0 to 26-127.
In the structure as described above, 1K lines of columns corresponding to the 2M cell arrays 11A and 11B are multiplexed at a ratio of 4:1 by the column switch selection signals CSW0 to CSW3, and are connected to the 256 pairs of DQ lines. In this state, the column switch selection signals CSW0 to CSW3 are common to the 256 pairs. Specifically, when one of the column switch selections signals CSW0 to CSW3 is selected, e.g., when the signal CSW0 is selected, 256 sense amplifiers 27-0, 27-4, 27-8, . . . , and 27-1021 are simultaneously connected to the pairs of DQ-lines 29-0 and /29-0, 29-1 and /29-1, . . . , and 29-255 and /29-255, and data held by the sense amplifiers is read out onto the DQ lines.
FIG. 3 is a block diagram extracting and more specifically showing a circuit section relating to bit lines, sense amplifiers and pairs of DQ lines shown in the block diagram of FIG. 2. 1K pieces of sense amplifiers 27 are divided into groups each consisting of four sense amplifiers and arranged at both ends of each of 256K blocks. Each sense amplifier 27 is connected with a pair of bit lines BL and /BL. The pairs of bit lines BL and /BL are arranged such that bit lines of the sense amplifiers in one side are inserted between bit lines of the other sense amplifiers in the opposite side. Four sense amplifiers 27 of each group are connected to a pair of DQ lines 29 and /29, through current paths of NMOS transistors 34-0 to 34-7 which serve as a multiplexer 28, respectively. The gates of the NMOS transistors 34-0 to 34-7 are supplied with column switch selection signals CSW0 to CSW3, output data of the sense amplifier 27 corresponding to that one of the column switch selection signals which is of a high level is read out onto the pair of DQ lines 29 and /29.
The pair of DQ lines 29 and /29 is used in common by eight cell array blocks and is arranged in a direction parallel to the bit lines BL and /BL (i.e., in an overlaid DQ structure). A DRAM having this overlaid DQ structure allows a number of pairs DQ lines to be provided in a small chip area, and is therefore used for a logic mixture DRAM having a large number of data inputs and outputs.
FIG. 4 is a timing chart for explaining operation of the circuit shown in FIGS. 1 to 3. Next, explanation of the operation will be made mainly with respect to pre-charge and equalize operation. Here, operation of column access will be made, supposing that a low address signal has been taken in with the /RAS signal kept at a low level, a word line has been selected, and latch operation of a selected row has been carried out.
When the /CAS signal goes to a low level, column address signals AC0 to AC2 are taken in by the column address buffer 16 by control of the /CAS buffer 18, and column addresses CA0, CA1, and CA2 are sequentially generated in clock cycles 0 to 2, respectively. A column access signal path from the column address buffer 16 to a data output is divided into three pipe line stages, e.g., the column address buffer 16 which performs flip-flop operation, a flip-flop 19 in the stage before the column pre-decoder 20, and a data I/O buffer 23 which also performs flip-operation. The route through which signals Y0F to F2F are transmitted from the column address buffer 16 to the flip-flop 19 is the first stage PS1. The route through which signals CSW0 to CSW3 and signals Y0S and /Y0S from the flip-flop 19 are activated and data of selected columns are latched by the data I/O buffer 23 through the pair of DQ lines 29 and /29, the DQ multiplexer 33, and the DQ buffer 22 is the pipe line second stage PS2. The last pipe line third stage PS3 corresponds to data outputting from the data I/O buffer 23.
In putted column addresses CA0, CA1, CA2, . . . are transmitted through the pipe line stages PS1, PS2, and PS3 in clock cycles 0, 1, 2, . . . , respectively. Specifically, signals /Y0F, /Y1F, and /Y2F are activated in the 0th clock cycle, and signals /Y0S, /Y1S, and /Y2S, and CSW0 are activated in the next first clock cycle. When the signal CSW0 is thereby turned to a high level, data of sense amplifiers 27-0, 27-4, . . . , 27-1021 shown I FIG. 2 is read through pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255. Since the signal /Y0S is now at a high level, data of the pairs of DQ lines 29-0 and /29-0, 29-2 and /29-2, . . . , 29-254 and /29-254 among 256 pairs of DQ lines is supplied to the DQ buffers 22-0 to 22-127 through the multiplexers 33-0 to 33-127 and is amplified. In this state, data of the pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . . , 29-255 and /29-255 does not passes through the multiplexers 33-0 to 3-127, and therefore is not read onto the DQ buffers 22-0 to 22-127.
Next, the column address CA1 input before the first clock cycle activates the signals Y0F, /Y1F, and /Y2F in the first clock cycle, and further, activates the signals Y0S, /Y1S, /Y2S, and CSW0 in the second clock cycle. Since the signals /Y1S, /Y2S, and CSW0 have already been activated in the first clock cycle, data to be read (D1 in FIG. 4) has already been output to the pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . . , 29-255 and /29-255.
However, in a conventional clock synchronous DRAM as described above, since the pairs of DQ lines are pre-charged and equalized in every clock cycle, and data read out onto the pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . . , 29-255 and /29-255 is broken by the pre-charging and equalizing operation and is read out again onto these DQ lines in the second clock cycle. Such wasteful pre-charging and equalizing operation leads to a problem that charging and discharging currents of DQ lines are increased, resulting in an increase of the power consumption of the chip.
In addition, the number of data lines has been increased in accordance with technical developments in recent years. Accordingly, the ratio of the power consumption of DQ lines to the entire power consumption of a semiconductor memory device has increased, so that the power consumption of DQ lines cannot be negligible.
Further, a conventional memory system using a semiconductor memory device as described above must use an expensive ceramic package in order to overcome heat generation caused by an increase of the power consumption, so that the cost of the entire system is increased.


A food preserving method is a method for preserving food using a food film (34A), (34B). The food film (34A), (34B) has a surface which has a plurality of raised portions (34Ap), (34Bp). The two-dimensional size of the plurality of raised portions (34Ap), (34Bp) is in a range of more than 20 nm and less than 500 nm when viewed in a direction normal to the food film (34A), (34B). The method includes bringing the food into direct contact with the surface.

Recently, it was reported that surficial nanostructures of black silicon, wings of cicadas and dragonflies have a bactericidal activity (Non-patent Document 1). Reportedly, for example, black silicon has 500 nm tall nanopillars, and the physical structure of the nanopillars produces a bactericidal activity. Wings of cicadas and dragonflies have 240 nm tall nanopillars.
According to Non-patent Document 1, black silicon has the strongest bactericidal activity on Gram-negative bacteria, while wings of dragonflies have a weaker bactericidal activity, and wings of cicadas have a still weaker bactericidal activity. The static contact angle (hereinafter, also simply referred to as "contact angle") of the black silicon surface with respect to water is 80°, while the contact angles of the surface of wings of dragonflies and cicadas with respect to water are 153° and 159°, respectively.

Food preservation method, food film, food container, and food handling method


A system to provide fractional bandwidth data transmission includes a network processor, physical layer device, or link layer device {“data device”) and a plurality of link layer devices that are coupled to a plurality of input-output ports. The link layer devices are coupled in a serial daisy chain fashion and pass data via a plurality of data channels. The first linked layer device is coupled to the data device and receives data therefrom and the last linked layer device is coupled to the data device and transmits data thereto forming a ring network that includes all of the link layer devices and the data device. Data received from the data device is contained in data packets that contain a destination identifier and the data. Each link layer device receives input data packets and separates the data packets based on the destination identifier contained therein. Data packets having a destination identifier corresponding to one of the plurality of input-output ports coupled to that particular linked layer device are diverted to the identified input-output port. The remaining data, and any data generated by that link layer device, is provided to the next adjacent down-stream link layer device. Data flow control is provided in an upstream direction from one link layer device to the next adjacent up-stream link layer device as a plurality of status indicators that correspond to the plurality of data channels. Each link layer device is responsive to the plurality of status indicators by not transmitting data on data channels having a corresponding status indicator indicative that no data is to be transmitted.

This invention relates to apparatus for providing data communication services, and in particular, to providing fractional bandwidth data communication services.
Data communication vendors typically sell data communication link bandwidth to end users in "full lot" quantities, i.e., an end user is required to purchase an entire unit of bandwidth. For example, an end user that desires to use any portion of a Gigabit Ethernet (GBE) link is required to purchase the entire 1.25 Gigabit per second (GBPS) bandwidth thereof. In some instances however, an entire unit of bandwidth of a data communications link may exceed the required bandwidth of the data to be transmitted by the end user. In this case, the end user is unable to make use of the entire purchased bandwidth resulting in a waste of economic resources of the end user and a waste of bandwidth for the service provider. Having to purchase an entire GBE link may discourage some end users from purchasing bandwidth from a high capacity data link provider. As an alternative, a end user may purchase a full unit of bandwidth from a data communications provider that utilizes smaller bandwidths, i.e., lower capacity data links, thus foregoing the advantages of a higher bandwidth data connection that may provide the end user with a competitive advantage.
In another situation where the difference between the aggregate bandwidth and the full rate data bandwidth of the client I/O module ports can result in a number of ports that can be aggregated into a single higher capacity link. For example, in a ESCON/SONET example, a single 12-port ESCON device could aggregate all 12 ports into a single 2.5 Gb/s OC-48 device, but it may be more attractive to use 4 ESCON devices to aggregate 48 ports into a single 10 Gb/s device.
Currently, the public switched telephone network (PSTN) uses synchronous optical networking (SONET) links that operate at a data rate of approximately 10 GBPS using a single OC-192 link or four OC-48 links. Typically, a telecommunications service provider will aggregate the data of two or more end users together in order to maximize the use of the available bandwidth on the PSTN. In the case of end users operating GBE links at approximately 1 GBPS, a maximum of 10 end users may be aggregated together to form a 10 GBPS signal for transmission across the PSTN. If one or more end users are unable to fully utilize their portion of the 10 GBPS bandwidth, neither the telecommunications provider nor the end user is maximizing the use of the available bandwidth.
The ability to provide fractional portions of high bandwidth capacity links, such as GBE links, to end users would allow them to utilize the advantages of high bandwidth data communications systems without requiring the end users to purchase bandwidth in full unit quantities. The data communications vendors would achieve a more efficient use of the available bandwidth as well, in addition to increasing the number of clients making use of their service. Thus, offering fractional bandwidths of high capacity links would offer advantages to both the suppliers of data communications services and the consumers those services.
However as discussed above, the currently existing equipment is not designed to accommodate fractional bandwidth usage. The development of new equipment to accommodate fractional bandwidth use by end users is both expensive and time consuming. Merely scaling the existing equipment to allow addition of many more users through adding additional input-output ports is not a viable alternative. Adding additional input-output ports to the existing equipment designs will require a much higher pin count than current equipment allows to accommodate the new users. In addition, each of the added input-output ports will require an additional interface circuit associated with each port, larger internal multiplexers and more memory. This additional circuitry will result in a larger chip area, more power and heat to dissipate, and an increase in the cost of the chips.
Therefore, it would be advantageous to provide for the aggregation of users to make use of a fractional high capacity data communication environment using existing equipment that does not require an increase in pin count, power dissipation, and additional circuitry.

System to provide fractional bandwidth data communications services