A pattern generator that generates a test pattern used for testing an electric part including: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory;

This patent application claims priority based on a Japanese patent application, H11-184470 filed on Jun. 29, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a pattern generator and an electric part testing apparatus which generates a test pattern used for testing an electric part.
2. Description of the Related Art
Conventionally, an electric part testing apparatus used for testing an electric part such as semiconductor memory comprises a pattern generator, which generates a test pattern used for testing an electric part. FIG. 1 shows a configuration of a conventional pattern generator. A pattern generator 100 generates a test pattern for a dynamic random access memory (DRAM), which is an example of an electric part.
A pattern generator 100 has a vector memory 102, a read out controller 103, a vector cache memory 104, an address expansion unit 106, an address designating unit (AP) 108, a timer 110, an interruption controller 112, a refresh address-designating unit (SPI) 114, a multiplexer (MUX) 116, and a pattern-generating unit 118. A timer 110 generates an interruption request for every predetermined time interval. The interruption controller 112 sets a refresh cycle signal (REF CYCLE) to xe2x80x9c1xe2x80x9d and outputs to an address expansion unit 106 and a multiplexer 116 on receipt of the interruption request from the timer 110.
The vector memory 102 is constituted by a mass storage static random access memory, SRAM, and stores a vector instruction (sequence instruction) that defines an order for reading out a control instruction, which defines a test pattern to be generated.
The read out controller 103 inputs a part of the vector instruction from the vector memory 102 and outputs the input vector instruction to the vector cache memory 104. The vector cache memory 104 is constituted by a small storage high speed SRAM, and stores a vector instruction input from the read out controller 103. Furthermore, the vector cache memory 104 outputs the vector instruction to the address expansion unit 106 based on the address, which is input from the address-designating unit 108.
The address expansion unit 106 generates an address by interpreting the vector instruction input from the vector cache memory 104 and outputs the generated address to the address-designating unit 108. Moreover, the address expansion unit 106 interrupts the generation of the address when the refresh cycle signal, which is set to xe2x80x9c1xe2x80x9d, is input from the interruption controller 112. The address expansion unit 106 restarts the generation of the address when the refresh cycle signal, which is set to xe2x80x9c0xe2x80x9d, is input from the interruption controller 112. The address-designating unit 108 stores and outputs the address input from the address expansion unit 106.
The refresh address-designating unit 114 stores and outputs an address, which corresponds to the control instruction for refreshing an electric part. The multiplexer 116 selects either the address input from the interruption controller 112 or the address input from the refresh address-designating unit 114, based on the refresh cycle signal input from the interruption controller 112. The address input from the refresh address-designating unit 114 is selected when the refresh cycle is xe2x80x9c1xe2x80x9d, and the address input from the address-designating unit 108 is selected when the refresh cycle signal is xe2x80x9c0xe2x80x9d.
The pattern-generating unit 118 has a control instruction memory 120, pattern operator 122, a resistor XB, a resistor YB, and a resistor RF. The control instruction memory 120 stores a control instruction, which generates a test pattern, and outputs the control instruction corresponding to the address, which is input from the multiplexer 116, to pattern operator 122. The resistor XB stores a value to be provided as a column address of a DRAM, which is an object to be tested. The resistor YB stores a value to be provided as a row address of the DRAM, and the resistor RF stores a row address for refreshing the DRAM. The pattern operator 122 generates a test pattern based on the control instruction output from the control instruction memory 120. Example of test patterns include, an address signal, a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, a data signal, and a write enable (/WE: where xe2x80x9c/xe2x80x9d stands for reverse logic) signal.
FIG. 2 shows various kinds of information stored in the conventional pattern generator. FIG. 2(A) shows an address stored in the refresh address-designating unit 114. The refresh address-designating unit 114 stores xe2x80x9c1#300xe2x80x9d as an address corresponding to the refresh controlling instruction. FIG. 2(B) shows a sequence instruction stored in the vector memory 102. In FIG. 2(B), xe2x80x9cNOPxe2x80x9d is an instruction that outputs the present address value and advances the address value to the next value, that is, adds xe2x80x9c1xe2x80x9d to the present address value. xe2x80x9cJNI STOxe2x80x9d is an instruction that outputs the present address value and executes the instruction of the address, which is allotted a label STO.
FIG. 2(C) shows a part of a control instruction stored in the control-instruction memory 118. In FIG. 2(C), xe2x80x9cXB less than 0xe2x80x9d is an instruction that clears the value of the resistor XB to xe2x80x9c0xe2x80x9d in the next cycle. xe2x80x9cXB less than XB+1xe2x80x9d is an instruction that adds xe2x80x9c1xe2x80x9d to the value of the resistor XB in the next cycle. xe2x80x9cYB less than 0xe2x80x9d is an instruction that clears the value of the resistor YB to xe2x80x9c0xe2x80x9d in the next cycle. xe2x80x9cYB less than YB+1xe2x80x9d is an instruction that adds xe2x80x9c1xe2x80x9d to the value of the resistor YB in the next cycle. xe2x80x9cRF less than RF+1xe2x80x9d is an instruction that adds xe2x80x9c1xe2x80x9d to the value of the resistor RF in the next cycle.
xe2x80x9cPAGE-INxe2x80x9d is an instruction that outputs a signal to the DRAM for inputting a row address and a column address, which executes the data writing process or data reading process. For example, xe2x80x9cPAGE-INxe2x80x9d is an instruction that outputs the value of the resistor YB as an address signal and outputs a RAS signal, which is set to LOW, and also outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to a negative pulse. xe2x80x9cPAGExe2x80x9d is an instruction that outputs the signal to the DRAM for changing a column address, which executes the data writing process or data reading process. For example, xe2x80x9cPAGExe2x80x9d is an instruction that outputs the value of the resistor as an address signal and outputs the CAS signal, which is set to a negative pulse.
xe2x80x9cPAGE-OUTxe2x80x9d is an instruction that outputs a signal to the DRAM for terminating the data reading process or data writing process. For example, xe2x80x9cPAGE-OUTxe2x80x9d is an instruction that outputs the value of the resistor XB as an address signal, and a CAS signal which is set to a negative pulse, and also outputs the RAS signal, which is set to HIGH. By setting the RAS signal to HIGH, the DRAM is pre-charged. That is, the wiring capacity of the DRAM is charged. xe2x80x9cREFRESHxe2x80x9d is an instruction that outputs a signal for executing the refreshing operation on the DRAM. For example, xe2x80x9cREFRESHxe2x80x9d is an instruction that outputs the value of the resistor RF as an address signal and outputs a RAS signal, which is set to LOW.
FIG. 3 shows an operation of the conventional pattern generator. FIG. 3 shows an operation of the pattern generator 100 when the several kinds of information shown in FIG. 2 are stored in the pattern generator. FIG. 3(A) shows a value of an address output from the address-designating unit 108, a value of the address PC output from the multiplexer 116, the value of the resistor XB, the value of the resistor YB, the value of the resistor RF, the value of the refresh cycle (REFCYCLE), the operation of the resistor, which is a provider of the address output to the DRAM, and the operation of the DRAM for each cycle during the operation of the pattern generator. FIG. 3(B) shows a signal, which is output to the DRAM from the pattern generator, from the cycle 6 to cycle 11.
In the cycle 1, the address expansion unit 106 picks out xe2x80x9cNOPxe2x80x9d from the vector cache memory 104, directs the address-designating unit 108 to output the present address value xe2x80x9c#0xe2x80x9d, and sets the address value to xe2x80x9c#1xe2x80x9d. Here, the refresh cycle signal xe2x80x9c#0xe2x80x9d is output from the interruption controller 112. The multiplexer 116 outputs xe2x80x9c#0xe2x80x9d, which is output from the address-designating unit 108, as an address PC to the pattern-generating unit 118 because the refresh cycle signal is xe2x80x9c0xe2x80x9d. Thereby the instruction xe2x80x9cXB less than 0xe2x80x9d, xe2x80x9cYB less than 0xe2x80x9dis output to the pattern operator 122 from the control instruction memory 120. Therefore, the pattern operator 122 sets the values of the resistor XB and the resistor YB to xe2x80x9c0xe2x80x9d in the next cycle.
In the cycle 2, the address expansion unit 106 picks out xe2x80x9cNOPxe2x80x9d from the vector cache memory 104, directs the address-designating unit 108 to output the present address value xe2x80x9c#1xe2x80x9d, and sets the address value to xe2x80x9c#2xe2x80x9d. Here, the refresh cycle signal of xe2x80x9c0xe2x80x9d is output from the interruption controller 112. The multiplexer 116 outputs xe2x80x9c#1xe2x80x9d, which is output from the address-designating unit 108, as an address PC to the pattern-generating unit 118 because the refresh cycle signal is xe2x80x9c0xe2x80x9d. Thereby the instruction xe2x80x9cXB less than XB+1xe2x80x9d, xe2x80x9cPAGE-INxe2x80x9d is output to the pattern operator 122 from the control instruction memory 120.
The pattern operator 122 outputs the value of the resistor YB as an address signal, and the RAS signal which is set to LOW, and then outputs the value of the resistor XB as an address signal, and the CAS signal, which is set to a negative pulse. The DRAM thereby executes the PAGE-IN operation. Moreover, the pattern operator 122 adds xe2x80x9c1xe2x80x9d onto the value of the resistor XB in the next cycle. The same operations shown above are executed from the cycle 3 to cycle 9.
For example, as shown in FIG. 3(B), in the cycle 6, the pattern operator 122 outputs the value of the resistor YB as an address signal and outputs the RAS signal, which is set to LOW., The pattern operator 122 then outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to be a negative pulse. The DRAM thereby executes the PAGE-IN operation, that is, the writing process or the reading process of the memory cell corresponding to the column of the value of the resistor XB and the row of the value of the resistor YB.
As shown in FIG. 3(B), in the cycle 7, the pattern operator 122 outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to be a negative pulse. The DRAM thereby executes the PAGE operation, that is, the writing process or the reading process of the memory cell corresponding to the column of the value of the resistor XB and the row of the value of the resistor YB, which is input in the cycle 6. The cycle 8 also executes the same operation as shown above.
In the cycle 9, the pattern operator 122 outputs the value of the resistor XB as an address signal, the CAS signal, which is set to be a negative pulse, and then the RAS signal, which is set to HIGH. The DRAM thereby executes the PAGE-OUT operation, that is, the writing process or the reading process of the memory cell corresponding to the column of the value of the resistor XB and the row of the value of the resistor YB, which is input in the cycle 6. The DRAM is thereby pre-charged.
Here, if the timer 110 detects the passing of the predetermined time at the cycle 9, the time for executing the refreshing operation is indicated, and therefore the timer 110 outputs the interruption request to the interruption controller 112. The interruption controller 112 sets the refresh cycle signal to xe2x80x9c1xe2x80x9d and outputs the refresh cycle signal to the address expansion unit 106 and the multiplexer 116 in the next cycle 10.
In the cycle 10, because the refresh cycle signal is xe2x80x9c1xe2x80x9d, the address expansion unit 106 makes the address-designating unit 108 hold the present address value and stops the generation of an address generated by the vector instruction. Furthermore, because the refresh cycle signal is xe2x80x9c1xe2x80x9d, the multiplexer 116 outputs the address xe2x80x9c1#300xe2x80x9d, which is output from the refresh address-designating unit (SPI) 114, to the pattern-generating unit 118 as an address PC.
Thereby, the control instruction memory 120 inputs xe2x80x9cRF less than RF+1xe2x80x9d and xe2x80x9cREFRESHxe2x80x9d to the pattern operator 122. Additionally, as shown in FIG. 3, the pattern operator 122 outputs the value of the resistor RF as an address signal and outputs the RAS signal, which is set to LOW. As a result, the DRAM executes the REFRESH operation, that is, refreshing the row value of the resistor RF. Furthermore, the interruption controller 112 changes the row address, which is to be refreshed in the next cycle, by adding xe2x80x9c1xe2x80x9d onto the value of the resistor RF in the next cycle 11.
In the cycle 11, the interruption controller 112 sets the refresh cycle signal to xe2x80x9c0xe2x80x9d and outputs the refresh cycle signal to the address expansion unit 106 and the multiplexer 116. The address expansion unit 106 thereby restarts the generation of the address by the vector instruction. Moreover, the multiplexer 116 outputs the address, which is output from the address-designating unit 108, to the pattern-generating unit 118 as an address PC. Then the control instruction memory 120 provides to the pattern operator 122, the control instruction-corresponding to the address provided from the multiplexer 116. The pattern operator 122 generates the test pattern according to the control instruction. The following cycles are executed as shown above.
The conventional electric part testing apparatus can perform predetermined testing of an electric part as expected, when the interruption request is generated by the timer 110 at the cycle of the PAGE-OUT, for example, cycle 9. However, because the interruption request generated by the timer 110 is a synchronous with the testing of the electric part, the interruption request may be generated during the cycle of the PAGE-IN and the cycle of the PAGE. Therefore, problems, which hinder the testing, may occur. For example, the refreshing operation may be executed without pre-charging the electric part, and thus the writing process or the reading process cannot be executed properly after the refreshing operation during the testing of the electric part.
Furthermore, in a case of making subroutine a set of a plurality of instructions executed repeatedly, there is a problem where it is difficult to control when and how this subroutine is read from the vector memory 102 to the cache. Also there is a problem where the configuration of the pattern generator becomes complicated in order to solve the above problem. Furthermore, it is difficult to generate a test pattern, which is to be provided to each of the configuration, cooperatively when the pattern generator generates the pattern for testing the device, on which a memory and a logic are mounted together. Even if the pattern can be generated cooperatively, the configuration of the pattern generator becomes complicated.
Therefore, it is an object of the present invention to provide a pattern generator and an electric part testing apparatus which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a pattern generator that generates a test pattern used for testing an electric part can be provided. The pattern generator may comprise: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information according to the interruption vector instruction stored in the interruption vector memory; and a pattern generating unit that generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit or the interruption test pattern information corresponding to the address generated by the interruption address expansion unit.
The pattern generator may further comprises: an interruption detecting unit that detects a point in time for starting the interruption process; and the interruption address expansion unit generates the address of the interruption test pattern information based on detection of the point in time for starting the interruption process by the interruption detecting unit; and the pattern generating unit generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit when the interruption detecting unit does not detect the point in time for starting the interruption process, and the pattern generating unit generates the test pattern based on the interruption test pattern information corresponding to the address generated by the interruption address expansion unit when the interruption detecting unit detects the point in time for starting the interruption process.
The pattern generator may further comprises: an interruption controller that interrupts generation of the address generated by the address expansion unit based on detection of the point in time for starting the interruption process by the interruption detecting unit; an interruption end detecting unit that detects an end of the interruption process; and a starting controller that starts generation of the address by the address expansion unit based on detection of the end of the interruption process by the interruption end detecting unit.
The electric part may be a memory having a function of storing data and which requires refreshing in order to hold the data, and the interruption pattern memory may store the interruption test pattern information, which defines a test pattern for refreshing the memory. The interruption pattern memory may further store the interruption test pattern information that defines a test pattern for pre-charging the memory and a test pattern for providing a column address, which is provided to the memory before executing the interruption process, to the memory; the pattern generating unit may generate the test pattern in an order of: the test pattern for pre-charging the memory, the test pattern for refreshing the memory, and the test pattern for providing the column address when the interruption detecting unit detects the point in time for starting the interruption process.
The pattern generator may further comprise a timer for measuring time, and the interruption detecting unit detects the point in time for starting the interruption process based on the time measured by the timer. The vector instruction, which is stored in the vector memory, may include a description that indicates the point in time for starting the interruption process; and the interruption detecting unit detects the point in time for starting the interruption process based on the description. Each of the test pattern information and the interruption test pattern may be the test pattern, or a control instruction for generating the test pattern. One of the test pattern information and the interruption test pattern information may be the test pattern; and another thereof may be a control instruction for generating the test pattern.
The test pattern information and the interruption test pattern information may be stored on a single memory space corresponding to the addresses which are different from each other; and the pattern generating unit may include: an address selecting unit that selects the address generated by the address expansion unit when the interruption detecting unit does not detect the point in time for starting the interruption process and selects the address generated by the interruption address expansion unit when the interruption detecting unit detects the point in time for starting the interruption process; and a unified pattern generating unit that generates the test pattern based on the test pattern information or the interruption test pattern information corresponding to the address selected by the address selecting unit.
The pattern generator may include: a first pattern generating unit that generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit; a second pattern generating unit that generates the test pattern based on the interruption test pattern corresponding to the address generated by the interruption address expansion unit; and a test pattern selecting unit that selects the test pattern generated by the first pattern generating unit when the interruption detecting unit does not detect the point in time for starting the interruption process, and selects the test pattern generated by the second pattern generating unit when the interruption detecting-unit detects the point in time for starting the interruption process.
According to the second aspect of the present invention, an electric part testing apparatus for testing an electric part can be provided. The electric part testing apparatus may comprise: a pattern memory that stores test pattern information that defines a test pattern including an input test pattern provided to the electric part for the testing, and an expected value, which is expected to be output from the electric part after providing the input test pattern to the electric part; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the best pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory that stores an interruption vector instruction, which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information in the interruption pattern memory according to the interruption vector instruction stored in the interruption vector memory; a pattern generating unit that generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit or the interruption test pattern information corresponding to the address generated by the interruption address expansion unit; a pin data selector that rearranges the test pattern generated by the pattern generating unit according to a pin arrangement of electric terminals of the electric part; a waveform formatter that formats a waveform of the input test pattern, which is included in the test pattern output from the pin data selector; a device socket that provides the input test pattern formatted by the waveform formatter to the electric part and receives an output signal output from the electric part; and a comparator that compares the output signal, which is received by the device socket, with the expected value.
The electric part testing apparatus may further comprise: an interruption detecting unit that detects a point in time for starting the interruption process; and the interruption address expansion unit generates the address of the interruption test pattern information based on detection of the point in time for starting the interruption process by the interruption detecting unit; and the pattern generating unit generates the best pattern based on the test pattern information corresponding to the address generated by the address expansion unit when the interruption detecting unit does not detect the point in time for starting the interruption process, and the pattern generating unit generates the test pattern based on the interruption test pattern information corresponding to the address generated by the interruption address expansion unit when the interruption detecting unit detects the point in time for starting the interruption process.
The electric part testing apparatus may further comprise: an interruption controller that interrupts generation of the address generated by the address expansion unit based on detection of the point in time for starting the interruption process by the interruption detecting unit; an interruption end detecting unit that detects an end of the interruption process; and a starting controller that starts generation of the address by the address expansion unit based on detection of the end of the interruption process by the interruption end detecting unit.
The electric part may be a memory having a function of storing data and which requires refreshing in order to hold the data, and the interruption pattern memory stores the interruption test pattern information, which defines a test pattern for refreshing the memory. The interruption pattern memory may further store the interruption test pattern information that defines a test pattern for pre-charging the memory and a test pattern for providing a column address, which is provided to the memory before executing the interruption process, to the memory; the pattern generating unit may generate the test pattern in an order of: the test pattern for pre-charging the memory, the test pattern for refreshing the memory, and the test pattern for providing the column address to the memory when the interruption detecting unit detects the point in time for starting the interruption process.
According to the third aspect of the present invention, a method for generating a test pattern used for testing an electric part can be provided. The method may include: generating test pattern information, which defines the test pattern; generating a vector instruction, which indicates an order for reading out the test pattern information; generating an address of the test pattern information according to the vector instruction; generating interruption test pattern information, which defines the test pattern during a predetermined interruption process; generating an interruption vector instruction, which indicates an order for reading out the interruption test pattern information; generating an address of the interruption test pattern information according to the interruption vector instruction; and generating the test pattern based on the test pattern information corresponding to the address generated by the generating the address of the test pattern information or the interruption test pattern information corresponding to the address generated by the generating the address of the interruption test pattern information.
This summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the above described features. The above and other features and advantages of the present invention will become more apparent from the following description of embodiments taken in conjunction with the accompanying drawings.

Pattern generator and electric part testing apparatus


A microphone includes a casing having an open side and a lid mounted to and covering the open side of the casing. A circuit board and a mounting plate are mounted in the casing. An audio conversion unit and a switch are mounted on the circuit board and electrically connected with each other such that activation of the switch controls on/off of the audio conversion unit. The lid includes a pivotal portion pivotably engaged with an end of the mounting plate distant to the switch, allowing the other end of the lid to pivot relative to the mounting plate between an activating position for pressing against and activating the switch and a non-activating position disengaged from the switch. A returning member is mounted between the lid and the casing for returning the other end of the lid to the non-activating position.

The present invention relates to a microphone and, more particularly to a handfree microphone for mobile phones.
Mobile phones provide people with convenient communication through direct conversation and messages. When not using an earphone, a user has to hold the mobile phone to one of his or her ears, leading to hazards if the user is driving. Thus, many countries outlaw use of mobile phones without earphones during driving. Handfree microphones have been proposed. A typical design includes an earphone having a microphone that is located adjacent to a user's mouth when the earphone is placed in an ear of the user. The microphone includes a case consisting of an upper casing and a lower casing. A circuit board is mounted in the case and includes an audio conversion device and a switch for controlling on/off of the audio conversion device. The upper casing includes a sound hole aligned with the audio conversion device for receiving sound. Also mounted on the upper casing is a push button that can be pressed to activate the switch. However, it takes some time for a driver to grope the push button when his or her mobile phone rings, which may cause problems to the driver whose both hands are on a steering device such as a steering wheel or handgrips. For safety consideration, the driver usually gropes and presses the push button when he or she feels no danger. However, the driver might miss the phone call.
It is, therefore, a need in a handfree microphone that allows easy operation even during driving.

This patent is subject to a terminal disclaimer.


A perpendicular magnetic recording head includes a main pole, a return yoke forming a magnetic path with the main pole, and a coil encompassing the main pole in a solenoid structure to allow the main pole to generate a magnetic field that records information on a recording medium is provided. When a side of the main pole toward the return yoke is an upper portion of the main pole and a side of the main pole opposite to the return yoke is a lower portion of the main pole, the coil includes a lower wire portion passing through the lower portion of the main pole, an upper wire portion passing through the upper portion of the main pole, and a connection portion electrically connecting the lower wire portion and the upper wire portion, and the upper wire portion includes an upper wire layer having at least two layers. The structure may improve a high frequency recording characteristics required for achieving a high recording density.

1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a perpendicular magnetic recording head and a manufacturing method thereof, and more particularly, to a perpendicular magnetic recording head having a solenoid type coil structure in which a coil, which generates a recording magnetic field, is formed at a main pole to increase a recording density of a recording medium by improving the strength of the recording magnetic field.
2. Description of the Related Art
Magnetic recording methods can be divided into horizontal magnetic recording methods and perpendicular magnetic recording methods. In a horizontal magnetic recording method, information is recorded based on the fact that the magnetization direction of a magnetic layer is parallel to the surface of the magnetic layer. In a perpendicular magnetic recording method, information is recorded based on the fact that the magnetization direction of a magnetic layer is perpendicular to the surface of the magnetic layer. In terms of recording density, a perpendicular magnetic recording method is superior to a horizontal magnetic recording method. As such, perpendicular magnetic recording heads having various structures are being developed.
To achieve high linear recording density with perpendicular magnetic recording heads, high frequency recording characteristics need to be improved through optimal design of a recording head. To improve the high frequency recording characteristics means maintaining a strong recording magnetic field at a high frequency while simultaneously shortening rise time of the recording magnetic field. For fast rise time of a recording magnetic field, it is important to decrease head inductance and eddy current loss.
The eddy current loss can be decreased by using a material having a high resistivity as a main pole of the recording head. However, since the characteristics of the main pole are determined by various factors, such as saturation magnetization and coercivity, in addition to the resistivity, it is difficult to increase the resistivity of the main pole without affecting other factors.

Perpendicular magnetic recording head and method for manufacturing the same


A computer creates a prioritization list of a set of project functions, wherein each project function is associated with a priority level and an amount of resources. The computer detects a request, wherein the request includes a request to do one or more of alter one or more project functions of the set of project functions, add one or more project functions to the set of project functions, and remove one or more project functions from the set of project functions. The computer determines whether to allow the request based on at least on a comparison to the prioritization list.

Companies are utilizing the cloud more and more to meet their data storage, project function, and data backup needs. As companies adopt larger amounts of cloud capabilities for test, development, and production workloads, controlling the associated expenses becomes increasingly more complex. Part of this complexity is due to the unbounded nature of the resources that may be consumed by the various projects. It is important for companies to keep in mind how the resources consumed by various projects affects the overall budget of the company. A brief discussion of the prior art is included below.
US Patent Publication US 2011/0231899 (Pulier et al.), discloses a system that provides a cloud-computing service from a cloud-computing environment which may comprise a management module configured to manage a cloud-computing resource as a cloud computing service, wherein the cloud-computing service performs a computer workload; an adapter configured to connect to the cloud computing resource to the system and translate a management instruction received from the management module into a proprietary cloud application program interface call for the cloud-computing resource; a cloud service bus configured to route the management instruction from the management module to the adapter; a consumption module configured to allow a user to subscribe the cloud-computing service; a planning module configured to plan the cloud-computing service; and a build module configured to build the cloud-computing service from the cloud-computing resource and publish the cloud-computing service to the consumption module.
US Patent Publication US 2011/0252137A1 (Steinhans et al.) discloses a method comprising configuration information for creating one or more software servers as images on a cloud computing system, specifying a processing load threshold, and continuously monitoring a processing load on one or more software servers. If the monitored load exceeds the processing load threshold, a request to the cloud computing system may be generated to instantiate an instance of one of said images. The method further includes creating a server instance on the cloud in response to the request, distributing the processing load across the one or more servers and the server instance, and monitoring the processing load on the one or more servers and the server instance.
US Patent Publication 2014/0101005 A1 (Baset et al.) discloses a method for providing a cloud-based service to an enterprise comprising a plurality of members including receiving at least a portion of a policy a first user within the enterprise, where the policy defines a limit on usage of the cloud-based service by at least some of the plurality of members, receiving a request for the cloud-based service from a second user associated with one of the plurality of members, and automatically responding to the request in accordance with the policy.
The prior art does not address a need for managing and effectively allocating computing resources based on an analysis of the characteristics of the computing resources.

Management of resources in view of business goals

INTERNATIONAL BUSINESS MACHINES CORPORATION


The invention relates to antigen peptide derived from the Nectin4 and its use for preventing and treating cancer.

Over the recent years, the understanding of tumor biology processes lead to the development of targeted therapies like tyrosine kinase inhibitors or monoclonal antibodies. Recent results obtained with monoclonal antibodies validated the immunotherapy approach. Induction of immunity by cancer vaccines is thought to induce immune memory and thereby prevent tumor development. Many immunotherapeutic approaches are aimed to stimulate anti tumor CD8+ CTL responses. New cell surface expressed tumor associated antigens (TAA) that are shared among different tumors and not expressed in normal tissues are attractive candidates for used in vaccines.
The inventors recently described a new tumor associated antigen named Nectin4 [S. Fabre-Lafay et al., 2007] which have been described as a new TAA in 50%, 49% and 86% of breast, ovarian and lung carcinomas respectively. Moreover, a soluble form of Nectin4 is found in sera of patients and Nectin4 expression is mainly found in tumors with adverse prognosis. These characteristics assigned Nectin4 as a potent candidate for used in vaccination.
Nectin4 is already known in cancer. For example, patent application WO2004016799 discloses 9mer peptides obtainable from the Nectin4 sequence and their possible use as vaccine against cancer. However, this patent application doesn't disclose experimental results and doesn't give any information about relevant peptides.

INSERM (Institut National de la Sante et de la Recherche Medicale)


A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to thereby apply disturb to all of the word lines one by one; and (l) reading and confirming the first piece data from the memory cell array.

1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a word line decoder and high-speed disturb testing method, which is for the purpose of reducing the time required for the disturb test.
2. Description of the Related Art
The development of a semiconductor fabrication technique realizes smaller but more complicated circuits. Thus, a memory device is becoming more dense as the number of memory cell per unit area is increased. However, this plane and vertical decrease of the memory device requires more complicated and precise fabrication process, and thus the memory device accomplished by this process needs a complicated test requiring longer time in order to guarantee its reliability and quality. Practically, the performance of a memory device cannot be guaranteed even though its memory cell passes a test of reading or writing data "1" or "0". Complicated and densely arranged memory cells of a highly integrated memory device may become poor due to the interaction between them. How much the interaction affects the memory device depends on various causes such as memory structure, addressing circuit, the amount of substrate resistance, characteristic and structure of a memory cell or variation in the fabrication process. As a result, defects in memory devices appear in various types, and a test for screening these defects becomes various and complicated. This requires longer test time.
As a typical memory testing method, march test or checker board test is known. The disturb test shown in FIG. 1 approves itself effective for screening the defects of DRAM, and thus it is widely used. The disturb test can screen the soft error which inverts data of neighboring cell from "1" to "0" in case that all memory cells are functionally normally operated but have the disturb as shown in FIG. 1, which means repeatedly accessing the same address data. The most important condition of the disturb test is that a word line is repeatedly activated when data "0" is stored in the disturb cell and its neighboring cells have data "1".
FIG. 2 is a cross-sectional view showing the mechanism of the disturb test. Referring to FIG. 2, when a silicon pit 20 is generated in a gate oxide 10 due to a particle, transistors are normally operated but electron impact ionization occurs according to a high electric field in the silicon pit, to thereby generate holes and electrons. These holes move toward a substrate 100, and produce an ohmic drop in the substrate. Then, a substrate voltage partially increased according to the ohmic drop makes a bit line 30 grounded at 0V forward bias. By doing so, minor carriers of electrons are injected from bit line 30 into substrate 100. Thereafter, the electrons are transmitted and united with holes in a neighboring cell having data "1", thereby generating a cell leakage current. As a result, the soft error is induced. Furthermore, in case that the disturb is applied for a longer time, the gradual propagation of the error in a radial manner can be easily explained with regard to the fact that the electrons injected from the bit line are radially diffused.
As described above, the disturb test is based on the fact that the bit line becomes forward-biased according to the partial increase of the substrate voltage in case that the word line is repeatedly activated at a state that a predetermined data pattern is maintained. Here, it should be noted that poor cells are locally produced, and two poor cells having a distance from each other do not interfere to each other. Moreover, it is important that the word line is activated without regard to reading and writing data "0".
However, in the aforementioned conventional disturb test, the time required for the test is very long because the same word line should be repeatedly activated. It is desirable that test time becomes short in order to secure competitiveness in the highly integrated memory device production. In the fabrication of the semiconductor memory device, its fabrication cost is fixed owing to the development of the fabrication process regardless of increase in integration. However, the increased integration also increases the number of cell to be tested, and thus the test time becomes longer. This raises the cost required for the test.
Practically, in case that the aforementioned disturb test is applied for a highly integrated memory device such as 64M or 256M DRAM, the total test time is so long that the test is difficult to apply in terms of its fabrication cost. On the other hand, in the highly integrated memory device, since the density of its memory cells is increased, the same kind of error occurs frequently.

High-speed disturb testing method and word line decoder in semiconductor memory device


An image forming apparatus includes: an image forming portion having an image carrying member, a charging device, an exposing device, and a developing device; a developing voltage power supply; a control portion; and an image density sensor. The developing device has a developer carrying member that carries two-component developer and a toner concentration sensor. The control portion senses toner concentration during calibration or during first image formation after calibration for correcting image density based on the sensing result from the image density sensor. If the difference Vtarget−V between the output value V of the toner concentration sensor actually sensed and a target value Vtarget of the toner concentration sensor to be observed when the toner concentration equals a reference concentration is equal to or larger than a predetermined value, the control portion performs calibration again when the amount of toner consumed after calibration reaches a predetermined threshold value.

The present disclosure relates to an image forming apparatus, such as a copier, a facsimile machine, or a printer, provided with a developing device that uses two-component developer containing magnetic carrier and toner. More particularly, the present disclosure relates to a method of predicting variation of the toner concentration in developer in a developing device.
Conventionally, as developing methods that use dry toner in image forming apparatuses employing an electrophotographic process, there are known a one-component developing method that uses no carrier and a two-component developing method that uses two-component developer, that is, developer in which non-magnetic toner is electrostatically charged using magnetic carrier, and that develops an electrostatic latent image on an image carrying member (photosensitive member) with a magnetic brush formed of magnetic carrier and toner that is formed on a developing roller.
In a developing device employing a two-component developing method, the toner concentration (the ratio of toner to carrier in developer) in the developing device is sensed by a toner concentration sensor, and as much toner as consumed by printing and the like is newly fed in. However, if the output of the toner concentration sensor varies due to a factor, such as temperature, other than variation of the toner concentration, toner concentration cannot be grasped accurately, with the result that, by unintended toner feeding, the actual value of the toner concentration may be higher than the intended toner concentration (reference concentration).
In that case, during disuse after the end of printing or the like, the temperature inside the developing device lowers and the output of the toner concentration sensor returns to normal; thus, printing may be performed with no new toner being fed in until the actual value of the toner concentration becomes equal to the reference concentration. Consequently, the amount of charge with which the toner inside the developing device is charged rises, and the developing performance of the toner falls; this may lead to a sharp drop in image density in subsequent printing. One measure is to correct the sensor output value in accordance with temperature, which is the factor causing variation of the sensor output, and this alleviates the increase or decrease in the toner concentration. However, increasing the accuracy of the sensing of the toner concentration requires a plurality of temperature sensors, and this leads to increased costs.
As one method of alleviating a drop in image density resulting from variation of toner concentration, there is known, for example, an image forming apparatus comprising a toner image forming means for forming a toner image on an intermediary transfer belt; a test image forming means for forming a test image between two toner images on the intermediary transfer belt; a density sensing means for sensing the density of the test image; a difference calculating means for calculating the difference between a predetermined ideal value and the sensed density; and an increasing-decreasing means for increasing and decreasing the developing voltage in accordance with the difference, the image forming apparatus thus being able to correct density promptly in response to a change in developing characteristics.


The present invention relates to a reciprocating saw tool (10) having a motor drive (17) with a reciprocating driver (21) for a tool (15) and having a mass equilibrating body (22). In addition, a device (20) is provided, which serves to convert a rotary movement of the motor drive (17) into a reciprocating movement of the reciprocating driver (21) along a first movement axis (41) and an opposite reciprocating movement of the mass equilibrating body (22) along a second movement axis (42). For improving the sawing performance, the mass equilibrating body (22) is guided at an angle α to the reciprocating driver (21) so that its movement axis (42) is constantly at an angle to the movement axis (41) of the reciprocating driver (21).

The present invention relates to a saber saw tool having a motor drive with a reciprocating driver means for a tool having a mass equilibrating body and a device for converting a rotary movement of the motor drive into a reciprocating movement of the reciprocating means along a first movement axis and an opposite movement axis. In this tool the mass equilibrating body is guided at an angle α to the reciprocating driver means such that the movement axis runs constant at an angle to the movement axis of the reciprocating driver means. This type of saber saw tool is a saber saw or a jigsaw, wherein a saw blade can be displaced in a reciprocating movement using a driving arrangement.
In saber saw tools a counterweight is provided for balancing the unbalance of the reciprocating means such as a stroke rod, which is operated with the reciprocating means in the direction opposite to the drive train.
U.S. Pat. No. 6,634,107 discloses this type of weight compensation in a driving arrangement of a reciprocating saber saw, which can be operated in an oscillating reciprocating mode or in a purely reciprocating mode. In the aforementioned driving arrangement, a counterweight is operated by a driven shaft opposite to a stroke rod. In oscillating operation of the oscillating reciprocating saw, the direction of movement of the stroke rod in the course of the oscillating movement is brought intermittently into a tilted position relative to the direction of movement of the counterweight. In pure reciprocating operation, on the other hand, the directions of movement of the stroke rod and the counterweight run parallel to each other.
In U.S. Pat. No. 6,634,107, with the movement of the stroke rod and, thereby, of the plunger and counterweigh parallel to each other and with both the plunger and the counterweight having centroids that agree with each other, no torque and no immanent contact force, which can be superimposed on the contact force applied by the saw user, is generated during the pure reciprocating mode. With the cutting performance being determined only by the contact force applied by the user, the cutting performance of the saw in pure reciprocating mode is rather low.


A digital footprint driven multi-channel integrated support system assists a user in managing electronic components based on his or her digital footprint. The digital footprint driven multi-channel integrated support system delivers a dramatically improved ‘digital home support’ experience across multiple support channels (e.g., ‘on-the-box’, web, IVR, agent voice, agent chat, agent email, and more). The digital footprint driven multi-channel integrated support system generates, displays, and uses a ‘digital footprint’ of the components within the home, such as computer hardware/software, computer peripherals, audio/visual equipment, gaming hardware/software, home security hardware/software, or other electronic components.

1. Technical Field
This application relates to integration and support of electronic devices. In particular, this application relates to a multi-channel integrated support system that provides support to a consumer based on his or her digital footprint of electronic components.
2. Related Art
Most consumers have multiple electronic components in their home, office, car, and virtually every other location that they frequent. For example, at home, a consumer may have a personal computer, DVD player, CD player, Blu-Ray player, a high-definition television, a digital video recorder, and other components. The consumer may even own more than one of the same type of component. A consumer often goes through great lengths in setting up their devices and interconnecting them. For a consumer comfortable and familiar with electronic components, setting up electronic equipment may be an enjoyable process that takes a reasonable amount of time.
However, for the layman that is not familiar with electronics, setting up one electronic component can be a daunting task. Moreover, a layman having to set up more than one electronic component and interconnect them in a configuration in which they cooperate and communicate may take hours or even days. After spending a great deal of time working with the electronic components and interconnecting them, there is a strong disincentive for the layman to ever change the configuration.
However, replacing an electronic component in a system is inevitable. Electronic components are prone to failure, either in hardware or software. Additionally, electronic components quickly become outdated and replaced by components implementing improved visual or audio standards. In other situations, a consumer may want to replace an electronic component simply to upgrade to a newer model of the same type of electronic component, or replace one type of electronic component with a second type of electronic component (e.g., replace a HD-DVD player with a Blu-Ray player).
Replacing or upgrading the older electronic component may be daunting task in and of itself. There are many factors for a consumer to consider when purchasing a new electronic component to replace the older electronic component. Such factors include whether the new electronic component is compatible with the existing system, whether the new electronic component supports the other pre-existing electronic components, whether the person will need additional cables to connect the new electronic component with the existing system, and many other factors. The consumer that spent many hours setting up their existing system has little to no desire to determine whether the new electronic component will be compatible with the existing system. Moreover, with all the aforementioned considerations, it is quite difficult for a consumer to keep track of all the different types of scenarios that could arise with purchasing the new electronic component.
Furthermore, with any purchase of an electronic component, there is no guarantee that the component will initially function or continue to function satisfactorily. And while the technology savvy consumer may be able to readily coax the component into satisfactory performance, the layman may be completely unable to find a workable solution. In an increasingly complex and technology dependent world, inadequately performing electronic components pass beyond merely annoying to serious roadblocks to day-to-day existence.
At the same time, there are many technical problems associated with addressing the problems noted above. Examples of the technical problems include how to determine the compatibility of the newer electronic component with the existing electronic components, tracking the addition, removal, and modification of the electronic components in the existing system, presenting compatibility information in a meaningful and understandable manner, avoiding data loss, detecting when components are not performing adequately, providing meaningful help to assist the consumer with correcting component performance problems, and storing information that captures the electronic components in the consumer's environment.
Hence, there is a need to address the problems noted above and others previously experienced.

Digital footprint driven multi-channel integrated support system


Apparatuses, systems, and methods are disclosed for target detection based on collateral cleavage of a reporter by an enzyme. A biologically gated transistor may include a channel and a reporter moiety immobilized to the channel. The state of the reporter moiety may affect one or more output signals from the biologically gated transistor when excitation conditions are applied to the biologically gated transistor and a sample fluid is applied in contact with the channel. A sample fluid may include an enzyme configured to activate in response to a target nucleic acid to cleave the reporter moiety. Excitation circuitry may apply the excitation conditions, and measurement circuitry may measure output signals from the biologically gated transistor. An analysis module may determine a parameter relating to presence of the target nucleic acid, based on the one or more measurements.

Various biochemical assays exist for detecting a target molecule or moiety. Where the target is a nucleic acid, such as viral RNA sequence in a test to detect viral infection, or a cancer microRNA sequence in a test to detect cancer, some assays may involve amplifying the target using recombinase polymerase amplification (RPA), or another amplification technique. Operational requirements of a test system to detect a nucleic acid target and distinguish it from non-target sequences may be complex.

Electronic detection of a target based on enzymatic cleavage of a reporter moiety


The difficulties encountered in conventional LED multiple chip modules where wire bonding is used to connect the chips to electrodes can be overcome by using an interconnect to connect the chip to electrodes in a module where the interconnect is supported at points along its length other than at endpoints thereof, by a carrier either directly or indirectly. This improves reliability of the interconnect over conventional designs. Preferably, the contacts of the chips, and the electrodes are all within, or do not extend beyond, two parallel planes that are 400 microns apart for a compact design.

Rapid advances in high-brightness (HB) Light Emitting Diode (LED) technology in the last 10 years have opened up the possibility of using HB-LEDs as sources of general illumination. From 1995 through 2004, the HB-LED exhibited a remarkable growth history, with an average annual growth rate of 46% to a market size of $3.7 billion in 2004. Remarkable progress of LED in external quantum efficiency, lumen output and long lifetime has initiated a market in niche lighting applications. It is believed that LEDs can have a significant share of the general lighting market in the next 10 years.
The current disadvantages of LEDs compared to conventional light sources are their much higher cost and lower lumen output per device. For increasing lumen output, high-density assembly of multiple chips in a compact module is becoming the trend. In a multi-chip assembly, the output color can also be changed dynamically as needed. As the number of chips in an array increases, interconnections among chips become very difficult and suffer from reliability. Wire bonds from chip to chip or from chip to electrical contact are typically used for interconnection. However, limited space for wiring and wire protrusion are a big challenge. The present invention introduces a means to interconnect all chips all at once without using bond wires.


A patient support includes a lower frame, an upper frame supported above the lower frame, an equipment carrier coupled to the upper frame, and an actuator operable to adjust the orientation of the equipment carrier to compensate for the upper frame changing its orientation between the Trendelenberg and reverse Trendelenberg positions.

The present disclosure relates to an equipment support rail for supporting patient care equipment, such as an infusion management system, adjacent to a patient support, such as a hospital bed.
Hospitalized patients often require patient care equipment to be in close proximity during hospital care. Such patient care equipment is typically supported on a patient care equipment support carried by a support structure, such as a service column, a hospital bed, and the like. Illustratively, the patient care equipment includes heart monitoring equipment, medical gas delivery equipment, infusion management systems, IV bags, patient monitors, equipment monitors, defibrillators, and the like, many of which directly connect to the patient via lines or tubes.
Many hospital beds are movable between a Trendelenberg position and a reverse Trendelenberg position. It is desirable to maintain the vertical orientation of the patient care equipment support carried by the hospital bed as the hospital bed moves between the Trendelenberg and reverse Trendelenberg positions.


In a transmission grating as a dispersive element, diffraction efficiency is enhanced and manufacturing costs are considerably reduced. A dispersive element includes resin members for forming a diffraction grating, being composed of a plurality of diffraction grating members having a cross-sectional shape respectively surrounded by two straight lines such as a triangular shape, and metal members as light-shielding members each being formed on corresponding one of the diffraction grating members at one side of the diffraction grating member along any of the straight line and the curved line of the cross-sectional shape of the diffraction grating member formed by the resin member. The metal members are configured to reduce zero-order transmitted light with respect to incident light, and to enhance diffraction efficiency of first-order transmitted light.

The present invention generally relates to dispersive elements and the like, and more specifically to dispersive elements and the like such as transmission gratings used in optical instruments.
Diffraction gratings are used in various optical instruments. Specifically, many diffraction gratings are used in spectrometers, wave filters and the like to utilize sharp dispersion characteristics thereof. Moreover, it is possible to manufacture the diffraction gratings while arbitrarily determining pitches thereof. Accordingly, a diffraction grating is sometimes used as an angle changing element, a light separating and mixing element or the like in an instrument using a light source such as a laser. The application of the diffraction grating also spreads to the field of displays where light is used as a means of expression instead of a means of communication.
There are already numerous basic researches and implementation examples involving the diffraction gratings, which are compiled in "Introduction to diffractive optical elements" (edited by optical design research group, Optical Society of Japan affiliated to The Japan Society of Applied Physics, published by The Optronics, Co., Ltd.) or the like, for example. To enhance diffraction efficiency, transmission gratings include a blazed type, a binary type, and the like.
FIG. 11 is a view for explaining a configuration of a conventionally used blazed-type diffraction grating. The blazed-type diffraction grating is designed to have a triangular cross-sectional shape with two straight lines so as to enhance the diffraction efficiency for a specific wavelength. That is, as shown in FIG. 11, the surface shape of the blazed-type diffraction grating is formed into grooves with triangular cross-sectional shapes (saw-tooth shapes), and a base angle of this triangle is equivalent to a blaze angle.
Meanwhile, an unillustrated binary-type diffraction grating includes finely arranged rectangles with different levels in terms of cross-sectional shapes. Such a shape is formed by lithography or electron beam drawing.
In the meantime, instead of the diffraction grating, there is also an element formed by arranging metal thin lines as polarizers ("Basic optics", co-authored by Keiei Kudo and Fumiya Uehara, Gendai Kogaku Sha). This element is formed by arranging metal thin lines such as wires evenly in a lattice and is configured to utilize functions of absorbing or reflecting parallel polarized components with respect to the thin lines and to transmit only perpendicular polarized light with respect to the thin lines. This element is normally referred to as a wire grid polarizer. In general, the thin lines can be formed at intervals of 1μm at the smallest. Accordingly, the use of the wire grid polarizer is limited to a linear polarizer for infrared rays, for example. Based on the same principle, there is also provided a type of a reflection grating called an echelette grating with shallow blaze angles, in which grating constant is reduced by forming metal thin lines thereon by means of oblique evaporation of metal.
FIG. 12 is a view showing an example of the wire grid polarizer. Here, the shape of the echelette grating as the reflection grating is utilized to form the metal thin lines on ridge portions by oblique evaporation of the metal. By narrowing the grating constant, the wire-grid polarizer is used as a linear polarizer in the range from near infrared rays to visible light. In such a polarization element, the widths of the metal thin lines are made as small as possible by means of evaporating the metal only on the ridge portions of the diffraction grating having triangular cross sections. This is because an increase in the width of the metal thin line causes a decline in efficiency as the polarizer due to an increase in intensity of first-order diffracted light. In general, the polarizer does not function properly unless the intervals of the thin lines are set to one-tenth or below of a wavelength and the widths thereof are set to one-hundredth of the wavelength. Since an element of this kind is used in the form of vertical incidence and transmission with respect to the surface thereof, the original function as the echelette grating is also restrained.
In the meantime, among the related art disclosed in patent publications, there is a technique adopted as a method of manufacturing a diffraction grating for use in photoresist, in which a metal-deposited pattern is formed only on one oblique surface of a diffraction grating, for example (see Patent Document 1, for example). Moreover, there is also disclosed a technique including the steps of forming a resist film only on one oblique surface by oblique evaporation, etching, and then removing the obliquely evaporated resist film (see Patent Document 2, for example).
[Patent Document 1]
Japanese Unexamined Patent Publication No. 63 (1988)-71851 (Page 3, FIG. 1)
[Patent Document 2]
Japanese Unexamined Patent Publication No. 59 (1984)-210403 (Pages 2 to 3, FIG. 1)
Now, in the above-described diffraction grating of the binary type, it is necessary to finely arrange rectangles with different levels in terms of cross-sectional shapes. Accordingly, there are numerous manufacturing processes, and an obtained diffraction grating is very expensive. On the other hand, the blazed type can be manufactured by molding or resin molding through press work as long as a mould is prepared. Accordingly, the blazed type is less expensive and excellent in mass production capability. However, first-order diffraction efficiency of a transmission grating of the blazed type is limited to about 20% at the maximum. Accordingly, when the efficiency is raised for a specific wavelength, a trouble arises in a device dealing with a multi-color light source such as a display because the efficiency of other wavelengths is reduced. Therefore, when the transmission grating of the blazed type is used as a diffraction element, it is necessary to raise the diffraction efficiency and particularly to reduce zero-order transmitted light.
That is, when the transmission grating is used, the zero-order diffracted light, i.e. the directly transmitted incident light inevitably occurs. However, the zero-order diffracted light not only deteriorates utilization efficiency of the light but also incurs stray light for other optical devices located in the vicinity, and thereby causing a problem in terms of a device layout and accuracy. Accordingly, to enhance the diffraction efficiency, it is effective to reduce the zero-order transmitted light.
In the meantime, to enhance the diffraction efficiency, it is necessary to form a diffraction grating member of the diffraction grating into an optimal shape. However, such an optimal shape is complicated and delicate. Accordingly, it is necessary to use electron beam drawing, lithographic technology, and the like upon formation. Since a small size is sufficient for use in the field of optical communication or the like, such a process is relatively easy. However, for use in a display or a projector, the size of the diffraction grating member needs to be as large as several centimeters to 30 centimeters each. Such a diffraction grating member is difficult to process, or even if processed, applicable process costs will be enormous. For this reason, there is an increasing demand for a diffraction grating in the field of a display system, for example, which has a large size, capability of formation at low costs, high diffraction efficiency, and a performance to reduce the zero-order transmitted light in particular. Such a demand is high especially in the field of a liquid crystal display which does not apply a color filter, and the like.
The wire grid polarizer using the echelette grating shown in FIG. 12 is not an application as the diffraction grating in a dispersive element for selecting a specific wavelength or the like, but is merely an application as the polarizer for absorbing/reflecting the polarized components parallel to the thin lines. Accordingly, the metal is evaporated only on the ridge portions of the asperities. It is not possible to reduce the zero-order diffracted light and to enhance the diffraction efficiency when this element is used as the diffraction grating.
Meanwhile, although the oblique evaporation is performed in the technique according to Patent Document 2, the film formed by the oblique evaporation is a resist film and the evaporated film is removed in a finished product. For this reason, no metal film is formed on the produced diffraction grating. Therefore, it is not possible to achieve enhancement of the diffraction efficiency by reducing the zero-order transmitted light in the diffraction grating as the dispersive element.
Moreover, although the metal is obliquely evaporated according to Patent Document 1, the technique of Patent Document 1 is intended to be used as photoresist but is not designed for use in the diffraction grating as the dispersive element. For this reason, the technique according to Patent Document 1 considers a case where a contrast ratio of a projection pattern of the diffraction grating becomes largest, and therefore a semitransparent film is selected as the metal film to be obliquely evaporated so that an intensity ratio between zero-order diffracted light and first-order diffracted light becomes 1 to 1 ratio. To be more precise, metal such as chromium oxide is thinly evaporated in a thickness from 10 to 100 nm. Therefore, even if the technique according to Patent Document 1 is adopted, it is not possible to achieve enhancement of the diffraction efficiency by reducing the zero-order diffracted light. Accordingly, this technique has a difficulty in achieving a performance required in recent years as the diffraction grating to be used in the dispersive element.

Dispersive element, diffraction grating, color display device, demultiplexer, and diffraction grating manufacture

International Business Machines Corporation


A military vehicle with a turbine engine mounted on an outer rear corner of the vehicle, with the engine being installed in a vertical orientation in order to save critical space. The vehicle is provided with access hatches which enable operators to easily work on the engine and related power generation components. The positioning of the engine allows the crew of the vehicle to be shielded from the heat, noise, and exhaust of the engine. The rear positioning of the engine also provides improved survivability of the engine, as well as a reduced heat signature for the vehicle. Finally, the unique engine placement provides easy access for maintenance and removal of components or component modules.

1. Field of the Invention
The present invention relates generally to military vehicles, and more particularly is a vehicle with a vertically mounted turbine engine situated at the rear end of the vehicle.
2. Description of the Prior Art
Current art vehicles most often have a front end, horizontally mounted engine. The frontal location exposes the engine to greater hazards, and exposes the crew of the vehicle to the noise and exhaust of the engine. To work on the engine, access is gained through an access hatch in the top of the vehicle. The operator therefore either has to reach into the hatch and work, or hoist out the engine if large repairs are needed.
In current art vehicles, the engine is mounted in the main part of the vehicle hull. This is true whether the engine is mounted in the front, back, or middle of the vehicle. Often, the operator has to enter the vehicle interior in order to perform maintenance or repairs. Because of the need for at least some protection of the engine, access is often limited.
Finally, the horizontal configuration of current art engines requires a significant amount of space for the power plant.
Accordingly, it is an object of the present invention to provide a vehicle with a turbine engine that is mounted on a rear corner of the vehicle.
It is another object of the present invention to provide a vehicle design that separates the crew from the noise, heat and exhaust of the engine.
It is still another object of the present invention to provide a vehicle with improved protection for the engine and associated components.
It is yet another object of the present invention to provide a vehicle with direct access to the engine for maintenance and repairs.

Rear mounted engine design with improved maintenance access for a military vehicle


A method and system for regulating packet flow to a downstream entity capable of forwarding packets to a plurality of intermediate destinations. The method includes maintaining a database of queues, each queue in the database being associated with packets intended to be forwarded to a corresponding one of a plurality of final destinations via a corresponding one of the intermediate destinations. Each queue in the database is further associated with a state that is either active or inactive. Upon receipt of a message from the downstream entity indicating a reduced (increased) ability of a particular one of the intermediate destinations to accept packets intended to be forwarded to a particular one of the final destinations, the method provides for rendering inactive (active) the state of the queue associated with packets intended to be forwarded to the particular final destination via the particular intermediate destination.

A router is a device with input ports and output ports, and capable of deciding to which output port it should forward a packet received via one of its input ports so as to move the packet closer to an end destination (usually specified within the packet itself). A device of this type may be equipped with a plurality of internal switching stages, where packets pass through a series of one or more intermediate (or "next hop") ports before emerging at a "final hop" port corresponding to one of the output ports of the router.
One of the advantages of packet forwarding systems is that data of varying priorities (or, more generally, service "classes") can be transmitted simultaneously using the same physical link. Thus, a stream of packets arriving at an input port of a router may contain packets corresponding to different service classes. In the following, packets that belong to the same service class and which are forwarded to the same final hop port will be said to belong to the same "flow".
It is to be noted that the next hop port for packets belonging to the same flow might be different from one packet to the next, depending on such factors as packet attributes, load balancing issues, and so on. Therefore, it is possible that a sequence of packets belonging to the same flow will follow different paths through the router. Since each path may have its own delay and loss characteristics, packets belonging to the same flow may need to be reordered upon exiting the router in order to reconstitute the order in which the packets originally arrived at the router.
It should be apparent that the number of possible internal paths through the router for a single flow increases with the number of switching stages and also with the number of input-to-output combinations per switching stage. As routers become designed to take on numerous switching stages and/or numerous ports per stage, the number of possible paths for all possible flows through a router can be on the order of millions or more. Simply ignoring this in managing congestion only by final hop port is impractical in scalable systems because avoiding internal flow convergence would require an N-fold switch fabric speedup to support N ports, which is impractical as the port count scales beyond a few ports. Faced with this immense and heretofore unimagined complexity, conventional routing algorithms are ill-equipped to deal with congestion, as is now explained.
Under some conditions, an output port of the router may become congested with respect to packets of a certain flow. This is typically the case for lower priority packets in a given flow but may generally affect packets belonging to any service class. In any event, it becomes impossible to send packets of a certain service class out of a given out output port of the router. Since a flow may consist of many different paths through the router, congestion affecting a flow at the output of the router will cause congestion along each of these individual paths. The severity of the congestion resulting at an individual next hop port that supports the affected flow will depend on such factors as the stage of switching at which the next hop port is located, the number of packets taking that path, the number of congested paths converging at that next hop port, etc. Because of variations in the severity of the congestion across different next hop ports, some of the next hop ports at an intermediate routing stage will no longer be capable of accepting packets belonging to the affected flow, while other next hop ports may still have the capacity to accept packets belonging to that flow. This also applies to situations where an intermediate hop port is congested that others for a flow due to degraded or non-functional switch fabric links, etc.
However, conventional routers do not have the capability to apply different scheduling paradigms to different packets belonging to the same flow. Therefore, in a situation such as the one just described, where different next hop ports at a same stage of switching have different capacities to accept packets belonging to an affected flow, a conventional router will either block/drop all packets belonging to the affected flow or will block/drop all packets going through each next hop port that supports the affected flow. The former option results in a reduction in the pipelining efficiency of a multi-stage router with a corresponding reduction in the ability of the router to operate at a high throughput when the congestion is short-lived and/or recurring, while the latter option results in reduced throughput and increased delay for all previously unaffected flows passing through the (now blocked) next hop ports.

Congestion management for packet routers


An apparatus and a method for controlling a driving mode of a vehicle are provided to control the driving mode according to a short term driving tendency and a long term driving tendency. The apparatus includes a driving information detector that detects driving information to determine driving tendency and a controller that calculates a short term driving tendency index based on the driving. The controller operates at least one of an engine and a transmission based on the short term driving tendency index and calculates a middle term driving tendency index using the short term driving tendency index. A delay time is then determined using the middle term driving tendency index. The controller enters a sport mode based on the short term driving tendency index and releases the sport mode after delaying the delay time when the short term driving tendency index satisfies releasing conditions of the sport mode.

(a) Field of the Invention
The present invention relates to an apparatus and a method for controlling a driving mode of a vehicle. More particularly, the present invention relates to an apparatus and a method for controlling a driving mode of a vehicle that controls the driving mode based on a short term driving tendency and a long term driving tendency of a driver.
(b) Description of the Related Art
Customer satisfaction of driving performance of a vehicle depends on how accurately the vehicle runs according to the driving tendency of the driver. While tendencies of the drivers vary, performance characteristics of a vehicle are set to one performance characteristic in the same type of vehicle model. Therefore, reaction of the vehicle may not coincide with the tendency of the driver.
Accordingly, when the driving tendency of the driver is detected and a shift of the vehicle is controlled to coincide with the tendency of the driver, customer satisfaction related to the driving performance may be maximized. Therefore, many methods of learning the driving tendency of the driver and controlling the shift according to the learned driving tendency have been developed.
Generally, a vehicle mode enters a sport mode from a normal mode when a short term driving tendency index is greater than a predetermined value. After that, the sport mode is released when the short term driving tendency index is less than or equal to the predetermined value, and thus, the vehicle mode returns to the normal mode. Entrance to the sport mode may be generated by a one-time rapid acceleration (short term driving tendency) or a continuous driving tendency (long term driving tendency). The sport mode should be immediately returned to the normal mode when the vehicle mode enters the sport mode according to the short term driving tendency. Further, the sport mode should be maintained when the vehicle mode enters sport mode according to the long term driving tendency.
However, the sport mode depending on the short term driving tendency may cause an acceleration complaint of the driver since the duration of the sport mode is determined to be substantially short. Moreover, the sport mode depending on the long term driving tendency may cause disharmony since the duration of the sport mode is determined to be substantially long.
The above information disclosed in this section is merely for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Apparatus and method for controlling driving mode of vehicle


The invention relates to compounds that are analogs of a cyclic peptide, cyclo[EKTOVNOGN] (SEQ ID NO: 13), AFPep, that has anti-estrotrophic activity. The analogs of the invention include peptides and peptidomimetics that inhibit estrogen receptor-dependent cell proliferation. The compounds of the invention are useful for treating cell proliferative disorders or physiological conditions characterized by undesirable or unwanted estrogen induced cell proliferation, including breast cancer.

Alpha-fetoprotein (AFP) is an embryo specific serum alpha-globulin glycoprotein that is synthesized in the fetal yolk sac and circulates through the serum of pregnant women (G. I. Abelev 1971). In the last several decades, clinical researchers have investigated the potential anti-estrogen and anti-breast cancer activities of AFP (Jacobson et al. 1990). A number of studies have since shown its effectiveness as a therapeutic agent to treat estrogen-dependent breast cancer, as well as its ability to prevent pre-malignant foci from developing into breast cancer. Specifically, these studies indicate that alpha-fetoprotein (AFP) interferes with estrogen-dependent responses, including the growth-promoting effects of estrogen on breast cancer (Bennett et al. 1998). U.S. Pat. Nos. 5,674,842 and 5,707,963 relate to a 34-amino acid peptide derived from alpha-fetoprotein that was shown to exhibit anti-estrotrophic activity. Subsequently, an 8-amino acid stretch of AFP, EMTPVNPG, (SEQ ID NO. 1), referred to as peptide P472-2, was identified as possessing anti-estrotrophic activity (Mesfin et al. 2000). Furthermore, U.S. Pat. Nos. 6,818,741 and 7,122,522 describe peptides of eight to twenty amino acids, including a cyclic 9-mer (AFPep) that is useful in reducing estrogen-stimulated growth of cells. Finally, peptides as small as from 4-7 amino acids have been shown to retain anti-estrogenic activity (U.S. Pat. No. 7,598,342)

Alpha-fetoprotein “ring and tail” peptides


An information transmitting device to supply operation data of a machine as needed and without unnecessary data. The information transmitting device includes information control device 4, remote base station 9, transmission means, e.g. communication satellite 6, and selected data outputting means for selecting and transmitting predetermined operation data from operation data collected. Information control device includes operation data collecting unit 4a and communication control unit 4b which includes transmitting and receiving parts. Selected data outputting means includes operation data selecting device 9e (external operating device 12) and, in information control device 4: identifier designating unit 4c for designating an identifier for selected operation data, identifier memory unit 4d, and transmission data preparing unit 4e for reading operation data, which correspond to an identifier designated by identifier designating unit 4c, from operation data collecting unit 4a, and preparing operation data for transmission.

As a conventional technique of this type, there is, for example, the technique disclosed in JP-A-11024744. According to this conventional technique, a construction machine is provided with sensors for detecting operation states, an operation data collecting device for collecting operation data detected by the sensor, and a communication device and antenna for transmitting the operation data collected in the operation data collecting device. The communication device includes a communication unit. Also disclosed are a base station for receiving signals, which have been outputted from the communication device, via a communication satellite, for example, and user equipment connected to the base station via a communication line. The base station is arranged at a place remote from the construction machine, and the user equipment is such that can directly receive the operation data of the construction machine via the antenna arranged on the construction machine.
According to this conventional technique, the operation data collected by the operation data collecting device are transmitting in their entirety to the base station or the user equipment. By the base station or the user equipment, the operation data of the construction machine are controlled and can be retrieved by a user as needed.
With the above-described conventional technique, various operation data of the construction machine which is performing work can be obtained by the base station at the remote place or by the user equipment. These operation data can be used, for example, for predicting a maintenance schedule for the construction machine, predicting a replacement schedule to a new construction machine, and providing the customer of the construction machine with information on the construction machine.
When the construction machine is a hydraulic excavator or the like, for example, the operation data include an extremely wide variety of data, that is, data based on operating pilot pressures such as digging time, traveling time and swinging time, data based on a main hydraulic circuit such as pump load, swing load and travel load, data relating to an engine such as operation time, coolant temperature and fuel level, data associated with working oil such as working oil temperature and existence or non-existence of filter clogging, position data indicating an actual position of the construction machine, and data on the use of a special attachment, such as a breaker or crusher, mounted upon performing special work.
The conventional technique is high in communication cost, because it transmits the above-mentioned various data in their entirety, for example, to the base station via a communication satellite or to the user equipment by using a telephone line. When transmission is performed via the communication satellite, for example, the communication cost is the product of the size of data and a unit price per byte. When the telephone line is used, on the other hand, the communication cost is the product of time of transmission, which is determined depending upon the size of data, and a unit price per unit time. Accordingly, the communication cost increases with the size of data to be transmitted.
For the user, on the other hand, such various data as mentioned above are not often required in their entirety. Further, necessary operation data may differ depending upon the user.
The present invention has been completed in view of the above-mentioned current circumstance of the conventional technique, and has as an object thereof the provision of an information transmitting system for a construction machine, said information transmitting system being capable of supplying operation data of the construction machine as much as needed by its user or the like without unnecessary data.

Information transmission device for construction machine

Hitachi Construction Machinery Co., Ltd.


A lower manifold for a V-style internal combustion engine comprising at least three shells: a top shell for mating with an upper manifold; a left shell for mating with a left engine head; and a right shell for mating with a right engine head. The three shells are formed independently by injection molding and are joined as by vibration welding when aligned in a welding jig. The molds for the left and right shells are formed such that the seal ring groove has a rectangular cross-section having sidewalls perpendicular to the lower shell surface because each left and right shell has its own draft angle preferably perpendicular to its lower shell surface. The method and apparatus of the invention permits runner cross-sections to be significantly rounded, which improves air flow characteristics of the runners.

Intake manifolds formed by injection molding of polymers are well known in the engine arts. A manifold assembly typically comprises an upper manifold, containing the air entry and control apparatus and an air plenum, and a lower manifold, containing individual runners for supplying air distributed from the upper manifold to the individual intake valve ports in the engine head. The upper and lower manifolds typically are formed separately and are joined as by vibration welding prior to being assembled to an engine. A lower manifold typically is further manufactured by injection molding of a top shell and a bottom shell which are subsequently joined as by vibration welding.
In forming a lower manifold for a V-style engine, a serious manufacturing problem is encountered, which problem is solved by the present invention. In the prior art, the bottom shell is formed as a single unit having a die draft direction that must be along the vertical axis of the shell in order for the mold to exit both left and right banks of the runners. Such a lower manifold is said to be of "two-piece" construction (upper and lower shells). The required die draft direction and split core mold construction restricts the individual runners to substantially rectangular cross-sections which shape is sub-optimal for air delivery and fuel/air mixing.
Further, in order to avoid the use of auxiliary molding slides, which can result in significant increases in cost, molding cycle time, and risk in a productive environment, the seal groove in the manifold face that mates with an engine head must be formed with divergent walls to permit removal of the part from the mold. This groove geometry is not optimal because a ring seal is not reliably retained in the groove during engine assembly without resort to adhesives or mechanical retention devices. Optimally, the groove walls are parallel to each other and perpendicular to the mating faces of the manifold and the engine head to spontaneously retain a seal ring during engine assembly, but such grooves cannot be formed by die drafting along the shell axis without use of an auxiliary molding slide.
What is needed in the art is a method and apparatus of forming a lower shell for a V-style intake manifold wherein the seal groove walls are parallel to each other and perpendicular to the mating faces of the manifold and the engine head without use of an auxiliary molding slide.
It is a principal object of the present invention to provide a lower shell for a V-style intake manifold wherein the seal groove walls are parallel to each other and perpendicular to the mating faces of the manifold and the engine head.

Three-piece lower manifold for a V-style engine intake manifold