Disclosed is an image sensing device having a reduced number of transistors within each imager cell as compared to prior art devices. Each imager cell includes a photosensitive element providing a photocharge responsive to incoming light, and first, second and third transistors. The first transistor is coupled to an activation line, e.g., a row select line, that carries an activation signal to a first plurality of imager cells to selectively activate cells for image data readout. This transistor transfers the photocharge towards a reference circuit node within the image cell in response to the activation signal. The second transistor is operably coupled to the first transistor, and is operative to selectively set a voltage level at the reference node. The third transistor has a control terminal coupled to the reference node, and an output terminal coupled to an output data bus common to a second plurality of image cells, e.g., a column of cells. The third transistor providing an output signal on the data line related to the reference node voltage, which is indicative of an amount of light incident upon the photosensitive element.

With the advent of multimedia communications, there arises the need for low cost solid state image sensors to complement computers and communication devices to realize practical videotelephones and the like. The image input device is central to any teleconferencing and multimedia application. Recently, CMOS image sensors have been recognized as a viable candidate for the image input device. These image sensors also have other applications such as in robotics, machine vision and automotive applications. An important advantage of CMOS image sensors (or imagers) is that signal processing circuits can be readily integrated on the same chip as the imager, thus enabling the design of smart, single-chip camera systems. CMOS imagers are inherently lower cost than conventional charge coupled devices (CCDs) because they can be manufactured in conventional, widespread CMOS fabrication lines without any process modification.
FIG. 1 schematically illustrates one example of prior art active-pixel CMOS imager circuitry. Imager 10 is single-stage, charge coupled device (CCD) type of image sensor, as disclosed in an article by Mendis et al., entitled "A 128.times.128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems", IEEE Electron Devices Meeting, p. 583, 1993. A MOS photogate 6 is employed as the light sensitive element in each pixel (imager cell) 18. The transistors within each pixel 18 are typically NMOSFETS. The overall imager 10 is considered a CMOS imager since CMOS electronics are used in conjunction with the imager cells. For example, the transistors 3 within readout circuit 31 are typically PMOSFETS. As shown in the simplified block diagram of FIG. 2, imager 10 includes a plurality of cells 18 arranged in an array of rows R.sub.1 -R.sub.M and columns C.sub.1 -C.sub.N. Typically, only one row at a time is activated for image charge readout from all the cells 18 in that row. Timing and control logic 14 provides row select signals (VROW) on row select lines RSL.sub.1 -RSL.sub.M to select the active row. RESET pulses on lines RES.sub.1 to RES.sub.M are also generated by logic block 14 for application to cells 18. The light-induced charge from each activated cell is read out as a corresponding voltage on one of column buses 15.sub.1 to 15.sub.N, each of which is connected to the cells 18 in corresponding columns C.sub.1 to C.sub.N. The voltage on each line 15.sub.i corresponds, at any given time, to the image charge of only one activated cell in the associated column C.sub.i and activated row. Readout circuits 31.sub.1 to 31.sub.N read out the voltage of the activated cell in the corresponding column 15.sub.1 -15.sub.N. A load transistor 28 is utilized on each column bus. Capacitance Cc represents the bus line capacitance. Bus lines 19.sub.1 to 19.sub.N carry voltages VDD, VPG and VTX to the respective cells 18. Processing/image storage electronics 16 receives the voltages from the readout circuits for storage in memory and subsequent processing and display. Logic blocks 14 and 16 are clock synchronized.
As shown in FIG. 1, within each cell 18, a small surface channel CCD is fabricated. Photo-charge "q" collected under photogate transistor 6 is transferred through a dc-biased transfer gate transistor 8 to a floating diffusion diode 7 formed beneath substrate surface 9. This floating diode 7 is periodically dc-restored by the application of a logic high RESET pulse to the gate of reset FET 11, thus resetting the potential of diode 7 (i.e., at circuit node 17) to a voltage determined by the threshold voltage of FET 11 and the power supply voltage (VDD). Following each diode reset cycle, the photo-charge is transferred to floating diode 7. The voltage on diode 7 then corresponds to the intensity of light incident upon imager cell 18. This voltage sets the potential of the gate of source follower FET 13, which amplifies or buffers the voltage appearing at its gate terminal for subsequent readout. When row select transistor 12 is turned ON by a VROW pulse on row select line RSL, the voltage at circuit node 17 is detected by readout circuit 31 detecting corresponding voltage on column bus 15.
The reset noise is removed by a variation of the correlated double sampling technique as disclosed in an article by White et al., entitled "Characterization of Surface Channel CCD Image Arrays at Low Light Levels", IEEE Journal of Solid State Circuits, vol. SC-9, p.1, 1974. To remove reset noise (kT/C noise) the signal level measured on column bus 15 is subtracted from the reset level on the column bus obtained just prior to the transfer of photo-charge to diode 7. In the embodiment of Mendis et al., the reset level and the signal level are stored on two separate sample and hold capacitors CR and CS, via two separate switches S1 and S2, respectively. Two identical readout circuit portions are required, one for the reset level, and one for the signal level. Further differential amplification at the multiplexed column output (within circuit block 16) is required to complete the reset noise removal operation.
One shortcoming of the Mendis-type cell 18 of FIG. 1 is that the row select transistor 12 is a relatively large MOSFET which occupies substantial space within the cell. Ideally, it is desirable to maximize the area within each pixel allocated to the light sensitive element (phototransistor or photodiode) to increase the resolution of the imager. Hence, the space occupied by FET 12 results in less surface area for photogate 6, thereby diminishing imager resolution and precluding any reduction in pixel size to improve resolution further. In general, it would be desirable to employ as little electronics as possible within each imager cell to maximize available space for the light sensitive element and also, to simplify the image sensor manufacturing process. The present disclosure is a step in this direction.

International Business Machines Corporation


A light activated power indicator includes an indicator and a receptor circuit with a light sensitive device electrically connected to the indicator. The light activated power indicator further includes a first terminal electrically coupled to a first end of the receptor circuit and a second terminal electrically coupled to a second end of the receptor circuit wherein the indicator indicates a state of charge of an electrical storage device when the light sensitive device is exposed to one or more wavelengths lying within a response spectrum.

On-cell indicators require a user to press one or two buttons, wait for several seconds and then observe an indicator that shows the state of charge of the battery. This is inconvenient for the users because they must remove the batteries from the device, hold the battery and press the button(s). The user must then reinstall the battery into the device. This is cumbersome and time consuming.
Electrochromic displays draw very little power from the cell being tested and can therefore remain on and allow the consumer to just look at the cell to determine the state of charge. However, the current state-of the-art in electrochromic indicator technology has short operational life if it is continuously powered in the on condition. The short operational life could be as short as a few weeks to as long as about a couple of months.
Accordingly, a need exists for improved on-cell indicators.


For delivering supply power evenly into chip, a semiconductor device includes plural power supply pads 17a and grounding pads 18a, arranged in alternation in X-direction. The device also includes first upper layer power supply wire 17b, extending in X-direction and connected to first ends of the power supply pads 17, a first upper layer grounding wire 18b, extending in X-direction and connected to second end, opposing first end, of the grounding pads 18a in X-direction. A second upper layer power supply wire 17c extending between first upper layer power supply wire 17b and first upper layer grounding wire 18b, from the power supply pad 17a nearly to neighboring grounding pad 18a, and second upper layer grounding wire 18c extending between first upper layer power supply wire 17b and first upper layer grounding wire 18b, from the grounding pad 18a nearly to neighboring power supply pad 17a. The pads or wires 17a, 17b, 17c, 18a, 18b and 18c are formed on the same pad layer.

In a certain semiconductor device (semiconductor chip), including an on-chip LSI (Large Scale Integrated Circuit), such as a micro-processor, a large number of protuberant electrodes (bumps) are formed on each pad formed on the chip surface. The chip is mounted on a wiring board, with its surface carrying the bumps directing downwards, so that the bumps will be directly connected to land wires on the wiring board, in which the bumps are electrically connected to outside. This semiconductor device is generally termed a flip chip. With the semiconductor device of the flip chip system, to enable unit cells to carry out accurate logic operations, the power supply wiring and the grounding wiring are arranged so as to reduce the voltage drop, in such a manner as to enable the power from the power supply to be delivered uniformly and efficiently within the chip.
A semiconductor device of the related art, supplying the power uniformly and efficiently within the chip, is disclosed in Patent Document 1, and is shown herein in FIGS. 9 and 10. From a power supply electrode 103, provided on the surface of a semiconductor chip 105, power supply wires 107, connected to this power supply electrode 103, are derived and extended in a direction X. From a grounding electrode 104, grounding wires 108, connected to this grounding electrode 104, are derived and extended in the direction X in adjacency to the power supply wire 107. A lower layer power supply wire 110 is formed in a layer below the power supply wires 107 for extending in a direction Y substantially orthogonal to the direction of the power supply wires 107. The lower layer power supply wire 110 is connected to the power supply wires 107. A lower layer grounding wire 113 is formed in a layer below the grounding wires 108 for extending in the direction Y substantially orthogonal to the direction of the grounding wires 108. The lower layer grounding wire 113 is connected to the grounding wires 108 (Patent Document 1, FIGS. 9 and 10).
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2001-203271A

Semiconductor device and semiconductor package


A device providing performance of CPR without need to exert forces of such magnitude that the patient may be injured, and which further provides performance of defibrillation and ventilation. The CPR assist device according to the present invention is composed generally of an elongate column member, handles mounted normal to the column member, a suction cup member mounted at one end of the column member, and a defibrillation system so that the patient may be defibrillated in conjunction with CPR. According to the method of the present invention, an aid giver places the suction cup member of the CPR assist device on the chest of the patient, then grabs the handles and proceeds to alternately press on the chest and pull from the chest. The suction cup member causes the chest to compress and expand, thereby creating a churning action within the chest cavity that resuscitates the patient. An added benefit of the CPR assist device is that the expansion of the chest cavity as the suction cup member is pulled away from the chest will stimulate lung action of the patient. Defibrillation is provided by the aid giver actuating one or more switches on the column member which supplies electrical stimulation at electrodes mounted to the suction cup member. The defibrillation circuit may operate from household current or may be powered by an internal battery.

1. Field of the Invention
The present invention relates to the process of cardiopulmonary resuscitation (CPR), and more particularly to a device which aids in the performance of CPR.
2. Description of the Prior Art
Cardiopulmonary resuscitation, hereinafter ref erred to as "CPR", has become a standard first aid technique to attempt revival of at person who has suffered cardiac arrest. In CPR, the heels of both hands are placed one over the other, so as to periodically apply a force to the chest between the middle and lower third of the sternum. The force is applied about 60 to 80 times per minute. Ordinarily, the force required is considerable, on the order of 80 pounds, so that the chest may be pushed vertically downward 1.5 to 2 inches. A problem that can arise from this amount of force can include broken ribs, a lacerated liver, or other internal organ damage that itself can be lethal to the patient.
In the event cardiac arrest continues or cardiac rhythm is life-threatening defibrillation has become a standard technique of correction. In defibrillation, an electrical stimulation is provided to the chest which shocks the heart muscle, and thereby causes the heart to begin beating in its normal manner.
Another serious problem associated with cardiac arrest is that the patient may cease breathing. In the art it is the established practice to establish an airway in the patient, then administer mouth-to-mouth ventilation. A problem arises when ventilation must accompany CPR.
What is needed in the art is a way in which to perform CPR without need to exert forces of such magnitude that the patient may be injured, and further in which to perform defibrillation, as well as to perform ventilation.

Cardiopulmonary resuscitation assist device


A radio frequency transmitting device includes a frequency multiplier circuit, a mixer circuit, a power splitter, a plurality of phase shifting circuits, a plurality of amplifiers, and a plurality of antennas. The frequency multiplier circuit is configured to amplify a fundamental signal to generate a harmonic signal. The mixer circuit is configured to generate a RF signal based on an input signal and the harmonic signal. The power splitter is configured to generate a plurality of sub-RF signals. The phase shifting circuits are configured to shift the phase of the sub-RF signals. The amplifiers are configured to amplify the power of the sub-RF signals. The antennas are configured to transmit the sub-RF signals. Furthermore, a radio frequency receiving device is also disclosed herein.

1. Field of Invention
The present invention relates to wireless communication technology. More particularly, the present invention relates to a radio frequency (RF) transmitting device and a radio frequency receiving device.
2. Description of Related Art
With progression of technology, transmission ways among electrical elements change from wire connection (for example: transmitting through Universal Serial Bus (USB)) into wireless connection so as to improve inconvenience resulted by wire connection.
However, there are many problems resulted by wireless connection. For example, linearity of signals transmitted by a radio frequency transmission device and AM/AM distortion. In addition, matching problems and linearity are existed in a variable gain amplifier of a radio frequency transmitting device with bias tuning technology or current steering technology.
In view of the foregoing, there exist problems and disadvantages in the existing products that await further improvement. However, those skilled in the art sought vainly for a solution.

Radio frequency transmitting device and radio frequency receiving device


A plurality of samples of a signal are stored in a buffer, the signal corresponding to a navigation system. A plurality of starting locations in the buffer are determined, the plurality of starting locations corresponding to a plurality of correlations to be calculated. A plurality of correlations are calculated using i) a plurality of local replica signals, and ii) data read from the buffer using the plurality of starting locations, the local replica signals corresponding to pseudo random number (PRN) codes utilized by transmitting devices in the navigation system. The plurality of correlations are utilized to one or more of i) detect PRN codes in the signal, ii) detect one or more phase shifts associated with PRN codes, or iii) detect one or more frequency shifts associated with PRN codes.

The Global Positioning System (GPS) is a U.S. government-supported system for precise position and velocity determination of objects. Orbiting satellites emit coded radio frequency signals that are received and processed by receivers on or near the surface of the earth to obtain pseudorange measurements, approximate instantaneous distances between the satellites and receiver. Because the satellite orbits and signal transmission times are known precisely, the receipt time of a particular signal bit can be used to quantify the transit time or range to the particular satellite. The orbits of the GPS satellites are arranged in multiple planes so that signals can be received from at least four satellites at any point on or near the earth, allowing precise position and velocity measurements of the receiver. Each satellite continually transmits a spread-spectrum signal that is modulated by a pseudo-random number (PRN) code unique to the satellite. A receiver can therefore identify and separate signals from each satellite into separate channels, process the channel data separately, and combine the processed data to compute a position of the receiver. In addition to the PRN code, the signals are modulated by slower-varying data signals defining the satellite orbits and other relevant information needed for the computations. The most common PRN code is a binary sequence of 0's and 1's or −1's and +1's that modulates the carrier phase.
The PRN code is combined with a 50 Hz data stream using binary phase shift keying (BPSK), and thus the polarity of the PRN code potentially changes every 20 ms, i.e., a 180° phase shift in the PRN code can occur every 20 ms.
In the receiver, local signals corresponding to known PRN codes are generated and correlated with the received signals to detect PRN codes in the received signals. Since the time at which each bit of a known PRN code sequence is transmitted from the satellite is known, the time of receipt of each bit is a direct measure of the transmit time of the signal from the satellite to the receiver, and therefore a measure of the distance between the two. Based on the computed relative phase of the received signal, the receiver calculates the desired quantities of distance, velocity, etc.

Method and apparatus for correlating signals received from a navigation satellite system


According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate to a first temperature while supporting the substrate on a substrate support, and supplying a process gas into a process vessel accommodating the substrate support; (b) lowering a temperature of a low temperature structure provided in the process vessel to a second temperature lower than the first temperature by supplying an inert gas or air to a coolant flow path provided in the process vessel after (a) for a predetermined time, wherein defects occur when a cleaning gas is supplied to the low temperature structure at the first temperature; and (c) cleaning the low temperature structure by supplying the cleaning gas into the process vessel after (b).

According to some related arts, as a part of a manufacturing process of a semiconductor device, a process gas is supplied to a substrate in a process vessel to process a film on the substrate (that is, to perform a film process).
When the film process is performed using a substrate processing apparatus according to some related arts, deposits may adhere to an inside of the process vessel of the substrate processing apparatus. Therefore, after the film process, a cleaning process may be performed in which a cleaning gas is supplied into the process vessel to remove the deposits adhering to the inside of the process vessel.
However, when the cleaning process is performed at a high temperature after the film process is performed at a high temperature, defects may occur in some locations. Therefore, it is preferable to lower an inner temperature of the process vessel to a desired temperature before performing the cleaning process after the film process. However, in such a case, a downtime of the substrate processing apparatus may increase and an operating rate of the substrate processing apparatus may be affected.

Method of manufacturing semiconductor device


Examiner's permission under MPEP §608.01(q) and 37 CFR §1.125(b) is requested to submit a substitute specification and abstract. The substitute specification corrects typographical errors, grammar and formatting. No new matter has been added. The substitute specification and abstract contain no new matter to the specification of record. A marked-up version is attached along with a clean version in an appendix attached hereto.

Electronic circuits are increasingly being optimized for lower power and smaller size requirements for better incorporation into integrated circuit designs. The increase in complexity and gate count within integrated circuits also requires that electrical circuit testability be addressed in the designs of integrated circuits. One general methodology of integrated circuit testability is referred to as Level Sensitive Scan Design (LSSD). A LSSD circuit complies with a set of design rules that enhances the observability and controllability of digital circuit elements so as to enhance testability of a complex digital design circuit.
In a LSSD design, scan chains provide access and testing for the internal circuits of large-scale integrated (LSI) circuits, very large scale integrated (VLSI) circuits, and other integrated circuits. The scan chains can be configured as one long chain or multiple short chains. FIG. 1 illustrates a block diagram of an exemplary LSSD design circuit 100 The exemplary LSSD design circuit 100 includes multiple scan chains 110 interfacing with the logic circuitry 120.
FIG. 2 is a block diagram of a scan chain 110. The scan chain 110 generally includes a set of shift register latch blocks or data storage elements 210 connected in a series configuration.
These latch blocks 210 incorporate a design that allows data to be loaded into a shift register through an alternate data input. This alternate input is generally used for circuit test and stimulation and is sometimes referred to as a "scan input" since it allows a pre-defined state to be "scanned" into the sequential circuit using these register latch blocks. Loading a latch block with a particular value allows, for example, placing a sequential logic circuit into a desired state.
FIG. 3 is a block diagram of a typical latch block 210. The latch block 210 or shift register latch includes a pair of latches L1 and L2 where L1 310 is the "master" latch and L2 318 is the "slave" latch. The L1 latch or master latch 310 has two data ports, a system input port SYS 302 and an alternate data input port SCAN 306 and may be updated by either a functional clock C1 304 or a scan clock A 308.
In normal operation of the shift register block 210, data is provided on the system input port SYS 302 and this data value is selected for storage into latch L1 310 upon a transition of the functional clock C1 304 from low to high. The shift register block 210 is also able to select for storage data from the alternate data input port SCAN 306 by providing a data value on the alternate data input port SCAN 306 and then causing this value to be stored into latch L1 310 upon a transition of the scan clock "a" 308. Once a data value is stored in L1 310, this value is available, after a propagation delay, at the L1 Output 312. The logical value that is present on the L1 Output 312 is stored into latch L2 318 upon a transition of shift clock "b" 314 (or shift clock c2) from a logical low level to a logical high level. After the L1 Output 312 is stored into the L2 latch or slave latch 318 that logic value is available, after a propagation delay, on the L2 output 320.
A scan chain provides access to the internal parts of a chip and its function is critical in testing a chip. A problem arises, however, when a scan chain fails. Often scan chain fallout occurs early in the life cycle for new chip technology development, and quickly diagnosing any scan fails is critical to improving the process so that targeted manufacturing yield levels can be achieved.
Generally, scan chain fails can be divided into two categories: DC defects and broken. A broken scan chain is one that will not operate under any conditions (e.g., voltage, frequency, temperature). A scan chain containing DC defects will only operate under certain conditions (e.g., only between 1.2V and 1.3V). The condition or conditions under which a scan chain operates or fails will be referred to as the "operating region" and "failing region", respectively.
One method provides some success in diagnosing and locating a first failed register latch in a scan chain. This method contains the steps of loading the scan chain in the operating region, and unloading the scan chain in the failing region.
Another method provides some success in diagnosing and locating a last failed register latch in a scan chain. This method contains the steps of loading the scan chain in the failing region, and unloading the scan chain in the operating region.
To illustrate these methods, consider the following example of a scan chain 400 consisting of eight latches as shown in FIG. 4. Assume there is a defect 450 at the output of RML5 408 that causes the chain to be stuck-at "1" in the failing region, where RML means "Register Measure Latch." Using the first method, the scan chain 400 is loaded with all zeroes (0's) in the operating region, resulting in the value of each latch to be a zero or RML(1:8)='00000000'. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 400 from scan input 202 is shown in block 420. Next, the scan chain 400 is switched into the failing region and unloaded. The following data is attained: RML(1:8)='00001111'. From this data, it may be diagnosed that the DC fail occurs on RML5 408. The output taken from scan output 204 is shown in block 422 after all of the input value of zero has propagated through the scan chain 400.
To illustrate the second prior art method shown in FIG. 5 is a block diagram of an exemplary scan chain circuit with a DC defect 450 again at the output of RML 5 being scanned. Using the second method, the scan chain 400 is loaded with all zeroes (0's) in the failing region, resulting in RML(1:8)='11110000'. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 400 from scan input 202 is shown in block 520. Next, the scan chain is switched into the operating region and unloaded. The following data is attained: RML(1:8)="11110000". The output taken from scan output 204 is shown in block 522 after all of the input value of zero has propagated through the scan chain 400. From this data, it may be diagnosed that the DC fail occurs on RML5 408.
Now consider the following example of a scan chain 600 consisting of eight latches with two DC defects 652 and 654 as shown in FIG. 6. Assume there are defects at the outputs of RML5 608 and RML3 612 that cause the chain to be stuck-at "1" in the failing region. Using the first method, the scan chain 600 is loaded with all zeroes (0's) in the operating region, resulting in the value of each latch to be a zero or RML(1:8)='00000000'. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 600 from scan input 602 is shown in block 620. Next, the scan chain 600 is switched into the failing region and unloaded. The following data is attained: RML(1:8)='00111111'. The output taken from scan output 604 is shown in block 622 after all of the input value of zero has propagated through the scan chain 600. From this data, it may be diagnosed that the DC fail occurs on RML3 412.
To illustrate the second prior art method shown in FIG. 7 is a block diagram of an exemplary scan chain circuit with a two DC defect 652 and 654 being scanned. Using the second method, the scan chain is loaded with all zeroes (0's) in the failing region, which results in RML(1:8)='1111000'. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 600 from scan input 602 is shown in block 720. Next, the scan chain is switched into the operating region and unloaded. The following data is attained: RML(1:8)='1111000'. The output taken from scan output 604 is shown in block 722 after all of the input value of zero has propagated through the scan chain 600. From this data, it may be diagnosed that the DC fail or fault occurs on RML5 408.
When there are multiple DC defects in a scan chain, only the first and last defect in the scan chain can be diagnosed and identified using the two mentioned methods. Although this is useful, if there are multiple defects, for example a third defect at RML 3 which is between defect 652 of RML4 and defect 654 This third defect or inner defect (inner meaning after the first and last defect of a chain) is to be detected by these prior art methods, either separately or combined. Further any multiple defects that occur between a first defect and a last defect are not detected by these prior art method either, again either separately or combined.
Accordingly, there is a need for a method to diagnose and locate all multiple DC defects in a scan chain.

Diagnostic method for detection of multiple defects in a Level Sensitive Scan Design (LSSD)

International Business Machines Corporation


A universal joint yoke includes a yoke base and two yoke arms, each respectively having a through extending bearing bore, a circular arc groove having a center that is arranged on a bore axis or is off-set from the bore axis toward the yoke base, and at least one securing recess on the outer face. A separate securing element for each yoke arm has an engagement portion with an outer circumference that is adapted to the circular arc groove and engaging the same and at least one securing portion that projects from the securing element in the direction away from the center and that engages the at least one securing recess and that secures the securing element against rotation around the center. A securing device retains the securing elements on the universal joint yoke.

The invention relates to a fixation arrangement for bearing bushings on a universal joint yoke.
From DE 102 61 114 A1, different fixation arrangements for bearing bushings on a universal joint yoke are known and include a universal joint yoke with a yoke base that defines a longitudinal axis. From the yoke base, two yoke arms project. The yoke arms extend diametrically offset from the longitudinal axis in the same direction from the yoke base. Each yoke arm has a through-extending bearing bore, wherein the bearing bores of both yoke arms are centered on a common bore axis that intersects the longitudinal axis at a right angle. The yoke arms each have, respectively, on an outer face facing away from the longitudinal axis and offset towards the yoke base when seen in a longitudinal sectional view containing the bore axis and facing the bearing bore, a circular arc groove. The center of the circular arc groove is arranged on the bore axis. The bearing bushing includes a bushing bottom and a circumferential wall. It is accommodated in the bearing bore of one yoke arm, wherein the bushing bottom faces towards the outside. On its outer face, the bushing bottom has a journal that projects outwardly beyond the bearing bore and is provided with a circumferentially extending groove, which center is arranged on the bore axis. A securing element is provided, which is formed like a kidney-shaped bow and has two portions that are elastically deformable towards each other and of which the outer portion engages in the circular arc groove and the inner portion engages in the groove of the journal at the bushing bottom. Alternatively, a securing element in form of a locking plate is provided that has an outer circumference which is adapted to the circular arc groove and engages in the same with an engagement portion. Furthermore, this securing element has a through bore, through which a screw can be inserted into a central bore in the bushing bottom. Alternatively, a plate-like securing element is proposed with an outer circumference that is adapted to the circular arc groove and is provided with a central through bore, wherein a journal, arranged to the bushing bottom, passes through this bore. The securing element is secured in its position by a securing ring, which engages in a groove of the journal at the bushing bottom. Additionally, in all embodiments, at the circumferential ends of the circular arc groove, abutments can be provided that secure the securing element against rotation.
The above-described securing arrangements necessitate measures and processing steps on the universal joint yoke, as well as on the bearing bushing. The journals, attached at the outside on the bushing bottom of the bearing bushing, or the attachment means, e.g. screws, however, enable that to a significant degree in front of the end of the yoke arms, which is distanced to the yoke base, a reduction of the rotational diameter of the universal joint yoke in the assembled condition of the bearing bushings is achievable, but, however, still necessitate, in many areas, a larger rotational diameter and, thus, limit also the maximum articulation angle.

Fixation arrangement for bearing bushings on a universal joint yoke


A method of establishing a voice communication session with a multimedia access device employable in a multimedia communication system. In one embodiment, the method includes initiating a session request from a first endpoint communication device employing an instant messaging client and coupled to a packet based communication network. The method also includes processing the session request including emulating the instant messaging client for a second endpoint communication device coupled to said packet based communication network. The second endpoint communication device is a non-instant messaging based communication device. The method still further includes establishing a voice communication session between the first and second endpoint communication devices in response to the session request.

Computer networks, such as the Internet, are extensively used for storage and retrieval of a vast reservoir of information. Person to person communication, in the form of electronic mail ("e-mail"), has also become widely accepted as a replacement for conventional mail and facsimile. Any individual who has access to the Internet can establish an e-mail account and communicate with other individuals on the Internet.
With conventional forms of telecommunication services, such as communication via a plain old telephone service ("POTS"), person to person communication may be facilitated merely by a calling party dialing a telephone number of a called party via a telephone coupled to the public switched telephone network ("PSTN"). The PSTN provides the communications intelligence and delivery of analog and digital information to end users. In such instances, the calling party and called party may have different local service providers and long distance carriers providing services over the PSTN. In either case, the specific service providers of the calling party and called party are irrelevant as the network providers and communication systems employ standard communication protocols for communication of disparate communication devices over the PSTN.
Similarly, e-mail communications use a standard communication protocol that allows the transmission of messages between users that may have different service providers. A message sender can subscribe to or obtain an account with a first service provider and still send an e-mail message to a recipient even when the recipient subscribes to a second service provider. This is true even when each service provider may have a unique communication protocol to communicate with its own subscribers because the communication between service providers employs a standard communication protocol. For instance, when subscriber A sends a message to subscriber B associated with a different service provider, the service providers negotiate the transmission of the message therebetween employing a protocol common to both service providers.
A new form of e-mail communication, known as instant messaging, is gaining popularity among users of the Internet. As shown in a popular movie, "You've Got Mail," two individuals can engage in an ongoing electronic communication without the need for entering the recipient's e-mail address for each individual transmission. The advantage of instant messaging is that two or more individuals may engage in an ongoing electronic "chat" by simply typing a message on the keyboard and pressing the "Enter" button on the computer keyboard or by clicking on a "Send" icon to the computer display screen. Another popular feature that some Internet service providers offer is activity data that allows a user to monitor another subscriber's activity or presence (i.e., being logged on to a service) on the Internet. Yet another emerging service provided by some instant messaging service providers is voice services between subscribers via an instant messaging client, albeit a limited service capability and feature functionality.
Unfortunately, service providers do not employ a standard communication protocol for instant messaging or activity data. As a result, a particular service provider only supports instant messaging and activity data between its own subscribers. If a user wishes to send an instant message to an individual that subscribes to a second service provider, the user must also subscribe to the second service provider and logon to the second service provider system to engage in an instant messaging session with that particular individual. At the very least, this is a cumbersome procedure. Also, even if an individual subscribes to different service providers, the individual cannot engage in an instant messaging session with participants who are subscribers to the other service providers.
Similar issues are observed in the emerging voice via instant messaging area. Again, the respective instant messaging service providers employ a proprietary protocol to provide basic voice services for their subscriber base. Additionally, the voice services can only be accessed by the subscriber via the use of a complex equipment configuration including a personal computer, microphone, sound cards, speakers and several low level software applications with many inter-dependencies and other compatibility issues.
Regarding the types of communication networks, in the past voice and data communication networks were bifurcated wherein the voice communication networks handled voice traffic and data communication networks handled data traffic including e-mail and instant messaging type messages. The voice communication networks embodied networks such as the PSTN, which is a type of circuit switched communication network, whereas the data communication networks embodied networks such as the Internet, which is a packet based communication network. With the advent of protocols such as the voice over Internet protocol ("VoIP"), transmission of voice-to-voice communications over data communication networks is not only possible, but in vogue. To the contrary, however, communications between conventional voice communication networks and data communication networks is still not seamless. For example, while current instant messaging services allow for voice communications connected directly to data communication networks, telephone calls between a calling party using the PSTN and a called party connected to a data communication network with an instant messaging client, for example, has not been adequately addressed. The following examples further clarify the challenges posed to consumers of disparate services.
Suppose, for instance, that a user in a home environment has a single telephone line into the house. When that telephone line is being used, no other incoming telephone calls can be accepted by any member of the household. It would be useful if the consumer's Internet connection could also be used to facilitate telephone calls to the PSTN and act as a virtual second telephone line, without paying for the expense of having a second hardwired telephone line.
Similarly, suppose that a business would like its employees to have the ability to receive incoming telephone calls while away from the office or, in lieu of a second telephone line to the desktop, when connected to the employer's data communication network. While one solution may be to provide every employee with a cellular phone, the costs would be prohibitive. Since many employees have laptop computers for use away from the office, it would be cost effective and efficient if the employee could use a connection to the Internet or the corporate communication network to participate in telephone calls via the PSTN by using an instant messaging client.
Accordingly, what is needed in the art is a system and method that facilitates communication between users employing disparate communication devices and different service providers, preferably located within the customer premises that allows for onsite or remote configuration. In accordance therewith, it would be advantageous to facilitate communications, albeit voice or data communications, within a home or enterprise environment regardless of the communication transport network to a user thereof. As an example, a system that facilitates voice communications over the PSTN via an instant messaging client would be well received and solve a limitation in the field of computer telephony.

Multimedia access device and system employing the same


Cyclic A/D-conversion of an analog input signal is performed according to a new and inventive recursive algorithm which generates a Gray coded digital output signal. In cyclic A/D-conversion, the output bits are generated cyclically, one by one. According to the inventive Gray coding algorithm, the analog input signal is cyclically subjected to a sample and hold operation, selectively, depending on the previously generated output bit, to a signal inversion, to an amplification by two, and to an addition of a predetermined reference signal. In a cyclic A/D-converter architecture based on the recursive Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the cyclic A/D-converter according to the invention.

An analog-to-digital (A/D) converter is a circuit on the borderline between the analog domain and the digital domain which acts as an intermediary in the exchange of information between the two domains. As the name indicates, an A/D-converter converts or transforms analog input signals to digital output signals. An A/D-converter could be used for converting analog information such as audio signals or measurements of physical variables into numbers consisting of two-level digits or bits; a form suitable for digital processing. A/D-converters are found in numerous applications of all modern technologies. They are widely used in different fields of electronics and communication.
The accuracy of an A/D-converter naturally determines to what extent the digital output signal truly represents the analog input signal. The performance evaluation of an A/D-converter with regard to accuracy and distortion is normally based on the magnitude of the error generated in the A/D-conversion. In general, all A/D-converters suffer from offset errors due to imperfections in the circuit realizations of the converters. These offset errors will influence the behavior and performance of the A/D-converter.
A particular type of A/D-converter is the cyclic A/D-converter which utilizes the same functional blocks cyclically for bit-wise generation of all the bits of a digital output value. Conventionally, cyclic A/D-converters are constructed to generate digital output signals of regular binary code. In these conventional binary code cyclic A/D-converters, the offset errors propagate and accumulate in a strictly increasing manner during a conversion, thus limiting the accuracy of the converter and increasing the distortion. Relatively large differential and integral non-linearities will be introduced, and in the worst case scenario some output codes might be missing.

Cyclic analog-to-digital converter that reduces the accumulation of offset errors


A hydraulic circuit for a boom cylinder in a hydraulic shovel has a pressurized discharge fluid from a hydraulic pump that is driven by an engine, the pressurized discharge fluid supplied via a directional control valve for a boom into a retraction pressure chamber and an extension pressure chamber of a boom cylinder for swinging the boom upwards and downwards. A relief valve is included in a circuit for connecting the retraction pressure chamber of the boom cylinder to the boom directional control valve, the relief valve having a relief set pressure. A switching device is included for switching the relief set pressure to a low pressure as well as to a high pressure if the directional control valve is set at a position that is other than a neutral position thereof, when the engine is driven, the switching device being adapted to switch the relief set pressure to a high pressure when the engine is halted.

A hydraulic shovel has hitherto been known as shown, for example, in FIG. 1 of the drawings attached hereto. In such a hydraulic shovel, a lower vehicle body 2 that is equipped with a traveling body 1 has an upper vehicle body 3 mounted thereon as turnable, the said upper and lower vehicle bodies 2 and 3 constituting a vehicle body 4. A boom 5 is attached onto the said upper vehicle body 3 so as to be swung upwards and downwards by means of a boom cylinder 6. A forward end of the said boom 5 has an arm 7 attached thereto so as to be swung upwards and downwards by means of an arm cylinder 8. A forward end of the said arm 7 has a bucket 9 attached thereto so as to be turnable up and down by means of a bucket cylinder 10. Thus, the hydraulic shovel has been so configured that each of the boom 5 and the arm 7 may be swung upwards and downwards and the bucket 9 may be turned upwards and downwards, and has been used to perform an excavating operation.
A hydraulic circuit for such a hydraulic shovel is generally designed to supply a pressurized discharge fluid from a hydraulic pump into the boom cylinder 6, the arm cylinder 8 and the bucket cylinder 10 via a boom directional control valve, an arm directional control valve and a bucket directional control valve, respectively, to effect an extension and a retraction operation for each of these cylinders.
While an excavating operation is being carried out with a bucket with each of the cylinders expansion and retraction operated as shown in FIG. 1, it can be seen that if the load of excavation is increased due to the presence of a rock in the ground being excavated, the boom 5, the arm 7 and the bucket 9 will cease moving and will be made incapable of continuing the excavating operation. Then, it will become necessary to effect an extension operation for the boom cylinder 6 by acting on the boom directional control valve to swing the boom 5 upwards, thereby displacing the bucket 9 upwards.
Thus, since if a large load of excavation is encountered, it becomes necessary to operate the boom directional control valve to displace the bucket 9 upwards in the conventional hydraulic circuit, the operating efficiency has hitherto been poor and since the vehicle body is then flapped, the operation has also been burdensome for the operator.
In order to resolve these problems, it has been suggested that as shown in FIG. 1, a relief valve 14 having a low relief set pressure (relief-operating at a low pressure) should be provided in a circuit that connects the retraction pressure chamber 11 of the boom cylinder 6 to the boom directional control valve 12. The boom directional control valve 12 will then be switched from its neutral position a to its retraction position b to supply a pressurized discharge fluid of a hydraulic pump 15 into the retraction pressure chamber 11 of the boom cylinder 6. During an excavating operation, if the excavating load is increased whereby the pressure within the first circuit 13 reaches the above mentioned relief set pressure, the pressure fluid in the retraction pressure chamber 11 of the boom cylinder 6 will be allowed to flow out through the relief valve 14 into a reservoir 16. As a result, a situation may be eliminated in which the boom 5 will no longer be swung downwards, and the boom 5, the arm 7 and the bucket 9 will altogether cease moving.
If such a measure is undertaken, however, the pressure within the retraction pressure chamber 11 of the boom cylinder 6 can only be elevated up to the relief set pressure of the relief valve 14. Then, the force by which the boom 5 is swung downwards will be reduced.
For this reason, problems arise such as the inability to lift up the vehicle body 4 with one end portion 1a of the traveling body 1 serving as a supporting point by swinging the boom 5 downwards to press the bucket 9 against the ground surface and the inability to obtain a sufficient force of excavation if a strong force of excavation is required. Thus, it has been recognized that there is an undesirable limitation in establishing the low pressure for the relief set pressure of the relief valve 14; hence there is an undesirable limitation in enhancing the operating efficiency of excavation.
In an attempt to overcome these problems, a hydraulic circuit has been proposed, as disclosed in Japanese Utility Model Unexamined Publication No. Hei 6-1465, in which the relief set pressure of the above mentioned relief valve 14 should be switched between a high pressure and a low pressure.
If such a hydraulic circuit is adopted, the relief set pressure of the relief valve 14 can be set at a low pressure during an excavating operation to enhance the operating efficiency of excavation. And, if the relief set pressure of the relief valve 14 is set at a high pressure, the vehicle body 4 can be lifted up and a strong force of excavation can be obtained.
However, the relief valve in the above mentioned hydraulic circuit is provided to elevate the relief set pressure to a high pressure with a pressurized discharge fluid from an auxiliary pump that is driven by the engine. Thus, if the engine ceases driving, the auxiliary hydraulic pump will also cease discharging the pressure fluid so that the relief set pressure of the relief valve may become a low pressure.
For this reason, if, for example, the relief set pressure is set at an elevated pressure to lift up the vehicle body 4 and the engine is halted for any cause in that state, the relief set pressure of the relief valve 14 will become a low pressure and this will cause the pressure within the retraction pressure chamber 11 of the boom cylinder 6 to be reduced to a low pressure. As a result, an extension operation will occur in the boom cylinder 6 due to the weight of the vehicle body and so forth so that the vehicle body 4 may be dropped.
More specifically, if a retraction operation occurs in the retraction pressure chamber 11 of the boom cylinder 6 when a pressure fluid is supplied therein, the boom 5 will be swung downwards with a supporting point 5a at a side of the vehicle body serving as a fulcrum. Then, if the bucket 9 is in contact with the ground surface, the boom 5 will not be able to be swung downwards and will, on the contrary, be swung upwards with a supporting point 5b at a side of the arm serving as a fulcrum so that the vehicle body 4 may be lifted up as shown by the phantom line. In that state, if the relief set pressure of the relief valve 14 is reduced to a low pressure, a force of extension due to the weight of the vehicle body 4 will be exerted on the boom cylinder 6 and, as a result, the pressure fluid within the retraction pressure chamber 11 will be allowed to flow out through the relief valve 14 into a reservoir 16. The boom cylinder 6 will then be extension operated, causing the vehicle body 4 to be dropped.
Thus, due to the possibility that the vehicle body may be dropped when the engine is halted, there has been a serious problem as to safety in the prior art.
Also, if the low set pressure of the relief valve 14 is elevated not to cause a drop of the vehicle body 4, a difference with a high set pressure will be reduced, thus giving rise to the problem that an enhancement of the operating efficiency of an excavating operating that is originally sought may not be realized.
With the above mentioned problems taken into account, it is, accordingly, an object of the present invention to provide a hydraulic circuit for a boom cylinder in a hydraulic shovel, which provides a sufficient safety and in which in a state where a vehicle body has been lifted up, there may be no false drop of the vehicle body when the engine is halted.

Hydraulic circuit for a boom cylinder in a hydraulic shovel


A sintered nuclear fuel body includes (U, Pu)O.sub.2 mixed crystals having a mean particle size in a range from 7.5 .mu.m to 50 .mu.m. This sintered nuclear fuel body has a high retention capacity for fission gas in a power reactor. In order to produce the sintered nuclear fuel body by sintering a body in a hydrogen-containing sintering atmosphere, a powered substance selected from the group consisting of aluminum oxide, titanium oxide, niobium oxide, chromium oxide, aluminum stearate, aluminum distearate and aluminum tristearate is added to the starting powder for the body. As an alternative or in addition, the body made from the starting powder is sintered during a holding period of 10 minutes to 8 hours at a sintering temperature of 1400.degree. C. to 1800.degree. C. in a hydrogen-containing sintering atmosphere, initially with an oxygen partial pressure of 10.sup.-10 to 10.sup.-20 bar and then from 10.sup.-8 to 10.sup.-10 and then cooled in a hydrogen-containing atmosphere having an oxygen partial pressure of 10.sup.-10 to 10.sup.-20 bar.

Field of the Invention
The invention relates to a sintered nuclear fuel body or compact that contains (U, Pu)O.sub.2 mixed crystals.
The invention also relates to a method for producing a sintered nuclear fuel body that contains (U, Pu)O.sub.2 mixed crystals from powdered starting materials of uranium dioxide UO.sub.2+X and plutonium dioxide PuO.sub.2, which are ground, compressed into bodies, and sintered as bodies in a hydrogen-containing sintering atmosphere. The variable X is in a range from 0 to 0.3.
One such sintered nuclear fuel body and one such method are known from German Published, Non-Prosecuted Patent Application DE 38 02 048 A1. In that known method, the powdered starting materials of uranium dioxide and plutonium dioxide are ground together with an additive, which is at least one powdered substance selected from the group consisting of ammonium uranyl carbonate, ammonium diuranate, ammonium bicarbonate, zinc stearate, zinc behenate, starch, cellulose, oxalic acid diamide and stearic acid diamide. The powder mixture can be ground and then compressed into tablet-like bodies, which are sintered in a sintering atmosphere of hydrogen.
The sintered nuclear fuel bodies that are obtained are dimensionally stable and also only have slight open porosity, so that gaseous nuclear fission products in a nuclear reactor can be trapped in the sintered nuclear fuel bodies.

Sintered nuclear fuel body and method for producing a sintered nuclear fuel body


A semiconductor memory device includes an operation control block suitable for controlling an entrance/escape to/from a test public mode and a test application mode in response to a first preset command and an address signal that is inputted through an address pad, a test normal input block suitable for receiving the address signal as a test operation signal in response to the first preset command in the test application mode, a test public input block suitable for receiving a data signal, which is inputted through a data pad as the test operation signal in response to a second preset command in the test public mode, and an internal circuit suitable for performing a preset test operation in response to the test operation signal in the test application mode.

1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device that supports a test mode accessible from the exterior.
2. Description of the Related Art
A synchronous semiconductor memory device uses a mode register and a mode register set (MRS). The mode register programs and stores data for controlling various operation modes of the synchronous semiconductor memory device.
The operation modes or characteristics of a conventional semiconductor memory device are decided by an inputted control signal. However, in the synchronous semiconductor memory device, a central processing unit (CPU) presets an operation mode of the synchronous semiconductor memory device to be used later, that is, CAS latency (column address strobe latency) or a burst length, and accesses the synchronous semiconductor memory device. Such an operation mode is set and stored in the mode register, and a set of a series of mode registers is called a mode register set (MRS). Accordingly, a series of codes indicating the modes of a semiconductor memory device are set in the mode register set, wherein such codes are called MRS (mode register set) codes.
Conventionally, the MRS codes are generated by a combination of addresses. The MRS codes are generated by the combination of addresses and respective operation modes of a semiconductor memory device are decided corresponding to the generated MRS codes. Such MRS codes are standardized by JEDEC. MRS codes for testing a semiconductor memory device designed in a semiconductor design process are necessary, which are called test MRS codes.
FIG. 1 is a table of MRS codes of a semiconductor memory device according to the conventional art.
Referring to FIG. 1, table values of the MRS codes are decided by a combination of signals applied through address pads BA2 to BA0 and A15 to A0.
In detail, among the signals inputted through the address pads BA2 to BA0 and A15 to A0, a signal TM of the address pad A7 is used in order to control entrance to a test mode of the semiconductor memory device. That is, the semiconductor memory device performs a normal operation when the value of the signal TM is '0', and performs a test mode operation when the value of the signal TM is '1'.
When the value of the signal TM is '1' and the semiconductor memory device performs the test mode operation, methods for inputting test operation codes used in a test mode to the semiconductor memory device differ between fabricating companies of the semiconductor memory device. That is, since detailed internal operations of the semiconductor memory device differ between the fabricating companies and methods for testing the operations are very complicated, the test methods performed on the semiconductor memory device are not accessible from the exterior of the semiconductor memory device.
As many functions are added to the semiconductor memory device, including timing adjustments and the like, to obtain high speed operation, it is highly necessary for an external semiconductor controller or user to perform specific common test functions of the semiconductor memory device. However, since semiconductor companies are concerned with security and compete to guarantee product operation, test mode operation methods necessary for development and testing are kept in secret and not generally open to the public. It is highly probable that defining a specific function or timing through a separate specification (SPEC.), by using MRS codes for the release, faces limitations when considering the growing types of necessary test modes. [Revised the paragraph to improve clarity. Please verify. Thank you.]
In this regard, it is necessary to provide a method for allowing an external semiconductor controller or user to access some internal test mode operations that may be open in the range of the specification (SPEC.) of a semiconductor memory device.

Semiconductor memory device and method for operating the same


A system predicts digital subscriber line (DSL) performance on an existing telephone loop. The system obtains a topological description of the existing telephone loop (410) and identifies a loop equivalent to the existing telephone loop from the topological description of the existing telephone loop (440). The system then determines DSL performance for the equivalent loop (450). From the DSL performance for the equivalent loop, the system predicts DSL performance for the existing telephone loop (460).

A. Field of the Invention
The present invention relates generally to digital subscriber line (DSL) systems and, more particularly, to systems and methods that predict performance of DSL service on arbitrary telephone loops.
B. Description of Related Art
Digital subscriber line (DSL) technologies use sophisticated modulation schemes to pack data onto existing copper telephone lines (i.e., plain old telephone service (POTS) lines). DSL technologies are sometimes referred to as last-mile technologies because they are used only for connections from a central office to a home or office, not between central offices.
It is envisioned that DSL service will be provided over a majority of the existing copper telephone lines or loops. One of the more difficult aspects of providing DSL service is predicting which customer loops cannot support the DSL service, which customer loops can support the service, and predicting what level of service (e.g., data rates) these latter loops can support. Conventional systems roughly estimate the level of service supportable by these loops by performing metallic line tests to estimate the lengths of the loops. These tests, however, cannot determine the wire gauges of the loops or the presence of bridged taps. Both of these factors can have a major impact on DSL performance, leading to possibly inaccurate estimations by the conventional systems.
As a result, a need exists for a method that more accurately predicts the level of DSL performance supportable by existing copper loops.

Systems and methods for performing DSL loop qualification


A coordinate input device includes a coordinate input element. The coordinate input element includes a transparent coordinate detector and a controller having a control circuit which drives and controls the coordinate detector and which corrects electrostatic capacitance noise disturbing the coordinate detector. The coordinate input device also includes a liquid crystal display device provided on the back side of the coordinate input element, a casing for holding the coordinate input element and the liquid crystal display device, and an L-shaped and a reverse L-shaped push button switches provided on the upper surface of the casing.

1. Field of the Invention
The present invention relates to electrostatic-capacitance-type coordinate input devices, which are operated with a user's finger and so on, and in which the coordinate position of a touched portion is detected based on a current variation according to a variation in electrostatic capacitance and the coordinate position of the touched portion is input.
2. Description of the Related Art
In recent years, notebook computers have been widely used for space-saving in offices and homes. In this type of computer, a pad-type coordinate input device operated by dragging a finger on a touch board has been widely adopted and put into practical use as a coordinate input device for moving a cursor displayed on a display.
FIG. 7 is a perspective view showing the configuration of a critical portion of a coordinate input device 100.
The coordinate input device 100 shown in FIG. 7 includes a planar touch board 101 provided at the top, a film substrate 106 comprising a dielectric thin film such as a resin film provided on the lower surface of the touch board 101, and a circuit board 107 provided on the lower surface of the film substrate 106. The film substrate 106 is a dielectric substrate. The upper surface of the film substrate 106 is provided with a plurality of X-electrodes 106a at predetermined intervals and the rear surface thereof is provided with a plurality of Y-electrodes 106 at predetermined intervals. The planar touch board 101 is bonded to the upper surface of the film substrate 106 with an adhesive or the like. Also, the film substrate 106 and the circuit board 107 are bonded via a dielectric film (not shown).
In the above-described film substrate 106, the Y-electrodes 106b extend in the direction orthogonal to the X-electrodes 106a and the electrodes 106a and 106b are arranged in a matrix in plan view, with the film substrate 106 therebetween. Also, the X-electrodes 106a and the Y-electrodes 106b are printed on the upper surface and the lower surface of the film substrate 106 respectively, with a silver paste or the like. Further, through-holes 108 are formed along one edge of the circuit board 107 and along another edge adjacent to that edge. Also, land portions electrically connected to the electrodes 106a and 106b are formed on the rear surface of the film substrate 106 at positions corresponding to first ends of the X-electrodes 106a and first ends of the Y-electrodes 106b. The land portions and the through-holes 108 of the circuit board 107 are electrically connected. That is, the X-electrodes 106a and the Y-electrodes 106b are electrically connected to a wiring pattern formed on the upper surface of the circuit board 107 via the through-holes 108.
Further, a ground layer 109 comprising a copper foil or the like is provided at the center of the upper surface of the circuit board 107. The ground layer 109 helps to prevent a signal generated in the lower part of the circuit board 107 from disturbing the X-electrodes 106a and the Y-electrodes 106b. Also, a control circuit chip 110 is soldered to the wiring pattern on the rear surface of the circuit board 107. By scanning the touch board 101 with a finger so that the finger is in soft contact with the touch board 101, a part of the electric flux lines formed between the X-electrodes 106a and the Y-electrodes 106b of the film substrate 106 is absorbed by the finger, and thus the electric flux lines to the Y-electrodes 106b are reduced so that electrostatic capacitance varies. The control circuit chip 110 converts the variation in the electrostatic capacitance to a variation in an electrical signal and the variation in the electrical signal is converted to a desired coordinate position, whereby the position of the finger on the touch board 101 can be detected.
The coordinate input device 100 having the above described configuration is often mounted in front of a keyboard in a notebook personal computer and can be operated without the user moving his/her hands much away from the home position of the keyboard. However, in many pad-type coordinate input devices, a flat touch board is exposed at the surface of the computer. Thus, a person who is not accustomed to operate a computer is often puzzled by the operation method and this type of coordinate input device does not have excellent ease of use.
Also, when the area of the touch board 101 is greatly reduced, the operability and ease of use of the above-described coordinate input device are reduced. Thus, it is inevitable that the touch board 101 occupies a predetermined space in the operating portion of a notebook personal computer. Therefore, it is difficult to further miniaturize the touch board in a notebook personal computer including the coordinate input device 100. Accordingly, the inventors of the present invention have considered adding another function to the portion occupied by the coordinate input device 100 and have investigated improving the ease of use of the coordinate input device and electronic equipment including the same, and as a result, the present invention has completed.


A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown state or an unblown state, a reference voltage output circuit unit that outputs a reference voltage that differs in accordance with a normal mode or a test mode, and a voltage comparison circuit unit that compares a read voltage corresponding to the resistance of the first fuse element with the reference voltage output from the reference voltage output circuit unit.

FIG. 2 illustrates an example of a configuration of a fuse element reading circuit. FIG. 3 illustrates the resistances and frequencies of electric fuse elements. An electric fuse element 211 has a resistance that differs in accordance with whether the electric fuse element 211 is in a blown state or an unblown state. The electric fuse element 211 in the unblown state has a small resistance, whereas the electric fuse element 211 in the blown state has a large resistance. In FIG. 3, a frequency distribution 301 represents the frequency of the electric fuse element 211 in the unblown state, and a frequency distribution 302 represents the frequency of the electric fuse element 211 in the blown state.
At the time of reading, a control node SEN is at a high level, and a read voltage output circuit unit 201 outputs a read voltage V1 corresponding to the resistance of the electric fuse element 211. The read voltage V1 is low when the electric fuse element 211 is in the unblown state, whereas the read voltage V1 is high when the electric fuse element 211 is in the blown state. A reference voltage output circuit unit 204 outputs a reference voltage V3 by resistance division.
A selection circuit unit 202 selects one of read voltages V1 of a plurality of read voltage output circuit units 201, and outputs the selected read voltage V1 as a read voltage V2. A voltage comparison circuit unit 203 compares the read voltage V2 with the reference voltage V3, and outputs a voltage V4, which represents a comparison result. A latch circuit unit 205 latches the voltage V4, and outputs a voltage OUT.
The electric fuse element 211 is capable of storing data in accordance with whether the electric fuse element 211 is in the blown state or the unblown state. If the resistance of the electric fuse element 211 is smaller than a threshold resistance 303 (see FIG. 3), it is determined that the electric fuse element 211 is in the unblown state. Meanwhile, if the resistance of the electric fuse element 211 is greater than the threshold resistance 303, it is determined that the electric fuse element 211 is in the blown state. The read voltage V2 is a voltage corresponding to the resistance of the electric fuse element 211. The reference voltage V3 is a voltage corresponding to the threshold resistance 303. If the read voltage V2 is lower than the reference voltage V3, the voltage comparison circuit unit 203 determines that the electric fuse element 211 is in the unblown state. Meanwhile, if the read voltage V2 is higher than the reference voltage V3, the voltage comparison circuit unit 203 determines that the electric fuse element 211 is in the blown state.
As described above, it is necessary for the electric fuse element 211 in the unblown state to have a resistance smaller than the threshold resistance 303, and it is necessary for the electric fuse element 211 in the blown state to have a resistance greater than the threshold resistance 303. To this end, a test for the resistance of the electric fuse element 211 is carried out. When the electric fuse element 211 is in the unblown state, if the read voltage V2 is lower than the reference voltage V3, the test is successful. When the electric fuse element 211 is in the blown state, if the read voltage V2 is higher than the reference voltage V3, the test is successful.
However, as depicted in FIG. 3, a variation in the resistance of the electric fuse element 211 may occur for various reasons. The electric fuse element 211 having a resistance within a region 304 or 305 passes the test. However, since the regions 304 and 305 are in the vicinity of the threshold resistance 303, erroneous determination may be made in the case of reading data of the electric fuse element 211. Namely, a sufficient reading margin is not ensured.
In addition, the semiconductor integrated circuit described below is described in Japanese Unexamined Patent Application Publication No. 2006-310457, the entirety of which is hereby incorporated by reference. The semiconductor integrated circuit includes a first fuse element, which stores data in accordance with a difference in resistance, depending on the presence or absence of electric writing, and from which data is read in accordance with the resistance when a voltage is applied across the ends of the first fuse element, and a second fuse element, which has a characteristic equivalent to that of the first fuse element and which is used for read trim control for determining a read condition relative to the first fuse element. The semiconductor integrated circuit further includes a trim value automatic control circuit unit, which reads data of the second fuse element by applying a constant voltage across the ends of the second fuse element before reading the data of the first fuse element, and which outputs a trim value specifying a desired read condition relative to the first fuse element in accordance with a read result, and a fuse data read circuit unit, which applies a constant voltage across the ends of the first fuse element at the time of reading the data of the first fuse element, and which reads the data in accordance with the trim value supplied from the read trim value automatic control circuit unit.
In addition, the resistance-change-type fuse circuit described below is described in Japanese Unexamined Patent Application Publication No. 2007-299926, the entirety of which is hereby incorporated by reference. The resistance-change-type fuse circuit includes a plurality of polysilicon fuses, which are made of polysilicon and which cause irreversible changes in resistance by causing a current to flow, a plurality of programming transistors, which are arranged in association with the plurality of fuses and which switch between causing and not causing currents to flow through the corresponding fuses, so as to cause changes in the resistance, and a dummy fuse group that includes a plurality of dummy fuses that have the same electric characteristic as that of the plurality of polysilicon fuses, and that have a resistance that is 1/n times the resistance of the plurality of polysilicon fuses. The resistance-change-type fuse circuit further includes a dummy transistor circuit unit that includes at least one dummy transistor that has a conductance that is 1/n times the conductance of the plurality of programming transistors, and that has a gate and drain connected to each other, and a current mirror circuit unit that includes the programming transistor and the dummy transistor, and that causes a current that is n times the current flowing in the dummy fuse group to flow in the plurality of polysilicon fuses.


A method and system for data masking a series of interrelated data records is disclosed. A lockable translation matrix repository resource is provided to contain both masked data as well as appropriate key information that provides links between respective copies of respective interlinked databases and maintains the data integrity of masking data inserted therein. Records are masked on a column by column or table by table basis. Records for which masking data is already in the repository are masked by making use of such data, while remaining records are segregated, masked and the masking data updated to the repository. Preferably a backup copy of the masked data records is stored in the repository to permit de-masking of the data records at a later stage. Pivot tables are applied where keys do not match exactly but still exhibit a one-to-one relationship.

In today's technology-driven economy, the need for data privacy and information security has never been greater. As organizations increasingly collect, store and distribute sensitive data, so grows the requirement to protect such information from unauthorized uses. In 2006, it was estimated that 54 percent of information in databases is considered confidential, including employee, customer, financial and supplier information. Approximately one-third of senior-level corporate and technology leaders do not trust their companies ability to protect sensitive data. Information governance has become a universal business mandate, thus placing considerable pressure on organizations worldwide to ensure the protection of sensitive data.
The focus of many organizations has been to secure production data stored and used in IT systems across networks; however organizations are now beginning to realize the importance of protecting data while stored and used outside production environments. Once sensitive data is exposed to individuals in non-production environments, the potential for internal data theft greatly increases. While organizations have been focused primarily on protecting sensitive data from external theft, researchers currently indicate that 70 to 80 percent of all security incidents come from insiders. It has been reported that 35 percent of IT professionals have abused their computer security and information access privileges in an attempt to access proprietary data.
Researchers currently estimate that 45 percent of organizations use live production data in non-production environments for such activities as software development, application testing, quality assurance, training, data mining/research, offshoring and outsourcing. The use of sensitive data for such non-production activities is often strictly prohibited by privacy legislation as well as by organizations' internal privacy policies.
Data masking is a process whereby the information in a database is masked or de-identified to ensure the protection of sensitive information used in non-production environments, while enabling the creation of realistic data without risk of unnecessarily exposing sensitive information. The data masking process enforces 'need to know access', minimizing the risks associated with using real production data in non-production environments. It is useful in situations where data is shared with third parties, either on-site, offsite, or offshore. Data masking has emerged as a new product class, and is now used throughout industry in addressing worldwide data privacy problems.
Large organizations typically have a number of database systems that integrate with each other. For instance, a Human Resources system and a Financials system might share certain data to support their respective business functions.
Accordingly, it is desirable to provide a novel and improved method and system for data masking that maintains data integrity across a plurality of inter-related databases.
It is further desirable to provide a novel and improved method and system for data masking that permits reversal of data masking for use in conjunction with unmasked databases.

Method and system for masking data in a consistent manner across multiple data sources


A vehicle LED tail-light bulb (10) that is designed to replace an incandescent light bulb, to be inserted into a conventional right and left vehicle light socket and to function in combination with a vehicle battery that powers the bulb (10) and a flasher unit that is activated by a vehicle turn-signal arm. The LED tail-light bulb incorporates an electronics circuit consisting of an input circuit (12), an intermediate circuit (14) and an output circuit (16). The electronics circuit is designed to operate the left and right turn lights and in some cases an emergency light and to produce a current flow of sufficient magnitude to energize the vehicle flasher unit. The energized flasher unit then causes the bulb (10) to blink when the vehicle turn-signal arm is placed in either a right turn or a left turn position.

High-intensity LED lights in vehicles are in common use because LED lights are reliable, cost-effective and they produce a greater light output using less power than conventional single or dual-filament incandescent lights. Additionally, LED lights require less space and have a longer useful life when compared to incandescent lights.
The prior art LED light bulbs operate in combination with a flasher unit which causes the lights to turn ON and OFF whenever the right or left turn signal arm or the emergency flasher button is depressed. The flasher unit is constructed using a set of contacts similar to a conventional relay with one exception. One of the relay support arms is made of a bimetallic material similar to the contacts in a home thermostat. The two metals that comprise the bimetallic material have different temperature coefficient characteristics. Thus, when the contacts are heated or cooled they expand or contract at different rates.
The flasher unit installed in a vehicle becomes operational when the current for the filament type lights flows through a heater coil mounted against the contacts in the flasher unit. When the turn signal is turned ON the heater coil heats the contacts causing one of the metal contacts to heat, which in turn causes it to bend. This action either OPENS or CLOSES the relay contacts of the flasher unit. Once the contacts OPEN current stops flowing to the lights and they turn OFF. The bimetallic metal cools and it bends back to its original shape closing the contacts in the flasher unit and the cycle repeats. This action makes the turn signal lights and the emergency light blink ON and OFF.
The flasher unit is designed so that the current from two or more lights is necessary to make it work. One light does not draw enough current to heat the metal enough to make it bend. The same problem arises when you try to substitute a low power LED light in place of a conventional filament light. They do not draw enough current to activate the flasher unit.
The instant invention eliminates this problem by allowing for the direct substitution of an LED light bulb for a conventional one or two filament light, while still enabling the flasher unit to function normally. This is accomplished by emulating the current drawn by a conventional filament light. To do this a circuit is placed in parallel across the LED light bulb which then causes the light bulb to draw additional current making the flasher unit function normally.
A search of prior art patents and industry literature did not disclose any products that read on the claims of the instant invention.


A display device includes a first substrate and a second substrate opposed to each other and a rectangular frame-shaped sealing material configured to bond the first and second substrates together. The first substrate has an interconnect layer overlapping a corner of the sealing material, a layered insulating film including an inorganic insulating film and an organic insulating film placed one upon the other on the interconnect layer, and a transparent conductive layer formed on the layered insulating film to be connected to the interconnect layer via a contact hole formed through the layered insulating film. The second substrate has an electrode layer electrically connected to the transparent conductive layer. The inorganic insulating film has an exposed portion exposed from the organic insulating film in the corner of the sealing material. The exposed portion is entirely exposed from the transparent conductive layer. In the exposed portion, a through hole is formed through the interconnect layer, and the inorganic insulating film covers the through hole.

Conventionally, taking advantage of their features of being thin and consuming low power, liquid crystal display devices have been widely used as displays for office automation (OA) equipment such as personal computers and portable information equipment such as cellular phones and personal digital assistants (PDAs).
A liquid crystal display device includes a thin film transistor (TFT) substrate, a counter substrate opposed to the TFT substrate, and a liquid crystal layer sealed with a rectangular frame-shaped sealing material between the TFT substrate and the counter substrate.
In the counter substrate, a common electrode layer and the like are formed on the side thereof facing the TFT substrate. In the TFT substrate, a plurality of interconnects including a plurality of source lines, a plurality of gate lines, a common interconnect for supplying a signal to the common electrode layer, and the like are formed. The TFT substrate often has a layered insulating film including an inorganic insulating film and an organic insulating film stacked one upon the other to cover the plurality of interconnects described above.
Since the TFT substrate and the counter substrate are fixed to each other with a sealing material, it is desirable to provide high adherence of the sealing material to the TFT substrate and the counter substrate.
For example, for enhancing the adherence of the sealing material to the TFT substrate, Patent Document 1 discloses a method in which an organic insulating film is partly removed to allow a sealing material to adhere directly to an inorganic insulating film that is comparatively high in adherence to the sealing material.


A fiberoptic delay line architecture for generating multiple replicas of an input RF signal with variable replica-to-replica time resolution is provided in which the required hardware is kept to a minimum. A series of cascaded binary fiberoptic segment delay lines is used in which each cascaded binary fiberoptic segment delay line has an equal and defined number of segments but variable minimum time resolution. The minimum time resolution of each cascaded binary fiberoptic segment delay line increases by a multiple of two compared to the prior cascaded binary fiberoptic segment delay line. In this manner, the required number of segments and switches increases in a log.sub.2 .times.log.sub.2 relationship as the number of desired replicas and possible replica-to-replica delay values increases.

1. Field Of The Invention
This invention relates to process signal generators, and, more particularly, to process signal generators for use with radar test devices to produce a substantially delayed replicas of a transmitted radar signal.
2. Description Of Related Art
In various applications, one often faces the need to generate multiple delayed replicas of a radar signal and transmit it back. It is well known that fiberoptic delay lines because of their inherent capability to support very wide bandwidth and large time delays are a good candidate for generating a single delayed version of an input signal. Such an arrangement is shown in U.S. Pat. No. 4,128,759 wherein a plurality of fiberoptic light paths, each having a determinably variant optical propagation delay, are used to generate multiple delayed replicas of a signal. Such a signal generator can be useful to produce delayed replicas of a transmitted radar signal to jam a radar detecting station by overwhelming the station with a plurality of signals.
An example of a prior art fiberoptic delay line is shown in FIG. 1. Therein, prior art fiberoptic delay line 10 receives an input signal 12 which drives a laser diode 14. The optical output of laser diode 14 drives a 1:N fiberoptic splitter 16. The output of fiberoptic splitter 16 is fed into N fiber segments 20 which are of linearly increasing length. The increment of the increasing length corresponds to the minimum delay resolution T.sub.1 . The transmission of each fiber 20 is controlled by an optical switch 18. The outputs of switches 18 drive an N:1 fiberoptic combiner 22 which sums the optical signals and drives a common detector 24. The output of detector 24 passes through buffer 26 before being transmitted as output signal 28.
In prior art fiberoptic delay line 10, when all N optical switches 18 are "on", the output of detector 24 consists of N signal replicas spaced T.sub.1 time apart. In order to create L replicas of a signal with up to R possible replica-to-replica delay values, a total of N=LR fiber segments 20 and switches 18 are needed. Thus, in order to create 64 signal replicas with up to 128 possible replica-to-replica delay values, a total of 8,192 fiber segments 20 and switches 18 are needed. From a hardware point of view, prior art fiberoptic delay line 10 is very inefficient and impractical.

Fiberoptic delay line for generating replicas of an RF signal with variable replica-to replica time resolution


Reinforcing fibers with small particles having a longest average dimension of approximately 0.01 nanometer to approximately 30 micrometers physically and/or chemically bonded directly to their surfaces to form protuberances thereon and a method and system for making these modified fibers are disclosed. The particles directly bonded to the surfaces of the fibers, serve to enhance physical properties of composite articles which incorporate such fibers as reinforcement.

It has long been known to make reinforcing fibers of glass, ceramics, carbon and certain polymers such as aromatic polyamides, etc. It has also long been known to coat the fibers with a sizing composition that protects the surfaces of the fibers against abrasive damage and enhances the bonding of a polymer or other matrix to the surface of the reinforcing fibers. The bond strength between the matrix and the surface of the fibers is extremely important for the physical properties of the composite materials since the strength of the reinforcing fibers is almost always significantly greater than the strength of the matrix material. Once the bond between the matrix and the surface of the reinforcing fiber is broken, the matrix can slip away from the fiber thereby causing strain or failure of the composite product. Since the bonding of the matrix to the surface of the fiber depends largely on the area of the fiber surface, increasing the surface area will also enhance the bond strength between the matrix and the reinforcing fiber. Reducing the diameter of the reinforcing fibers increases its surface area, but also increases costs and makes the manufacturing and processing more difficult. To further enhance bonding to a surface it is known to nano-roughen the surface of a substrate using a laser as disclosed in U.S. Pat. No. 6,350,506. To increase the surface area of reinforcing fibers it has also been proposed to etch or make nano-sized depressions in the surface of the fibers as disclosed in COMPOSITES SCI. TECH., 2006, Vol. 66, p. 509.
Chopped strand reinforced products, such as chopped strand for thermoset or thermoplastic resins, usually comprises glass fibers and can also comprise carbon, ceramic or polymer fibers, alone or in combination. These products are typically made from pellets or other forms, of one or a mixture of polymers having the fibers dispersed therein. These pellets, etc., are typically made by feeding bundles of fibers containing up to several thousand fibers, typically having a length of less than approximately 3 mm to about 7 mm or even up to approximately 250 mm, into a compounding or extruding machine along with one or more polymers and heating with high shear mixing to plasticize the polymer(s) and disperse the fibers therein. The current technology for long fibers includes feeding of the strands of fibers into molten polymer or other material matrix material, followed by cutting and compression molding.
Fiber products used to make FRP typically have a sizing that normally contains a coupling agent such as one or more silanes and one or more film formers or binders, and can contain other ingredients such as lubricants, surfactants, dispersants, fillers, stabilizers, antioxidants, biocides, and others that are needed or preferred for particular applications. The sizing is usually applied to the fibers as an aqueous slurry, solution, or emulsion, but liquids other than water may also be used. The amount and type of bonding agent(s) used in the sizing on the fibers results in stronger fiber-to-fiber bonding in the bundles. This aids the fiber handling characteristics, but may not be good for later processing and may affect the final product characteristics. To achieve good feeding characteristics in the fiber bundles, important to the final users, a substantial amount of film former or binding agent commonly is used in the sizing composition that is coated on each fiber to prevent filamentation during storage, shipment and handling. Filamentation, the breaking down of the fiber bundles resulting in excessive small fiber bundles and individual fibers in the product, causes bridging in the feeding bin cones, and other fiber handling equipment resulting in costly scrap and downtime.
Once in the compounder and in contact with the polymer(s), it is desirable that the bundles separate into individual fibers and that the fibers disperse thoroughly in the polymer(s). The time and amount of mixing action to accomplish this has a practical limit, and because of the strength of the bonds between the fibers, high-shear mixing commonly is required to achieve an acceptable degree of fiber dispersion and wet out (coating of the fibers with the polymer or polymer mixture). This shear damages the fiber surface and breaks the fibers into shorter segments, and commonly still falls short of optimum fiber dispersion. As a result, the produced reinforced plastic parts commonly do not reach their full potential with respect to surface characteristics and physical properties. Most product and process development work in this area is aimed at addressing these problems and opportunities.
Potential cost reduction opportunities exist in the chopped fiber bundle manufacturing processes by preparation of fibers having larger diameters. The fiber bundles are made by pulling fibers from a plurality of orifices in a fiberizing bushing, usually from tips, nozzles, on tip plates of a plurality of fiberizing bushings, while the material is in a molten or plastic state, cooling the fibers, coating the fibers with water or other cooling liquid medium such as glycols, and then with the sizing mixture usually containing one or more binding agents, gathering the fibers into strands, chopping the strands into segments of desired lengths, drying the wet chopped strands in an oven, and sorting the resultant dry bundles to remove undesirable small bundles and individual fibers, lumps and fuzz clumps. Typical processes are described in U.S. Pat. No. 3,996,032. These types of processes produce chopped strand bundles having a wide range of diameters and containing a wide range of numbers of filaments, e.g. from just a few fibers to 4000 or more fibers per segment. Many dry chopped strand products have been produced with the above-described processes and are used in making a wide variety of fiber reinforced products, but as described above, to achieve substantial improvement in bonding strength to the matrix, something different than the heretofore developed and proposed solutions is needed.
It has been documented that long fibers, with lengths typically more than 12 mm, provide reinforced products displaying improved physical properties, as reported by Thomason and co-workers (Composites A 1997, 28, 277 and Composites A 2002, 33, 1641). However, processing of long chopped glass fibers using standard equipment is not feasible due to the damage that the fibers would sustain under the high shear mixing and difficulties in dispersing of these long fiber bundles. In contrast, short fibers are easy to process and disperse, but they do not provide optimum properties within the composite materials.
It has been proposed to prepare an epoxy thermoset resin, which incorporates a woven continuous filament fabric, in which a sizing package including colloidal silica is applied to the woven fabric prior to the incorporation followed by vacuum assisted resin transfer molding. See, for instance, Army Research Laboratory Report No. ARL-TR-3241 (July 2004), and R. E. Jensen, S. H. McKnight, Composites Sci. Tech., Vol. 66, Pages 509 to 521 (2006). However, a long felt need still exists for overcoming current limitations of the sized reinforcing fibers to achieve better physical properties in the fiber reinforced polymer composite products.

Method and system for forming reinforcing fibers and reinforcing fibers having particulate protuberances directly attached to the surfaces