A method is provided for a dynamic optimization of network resource allocation on the part of a network service provider. In particular, the method of the invention provides an analytical framework for a determination by network service providers of an optimal resource allocation among links in a service provider's own network and links obtained from other network service providers. The analytical framework of the invention also incorporates, as a parameter, the provision of link capacity to other network service providers in the determination of an optimal resource allocation. In a preferred embodiment of the invention, such an optimal resource allocation is determined in respect to revenue maximization for the network service provider.

Modem communication networks are typically comprised of a group of switches, which are referred to as nodes, and a plurality of transmission links that interconnect the nodes. The nodes serve both to provide user access to the network and to provide means for routing data transmitted across the network. The transmission links that interconnect these nodes carry the communication signals, and may comprise one or more different types of communications media such as wire, cable, radio, satellite or fiber optic communications links.
For a large geographical area, such as the contiguous United States, the total communication network infrastructure is usually an aggregate of a number of communication networks installed by individual network service providers that are interconnected at various node points. In many cases, a given network service provider will find it necessary (in order to meet a user requirement) to establish a connection between a node on its network and one or more nodes on a network of another network service provider. While interconnection arrangements between network service providers to facilitate such inter-network connections are known, they are generally based on long-term contractual arrangements and seldom result in an optimal allocation of network resources among the interconnecting network service providers.

Decision support mechanisms for bandwidth commerce in communication networks


Phase unwrapping is applied to velocity data to remove aliasing artifacts. Phase unwrapping is applied on multidimensional regions of velocity data. The unwrapped velocity image is displayed. The displayed image may have high sensitivity to slow motion but may also avoid aliasing of fast motion despite being undersampled.

The present embodiments relate to imaging motion with ultrasound. Fluid motion (flow) or tissue motion is detected with ultrasound. A Doppler or correlation process estimates motion parameters such as velocity, energy or variance from received echoes. If the motion is undersampled, such as due to a long pulse repetition interval (PRI), the estimates are aliased. As the PRI decreases, the maximum depth of motion imaging may be limited. If the motion is oversampled, the sensitivity to low-velocity motion may be lost.
The PRI is increased or decreased to provide the desired sampling rate. For example, a user alters the PRI so that flow with the highest velocity in a region of interest or through a sequence is not undersampled. The user may purposefully set the PRI to undersample the highest velocities for sensitivity to low-velocity flow, resulting in aliasing of higher velocities. As another example, the PRI is adaptively updated by a processor in a medical diagnostic ultrasound imaging system. U.S. Pat. No. 6,478,742 discloses adjusting a pulse repetition frequency for automatic optimization. U.S. Pat. No. 7,288,068 also discloses automatic optimization of the PRI. However, optimizing the PRI to prevent aliasing of high-velocity flow may result in undesired decrease in low-velocity motion sensitivity.

Phase unwrapped velocity display for ultrasound medical imaging


Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.

The present invention relates generally to a semiconductor device and method of forming the same and, more specifically, to CMOS SiGe channel pFET and Si channel nFET devices.
For certain technology node device requirements, it may be necessary to use different channel materials on nFET and pFET devices. The channel materials may be grown using epitaxial growth techniques. In high-k/metal-gate technologies, silicon germanium (SiGe) may be used as the pFET channel material to assist in reaching a desired pFET metal-semiconductor workfunction, while maintaining a traditional silicon channel for the nFET devices. When using epitaxial growth for channel materials on a desired device, a hardmask material such as silicon dioxide (SiO2) or silicon nitride (SiN2) may be used to protect against growth of new channel material on the other devices. The hardmask material is then removed.
Nitride hardmasks are usually not used when growing silicon germanium (SiGe) channel materials. The etchant, such as hot phosphoric acid, used to remove the nitride hardmask also etches the silicon germanium (SiGe) material itself. Patterning of oxide hardmasks with common oxide etchants, such as hydrofluoric acid, also etches the shallow trench isolation (STI) oxide resulting in a different step-height (STI oxide height relative to channel silicon) between nFET and pFET devices. Different size STI divots (amount of STI oxide pulldown immediately next to the active silicon device) may also occur between nFET and pFET devices. Step-height differences and divot differences can create structural topography problems in downstream processing as well as electrical device issues, such as leakage, performance, active width and corner device. A large difference can exist between STI areas and active silicon areas in pFETs versus nFETs. This is all driven by the patterning of the hardmask layer used to protect the nFET device from receiving epitaxial growth. The size of the STI divots near the edge of the active silicon are drastically asymmetrical.

CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess

International Business Machines Corporation


An electro-optical modulator includes a structural substrate, having an insulating layer on top. A waveguide layer, disposed on the insulating layer. A curving resonant MOS device, disposed on the insulating layer and having an optical coupling region with the waveguide layer.

1. Field of the Invention
The present invention relates to an electro-optical modulator. More particularly, the present invention relates to an electro-optical modulator with a curving metal-oxide semiconductor (MOS) device.
2. Description of Related Art
Signal transmission is expected to be changed from previous long-distance transmission, middle-distance transmission, and current module-to-module transmission to chip-to-chip transmission and intra-chip transmission in the future. Conventional cable transmission will be confronted with bottleneck along with the increases in both transmission speed and bandwidth. To meet such requirement, the characteristic of high transmission speed of optical signal has to be integrated with module-to-module, chip-to-chip, or even intra-chip transmission through optical waveguide.
In the future, if the processing speed of an intra-chip communication product in an integrated circuit (IC) is increased up to certain degree, for example, the operation speed of a central processing unit (CPU) reaches 5 GHz, then the internal transmission interface in the IC has to reach certain speed correspondingly. The previous low-cost copper cable design is confronted with bottleneck in the design of high frequency signal transmission. The design and fabrication of such high frequency circuit is very complex and has high cost, thus, copper cable loses its advantage in such circuit design.
Accordingly, electro-optical system chip is one of the major techniques to be developed, wherein an electro-optical modulator of high speed, small volume, and CMOS process compatibility is further required to meet the requirement of intra-chip communication. Usually a semiconductor electro-optical modulator changes the resonant property of a resonator corresponding to an operating wavelength by controlling free carriers of a semiconductor, so as to serve as an optical switch and accordingly to transmit digital signals quickly.
FIG. 1 is a cross-sectional view illustrating the semiconductor structure of a conventional electro-optical modulator. Referring to FIG. 1, a conventional electro-optical modulator is composed of a P-I-N diode. A silicon oxide insulating layer 102 is formed on a silicon substrate 100. A silicon layer 104 having a rib thereon is formed on the insulating layer 102 to serve as a resonator. An N-doped region 106 and a P-doped region 108 are respectively disposed at two sides of the rib, and an operation voltage is supplied to the two by a cathode 112 and an anode 114. Besides, a silicon oxide layer 110 covers the exposed silicon layer 104 between the cathode 112 and the anode 114. The structure illustrated in FIG. 1 adopts a diode as the base thereof, and dopants corresponding to the conductive types of the N-doped region 106 and the P-doped region 108 are respectively doped into the silicon layer 104 to form the diode. The optical resonator is provided by the silicon layer 104 having a rib. The mechanism of the electro-optical modulator described above is achieved by controlling free carriers of the semiconductor. However, the running speed of free carriers is very slow, so that the speed of the electro-optical modulator is lower than 1 GHz. An improved design has been provided in U.S. Pat. No. 6,298,177 to increase operation speed.
FIG. 2 is a cross-sectional view illustrating the semiconductor structure of a conventional annular electro-optical modulator. Referring to FIG. 2, another design of electro-optical modulator is described in pages 325-327 of NATURE Vol. 435 issued on 19, May 2005, wherein a micro-ring resonator is used as the base of the electro-optical modulator. A linear waveguide 120 has an input terminal and an output terminal. An optical signal is input from the input terminal. An annular resonator and the linear waveguide 120 have an optical coupling region which can lead the input optical signal having operating wavelength into the annular resonator. The transverse structure of the annular resonator is a resonant silicon layer having three regions. The resonant silicon layer has an annular rib 122 in the middle to achieve resonant effect along with the resonant mode. An N-doped annular region 126 is disposed at the external rim of the rib 122 to serve as a cathode. A P-doped region 124 is disposed at the internal rim of the rib 122 to serve as an anode.
The operation mechanism illustrated in FIG. 2 is to modulate an optical signal through the resonant effect to a particular wavelength. When a suitable voltage is supplied, the resonant wavelength function changes along with the voltage level, wherein the characteristic resonant wavelength also shifts. Thus, the transmittance of an input light having fixed wavelength in the linear waveguide 120 changes along with the resonant state so that the effect of an optical switch is achieved.
However, the electro-optical modulators described above are both based on the design of Mach-Zehnder interference, thus, the lengths thereof, which are usually in mm level, are very long. Accordingly, the device has very large volume and is very difficult to be applied to intra-chip communication. An electro-optical modulator has to be high-speed, small-volume, and CMOS process compatible to meet the requirements of intra-chip communication. Moreover, such performances as high speed, small volume, and CMOS process compatibility of an electro-optical modulator are the concerning of future development.

Electro-optical modulator with curving resonator

Industrial Technology Research Institute


Embodiments of the present invention are directed to porous resins for solid phase extractions. The resins feature at least one hydrophobic component, at least one hydrophilic component and at least one ion exchange functional group. The resins exhibit superior wetting and ion exchange performance.

Solid phase extraction (SPE) is a chromatographic technique which is widely used, e.g., for preconcentration and cleanup of analytical samples, for purification of various chemicals, and for removal of toxic or valuable substances from aqueous solutions. SPE is usually performed using a column or cartridge containing an appropriate resin. SPE procedures have been developed using sorbents which can interact with analytes by hydrophobic, ion exchange, chelation, sorption, and other mechanisms, to bind and remove the analytes from fluids. Since different SPE applications can require different sorbents, there is a need for sorbents with novel properties which have unique selectivities.

Ion exchange porous resins for solid phase extraction and chromatography


An apparatus for shredding cheese is disclosed which is capable of producing relatively precise square cross-section cheese shreds of a desired length. The apparatus is capable of simultaneously shredding multiple cheese blocks for high capacity cheese shredding. The length of the cheese shreds can be altered as desired, as well as the width and height to produce cheese shreds having a rectangular cross-section. A containment center is used to feed the blocks of cheese toward the cheese shredding apparatus. A series of horizontally mounted sectioning knives are at a front end of the containment center to section the cheese block into predefined lengths, thereby defining the length of each cheese shred. The cheese shredder includes multiple slicing and peeling assemblies mounted over a series of openings in a rotatable disk. Each slicing and peeling assembly includes a number of rakers having outwardly projecting slicing blades to vertically score a sectioned block of cheese. The slicing and peeling assemblies also includes a peeling knife arranged transversely to the slicing blades to peel the sectioned and scored cheese block. The individual cheese shreds are then fed through openings in the rotatable disk and fall into a discharge chute below.

The present invention relates generally to food processing, and more particularly, to a method and apparatus for high capacity cheese shredding.
There are several problems with prior art cheese shredding machines that have been unresolved to date. One particular problem is the type of cut produced. Purchasers of shredded cheese prefer shredded cheese with a square cross-section or a rectangular cross-section with clean, sharp corners and flat surfaces. However, the known prior art high capacity cheese shredders tend to produce shredded cheese with convex surfaces, and at a maximum rate of only 2500 lbs. per hour. A further limitation to these prior art devices is that they can only shred approximately a single 1/2 lb. block of cheese at a time.
Much of the prior art patents in this area are directed toward low capacity food processors typically constructed for home use. Such processors are small, light duty, typically only have a single cutting blade, and are not constructed to withstand high capacity production, nor meet USDA sanitary approval. For example, U.S. Pat. No. 4,198,887 shows a rotary food processing apparatus in which a cutting structure is spot welded to a rotating disk. Such retention methods allow for the accumulation of food materials and do not allow removal for cleaning. Further, such a device would not withstand heavy use because of the orientation and construction of the cutting structure.
Therefore, it would be desirable to have a method and apparatus for high capacity rotary cheese shredding that is capable of producing square cuts, shred multiple cheese blocks simultaneously, and meet USDA sanitary standards.

Apparatus for high capacity rotary cheese shredding


A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material. Each layer of electrically conducting material can include a plurality of spaced apart interconnect lines, each line coupled to one of the bond fingers. The package can include an electrical conductor interconnecting the electrically conducting material on spaced apart layers of the header.

This invention relates to a structure and procedure for providing a reusable package for use in conjunction with testing and burn-in for a digital signal processor (DSP) known good die (KGD).
The typical semiconductor device progresses through a life cycle toward a maturity where environmental screens, such as temperature testing and burn-in are ultimately not required. During the early phases of the device life-cycle, however, burn-in and temperature testing are required to deliver the quality and reliability of product necessary for the customer. In early life, if devices are to be delivered as KGD, these devices must also receive temperature testing and burn-in.
Presently, one of the greatest costs associated with die level KGD test and burn in carriers is the cost of design and redesign of the test carrier. Initially, the KGD test carrier must be designed so that the test contacts are correctly matched to the bond pads of the integrated circuit for electrical connection to the device. The inputs and outputs from the device will proceed through the KGD carrier contacts. The test carrier contacts are connected to metal leads that carry the electrical signals to the edge of the carrier where there are connections that interface with a test socket or burn-in socket. The trace of the metal lead that carries this signal is one of the important design concerns in the electrical performance of the test carrier. The initial design of the test carrier is quite large. The initial design also requires a tooling set to build the patterns associated with the carrier. The cost of a tooling set for a test carrier is also quite large.
If the integrated circuit then goes through a redesign to enhance the performance of the device, the test carrier must be redesigned and the tooling must be rebuilt. The redesign of the integrated circuit is a common occurrence, especially during the early life of the device. Integrated circuits average in early life a redesign about every three months. If the device has problems such as yield during fabrication or electrical performance, then a redesign can occur much more frequently. Each redesign has an associated design and tooling charge associated therewith.
The typical cycle for design and fabrication of a KGD test carrier is about six weeks. The design of the test carrier cannot occur until the final lay out of the integrated circuit is known. This cycle time is therefore added into the delivery schedule of the KGD product.
This limits the growth of the KGD business to supporting mature products that only require test screens, used to make quality and reliability levels equivalent to burned in parts, at probe or hot chuck probe. It is apparent that if a low cost. method of screening the leading edge DSP product could be developed with burn-in and temperature test, then these early life DSP products could also be offered as KGD and thereby provide a significant economic advantage to the manufacturer. It is also apparent that the test carrier metal traces and leads could be easily reconfigured to adapt to the cycles of design and redesign that are associated with the integrated circuit, then significant cost and cycle time could be removed from the time required for fabrication of KGD carriers.
One option for temperature test and burn-in is to use high pin count test carriers. The established temporary test carriers generally operate below 280 pins. A temporary test carrier for leading edge DSP devices has yet to be developed and those contemplated have several technical problems that limit the development and scalability from low to high volume applications. Costs related to building special assembly techniques, unique test and burn-in infrastructure and unique unload to package for KGD are high. The line requires a separate assembly, test and bum-in infrastructure to support the production of KGD using the prior art techniques. Each step of the process is costly because the line has to separate engineering development and eventual product development.
In addition, there is generally a great deal of risk associated with developing a separate line to support carriers for KGD because the device is generally in the early life cycle and the customer requirements are often not firm. Another example is where the die reaches maturity and no longer requires the carrier technology before the required delivery
The present invention solves three of the fundamental problems of KGD productization. First, the invention allows entry into the KGD market during the early phases of the DSP product life-cycle when temperature test and burn-in are still required. Second, the solution is a viable technical solution to burn-in and temperature test of KGD versus the proposed solutions of high pin count test carriers. The failures related to the development of the Die Mate, high cost and poor performance, amplify this need. Third, the costs involved using the present solution are much less and thus the financial risk associated with developing KGD in early life of a DSP is much more attractive.
A solution to providing DSPIKGD is to take the existing ceramic package or its equivalent in other materials, such as, for example, standard plastic packaging, and reroute the signal lines in the header, package or chip carrier base so that a special substrate can be mounted in the header to contact the die by the die bonding pads with the resulting signals from the DSP/KGD package thereby being able to match the header bond fingers existing in the header. The special substrate mounted within the package serves as a testing interface for the die product. The substrate is bonded to the package in much the same manner that a die product is bonded to the header post with aluminum bond wire. The substrate has conductive bumps which connect to the aluminum bond pads on the DSP die or the flip chip bumps. The substrate is also connected to a bonding surface that connects the substrate to the rerouted header. The conductive bumps conduct the signals to and from the device under test (DUT). The DSP device is mounted atop the bumps on the substrate bumps, similar in configuration to the procedure used in standard KGD carriers. The DSP is held in place by a spring load as is presently used in the prior art or by the temporary lid and compliant material used in the standard KGD carrier. The bumps upon the substrate can be either conductive polymer, such as, for example, as manufactured by EPI, compliant bumps, such as, for example, as manufactured by DTO or hard nickel-plated bumps, such as, for example, as manufactured by MMS. Other types of conductive bumps could serve as well.
The cost associated with this KGD system in accordance with the present invention is the cost associated with retooling the ceramic or equivalent header and the cost to build the substrates for electrical interconnection between the die and the header. This solves the problems previously presented to the DSP/KGD program by making available a test carrier with established electrical characteristics that fits into the existing package flow as, for example, the pin arrangement changes and/or the pin arrangement and number remains the same but the chip and bond pad locations thereon are shrunk or enlarged, generally the former, thereby making the header reusable.
The DSP/KGD solution of the present invention differs from the KGD carrier solutions in that, first, it utilizes the principle of maintaining the electrical test and burn-in infrastructure that is already in place for the DSP product line. This means that a new product can be provided and subjected to burn-in and the test on a single package that can use DSP/KGD and the KGD can be produced along with the package product for the same process flow and pin configuration. The KGD that result can be used for several options that can leverage the backend structure. These options include (a) a KGD die bank for customers to draw upon, (b) multichip module (MCM) die product, (c) KGD to be used for other more expensive packages that require a high yield die, and (d) KGD to be shipped directly to customers. The use of a single package qualification results in a much lower cost for KGD electrical and test infrastructure. Furthermore, the DSP/KGD solution is scaleable from low to high volume lines. This solution can be used for a low cost manually loaded die into the package. It can also be loaded by an automated assembly line that uses load and unload equipment set up prior art style carriers and then proceeds through the same test and burn-in lines. The low cost at each end of the spectrum makes the DSP/KGD attractive to the broad range of production requirements for KGD.
A further solution to the problem is to fabricate a special membrane that can be easily adapted to the design and change cycles of the integrated circuit. Such a membrane is composed of thin traces of metal lines that cross one another forming a criss-cross pattern upon the substrate material that is to be used for the base of the KGD test carrier. The metal is deposited upon a substrate such as, for example, a silicon wafer, ceramic, or polymer material that will fit into the test carrier. The metal can be any one or more of a plurality of electrical conductors such as, for example, aluminum, gold, silver or copper. The metal is coated onto the substrate. To form the crisscrossed structure for the test carrier membrane, the substrate is processed through a lithography and etching operation of standard type or other available technology to set the pattern in as tight or narrow a structure as required for the appropriate test contact pitches.
Once the test carrier membrane has been fabricated, it can be set up for the tooling process. The coordinates and types of signals upon the integrated circuit bonding pads and the size of the integrated circuit die product are known in advance. The design of the membrane is set so that it is a mirror image of the bond pads of the integrated circuit die. The traces from the interconnecting bump on the membrane connected to the bond pads on the die are routed to a bonding pad on the membrane for interconnection to the KGD test carrier leads. The design parameters are fed into the electrically controlled laser system which then cuts the criss-crossed metal leads into the pattern that has been fed to the laser system by the operator. After the leads are formed, the bumped interconnection is placed on the inner lead terminal which is the interconnection to the bond pads of the integrated circuit. This interconnection can be of the type set for in Ser. No. 09/431,730, the contents of which are incorporated herein by reference or a screened on conductive polymer bump. The location of the bump is programmed into the automated stud bump bonder. The conductive polymer location is defined by the screening mask. The die carrier membrane is then sawed on its sides and removed from the remainder of the substrates.
The completed test carrier membrane is then taken and mounted into the KGD test carrier which can be any one of the test carriers set forth in the above identified copending applications. Once mounted within the test carrier, the test carrier membrane is wire bonded to the test carrier to interconnect the bumped terminal to the test carrier leads.
The test carrier then goes through its normal assembly process which will place a spring held lid upon the backside surface of the integrated circuit die product to be tested.
The cost of the redesign is at a minimum because the membrane only requires software parameters for the laser to etch a new pattern therein. The formation of the bumps is also a software change to the bonder.
A principal feature of this invention lies in the use of the rerouted package so that the electrical test characteristics of the device are equal to what is already observed by the existing package. The rerouted header is a cost effective approach to producing a KGD carrier versus tooling a test carrier line. This invention utilizes already proven substrate technologies for carrying electrical signals from the die to the package lead. This invention also relies upon proven loading technology. For low volume lines, GelPac(trademark) or other appropriate soft material which also applies temporary adhesion to the KGD and a temporary lid are used for loading. For high volume lines, a spring and lock can be used. The use of the rerouted header differentiates the DSP/KGD package option from other prior art solutions.
The DSP KGD has the advantage of using the same package outline and pin structure as the already qualified DSP. This significantly lowers the cost of producing early life DSP product in the KGD format. The equivalent package form provides the option of using the same package for processing the KGD as is already used for the existing packaged parts. This can be leveraged to build a KGD die bank for economically providing whatever KGD product the customer requires.
There is a significant decrease in the redundancy of package qualification. The reduced requirement to qualify numerous packages means less cost of manufacturing the product and thus greater profit per KGD product. The DSP/KGD packaging option can be used for processing internally the KGD product that requires burn-in to open the early maturity product that was before excluded from the KGD program. The low cost of producing early life KGD provides a significant advantage in KGD product over those that require test carriers or require waiting until the die is sufficiently mature for probe. The temporary carrier lines are fraught with problems on the KGD such as, for example, handling damage, contamination and poor visual quality of the product. The DSP/KGD approach solves these problems because the dice are handled in a closed carrier with xe2x80x9cSoft Handling Technologyxe2x80x9d as set forth in Ser. Nos. 09/164,580 and 09/500,519, now U.S. Pat. No. 6,209,532.

Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers


An oxygen permeable film including an aggregate of water-repellent particles and having an average particle size of the particles of 0.01 to 50 μm has a contact angle with water of not less than 120° and super water repellency, and therefore has an excellent water vapor permeation inhibiting capability. As the particles, fluorocarbon resins such as polytetrafluoroethylene, polyvinyl fluoride and polyvinylidene fluoride are suitable. The specific surface area of the oxygen permeable film is preferably not less than 0.1 m2/g and not more than 500 m2/g.

In order to prevent the entrance of moisture along with oxygen, various contrivances have been made to many elements and devices utilizing oxygen in air, such as air cells and fuel cells. In the case of an air cell, for example, the entrance of water vapor in the atmosphere into the cell causes the concentration change or volume change of the electrolyte, thus degrading the discharge characteristics.
Therefore, it has been proposed to provide an oxygen-selective permeable film comprising a siloxane-based compound and an oxygen-permeable solution layer at the air intake opening of an air cell, thereby preventing the entrance of water vapor in the atmosphere into the cell (Patent Document 1).
Further, an air cell has also been proposed in which a uniform film or the like is provided with plural permeable pores of not more than 300 μm for passing air and that uses this as a selective permeable film for inhibiting the permeation of water vapor (Patent Document 2).
Further, although not in the field of batteries, in the case of a radio antenna used in a heavy snowfall area, snow or ice attached to the surface of the antenna may reduce the electric field strength, thus causing deterioration in the quality of telecommunication. In order to prevent this, a technique is available in which PTFE (polytetrafluoroethylene) particles are applied as the snow resistant material to the surface of the antenna, using a binder (Non-Patent Document 1).
Patent Document 1: Japanese Laid-Open Patent Publication No. Sho 59-75582
Patent Document 2: Japanese Laid-Open Patent Publication No. Hei 6-44954
Non-Patent Document 1: Super water-repellency and super water-repellent technology, published by Technical Information Institute Co. Ltd., p. 155-163

Oxygen permeable film, oxygen permeable sheet, and cell including these

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


The present invention relates to a real-time wideband compressor for multi-dimensional data. The compressor comprises a plurality of compression engines for simultaneously compressing a plurality of data subsets of a set of input data vectors and providing compressed data thereof using one of SAMVQ or HSOCVQ data compression. Each compression engine comprises an along spectral vectors codevector trainer as well as an across spectral bands codevector trainer. The compression engines are programmable to perform either along spectral vectors codevector training or across spectral bands codevector training in combination with one of the SAMVQ or HSOCVQ techniques without changing hardware. The compressor further comprises a network switch for partitioning the set of input data vectors into the plurality of data subsets, for providing each of the plurality of data subsets to one of the plurality of compression engines, and for transmitting the compressed data. The real-time wideband compressor is highly advantageous in, for example, space applications by programmable enabling performance of different techniques of codevector training as well as different techniques of VQ. Furthermore, after the compression process is started the compression process is performed autonomously without external communication.

The next generation of satellite-based remote sensing instruments will produce an unprecedented volume of data. Imaging spectrometers, also known as hyper-spectral imagers, are prime examples. They collect image data in hundreds of spectral bands simultaneously from the near ultraviolet to the short wave infrared, and are capable of providing direct identification of surface materials.
Hyper-spectral data thus collected are typically in the form of a three-dimensional (3D) data cube. Each data cube has two dimensions in the spatial domain defining a rectangular plane of image pixels, and a third dimension in the spectral domain defining radiance levels of multiple spectral bands per each image pixel. The volume and complexity of hyper-spectral data present a significant challenge to conventional transmission and image analysis methods.
Data compression using Vector Quantisation (VQ) has received much attention because of its promise of high compression ratio and relatively simple structure. The VQ procedure is known to have two main steps: codebook generation and codevector matching. VQ can be viewed as mapping a large set of vectors into a small set of indexed codevectors forming a codebook. During encoding, a search through a codebook is performed to find a best codevector to express each input vector. The index or address of the selected codevector in the codebook is stored associated with the input vector or the input vector location. Given two systems having a same codebook, transmission of the index to a decoder over a communication channel from the first system to the second other system allows a decoder within the second other system to retrieve the same codevector from an identical codebook. This results in a reconstructed approximation of the corresponding input vector. Compression is thus obtained by transmitting the index of the codevector rather the codevector itself.
In an article entitled "Lossy Compression of Hyperspectral Data Using Vector Quantization" by Michael Ryan and John Arnold in the journal Remote Sens. Environ., Elsevier Science Inc., New York, N.Y., 1997, Vol. 61, pp. 419-436, an overview of known general vector quantization techniques is presented. The article is herein incorporated by reference. In particular, the authors describe issues such as distortion measures and classification issues arising from lossy compression of hyper-spectral data using vector quantization.
Two innovative data compression techniques have been recently disclosed by the same inventor in U.S. patent application Ser. No. 09/717,220 filed 22 Nov. 2000 issued as U.S. Pat. No. 6,701,021 and in U.S. patent application Ser. No. 09/725,370 filed 24 Nov. 2000 issued as U.S. Pat No. 6,724,940, which are incorporated herein by reference. Both compression techniques—Successive Approximation Multi-Stage Vector Quantization (SAMVQ) and Hierarchical Self-Organizing Cluster Vector Quantization (HSOCVQ), respectively—are capable to provide near-lossless data compression if a fidelity threshold parameter is set to a value such that the error induced during the compression is at the same level of the intrinsic noise of the original data.
However, implementation of a lossy compression method for real-time data compression of a continuous data flow is substantially complicated due to the fact that the complete hyper-spectral data cube is not available for compression. In real-time compression onboard a satellite, hyper-spectral data corresponding to only a 2D focal plane frame sensed at a given moment from a swath target—across track line—on ground is available together with the hyper-spectral data corresponding to 2D focal plane frames sensed before. One—spatial-dimension of the 2D focal plane frame corresponds to a line of ground samples—called ground pixels, and another dimension of the 2D focal plane frame corresponds to a spectrum expansion of each ground pixel in wavelength. The spectrum expansion of a ground pixel is referred to as a "spectral vector". A focal plane frame comprises a same number of spectral vectors and ground pixels. The second spatial dimension of the hyper-spectral data cube is obtained by sensing successive swath targets in along-track direction of the moving satellite producing successive 2D focal plane frames.
Therefore, it is only possible to apply the compression to successive 2D focal plane frames or successive regions comprising several 2D focal plane frames substantially inhibiting successful application of lossy compression at high compression ratios. Application of conventional lossy compression methods on a region-by-region basis results in visible artifacts at the boundaries between the regions severely affecting image quality after decompression.
Furthermore, for real-time compression of a continuous hyper-spectral data flow, it is necessary to increase data throughput by using parallel operation of a plurality of compression engines. Therefore, a regional data cube is split into a plurality of smaller regional sub-cubes, referred to as vignettes herein. However, when a regional data cube is split into vignettes and each vignette is processed independently, a spatial boundary is introduced between two adjacent vignettes resulting in visible artifacts after decompression.
In U.S. patent application Ser. No. 10/606,761 filed Jun. 27, 2003 issued as U.S. Pat. No. 6,798,360 and U.S. patent application Ser. No. 10/611,897 filed Jul. 03, 2003 published as U.S. Patent Pub. No. 20050002584, which are incorporated herein by reference, the same inventor discloses compression techniques for compressing a continuous data flow in real time also enabling data compression using parallel operation of a plurality of compression engines. These innovative techniques overcome the above problems of real time data compression and allow implementation of SAMVQ as well as HSOCVQ.
Therefore, these techniques support a successful realization of a real-time wideband compression system.

Data compression engines and real-time wideband compressor for multi-dimensional data


A modular data storage tape library includes a modular frame having a form factor similar to other types of computing racks. The modular data storage tape library includes a hermetically sealed enclosure within the modular frame and a cooling portion within the modular frame. Data storage tapes, data storage drives and robotics for moving the data storage tapes are included within the hermetically sealed enclosure. A heat exchanger transfers heat from the hermetically sealed enclosure to the cooling portion outside of the sealed enclosure through a boundary of the hermetically sealed enclosure without introducing air from the data center into the hermetically sealed enclosure. Because air is neither introduced nor removed from the hermetically sealed enclosure, humidity fluctuations are minimal, if existent, and contaminants are prevented from entering the hermetically sealed enclosure, thus increasing the life spans of the data storage tapes included in the hermetically sealed enclosure.

As the technological capacity for organizations to create, track, and retain information continues to grow, a variety of different technologies for managing and storing the rising tide of information have been developed. Secure and reliable long-term data storage is one such technology that satisfies the need to archive collected information that may be used infrequently. For instance, information archives may be stored on physical mediums, such as magnetic tape data storage.
Magnetic tape cartridges may store archived data for long periods of time and may be susceptible to decay or damage over time if not properly stored. For example, humidity, particulate matter (such as dust), heat, fluctuations in temperature or humidity, etc. may over time cause the magnetic tape in the magnet tape cartridges to decay or become damaged.
Moreover, to avoid such decay or damage over long periods of time, magnetic tape cartridges may need to be maintained in an environment with tighter controls, such as in regard to temperature, humidity, particulate matter, etc., than are acceptable or needed for other computing components such as servers, networking equipment, etc.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include," "including," and "includes" mean including, but not limited to.

Modular rack sized data storage tape library with hermetically sealed tape compartment


A retractable cleat for recreational boats and the like includes a seal to inhibit moisture from entering the interior of the cleat. The retractable cleat has a base member, a retractable cleat member and seal positioned therebetween. The base has an upper plate for mounting on an associated boat surface, and a tube depending therefrom. The tube has a hollow interior with a stepped-shaped seat disposed adjacent to an uppermost end thereof. The retractable cleat member has an upper cleat-shaped head and a post depending therefrom. The post is telescopingly received into the interior of the base tube. The seal has an exterior surface thereof closely received in the base seat, and an interior surface closely receiving the cleat post therein. The resilient seal is configured to permit the post to slide longitudinally when the retractable cleat is shifted between a raised use position and a lowered storage position, and forms a watertight seal about the post to inhibit water from seeping into the base.

The present invention relates to cleats for recreational boats and the like, and in particular to a retractable cleat which incorporates a seal that prevents water from seeping into the interior of the retractable cleat.
Retractable cleats are widely used within recreational boats for securing mooring lines and the like thereto. These retractable cleats typically include a base member, and a retractable cleat member that is telescopingly received within the interior of the base.
Heretofore, retractable cleats have generally been constructed such that the mounting post portion of the retractable cleat fits rather loosely within the associated base. This loose fitting connection can allow water to seep into the base, and collect at the bottom thereof, thus causing corrosion of the base as well as the posts. The corrosion of the retractable cleat and base members often result in an unattractive overall appearance, and can hinder proper operation of the retractable cleat itself.


To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

The present invention relates to memory accessing and addressing for a parallel processing computer system. More particularly, the invention relates to a distributed/shared memory in which each of the processors constituting a parallel processing computer system can refer to all of the memories.
The demand for a high-speed processing performance of computers has prompted the appearance of a parallel processing computer system in which plural arithmetic processors are linked to each other. A TCMP (Tightly Coupled Multi-Processor) type parallel processing computer system has several arithmetic processors, which share one memory.
On the other hand, there has appeared a parallel processing computer system having many more arithmetic processors than those of the TCMP type, more specifically, several hundreds to several thousands of arithmetic processors. From the viewpoint of the degree of ease in realizing the hardware, each arithmetic processor has its own memory independently and the arithmetic processors do not share one storage, which is a parallel processing computer system of distributed memory type.
The distributed memory type can have a higher performance than the TCMP type. However, it has been pointed out that the distributed memory type parallel processor computer system involves some problems in portability being restricted by a conventional programming style (in which a single arithmetic processor and a single memory is assumed to be used) and in the case of programming generally. Therefore, in recent years, a distributed/shared memory type parallel processing computer system tends to be introduced increasingly in which each of the arithmetic processors of a distributed memory type can refer to the memories of the other arithmetic processors.
In order to implement a distributed/shared memory type, various problems should be solved. One of them is how to allow each of the processors to refer to the memories of the other processors. This problem can be solved by addressing. More specifically, in the address space of each processor, the memories of the other processors are mapped. For example, "RP3 Processor-Memory Element", p. 782 to p. 789, a proceeding on the International Conference on Parallel Processing in 1985 and U.S. Pat. No. 4,754,394 use an address having a format as shown in FIG. 4 to refer to the memory of the other arithmetic processors. Japanese Patent Laid-Open No. 155465/1981 uses an address having a type shown in FIG. 11.
The address shown in FIG. 4 is such that the accessed arithmetic processor having a memory to be referred to is designated by the fixed length processor number field 401, and the address in the memory is designated by the fixed length offset field 402. Also, the address shown in FIG. 11 is such that whether the memory to be referred to belongs to the accessing processor or to another processor is designated by one bit field F 1101; the accessed arithmetic processor having the memory to be referred to when accessing another processor is designated by the fixed length processor number field 1102; the address in the memory is designated by the fixed length offset field 1103; and the content of the fields 1102 and 1103 coupled to each other is used as the address when accessing the memory of the accessing processor.

Memory access mechanism for a parallel processing computer system with distributed shared memory


A method and computer system for identifying internet web pages containing documents that comply with a predetermined XML schema. The method includes searching the internet with a search engine for web pages using initial search terms and identifying a first set of HTTP URLs, web crawling at least the first set of HTTP URLs to identify additional HTTP URLs, appending a query to the identified URLs, and evaluating the responses to the query to determine which responses comply with the predetermined XML schema. The XML schema can be a Web Mapping Services schema. The system can store responses that comply with the XML schema in a database of servers, periodically check the database for validity, and convert the map requests for map servers in the database to a GIDB Portal Interface API.

Worldwide governmental and commercial entities continue to make more geospatial data available on the internet. The Open Geospatial Consortium (OGC) provides public specifications for a variety of geospatial web services such as Web Mapping Service, Web Feature Service, and Web Coverage Service. Web Mapping Services (WMS) are those services that interface client applications with server applications to provide a map image.
While the number of available WMS servers on the web has been growing steadily, searching for new WMS sources is often reduced to simply using an Internet search engine (e.g., GOOGLE™ or a similar search engine) to find WMS servers on the Internet.
The Open Geospatial Consortium has provided a number of public standards for geospatial web services, which have grown substantially in popularity and use over the past several years. However, while some client and server applications adhere to the OCG standards, the process for searching for OGC web services on the web is still mostly done manually. There have been attempts to automate the discovery process. For example, Refractions Research provides an online service at <http://www.refractions.net> for conducting an automated OGC web services survey using the Google APIs to search for WMS "Capabilities" documents by including strings such as "url:REQUEST=GetCapabilities" in the Google API search query. The Google API query returns found URLs of this form that are then processed to verify whether a URL returns a valid OGC web service "Capabilities" document.
A web mapping services server is most often advertised by a typical HTTP URL such as http://www.wmsServerHost.com/path?. Requests to the WMS server are constructed by configuring key-value pairs in the query part of the URL. For example, a URL of the form http://www.wmsServerHost.com/path?REQUEST GetCapabilities&SERVICE=WMS can return an XML "Capabilities" document that adheres to a WMS "Capabilities" schema as published by the Open Geospatial Consortium. A "Capabilities" document is analogous to a web service definition file in the WSDLISOAP web service model (W3C. 2001) and describes the map layers that the WMS server provides, along with the WMS server's contact info and metadata. A WMS client retrieves and scans this document to issue map requests for map layers featured within the document.
A number of WMS client applications provide a variety of mapping capabilities such as zoom in/out, map image transparency, and layering by configuring the HTTP key-value pairs according to user actions. OGC Web Mapping Service Capabilities documents validate to a common XML Schema published by the Open Geospatial Consortium, for example, the current XML schema W3C.2004. Programming to a common standard interface allows for a great amount of interoperability between WMS client and server implementations.
A map can be fetched from a WMS server by typing a WMS URL request in an internet browser to retrieve the map image. An example of a WMS URL request is <http://dmap.nrlssc.navy.mil/ogcwms/servlet/WMSServlet/GIDBImageServer.wms?Request=GetMap&SERVICE=WMS&Layers=NASA_BLUE&BBOX=−180.−90.0,180.0,90.0&WIDTH=800&HEIGHT=600&FORMAT=image/png>. This WMS URL request fetches a NASA Blue Marble PNG map image of 800 pixels width and 600 pixel height and geographic region of (−180, 90, 180, 90). The WMS server host is <dmap.nrlssc.navy.mil>, and the URL path is </ogcwms/servlet/GIDBImageServer.wms?>. The query part of the URL is: <Request=GetMap&SERVICE=WMS&Layers=NASA_BLUE&BBOX=−180.−90.0,180.0,90.0&WIDTH=800&HEIGHT=600&FORMAT=image/png>. The various map request parameters in the query part of this URL are HTTP key-value pairs that specify the geometric bounding box of the map image (e.g., pixel width and height).
As discussed previously, manually searching for new WMS systems can be accomplished by using an internet search engine (e.g., the GOOGLE™ search engine) to find WMS servers on the internet. In addition, Refractions Research (<www.refractions.net>) provides the ability to conduct an automated OGC web services survey using the Google™ search engine APIs to search for WMS "Capabilities" documents by including strings such as "url:REQUEST=GetCapabilities" in the Google API search query, then retrieving a "Capabilities" document by constructing a URL of the form: <http://wmsServerHost/path?REQUEST=GetCapabilities>. The search engine API query returns found URLs of this form that can then be processed to verify whether a URL returns a valid OGC Web Service "Capabilities" document. A recent Refractions Research OGC Web Services Survey has found over 1000 WMS Capabilities URLs.
WMS servers are sometimes advertised on the internet with a query within the URL string "REQUEST=GetCapabilities&SERVICE=WMS", e.g., <http://wmsServerHost/path?REQUEST=GetCapabilities&SERVICE=WMS", or with the WMS server URL but without the query term, e.g., <http://wmsServerHost/path> without the "REQUEST=GetCapabilities&SERVICE=WMS" appended. If a website hosts a spreadsheet or xml listing of WMS Servers advertised with only the WMS Server URL, Servers that conduct a search with a <http://wmsServerHost/path?REQUEST=GetCapabilities> query will be unable to find the website, for there is no URL pattern substring pattern to take advantage of.

System and method for automated discovery, binding, and integration of non-registered geospatial web services

The United States of America as represented by the Secretary of the Navy


A system and a method of creating context dependent yield variants of integrated circuit (“IC”) design components and using these variants during a physical design of an IC block to maximize manufacturing yield are described. A plurality of variants of each design component is generated and characterized with manufacturing yield as a function of neighboring context (“context”) that includes, but is not limited to, neighboring design components and other layout objects and shapes. The present invention describes a system and method where a physical design process, in addition to satisfying design and performance requirements such as, but not limited to, power, timing, signal integrity and minimal layout area, selects context dependent yield variants to maximize manufacturing yield.

An integrated circuit (IC) can be considered to be a graph of connected primitives such as, but not limited to, transistors and resistors. Such an entity is commonly referred to as a netlist. Each primitive is mapped to one or more layout objects that are two-dimensional geometrical objects such as, but not limited to, rectangles, polygons, and paths. In turn, these layout objects are used to define regions within a semiconductor die, which will receive different processing steps such as dopant, implants to produce N-type or P-type regions during the integrated circuit fabrication process.
Ultimately, every netlist must be mapped to an IC design layout ("layout") prior to its manufacture. IC designers typically use electronic design automation ("EDA") applications to create a layout. These EDA applications provide sets of computer-based tools for creating, editing, and analyzing layouts.
EDA applications create layouts from a netlist by various operations. Some, but not all, of a physical design ("PD") operations need to transform a netlist to a layout include: (1) placement which specifies locations of the IC components; (2) routing which generates layout objects to connect IC components; (3) additional operations to complete a layout such as, but not limited to adding substrate/well contacts and power/ground routing. The result of the physical design process is a layout.
A netlist can be partitioned into clusters of functional blocks ("blocks") such as logic, memory, analog and other functions. Since interface specifications for interactions among blocks are usually well defined, different IC designers can create each block independently and concurrently. IC designers create these blocks by assembling pre-built design components ("components") using EDA applications. These components are stored in a design component library ("DCL") and contain pre-characterized data called views such as, but not limited to, layout, logic, timing, power and other data views, required by EDA applications.
FIG. 1 illustrates some embodiments of a physical design process 1010 for a block. The process starts at 1040 by accepting a block specification 1030 and selecting components from a pre-built Design Component Library 1020. At 1050, the process computes component locations ("placement") and then generates the required component interconnections at 1060_("routing"). The result is a block 1070 composed of placed and interconnected components.
FIG. 2 illustrates some embodiments of an IC logic block composed of placed and routed components which are called standard cells. A standard cell implements a basic logic function and is stored in a pre-built standard cell library. All cells in a standard cell library conform to a certain set of standard requirements, including physical dimensions, electrical characteristics, etc. The physical design process places standard cell components in a two-dimension plane representing an IC chip and then generates interconnection among them. Such a physical design flow is called an application specific integrated circuit ("ASIC") flow. 210 is a representative standard cell component while 220 is a representative interconnection or routing among components.
FIG. 3 illustrates some embodiments of a physical design process 300 to generate an ASIC IC block. A standard cell library 310 contains basic design components, implemented as layout, logic, timing, power and other data views. Logic or physical synthesis tools 312, such as Synopsys Physical Compiler, transfer the logic description of the design 302 into a netlist 304 of logic views of cells; then placement tools 314, such as Cadence Encounter, transfer the netlist into a placed design in which cells are placed within a die area; then routing tools 316, such as Cadence Encounter, transfer a placed design to a IC mask layout 308 by generating required connections among cells. Both 314 and 316 use the layout view of the cells.
FIG. 4 illustrates some embodiments of an IC memory block composed of a bit-cell array and peripheral ("periphery") blocks. 430 is a bit cell array which contains IC components providing the memory functionality. Periphery 410, 420 and 440 contain circuitry to read and write information to and from the bit cell array. Periphery 450 and 460 are so called dummies blocks required to be present during a manufacturing process. The design of the bit-cell array and individual bit cells uses very specialized techniques to ensure that these structures are manufacturable with smallest layout area and is beyond the scope of this document. Peripheries, however, are implemented in a similar fashion as a logic block flow. Bit slice components are placed and routed to form a particular periphery such as, but not limited to, an address decode block. These bit slice components are stored in a collection analogous to a standard cell library.
The construction of the memory peripheral block is done either manually by a human designer or by a specialized EDA tool called a memory compiler. The operation to create a periphery is similar to that of an ASIC flow. FIG. 5 illustrates some embodiments of a process 510 used to generate a memory block. The process at 524 computes a memory architecture required for the memory requirement 520. At 528 the process selects a periphery to generate. At 532 the process computes the periphery parameters based on the memory architecture determined in 524. At 536 the process selects a set of bit slice components, places them in 540, and generates interconnections at 544. At 548 the process determines if there are any additional peripheries to be generated. If there are additional peripheries to be generated, the process returns to 528 to select another periphery to generate. If there are no more peripheries to be generated, the process produces the memory block at 552.
The quality of the components used to create the IC blocks is the primary determinant of the final IC design quality. Therefore, significant amount of resources are invested in the optimization of the components. The optimization objectives for the creation of the components include such aspects, but are not limited to, layout area, timing, power and signal integrity.
Each component is typically optimized individually with the assumption that electrically isolated neighboring components will have limited impact on the component eventual performance. For example, physical IP vendors like ARM optimize standard cells without considering context dependencies. Normally several versions of cell libraries are made for each process node to accommodate special needs for power consumption, speed or other user requirement.
Similar efforts are undertaken to design components comprising various memory peripheral blocks. For example, many variants of bit slice components for an address decode block are created to accommodate different configuration of bit cell arrays that a decode block might connect to. These variants are necessary since different bit cell array configuration have different electrical characteristics that must be accommodated in a particular bit-cell array configuration to order to satisfy performance requirements. These pre-built components are then selected by either a memory designer or an EDA memory compiler tool to construct a particular variant of a memory block.
IC fabrication is an extremely complex manufacturing process. Numerous manufacturing related considerations such as, but not limited to, lithography, etch, deposition and chemical mechanical polishing affect the final quality of the manufactured IC. Traditionally IC designers have not had to consider the manufacturing considerations during the design process; however, starting at the 130 nm process node, manufacturing considerations have started to impact negatively fabricated IC circuit performance relative to design requirements.
The manufacturing yield of an IC is defined to be the percentage of manufactured ICs meeting the product requirements. Examples of product requirements include, but are not limited to, functional correct operations at the specified clock frequency range and power dissipation below a specified value. The manufacturing yield is impacted by such considerations, but is not limited to, as the inherent variations of the IC manufacturing process, the semiconductor electrical property variations due to proximity effects such as STI stress and orientation relative to intentionally introduced stress structures, lithographic context dependent printability, and localized chemical mechanical polish (CMP) effects.
It has been recognized that variants of integrated circuit components dependent on different manufacturing considerations could be provided to designers so that the tradeoffs regarding yield and circuit performance can be made. Current approaches provide yield component variants that are developed and characterized in isolation without regard to neighboring context. A neighboring context ("context") is defined to be the surrounding layout regions of a particular component during fabrication as well as during a component's operational mode. Physical design tools using components characterized for yield without regard to the context may not improve the yield, and sometimes even reduces it.

System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells


A semiconductor device in which a flat inner lead is connected to a semiconductor pellet so that a side edge of the inner lead is connected to the semiconductor pellet. The lead includes a constricted portion that is twisted so that the side edge faces a surface of the pellet to which the lead is connected. A lead frame is arranged so that the side edge can be twisted into position.

1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing the same, and a lead frame used therefor and, more particularly, to a technique of connecting an inner lead to a semiconductor pellet without using any bonding wire.
2. Description of the Prior Art
A technique most popularly used to connect an inner lead to a semiconductor pellet is a wire connection method. As shown in FIG. 1, a semiconductor pellet 20 is mounted and fixed on an inner lead 52. The pellet electrode (not shown) of the semiconductor pellet 20 is connected to an inner lead 51 by a bonding wire 54, i.e., a metal thin wire, and the resultant structure is encapsulated with a resin material 13.
In this connection method, a large area must be ensured for the inner lead to which the bonding wire 54 is connected, i.e., the inner lead 51 such that wire bonding is enabled, and a size reduction is difficult to attain. Additionally, since a noble metal such as Au is often used for the bonding wire 54 because of restrictions on various necessary solid state properties, the material cost increases. Furthermore, the bonding wire 54 is a thin wire and therefore has a poor mechanical strength regardless of its material. In an exposed state, the bonding wire 54 easily deforms or ruptures. Hence, measures for protecting the bonding wire must be taken in the manufacturing process. In addition, when an overcurrent flows to a semiconductor device manufactured using this method, the wire tends to fuse and rupture because of resistance heating of the wire, so the semiconductor device cannot be used under such conditions. That is, a problem of surge resistance arises.
As described above, the wire connection method has a lot of restrictions and problems. To solve some of these problems, Japanese Unexamined Utility Model Publication No. 3-21854 discloses a technique shown in FIG. 2. Referring to FIG. 2, the terminal portion of an inner lead 51 is made to overlap that of an inner lead 52. A semiconductor pellet 20 is inserted between the inner lead 51 and the inner lead 52 and connected to the two inner leads, and the resultant structure is encapsulated with a resin material 13.
When the technique disclosed in Japanese Unexamined Utility Model Publication No. 3-21854 shown in FIG. 2 is used, the semiconductor device can be made compact, unlike the wire connection method. In addition, without any bonding wire, the process of encapsulating the resultant structure with a molten synthetic resin can be completed within a short period of time.
However, to make the inner lead 51 overlap the inner lead 52, at least two lead frames are needed to form the respective leads. This results in a larger material cost for the lead frame than that of the wire connection method. In addition, when the semiconductor pellet 20 is to be inserted, the inner leads 51 and 52 and the semiconductor pellet 20 interfere with each other. The semiconductor pellet 20 tends to break by chipping. Furthermore, the bonding interface of the inner lead 52 is not always parallel to the electrode of the semiconductor pellet 20. Therefore, a process of forming a projecting electrode on the semiconductor pellet or a projecting bonding surface on the inner lead 52, or a process of inserting a bonding medium 55 between the electrode of the semiconductor pellet 20 and the inner lead 52 is necessary. This complicates the manufacturing process and also makes automation difficult, resulting in an increase in manufacturing cost.
Another prior art as shown in FIG. 3 is disclosed in Japanese Unexamined Patent Publication No. 4-93055. Referring to FIG. 3, one major surface of a semiconductor pellet 20 is bonded to the terminal portion of an inner lead 51, thereby mounting the semiconductor pellet 20. Thereafter, the terminal portion of an inner lead 52 is connected to a pellet projecting electrode 56 provided on the other major surface of the semiconductor pellet 20, and the resultant structure is encapsulated with a resin material 13.
As in the prior art shown in FIG. 2, in the prior art shown in FIG. 3 as well, the semiconductor device can be made compact, unlike the wire bonding method. In addition, the surge resistance increases. In the prior art shown in FIG. 3, the semiconductor pellet hardly breaks. However, a process of forming the pellet projecting electrode 56 is necessary, and as in the prior art shown in FIG. 2, two lead frames are needed to overlay the leads, resulting in an increase in material cost for the lead frames. Therefore, the manufacturing cost of the semiconductor device increases as a whole.
As a technique of solving some of the above problems in the prior arts shown in FIGS. 2 and 3, a semiconductor device shown in FIG. 4 is disclosed in Japanese Unexamined Patent Publication No. 60-241241. Referring to FIG. 4, the distal end portions of inner leads 51 of a lead frame which is covered with a metal suitably used as solder are connected to a pellet projecting electrode 56 of a semiconductor pellet 20 through a flat lead 57, and the resultant structure is encapsulated with a resin material 13.
Since only one lead frame is used for the semiconductor device shown in FIG. 4, an increase in material cost for the lead frame can be prevented. However, a process of connecting the pellet projecting electrode 56 and the inner leads 51 of the lead frame through the flat lead 57 is necessary. This makes the manufacturing process more complex than that in the prior art shown in FIG. 2 or 3 and also makes automation difficult. In addition, since the flat lead 57 must be prepared, the number of members increases to result in an increase in material cost. Furthermore, a process of forming a pellet projecting electrode to obtain the projecting electrode 56 or forming a projecting bonding portion on the flat lead 57 is needed. Therefore, the manufacturing cost increases as a whole.
A semiconductor device shown in FIGS. 5A and 5B is disclosed in Japanese Unexamined Patent Publication No. 62-35549. FIG. 5A is a horizontal sectional view, and FIG. 5B is a longitudinal sectional view. This semiconductor device solves some of the problems of the semiconductor devices shown in FIGS. 1 to 4. One lead frame is used in this device. The distal end portion of an inner lead 52 is bent sideways. A semiconductor chip 20 is mounted between the distal end portion of the inner lead 52 and that of an inner lead 51, and the resultant structure is encapsulated with a resin material 13.
In the semiconductor device shown in FIGS. 5A and 5B, the number of members decreases because one lead frame is used. However, plating must be performed for both the upper and lower surfaces of the lead frame, resulting in an increase in plating cost, as compared to the above-described prior arts. In addition, since the distal end portion of the inner lead 52 is bent, a width A of the semiconductor device after encapsulation cannot be decreased, and a large mounting area is required. Furthermore, since a process of bending and fully inverting the distal end portion of the inner lead 52 sideways is necessary, the lead frame transfer speed in the manufacturing process of the semiconductor device must be reduced, resulting in a decrease in productivity.
A similar semiconductor device as shown in FIG. 6 is disclosed in Japanese Unexamined Patent Publication No. 48-38070 in which one lead frame is used, and the distal end portion of an inner lead is bent. Referring to FIG. 6, the lead frame is constituted by support frames 58 and 59 and inner leads 51 and 52. A semiconductor chip 20 is mounted on an island, i.e., a wide portion at the distal end of the inner lead 51. The distal end portions of the inner leads 52 are bent and fully inverted sideways and connected to solder bumps serving as pellet projecting electrodes 56 of the semiconductor pellet 20.
In the semiconductor device shown in FIG. 6, the number of members is small because only one lead frame is used as in the device shown in FIGS. 5A and 5B. However, the solder bumps 56 must be formed on the semiconductor pellet 20 in advance. In addition, plating must be performed for both the upper and lower surfaces of the lead frame. This increases the manufacturing cost as a whole. Furthermore, in mounting the semiconductor pellet 20 on the inner leads 51 and 52, the inner leads 52 are bent and connected to the solder bumps 56 of the semiconductor pellet 20 before the lower surface portion of the semiconductor pellet 20 is fixed on the wide island of the inner lead 51. Since this operation is performed before the semiconductor pellet 20 is fixed to the inner lead 51, misalignment tends to take place between the semiconductor pellet 20 and the distal end portions of the inner leads 52, resulting in a bonding position misalignment of the inner leads 52. As in the prior art shown in FIGS. 5A and 5B, the lead frame transfer speed must be reduced.
As another prior art of this type, a semiconductor device shown in FIGS. 7A and 7B is disclosed in Japanese Unexamined Patent Publication No. 2-33956. The inner leads shown in FIG. 7B extend inward from support frames 58 and 59, and portions near the centers of them along the longitudinal direction serve as inner leads 51 and 52, respectively. The support frames 58 and 59 are connected through tie bars 53. A semiconductor pellet 20 is mounted on a wide portion at the distal end of one inner lead, e.g., the inner lead 51. The inner lead 52 is lifted together with the support frame 59 relative to the support frame 58 and the inner lead 51 (displaced in the direction coming out of the page of FIG. 7B), and at the same time, shifted in a direction indicated by an arrow in FIG. 7B relative to the support frame 58 and the inner lead 51. With this operation, the distal end portion of the inner lead 52 overlaps (overhangs) the semiconductor pellet 20 and is connected to the surface pellet electrode of the semiconductor pellet 20, as shown in FIG. 7A.
This semiconductor device can be made compact, and the lead frame transfer speed during the manufacturing process of the semiconductor device can be increased. As a matter of fact, however, with the planar shape shown in FIG. 7B, it is difficult to horizontally move the upper half portion of the lead frame relative to the lower half portion in the direction indicated by the arrow in FIG. 7B to attain a predetermined displacement and make the semiconductor pellet overlap the distal end portion of the inner lead 52 with good reliability. In addition, to selectively connect the inner lead 52 to the surface electrode of the semiconductor pellet 20, a bump electrode must be formed, or a projecting bonding portion must be formed on the inner lead 52. Furthermore, plating must be performed for both the upper and lower surfaces of the lead frame. This increases the member of manufacturing steps and the plating cost.
As described above, the prior arts have unique problems, respectively.
More specifically, the semiconductor device shown in FIG. 1 can hardly be made compact. The material cost for the bonding wire increases. The bonding wire tends to deform or rupture. The surge resistance of the semiconductor device in use is decreased.
In the semiconductor device shown in FIG. 2, the material cost of the lead frame increases. In the assembly process, the semiconductor pellet is susceptible to chipping and scratching. A process for forming a projecting electrode on the semiconductor pellet or a projecting bonding interface on the inner lead, or a process for inserting a bonding medium is needed. This complicates the manufacturing process and makes automation difficult to accomplish.
In the semiconductor device shown in FIG. 3, to form a projecting pellet electrode, the number of manufacturing steps increases. In addition, the material cost for the lead frame increases.
In the semiconductor device shown in FIG. 4, since the flat lead is used, the numbers of manufacturing steps and members increase. To form a projecting pellet electrode or a projecting bonding portion on the flat lead, the number of manufacturing steps increases.
In the semiconductor device shown in FIGS. 5A and 5B, since plating must be performed for both the upper and lower surfaces of the lead frame, the plating cost increases. The width of the semiconductor device can hardly be reduced. The lead frame transfer speed is low.
In the semiconductor device shown in FIG. 6, to form the solder bump on the semiconductor pellet, the number of manufacturing steps increases. Since plating must be performed for both the upper and lower surfaces of the lead frame, the plating cost increases. The lead frame transfer speed is low. Misalignment tends to occur between the semiconductor pellet and the distal end portion of the inner lead.
In the semiconductor device shown in FIGS. 7A and 7B, it is difficult to make the semiconductor pellet overlap the distal end portion of the inner lead. A process for forming a bump electrode or a projecting bonding portion on the inner lead is necessary. Since plating must be performed for both the upper and lower surfaces of the lead frame, the plating cost increases.

Semiconductor device, and lead frame used therefor


A color image processing system includes a color television camera monitoring an object to provide a video signal comprising three primary color components, and a color determination section which defines particular hue, chroma, and brightness regions. The video signal from the camera is analyzed at the color determination section in such a manner as to determine the video signal denotes the particular hue, chroma, and brightness when the three primary color components are found to fall within the particular hue, chroma, and brightness regions, respectively. Thus determined video signal is extracted as forming individual color signals indicating filtered images of the object with regard to the particular hue, chroma, and the brightness, respectively. A logic circuit is included in the system to perform a suitable logical function with regard to thus extracted color signals and to generate an output indicating an image of the object reflecting the result of the logical function, which is processed in an image deriving section to obtain geometrical characteristics including a location, area, and profile of the object with regard to a suitable combination of the filtered images.

1. Field of the Invention
The present invention relates to a process for extracting a particular color image of an object and a color processing device for deriving geometrical characteristics including a location, area, and profile of the object from the process.
2. Description of the Prior Art
For identification or inspection of an object or component in a factory assembly line, there has been proposed to utilizes a television camera to obtain a black-and-white image of the object and to process the image for deriving geometric characteristics of the object. Such process based on the black-and-white image is only available for identification in terms of the geometric characteristics and is therefore not able to distinguish the object by its color. To this end, another prior art process has been proposed to use a color television camera providing a video signal indicating a color image of the object and to process the video signal in such a manner as to extract a color image with regard to a particular color for obtaining the geometrical characteristics based upon the particular or filtered color image of the object. The particular color is generally selected and determined by the users to be a combination of three primary colors each having a suitable range of level. That is, when considering a color space defined by a coordinate system having coordinates of the three primary colors, the particular color can be determined within the color space as corresponding to a limited zone having the limited ranges of levels with respect to the three primary colors, respectively. However, such determination of the color is found not to be practical and reliable since the levels of the three primary colors will vary as the objects is monitored in varying illumination levels. To overcome this problem, it is also contemplated to elongate the zone by a certain extent in order to compensate for the variation in the illumination level as described in Japanese Patent Publication [kokoku] No. 59-5944. Nevertheless, a critical problem remains in this process in that it can not select the hue, chroma, and brightness independently from each other. For example, it is not possible to extract an image of the object having the same chroma but having different hue.

Process for extracting a particular color image of an object and a color processing device therefor


An embodiment of the present invention is directed to low-maintenance conversion of an advance function presentation (AFP) format to a portable document format. According to an embodiment of the present invention, hidden text may be inserted as locators in the AFP files. For example, the hidden text may be inserted in a small font size (e.g., approximately 1 point) in a color that matches the background, e.g., text in white. A benefit of this hidden text is that it does not need to change with the maintenance of the statement template. Accordingly, the transformation software template may be built, or trained, to look for these hidden text locators to identify the beginning and end of sections. This leads to a robust transformation software template that does not need to be maintained or changed with text changes in the statements.

Documents, such as bank statements, are often created using a tool such as OpenText™ Exstream, in a highly-structured format such as the AFP (Advance function presentation) format. AFP is an efficient format for high speed printing. The AFP format may also be compressed for archival purposes.
When a customer requests a statement/notice online, the data in the AFP format may be converted to PDF UA (Accessible format of PDF) for presentation to the end customer. Examples of suitable transformation software include the OpenText™ Output Transformation software and MasterONE from Crawford Technologies. Other suitable software that can convert AFP to Accessible PDF (PDF UA) may be used as is necessary and/or desired.
For this transformation to be done efficiently, the software requires the template of the composed AFP document. Specifically, it needs to know: (1) How composed statement/notice was structured (e.g., which section comes after which). For example, sections in statements may include the summary section, activity section etc.; (2) How to locate the beginning and end of a section; and (3) Once a section is located, what to expect inside of it (e.g., a three column table, seven column table, simple text, etc.).
To effectively communicate all the above information to the transformation tool, the statement template may be built in the transformation software as well along with Exstream. The template in the transformation software and in Exstream must be tightly coupled and maintained together.
Because bank statements are dynamic (e.g., changing/adding logos, headers, and messages on the statement), the templates in the transformation software and Exstream must be changed to reflect those changes. With each change in statement text, there is an increased risk of breaking the transformation software template by changing the text that is used as a locator in the transformation software.
These and other drawbacks exist.

System and method for low-maintenance conversion of advance function presentation format to portable document format