A signal processing apparatus and method for measuring a mass flow rate of a fluid flowing in conjunction with a surface of a Coriolis mass flow meter and a field-provable Coriolis mass flow meter. The apparatus includes: (1) a driver for creating a prescribed vibration in the surface, (2) a motion sensor for measuring a motion of the surface, (3) response characteristic determination circuitry, coupled to the motion sensor, for determining a response characteristic of the surface and (4) flow rate calculation circuitry, coupled to the response characteristic determination circuitry, for calculating a measured mass flow rate of the fluid as a function of the motion and the response characteristic. The field-provable meter employs the response characteristic to monitor or compare meter performance without requiring a separate proving device.

In the field of flow meters, Coriolis flow meters are unique in that they can directly measure the mass flow rate of a fluid with little or no intrusion into the fluid stream. Because of this, they have become increasingly popular and currently account for the fastest growing segment of the overall flow meter market.
Over the last 15 years, there has been a rapid evolution of developments in the field of Coriolis flow meters. These developments have concentrated on improving performance by optimizing flow conduit shapes and introducing improved signal processing techniques and different modes of vibration.
This evolutionary process began with the introduction of the first commercially-viable Coriolis mass flow meter using a U-shaped flow conduit vibrated in its first bending mode of vibration. The signal processing scheme employed was a time delay measurement between inlet and outlet motion signals. This method could give useful results, however, it was understood at that time that the elastic modulus of the vibrating portion of the flow conduit was itself a function of temperature, and that any changes therein change the sensitivity of the device. The temperature of the flow conduit had to be measured; then, the effect of temperature upon the elastic modulus of the flow conduit had to be characterized and a compensation value added to the flow signal to minimize the effects of changes in the elastic modulus of the flow conduit.
For example, 316L stainless steel is commonly used for the flow conduit material in these devices, yielding a theoretical tensile elastic modulus vs. temperature relationship of about -2.2% per 100.degree. F. increase (in the range between 0.degree. F. and 350.degree. F.) and nearly linear for that material. Therefore, the compensation value is commonly applied in a linear relationship to account for the effects of temperature on tensile elastic modulus. It should be noted here that some meter designs depend upon the shear modulus rather than the tensile modulus, or a combination thereof, and a corresponding compensation value exists thereto.
While the prior art compensation method was simple, it was also known that 316L elastic modulus became increasingly non-linear as the temperature became colder or hotter, and in general, for most common conduit materials, the elastic modulus vs. temperature curves are non-linear. This fact therefore necessitated adding more complex temperature compensation methods to account for a wider range of materials and non-linear temperature relationships.
As more Coriolis flow meters of different designs were put into service, it was found that not only temperature, but fluid density and pressure could also effect the sensitivity of the device. This realization prompted the same type of response from manufacturers as did the temperature problem earlier described in that the effects were required to be characterized and compensated for.
In the case of density effects, many types of Coriolis flow meters can calculate the density by virtue of the natural frequency of the conduit thereby yielding a signal proportional to density that can be used to compensate for density effects on sensitivity.
In the case of pressure effects, it was found that by restricting the conduit geometry to certain design relationships, pressure effects could be minimized. In either case however, the result was either more compensation circuit complexity or geometric design restrictions.
Flow meters with straight flow conduits were later introduced into the market. These meters are subject to temperature gradients between the flow conduit and the surrounding support structure that cause stresses in the flow conduit that can alter the sensitivity and zero of the device. Several methods were therefore introduced to accommodate this added problem, such as measuring the difference in temperature between the flow conduit and its support and calculating what the stress should be and deriving a compensation value based on that difference. Methods employing strain gages have also been employed for the purpose of determining the stress level and deriving the requisite compensation value, again adding more complexity to the circuit and necessitating greater understanding of the complex relationships between stress and the change in the sensitivity of a given device.
While the prior discussion has dealt primarily with effects on the sensitivity of a flow meter, another important flow measurement parameter is the zero. Since Coriolis flow meters are highly linear devices (or are made to have linear outputs) relative to mass flow rate, the two most important mathematical factors allowing their use as flow measurement devices are therefore (a) the slope of the output signal vs. the mass flow rate therein (here defined as the "sensitivity" or "K-factor"), and (b) the value of the output signal at the intercept of the line with a zero mass flow point (herein defined as the "zero").
The zero has been a much more elusive parameter for manufacturers to control because zero shifts are not usually caused by predictable changes in material constants etc., but can be caused by a number of subtle and interrelated problems in both the mechanics of the flow conduit, and in the electronics, both by design or by imperfections therein. These zero shifts are normally encountered along with changes in fluid or ambient conditions on the device similar to those just described for sensitivity effects, e.g., changes in temperature, pressure, density, frequency, viscosity or conduit stress.
To summarize the history, as Coriolis flow meter manufacturers have discovered effects on their devices that cause errors or changes in the sensitivity of their devices, they have generally chosen to characterize, measure and compensate for each effect individually, thereby creating complex compensation methods that are more expensive and less accurate than the method disclosed herein. A similar progression has taken place toward zero effects as well.
Although these various means and methods just described (and others not described) are employed to measure, and compensate for parameters that effect Coriolis flow meter sensitivity and zero, the primary and fundamental goal of all of these have been to simply determine the sensitivity and/or zero of the device to fluid flow, and then compensate for any changes therein. What is needed in the art is a way of avoiding the need to measure and compensate. What is needed is systems and methods for directly determining sensitivity or zero characteristics, or both, of a Coriolis flow measurement device, thereby allowing overall compensation for any changes in sensitivity or zero characteristics, regardless of source.

Signal processing and field proving methods and circuits for a coriolis mass flow meter


A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units being equal to the delay time of each of the first delay units; and a blocking control circuit configured to control the blocking circuit whether to pass or block the delayed signal that is input in the blocking circuit.

1. Field of the Invention
The present invention relates to a DLL (Delay-Locked Loop) circuit.
2. Background Art
A DLL circuit can control the delay of a signal. The DLL circuit is used, for example, for delaying the internal clock of a circuit device to synchronize the internal clock to an external clock of the circuit device. The performance of the DLL circuit can considerably affect the performance of a high-speed memory such as a DDR (Double Data Rate) memory.
Typically, the DLL circuit is provided with a delay line which includes plural delay units connected in series with each other. In the delay line, a reference signal propagates from a delay unit in an earlier stage to a delay unit in a later stage, and each delay unit outputs a delayed signal of the reference signal. The DLL circuit can decrease the delay of the reference signal, by employing a delayed signal output from a delay unit in an earlier stage. On the other hand, the DLL circuit can increase the delay of the reference signal, by employing a delayed signal output from a delay unit in a later stage. Hereinafter, a delay unit in an earlier stage is referred to as an earlier delay unit, and a delay unit in a later stage is referred to as a later delay unit.
Such a DLL circuit has a problem that considerable electric power is wasted on the delay line. In the DLL circuit, even when a delayed signal output from an earlier delay unit is used, the reference signal propagates to a later delay unit. In other words, the reference signal propagates to delay units located after a delay unit that outputs a delayed signal to be used, although they do not need the supply of the reference signal. Consequently, delay units that do not need to operate uselessly operate to waste power.
Therefore, an idea has been proposed that provides a blocking circuit in the delay line. The blocking circuit can switch between passing a reference signal (delayed signal) from a preceding stage to a subsequent stage and blocking the reference signal (delayed signal). In this case, the DLL circuit is provided with a delay line including plural delay units connected in series with each other and a blocking circuit inserted between those delay units.
In such a DLL circuit, wasted power consumption on the delay line is reduced. However, in this case, the delay time of each delay unit must be made equal to the delay time of the blocking circuit in order to enable the blocking circuit to serve as a delay unit. To make the delay time of each delay unit equal to that of the blocking circuit, the delay time of each delay unit must be increased, or the delay time of the blocking circuit must be decreased. The blocking circuit includes a circuit element for implementing the blocking function. Therefore, the delay time of the blocking circuit that has both blocking function and delaying function usually cannot be reduced to a value equal to the delay time of a delay unit that has only the delaying function. Accordingly, to make the delay time of each delay unit equal to that of the blocking circuit, in general, the delay time of each delay unit must be increased.
The equalized delay time is the minimum unit of delay time that the delay line can adjust. In other words, the delay time adjusted by the delay line has an error equal to the equalized delay time at maximum. This causes jitter in the DLL circuit that includes plural delay units and the blocking circuit. Therefore, the DLL circuit has a problem that jitter increases while wasted power consumption on the delay line is reduced. This is because the delay time of each delay unit needs to be increased in order to make the delay time of each delay unit equal to that of the blocking circuit in the DLL circuit, which increases the minimum unit of delay time that the delay line can adjust. A large jitter is a problem when handling an RF signal, in particular.
JP-A H11-272355 (KOKAI) discloses a clock synchronization delay control circuit and a clock synchronization delay control method that prevent wasteful consumption of electric power.


A fuel pump noise reducing apparatus and a methods for a Liquefied Petroleum Injection (LPI) vehicle stops fuel provision by shutting off valves if a Liquefied Petroleum Gas (LPG) switch is turned off. Also, operation of a fuel pump is stopped by allowing an Interface Box (IFB) Electronic Control Unit (ECU) to turn off a relay and by insulating battery power provided to the fuel pump, thereby resulting in a reduction of noise and engine output consumption generated from unnecessary operation of the fuel pump.

Typically, vehicles that use LPG for fuel are configured in a way so that the LPG is injected to the engine in a gas state. LPG is provided from the fuel tank and is turned into gas by being passed through a vaporizer and mixer. However, the LPG engine has drawbacks in that the engine output performance, fuel economy, vehicle start at a low temperature, exhaust gas, and the like are compromised. Therefore, LPI engine vehicles have been under development recently to facilitate increased use.
LPI engine vehicles are configured to compressively transmit LPG fuel to an injector through the fuel line by using a fuel pump installed in the fuel tank. Next, the injector injects fuel into the engine in a liquid state to improve engine output, fuel economy, vehicle start function at a low temperature, and to decrease exhaust gas. In LPI engine vehicles, a shut off valve is equipped in the fuel tank and regulator, respectively. If the LPG switch is turned off while the engine is running, an Interface Box (IFB) closes the shut off valves and stops the fuel flow through the injector.
In the conventional LPI engine vehicles, when the LPG switch is turned off, the isolating valves in the fuel tank and regulator are closed to stop the fuel supply. However, there is a drawback in that even when the engine stops, the fuel pump is continuously activated by another power source, thereby increasing noise and output consumption due to the unnecessary operation of the fuel pump.

Fuel pump noise reducing apparatus and method thereof for liquefied petroleum injection vehicle


Systems and methodologies that facilitate real time recognition of missing and/or invalid objects in a component based framework, via employing a graceful load fail over engine that can self heal a component based application that has missing or invalid references, to be properly read, validated and executed on a user's machine. Information about the various components installed on a user's machine can be stored to reference a package backed up to a persistence state, and/or dummy objects or stubs can be provided to represent the missing object, and typically assure proper validation and/or execution of loaded object models.

Increasing advances in computer technology (e.g., microprocessor speed, memory capacity, data transfer bandwidth, software functionality, and the like) have generally contributed to enhanced computer application in various industries. Ever more powerful server systems, which are often configured as an array of servers, are commonly provided to service requests originating from external sources such as the World Wide Web, for example.
As software systems have become more complicated, it has become common to build such systems from a plurality of objects and files. For example, a software system may include hundreds of files or objects, wherein building a software or application system can be undertaken on one or more build machines that can compile, assemble, link, and/or interpret files or objects. Typically, object-oriented computing is based upon the object model, wherein pieces of code called "objects" contain data (e.g., attributes) and may have actions (e.g., operations) performed thereon. An object can be defined by its interface, wherein the interface defines the characteristics and behavior of a kind of object, including the operations that can be performed on objects of that interface and the parameters to each operation. A specific instance of an object is identified within a distributed object system by a unique identifier called an object reference.
Many of the requisite files in the completed software product can be built in various stages, thus requiring a plurality of sources and/or generated/built files. Files generated by one part of the build process can be required as inputs to one or more other parts of the build process, and the build machines can have complete copies of the source files. For example, if a build machine A generates a file A1, and a build machine B generates a file B2, build machine A may need file B1 to produce a file A2, and build machine B may need file A1 to produce file B2. At the same time, objects loaded on a machine can become corrupted or even fail to properly load during a read, validation or execution.
In a distributed object system, a client can also create a proxy that images an object on a server. Typically, a proxy is an image of an object where the object resides in a different logical and/or physical entity (e.g., machine, process, network, and the like.) In distributed systems, proxies can facilitate local processing to improve efficiency. The object that is imaged can implement a first set of one or more interface and base class data types. Moreover, such objects can require that a proxy load a first set of one or more attributes and/or methods to image the object. When the proxy is created for the object that is imaged, the interface and base data types implemented by the object are typically automatically loaded into the client. Nonetheless and as explained earlier, objects loaded on a machine can become corrupted or even fail to properly load during a read, validation, or execution.
Distributing files necessary to complete the build of the software system to the build machines involved in the build is network bandwidth intensive, requiring large transfers of information, some of which can become corrupted or even unavailable during an up load. For example, one build machine can only need ten files to complete its portion of the build, while another build machine can need two hundred files to complete its portion of the build, and yet one missing file or object can hinder a proper operation of a requisite application, e.g., by failing to properly load during a read, validation, or execution.
Therefore, there is a need to overcome the aforementioned exemplary deficiencies associated with conventional systems and devices.


Disclosed is a semiconductor memory device including a normal memory array and preliminary memory array enabling a mutual data transfer. Word lines in the normal memory array and those in the preliminary memory array are controlled by separate row decoders and separate word drivers. Bit lines and sense amplifiers are provided commonly to the normal memory array and the preliminary memory array. When test data is written in a predetermined pattern into the normal memory array, data corresponding to the predetermined pattern is written in advance for each memory cell in the preliminary memory array. Then, after the row decoder and word driver for the preliminary memory array are enabled so that the word lines in the preliminary memory array are activated, the row decoder and word driver for the normal memory array are enabled so that the word lines in the preliminary memory array are activated. Thus, data signals read from memory cells of one row in the normal memory array are simultaneously amplified by the sense amplifiers via the bit lines and then transferred via the bit lines to memory cells of one row in the preliminary memory array. In this result, the test data are written at one time into the memory cells of one row in the normal memory array.

1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to a semiconductor memory device capable of reducing the time required for a functional testing of an internal circuit.
2. Description of the Background Art
As the capacity of a semiconductor memory device increases, an increase in the test time required for a functional testing of an internal circuit becomes a significant problem. Parallel testing technology for reducing the functional testing time of VLSI memories is proposed in the article by J. Inoue et al, entitled "PARALLEL TESTING TECHNOLOGY FOR VLSI MEMORIES", 1987 ITC Proceedings, pp. 1066-1071. In this parallel testing technology, all memory cells connected to one word line are tested at a time by adopting an on-chip testing circuit system in which a testing circuit for performing a functional testing of a memory and a tested circuit are mounted on a common chip.
FIG. 12 is a schematic block diagram showing the configuration of a memory including an on-chip testing circuit disclosed in the above-described document, which is a circuit for testing provided on the same chip as that of a tested circuit.
Referring to FIG. 12, a memory array 10 includes a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, and memory cells provided one for each of cross-over points between the bit lines and the word lines.
In this memory, in normal data writing, a data input circuit 101 receives externally applied data D.sub.IN. An externally applied address signal is applied via an address buffer 106 to a column decoder 104 and a row decoder 108. Column decoder 104 decodes the applied address signal to select a bit line connected to memory cells corresponding to the applied address signal. Row decoder 107 decodes the applied address signal, to select a word line connected to memory cells corresponding to the applied address signal. A word driver 108 activates the word line selected by row decoder 107 so as to enable data writing/reading relative to the memory cells connected to the selected word line. Then, the data received by data input circuit 101 is written via a multiplexer 103 into a memory cell provided in correspondence with the cross-over point between the bit line selected by column decoder 104 and the word line activated by word driver 108.
In normal data reading, column decoder 104 and row decoder 107 select a bit line and a word line, respectively, corresponding to an address signal applied through address buffer 106. Word driver 108 activates the word line selected by row decoder 107 similarly to the case of normal data writing. Accordingly, in response to storage data of a memory cell provided corresponding to the cross-over point between the bit line selected by column decoder 104 and the word line selected by row decoder 107, the potential of the selected bit line rises (when the storage data is logical high or an H level) or falls (when the storage data is logical low or an L level).
When no data reading/writing is carried out, two bit lines constituting each bit line pair is equalized at a predetermined potential (in general, V.sub.cc /2, 1/2of a supply potential). In data reading, the potential of the selected bit line rises or falls from the predetermined potential V.sub.cc /2 in response to the storage data of the selected memory cell. A sensing circuit 105 comprises differential amplifier circuits each receiving as inputs the respective potentials of the two bit lines constituting each bit line pair.
More specifically, when the potential of a bit line connected to the selected memory cell rises higher than the potential obtained in equalization, sensing circuit 105 raises the potential of this bit line to a high potential (supply potential) corresponding to a high logic level or the H level and simultaneously lowers the potential of the other bit line paired with this bit line to a low potential (ground potential) corresponding to a low logic level or the L level. Conversely, when the potential of the bit line connected to the selected memory cell falls lower than the potential obtained in equalization, sensing circuit 105 lowers the potential of this bit line to a low potential corresponding to the L level and simultaneously raises the potential of the other bit line paired with this bit line to a high potential corresponding to the H level. As a result, complementary data associated with the storage data of the selected memory cell is read onto the selected bit line and the other bit line paired therewith.
In normal data reading, as the result that sensing circuit 105 performs the foregoing operation, a potential appearing on the bit line connected to the selected memory cell, (which is the bit line selected by column decoder 104) is transmitted as the storage data of the selected memory cell via multiplexer 103 to a data output circuit 102. Data output circuit 102 outputs the data from multiplexer 103 as final read data D.sub.OUT.
A determination is made as to the presence/absence of defects of memory cells in the memory array, for example, dependently upon whether or nor data written in advance in the memory cells is the same data read from these memory cells. In this case, in order to test all the memory cells in the memory cell array, data should be read from each memory cell after the data is written in advance in all the memory cells. In normal data writing, however, data can be written into only one memory cell at one time. Thus, if the total number of memory cells in the memory array increases due to an increase in the storage capacity of the memory, a long time has to be spent for data writing for testing, resulting in an increase in the time required for a functional testing of the memory, in which the above-described presence/absence of defects of the memory cells and other problems are checked.
Thus, in the memory shown in FIG. 12, a testing circuit 20, including a write circuit 30 for performing data writing for testing in a different path from that established in normal data writing, is provided on a common chip on which memory array 10, data input circuit 101, data output circuit 102, multiplexer 103, column decoder 104, sensing circuit 105, address buffer 106, row decoder 107 and word driver 108 are provided, in order to reduce the time required for data writing for testing.
Testing circuit 20 includes write circuit 30, a comparison circuit 40 and a detection circuit 50. In testing, write circuit 30 receives as an input, data D.sub.TE for testing which is to be written in advance. Write circuit 30 simultaneously writes the data D.sub.TE into all memory cells connected to a single word line at a time. When this writing is completed, comparison circuit 40 is supplied with inversion data D.sub.TE of the previously written data D.sub.TE as expected data. Also, the operation of row decoder 107 as described above causes data to be read simultaneously from all the memory cells connected to the single word line, into which the data D.sub.TE is written in advance. Comparison circuit 40 makes a comparison between the read data and the inversion data D.sub.TE .
As the result of comparison by comparison circuit 40, if none of the read data match the inversion data D.sub.TE , i.e., the same data as the previously written data are read from all of the memory cells connected to the single word line, then detection circuit 50 outputs a flag signal DS of a predetermined logic level indicating that no defective memory cells exist. Conversely, if any of the read data matches the inverted data D.sub.TE , i.e., different data from the previously written data is read from at least one of the memory cells connected to the single word line, then detection circuit 50 outputs a flag signal DS of the opposite logic level to the predetermined logic level, indicating that a defective memory cell exists.
As described above, in this memory, a so-called line test is carried out by testing circuit 20, in which the presence/absence of defects of all the memory cells arranged in one word line direction (a row direction) in memory array 10 is checked at a time.
FIG. 13 is a circuit diagram showing the configuration of testing circuit 20 and peripheries thereof. The circuit of FIG. 13 is described in "1987 International TEST Conference", pp. 1066-1071. Referring to FIG. 13, memory array 10 is connected with testing circuit 20. Four word lines WL1-WL4 and two bit line pairs B1, B1 and B2, B2 are representatively shown.
Write circuit 30 includes N channel MOS transistors Q1-Q4, a write control line WC and write lines W and W. Comparison circuit 40 includes comparators having a common structure and provided corresponding to respective bit line pairs. The comparators provided corresponding to bit line pairs B1, B1 and B2, B2 are representatively shown in FIG. 13. A comparator CP1 corresponding to bit line pair B1, B1 includes N channel MOS transistors Q5 and Q6. Similarly, a comparator CP2 corresponding to bit line pair B2, B2 includes N channel MOS transistors Q7 and Q8.
A description will now be made of operation of testing circuit 20 upon line testing.
Data of the H level and that of the L level, for example, are first supplied to write lines W and W, respectively, so that the potential of write control line WC is raised to the H level. Accordingly, transistors Q1-Q4 are rendered conductive, so that the potential of bit lines B1 and B2 attains the H level, and the potential of bit lines B1 and B2 attains the L level. Now, the potential of word line WL1, for example, is raised to the H level by word driver 108 in FIG. 12 so that the word line may be activated. In response to the rise of the potential of word line WL1, data of the H level is written into memory cells M1 and M3. After this writing, the potential of word line WL1 attains the L level by word driver 108 so that the word line may be deactivated, and also the potential of write control line WC attains the L level.
Thereafter, when the potential of word line WL1 is again raised to the H level by word driver 108, potential changes depending on the data stored in memory cells M1 and M3 occur on bit lines B1 and B2. The potential changes on bit line pair B1, B2 are amplified by sensing circuit 105 in FIG. 12, as described above. As a result, each of bit line pairs B1, B1 and B2, B2 attains complementary potentials depending on data read from memory cells M1 and M3.
Data of the L level and that of the H level are then supplied to write lines W and W, respectively, oppositely to the case of data writing.
Detection circuit 50 includes an inverter G1, an N channel MOS transistor Q9 connected between an input terminal of inverter G1 and ground and having its gate receiving the potential on the connecting point between transistors Q5 and Q6 (an output terminal of comparator CP1), an N channel MOS transistor Q10 having its gate receiving the potential on the connecting point between transistors Q7 and Q8 (an output terminal of a comparator CP2), and a precharge circuit 51 connected to a connecting line N11 connecting transistors Q9 and Q10 and inverter G1. In practice, not only transistors Q9 and Q10 but also N channel MOS transistors are provided between inverter G1 and ground, one for each comparator provided corresponding to each of all the other bit line pairs. Precharge circuit 51 precharges connecting line N11 to the H level upon the start of testing.
When data is read out of memory cells M1 and M3, into which data for testing is written as described above, the potential of bit lines B1 and B2 attains the H level, and the potential of bit lines B1 and B2 attains the L level when the read data is at the same H level as that of the previously written data for testing. Accordingly, transistors Q5 and Q7 are rendered conductive in comparators CP1 and CP2, so that the potential of a connecting line N9 connecting comparator CP1 and transistor Q9 and that of a connecting line N10 connecting comparator CP2 and transistor Q10 both attain the L level in response to the potential on write line W. Thus, transistors Q9 and Q10 are put in an OFF state, so that the potential of connecting line N11 precharged by precharge circuit 51 does not fall. Accordingly, if data read from any other memory cells connected to word line WL1 is at the same H level as that of the previously written data, none of the N channel MOS transistors provided one for each comparator in detection circuit 50 are rendered conductive, so that a signal of the L level representing that no defective memory cells exist is output from inverter G1. This output of inverter G1 is the above-described flag signal DS.
Assuming now that memory cell M1 is defective, for example, data read from memory cells M1 and M3 attain the L level and the H level respectively despite the fact that data of the H level is written in memory cells M1 and M3. In response to the data attaining the L level and the H level, sensing circuit 105 performs the opposite operation from that of the foregoing case, so that the potentials of bit lines Bl and Bl attain the L level and the H level, respectively. Write lines W and W are supplied with data of the L level and that of the H level, respectively. Accordingly, transistor Q6 becomes conductive in response to the H level potential on bit line Bl, and connecting line N9 is charged to the H level. This causes transistor Q9 to be conductive, so that connecting line N11 is coupled to ground to be discharged to the L level. As a result, a flag signal DS of the H level representing that defective memory cells exist is output from inverter G1. More specifically, if there is one defective memory cell of all memory cells connected to a selected word line, then an output of a comparison circuit provided corresponding to a bit line pair corresponding to the defective memory cell causes a corresponding transistor in detection circuit 50 to be conductive, so as to lower the potential of connecting line N11 to the L level. This causes flag signal DS to attain the H level.
In this manner, the same data is written via write lines W and W in the memory cells of a single row connected to the selected single word line. Then, data is read from the memory cells of that row, and the opposite data from the previously applied data are applied to write lines W and W, respectively. When all the data read from the memory cells of the single row match the data previously written in those memory cells of the single row, the flag signal DS attains a logic level indicating that no defective memory cells exist. On the other hand, if there is at least one defective memory cell of the memory cells of the single row connected to the single word line, and data read from that defective memory cell does not match previously written data, the flag signal DS attains a logic level indicating that the defective memory cell exists.
As described above, in the memory including the on-chip testing circuit shown in FIG. 13, after the data for testing is written in all the memory cells connected to the single word line at the same time, a test is carried out for the memory cells at the same time. Therefore, a substantial reduction in test time is expected.
As has been mentioned above, in the conventional semiconductor memory device enabling the reduction in the test time, since the write control line and the write lines are provided in common to all the bit lines as shown in FIG. 13, identical data is written into the memory cells of a single row connected to a single word line. In other words, the pattern of test data entered in the memory cells of the single row is all the H level data or the L level data. Thus, it is impossible to perform a test which is enabled by writing of alternate data into two adjacent memory cells in a row direction, e.g., a detection of data interference between the adjacent memory cells, and the like. Therefore, in the conventional art, although the test time can be decreased by line testing, the kinds of tests practicable in shorter test time are limited. It is thus becomes difficult to detect defective memory cells from many aspects, resulting in a degradation in sensitivity of detection of the defective memory cells.

Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode


A method for processing a sound signal y in which redundancy, consisting mainly of almost repetitions of signal profiles, is detected and correlations between the signal profiles are determined within segments of the sound signal. Correlated signal components are allocated to a power component and uncorrelated signal components to a noise component of the sound signal. The correlations between the signal profiles are determined by methods of nonlinear noise reduction in deterministic systems in reconstructed vector spaces based on the time domain.

This invention relates to methods for processing noisy sound signals, especially for nonlinear noise reduction in voice signals, for nonlinear isolation of power and noise signals, and for using nonlinear time series analysis based on the concept of low-order deterministic chaos. The invention also concerns an apparatus for implementing the method and use thereof.
Noise reduction in the recording, storage, transmission or reproduction of human speech is of considerable technical relevance. Noise can appear as pure measuring inaccuracy, e.g., in the form of the digital error in output of sound levels, as noise in the transmission channel, or as dynamic noise through coupling of the system observed with the outside world. Examples of noise reduction in human speech are known from telecommunications, from automatic speech recognition, or from the use of electronic hearing aids. The problem of noise reduction does not only appear with human speech, but also with other kinds of sound signals, and not only with stochastic noise, but also in all forms of extraneous noise superimposed on a sound signal. There is, therefore, interest in a signal processing method by which strongly aperiodic and non-stationary sound signals can be analyzed, manipulated or isolated in terms of power and noise components.
A typical approach to noise reduction, i.e. to breaking down a signal into certain power and noise components, is based on signal filtering in the frequency band. In the simplest case, filtering is by bandpass filters, resulting in the following problem however. Stochastic noise is usually broadband (frequently so-called xe2x80x9cwhite noisexe2x80x9d). But if the power signal itself is strongly aperiodic and thus broadband, the frequency filter also destroys a power signal component, meaning inadequate results are obtained. If high-frequency noise is to be eliminated from human speech by a lowpass filter in voice transmission, for example, the voice signal will be distorted.
Another generally familiar approach to noise reduction consists of noise compensation in sound recordings. Here, for example, human speech superimposed with a noise level in a room is recorded by a first microphone, and a sound signal essentially representing the noise level by a second microphone. A compensation signal is derived from the measured signal of the second microphone that, when superimposed with the measured signal of the first microphone, compensates for the noise from the surrounding space. This technique is disadvantageous because of the relatively large equipment outlay (use of special microphones with a directional characteristic) and the restricted field of use, e.g., in speech recording.
Methods are also known for nonlinear time series analysis based on the concept of low-order deterministic chaos. Complex, dynamic response plays an important role in virtually all areas of our daily surroundings, and in many fields of science and technology, e.g., when processes in medicine, economics, signal engineering or meteorology produce aperiodic signals that are difficult to predict and often also difficult to classify. Thus, time series analysis is a basic approach for learning as much as possible about the properties or the state of a system from observed data. Known methods of analysis for understanding aperiodic signals are described, for example, by H. Kantz et al. in xe2x80x9cNonlinear Time Series Analysisxe2x80x9d, Cambridge University Press, Cambridge 1997, and H.D.I. Abarbanel in xe2x80x9cAnalysis of Observed Chaotic dataxe2x80x9d, Springer, N.Y. 1996. These methods are based on the concept of deterministic chaos. Deterministic chaos means that, although a system state at a certain time uniquely defines the system state at any random later point in time, the system is nevertheless unpredictable for a longer time. This results from the fact that the current system state is detected with an unavoidable error, the effect of which increases exponentially depending on the equation of motion of the system, so that after a relatively short time a simulated model state no longer bears any similarity with the real state of the system.
Methods of noise suppression were developed for time series of deterministic chaotic systems that make no separation in the frequency band but resort explicitly to the deterministic structure of the signal. Such methods are described, for example, by P. Grassberger et al. in xe2x80x9cCHAOSxe2x80x9d, vol. 3, 1993, p 127, by H. Kantz et al. (see above), and by E. J. Kostelich et al. in xe2x80x9cPhys. Rev. Exe2x80x9d, vol. 48, 1993, p 1752. The principle of noise suppression for deterministic systems is described below with reference to FIGS. 10a-c.
FIGS. 10a-c show schematically the dependence of successive time series values for noise-free and noisy systems (exemplified by a one-dimensional relationship). The noise-free data of a deterministic system produce the picture shown in FIG. 10a. There is an exact (here one-dimensional) deterministic relationship between one value and the sequential value. The time delay vectors, details of which are explained further below, lie in a low-dimensional manifold in the embedding space. Upon introduction of noise, the deterministic relationship is replaced by an approximative relationship. The data are no longer on the low-dimensional manifold but close to it as shown in FIG. 10b. The distinction between power and noise is by dimensionality. Everything leading out of the manifold can be traced to the effect of the noise.
Consequently, the noise suppression for deterministically chaotic signals is made in three steps. First the dimension m of the embedding space is estimated and the dimension Q of the manifold in which the non-noisy data would be. For the actual correction, the manifold is identified in the vicinity of every single point, and finally the observed point is projected to the manifold for noise reduction as shown in FIG. 10c.
The disadvantage of the illustrated noise suppression is its restriction to deterministic systems. In a non-deterministic system, i.e., in which there is no unique relationship between one state and a sequential state, the concept of identifying a smooth manifold, as shown in FIGS. 10a-c, is not applicable. Thus, for example, the signal amplitudes of speech signals form time series that are unpredictable and correspond to the time series of non-deterministic systems.
The applicability of conventional, nonlinear noise reduction to speech signals has been out of the question to date, especially for the following reasons. Human speech (but also other sound signals of natural or synthetic origin) is very much non-stationary as a rule. Speech is composed of a concatenation of phonemes. The phonemes are constantly alternating, so the sound volume range is changing all the time. Thus, sibilants contain primarily high frequencies and vowels low frequencies. So, to describe speech, equations of motion would be necessary that constantly change in time. But the existence of a uniform equation of motion is the requirement for the concept of noise suppression described with reference to FIGS. 10a-c.
It is accordingly an object of the invention to achieve an improved signal processing method for sound signals, especially for noisy speech signals, by which effective and fast isolation of the power and noise components of the observed sound signal can be performed with as little distortion as possible.
It is also an object of the invention to provide an apparatus for implementing a method of this kind.
A first aspect of the invention consists, in particular, in recording non-stationary sound signals, composed of power and noise components, at such a fast sampling rate that signal profiles within the observed sound signal contain sufficient redundancy for the noise reduction. Phonemes consist of a sequence of virtually periodic repetitions (forming the redundancy). The terms periodic and virtually periodic repetition are set forth in detail below. In what follows, uniform use will be made of the term virtually periodic signal profile. The recorded time series of sound signals produce waveforms that repeat at least over certain segments of the sound signal and allow application, on restricted time intervals, of the above mentioned, familiar concept per se of nonlinear noise reduction.
According to another aspect of the invention, virtually periodic signal profiles are detected within an observed sound signal and correlations are determined between the signal profiles so that correlated signal components can be allocated to a power component and uncorrelated signal components to a noise component of the sound signal.
Yet another aspect of the invention is the replacement of temporal correlations by geometric correlations in the time delay embedding space, expressed by neighborhoods in this space. Points in these neighborhoods yield the information necessary for nonlinear noise reduction of the point for which the neighborhood is constructed.
Another aspect of the invention provides an apparatus for processing sound signals comprising a sampling circuit for signal detection, a computing circuit for signal processing, and a unit for the output of time series devoid of noise.

Method and apparatus for processing noisy sound signals

Max-Planck-Gesellschaft zur Forderung der Wissenschaften e.V.


A process in which halogen is recovered from a cyclic operation for regenerating hydrocarbon conversion catalysts is disclosed. The process uses an arrangement of beds of adsorbent and a circulating stream to return the halogen-containing materials to a regeneration circuit.

Numerous hydrocarbon conversion processes are widely used to alter the structure or properties of hydrocarbon streams. Such processes include isomerization from straight chain paraffinic or olefinic hydrocarbons to more highly branched hydrocarbons, dehydrogenation for producing olefinic or aromatic compounds, reforming to produce aromatics and motor fuels, alkylation to produce commodity chemicals and motor fuels, transalkylation, and others.
Many such processes use catalysts to promote hydrocarbon conversion reactions. These catalysts tend to deactivate for a variety of reasons, including the deposition of carbonaceous material or coke upon the catalyst, sintering or agglomeration or poisoning of catalytic metals on the catalyst, and/or loss of catalytic metal promoters such as halogens. Consequently, these catalysts are typically reactivated in a process called regeneration. Reactivation can thus include, for example, removing coke from the catalyst by burning, redispersing catalytic metals such as platinum on the catalyst, oxidizing such catalytic metals, reducing such catalytic metals, replenishing catalytic promoters such as chloride on the catalyst, and drying the catalyst.
One of the problems during regeneration of halogen-containing catalysts is loss of halogen itself from the catalyst. This happens when the catalysts are contacted with gases that, while regenerating the catalyst, tend also to remove halogen from the catalyst.
U.S. Pat. No. 5,965,473 discloses a method for recovering chlorine-containing materials from the effluent gases during catalyst regeneration in a hydrocarbon conversion process with a cyclic regeneration operation. To prevent loss of chlorine-containing materials, U.S. Pat. No. 5,965,473 uses one of the off-stream catalyst beds. This is an inefficient use of the vessel that contains the off-stream catalyst bed as well as of the catalyst itself, both of which could be better used for promoting hydrocarbon conversion reactions. Therefore, more efficient methods are sought to decrease the loss of halogen during halogen-containing catalyst regeneration.

Cyclic catalyst regeneration process using a circulating stream for desorption


A toggle linkage for incorporation into a frame of a structure, such as a building, including a first link having a shock absorber therein, a first end on the first link connected to a first area of the frame, a second link having a first end connected to a second area of the frame remote from the first area, a second end on the second link, a third link having a first end connected to a third area on the frame remote from the first and second areas, a second end on the third link, a second end on the first link connected proximate the second end of the second link, and the second ends of the second and third links being connected to each other by a metal plate which is welded therebetween and which flexes in the direction of its thickness and not in the direction of its width so as to maintain the longitudinal axes of the second and third links in the same plane when the toggle linkage is activated by a seismic event as before the toggle linkage was activated.

The present invention relates to an improved seismic isolation structure utilizing a toggle linkage.
By way of background, there are in use two common types of seismic isolation devices utilizing viscous dampers. One type is a diagonal brace structure incorporating a viscous damper, which is placed in a frame of a structure, such as a building. Another type of device is a Chevron structure which is placed in the frame of a building. The seismic displacement which is opposed by the foregoing seismic isolation devices is the horizontal displacement between the floors of a building or between various levels of other structures, such as bridges, and it is this displacement which must be used to drive the viscous damper. However, in diagonal and Chevron isolation devices, the damper has a very small displacement as the various levels of a structure move relative to each other, thereby requiring large, heavy, short stroke dampers which are relatively expensive both in initial cost of fabrication and cost of installation. By way of broad example, the relative movement between floors of a building could be on the order of a fraction of an inch. Thus, for example, in a rectangular frame of a building wall having a dimension of about 22 feet horizontally and 20 feet vertically and having a diagonal of about 30 feet, the change in length of the diagonal would be only a fraction of an inch. This small fraction of an inch in change in length of a diagonal constitutes the stroke which has to be applied to the viscous damper, thereby necessitating the above-mentioned relatively large, heavy, short stroke dampers. Another type of seismic isolation device which is known in the prior art is a toggle linkage such as shown in opened Japanese patent application Sho 63-114069 (Patent No. 1-284639). The advantage of a toggle linkage is that it essentially magnifies relatively small movements between levels of a structure, that is, it provides a motion which is larger than the motion produced by the change in length of a diagonal brace or by the movement of a Chevron brace. Thus, a toggle brace permits the use of relatively inexpensive long stroke, relatively light hydraulic dampers and also permits the use of other types of long stroke shock absorbers. However, toggle linkages with clevis types of connections at the junctions of the links of a toggle linkage have certain deficiencies, namely, (1) there is too much play at the clevis so that the shifting of the floors of a building is not fully transmitted by the links of the toggle linkage to the damper, and (2) the clevis connection inherently permits out-of-plane buckling which further diminishes the amount of floor shifting which is effectively transmitted to the toggle linkage. It is with overcoming the foregoing deficiency of toggle linkages having a clevis connection that the present invention is concerned.

Toggle linkage seismic isolation structure


In an apparatus such as an electric coffee-maker, a filter (5) is placed at the bottom of a vessel (3) containing the product to be treated such as ground coffee. Resilient tongues (18) cut in the filter are disposed at uniform intervals about the center so as to form normally-closed orifices (17). When a predetermined pressure of liquid such as hot water is attained within the vessel, the orifices are freed to a sufficient extent to permit filtration of the liquid which has been in contact with the product.

1. Field of the Invention
The present invention relates to a filter for rapid extraction of the aromatic substances of a product by a liquid under pressure.
The present invention also relates to an apparatus equipped with a filter of this type.
2. Description of the Prior Art
There was described in French patent Application No. 2 655 529 in the name of the present Applicant an apparatus for the preparation of beverages by rapid extraction of the drinkable aromatic substances of a product which is subjected to a liquid under pressure. In this apparatus, an injector for liquid under pressure opens into a vessel containing the product to be treated, the bottom wall of the treatment vessel being provided with at least one orifice which cooperates with resilient closure means. The orifice is freed by the closure means at least to a partial extent so that, when a predetermined pressure is attained within the treatment vessel, the extract is permitted to flow through a passageway of sufficiently small width to ensure filtration of the liquid which has been in contact with the product to be treated.
When the aforementioned product is ground coffee which is treated with very hot water under pressure in order to obtain "espresso" coffee, there are carried out in a single step the three operations of extraction of aromatic substances, of filtration of the ground coffee in order to allow only the coffee extract to pass through, and of production of froth which is particularly appreciated by users.
However, the particular means described in this prior patent Application are liable to present certain problems of reliability in time.
The object of the present invention is to overcome the disadvantages of the apparatus described in the foregoing and to propose for this apparatus a filter which makes it possible to carry out the three aforementioned operations in a single step, which is easy to construct and the operation of which is particularly reliable over a period of time.

Filter for rapid extraction of the aromatic substances of a product by a liquid under pressure, and an apparatus equipped with a filter of this type


The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an item of information, and which has a selection switch, which can be driven via the word line, in order to connect a first potential to the bit line via the CBRAM resistance element; a reference resistance cell, which is connected to the bit line and to a reference line and has a reference resistance element, the resistance of which is set to a resistance threshold value, and a reference selection switch, which can be driven via the reference line, in order to connect a second potential to the bit line via the reference resistance element; a read-out unit, which is configured to activate the reference selection switch and the selection switch for the purpose of reading out a memory datum, so that a memory cell current flows via the CBRAM resistance memory cell and a reference current flows via the reference resistance cell onto the bit line; and an evaluation unit, which is connected to the bit line, and which outputs the memory datum in a manner dependent on a resulting electrical quantity assigned to the bit line.

1. Field of the Invention
The invention relates to a memory circuit having resistance memory cells, in particular having conductive bridging random access memory (CBRAM) resistance memory cells. The invention furthermore relates to a method for reading out a memory datum from such a memory circuit.
2. Description of the Related Art
By way of example, memory circuits may have resistance elements as memory cells, the respective resistance value of which resistance elements may be different depending on the information to be stored. In this case, the resistance elements are arranged in a matrix of word lines and bit lines as is generally customary in memory circuits, and the information is determined by applying a voltage to the word line and measuring the resulting current on the bit line. The bit line current determined is compared with a reference value, and the value of the stored datum is determined in accordance with the result of the comparison. Reference resistance elements are usually provided for this purpose, the resistance value of said elements corresponding to a resistance threshold value, whereby a limit between two states to be stored is defined.
Customary resistance elements include CBRAM resistance elements having a solid electrolyte, for which different resistance values may be set by applying a write current in the CBRAM resistance element. Resistance elements of this type are also referred to as PMC resistance elements (programmable metalization cell) in the literature. Such elements, as already described, are preferably read by applying a voltage across the CBRAM resistance element and by determining the resulting current through the CBRAM resistance element with a voltage drop that is kept constant. For comparison with a reference value, provision is made of a reference resistance element having a resistance threshold value. A sense amplifier circuit is preferably provided for the reference resistance element, the sense amplifier circuit being identical to the sense amplifier circuits for the CBRAM resistance elements. The corresponding output quantities of the sense amplifier circuit for the reference resistance element and the CBRAM resistance element are compared with one another. Since one or more reference resistance elements are essentially provided for each bit line present, there is a considerable additional outlay on circuitry in order to generate the comparison quantity dependent on the resistance threshold value of the reference resistance element and to compare it with the electrical quantity dependent on the memory datum stored in the CBRAM memory cell. In addition, various electrical parameters of the respective sense amplifier circuit for the CBRAM memory cells and for the reference resistance elements influence the corresponding electrical quantities, such as, for example, the parameter of the offset of an operational amplifier used in the sense amplifier circuit. The separation between the resistance values for the individual states of the memory datum that are to be stored therefore has to be chosen to have a sufficiently large magnitude.

Memory circuit and method for reading out a memory datum from such a memory circuit


The invention concerns a system for assisting regeneration of pollution management means (1) associated with oxidation catalyst forming means implementing an oxygen storage capacity (OSC) function, and integrated in an exhaust line (3) of a motor vehicle diesel engine (4), wherein the engine is associated with common ramp means (7) supplying fuel to the cylinders thereof. The invention is characterized in that it comprises means (8) for determining the number of incomplete regeneration processes of the pollution management means and for comparing same to predetermined threshold values (10) to control the engine (4) in a first lean mixture regeneration operating mode (11) for a number less than the threshold values or in a second regeneration operating mode of engine operation sequences alternating rich mixture and lean mixture operating phases (12) for a number greater than the threshold values.

The present invention concerns a system for assisting the regeneration of depollution means associated with means forming oxidation catalyst implementing an OSC function constituting an oxygen reserve, integrated in an exhaust line of a motor vehicle diesel engine.
More particularly, the invention relates to such a system in which the engine is associated with common rail means for the supply of fuel to the cylinders thereof.
To ensure the regeneration of depollution means such as a particle filter, the soot trapped therein is burned thanks to the thermal energy provided by the engine and to the exotherm performed by the conversion of the HC and of the CO on means forming oxidation catalyst placed upstream of the particle filter.
This combustion can be assisted by a catalyst element mixed with the soot, coming, for example, from a regeneration assistance additive, mixed with the fuel for the supply of the engine, or by a catalyst deposited directly on the walls of the particle filter (catalyzed particle filter).
The higher the thermal levels in the exhaust line at the inlet of the particle filter, the shorter the duration of the filter regeneration.

System for assisting regeneration of pollution management means in an exhaust line


An image photographing apparatus for automatically focusing a photographed image to improve the image quality. The image photographing apparatus automatically focuses the image through a zoom actuator for changing a zoom ratio and a focus actuator for controlling the focus to thereby enhance the image quality. Also, the image photographing apparatus adds a zooming function to diversify the application fields of image photographing.

The present invention relates to an image photographing apparatus, particularly to an image photographing apparatus having a simple and small structure mounted on a communication terminal.
FIG. 1 is a block diagram explaining the constitution of the conventional image photographing apparatus. As shown in FIG. 1, a mobile phone 100 comprises: a main frame 101; buttons 102 for operating the mobile phone, a screen 103 for displaying telephone numbers or images, and a camera module 104 for photographing images. The interior constitution of the camera module 104 is shown in FIG. 2. That is, the camera module 104 comprises a module case 201, a photographing element 203, a second lens group 206, and a third lens group 207. FIG. 3 is a view separating a photographing optical system 300, which comprises a moiré interference prevention filter 202, the first lens group 205, the second lens group 206 and the third lens group 207, from the camera module 200 to explain the function thereof. The photographing optical system 300 photographs an image of an object positioned on an object surface 301 on an image plane 303. Accordingly, the photographing element 203 is positioned on the image plane 303, and thus an object 302 on the object surface 301 is formed as an image 304 on the image surface 303.
As shown in FIG. 4 showing the conventional constitution, if an object 401 escapes from the object surface 301 and positions near the camera, the image of the object 401 is formed apart from the image surface 303. On the contrary, as shown in FIG. 5, if an object 501 escapes from the object surface 301 and positions far from the camera, the image 501 of the object escapes from the image plane and moves along the direction which is near the photographing optical system 300. As above, if the object escapes from the object surface initially set by the photographing optical system 300, the image of the object also escapes from the image plane 303. Thus, the photographed image is. out of focus and the quality of the photographed image becomes worse.


A method for determining camera module assembling quality is provided. The method includes a step of determining whether the shooting position and the shooting posture of and under-test camera module are correct according to a result of judging whether a relationship between the world coordinate of at least one chart characteristic point of a reference chart and the image coordinate of a corresponding image characteristic point of an image plane coordinate system complies with a standard relationship. Then, the under-test camera module at the correct shooting position and with the correct shooting posture is used to shoot the reference chart. Consequently, an assembling information of the under-test camera module is obtained.

Recently, with the development of electronic industries and the advance of industrial technologies, various electronic devices are designed toward small size, light weightiness and easy portability. Consequently, these electronic devices can be applied to mobile business, entertainment or leisure purposes whenever or wherever the users are. For example, various camera modules are widely used in many kinds of fields such as smart phones, wearable electronic devices or any other appropriate portable electronic devices. Since the electronic devices are small and portable, the users can take the electronic devices to capture images and store the images according to the practical requirements. Alternatively, the images can be uploaded to the internet through mobile networks. In other words, these electronic devices not only have important commercial values but also provide more colorful lives to people.
Generally, the assembling quality of the camera module is one of the most important factors that influence the imaging performance of the camera module. Consequently, the worker in the production line detects the camera module before the camera module leaves the factory. A method of detecting the camera module will be described as follows. Firstly, the under-test camera module is used to shoot a reference chart with a specified pattern. Then, an image analysis is performed on the image of the captured image of the reference chart in order to determine the assembling quality of the camera module. For example, the assembling quality of the camera module is determined according to the result of judging whether there is a tilt angle between a sensing element and a lens of the camera module.
Before the under-test camera module shoots the reference chart, it is necessary to confirm that the under-test camera is at the correct shooting position and with the correct shooting posture. For example, it is necessary to confirm that the distance between the camera module and the reference chart is correct and the camera module is in parallel with the reference chart. According to the conventional technologies, a through focus method, an ISO12233 resolution test method and/or a spatial frequency response (SFR) calculation method are employed. However, the conventional technologies still have some drawbacks. For example, each under-test camera module has to shoot the reference chart many times in order to complete the calibration process. In other words, the calibration process is complicated and lengthy and needs to be improved.

Method for determining camera module assembling quality


A system for managing DLL modules and providing administrators of Windows based PCs with more control over Windows modules. The invention beneficially patches standard Windows API call logic with code that serves to (i) more accurately load the correct DLLs associated with specified applications, (ii) enable multiple DLLs of the same name to be loaded simultaneously where otherwise precluded (such as in a 16-bit Windows environment) and (iii) efficiently track module use and the relationships between modules at run-time.

The present invention relates to dynamic link library modules in a computer system and more particularly to a system for reducing conflicts that arise in loading these modules as required by computer applications.
As described by Jeffrey Richter, "Advanced Windows" (Microsoft Press, 3d ed. 1997), Dynamic link libraries serve as the cornerstone of computer operating systems such as Microsoft Windows and IBM OS/2. A dynamic link library, or DLL, is a computer code module that contains functions to be linked with application code at run time. In contrast to a standard programming library, whose functions are linked into an application when the application's code is compiled, a DLL may be loaded and linked to an application at run time, and then unloaded when no longer needed.
A DLL usually consists of a set of autonomous functions that any application can use.
These function are typically those that the application alone could not handle, such as special dialog box controls. There is usually no support code for processing message loops or creating windows within DLLs. Rather, a DLL is simply a set of source code modules, with each module containing a set of functions. These functions are written with the expectation that an application (EXE file) or another DLL will call them.
In 32-bit Windows operating systems such as Windows NT, Windows 95 and Windows CE, for instance, all of the functions in the Win32 API (application programming interface) are contained in DLLs. These DLLs include, for example, KERNEL32.DLL, which consists of functions for managing memory, processes, and threads; USER32.DLL, which consists of functions for performing user-interface tasks such as window creation and message sending; and GD132.DLL, which consists of functions for drawing graphical images and displaying text.
In the 32-bit Windows environment, for an application or another DLL to call functions contained within a DLL, the DLL's file image must first be mapped, or copied from some data storage device such as a disk drive, into the calling process's address space, by either implicit load-time linking or explicit run-time linking, as discussed more below. Once the DLL's file image is mapped into the calling process's address space, the DLL's functions are available to all the threads running within that process. Another process running at the same time will not have access to the DLL and its functions until the DLL is also mapped into the other process's address space.
In contrast, in the 16-bit Windows environment, when a DLL is loaded, the DLL becomes part of the operating system. The DLL exists in common memory space in order to reduce memory use. Therefore, after the DLL is loaded, any and all of the applications currently running have immediate access to the DLL and its functions.
In any Windows operating system, each module loaded into a process's address space is assigned a unique instance handle or module handle used by the operating system to refer to the module. The actual value of the module handle is the base memory address where the operating system loaded the module into the calling process's address space.
A DLL's file image may be mapped into the address space of a calling thread's process in one of two ways, either implicitly linking to functions in the DLL or explicitly loading the DLL. To implicitly link DLLs, a linker embeds information into the header of the application's EXE file indicating the name of DLLs containing functions that the EXE requires. When the operating system loads an EXE file, the system examines the contents of the EXE file image, such as the header of the EXE module, to determine which DLLs must be loaded for the application to run. The system then attempts to map the required DLL file images into the process's address space. If the system cannot locate the DLL, the system displays an error message and terminates the entire process. With implicit linking, any DLL file images mapped into the process's address space are not unmapped until the process is terminated.
Alternatively, to explicitly link a DLL's file image into a process's address space, one of the process's threads must call the LoadLibrary or LoadLibraryEx function at run-time. These functions locate a file image on the user's system and attempt to map the DLLs' file image into the calling process's address space. If the DLL could not be mapped into the process's address space, the function returns a NULL or other value indicative of an error.
According to existing module load search rules in the Windows operating system, when the system receives a request to load a DLL module, the system first makes one or more preliminary determinations. In the 16-bit Windows environment, the system first determines if a DLL module having the same name as the requested DLL is already loaded into the common memory space. If so, the system completes the load process by returning the handle of the existing module, thereby preventing two modules of the same name from being open at the same time. In addition, in any Windows environment, the system determines if the requested module is fully qualified with path information. If the module is fully qualified, the system attempts to load the module from the associated path. If the module is not qualified, however, the system searches for the module in the following locations:
In the 32-bit Windows Environment:
1. The directory from which the application (EXE image) loaded PA1 2. The process's current directory PA1 3. The Windows system directory PA1 4. The 16-bit Windows system directory (for Windows NT only) PA1 5. The Windows directory PA1 6. The directories listed in the PATH environment variable PA1 1. The current directory PA1 2. The Windows directory PA1 3. The Windows system directory PA1 4. The directory from which the application (EXE image) loaded PA1 5. The directories listed in the PATH environment variable
In the 16-bit Windows Environment:
Unfortunately, this existing module search and load logic is deficient for several reasons. Principally, the existing logic searches for an unqualified module file and may therefore locate and load different versions of the same file at different times. As noted by Windows expert Brian Livingston in the Sep. 2, 9 and 16, 1996 issues of InfoWorld, Microsoft and other vendors provide a number of shared DLLs with their applications, and different versions of these DLLs may have the same name. When a user installs a new application that also uses one of these DLLs, the application may install a version of a DLL that is older or different than the one the other applications support. Because one version of a DLL may not have a programming call that a another version of the same-named DLL supports, conflicts may arise.
For example, Mr. Livingston states that the DLL called "OLE2NLS.DLL" is used by Microsoft Office 4.0, 4.2, 4.2c, 4.3, 4.3c, Microsoft Excell 5.0, 5.0c, Microsoft Word 6.0, 6.0a, 6.0c, Microsoft PowerPoint 4.0, 4.0c, Microsoft Project 4.0, and Microsoft Visual FoxPro 3.0 is Version 2.01. However, according to network analyst Michael Green of Paranet Inc., in Houston, Tex., Microsoft Office 4.3c cannot use OLE2NLS.DLL Version 2.02.
Additionally, the existing module search logic is not versatile. The existing logic may attempt to load a particular DLL module when in fact the application or the end user requires another module to be loaded instead. For example, the "OLE" (object linking and embedding) application includes hard coded DLL paths. However, when running the OLE application, a user may wish to use some other DLL version. Unfortunately, existing module search logic will not permit variance from the hard coded path. As another example, the "ODBC" (open database connectivity) application regularly loads modules twice, once based on a qualified module name and once based on an unqualified name. ODBC will then use the more recent version of the two modules. A user, however, may wish to use the older version module. Again, though, the existing module search logic will not permit this variance.
Still further, in the 16-bit Windows environment, it is often necessary to load multiple versions of the same-name DLL module, in order to enable several different applications to run at once. Therefore, an operating system that prevents two modules of the same name from being open at the same time may give rise to additional conflicts, possibly preventing one of the applications from running.
A need therefore exists for an improved system for managing DLL modules that will overcome the foregoing deficiencies.

System for reducing conflicts among dynamic link library modules by aliasing modules


A method for aperiodic channel status information (CSI) reporting in a wireless access system, and a user equipment (UE) for performing the method are discussed. The method is performed by a user equipment (UE) and includes receiving a radio resource control (RRC) message configuring one or more CSI measurement sets. Each of the one or more CSI measurement sets includes one or more subframes. The method includes receiving a physical downlink control channel (PDCCH) including a CSI request field triggering the aperiodic CSI reporting; and reporting a CSI on a subframe ‘n’. The CSI has been measured on a subframe ‘n-nCQI_ref’. ‘nCQI_ref’ is a value which makes the subframe ‘n-nCQI_ref’ to be included in a valid CSI measurement set which is closest from the subframe ‘n’.

Field of the Invention
The present invention relates to a wireless communication system, and more particularly, to various methods of reporting channel status information to a base station and apparatus for supporting the same.
Discussion of the Related Art
Generally, a wireless communication system is developing to diversely cover a wide range to provide such a communication service as an audio communication service, a data communication service and the like. The wireless communication is a sort of a multiple access system capable of supporting communications with multiple users by sharing available system resources (e.g., bandwidth, transmit power, etc.). For example, the multiple access system may include one of CDMA (code division multiple access) system, FDMA (frequency division multiple access) system, TDMA (time division multiple access) system, OFDMA (orthogonal frequency division multiple access) system, SC-FDMA (single carrier frequency division multiple access) system and the like.
A user equipment periodically can transmit channel status information (CSI) to a base station. Alternatively, if a base station makes a request, the user equipment can aperiodically report CSI to the base station.
In LTE-A system, in case that a CSI reference resource belongs to a CSI measurement set, a user equipment just reports a CSI corresponding to the CSI reference resource to a base station. However, if a CSI reference resource does not belong to any CSI measurement set, it may cause a problem that a CSI to be reported does not exist.

This patent is subject to a terminal disclaimer.

Method and device for aperiodically reporting channel state information in wireless connection system


Method and circuitry for performing a line loop back test includes a receiver, a deserializer, and a low speed parallel loop back data multiplexer selects either the low speed parallel data from the deserializer when in loop back mode or low speed parallel input data when in normal mode. The deserializer produces a low speed clock output signal that is fed to a low speed loop back reference clock multiplexer and also to a low speed loop back clock multiplexer. Both the loop back reference clock multiplexer and the loop back clock multiplexer select the low speed clock output signal from the deserializer when in line loop back mode. A clock multiplying unit converts the output of the low speed loop back reference clock multiplexer into a high speed clock signal. The serializer generates the high speed serial transmitter data in synchronization with the high speed clock signal received from a clock multiplying unit. A clock divider circuit converts the high speed clock signal from the clock multiplying unit into a low speed FIFO output clock. A first-in-first-out buffer receives the low speed parallel output data in synchronization with a clock multiplexer output, and transmits low speed parallel FIFO data to the serializer in synchronization with the low speed FIFO output clock. A low speed parallel loop back data buffer provides coupling between the deserializer and the low speed parallel loop back data multiplexer, and a low speed loop back clock buffer provides coupling between the deserializer and the loop back reference clock multiplexer and the loop back clock multiplexer.

1. Field of the Invention
The present invention pertains to the field of high speed telecommunications transceivers; and specifically, to the field of testing high speed telecommunication links using the transceiver circuitry.
2. Background of the Invention
In many telecommunications applications, line loop-back mode is used to test the serial high-speed link between two locations. A stream of serial bits is sent over the link, fiber optics for example, to a receiver, which sends it directly to the transmitter and sends it back over the link to the original sender. The sender compares the transmitted and received data, and, if they match, the link must be functional. Such loop-back mode typically requires high speed multiplexers and buffers which are not only very difficult to implement, but also consume a great deal of power and degrade jitter performance of the normal mode operation.
FIG. 1 illustrates general line loop back 100 signal flow. A sender (not shown) sends an optical signal 101 over the link 102. The signal 101 is received by the receiver 103 and passed to the transmitter 105 through a line loop back connection 104 between the receiver 103 and transmitter 105. The transmitter 105 sends an equivalent signal 106 back right away through the link 107. The purpose of the general line loop back mode is to be able to test the links 102 and 107 themselves. The testing sender sends signal 101 then compares the looped back signal 106 to the original signal 101. If the sent signal 101 matches the looped back signal 106, then the lines 102 and 107 are functioning properly. A typical implementation for a line loop back test is on an integrated circuit itself having a receiver 103 and a transmitter 105. The receiver 103 receives the optical serial data on its input 108, converts the data to a lower speed parallel form, and then sends the lower speed parallel data through parallel output port 109 to another application specific integrated circuit (not shown) which performs further processing on the parallel data. Typically, either the same or another application specific integrated circuit feeds the transmitter 105 lower speed parallel data through input port 110.
As is apparent from the above discussion, a need exists for a telecommunications circuit suitable for transceivers that provides for cost-effective and efficient implementation of the line loop back test which is not difficult to implement, conserves power, and which does not adversely affect the jitter performance of normal mode transceiver operation.

Line loop back for very high speed application


An inkjet printhead with an array of nozzles and corresponding actuators for ejecting ink through the nozzles, the nozzles being arranged in rows such that the nozzle centres are collinear; wherein,                the nozzle pitch along each row is greater than 1000 nozzles per inch.

The present invention involves the ejection of ink drops by way of forming gas or vapor bubbles in a bubble forming liquid. This principle is generally described in U.S. Pat. No. 3,747,120 (Stemme). Each pixel in the printed image is derived ink drops ejected from one or more ink nozzles. In recent years, inkjet printing has become increasing popular primarily due to its inexpensive and versatile nature. Many different aspects and techniques for inkjet printing are described in detail in the above cross referenced documents.
Nozzle packing density, or the number of nozzles per square mm of printhead, has a bearing on the print resolution and fabrication costs. In view of this, there are ongoing efforts to increase nozzle packing densities.

Abstract: By configuring the components of the unit cell (the repeating chamber, nozzle and actuator unit) such that the overall width of the unit is reduced, the same number of nozzles can be arranged into a single row instead of two staggered and opposing rows without sacrificing any print resolution (d.p.i.). One row of drive circuitry simplifies the CMOS. fabrication and connection to a print engine controller for receiving print data. Alternatively, the unit cell configuration used in the present invention can be arranged into opposing rows that are staggered with respect to each other to effectively double the print resolution—in the case of the preferred embodiment, to 3200 d.p.i.


A method for raising or lowering the fluid level in a chamber in an extracorporeal circuit of a dialysis machine, such as an air trap or compliance chamber, is provided which uses a touch screen. The user of the machine is prompted to indicate on the touch screen the current or actual level of fluid (e.g., blood) in the drip chamber. The user then touches the touch screen to indicate the level, such as by touching an illustration of the chamber at a level corresponding to the actual level. The control system for the machine determines from the level indicated on the touch screen whether the level in the chamber needs to be raised or lowered, and by how much, and responsively operates chamber level adjustment apparatus (such as pressure adjustment apparatus in air communication with the chamber) to raise or lower the level closer to the proper level.

1. Field of the Invention
This invention relates to dialysis machines, and more particularly to hemodialysis machines that have an extracorporeal blood circuit with a chamber that stores a quantity of blood.
2. Description of Related Art
Dialysis machines are used for treating patients with inadequate kidney function. Hemodialysis machines include, among other things, an extracorporeal blood circuit typically comprising an arterial line, a blood pump, a dialyzer and a venous line. Blood is removed from the patient via the arterial line and pumped by the blood pump to the dialyzer, where blood-borne toxins and excess fluids are removed from the patient's blood. The blood is then returned to the patient via the venous line.
Typically, extracorporeal circuits of hemodialysis machines include a blood drip chamber in the venous line which is designed to separate and remove bubbles of air or foam from the blood being returned to the patient. The chamber, sometimes referred to in the art as an "air trap", stores a quantity of blood which is constantly replenished by blood from the dialyzer, as blood is withdrawn from the chamber (typically from the bottom of the chamber) and returned to the patient. It is also common to have blood chambers in the arterial line leading to the dialyzer, especially in single needle dialysis systems.
During the course of the dialysis session, the blood level may rise above or fall below a predetermined or desired level in the chamber (e.g., the middle of the chamber), due to pressure changes in the extracorporeal circuit, changes in the pump rate of the blood pump, accidental occlusion at the blood access site and trapped air in the chamber displacing fluid. Problems can arise if the level goes too high or too low. For example, if the level in the drip chamber becomes too low, excessive foaming may occur or become entrained in the blood. If the level becomes too high, plasma may separate from whole blood and clotting may occur more readily.
In the prior art, adjustment of the level in an air trap was typically accomplished by manually operating valves or pumps that change the level of blood in the chamber, or by manually manipulating up and down buttons on the face of the dialysis machine which control the level adjustment apparatus. For example, the patent to Grogan et al., U.S. Pat. No. 5,326,476, which is incorporated by reference herein, incorporates up and down buttons on the face of the machine that control the operation of arterial and venous valves and a peristaltic pump. The user operates the buttons to raise or lower the level in the chamber.
It has also been proposed to use optical sensors to sense the level of blood chamber and a control system to responsively operate pressure adjustment apparatus to regulate the pressure and hence level in the chamber. See, e.g., the patent to Chevallet et al., U.S. Pat. No. 5,227,048, which is incorporated by reference herein.
The present invention departs from these approaches by using the user interface, and preferably a touch screen, as a way of indicating the current level of blood or other fluid in the air trap and using the central computer system to make adjustments to the level. Touch screen user interfaces are known in the dialysis art, see, for example, the above Grogan et al. patent. The Grogan et al. patent describes using the touch screen to select, enter and confirm certain parametric value changes for the machine. However, the Grogan et al. patent does not recognize the feasibility of using the touch screen to change the level of the drip chamber, and relies on the use of physical buttons on the face of the machine to control the blood chamber level adjustment apparatus.
Usage of the touch screen to adjust the level of a chamber in the extracorporeal circuit has several distinct advantages. First, it consolidates the user's interaction with the machine controls in one location. Second, it avoids the use of the optical sensors (such as described in the above Chevallet et al. patent), and thus is a less costly implementation since no additional hardware is required. Third, the usage of the touch screen and associated hard keys adjacent to the touch screen (described below) allows for backup safety and verification procedures to be implemented in the central computer control system for the machine, particularly where the user interface supplies input signals to a control system comprising host and backup safety central processing units, such as employed in the inventors' preferred embodiment of the invention.
These, and other advantages and features of the invention will become more apparent from the following detailed description of preferred and alternative embodiments of the invention.

Methods and apparatus for adjustment of blood drip chamber of dialysis machines using touchscreen interface


An apparatus for a self-cleaning litter box having a control system for a mechanical self-cleaning mechanism. The litter box has a turret carrying a rake. The box includes an animal sensor that detects the presence of an animal in the box. A specified time after the animal leaves the box, the turret sweeps the rake through the litter, picks up the collected waste, and carries it to a waste bin, where the waste is dumped. The litter box is controlled by a processor executing a software program that monitors the instruments and sensors and controls the turret and rake motors. The software, in various embodiments, controls the rake motor and turret motor to execute a scoop sequence, a startup sequence, and a go home sequence.

1. Field of Invention
This invention pertains to a self-cleaning litter box. More particularly, this invention pertains to a control system for a pet litter box with a mechanical self-cleaning mechanism.
2. Description of the Related Art
Domestic cats kept as pets are usually trained to use a litter box for elimination of both liquid and solid wastes. A cat litter box is normally made of a liquid impermeable material so that a cat's urine will not leak through the box. The box may optionally have a cover. The litter used in these boxes may be one of any number of particulate litter or other materials that absorb moisture from the waste of the cat. The litter material may also suppress odor from cat waste. Some forms of litter form clumps when wet. Usually, a cat will bury its solid waste in the litter material in the box. The litter box requires periodic cleaning to remove the cat's solid waste and the litter that is saturated with urine.
Thus, a number of devices have been proposed for automating cleaning of cat litter boxes. The following patents illustrate the use of motorized cleaning mechanisms. U.S. Pat. No. 5,048,465, titled "Self-cleaning kitty litter box," issued to Carlisi on Sep. 17, 1991, discloses a kitty litter box with a motor, timing device, and a rake. U.S. Pat. No. 5,226,388, titled "Automated cat litter disposal system," issued to McDaniel on Jul. 13, 1993, discloses an automated cat litter disposal system for a cat litter box. U.S. Pat. No. 6,082,302, titled "Self-cleaning litter box," issued to Thaler, et al., on Jul. 4, 2000, discloses a self-cleaning litter box for cats with a comb drive. The litter box is rectangular and the comb moves through the litter until it encounters an obstruction, at which time it stops. The comb has a sensor for sensing contact with any obstruction encountered by the comb as it moves through the box.
U.S. Pat. No. RE36,847, titled "Automated self-cleaning litter box for cats," issued to Waters on Sep. 5, 2000, discloses an automated self-cleaning litter box for cats. The Waters patent describes a system for moving a comb through the litter contained in a rectangular litter box. The system is responsive to entry and exit of the cat from the litter box. In addition, Waters provides an improved disposal receptacle and alarms to report an insufficient litter supply and a fill disposal receptacle.


2-R.sub.2 -R.sub.4 -substitutea-3-R.sub.3 -CO-1-[(C-attached-N-heteryl)(Alk).sub.n ]-1H-indoles useful as analgesic, anti-rheumatic, anti-inflammatory or anti-glaucoma agents.

1. Field of the Invention
This invention relates to 3-arylcarbonyl-1-(C-attached-N-heteryl)-1H-indoles which are useful as analgesic, antirheumatic, anti-inflammatory and antiglaucoma agents.
2. Information Disclosure Statement
It is believed that compounds of the indole series having a nitrogen-containing heterocyclic group attached to the nitrogen atom of the indole either directly through a carbon atom of the heterocycle or through an intervening alkylene group attached to a carbon atom of the heterocycle and having, in addition, any carbonyl-containing function at the 3-position of the indole nucleus are unknown.
3-Arylcarbonyl substituted-1H-indoles having a nitrogen-containing heterocyclic group attached to the 1-position through the nitrogen atom of the heterocycle have been disclosed in the prior art, for example in Deschamps et al. U.S. Pat. No. 3,946,029, which describes compounds useful as fibrinolytic and anti-inflammatory agents, and in Bell U.S. Pat. No. 4,634,776, which discloses compounds useful as analgesic, antirheumatic and anti-inflammatory agents.
Essentially the same disclosure of Deschamps U.S. Pat. No. 3,946,029 is found in Inion et al., Europ. J. of Med. Chem., 10(3), 276-285 (1975). Specifically disclosed in both the Deschamps and Inion et al. references is 2-isopropyl-3-(3-pyridylcarbonyl)-1-[2-(4-morpholinyl)ethyl]indole.
Herbst U.S. Pat. No. 3,489,770 generically discloses compounds having the formula: ##STR1## where, inter alia, R.sub.1 is "diloweralkylamino, pyrrolidinyl, piperidino and morpholino and R.sub.2 is . . . cyclo (lower) alkanoyl and adamantanyl carbonyl". Although not within the ambit of the above-defined genus, the Herbst patent also discloses a variety of species where R.sub.2 is an arylcarbonyl group. Specifically disclosed, for example, is the species "1-p-(chlorobenzoyl)-3-(2-morpholinoethyl)indole". The compounds are said to possess anti-inflammatory, hypotensive, hypoglycemic and CNS activities.
Tambute, Acad. Sci. Comp. Rend., Ser. C, 278(20), 1239-1242 (1974) discloses compounds of the formula: ##STR2## where n is 2 or 3. No utility for the compounds is given.
1-Primary amino-lower-alkyl-3-arylcarbonyl-1H-indoles for which no utility is stated are disclosed by Dalla Croce, Chem. Abst., 80, 95655f (1974).
The prior art also discloses a number of indoles having no substituent at the 3-position and a C-attached heterocyclic alkyl group attached to the 1-position. For example Bosch et al., J. Org. Chem., 48(25), 4836-41 (1983) disclose the species 1-[(1-methyl-4-piperidinyl)methyl-1H-indole; Bosch et al., Tetrahedron, 40(8), 1419-24 (1984) disclose 1-[(1-methyl-2-oxo-4-piperidyl)methyl]-1-indole and 1-[(1-methyl-1,2,5,6-tetrahydro-4-pyridyl)methyl]-1H-indole; and Bennasar et al., Tetrahedron, 42(2), 637-647 (1986) disclose 1-[4-(3-methoxy-1-methyl-1,2,5,6-tetrahydropyridyl) methyl]-1H-indole and 1-[4-(1-methyl-3-oxopiperidyl)methyl]-1H-indole, all useful as intermediates for the preparation of a partial structure of the indole alkaloid vinoxine.
Vartangan et al., Ann. Khim. Zh., 38(5), 308-313 (1985); Chem. Abst. 105, 114874e (1985) disclose compounds of the formula: ##STR3## where R is hydrogen, COOH or COOCH.sub.3, for which no utility is disclosed; Nilsson et al., Acta. Chem. Scand., Ser. B, B39(7), 531-537 (1985) disclose compounds having the formula: ##STR4## where X is O or S and R is hydrogen or methyl which were prepared for circular dichroism studies; and Sasakura et al., Syn. Comm. 18(3), 265-273 (1988) disclose compounds having the formula: ##STR5## where X is hydrogen, chlorine, fluorine or methoxy; Y is hydrogen or fluorine; R is methyl or benzyl and n is 1 or 2 for which no utility is disclosed.