A capacitive sensor sheet producing method for producing a capacitive sensor sheet uses a base having an insulative base layer on which a binder resin layer including conductive nanowires is formed. The conductive nanowires partially projecting from a surface of the binder resin layer. The method includes removing a binder resin from projections of conductive nanowires partially projected from a plurality of detection electrodes by implementing a surface etching and shaping treatment on a surface of the binder resin layer, or surface ends of at least partial detection electrodes of the plurality of detection electrodes, forming wiring lines of the conductive pattern layer, and connecting the wiring lines to the surface ends of at least partial detection electrodes in the pattern layer. The projections of the conductive nanowires removed the binder resin are put into contact with the connecting portions.

A conventional capacitive sensor sheet is assembled as a control means to an automobile-mounted device, including unillustrated first and second bases opposing, and adhering to, each other, the first base being formed with a conductive X-pattern layer, and the second base being formed with a conductive Y-pattern layer, and functions to detect a change of capacitance when a user's finger being a conductor approaches a selected point of the X-pattern layer and/or Y-pattern layer, and output the detection to a control device, to thereby contribute to the operation of the automobile-mounted device (see Patent Documents 1, 2, 3, 4 and 5).
The first and second bases each include an insulative base layer, a binder resin layer including silver nanowires laminated on the surface of the base layer, and are adhered and fixed to each other by an insulative adhesive sheet. The first and second bases each have an elongate tail section at the rear periphery of the base layer, so that these tail sections are connected to the control device.
The binder resin layer of the first base is formed by applying a binder resin solution with silver nanowires dispersed therein, on the surface of the base layer and then drying and curing, forming part of the X-pattern layer. The binder resin layer of the second base is formed by applying a binder resin solution with silver nanowires dispersed therein, on the surface of the base layer and then drying and curing, forming part of the Y-pattern layer.
The X-pattern layer is formed by arranging lines of a plurality of X-detection electrodes that are aligned in one row in the Y-direction on the surface of the base layer of the first base, abreast in the X-direction with a predetermined pitch. Conductive wiring lines are laid over and electrically connected to the surface of the terminal X-detection electrodes among the plurality of X-detection electrodes aligned in the Y-direction. The wiring line is extended to the tail section of the first base and electrically connected to the control device.
Each X-detection electrode is formed in an approximate diamond shape and functions to detect a change of capacitance when a user's finger approaches. The thus configured X-pattern layer is formed with the plurality of X-detection electrodes by etching and shaping the binder resin layer of the first base while the surface of the base layer of the first base is printed with silver paste, and then dried and cured to form a plurality of wiring lines.
The Y-pattern layer is formed by arranging lines of a plurality of Y-detection electrodes that are aligned in one row in the X-direction on the surface of the base layer of the second base, abreast in the Y-direction with a predetermined pitch. Conductive wiring lines are laid over and electrically connected to the surface of the terminal Y-detection electrodes among the plurality of Y-detection electrodes aligned in the X-direction. This wiring line is extended in the tail section via a through-hole and electrically connected to the control device.
Each Y-detection electrode is formed in an approximate diamond shape and detects a change of capacitance when a user's finger approaches. Similarly to the X-pattern layer, the thus configured Y-pattern layer is formed with the plurality of Y-detection electrodes by etching and shaping the binder resin layer of the second base while the surface of the base layer of the second base is printed with silver paste, and then dried and cured to form a plurality of wiring lines.

Capacitive sensor sheet producing method and capacitive sensor sheet


This vehicle control devices provided with: a travel segment determination unit 15 which determines a next travel segment, forwards in the travel direction of the vehicle, which has a different road slope from the current travel segment where the vehicle is currently traveling; a next gear stage selection unit 16 which, on the basis of the road slope of the next travel segment, selects a next gear stage, which will be the gear stage of the vehicle in the next travel segment; and a shift control unit 17 which upshifts to the next gear stage in the current travel segment in the case that the travel resistance in the next travel segment is less than the travel resistance of the current travel segment, the value obtained by subtracting the travel resistance of the vehicle in the current travel segment from the drive force at the current speed of the vehicle in the next gear stage is less than a first prescribed value, and the value obtained by subtracting the travel resistance of the vehicle in the next travel segment from the drive force at the current vehicle speed in the next gear stage is less than a second prescribed value.

There has been proposed a technique for setting a shift schedule to minimize fuel consumption amount on a travel route based on: road information of a travel route from a current position of a vehicle to a target position thereof; and drive force of the vehicle in the travel route (see PTL 1).

Vehicle control device and vehicle control method


A fuel cell system includes a fuel cell that is subjected to a purge operation of supplying an inert gas to an anode and/or cathode upon shut-down of the fuel cell. The differential pressure ΔP is defined as ΔP=Pa−Pc where Pa is the pressure in an inlet-side flow path leading to the anode and Pc is the pressure in an inlet-side flow path leading to the cathode. The differential pressure during the purge operation is controlled such that the differential pressure during operation ΔPo and the differential pressure during the purge operation ΔPp satisfy the relation: 0<ΔPo×ΔPp. This makes it possible to reduce the stress exerted on a solid electrolyte membrane and improve the long-term reliability of the fuel cell.

Fuel cells are basically composed of a pair of electrodes, i.e., anode and cathode, sandwiching an ion-conductive electrolyte, and an anode-side separator and a cathode-side separator sandwiching the electrodes. The anode-side separator has a flow channel for supplying a fuel to the anode, while the cathode-side separator has a flow channel for supplying an oxidant to the cathode. By supplying the anode with a fuel, such as hydrogen gas or ethanol, and supplying the cathode with an oxidant such as oxygen or air, the chemical energy of these reactive substances is converted to electrical energy through oxidation or reduction reaction on the electrodes, to produce current.
A type of fuel cell uses a hydrogen-ion conductive polymer membrane as the electrolyte, uses hydrogen or a mixed gas composed mainly of hydrogen as the fuel, and uses oxygen or gas such as air as the oxidant. In this fuel cell, hydrogen gas is oxidized on the anode in the reaction of formula (1) to produce electrons and hydrogen ions. The hydrogen ions move through the solid electrolyte membrane and reach the cathode side. The electrons move through an external circuit and reach the cathode. The oxygen, the electrons and the hydrogen ions at the cathode are reduced in the reaction of formula (2) to produce water.2H2→4H++4e  (1)4H++O2+4e→2H2O  (2)
The solid polymer membrane that is the electrolyte of this fuel cell exhibits ionic conductivity only when it is hydrated. Thus, in order to maintain the high power generation performance, the water produced by the reaction of formula (2) alone is insufficient, and it is thus necessary to supply water from outside. A common method for supplying water necessary for the operation of a fuel cell is to use a device that is placed inside or outside the fuel cell for humidifying the gas to be supplied to the fuel cell.
Also, the operation temperature of this fuel cell is usually 90° C. or lower, because there are limitations resulting from the heat-resisting performance of the solid polymer membrane serving as the electrolyte. However, since the reactions of formulae (1) and (2) are unlikely to occur in an environment of 90° C. or lower, the anode and cathode need to be equipped with a catalyst that is capable of activating such reaction. Therefore, the anode and cathode of this fuel cell comprise platinum with a high catalytic ability.
An exemplary conventional fuel cell system including this fuel cell is a system that is configured as illustrated in FIG. 1 (see Patent Document 1, for example). That is, this system includes a fuel cell 10 that generates power by reacting hydrogen supplied from hydrogen supply means 11 with oxygen in the humidified air that is supplied from air supply means 12 via a humidifier 13. It includes a pump 16 for circulating cooling water through the fuel cell 10 to collect the heat of electrode reaction, and an inverter 25 for converting the direct current generated by the fuel cell 10 into an alternating current. The cooling water circulated by the pump 16 releases the thermal energy it acquired from the fuel cell at a heat exchanger 19. On the other hand, the water in a hot water reservoir 18 that is circulated by a pump 17 absorbs heat from the heat exchanger 19 and becomes warm water, which is stored in the hot water reservoir 18.
In this conventional system, a flow path 14 leading to a fuel gas inlet 14a of the fuel cell 10 and a flow path 15 leading to an air inlet 15a are provided with three-way valves 21 and 22, respectively. When the operation of the fuel cell 10 is shut down, an inert gas is supplied to the fuel gas flow path and the air flow path from an inert gas cylinder 20. 14b represents a fuel gas outlet, and 15b denotes an air outlet.
In order for such a fuel cell system as the above example to efficiently utilize the chemical energy of the fuel gas, there is a need to change the output of the operation or repeatedly start up and shut down the system according to the demand for power it supplies. However, in starting up and shutting down the fuel cell which is a power generation source, the following problems arise, so the gas supplied to one or both of the anode and the cathode needs to be replaced, i.e., purged, with an inert gas.
First, in terms of safety, a problem associated with the start-up and shut-down is that hydrogen gas needs to be removed from the fuel cell during shut-down. The reason is that since the solid polymer membrane separating the anode from the cathode is permeable to oxygen gas and hydrogen gas, hydrogen and oxygen become mixed together if the shut-down of operation of the fuel cell is maintained for an extended period of time.
Second, in terms of power generation efficiency, oxygen gas in the cathode needs to be removed. The reason is as follows. When oxygen is present in the cathode at the time of no load, the cathode has a potential of approximately 1 V relative to the potential of the standard hydrogen electrode. This potential causes oxidation reaction or dissolution reaction of platinum serving as the electrode catalyst, thereby lowering the catalyzing ability of the electrode.
Third, in terms of start-up stability, water vapor in the anode and cathode needs to be removed. The reason is as follows. The gas inside the fuel cell has a relative humidity close to 100% at the temperature during operation, because of the combination of the humidified gas supplied to the fuel cell and the water produced in the reaction of formula (2). Although the operation temperature of the fuel cell is normally 60° C. to 80° C., the gas remaining in the fuel cell during the shut-down of the fuel cell is cooled to room temperature. Thus, the moisture in the gas condenses into water. When the fuel cell is started up, the temperature of the fuel cell is low, so the condensed water remains in liquid form in the cell. The condensed water covers the platinum surface, clogs the pores of the porous gas diffusion layer, and closes the gas flow channel of the separator, so that the gas diffusion is hampered, thereby resulting in unstable power generation upon start-up.
With respect to the purge method for solving these problems, the most common method is shown in FIG. 1. That is, the system is equipped with the cylinder 20 of an inert gas such as nitrogen gas, and when the fuel cell is shut down, the inert gas is supplied through the flow path 14 leading to the fuel gas inlet 14a of the fuel cell 10 and the flow path 15 leading to the air inlet 15a, using the pressure of the cylinder as the driving power. Other methods that have been proposed so far include a method of purging with cooling water (e.g., Patent Document 2), a method of removing oxygen from the cathode exhaust gas and resupplying it to the fuel cell (e.g., Patent Document 3), and a method of burning the fuel hydrogen and air and then supplying it to the fuel cell (e.g., Patent Document 4).
Patent Document 1: Japanese Laid-Open Patent Publication No. Hei 11-214025
Patent Document 2: Japanese Laid-Open Patent Publication No. Hei 06-251788
Patent Document 3: Japanese Laid-Open Patent Publication No. Hei 06-203865
Patent Document 4: Japanese Laid-Open Patent Publication No. 2002-50372

Fuel cell system with differential pressure control


An apparatus and method for forming a circularly or substantially circularly shaped pocket between layers of a live cornea, and then, expanding the pocket to form a flap-like layer at the front of the live cornea which is pivotally attached to the remainder of the cornea by a flap connecting section. The cutting tool of the apparatus preferably has a circular or substantially circular cutting portion which is inserted into the cornea and reciprocated to form the pocket. Suction is applied to the front surface of the cornea to stabilize the cornea during the pocket forming process.

1. Field of the Invention
The present invention relates to an internal keratome apparatus and method of using the same to form a pocket between layers of a live cornea More particularly, the present invention relates to an internal keratome apparatus having a circularly-shaped reciprocating blade, and a method for using the same to form a circularly-shaped pocket between layers of a live cornea, and then expanding the pocket to form a flap-like layer at the front surface of the live cornea.
2. Description of the Related Art:
A normal ametropic eye includes a cornea, lens and retina. The cornea and lens of a normal eye cooperatively focus light entering the eye from a far point, i.e., infinity, onto the retina. However, an eye can have a disorder known as ametropia, which is the inability of the lens and cornea to focus the far point correctly on the retina. Typical types of ametropia are myopia, hypermetropia or hyperopia, and astigmatism.
A myopic eye has either an axial length that is longer than that of a normal ametropic eye, or a cornea or lens having a refractive power stronger than that of the cornea and lens of an ametropic eye. This stronger refractive power causes the far point to be projected in front of the retina.
Conversely, a hypermetropic or hyperopic eye has an axial lens shorter than that of a normal ametropic eye, or a lens or cornea having a refractive power less than that of a lens and cornea of an ametropic eye. This lesser refractive power causes the far point to be focused on the back of the retina.
An eye suffering from astigmatism has a defect in the lens or shape of the cornea. Therefore, an astigmatic eye is incapable of sharply focusing images on the retina.
In order to compensate for the above deficiencies, a technique known as photorefractive keratectomy has been developed which involves the placement of lenses in front of the eye (for example, in the form of glasses or contact lenses). However, this technique is often ineffective in correcting severe vision disorders.
An alternative to photorefractive keratectomy is surgery. For example, in a technique known as myopic keratomileucis, a microkeratome is used to cut away a portion of the front of the live cornea from the main section of the live cornea. That cut portion of the cornea is then frozen and placed in a cyrolathe where it is cut and reshaped. Altering the shape of the cut portion of the cornea changes the refractive power of this cut portion, which thus effects the location at which light entering the cut portion of the cornea is focused. The reshaped cut portion of the cornea is then reattached to the main portion of the live cornea. Hence, this reshaped cornea will change the position at which the light entering the eye through the cut portion is focused, so that the light is focused more precisely on the retina, thus remedying the ametropic condition.
Keratophakia is another known surgical technique for correcting severe ametropic conditions of the eye by altering the shape of the eye's cornea In this technique, an artificial organic or synthetic lens is implanted inside the cornea to thereby alter the shape of the cornea and thus change its refractive power. Accordingly, as with the myopic keratomileucis technique, it is desirable that the shape of the cornea be altered to a degree which enables light entering the eye to be focused correctly on the retina.
Laser in situ keratomileusis (LASIK), as described, for example, in U.S. Pat. No. 4,840,175 to Peyman, the entire contents of which is incorporated herein by reference, is a further known surgical technique for correcting severe ametropic conditions of the eye by altering the shape of the eye's cornea. In the LASIK technique, a motorized blade is used to separate a thin layer of the front of the cornea from the remainder of the cornea in the form of a flap. The flap portion of cornea is lifted to expose an inner surface of the cornea. The exposed inner surface of the cornea is irradiated with laser light and thus reshaped by the laser light. The flap portion of the cornea is then repositioned over the reshaped portion and allowed to heal.
In all of these techniques, it is critical that the incisions are made in the cornea in a very precise manner. Otherwise, the vision may not be corrected properly, and worse, severe damage to the eye may occur.
Accordingly, it is necessary that the cornea be prevented from moving while the cutting or separating of the corneal layers is being performed. Also, it is necessary to flatten out the front portion of the cornea when the corneal layers are being separated or cut so that the separation or cut between the layers can be made at a uniform distance from the front surface of the cornea. Previous techniques for flatting out the front surface of the cornea involve applying pressure to the front surface of the cornea with an instrument such as a flat plate. However, these techniques can cause damage to the eye, in particular, the pressure can cause fluid to leak out of the eye.
In addition to stabilizing the cornea when the cutting or separating is being performed, the cutting tool must be accurately guided to the exact area at which the cornea is to be cut. Also, the cutting tool must be capable of separating layers of the cornea without damaging those layers or the surrounding layers.
Furthermore, when the keratophakia technique is being performed, it is desirable to separate the front layer from the live cornea so that the front layer becomes a flap-like layer that is pivotally attached to the remainder of the cornea and which can be pivoted to expose an interior layer of the live cornea on which the implant can be positioned. It is therefore necessary that the cutting tool be accurately guided to form a suitable flaplike layer without damaging the surface onto which the implant is to be positioned. It is also necessary that the angle of the cutting is controlled so that the surface of the exposed interior layer is at a desired angle (e.g., normal) with respect to the optical axis of the eye.
Additionally, because the epithelium cells which are present on the surface of the live cornea may become attached to the blade when the blade is being inserted into the live cornea and thus become lodged between the layers of the live cornea, thereby clouding the vision of the eye, it is desirable to remove the epithelium cells prior to performing the cutting.
Examples of known apparatuses for cutting incisions in the cornea are described in U.S. Pat. No.: 4,298,004 to Schachar et al., U.S. Pat. No. 5,215,104 to Steinert, and U.S. Pat. No. 4,903,695 to Warner, the entire contents of which are incorporated herein by reference.
However, a continuing need exists for an improved apparatus and method for cutting a precise incision into a live cornea. A continuing need also exists for an effective and simple method of removing the epithelium cells from the surface of the live cornea prior to inserting a cutting tool into the live cornea.

Internal keratome apparatus and method for using the same to form a pocket/flap between layers of a live cornea


Implants, tools and techniques facilitate a percutaneous posterior lateral approach to the placement of an in-situ cage, and an inventive cage design to meet this objective. In terms of apparatus, the invention includes a laterally expandable cage, including a locking gate, enabling the system to be introduced into an intradiscal space through a minimally invasive percutaneous posteo-lateral approach. In addition to the cage designs, adapted to hold bone graft and/or other biologic materials, the invention includes other novel instruments, including an introducer associated with cage placement, deployment and closure.

One of the most common causes of chronic back pain is degenerative disc disease. The degeneration may start after a particular injury, or many occur due to multiple injuries over time. Degeneration usually takes several years. As the vertebrae grow closer, the openings in the back of the spine where the nerve roots leave the spinal canal become narrower. This can lead to pinching and irritation on the nerves, causing pain.
There are many surgical approaches and methods used to fuse the spine. Most involve the placement of a bone graft between the vertebrae. Supplemental hardware, such as plates, screws and cages may or may not be used, depending upon the indication.
An early cage design is described in U.S. Pat. No. 4,501,269 to Bagby, entitled "PROCESS FOR FUSING BONE JOINTS." According to the method, a hole is bored transversely across the joint and a slightly larger cylindrical basket is driven into the hole, thereby spreading the bones in resistance to the tensile forces of the surrounding tissue. Immediate stabilization of the joint is achieved by the implantation of the rigid cylindrical basket. Subsequent bone-to-bone fusion is achieved, both through and about the basket, which is filled with bone fragments produced during the boring step.
The Bagby patent states that the process is applicable to any human or animal joint formed by opposed contiguous bony surfaces which are covered and separated by intervening cartilage and are surrounded by ligaments which resist expansion of the joint. Specific examples of such joints are a spinal joint between adjacent vertebrae or the ankle joint.
This stand-alone interbody fusion technique continued to evolve with material changes and the design of threaded cages to increase stability and decrease displacement rates. Bilateral, parallel implants were designed for use in the lumbar spine, with the first human implantation occurring in the early 1009s. The cylindrical titanium cages were threaded to screw into the endplates, thereby stabilizing the device and allowing for increased fusion rate with a stand-alone anterior device.
Ray and colleagues developed a similar titanium interbody fusion device which was initially used in posterior lumbar interbody fusions (PLIF), but expanded to include ALIF procedures (anterior lumbar interbody fusions). In 1985, Otero-Vich reported using threaded bone dowels for anterior cervical arthrodesis, and femoral ring allograft bone has subsequently been fashioned into cylindrical threaded dowels for lumbar application.
Currently, there are a wide number of available interbody fusion devices of varying design and material, including:
1) Cylindrical threaded titanium interbody cages;
2) Cylindrical threaded cortical bone dowels; and
3) Vertical interbody rings, boxes and wedges.
A typical intervertebral fusion cage is a large, hollow cylinder made of some type of metal, usually titanium. It is designed as a "cage" so that bone graft can be placed inside the hollow cylinder. Holes throughout the cage allow bone to form around and through the cage to allow a spinal fusion to occur between two vertebrae. Many of the newer types of intervertebral fusion cages are also designed to facilitate an open incision or a laproscopic procedure.
An intervertebral fusion cage serves a couple important purposes. First, it distracts the vertebrae, making more room for the nerves, thereby decreasing pinching and irritation. The strong ligaments that surround the disc are also tightened, which decreases the segmental instability between the two vertebrae and decreases the mechanical pain in the spine. The cage also hold the two vertebrae in the correct position until a fusion occurs.
There are several drawbacks with existing approaches and techniques, such that further research and improved designs are desirable. Increased morbidity of anterior in-situ cage placement is not justified when less anatomic correction of the disc space is possible. Additionally, current PLIF and transverse lumbar interbody fusions (TLIF) cage and allograft placements require large dissections for exposure. PLIF and TLIF approaches also weaken existing posterior elements via bony destruction resulting from the operative procedure used to access the disc space.
My co-pending U.S. patent application Ser. No. 10/462,498, incorporated herein by reference, improves upon existing solutions by providing a spinal fusion system including a cage with a fillable volume and removable locking gate. This enables the fillable volume to be packed with graft, biologic or other materials prior to the gate being closed and locked. In the preferred embodiment, the locking gate is positioned anteriorally, though lateral, posterior, and combinations thereof are also possible.

Percutaneous posterior lateral in-situ cage


A thin-film transistor has a channel having a plurality of branch channels, and a gate having a plurality of branch gates. At least one of or all of the branch channels are surrounded by the branch gates in a three dimensional way. That is, the branch channels and the branch gates are formed so as to intersect each other in a three-dimensional space so that the branch channels are surrounded by the branch gates, and the branch gates are surrounded by the branch charnels. Consequently, the area of the channel is increased and the current capacity is enhanced. Thus, a thin-film transistor is obtained which takes a small area and has a large current capacity.

1. Field of the Invention
The present invention relates to a semiconductor device formed by a semiconductor thin film, and a method of fabricating such a semiconductor device.
2. Background Art
A polysilicon thin-film transistor (hereinafter referred to as TFT) is employed as a load element in a low-power SRAM. The TFT must take a small area and have a large current capacity to form an SRAM having an improved ability and a high degree of integration. The conventional gate all around TFT with a gate electrode wound around a channel polysilicon film has current capacity twice that of a single-gate TFT having the same area.
FIGS. 49 to 51 show a conventional polysilicon thin film transistor. FIG. 49 is a perspective view of the thin-film transistor, FIG. 50 is a sectional view taken on line A-A' in FIG. 49, and FIG. 51 is a sectional view taken on line B-B' in FIG. 49.
Shown in FIGS. 49 to 51 are a silicon substrate 1, a silicon dioxide film 2 formed on a surface of the silicon substrate 1, a channel polysilicon film 6 serving as the channel of a thin-film transistor, a silicon dioxide film 7 formed over the surface of the polysilicon film 6 and the surface of the silicon dioxide film 2, and a gate polysilicon film 8 serving as the gate of the thin-film transistor. The silicon dioxide film 7 between the channel polysilicon film 6 and the gate polysilicon film 8 serves as the gate oxide film of the thin-film transistor.
In this thin-film transistor, the gate 8 consists of a bottom branch gate 8a formed on a surface of an insulating film, and a branch gate 8b branching from the bottom branch gate 8a, extending over the bottom branch gate 8a and having through holes extending therebetween.
The channel 6 is formed so as to branch from one side of the branch gates 8a and 8b, i.e., from one side of the through hole of the gate 8, and pass the through hole of the gate 8.
A gate oxide film 7 is formed between the channel 6, and the branch gates 8a and 8b.
A source/drain region, not shown, is connected to the channel 6 on the sides of the branch gates 8a and 8b, i.e., on the opposite sides of the through hole of the gate 8.
FIGS. 52 to 56 are views for explaining a method of fabricating the foregoing conventional semiconductor device. The conventional semiconductor device fabricating method will be described with reference to FIGS. 52 to 56.
Referring to FIG. 52, a silicon dioxide film 2 of a predetermined thicknesses formed on a silicon substrate 1 by, for example, a thermal oxidation process. A silicon nitride film 3 of a predetermined thickness is deposited by, for example, a reduced pressure CVD process. Then, the silicon nitride film is patterned in a strip of a width corresponding to that of the channel of a desired 5 transistor.
Referring to FIG. 53, polysilicon is deposited over the surface of the workpiece to form a channel silicon film 6. Polysilicon not containing any impurity is deposited in a polysilicon film of a predetermined thickness, and the polysilicon film is patterned by a photolithographic etching process to form the channel silicon film 6 of a desired pattern.
Then, as shown in FIG. 54, the silicon nitride film 3 is removed entirely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150.degree. C. Consequently, an opening is formed in the channel silicon film 6.
Referring to FIG. 55, a gate silicon dioxide film 7 of a predetermined thickness, i.e., a gate insulating film, is deposited over the entire surface of the workpiece so as to cover a first silicon dioxide film 1 and the channel silicon film 6 entirely.
Referring to FIG. 56, a gate polysilicon film 8 doped with phosphorus (i.e. doped polysilicon film) is deposited in a predetermined thickness over the entire surface of the workpiece by a reduced pressure CVD process. The opening formed in the channel silicon film 6 is filled up with the second polysilicon film 8 because the film deposited by the reduced pressure CVD process has an excellent coverage.
Referring to FIGS. 49 to 51, the gate polysilicon film 8 is patterned by a photolithographic etching process in a desired pattern to form a gate electrode.
Then, source/drain implantation is carried out for end portions of the channel silicon film 6 by using the gate electrode 8 superposed on the channel silicon film 6 as a mask. An interlayer insulating film is formed, and wiring lines, such as aluminum lines, are formed so as to extend from the source/drain region to complete a 10 desired transistor, although not shown.
The foregoing gate all around TFT,having the gate electrode wound around the channel polysilicon film has a current capacity twice that of a single-gate TFT taking the same area. If the degree of integration of a low power SRAM increases, a TFT having a smaller area and a greater current capacity is required. However, the conventional TFT is unable to comply satisfactorily with such a request.

Thin film transistor having a branched gate and channel


A system collaboratively and autonomously plans and controls a team of vehicles having subsystems within an environment. The system includes a mission management component, a communication component, a payload controller component, and an automatic target recognition component. The mission management component plans and executes a mission plan of the team and plans and executes tasks of the vehicles. The communication component plans communication and networking for the team. The communication component manages quality of service for the team. The communication component directs communication subsystems for the team and for the vehicles. The payload controller component directs and executes sensor subsystems for the team and for the vehicles. The automatic target recognition component processes and fuses information from the sensor subsystems and from the vehicles for use by the mission management component.

Conventionally, remote stations control unmanned vehicles. These unmanned vehicles may be self-controlling, or autonomous. Conventional unmanned systems may extend the vision and the reach of a Warfighter. However, the Warfighter may spend so much time managing these assets that the Warfighter may lose effectiveness as a Warfighter.
Autonomy can relieve a Warfighter of this burden. By limiting the required role of a Warfighter from command and control to command only, an unmanned system may move from force extension to force expansion. Collaboration may further move an unmanned system from force expansion to force multiplication. This may allow a Warfighter to perform his duties more effectively, more successfully, and more decisively.
However, an autonomous system may face increasing challenges in control techniques. An autonomous system must be aware of the environment and adapt plans based on changes in understanding of the environment. Control, therefore, ideally is flexible, both in development and in execution.
An autonomous system is given objectives to be achieved. These objectives may be as simple as monitor state and report problems, or complex, for example, assault and capture a target area. Also, a system may be given constraints, such as flight corridors, acceptable risks, or authorized targets. A challenge may then be to integrate these objectives and constraints with environmental state and system state to plan and execute a mission plan in order to achieve the input objectives without violating the constraints.
Furthermore, an autonomous system may itself consist of autonomous systems. Thus, the autonomy may also coordinate multiple autonomous systems to act in concert. The team of unmanned vehicles may have access to assets external to the autonomous team that would aid in performance of the mission. These assets should also be used in concert with the autonomous team.
Conventional systems focus on individual autonomy, ignoring an important facet of collaborative autonomy. Conventional systems are also monolithic insofar as a single control system performs all functions required. Conventional systems thus fail to recognize different disciplines needed to perform the various functions. For example, the conventional system requires awareness of its environment. This requires inferences and estimations of probabilities in a data rich environment. This is different from planning, which takes the estimate of the environment and attempts to optimize courses of actions that effect change to the environment.

System for intelligently controlling a team of vehicles


A computer-implemented method of dynamically selecting and presenting a webpage includes: receiving a request, at a server, from a client device to display a webpage; determining, at the server, a homepage defined by a user of the client device; accessing, at the server, a list of one or more webpages associated with the user; selecting a chosen webpage from the homepage and the list of one or more webpages; and facilitating the display of the chosen webpage on the client device.

These days, there is an abundance of information available on the World Wide Web (hereinafter "Web"). However, if a user does not know about a website or that certain information may be available on the Web, the user may not be able to access that website or be presented with information that they may be interested in. The terms website and webpage are used interchangeably throughout this document.
Additionally, since the advent of the Web, web browsers (hereinafter "browser") such as NETSCAPE or INTERNET EXPLORER have presented users with a default page that loads when the browser is first launched. Most browsers, however, allow users to change their default homepage. If users change their homepage at all, they typically set their homepage either to a search engine, such as google.com, or to a content portal, such as yahoo.com or msn.com. Search engine homepages, however, often have static content, i.e. the user is presented with the same homepage each time the browser is launched, while content portals provide overly generalized content that is selected by the content provider. Accordingly, being presented with the same homepage each time that the user launches their browser does not expose the user to a variety of websites that they may otherwise be interested in viewing.
In recent years, services have emerged that allow users to personalize their homepage. These services, such as MY YAHOO and NETVIBES, aggregate content from a wide variety of sources and present this content in a modular fashion within a personalized homepage. While these personalized homepages present dynamic content, they do not present dynamic user experiences, as the content may change but the format and website remain the same. For example, while users can view the latest news feeds, blogs, weather, and other items, but does not experience new websites or content as its publisher intended.
Furthermore, even the earliest browsers had the ability to store a user's favorite links, called favorites or bookmarks. A major expansion on this has been the advent of bookmarking websites such as DEL.ICIO.US and FURL. These services began as ways for users to store their bookmarks with an online service so that those bookmarks could be accessed from any computer. This model quickly involved into what has become known as social bookmarking, which allows users to easily share bookmarks with one another. Typically a user can browse another user's bookmarks either by invitation or by public access, and if the user likes the description of a link, the user can select that link to view a webpage associated with the link. Similarly, users can access their own bookmarks stored on the online service. However, there are many situations where it would be desirable to have a simplified and streamlined process for accessing either one's own bookmarks or the shared bookmarks of others. For example, if a user would like to access a random link within her company's collection of "competitor companies" bookmarks, there currently isn't an easy way to do so. Alternatively, a user might want to simply select an icon or button to access the next sequential web page within a set of bookmarks.
As such, it would be highly desirable to address the above drawbacks while providing a more dynamic and personalized experience for Internet users.

System and method for selecting and displaying webpages


To provide a dynamic semiconductor memory device wherein it is possible to perform a reliable redundancy relief with a small layout area and high redundancy relieving rate while properly dealing with the standby current fault caused by a short-circuit defect between a bit line and word line. A common current-limiting element is provided for an equalizer circuit for a bit line pair on one side and another equalizer circuit for another bit line pair on the other side in a shared sense amplifier, and a bit line precharge potential is supplied to the equalizer circuits on the both sides through the current-limiting element.

In a conventional DRAM, redundant cells are provided in order to improve manufacturing yield, therefore, even when a defect occurs in a part of normal memory cells, by relieving and replacing the defective cells with redundant cells, the device can be made non-defective. The replacement with redundant cells is performed by programming such as cutting the fuses according to the addresses with a write/read fault during a preliminary test in the wafer state. First, a typical example of an array configuration of a DRAM with the function of replacing a defective cell with a redundant cell is explained with reference to FIG. 1. FIG. 1 shows an overall array configuration of an embodiment where the present invention is applied, however, this will be explained first for the understanding of the invention technology.
In reference to FIG. 1, memory plates 7 are composed of a memory cell group N7, which is a group of normal cells, and an R memory cell group R7, which is a group of column redundancy cells, and provided plurally, arranged in a matrix form of row number 0 through M and column number 0 through N. The memory plates 7 and word line drivers (sub-word line drivers) SWD 12 are provided alternately in the column direction.
Sense amplifiers 6 are composed of SAN 6, which are sense amplifiers controlling the memory cell group N7, and SAR 6, which are sense amplifiers for the column redundant cells, controlling the R memory cell group R7.
The memory plates 7 and sense amplifiers 6 are provided alternately in the row direction. A sense amplifier sandwiched by the memory plates 7, for example the sense amplifier 6, which is sandwiched by the memory plates 7 on row number 0 and row number 1 in FIG. 1, controls both of the memory plates, the one on row number 0 (on the left side in FIG. 1) and one on row number 1 (on the right side in the drawing).
Such a sense amplifier configuration that controls the memory plates on both left and right sides is called shared sense amplifier.
Further, X decoders XDEC 14 are provided below the array configuration in FIG. 1, and Y decoders YDEC 13 are provided on the left side of the array configuration. The YDEC 13 comprises a YDEC N13 that outputs multiple row selecting signal lines YSW 0, YSW 1, etc. controlling a sense amplifier N 6 for the normal cells, and a RYDEC R13 that outputs a row selecting signal line RYSW controlling a sense amplifier R6 for the column redundancy cells.
In FIG. 1, only the row selecting signal lines YSW0, YSW1, etc and the RYSW on row number 0 are shown, however, these are similarly provided in row numbers 1 through N as well. Also, in the array configuration example shown in FIG. 1, only a column redundancy architecture that performs the replacement in the column direction is shown, however, a row redundancy architecture that performs the replacement in the row direction is also provided in a conventional configuration.
FIG. 6 is a drawing showing an example of a conventional circuit configuration of the shared sense amplifiers sandwiched by 2 memory plates 7 out of the sense amplifiers 6 shown in FIG. 1.
In reference to FIG. 6, to the left of a shared sense amplifier 60 (which corresponds to 6 in FIG. 1), a memory cell group N7L, a group of normal cells, and an R memory cell group R7L, a group of column redundancy cells, are provided and to the right, a memory cell group N7R, a group of normal cells, and an R memory cell group R7R, a group of column redundancy cells, are provided.
In the memory cell group N7L, multiple bit lines such as a pair of bit lines BL0LT and BL0LN, and another pair of bit lines BL1LT and BL1LN are provided, and multiple memory cells 8 are connected to each bit line. The memory cell group N7R, memory cell group R7L, and R7R have the same configuration.
The memory cell 8 is comprised of a cell capacitor and cell transistor formed with NMOS transistors. One side electrode of the cell capacitor is connected to a capacitor plate to which a voltage VP is supplied, and the other side electrode of the cell capacitor is connected to one of electrodes of the cell transistor. Furthermore, the other electrode of the cell transistor is connected to a bit line and the gate is connected to a word line.
A sense amplifier circuit 60 comprises equalizer circuits 1L and 1R on its left and right, shared switches 2L and 2R, an NMOS sense circuit 3, a PMOS sense circuit 4, and an IO switch 5, and controls the two bit line pairs, the bit line pair BL0LT and BL0LN on the left and the bit line pair BL0RT and BL0RN on the right. Sense amplifier circuits 61, 62, 63, . . . and R60, R61 have the same circuit configuration.
The equalizer circuit 1L comprises three NMOS transistors: an NMOS transistor whose electrode (either the source or drain electrode) is connected to the bit line BL0LT and other electrode (either the source or drain electrode) is connected to the bit line BL0LN, an NMOS transistor whose electrode is connected to the bit lineBL0LT and other electrode is connected to a bit line precharge power supply VHB, and an NMOS transistor whose electrode is connected to the bit line BL0LN and other electrode is connected to the a bit line precharge power supply VHB, and, to the gates of these three NMOS transistors, a control signal EQL is connected in common. When the control signal EQL is brought to a high level, the NMOS transistors of the equalizer circuit 1L are turned on and the bit lines BL0LT and BL0LN are precharged to the precharge power supply VHB. Like the equalizer circuit 1L, the equalizer circuit 1R comprises three NMOS transistors and a control signal EQR is connected in common to the gates of the three NMOS transistors.
The shared switch 2L comprises two NMOS transistors: an NMOS transistor whose electrode is connected to the bit line BL0LT and other electrode is connected to a sense amplifier circuit node SL0T, and an NMOS transistor whose electrode is connected to the bit line BL0LN and other electrode is connected to a sense amplifier circuit node SL0N, and a control signal SHL is connected in common to the gates of these two NMOS transistors. A shared switch 2R on the right has the same circuit configuration and a control signal SHR is connected in common to the gates of its two NMOS transistors. When each of the control signals SHL and SHR is brought to a high level, each of the shared switches 2L and 2R is turned on, the bit line pair BL0LT and BL0LN on the left and the bit line pair BL0RT and BL0RN on the right become electrically connected to the sense circuits (the NMOS sense circuit 3 and PMOS sense circuit 4).
The NMOS sense circuit 3 comprises two NMOS transistors: an NMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T, other electrode is connected to a sense signal SAN and gate is connected to the sense amplifier circuit node SL0N, and an NMOS transistor whose electrode is connected to the SL0N, other electrode is connected to the SAN and gate is connected to the SL0T.
The PMOS sense circuit 4 comprises two PMOS transistors: an PMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T, other electrode is connected to a sense signal SAP and gate is connected to the sense amplifier circuit node SL0N, and an PMOS transistor whose electrode is connected to the node SL0N, other electrode is connected to the SAP and gate is connected to the SL0T.
The IO switch 5 comprises two NMOS transistors: an NMOS transistor whose electrode is connected to the SL0T, other electrode is connected to one of multiple IO lines and gate is connected to the row selecting signal line YSW0, and an NMOS transistor whose electrode is connected to the SL0N, other electrode is connected to another line of the multiple IO lines and gate is connected to the row selecting signal line YSW0.
In the configuration shown in FIG. 6, one row selecting signal line controls two sense amplifier circuits. In other words, the row selecting signal line YSW0 is inputted into the sense amplifier circuit 60 and a sense amplifier circuit 61, and into the gates of 4 NMOS transistors within the IO switch circuit. In this case, four IO lines are provided, and the other electrodes of the four NMOS transistors, which constitute the IO switch circuit and have the common row selecting signal line connected to its gates, are connected to separate IO lines.
With this example of a circuit configuration, when the row selecting signal line YSW0 is activated according to the address inputted externally, two sense amplifier circuits, the sense amplifier circuit 60 and sense amplifier circuit 61, can be written or read simultaneously.
As another example, there is a case where one row selecting signal line is inputted into one sense amplifier circuit. In this case, two IO lines are provided and by activating one row selecting signal line, the write or read operation of one sense amplifier circuit will start.
As a further example, there is a case where one row selecting signal line is inputted into four sense amplifier circuits, and in this case, eight IO lines are provided, and by activating one row selecting signal line, four sense amplifier circuits can be written or read simultaneously.
When a write/read fault occurs in a cell within the memory cell group N7L, which is a normal cell group on the left of the sense amplifier shown in FIG. 6, it is replaced with a redundant cell. For example, if a write/read fault occurs in a memory cell connected to the bit line BL0LN, a memory cell group 10 connected to 2 pairs of bit lines BL0LT, BL0LN and BL1LT, BL1LN, a total of four bit lines, is replaced with the column redundancy cell group R7L as a set.
In other words, a memory cell group controlled commonly by the row selecting signal line YSW0 and within the memory cell group N7L is replaced as a set. It is because of the necessity to replace sense amplifier circuits, which is written or read by one selecting signal line, as a set.
In the case where one row selecting signal line is inputted into one sense amplifier circuit, a pair of bit lines is replaced as a set.
Furthermore, in the case where one row selecting signal line is inputted into four sense amplifier circuits, eight bit lines are replaced as a set.
Furthermore, only one row selecting signal line RYSW for the column redundancy cells is shown in FIGS. 1 and 6, however, there is a case where multiple row selecting signal lines for the column redundancy cells are provided so that multiple faults can be relieved.
The shared sense amplifier shown in FIG. 6 is constituted such that the memory cell group 10, which corresponds to the row selecting signal line YSW0, is replaced by the column redundancy cells R7L of the row selecting signal line RYSW on the left side, and a memory cell group 11, which corresponds to the row selecting signal line YSW1, is replaced by the column redundancy cells R7R on the right side. In other words, this is a method in which a memory plate on one side of the shared sense amplifier and one on the other side are divided into different column replacement segments. In the present description, "column replacement segment" is a unit of memory cell group with the same group to replace in the column redundancy.
With a small layout area of column redundancy cells, the can be improved by having separate column replacement segments rather than having a common column replacement segment for the both sides of the shared sense amplifier.
In FIG. 1, let's assume that there are L number of the row selecting signal lines RYSW for the column redundancy cells on column number 0. If the left and right sides of all shared sense amplifiers have one common column replacement segment, the big region covered by M+1 number of memory cell groups, which corresponds to column number 0 and row numbers 0 through M, becomes one column replacement segment. In this case, up to L number of faults within this big region of column replacement segment can be relieved, however, if L+1 number of faults occur, it cannot be relieved.
In order to relieve L+1 number of faults, L+1 number of the row selecting signal lines RYSW for the column redundancy cells of column number 0 are needed, and as a result, the layout area of the column redundancy cells will increase.
On the other hand, in the case where the left and right sides of all shared sense amplifiers have separate column replacement segments, each memory cell group N7 on column number 0, but a different row number, becomes a small separate column replacement segment. In this case, up to L number of faults within the each small column replacement segment can be relieved.
Therefore, if the same amount of faults occur in each of the column replacement segments, a maximum of L×(M+1) number of faults can be relieved within the big region covered by M+1 number of memory cell groups that correspond to column number 0 and row numbers 0 through M.
As described above, with the same amount of the row selecting signal lines for the column redundancy cells, the smaller the column replacement segment, the more faults can be relieved.
Further, when trying to relieve the same fault density, the smaller the column replacement segment, the fewer row selecting signal lines for the column redundancy cells is needed, and as a result, a small layout area of the column redundancy cells can be achieved.
Also, not all shared sense amplifiers have memory cell groups on the both sides assigned to different column replacement segments. In general, a configuration where several memory cell groups are assigned to one column replacement segment is commonly used.
For example, in FIG. 1, the two memory cell groups on column number 0 and row numbers 0 and 1 are assigned to one column replacement segment, and the memory cell groups on row numbers 2 and 3 are assigned to one column replacement segment. This means every two memory cell groups are assigned to one column replacement segment. This is because of the following problem: The smaller column replacement segment results in more sets of the column replacement. It means more fuses for programming are needed, and as a result, the layout area of the fuses increases.
In FIG. 6, the PMOS sense circuit 4 is provided in an N-well region. All the circuits shown in FIG. 6, except for the PMOS sense circuit 4, are provided in a P-well region. On the borderline between the N-well and P-well, an wasted region with a width of several um (micrometers) called "well isolation area" where no transistor can be provided occurs. Therefore, in order to decrease the layout area, all the N-well regions of the PMOS sense circuits 4 within the sense amplifier circuits 60, 61, 62, 63, . . . , and R60 and R61 are connected, and the N-well regions are provided zonally in the vertical direction of the drawing.
FIG. 7 is a timing chart showing an example of the general operation of the shared sense amplifier shown in FIG. 6. As power-supply voltages, a boost level VPP, an array voltage VAR, the bit line precharge power supply VHB, and a reference voltage GND are supplied. The level of the VHB is set to the level of ½×VAR level. Further, the level of a capacitor plate voltage VP supplied in FIG. 6 is generally the same fixed level as the VHB.
Also, in the example shown in FIG. 7, the level of the word line during the equalizing period is at the GND potential, however, with recent DRAM's, there are cases where a power supply VKK with a negative potential, lower than the GND potential, is provided, and the level of the word line during the equalizing period is set to the VKK. Further, in a conventional DRAM, a negative potential VBB, lower than the GND potential, is supplied as the potential of the P-well shown in FIG. 6.
During the equalizing period before timing T1, the control signals EQL and EQR is set to the VPP level (the EQR is shown in the drawing). Because of this, the equalizer circuits 1L and 1R are turned on, a short circuit between the pairs of the bit line pair BL0LT, BL0LN and bit line pair BL0RT, BL0RN occurs (an equalizing operation is performed), and the bit line precharge power supply VHB is supplied. The control signals SHL and SHR are set to the VPP level, and the shared switch circuits 2L and 2R are turned on. Because of this, the sense amplifier circuit nodes SL0T, SL0N etc. are set to the VHB level, the same level as the bit line pair BL0LT, BL0LN and bit line pair BL0RT, BL0RN.
Let's assume that the word line within the memory cell group N7L on the left of FIG. 6 is activated at the timing of T1. In this case, the control signal SHR is set to the GND level, and the sense amplifier circuit nodes SL0T and SL0N, and the bit lines BL0RT and BL0RN are disconnected respectively. Also, the control signal EQL is set to the GND level, the equalizer circuit 1L is turned off, and the equalizing operation of the bit line pair BL0LT, BL0LN is stopped.
The control signal EQR is always kept at the VPP level during the period shown in FIG. 7, and it continues to supply the VHB level to the bit line pairs BL0RT, BL0RN, etc. The control signal SHL (not shown in the drawing) is also always kept at the VPP level during the period shown in FIG. 7, and it keeps the bit lines BL0RT and BL0RN, and the sense amplifier circuit nodes SL0T and SL0N connected electrically.
Next, the electric charge of the cell capacitor of the memory cells 8 connected to a word line, which has been elevated to the VPP level and within the memory cell group N7L, is outputted to the bit line BL0LT or BL0LN. In the example shown in FIG. 7, a high level is outputted to the bit line BL0LT, and this output is transferred to the sense amplifier circuit nodes SL0T and SL0N through the shared switch circuit 2L, and there is a slight difference potential between the SL0T and SL0N. After this, a sense operation is performed, setting the sense signal SAN at the GND level and the sense signal SAP at the VAR level.
During the sense operation, each one of the two transistors of the NMOS sense circuit 3 and PMOS sense circuit 4 corresponds to the slight difference potential between the SL0T and SL0N, and is turned on to amplify this difference potential. The SL0T is sensed at the VAR level and the SL0N at the GND level.
Since the NMOS sense circuit 3 and PMOS sense circuit 4 are designed such that they amplify the slight difference potential normally when the levels of the SL0T and SL0N are close to the VHB level, they cannot amplify normally when the levels of the SL0T and SL0N are not close to the VHB for some reason.
Furthermore, the levels of the nodes SL0T and SL0N within the sense amplifier circuits are transferred to the bit lines BL0LT and BL0LN respectively through the shared switch circuit 2L, and the bit lines BL0LT is set to the VAR level and the BL0LN at the GND level.
Furthermore, although not shown in the drawing, if the level of the row selecting signal line YSW0 is increased from the GND to the VAR level when in the state described above, an IO switch circuit 5 is turned on, and the IO line and the sense amplifier circuit nodes SL0T and SL0N are electrically connected. Because of this, the sense amplifier circuit can be written or read through the IO line, and a write/read operation is performed on the memory cells 8 connected to a selected word line.
The equalizing operation is performed as follows: first, the word line is set to the GND level. Then, by setting the control signal EQL at the VPP level at the timing of T2, the equalizer circuit 1L is turned on and the bit line pair BL0LT, BL0LN is equalized to the VHB level.
During this equalizing operation, even if the bit line precharge power supply VHB hardly supplies any level, the bit line pair BL0LT, BL0LN can be equalized to the VHB level. While being active, the BL0LT is at the VAR level and the BL0LN at the GND level, and the BL0LT and BL0LN have nearly the same wiring capacitance. Therefore, during the equalizing operation, they can be set to the level of ½×the VAR level, i.e., the VHB level by a charge reallocation of each bit line.
Also, the control signal SHR is set to the VPP level around the timing of T2, and the shared switch circuit 2L, 2R is turned on. By doing this, the nodes SL0T and SL0N within the sense amplifier circuit are connected to the bit line BL0LT, BL0LN, and BL0RT, BL0RN respectively through the shared switch circuit 2L and 2R, and as a result, they are set to the VHB level. Since the wiring capacities of the sense amplifier circuit nodes SL0T and SL0N are small, the nodes SL0T and SL0N follow the potential change of the bit lines BL0LT, BL0LN, and BL0RT at a high speed, and reach the VHB level even if the on-resistance of the shared switch circuits 2L and 2R is high.
The period between the timing of T1, when the control signal EQL is set to the GND level, and the timing of T2, when it is set to the VPP level, is an active period, and the period during which the control signal EQL is set to the VPP level is an equalizing period. Further, a case where all the sense amplifiers within the DRAM are in the equalizing period is called "standby."
In the recent DRAM specifications, there has been the stronger demand for an increase in speed by shortening the equalizing period. Therefore, after the control signals EQL and SHR reaches the VPP level, it is preferred that the bit lines BL0LT and BL0LN, and the sense amplifier circuit nodes SL0T and SL0N reach the VHB level sooner than later.
In the circuit configuration shown in FIG. 6, for the purpose of decreasing the layout area of the sense amplifier circuit, it is possible to have a circuit configuration where there is only one equalizer circuit, instead of having the two equalizer circuits (1L and 1R), connected to the sense amplifier circuit nodes SL0T and SL0N.
FIG. 8 is a drawing showing a circuit configuration of such a shared sense amplifier. Only the part controlled by the row selecting signal line YSW0 is extracted from the configuration shown in FIG. 6, and shown in FIG. 8.
The difference between the configurations shown in FIGS. 6 and 8 is the fact that the equalizer circuits 1L and 1R in FIG. 6 are omitted in FIG. 8 and an equalizer circuit 1 is provided instead.
The equalizer circuit 1 comprises an NMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T and other electrode is connected to the SL0N, an NMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T and other electrode is connected to the VHB, and an NMOS transistor whose electrode is connected to the VHB and other electrode is connected to the sense amplifier circuit node SL0N, and a control signal EQ is connected to the gates of these three NMOS transistors.
The operation of the configuration in FIG. 8 is the same as the one in FIG. 7 except for the fact that the control signal EQL is replaced by the control signal EQ. The equalizing operation is performed when the control signal EQ reaches the VPP level at the timing of T2 and the equalizer circuit 1 is turned on. At that time, the short circuit between the bit lines BL0LT and BL0LN occurs through the shared switch circuit 2L and the equalizer circuit 1. The wiring capacities of the bit lines BL0LT, BL0LN, etc. are several times the amount of the wiring capacities of the sense amplifier circuit nodes SL0T, SL0N, etc. Therefore, the on-resistance of the shared switch circuit 2L needs to be low enough in order to have the bit line pairs BL0LT, BL0LN equalized at a high speed and reach the VHB level.
In other words, the transistor size of the shared switch circuit needs to be enlarged. As a result, in order to deal with the demand for speeding up the equalizing period, the layout area of the configuration shown in FIG. 8 ends up bigger than the one of the configuration shown in FIG. 6.
Further, in the configuration shown in FIG. 8, since the shared switch circuit 2R is turned off during the active period, the bit lines BL0RT, BL0RN, etc. are floated. Depending on the specifications of the DRAM, there are cases where the active period becomes very long. If a fault where a minute leakage current flows in the bit lines BL0RT or BL0RN occurs at this time, the level will greatly deviate from the VHB and the bit line will have a write/read fault. Therefore, with the configuration shown in FIG. 8, the manufacturing yield will be reduced compared to the circuit configuration shown in FIG. 6.
Because of the problem described above, the equalizer circuits of the recent DRAM's should be provided discretely for the bit line pairs on the left and right sides of the shared sense amplifier as in the example shown in FIG. 6.
In the configuration of a conventional DRAM shown in FIG. 6, if a short-circuit defect between a bit line and word line occurs, it will result in a write/read fault. For example, if a short-circuit defect 15 between the bit line BL0LT and the word line occurs in FIG. 6, memory cells connected to the bit line pair BL0LN, BL0LT will have a write/read fault.
When this fault occurs, the memory cell group 10 will be replaced by the column redundancy memory cell group R7L and made non-defective in terms of write/read operation.
However, even after the replacement, since the VHB level is supplied to the bit line BL0LT and the GND level (or the VKK level) is supplied to the word line during the equalizing period, a leakage current will flow and the standby current will increase.
Further, the resistance value of the short-circuit defect can be anywhere from a low resistance of several ohms to high resistance of more than several hundreds mOhms. According to our estimate, when a short-circuit defect between a bit line and word line has a low resistance of several ohms, a leakage current at a short-circuit defect area will be approximately 200 μA (microampere).
Since the standby current specification of a conventional DRAM is as small as several mA (milliampere), just by having 10 short-circuit defects with a low resistance between a bit line and word line, it becomes a leakage current fault, resulting in a manufacturing yield reduction.
Therefore, means for reducing leakage current even when a short-circuit defect occurs between a bit line and word line is desired, and several methods have been proposed.
As means for reducing the leakage current caused by a short-circuit defect between a bit line and word line, a method of providing a current-limiting element between a equalizer circuit and bit line precharge power supply VHB is published in Patent Document 1.
FIG. 9 is a drawing showing the configuration of the shared sense amplifier circuit described in Patent Document 1. In FIG. 9, only the part controlled by the row selecting signal line YSW0 is extracted from FIG. 6. The difference between FIG. 6 and FIG. 9 is the fact that the current-limiting elements 9 are provided between the equalizer circuits 1L and 1R and the VHBs in FIG. 9.
Furthermore, as concrete circuit configuration examples, the configurations shown in FIG. 10A, FIG. 10B, FIG. 10C, and FIG. 10D are published in Patent Document 1.
In the circuit configuration shown in FIG. 10A, an NMOS transistor is used as a current-limiting element 9, and one electrode of the NMOS transistor is connected to the VHB, and the other electrode is connected to a node A. Further, its gate is connected to a constant voltage level V1, and the voltage of the V1 is set to a level with which an appropriate current can be flowed. Also, the node A is supplied to the equalizer circuit 1L.
In the circuit configuration shown in FIG. 10B, a PMOS transistor is used as a current-limiting element 9. A gate voltage V1 of the PMOS transistor is set to a level with which a proper current can be flowed.
In the circuit configuration shown in FIG. 10C, a depression-type NMOS transistor is used as a current-limiting element 9. The gate of the depression-type NMOS transistor is connected to the node A. The threshold voltage of the depression-type NMOS transistor is set to a value with which a proper current can be flowed by adjusting the impurity doping level.
In the circuit configuration shown in FIG. 10D, a register is used as a current-limiting element 9. The resistance value of the register is set to a value with which a proper current can be flowed.
Furthermore, in Patent Document 2 and Non-Patent Document 1, a configuration where one current-limiting element is shared by multiple equalizer circuits controlling multiple bit line pairs, which are to be replaced by a column redundancy memory cell group simultaneously as a set is published. By doing so, the number of the current-limiting elements can be reduced and the increase in layout area can be restrained.
FIG. 11 is a drawing showing the circuit configuration of a shared sense amplifier based on such a principle published in Non-Patent Document 1 as FIG. 8.
The differences between FIGS. 11 and 6 are the facts that one current limiting element 9 is provided for two equalizer circuits 1L respectively connected to the bit line pair BL0LT, BL0LN and bit line pair BL1LT, BL1LN, which are to be replaced by a column redundancy memory cell group as a set, one electrode of the current-limiting element 9 is connected to the bit line precharge power supply VHB while the other electrode is connected to a node A0L, and the node A0L is supplied to the two equalizer circuit 1L.
Similarly, one current-limiting element 9 is shared by two equalizer circuits 1R connected to 2 bit line pairs, which are to be replaced by a column redundancy memory cell group as another set. The same goes for the areas controlled by the column redundancy row selecting signal line RYSW. In the example of Non-Patent Document 1, a depression-type NMOS transistor is used as a current-limiting element 9, however, it is possible to use it as a different type of current-limiting element.
FIG. 12A shows the means for reducing the leakage current caused by a short-circuit defect between a bit line and word line, published in Patent Document 2, and the drawing shows only the part on column number 0 extracted from the DRAM array configuration shown in FIG. 1. Furthermore, FIG. 12B is an example of a circuit configuration where this method is applied to a shared sense amplifier circuit, and only the part controlled by the row selecting signal line YSW0 is extracted from FIG. 6.
What is different about FIG. 12A from FIG. 1 is the fact that signal lines A0, A1, . . . RA are wired so that each of them is parallel to each of row selecting signal lines YSW0, YSW1, . . . RYSW, each of the signal lines A0, A1, . . . RA is connected to each of the sense amplifier 6, and the signal lines A0, A1, . . . RA and the bit line precharge power supply VHB are connected through each fuse. As a current-limiting element 9, a fuse is used.
What is different about FIG. 12B from FIG. 6 is the fact that, instead of the VHB, the signal line A0 is connected to the four equalizer circuits within the sense amplifier circuits 60 and 61 controlled by the row selecting signal line YSW0.
In the configuration published in Patent Document 2 shown FIGS. 12A and 12B, when the short-circuit defect 15 between the bit line and word line occurs, the row selecting signal line YSW0, which has become faulty, is replaced by the column redundancy row selecting signal line RYSW and the fuse of the corresponding signal line A0 is cut off so that the leakage current is shut off.
[Patent Document 1]
Japanese Patent Kokai Publication No. 8-263983 (Claim 9, FIG. 3, FIG. 4, FIG. 5)
[Patent Document 2]
Japanese Patent Kokai Publication No. 7-334987 (Paragraph [0035], [0036], FIG. 1, FIG. 2, FIG. 3)
[Non-Patent Document 1]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 4, APRIL 1996, P558˜P566, Fault-Tolerant Designs for 256 Mb DRAM, Toshiaki Kirihata, et al., Publication Date: NO. 4, April 1996, P563, FIG. 8
The entire disclosure of these documents are incorporated herein by reference thereto.


In a printer system wherein one or a plurality of host computers use in common a single printer such as an expensive photo printer for electronic publishings of desktop publishings such as word processors, character format data of characters to be printed out is stored beforehand as character pattern data at a printer controller of the printer system. The host computer either stores minimum necessary character pattern data for monitor display or control, or stores no character pattern data. The character pattern data necessary for monitor display or control are used by transferring them from the printer controller to the host computer.

The present invention relates to an improvement on a printer system wherein at least one host computer connected to a printer supplies data to the printer to print out corresponding image data, and more particularly to an improvement on a method of operating a printer system wherein a plurality of host computers use in common a single high quality printer such as a laser printer to print out according to data supplied from the computers.
In known printer systems such as photoprinters used for electronic publishings or desktop publishings such as word processors, several proposals have been hitherto made to effectively utilize memories for storing print data or like (e.g., U.S. patent application Ser. No. 145312 entitled "Method of controlling photo printer and apparatus therefor", filed on Jan. 19, 1988, by Takagishi et al and assigned to Hitachi Ltd.; or U.S. patent application Ser. No. 225782 entitled "Photo printer having a host computer support and method of controlling the same", filed on Jul. 29, 1988, by Kawamata et al and assigned to Hitachi Ltd., both being still pending) a printer is connected via data communication means to a host computer which supplies data, such as graphs, figures, photographs, characters and the like to the printer. Character pattern data for characters to be printed are stored beforehand in a memory of the host computer as well as in a memory of a printer controller of the printer. Character pattern data corresponding to inputted data is read out from the memories and converted into corresponding character image data to be printed out by a printer engine of the printer. One of such conventional system arrangements adopts a character data transfer method (Japanese Patent Laid-open Publication JP-A-61-134791). According to the method, the memory of the host computer stores therein main character pattern data, whereas the memory of the printer controller stores therein supplementary character pattern data. Character pattern data not stored in the memory of the printer controller is accessed by the host computer and transferred from the host computer to the printer controller. The character pattern data stored in the memory of the host computer is used as print data and also as display data on a CRT of the host computer for monitoring and controlling the printing.
The resolution of the image at the printer output side is required to be high so as to obtain a high print quality. In view of this, the resolution at the printer output side is set, e.g, at 48.times.48 dots in spite of the resolution of 24.times.24 dots of the CRT screen of the host computer. Therefore, with such a conventional method by which character pattern data stored at the host computer is transferred to the printer controller, the data amount to be transferred becomes large, posing a problem of long transfer time.
Apart from the above, various character types and sizes are used for applications, such as electronic publishing or desktop publishings and the like, so that the capacity of a memory storing such voluminous character pattern data becomes large. In the case where a single printer (printer controller) is used with a plurality of host computers connected thereto, every host computer has the same character pattern data in duplicate, thus posing a problem of a large memory capacity of the overall system.

Printer system and operating method therefor


The present invention relates to a hormonal contraceptive product having two hormonal components, an estrogen and a gestagen, and a process for the combined, continuous administration of the product of the invention.

The present invention relates to a hormonal contraceptive product with two hormonal components, the use thereof and a hormonal contraception process.
Since hormonal contraceptives became available in the 1960""s, a number of hormonal components have been investigated with regards to their suitability in the most varied administration diagrams. A fundamental subdivision into combination and sequential products is possible.
For example, if the desired cycle time is 28 days, in the case of the known combination products administration takes place over 21 days in a constant or varying absolute and/or relative dosage of a combination of an estrogen product and a gestagen product, in which the estrogen product can e.g. be natural estrogen or synthetic ethinyl estradiol and the taking of the aforementioned 21 daily units is followed by a seven-day interval where there is a withdrawal bleeding simulating natural menstruation.
In the known sequential products, once again for a desired cycle time of 28 days, administration takes place for 7 days of a pure estrogen product and then for 15 days of a combination of an estrogen product and a gestagen product and here again there is then a taking-free period of e.g. 6 days when withdrawal bleeding occurs. It is admittedly already known to bridge the inherent taking intervals of combination and sequential products in the interest of greater taking security by administering within the days in question placebos. However, it has hitherto always been assumed that during the roughly one-week taking interval no hormones of the present type should be administered, in order to ensure a reliable withdrawal bleeding. Only in the case of substitution products in the menopause of older women have hormones been administered throughout the cycle, e.g. in the sequence 10 days estrogen product, 11 days combination of estrogen and gestagen product, 7 days estrogen product, 7 days estrogen product in a particularly low dosage, but said substitution products are unsuitable for ovulation inhibition.
The sequential products used in substitution therapy are in particular unsuitable for contraception because the natural estradiol does not prevent ovulation in the dosage administered and the phase in which gestagen is administered is too short, being only 11 days. However, in the case of the substitution products, the above-described sequential system guarantees a relatively good cycle control.
German patent 43 08 406 discloses a combination contraceptive product, which comprises one or more stages. At least one stage contains the combination of three components, namely a biogenous estrogen, a synthetic estrogen and a gestagen and the further stages in each case comprise a pharmaceutically unobjectionable placebo or a biogenous or synthetic gestagen, or a biogenous or synthetic estrogen, or a combination of two components, namely a biogenous estrogen, a synthetic estrogen and a gestagen or a combination of synthetic estrogen and a gestagen.
The description of the above document makes it clear that in the stage concept described therein there is typically a change of state over the period of time. Such a state change can take place in that the composition of the phases forming the stage is modified with respect to the components used and in that only the concentrations of the components used in the phases forming the stage undergo changes.
The problem of the invention is to provide a hormonal contraceptive product, which ensures high contraceptive safety or reliability and prevents inter-menstrual bleeding. There is also to be a further reduction in the side effects otherwise observed in hormonal contraceptive products.
According to the invention this problem is solved by a hormonal contraceptive product having two hormonal components, the agent comprising for continuous, combined administration a first hormonal component comprising at least one gestagen and a second hormonal component comprising at least one estrogen.
The problem is also solved by a hormonal contraception process, in which an a product, which comprises at least one first hormonal component, which comprises at least one gestagen, and a second hormonal component comprising at least one estrogen is continuously administered.
According to another aspect of the invention the product according to the invention is used for inhibiting ovulation.
According to a further aspect of the invention the product according to the invention is used for the treatment and/or prophylaxis of breast tumours.
According to another embodiment the invention proposes that gestagen as the first hormonal component is chosen from the group comprising progesterone, chlormadinone acetate, norethisterone acetate, cyproterone acetate, desogestrel, levenorgestrel, other natural and/or synthetic gestagens, anti-gestagens and hormonal analogs with gestagen or antigestagen action, as well as hormonal compounds which rapidly split off at least one gestagen following taking.
In the product according to the invention, the estrogen as the second hormonal component can be selected from the group comprising synthetic estrogens, biogenous estrogens, antiestrogens and hormonal analogs with estrogen or antiestrogen action.
In a preferred embodiment the synthetic estrogen is selected from the group comprising ethinyl estradiol, mestranol and the like, as well as hormonal compounds rapidly splitting off at least one synthetic estrogen following taking.
In particularly preferred manner the synthetic estrogen is ethinyl estradiol.
In preferred embodiments the daily administered ethinyl estradiol quantity is 1 to 20 xcexcg. In particularly preferred manner, the daily administered ethinyl estradiol quantity is 5 to 10 xcexcg.
According to the invention the biogenous estrogen is selected from the group comprising estradiol, estriol, estrone, estrane, etc., as well as hormonal compounds rapidly splitting off at least one biogenous estrogen after taking.
According to an embodiment the estradiol comprises 17-xcex1-estradiol and/or 17-xcex2-estradiol.
According to another embodiment the daily administered biogenous estrogen quantity in the case of estradiol, particularly xcex1 and xcex2-estradiol, is 0.1 to 2 mg and in the case of conjugate estrogens 0.05 to 0.5 mg.
In an embodiment the product according to the invention can be administered orally.
In an alternative embodiment the product according to the invention can be administered transdermally.
In a second alternative embodiment the product according to the invention can be administered intravaginally.
In a third alternative embodiment the product according to the invention can be in depot injection form.
In a fourth alternative embodiment the product according to the invention can be administered as a hormonal implant.
Finally, the daily units in each case comprising both hormonal components, are placed in spatially separated and individually removable manner in a packaging unit.
In an embodiment of the process according to the invention the first hormonal component can be administered in combination with the second hormonal component.
In another embodiment of the process according to the invention the product according to the invention is administered.
The invention is based on the surprising finding that as a result of the continuous, combined administration of a product comprising two hormonal components, namely a first hormonal component comprising at least one gestagen and a second hormonal component comprising at least one estrogen, a high contraceptive reliability can be achieved.
In accordance with modern opinion, estrogens are not understood to cover steroid molecules, which preferably evolve their action in that they in different ways exert a biological effect at different cell locations in different organs. Estrogens can act (1) on the cellular membrane, (2) intracellular, cytoplasmic proteins and (3) specific nuclear receptors. It has recently become known that besides the standard estrogen receptor type 1 there is a second estrogen receptor type 2, whose organ distribution is different from that of the estrogen receptor type 1.
Thus, the above definition also covers the compounds known as xe2x80x9cdesigner hormonesxe2x80x9d, which have the aforementioned characteristics.
Thus, biogenous estrogens are steroid molecules, which evolve an estrogen-like action on the membrane, cytoplasmic proteins and nuclear receptors for hydrophobic ring substances and consequently trigger biological effects corresponding to a hydrophobic steroid ring structure able to initiate an estrogen-like action in cells, organs and the complete organism.
The term biogenous estrogens also covers those estrogens which are produced by the human body and consequently include endogenic estrogens. The biogenous estrogens used in specific embodiments of the product according to the invention are typically those which are chemically synthesized. However, it is fundamentally also possible to use compounds isolated from an organism.
Biogenous estrogens also cover conjugate, biogenous estrogens such as e.g. estradiol valerate and estrone sulphate.
The term antiestrogens is here understood to mean hydrophobic ring structure substances and other substances able to specifically and selectively counteract the above-described estrogen action on cells, organs or the overall organism.
Continuous administration is here understood to mean an administration uninterrupted over the use period, in which there are no hormonal component taking-free intervals. This means that there is no interruption of the administration of the product by administering placebos in place of the hormonal product. Thus, over the administration period typically lasting several months to years there are no changes to the fundamental composition of the hormonal components. Instead over the entire administration period the hormonal components forming the hormonal product according to the invention are administered uninterrupted and unchanged with no modification to the concentration. However, it is conceivable for the concentration of estrogen, understood in the full breadth of the concept defined here, and gestagen, also understood in the full breadth of the term defined here, can be changed for older women compared with younger women. This can also take place in such a way that over the continuous administration period initially there is a start with a specific composition and this is then adapted over a period of weeks, months and years to the changed biological needs of the women through the administration of a subsequent product, but which also comprises a product according to the present invention.
As a result of the continuous administration of said hormonal components it is ensured that the natural hormonal processes taking place in the female organism do not interrupt the contraceptive security.
As a result of the estrogen component, respectively by specific action of hydrophobic ring substances with an estrogen-like action, there can be a suppression of gonadotropins. This is desirable. The resulting suppression of the ovarial function is compensated by an adequate substitution of estrogen action. This prevents the development of osteoporosis, the favourable vascular effects of estrogens are maintained and there is no unfavourable influence to the lipid metabolism. By interrupting the cycle-dependent instability in the hormone system, the premenstrual syndrome can be favourably influenced. In addition, the physiological equilibrium of the coagulation system is not disturbed, because the unstable equilibrium in which the coagulation system occurs is not activated and deactivated by the up and down of hormone fluctuations. Thus, the hormonal product according to the invention is particularly suitable for women aged more than 40, where the risk of circulatory disturbances is known to increase with increasing age. There is also a reduction in the thrombosis risk, which has of late acquired considerable significance in contraceptive therapy.
It has surprisingly also been found that on administering the product according to the invention there is a reliable continuous suppression of the menstrual cycle and menstruation in the case of a very low dosage. Without wishing to be bound by this explanation, the combination of the two indicated hormonal components and in particular the low estrogen dosage would appear to be suitable for eliminating the otherwise conventional side effects of ethinyl estradiol and to drop below the administrations of more than 15 xcexcg of ethinyl estradiol otherwise considered typically necessary in prior art contraceptives.
The low dosage of the two hormonal components and in particular the estrogen component is made possible by the additive action of the two hormonal components, without there being any limitation to the action of the product according to the invention with respect to its contraceptive and ovulation-inhibition properties.
The ovulation inhibition and menstrual cycle suppression reliably ensured by the product according to the invention is of great significance for certain patients, such as e.g. for top sports women, dancers and business women, who wish to exclude any reduction in their physical, intellectual and emotional efficiency as a result of the menstrual cycle. As a result of the combined, continuous administration of the two hormonal components of the product according to the invention it is possible to administer the same either orally, transdermally, intravaginally, by depot injections or hormone implants. Here again the advantages observed for the particular administration forms are obtained.
Possible oral administration forms are all the forms known from the prior art such as e.g. tablets, dragees, pills or capsules, which are produced using conventional adjuvants and carrier substances.
In the transdermal administration of the product according to the invention the two hormonal components forming the product can e.g. be applied to a plaster or also can be applied by transdermal, therapeutic systems and are consequently supplied to the organism. For example an already prepared combination of the two hormonal components or the latter individually can be introduced into such a system, which is based on ionotherapy or diffusion or optionally a combination of these effects.
In the case of oral administration it has proved appropriate to place the daily units, which in case comprise a combination of the two hormonal components, in a spatially separated and individually removable manner in a packaging unit, so that it is easy to check whether the typically daily taken, oral administration form has in fact been taken. It is important to ensure that there are no taking-free days. Depot injections can be administered at 1 to 6 months or longer intervals. Hormonal implants contain both hormonal components and deliver the same over a period of preferably 3 to 6 months.
When using the product according to the invention it has surprisingly been found that the treatment and/or prophylaxis of breast tumours is possible. The latest breast cancer risk research has revealed that mutations, which can be hereditary or acquired, occur in certain risk genes. Modern cancer therapy assumes that a cancerogenic mutation is present on one of the two allels of a gene which is initially controlled by the other, healthy allel. If a further mutation occurs in a specific organ cell on the second allel, then uncontrolled, malignant growth can occur.
Mutations on the second allel particularly frequently occur in given phases of the cell cycle, namely in the G1 phase. Every four weeks the menstrual cycle drives the breast cell in a cell cycle, xe2x80x9copensxe2x80x9d the genome for mutations, which are either repaired or apoptotically xe2x80x9cremovedxe2x80x9d. Under the conditions of the conventional combined or sequential contraception treatment a women can have 500 to 700 cycles over her life span, whereas under natural conditions a women has a maximum of 20 to 30 cycles. Thus, in an unusually frequently number of cell cycles over in each case 8 days a considerable mutation risk is introduced into the stimulated breast tissue. If the menstrual cycle is suppressed, as is possible with the product according to the invention, the breast cells are brought into a xe2x80x9crest phasexe2x80x9d and it is scientifically ensured that in the rest phase less cancerogenic mutations are introduced into a tissue than in a stimulated tissue. This reduces by a multiple mutagenesis, i.e. the breast cancer risk.
The aforementioned use of the product according to the invention for the treatment and/or prophylaxis of breast cancers is in particular associated with special advantages if the users of the product are high-risk subjects, such as e.g. those with a high family breast cancer risk.
The quantity of administered gestagens and estrogens substantially corresponds to the quantity of comparable prior art products. The examples provide further information concerning the quantities to be administered daily of the different compounds forming the first and/or second hormonal components.
The invention is explained in greater detail hereinafter relative to examples revealing further features, advantages and embodiments of the present invention.


A photomultiplier includes a photocathode (3); an electron multiplier section (60) for cascade-multiplying photoelectrons emitted from the photocathode (3); a faceplate (2) provided with the photocathode (3); a metal housing (1) accommodating the photocathode (3) and the electron multiplier section (60); and a structure disposed on the faceplate (2) for increasing the effective light entrance region of the faceplate (2). In a preferred embodiment the subject structure includes a lens element (30) attached to the faceplate for increasing the effective light entrance region of the faceplate (2). In order to improve the optical coupling efficiency, either the faceplate (2), or the lens element (30), or both the faceplate (2) and the lens element (30) may further include a protrusion.

1. Field of the Invention
The present invention relates to a photomultiplier for multiplying photoelectrons emitted in response to incident light which has reached a photocathode and, in particular, to a photomultiplier having a structure for making the area of an effective light entrance region for the incident light become greater than the area of the light receiving surface of the photomultiplier.
2. Related Background Art
Conventionally, as an optical sensor for measuring weak light or the like, so-called head-on type photomultiplier has widely been used. In the head-on type photomultiplier, one end of a cylindrical vacuum container constitutes a faceplate. Though the vacuum container of such a head-on type photomultiplier is made of a glass tube in general, there has recently been developed, as disclosed in Japanese Patent Application Laid-Open No. 6-310084 or the like, a photomultiplier constituted by a cylindrical metal tube and a faceplate (where a photocathode is disposed) disposed at one end thereof and supported by a flange extending toward the tube axis of the metal tube.