A method for supporting to collect hard negative image is provided. The method includes the steps of: (a) a classifier receiving from a hard negative proposer, and classifying, hard negative image candidate corresponding to a certain label candidate or a specific label candidate judged to have semantic or visual relationship with a target object; and (b) the classifier (i) allowing the hard negative proposer to select an additional label candidate whose similarity to the certain label candidate or the specific label candidate exceeds a preset degree of similarity, if a percentage or a number of the hard negative image candidate mistaken for having the target object is judged to satisfy a prefixed condition, (ii) receiving at least one additional hard negative image candidate corresponding to the selected additional label candidate and (iii) classifying the additional hard negative image candidate.

Today, technologies for object detection or recognition which have been developed and embedded in a variety of electronic devices are used. For example, pedestrian detection technology for preventing risks of pedestrians by detecting the pedestrians is being put to use in a variety of electronic devices.
The object detection or recognition technology includes a process of learning (i.e., classifying) acquired images. The performance of a detector (i.e., classifier) depends on which types of features showing positions and intensity values of pixels of images to learn will be used and how many images will be used for learning. Recently, as image database where a lot of image data are accumulated has been built, a lot of image data enough to be used for learning have come to be obtained easily.
In general, a classifier may learn negative images which do not include a target object to detect or recognize. A detection system may repeat a bootstrapping process under which hard negative images, even as negative images, mistaken for including the target object are collected and re-learned.
If the bootstrapping process is repeated by using a lot of negative images, the operation quantity of the bootstrapping process, however, increases too much, resulting in too much time for whole learning. For effective learning by the classifier, it is necessary to select and learn only hard negative images mistaken for positive images, i.e., images including the target object, although the hard negative images do not include the target object.

Method, hard negative proposer, and classifier for supporting to collect hard negative images using a similarity map


A technique for supporting the sizing of hierarchical computer resources is provided. The sizing support system includes a memory, a table definition module and field calculation module. The memory stores lower level resource data which indicates the kinds and the maximum number of lower level resources belonging to the resources of each hierarchy level, and resource data which indicates parameters of resources of each hierarchy level. The processing is executed in a unit of three levels. In the unit process of three levels, the table definition module generates a table frame indicating the possible configurations of first resource by referring the lower level resource data. The field calculation module calculates the performance and cost of the configuration in the table frame by referring the resource data.

1. Field of the Invention
The present invention relates to a sizing of hierarchical computer resources. More particularly, the present invention relates to a sizing support system, method and program for supporting the sizing for hierarchical computer resources of 3 hierarchy levels or more.
2. Description of the Related Art
The prices of the information processors such as the personal computer, workstation and the like (hereafter, referred to as nodes), which has one or more CPUs, memories and communication devices, have been reduced recently. As a result, the cluster constructed by combining (or clustering) a plurality of nodes to operate as one system becomes popular. In the cluster, the nodes are connected to and communicate with each other. The cluster is excellent in the cost performance and in the scalability.
The excellent scalability results from the characteristic that the cluster is hierarchical computer resources. The hierarchical resources are constructed from the computer resources provided with a plurality of hierarchy levels, and a resource of higher level (the higher level resource) is constituted by the combination of the resources of lower hierarchy level (the low level resources). The performance of a high level resource can be enhanced by increasing the number of low level resources or improving the performance of low level resources. For example, by increasing the number of the nodes constituting a cluster or improving the performance of the node, the performance of the cluster is enhanced. Thus, a cluster is hierarchical resources, and the nodes constituting the cluster are also hierarchical resources. This is because the increase in the number of the CPUs constituting a node or the improvement of the performance of the CPU improves the performance of the nodes.
Also, hierarchical resources having a uniform configuration are called as uniform hierarchical resources. For example, a cluster provided with only the nodes of the same kind is uniform hierarchical resources. Each of the nodes of the same kind is composed of the CPUs of the same kind and the same number. The actually used clusters are in many cases the uniform hierarchical resources.
It is important to consider the type of the resources to be employed and to determine the configuration of the hierarchical construction before constructing or enhancing the hierarchical resources. That is, in order to attain the processing performance necessary for the system, it is important to consider the types of the resources to be employed and to determine the configuration of the resource hierarchy. Such a process is called as sizing. The system which cannot provide the sufficient processing performance cannot provide sufficient services to clients. Thus, it is very important to execute the sizing at a high precision.
Typically, the sizing plan is experientially made on the basis of the sense and experience of skilled technicians. The processing performance of the hierarchical resources constituted in accordance with the sizing plan is estimated and compared with the processing performance required for the system. If the processing performance does not agree with the requirement, the sizing planning is executed again.
It is required that a technique which makes it possible to quantitatively execute the sizing of the hierarchical resources independently from the experience of technicians before construction or enhancing the hierarchical system. In particular, in many cases, clusters are the uniform hierarchical resources. Thus, the technique which supports the quantitative execution of the sizing of the uniform hierarchical resources is desired.
As the conventional technique related to the control and performance estimation of the computer resources after a computer system is constructed, the following techniques are known.
In Japanese Laid Open Patent Application (JP-P 2003-223335A), a virtual stand-alone outsourcing system is described. According to the virtual stand-alone outsourcing system, the computer resources are divided into a plurality of partitions, and the respective partitions are used by clients. Also, correspondingly to the performance information for each partition, the configuration of the partition is dynamically changed.
In Japanese Laid Open Patent Application (JP-P 2004-288183A), a method for automatically allocating computing resources in a partition server is described. According to the method, priorities are set for partitions. In accordance with the priority, the competition between the resources (CPUs) is solved, and the resource amount assigned to the partition is determined.
In Japanese Laid Open Patent Application (JP-P 2004-302525A) a performance balance evaluating apparatus of a computer system is described. A performance estimation index obtaining means individually transmits and receives a test application to and from each apparatus constituting an estimation target computer system. Then, the performance estimation index obtaining means changes the number of the test applications and obtains a transaction density and a performance estimation index of each apparatus. A use rate obtaining means transmits the test application to the estimation target computer system and instructs each apparatus to process such as a usual service application and obtains a use rate of each apparatus. A capacity calculating means divides the performance estimation index of each apparatus by each use rate and calculates the capacity of each apparatus. A performance balance evaluating means defines any one of the apparatuses as a standard apparatus and calculates a performance balance from a ratio between the capacity of a different apparatus and the allowable amount of the standard apparatus.
In Japanese Laid Open Patent Application (JP-P 2000-29753A), a performance evaluating method of a system having a hierarchical resource competition is described. In the hierarchical resources, a layer of a software resource is a higher order layer, and a layer of a hardware resource is a lower order layer. At first, the hardware configuration of the lower order layer is inputted. Next, a transaction data of a transaction using the software resource of the higher order layer is inputted. Next, a process data of a process constituting the software resource is inputted. Next, the restriction condition of the process is inputted. Next, the setting which shows what type of a performance estimation value is displayed in what type of a format is carried out. Next, whether or not the given data is sufficient for calculating the performance estimation value is checked. If it is sufficient, the performance estimation value to be determined under the restriction condition of the process of the higher order layer is calculated. Finally, a displaying means indicates those performance estimation values to a user.
In Japanese Laid Open Patent Application (JP-P 2004-78947A, having a counterpart U.S. Pat. No. 7,389,435), a method for satisfying the demanded capacity in a blade-based computer system is described. In the blade-based computer system, the number of loaded blades in the system is determined. Next, an optimal performance configuration for each of the individual blades is determined. The optimal performance configuration is based at least in part on the number of the blades loaded in the chassis and the overall thermal and power envelope. Then an individual frequency for at least one of the individual blades is set creating a more efficiently run system.
In Japanese Laid Open Patent Application (JP-P 2006-331135A, a performance prediction apparatus of a cluster system is described. The cluster system has nodes which share the data in a main storage device. The performance prediction apparatus calculates the frequency of block copy between the nodes, by which the data is copied by the unit of the memory block of the storage device per unit time. The clustering overhead occurred in the cluster system is calculated based on the frequency of the block copy and the information of the CPU load per block copy.
In a textbook (Kameda, H. (1998) The Elements and Applications of Performance Assessment, ISBN: 9784320026650, KYORITSU SHUPPAN CO., LTD. 28-30 (in Japanese)), the queuing theory for performance analysis is described.

System, method and program for supporting a computer sizing having N level hierarchical resources


A mechanism for winding a cord includes a storage space in which a cord is wound around a central axis. The storage space includes a first storage space which is provided to allow the cord to be wound in one row, in a predetermined direction intersecting a direction of the central axis, and has a first height in a direction perpendicular to the predetermined direction that is substantially the same as a diameter of the cord, and a second storage space which is provided on one or both of an outer circumference and an inner circumference of the first storage space, has a second height along the direction of the central axis that is at least twice the diameter of the cord, and is provided to allow the cord to be wound in a plurality of rows along the central axis.

JP-T-2001-513979 discloses an apparatus for accommodating or storing a cable having a plurality of conducting wires. The apparatus is provided with a winding drum that can rotate around an axis to accommodate the cable. A lead wire of the cable is connected to a first connecting device and is connected to a wiring of a supply system via the first connecting device in an electrically conductive state. The first connecting device is connected to the winding drum and has a first electrical contact, and the first electrical contact is connected to the lead wire of the cable and is disposed on a circle coaxial with the axis of the drum. The electrical wiring guided to the supply system is connected to a second connecting device, which is axially movable along the axis of the drum and has a second electrical contact, and the second electrical contact forms an electrically conductive state with the first electrical contact.

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A humidity detection material includes oxide of at least one metal selected from the group consisting of Mg, Ca, Mn, Fe, Co, Ni, and Cu. The metal oxide is preferably in the form of a porous material. The metal oxide is formed preferably in the form of a thin film on a transparent substrate. The humidity detection material is contacted with water vapor in the presence of a gas such as air, and the optical absorbance of the humidity detection material is measured to detect the humidity. The humidity can be detected by an optical method.

Detection of moisture in gases such as air, that is, humidity, is important in relation to environmental problems. Recently, not only for obtaining more comfortable life space, but also with the advance in home automation and factory automation, detection, measurement, and control of humidity by a sensor becomes more and more important in view of operation environment of precision devices which are subject to troubles due to dew condensation.
Heretofore, various methods have been used for detecting humidity of gases such as air, such as (1) a method utilizing elongation of hair when it absorbs water vapor (so-called hair hygrometer), (2) a method utilizing a change in electrical resistance of an electrolyte by water vapor, (3) a method of detecting a change in resistance or volume of a dielectric material such as organic substances, semiconductors, metal oxides, and the like when moisture is adsorbed by the material, and (4) a method of detecting a weight change of a quartz oscillator coated with polyamide when moisture is adsorbed by the oscillator.
However, with these conventional methods, the method (1) has problems in that the operable ambient temperature is limited to the vicinity of room temperature, and the method cannot be used in the presence of corrosive vapors such as acid or base. In the electrochemical method (2), the device becomes complex in structure as compared to other methods, and requires maintenance of the electrodes and electrolyte. A method utilizing a change in resistance of the method (3) often uses conductivity of H.sup.+ ion generated by adsorption of water, and therefore the resistance of the humidity sensor element becomes excessively high at low humidities where the adsorbed water amount is small, and the resistance and humidity tend to be difficult to be exactly measured by an ordinary method. Further, the device generally has a difficulty of measurement due to high element resistance, and a method using a hydrophilic polymer as a moisture sensitive material cannot be used at high humidities having a possibility of dew condensation.
Further, in the method (4) using a weight change, since a signal is always output when a change in the weight of element occurs even by adsorption of molecules other than water, it requires a devise for selective detection of only water, which is sometimes difficult. Since the humidity detection signal is output as an electrical signal, the humidity detection signal tends to be disturbed by strong electromagnetic waves or noise generated by various emission sources when humidity detection is carried out by a remote control in a wide area such as in a chemical plant or a coal mine. Further, the humidity detection method based on the electrical signal is difficult to be combined directly with an information system or control system using optical signals, which recently becomes widely used, and an apparatus is required for converting the electrical signal to optical signal.
Therefore, development is in demand of a humidity detection apparatus which is immune to electrical disturbance and can be easily combined directly with an optical information system or optical control system. Heretofore, as methods for detecting humidity by an optical signal, (1) a method utilizing humidity dependence of visible light absorption spectrum or fluorescence intensity of a film comprising a polymeric carrier combined with an organic dye such as crystal violet, betaine type dye, or rhodamine type dye, and (2) a method utilizing a change in visible light absorption spectrum of cobalt chloride carried on a polymeric carrier, have been studied. However, organic dyes and organic polymers are low in heat resistance and relatively narrow in the operation temperature range, and tend to undergo an irreversible change if a highly reactive vapor is present in the environment. Therefore, a humidity detection material with improved chemical and thermal stability and a humidity detection method using the material are required.
In view of the above prior art problems, a primary object of the present invention is to provide a humidity detection material which is high in chemical and thermal stability and can detect humidity by an optical means and a humidity detection method using the material.

Agency of Industrial Science & Technology


The present invention relates to a new class of peptides having antibacterial activity and presenting D-amino acids and their uses. It also relates to a new enzyme presenting a peptide epimerase activity in vitro and in vivo, thereby being useful for modifying peptides in order to change the amino acid configuration from L to D.

Antimicrobial resistance threatens the effective prevention and treatment of an ever-increasing range of infections caused by bacteria, parasites, viruses and fungi. It is an increasingly serious threat to global public health that requires action across all government sectors and society. Antimicrobial resistance is present in all parts of the world. New resistance mechanisms emerge and spread globally.
In consideration of the constant problems due to the antimicrobial resistance, there is a strong need of new classes of antimicrobials. In particular, antimicrobial peptides are of high interest. These peptides are generally potent. In addition, they often offer a better selectivity and specificity than small molecules generally used as therapeutics.
Nevertheless, a major limitation to their use and therapeutic development is associated with their half-life. Indeed, it is commonly decreased by the action of proteases and peptidases which are present in organisms.
Therefore, numerous strategies have been developed in order to reduce the peptide degradation such as C-amidation and N-acetylation against exopeptidase, introduction of non-natural amino acids or of D-configured amino acids. However, these strategies can only be used in the context of synthesized peptides and are not suitable for recombinant production of peptides. In particular, there is no easy way for introducing D-configured amino acid in a peptide, despite the interest of such a modification. Indeed, D-configured amino acid presents the same properties than natural amino acids but are usually more resistant to proteases and even could be less immunogen.
In conclusion, any new class of antimicrobials is of great interest, especially antimicrobial peptides. In addition, any process suitable for modifying L-configured amino acid into D-configured amino acid in a peptide would be highly valuable in this context.

Peptides having antimicrobial activity and new enzyme capable of converting L-configured residue in D-configured amino acid in a peptide

INSTITUT NATIONAL DE RECHERCHE POUR L'AGRICULTURE, L'ALIMENTATION ET L'ENVIRONNEMENT


In the current limiting circuit, which is provided with: the D/A converter 2A to output the voltage signal to supply the power source onto the load 11; reversal amplifier circuit to amplify the voltage signal; capacitor 10 to absorb the fluctuation of the power source supplied onto the load 11; operational amplifier 4B to set the amplification factor of the reversal amplifier circuit; transistor 5; and resistor 3E, the current detection circuit 7 detects the current value to be inputted into the load 11, and according to the detected current value, calculates the voltage at the current detection position, and the CPU 1 sets the predetermined voltage, the comparing circuit 8 compares the setting voltage value to the calculated voltage value, and according to the comparison result, by ON/OFF-controlling the switch 9, the setting of the amplification factor of the reversal amplifier is changed.

The present invention relates to a current limiting apparatus, and in detail, to a current limiting apparatus for used in a single body power source apparatus and an integrated circuit measuring apparatus.
Referring to FIG. 5 to FIG. 8, the conventional current limiting apparatus will be described. FIG. 5 is a view showing the circuit structure of a conventional current limiting apparatus 200. In FIG. 5, the conventional current limiting apparatus is structured by a CPU 1, D/A converters 2A, and 2B, resistors 3A, 3B, and 3D, operational amplifiers 4A and 4B, transistor 5, and capacitor 10. In this conventional current limiting apparatus 200, its one end is connected to a load 11 structured by a DUT (Device Under Test).
Initially, the structure of this conventional current limiting circuit 200 will be described below. The CPU 1 is connected to the D/A converter 2A and D/A converter 2B, and an output terminal of the D/A converter 2A is connected to a reversal input terminal of the operational amplifier 4A through the resistor 3A. Further, non-reversal input terminal of the operational amplifier 4A is electrically grounded. The output terminal of the operational amplifier 4A is connected to one end of the capacitor 10 and the load 11. Further, the other end of the capacitor 10 is electrically grounded. One end of the capacitor 10 and the load 11 are connected to the reversal input terminal of the operational amplifier 4A through a feedback resistor 3B. Thereby, a negative feedback closed loop is formed between the output terminal and the reversal input terminal of the operational amplifier 4A.
Further, the operational amplifier 4A has a current limiting adjustment terminal A, and the current limiting adjustment terminal A is connected to the collector terminal of the transistor 5. The output terminal of the operational amplifier 4B is connected to the base terminal of the transistor 5, and the output terminal of the D/A converter 2B is connected to the non-reversal input terminal of the operational amplifier 4B. The emitter terminal of the transistor 5 is connected to a negative source terminal B through the resistor 3D. Further, the emitter terminal of the transistor 5 is connected to the reversal input terminal of the operational amplifier 4B. Thereby, the negative feedback closed loop is formed between the output terminal of the operational amplifier 4B and the reversal input terminal of the operational amplifier 4B through the emitter terminal of the transistor 5.
Next, the operation of the conventional current limiting apparatus 200 in FIG. 5 will be described. The function of this conventional current limiting apparatus 200 can be divided into 2 kinds of functions, that is, the current limiting function to limit the output current IO of the operational amplifier 4A by the CPU 1, and the function in which the input voltage VIN is set by the CPU 1, and the current IO required by the load 11 is supplied from the operational amplifier 4A.
Initially, the function to limit the output current IO will be described. The CPU 1 sets the voltage to limit the output current IO of the operational amplifier 4A by the digital signal, and outputs to the D/A converter 2B. The D/A converter 2B converts the inputted digital signal into analog signal, and outputs to the non-reversal input terminal of the operational amplifier 4B. When this analog signal is inputted, the operational amplifier 4B generates the potential difference between the base and emitter of the transistor 5, and the current flows from the base to the emitter. Thereby, the transistor 5 is operated, and the limiting current IA flowing through the current limiting adjustment terminal A of the operational amplifier 4A is determined according to the relationship of the negative source terminal B, emitter voltage, and resistor 3D.
When the resistance value of the resistor 3D is RD, and the voltage value of the negative source terminal B is VB, then, the emitter voltage of the transistor 5 is set by the digital signal outputted from the CPU 1, and is equal to the voltage value VC converted into the analog value by the D/A converter 2B, therefore, the limiting current IA flowing in the current limiting adjustment terminal A is
IA=(VCxe2x88x92VB)/RDxe2x80x83xe2x80x83(1).
As described above, by limiting the current flowing in the current limiting adjustment terminal A of the operational amplifier 4A, the output current IO of the operational amplifier 4A is limited so that the input current into the load 11 is not excessive. Further, the following relationship exists between the output current IO of the operational amplifier 4A and the limiting current IA flowing in the current limiting adjustment terminal A:
IO=IAxc2x7Gxe2x80x83xe2x80x83(2).
Herein, G is a current amplification factor of the operational amplifier 4A. By using the above expressions (1) and (2), the following relational expression is obtained between the current limit voltage VC set by the CPU 1 and the output current IO:
IO=Gxc2x7(VCxe2x88x92VB)/RDxe2x80x83xe2x80x83(3).
In this expression (3), as shown in FIG. 6, the output current IO has a proportional relationship to the current limit voltage VC set by the CPU 1.
Next, the function to supply the current to the load 11 in the setting of the input voltage will be described. In the conventional current limiting apparatus 200, the CPU 1 sets the digital signal corresponding to the input setting voltage and outputs to the D/A converter 2A, and the D/A converter 2A converts the inputted digital signal into the analog signal and outputs to the resistor 3A. This analog signal is inputted into the reversal input terminal of the operational amplifier 4A through the resistor 3A, and this operational amplifier 4A amplifies the output voltage to the input setting voltage corresponding to this inputted analog signal. The voltage amplified by the operational amplifier 4A is outputted to the load 11, and the operational amplifier 4A outputs the current IO to be supplied to the load 11. In this case, the capacitor 10 is charged when the output current flows.
Herein, when the value of the voltage inputted into the reversal input terminal of the operational amplifier 4A by the digital signal outputted by the CPU 1, is VIN, the resistance value of the resistor 3A is R1, and the resistance value of the feedback resistor 3B is R2, then, the value VO of the voltage supplied to the load 11 is as follows:
VO=xe2x88x92(R2/R1)xc2x7VINxe2x80x83xe2x80x83(4).
By this expression (4), the output voltage VO is determined by the input setting voltage VIN. When the capacity of the capacitor 10 is C, the value of the output current is IO, and the value of the output voltage is VO, then, the time t necessary for charging the capacitor is,
t=(Cxc2x7VO)/IOxe2x80x83xe2x80x83(5),
and when the expression (4) is substituted into the expression (5), it can be clear that the time t necessary for charging the capacitor is, as shown by the following expression, formed of the relationship of the input voltage VIN and output current IO:
t=xe2x88x92Cxc2x7(R2/R1)xc2x7(VIN/IO)xe2x80x83xe2x80x83(6)
As described above, when the input voltage VIN is set by the CPU 1, because C, R1, and R2 are respectively known capacity of the capacitor 10, resistance values of the resistors 3A and 3B, the time t necessary for charging the capacitor 10 depends on only the output current IO.
FIG. 7 is a view showing the relationship of t xe2x88x92IO in the expression (6). As can be clearly seen from FIG. 7, the output current IO and the time t are in inversely proportional relationship to each other. In the case where the charging current for charging the capacitor 10 is IC, when the output current IO is smaller than the charging current IC, because a long period of time is necessary for charging the capacitor 10, the time t for supplying the current to the load 11 is increased.
However, in the conventional current limiting apparatus 200, by outputting the digital signal from the CPU 1 to the operational amplifier 4B through the D/A converter 2B, when the limiting current IA of the operational amplifier 4A is set, the output current IO of the operational amplifier 4A is limited by the limiting current IA, and when the current is supplied to the load 11, the current is limited lower than the current drive capacity. That is, when the current required by the load 11 is supplied, as the limiting current IA flowing from the current limiting adjustment terminal A set by the CPU 1 is closer to the limited output current IO, the current drive capacity is close to the limit, and there is a problem that a long period of time is necessary for reaching the current required by the load 11.
As the result, when the input voltage VIN is applied, because the current satisfying the load 11 is limited by the limiting current IA, the output voltage VO becomes a function proportional to the t1 in FIG. 8. Further, when the capacitor 10 is added to absorb the fluctuation of the voltage supplied to the load 11, because the time to charge the capacitor 10 is necessary, for the current to charge the capacitor 10, due to the limiting current IA, the output voltage has the relationship of the integral function proportional to the time t2 shown in FIG. 8, and there is also a problem that the time for supplying the current to the load 11 is further increased.
Furthermore, even when the maximum current of the operational amplifier 4A is sufficiently larger than the output current IO limited by the CPU 1, and the current drive capacity of the operational amplifier 4A is sufficient, the output current IO is limited by the limiting current IA set by the CPU 1.
A problem of the present invention is to provide a current limiting apparatus by which the setting voltage can be supplied onto the load more quickly, without the output current being limited by the limiting current of the operational amplifier.
In order to solve the problems, in the invention according to the first aspect, a current limiting apparatus, in which a power source signal output means (for example, a D/A converter 2A in FIG. 1) for outputting a voltage signal to supply a power source to a sample to be measured (for example, a load 11 in FIG. 1), a signal amplifying means (for example, a reversal amplifier circuit structured by resistors 3A and 3B and an operational amplifier 4A in FIG. 1) for amplifying the voltage signal outputted by the power source signal output means, a power source fluctuation absorption means (for example, a capacitor 10 in FIG. 1) for absorbing the fluctuation of the power source supplied to the sample to be measured by the voltage signal amplified by the signal amplifying means, and an amplification factor setting means (for example, a D/A converter 2B, operational amplifier 4B, transistor 5, and resistor 3D in FIG. 1) for setting a amplification factor in the signal amplifying means, are provided, the current limiting apparatus is characterized in that, it has: a current detection means (for example, a current detection circuit 7 to detect the current flowing through a resistor 3C in FIG. 1) for detecting a current value to be inputted into the sample to be measured; a voltage calculation means (for example, a current detection circuit 7 to calculate a voltage value according to a value of the current flowing through the resistor 3C in FIG. 1) for calculating the voltage at the current detection position, according to the current value detected by the current detection means; a voltage setting means (for example, the setting voltage stored in a CPU 1 in FIG. 1) for setting the predetermined voltage; a voltage comparing means (for example, a comparing circuit 8 in FIG. 1) for comparing the voltage value set by the voltage setting means to the voltage value calculated by the voltage calculation means; and an amplification factor changing means (for example, resistors 3E and 3F, a diode 6, and switch 9 in FIG. 1) for changing the setting of the amplification factor of the amplification factor setting means, according to the comparison result of the voltage comparing means.
According to the invention of the first aspect, in a current limiting apparatus, in which a power source signal output means for outputting a voltage signal to supply a power source to a sample to be measured, a signal amplifying means for amplifying the voltage signal outputted by the power source signal output means, a power source fluctuation absorption means for absorbing the fluctuation of the power source supplied to the sample to be measured by the voltage signal amplified by the signal amplifying means, and an amplification factor setting means for setting a amplification factor in the signal amplifying means, are provided, a current detection means detects a current value to be inputted into the sample to be measured; a voltage calculation means calculates the voltage at the current detection position, according to the current value detected by the current detection means; a voltage setting means sets the predetermined voltage; a voltage comparing means compares the voltage value set by the voltage setting means to the voltage value calculated by the voltage calculation means; and an amplification factor changing means changes the setting of the amplification factor of the amplification factor setting means, according to the comparison result of the voltage comparing means.
Further, like as the invention according to the second aspect, in the current limiting apparatus of the first aspect, the amplification factor changing means may be structured such that, when the voltage comparing means detects that the voltage value calculated by the voltage calculation means is larger than the predetermined voltage value set by the voltage setting means, the setting of the amplification factor of the amplification factor setting means is made smaller.
Further, like as the invention according to the third aspect, in the current limiting apparatus of the first or the second aspect, the amplification factor changing means may be structured such that it includes a diode (for example, a diode 6 in FIG. 1) and a switch (for example, a switch 9 in FIG. 1), and by ON/OFF-controlling the switch, the setting of the amplification factor of the amplification factor setting means is changed.
Accordingly, according to the invention of the first aspect to the third aspect, the power source voltage can be quickly applied onto the sample to be measured, and in the overall test, the test time of the sample to be measured can be reduced.


A device may include a transient optical amplifier having stored energy associated with a lower boundary and an upper boundary of a dynamic equilibrium, and a target level defining stored energy for amplifying a high energy input pulse to a higher energy output pulse. The device may include a pump to increase the amplifier's stored energy, and a source to pass low energy control pulses or the high energy input pulse to the amplifier. The device may include a controller configured to maintain the amplifier's stored energy in the dynamic equilibrium by requesting low energy control pulses for the amplifier at a high repetition frequency. The controller may wait to receive a trigger. Based on receiving the trigger, the device may stop passing low energy control pulses to the amplifier, and may pass the high energy input pulse to the amplifier when the amplifier's stored energy reaches the target level.

Short pulse laser systems generate optical pulses having sub-microsecond pulse width and sub-millisecond temporal spacing. As used herein, a short pulse of light is an electromagnetic pulse whose time duration is less than a microsecond (10−6 seconds). Short pulse laser systems include ultrashort pulse laser systems (or conversely ultrafast laser systems) such as nanosecond, picosecond and femtosecond laser systems and other laser systems that can produce amplified optical pulses with sub-microsecond pulse width and sub-millisecond temporal resolution.
In conventional short pulse laser systems, high energy pulses are produced at a constant frequency and constant energy. Changing the time between pulses in such lasers can produce significant differences in the energy of each pulse with the potential for damage to the laser or the object to which the pulses are applied. There is a need for short pulsed lasers that can be triggered at any arbitrary time to provide a short duration pulse while controlling the energy of each triggered optical pulse. Such a laser would be advantageous for micromachining and potentially in other fields (e.g., ophthalmology, biomedical imaging, ultrafast spectroscopy, ultra-high-speed optical networks, reaction triggering, femtochemistry, etc.).
Taking conventional ultrafast laser micromachining as just one example, an optical beam is moved on a workpiece to apply the beam in a specific pattern. The beam can be moved, the workpiece can be moved, or both can be moved to trace the pattern. In order to maximize the processing speed, this movement should be as fast as possible; however, the speed is limited by the requirements on the accuracy of the movement. The movement can be very fast for straight lines, but may need to be very slow for small or complex features. The transitions between fast and slow movement occur dynamically, depending on the complexity of the pattern being traced.
When micromachining with ultrafast lasers, the optical beam being applied to the workpiece comprises nanosecond to femtosecond duration optical pulses with a pulse repetition frequency (PRF) in the range of kHz to MHz. Ideally, the energy of each pulse is kept constant and the pulses are evenly spaced in physical location on the workpiece. The spacing of pulses on the workpiece is proportional to the scanning speed (the relative speed between the optical beam and the workpiece) and the time between optical pulses (or inversely, the pulse repetition frequency (PRF) of the optical beam). Because the scanning speed dynamically changes, the time between optical pulses must also dynamically change to keep spacing of pulses constant on the workpiece. Unfortunately, dynamically changing PRF of a conventional amplified ultrafast laser will change the energy of the output optical pulses. In FIG. 1, the solid line is the amplifier's (e.g., the amplifier of a conventional ultrafast laser) stored energy, the input pulses are represented by the filled circles, and the output pulses are represented by the hollow circles. The relative energy level of a pulse is represented by the diameter of its solid or hollow circle.
FIG. 1 graphs the stored energy of an amplifier of a conventional ultrafast laser (such as an ultrafast laser according to U.S. Pat. No. 7,386,019 "Light pulse generating apparatus and method" published Jun. 10, 2008 incorporated herein by reference in its entirety). The solid line represents the amplifier's stored energy over time. The solid circles on the graph represent input pulses entering the amplifier where the size of the solid circle represents the energy of the input pulse. The outlined circles represent output pulses, concentric with their corresponding input pulse, and the size of the hollow circle represents the energy of the output pulse. In the example of FIG. 1, the energy of all input pulses remains the same. Conventionally, and as illustrated for the first three input pulses, the temporal spacing is fixed based on a pulse repetition frequency of a source (e.g., a short pulse laser source, etc.) providing the pulses to the amplifier. For the first three pulses, there is fixed temporal spacing, the stored energy is in dynamic equilibrium, returning to a target level at the same time the next pulse arrives, and the output pulses accordingly have a constant energy level. When the temporal spacing between pulses changes, the amplifier's dynamic equilibrium is broken. Where the time between pulses increases, the amplifier overshoots the target and the energy of the next pulse can be so great that the pulse can damage the laser, the workpiece or other things. When the time between pulses decreases, the amplifier cannot replenish its stored energy to the target level and the energy of the next pulse may be insufficient to perform its task. If the timing of even one pulse is sufficiently off, the amplifier can take a significant amount of time to re-establish its equilibrium. These problems compound as more pulses deviate from a constant temporal spacing, or a constant pulse repetition frequency. Further problems occur if the energy of each input pulse is not held constant.
The lack of arbitrarily timed, or arbitrarily triggered pulsed lasers that keep pulse energy fluctuations sufficiently small, results in compromising on either throughput, quality or system complexity. In many of today's ultrafast laser applications and market areas, this is a very significant limitation. Accordingly, it would be advantageous to have a pulsed laser that can be triggered at arbitrary times, with high temporal resolution, to provide a short duration optical pulse in association with each trigger while being able to control the energy of all the optical pulses.

Gain control for arbitrary triggering of short pulse lasers


A method for initializing an electronic article surveillance (EAS) system which transmits pulses into an interrogation zone and receives signals from the interrogation zone in a sequence of multiple successive transmit and receive windows during each line period of an AC mains supply energizing the EAS system, associated with a corresponding apparatus, comprises the steps of: (a.) determining whether a delay value is stored in a nonvolatile memory; (b.)if the delay value is stored in the nonvolatile memory, loading the stored delay value into a delay control register, terminating the initializing and omitting all remaining steps; (c.) if the delay value is not stored in the nonvolatile memory, loading a first delay value into the delay control register; (d.) determining whether noise in a certain receive window is less than a threshold level; (e.) if the noise is less than the threshold level, terminating the initializing and omitting all remaining steps; (f.) if the noise level is not less than the threshold level, loading a second delay value into the delay control register; (g.) determining if the EAS system is operating properly; (h.) if the EAS system is operating properly, terminating the initializing and omitting all remaining steps; (i.) if the EAS system is not operating properly, loading the first delay value into the delay control register; and, (j.) terminating the initializing.

1. Field of the Invention
This invention relates to the field of pulsed magnetic electronic article surveillance (EAS) systems, and in particular, to generating accurate line synchronized delays for synchronizing operation of multiple EAS systems operating in proximity to one another.
2. Description of Related Art
When multiple pulsed magnetic EAS systems operate in proximity, their transmitter timing windows must never coincide with their receiver timing windows.
In certain pulsed magnetic EAS systems available from Sensormatic Corporation, the operation of such multiple EAS systems is synchronized by sensing the positive zero crossings of the local mains power line. Each line cycle is divided up into six time windows: three for transmission and three for reception, as shown in FIG. 3. The first transmit-receive window sequential pair, designated phase A, occurs at 0.degree. with respect to the zero crossing. The second transmit-receive window sequential pair, designated phase B, occurs at 120.degree. with respect to the zero crossing. The third transmit-receive window sequential pair, designated phase C, occurs at 240.degree. with respect to the zero crossing.
Ideally, two or more systems in proximity sense the same zero crossing and do not interfere with one another. Sometimes, however, the two or more EAS systems are connected to different phases of a building's three phase power supply, and it may be desired to delay one system's zero crossing signal, for example, from phase A to phase B. It can also sometimes happen through a building being mis-wired that two EAS systems can be connected with their respective zero crossings 180.degree. apart. This results in one system's transmitter burst being centered in the other system's receiver window and vice versa. Systems cannot function in this mode. When this happens, the usual approach is to rewire one system's input power leads. The rewiring process is tedious and can be dangerous.
In present Ultra*Max pulsed magnetic EAS systems available from Sensormatic Corporation, reliance has been placed on analog circuitry to produce long zero crossing synchronizing delays. For purposes of the inventive arrangements, long delay times refers to delays of up to one whole period of the power line frequency, namely 16.6 sec for 60 Hz power and 20 msec for 50 Hz power. In designs which did incorporate digital or microprocessor generated delays, these designs utilized digital delays only for fine adjustment of the analog delays.

Line synchronized delays for multiple pulsed EAS systems


A magnetic encoder having a magnetic sensor composed of SVGMR elements, in which a signal output with a half of a cycle of magnetic regions on a magnetic medium. The magnetic encoder comprises the magnetic medium, on which first magnetic regions and second magnetic regions are oppositely magnetized along the medium extending and disposed successively and alternately with each other, and the magnetic sensor that has an even number of SVGMR elements and is movable relatively to the medium along the medium extending. Magnetizations of pinned magnetization layers of all the SVGMR elements are directed in a same direction along the medium extending. Each of the even number of SVGMR elements in the magnetic sensor is apart by a half of the sum of a first magnetic region length plus a second magnetic region length from each other along the medium extending, and the even number of SVGMR elements are connected in series so that a cycle of resistance change of the magnetic sensor is a half of a cycle length of the first and the second magnetic regions on the medium and the signal output with high resolution can be obtained.

1. Field of the Invention
The present invention relates to a magnetic encoder using a magnetic sensor with a spin-valve type giant magneto-resistance effect film.
2. Description of the Related Art
In recent years, a magnetic encoder applied to civil appliances, such as small-sized robots, digital cameras and ink-jet printers, is required not only to be cheap and small-sized but also to have a high resolution and excellent gap output characteristics. In other words, it is required that a magnetic encoder is small-sized but does not need a processing circuit for doubling frequency of signal and also can maintain a stable output against gap variation during its operation. Further, low electric power consumption is required.
In a conventional magnetic encoder, magnetic resistors formed from an anisotropic magneto-resistance effect film (hereinafter referred to as "AMR element") are applied. The AMR elements are widely used, because electric resistance is changed by some percent by a magnetic field change in them even in a region of a relatively small magnetic field, and because their films are easily produced. However, it is necessary to thicken the film to 20 nm to 40 nm, in order to obtain a stable magneto-resistance effect for the AMR elements having NiFe alloy thin film or NiCo alloy thin film. But, they are difficult to use, since electric resistance of the elements reduces due to the thicker film. If a width dimension of the AMR element is reduced to increase the resolution, a shape anisotropy (Hk) is increased together with an influence of the thicker film and a sufficient electric resistance change cannot be obtained in a region of a weak magnetic field to cause an expected electric output. Because of the reason, it was difficult to enhance the resolution in a magnetic encoder using AMR elements. Increase of the resolution means narrowing pitches of the elements and/or magnetizations on a medium and also increase of a number of the electric output signals for a unit length.
Instead of the AMR elements, which are difficult to enhance resolution, an element using a coupled giant magneto-resistance effect film (hereinafter referred to as "coupled GMR element") is disclosed in Japanese Patent 2812042. The coupled GMR element has an electric resistance variation ratio as much as twice to four times of the AMR element. In the coupled GMR elements described in Japanese Patent 2812042, an artificial lattice metallic film having some-ten layers of alternately laminated NiCoFe thin films and non-magnetic metal thin films is used. Multiple lamination of the ferro-magnetic thin films and the non-magnetic metal thin films leads to a large magneto-resistance variation ratio. However, it is difficult to accomplish a low electric power consumption, since the non-magnetic metal thin films are a good electrically conductive material and the electric resistance of the film is as low as a half to a third of that of an AMR element. The coupled GMR elements have an electric resistance variation ratio as much as 20% to 30%, but the electric resistance variation ratio can be obtained only by using them in a large magnetic field. By the reason, it was hard to use them in a relatively small magnetic field as in a magnetic encoder.
There is a spin-valve type giant magneto-resistance effect film as used in a magnetic head of a hard disk storage device (HDD), which is a film showing, in a region of a relatively small magnetic field, an electric resistance variation ratio as much as a coupled GMR element. As described in Japanese Patent 3040750, the spin-valve type giant magneto-resistance effect film is composed of a pinned magnetization layer, in which a magnetization direction is not changed by a variation on an external magnetic field (or magnetic flux) direction, a non-magnetic conductive layer and a free magnetization layer, in which a magnetization direction is changed following a variation of an external magnetic field. An element machined from a spin-valve type giant magneto-resistance effect film (hereinafter referred to as "SVGMR element") has an electric resistance as large as five times to six times of that of the coupled GMR element, and reduction of electric power consumption is easily achieved when it is used for a magnetic sensor. Also, it can work in a region of a magnetic field as relatively small as 1 A/m to 160 A/m, that is, about 0.006 Oe to 20 Oe.
However, a magnetic encoder has a disadvantage that resolution is reduced by only a substitution of the SVGMR elements for AMR elements and coupled GMR elements. When the SVGMR elements are used with a magnetic medium alternately magnetized with N-poles and S-poles with a magnetized pitch λ, a signal has an output cycle of 2λ that is twice of the magnetized pitch. In other words, the resolution becomes a half. This is caused by a magneto-resistance variation characteristic, and the reduction in the resolution cannot be avoided in a conventional encoder structure.
This is because the SVGMR elements have characteristic that electric resistance of the elements changes when an external magnetic field is applied in a same direction as magnetizations of pinned magnetization layers in the elements, while it does not change when the external magnetic field is applied oppositely. Or, because the SVGMR elements have characteristic that electric resistance of the elements does not change when an external magnetic field is applied in a same direction as magnetizations of pinned magnetization layers in the elements, while it changes when the external magnetic field is applied oppositely. When a magnetic medium is magnetized with a magnetized pitch λ, a magnetic field direction changes for every λ. Because of that, electric resistance of SVGMR elements changes with a cycle of 2λ that is twice of the magnetized pitch. By contrast, using coupled GMR elements or AMR elements provides an electric signal of a cycle of λ. The coupled GMR elements and AMR elements show maximum electric resistances in a state of no magnetic field, and the electric resistances reduce when an external magnetic field increases. That is, regardless of a magnetic field direction, a signal is caused by increase and decrease of magnetic field intensity. From the reason, an electric signal of the same cycle as the magnetized pitch λ can be obtained. SVGMR elements have not been applied to a magnetic encoder because they hardly satisfy a high resolution that is demanded in a market. However, since the SVGMR elements show a magneto-resistance variation ratio as much as in coupled GMR elements in a region of a relatively small magnetic field and also an electric resistance as large as five times to six times that of the coupled GMR elements, it is hard to give up an advantage that a low electric power consumption can be easily accomplished by the SVGMR elements.


Soldering system includes a first soldering device having a control apparatus that has a central microcontroller and/or microprocessor and is designed for controlling at least one operating parameter of the soldering device, wherein a radio module is provided which includes a communication module designed for setting up a wireless data connection, and at least a second soldering device having a control apparatus that has a central microcontroller and/or microprocessor and is designed for controlling at least one operating parameter of the soldering device, wherein a radio module is provided which comprises a communication module designed for setting up a wireless data connection.

The invention relates to a soldering system, comprising at least two soldering devices. Soldering devices are in particular a soldering station for manual soldering or for robot-operated soldering or desoldering, a rework system, a solder bath, a hot plate or a solder-fume extraction device, comprising a control apparatus that has a central microcontroller and/or microprocessor and is designed for controlling at least one operating parameter of the soldering device. The invention further relates to a method for operating a soldering system of this type.
Soldering devices of the type mentioned at the outset are widely known from the prior art. Soldering devices for manual soldering which comprise a soldering iron, a desoldering iron or a hot air gun are commonly known as soldering stations. It is conceivable in this case for the soldering iron to be operated manually or by robot.
Solder-fume extraction devices are used for extracting vapors or soldering fumes which result from soldering or desoldering. The solder-fume extraction devices typically comprise a filter and a fan wheel which is driven by a speed-controlled electric motor.
Soldering devices designed as hot plates are apparatuses for heating a printed circuit board to be processed during manual or robot-operated soldering.
Rework systems or rework apparatuses refer to soldering devices used in the context of prototyping and the repair of electronics. Rework systems of this type typically comprise a plurality of motor-driven or manually driven shafts. The rework systems known from the prior art further comprise heating apparatuses, in particular heating apparatuses for heating a working space which are arranged above and below the working space, grip apparatuses arranged on the shafts, and cameras and sensors for process monitoring, such as temperature sensors.
Said soldering devices known from the prior art are often used together. It is therefore known e.g. to extract vapors or soldering fumes occurring in a rework system by means of a solder-fume extraction device. Moreover, it is known to use a soldering station together with the hot plates mentioned at the outset, and to likewise extract vapors or soldering fumes which result from soldering or desoldering by means of a solder-fume extraction device.
Some of the known soldering devices can be interconnected by means of cables, such that it is possible to operate a solder-fume extraction device or a hot plate only when the soldering station is also being operated for soldering or desoldering, or when a rework system is being operated. Since the apparatuses in question are therefore operated only when necessary, energy can be saved.
US 2015/0246404 A1 shows a soldering device, which comprises a control unit, which communicates via a radio connection with a power supply unit of the soldering device.
However, it is evident from the soldering devices known from the prior art that connecting the different soldering devices by means of cables results in a considerable amount of wiring being required at the particular work location, and that, owing to the connection by means of wires, the soldering devices are not particularly flexible in terms of the use thereof.


A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for accessing the first latch circuit, the buffer circuit transferring, to the second region, the initialization data transferred from the first latch circuit, and transferring, to the first latch circuit, the initialization data transferred form the second region.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that operates using, for example, initialization data.
2. Description of the Related Art
Semiconductor memory devices for use in mobile apparatuses, such as cell-phones, employ a technique for reducing the consumption of power during a standby state by cutting the current paths of peripheral circuits connected to a memory cell array and memory bank that are not accessed. In these semiconductor memory devices, the peripheral circuits that are not accessed are set in a low power-consumption state called a sleep mode. To realize the sleep mode, a switching element (e.g., a transistor) is provided across each current path, and is turned on or off to close or open each current path.
A redundancy function for rescuing a defective cell in a memory cell array using a redundancy-circuit is well known. Redundancy data used for the redundancy function is, for example, transferred, upon turn-on of the power supply, from a nonvolatile element provided outside a semiconductor memory device.
When the sleep mode is employed for a semiconductor memory device having such the redundancy function, the consumption of power can be reduced by interrupting the supply of current to peripheral circuits (such as a sense amplifier circuit, DQ buffer, column redundancy circuit, IO buffer and row decoder). However, if the current path of a circuit that latches row redundancy data is cut, the row redundancy data is lost. In this case, initialization processing must again be performed, therefore a considerable time is required to recover the device. Further, initialization processing itself inevitably interferes with access to a memory cell array or other macros that are not in the sleep mode.
Latch circuits that must retain data in the sleep mode include, as well as that for redundancy data, a latch circuit for, for example, data used to control operation timing or an operation voltage. In particular, in the case of dynamic random access memories (DRAMs), a large number of data items must be retained in the sleep mode. Therefore, unless the supply of current to the circuits that retain the data items is interrupted, reduction of power consumption in the sleep mode cannot be realized.
A semiconductor integrated circuit having a data retaining function for reducing the consumption of current is disclosed as a technique relevant to the above (see Jpn. Pat. Appln. KOKAI Publication No. 2002-56671).

Semiconductor memory device operating using read only memory data


A design structure for a circuit providing the same trigger voltage across the multiple fingers is provided, which comprises a data representing an external current injection source connected to individual fingers of a multi-finger semiconductor device. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

In typical CMOS circuitry, semiconductor devices with multiple fingers are utilized and distributed over a wide area of a chip for various purposes. The multifinger semiconductor devices can also be considered multiple parallel devices with a common control component, such as a gate of a transistor or a thyristor. A typical example is an electrostatic discharge (ESD) protection circuit that requires placement of multiple fingers of a MOSFET in a parallel connection that is spread over a chip. In this case, distribution of multiple fingers across the chip area is not only advantageous but necessary to provide maximum protection against a potential electrostatic discharge event that might happen anywhere on the chips. By connecting the sources and drains of the individual fingers in a parallel connection to form a large multifinger gate-grounded NMOSFET (GGNMOSFET), the ESD device can handle a higher amount of electrostatic charge than any individual finger.
In an ESD event, it is preferred that all the fingers of a multifinger ESD protection MOSFET turn on to maximize the charge handling capacity of the ESD circuit since the magnitude of voltage spike on the circuit is inversely proportional to the amount of current the multifinger ESD protection MOSFET can pass. However, the multiple fingers of the ESD protection MOSFET typically do not turn on simultaneously due to differences in circuit parameters among the multiple fingers. To make matters worse, once a finger turns on, the voltage on the drain, which is shared by all the fingers in the multifinger MOSFET, snaps back to a lower value, preventing a turn on of the remaining fingers. In this case, the amount of current the ESD protection MOSFET can pass is limited to the current that the one turned-on finger can pass.
FIG. 1 shows a semiconductor chip with an ESD protection MOSFET circuit provided with multiple fingers that are distributed over the chip area. One finger 10 of the ESD protection MOSFET is circled with references made to the drain 12, gate 14, and source 18. The substrate ring contact 19, or the guard ring is shown in FIG. 1 as well. The source of each finger 10 of the ESD protection MOSFET electrically contacts the substrate ring contact 19 to ground the ESD protection circuit.
FIG. 2A shows an electrical circuit comprising a finger 20 of an ESD protection NMOSFET along with an I/O pad 21. The gates of the fingers are tied together and connected to the ground, forming a gate-grounded NMOSFET (GGNMOSFET) configuration. The finger 20 comprises a drain 22, a gate 24, a source 28, a parasitic npn bipolar transistor, and a parasitic resistor 27. Also, a parasitic impact ionization current source 23 is shown between the body 26 and the drain 22 of the finger 20.
The parasitic npn bipolar transistor and the parasitic resistor 27 result from the physical structure of the finger 20 of the ESD protection NMOSFET. In a typical CMOS circuit, NFETs are built in the P-substrate with an n-doped source 28 and an n-doped drain 22. The source 28, the body 26, and the drain 22 of an NFET therefore form a parasitic npn bipolar transistor, with the source 28 being the emitter, the body 26 being the base, and the drain 22 being the collector. Since the semiconductor material forming the source 28 and the body 26 has a finite resistance, there is a parasitic resistance between the source 28 and the body 26 of each finger. Also, since the source 28 is tied to a substrate ring contact 19 that is placed around the periphery of the chip area, there is a finite resistance between the source 28 and the substrate ring contact (not shown explicitly in FIG. 2A). The parasitic resistance 27 reflects the two parasitic resistances mentioned above and has a resistance value for the path from the body 26 to the substrate ring contact. The circuit in FIG. 2 therefore reflects the parasitic components of a physical finger 10 of the ESD protection NMOSFET circuit shown in FIG. 1.
The impact ionization source 23 simulates the parasitic impact ionization current in the reversed biased junction between the body 26 and the drain 22 of one finger of the NMOSFET. This occurs naturally since the drain 22 is N-doped and the body 26 is in a P-doped substrate while a more positive voltage is applied to the drain 22 relative to the body 26 and thus forming a reversed biased diode. This current can be modeled as an exponential function of the drain-to-body voltage.
Examination of FIGS. 1 and 2A shows the source of the differences in the circuit parameters among the various fingers 10 of an ESD protection NMOSFET. Even if the non-parasitic characteristics of each finger 10 of the ESD protection NMOSFET is matched, the parasitic components are different. Specifically, the resistance of the parasitic resistor 27, or the "substrate resistance," heavily depends on the location of the finger since it includes the resistance between the source 28 and the substrate ring contact 19. A finger nearer to the substrate ring contact 19 has a lower parasitic resistance than another finger that is farther away from the substrate ring contact. However, multiple fingers are generally required to handle the large amount of current during an ESD event. To turn on the multiple fingers of an ESD protection NMOSFET during an ESD event at the same time, the trigger voltage, or the voltage at the drain 22 of a finger 20 above which the finger 20 turns on, needs to be matched.
A study demonstrating a nonuniform turn-on of a multi-finger ESD protection MOSFET is shown in Lee et al., "The Dynamic Current Distribution of a Multi-fingered GGNMOS under High Current Stress and HBM ESD Events," IEEE 44th IRPS, 2006, pp. 629-630. Lee et al. observed that during the initial transient of an ESD discharge, the current distribution is non-uniform in a GGNMOSFET according to the measurements performed on a nanosecond time scale.
A first prior art solution to this problem is to add drain ballasting resistance to individual fingers of an ESD protection MOSFET. However, this approach requires a large area of semiconductor substrate for such drain ballasting resistors. Furthermore, the addition of drain ballasting resistors adds large on-resistance in the circuit, effectively reducing the current capacity of the ESD protection MOSFET and thus, requiring a large clamping voltage.
A second prior art solution disclosed in Duvvury, "Substrate Pump NMOS for ESD Protection Applications," Proc. EOS/ESD Symp, 2000, 2000, pp. 1A.2.1-11, utilizes a substrate pump to achieve a uniform triggering voltage for a multi-finger NMOS ESD circuit. A third prior art solution disclosed in Mergens et al., "Multi-finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance and Width-Scaling," Proc. EOS/ESD Symp, 2001, pp. 1-11, uses a domino-type NMOS multi-finger transistor wherein the source of a finger is connected to the gate of an adjacent finger in a cascade configuration.
While the prior art solutions tend to equalize the trigger voltages across the multiple fingers, they also tend to introduce additional resistance to the circuit. Additionally, the semiconductor area used for the prior art solutions are significant. Also, the ability to tune the trigger voltage so that a circuit would turn on at a predetermined bias voltage is also desired.
While the discussions above is limited to multi-fingered GGNMOSFETs, there is also need to control the turn-on of other multi-fingered devices such as general NMOSFETs, general PMOSFETs, and thyristors, especially when the multiple fingers of such devices are spread over a large area of a chip.
FIG. 2B shows an electrical circuit comprising a finger 20B of a PMOSFET with an I/O pad 21. The finger 20B comprises a drain 22B, a gate 24B, a source 28B, a body 26B, which is also the base of a parasitic pnp bipolar transistor, and a parasitic resistor 27B. An impact ionization current source 23 is present between the body 26B and the drain 22 B in this circuit.
FIG. 2C shows an electrical circuit comprising a finger 20C of a multi-finger thyristor with an I/O pad 21. A thyristor has a pnpn semiconductor structure. In a typical thyristor, the outer p-doped region is the anode and is connected to a positive power supply, the outer n-doped region is the cathode and is connected to a negative power supply, and the inner p-doped region is the gate and is connected to a control input. The finger 20C comprises an anode 22C, a gate 26C, a cathode 28C, and a parasitic resistor 27C. Also, an impact ionization current source 23C is a built-in component of the thyristor between the gate 26C and the cathode 28C of the finger 20C since the thyristor contains a reverse biased PN junction between the anode 22C and the gate 26C. The multiple fingers of a thyristor need to turn on at the same time to fully utilize the current capacity of the thyristor. An alternate configuration wherein the gate is connected to the inner n-doped region and corresponding alteration of circuit is herein contemplated.
In FIG. 3, an exemplary prior art ESD protection NMOSFET circuit is shown, wherein five fingers (30A-30E) are connected in a parallel connection. One end of the parallel connection of five fingers which connect the drain of each finger is connected to an I/O pad 31, which is connected to a positive power supply. The other end of the parallel connection of five fingers which connect the source of each finger is connected to a substrate ring contact 39, which is connected to ground.
Each of the fingers (30A-30G) has a parasitic bipolar transistor wherein the base (36A-36E) is the body of each finger, a parasitic injection source (33A-33E), and a parasitic resistor (37A-37E). If a design layout for each finger (30A-30E) is the same, each finger (30A-30G) has substantially the same amount of parasitic injection current. However, due to the differences in the physical resistive paths between the body (36A-36B) of each finger and the substrate ring contact 39, the resistance values of the parasitic resistors (37A-37E) are different from finger to finger. This results in variations in the trigger voltage, i.e., the voltage at the drain above which each finger to turn on. As described above, non-uniform trigger voltages across the fingers can lead to a condition wherein not all of the fingers are turned on during an ESD event.
The above problem is generic across semiconductor devices of which the trigger voltage, or the turn-on voltage, is dependent on the value of a parasitic resistance of the device. Other than multi-finger ESD protection NMOSFETs, multi-finger NMOSFETs in general, multi-finger PMOSFETs in general, and multi-finger thyristors in general have a parasitic resistance dependent trigger voltages for their fingers, and as a consequence, not all of the fingers may turn on when the device needs to be turned on.
Therefore, there exists a need for a structure and circuit technique for achieving a uniform turn-on of multi-fingered semiconductor devices without adding resistive components or with a minimal addition of resistive components.
There also exists a need for a structure and circuit technique for achieving a uniform turn-on of multi-fingered semiconductor devices with a minimal additional area for the added circuit components.
Furthermore, there exists a need for a structure and circuit technique for tuning a turn-on voltage, or a trigger voltage, of multi-fingered semiconductor devices.

Design structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage

International Business Machines Corporation


A device for the operation of a valve (5) to the combustion chamber (6) of a combustion engine, wherein the combustion engine comprises a cylinder, a piston (3) displacably arranged in the cylinder (2), and a combustion chamber (6) delimited by the cylinder (2) and the piston (3), and said valve (5), and wherein the device comprises a valve actuator (7) that comprises an actuator chamber (8), an actuator piston (9) displacably arranged in the latter and arranged to drive the valve (5), and a communication channel (11) through which a pressure fluid is conducted into the combustion chamber (8) for the driving of the actuator piston (9) and, thereby, the valve (5) in a direction in which the valve (5) is opened. The communication channel (11) extends from the combustion chamber (6) to the actuator chamber (8), and said pressure fluid comprises fluid pressurized by the pressure in the combustion chamber (6).

It is a well known fact that the more a combustion engine provided with opened valves in the cylinder head is loaded, and the higher will the cylinder pressure be when the outlet valves are to be opened and the more energy will be required for the opening thereof. This fact is regardless of the method used for the opening of the valves. A problem encountered by a pneumatically, electromagnetically or hydraulically activated valve opening, but not encountered by cam shaft activated valve opening, is the opening against high cylinder pressures upon evacuation of combustion gases. The main problem is that the dimensioning of the valve opening power has to be adopted to the highest cylinder pressure instead of the most common cylinder pressure, which is substantially lower than the highest pressure. If the operation of the valve is done by a means such as a pressure fluid or an electromagnet, the power of this means must, with contemporary technology, be dimensioned in order to be able to perform a valve opening against the force generated by the maximum cylinder pressure. It would be desirable to reduce this need of over dimensioning.
Furthermore, a high pressure in the cylinder will, when the exhaust gases are evacuated, result in a waste of energy in the sense that a possible expansion work is not made use of (however if there is a turbo, some of the energy will be made use of).
The motor-braking technique for vehicles can be developed as to capacity and controllability, and for power-saving purposes. In vehicles with combustion engines such as heavy lorries, motor-braking is actively used as a supplement to the ordinary braking system. One such method comprises exhaust gas-braking, by which the evacuation of the exhaust gases out of the cylinder of the engine is inhibited. As an alternative, air is permitted to leak out into the exhaust gas system during the compression strokes. A problem of the methods as of today is the fact that a maximum braking effect and the possibility of controlling the braking effect is unsatisfactory. In connection to this problem, and with relevance for light vehicles, there is a possibility of storing brake energy upon motor-braking. There are known suggestions of how to conduct compressed air to a tank upon motor-braking, and to use the stored energy when there is a subsequent need of acceleration. There is a common feature of both light weight and heavy weight vehicles that a good controllability and high brake efficiency and energy saving by means of compressed air is enabled through the use of freely operable valves in the cylinder head of the engine. In this context, upon use of freely operable valves, it might be a problem that the cylinder pressure will be high during compression strokes, resulting in a need of a large amount of energy for the purpose of opening the valves. A large engine load is another operation mode that presents a relatively high cylinder pressure when the exhaust gases are to be evacuated.

Method and device for the operation of a valve of the combustion chamber of a combustion engine, and a combustion engine


A method of transmitting a wireless signal (FIGS. 3A-3C) is disclosed. A data stream is divided (306) into a first data stream and a second data stream. The first data stream is encoded (300) at a first data rate. The second data stream is encoded (320) at a second data rate different from the first data rate. A first part of the encoded first data stream is transmitted from a first transmit antenna (308). A second part of the encoded first data stream is transmitted from a second transmit antenna (312).

The present embodiments relate to wireless communications systems and, more particularly, to Multiple-input Multiple-output (MIMO) communication with Per Group Rate Control (PGRC).
Wireless communications are prevalent in business, personal, and other applications, and as a result the technology for such communications continues to advance in various areas. One such advancement includes the use of spread spectrum communications, including that of code division multiple access (CDMA) which includes wideband code division multiple access (WCDMA) cellular communications. In CDMA communications, user equipment (UE) (e.g., a hand held cellular phone, personal digital assistant, or other) communicates with a base station, where typically the base station corresponds to a "cell." CDMA communications are by way of transmitting symbols from a transmitter to a receiver, and the symbols are modulated using a spreading code which consists of a series of binary pulses. The code runs at a higher rate than the symbol rate and determines the actual transmission bandwidth. In the current industry, each piece of CDMA signal transmitted according to this code is said to be a "chip," where each chip corresponds to an element in the CDMA code. Thus, the chip frequency defines the rate of the CDMA code. WCDMA includes alternative methods of data transfer, one being frequency division duplex (FDD) and another being time division duplex (TDD), where the uplink and downlink channels are asymmetric for FDD and symmetric for TDD. Another wireless standard involves time division multiple access (TDMA) apparatus, which also communicate symbols and are used by way of example in cellular systems. TDMA communications are transmitted as a group of packets in a time period, where the time period is divided into time slots so that multiple receivers may each access meaningful information during a different part of that time period. In other words, in a group of TDMA receivers, each receiver is designated a time slot in the time period, and that time slot repeats for each group of successive packets transmitted to the receiver. Accordingly, each receiver is able to identify the information intended for it by synchronizing to the group of packets and then deciphering the time slot corresponding to the given receiver. Given the preceding, CDMA transmissions are receiver-distinguished in response to codes, while TDMA transmissions are receiver-distinguished in response to time slots.
Referring to FIG. 4, there is a wireless communication system or the prior art including a transmitter and user equipment 450-454. The transmitter includes a separate buffer 440-444 for each respective user equipment 450-454. Data from these buffers is applied to serial-to-parallel converter circuit 410. The serial-to-parallel circuit 410 converts the serial data streams into parallel data words which are then applied to modulation code scheme (MCS) circuits 400 and 404. The modulation code scheme circuits 400 and 404 transmit the signals via respective antennas 402 and 406 to user equipment within the wireless system. For example, a signal 462 from antenna 402 is transmitted to UE 1 450. Likewise, a signal 468 is transmitted from antenna 406 to UE 3 454. Antennas 402 and 406, however, also transmit respective interference signals 466 and 464. These interference signals degrade the intended data signal at the user equipment.
Wireless communications are also degraded by the channel effect. For example, the transmitted signals 462 and 468 in FIG. 4 are likely reflected by objects such as the ground, mountains, buildings, and other things that it contacts. Thus, when the transmitted communication arrives at the receiver, it has been affected by the channel effect as well as interference signals. Consequently, the originally-transmitted data is more difficult to decipher. Various approaches have been developed in an effort to reduce or remove the channel effect from the received signal so that the originally-transmitted data is properly recognized. In other words, these approaches endeavor to improve signal-to-interference+noise ratio (SINR), thereby improving other data accuracy measures (e.g., bit error rate (BER), frame error rate (FER), and symbol error rate (SER)).
One approach to improve SINR is referred to in the art as antenna diversity, which refers to using multiple antennas at the transmitter, receiver, or both. For example, in the prior art, a multiple-antenna transmitter is used to transmit the same data on each antenna where the data is manipulated in some manner differently for each antenna. One example of such an approach is space-time transmit diversity (STTD). In STTD, a first antenna transmits a block of two input symbols over a corresponding two symbol intervals in a first order while at the same time a second antenna transmits, by way of example, the complex conjugates of the same block of two symbols and wherein those conjugates are output in a reversed order relative to how they are transmitted by the first antenna and the second symbol is a negative value relative to its value as an input.
Another approach to improve SINR combines antenna diversity with the need for higher data rate. Specifically, a Multiple-input Multiple-output (MIMO) system with transmit diversity has been devised, where each transmit antenna transmits a distinct and respective data stream. In other words, in a MIMO system, each transmit antenna transmits symbols that are independent from the symbols transmitted by any other transmit antennas for the transmitter and, thus, there is no redundancy either along a single or with respect to multiple of the transmit antennas. The advantage of a MIMO scheme using distinct and non-redundant streams is that it can achieve higher data rates as compared to a transmit diversity system.
Communication system performance demands in user equipment, however, are often dictated by web access. Applications such as news, stock quotes, video, and music require substantially higher performance in downlink transmission than in uplink transmission. Thus, MIMO system performance may be further improved for High-Speed Downlink Packet Access (HSDPA) by Orthogonal Frequency Division Multiplex (OFDM) transmission. With OFDM, multiple symbols are transmitted on multiple carriers that are spaced apart to provide orthogonality. An OFDM modulator typically takes data symbols into a serial-to-parallel converter, and the output of the serial-to-parallel converter is considered as frequency domain data symbols. The frequency domain tones at either edge of the band may be set to zero and are called guard tones. These guard tones allow the OFDM signal to fit into an appropriate spectral mask. Some of the frequency domain tones are set to values which will be known at the receiver, and these tones are termed pilot tones or symbols. These pilot symbols can be useful for channel estimation at the receiver. An inverse fast Fourier transform (IFFT) converts the frequency domain data symbols into a time domain waveform. The IFFT structure allows the frequency tones to be orthogonal. A cyclic prefix is formed by copying the tail samples from the time domain waveform and appending them to the front of the waveform. The time domain waveform with cyclic prefix is termed an OFDM symbol, and this OFDM symbol may be upconverted to an RF frequency and transmitted. An OFDM receiver may recover the timing and carrier frequency and then process the received samples through a fast Fourier transform (FFT). The cyclic prefix may be discarded and after the FFT, frequency domain information is recovered. The pilot symbols may be recovered to aid in channel estimation so that the data sent on the frequency tones can be recovered. A parallel-to-serial converter is applied, and the data is sent to the channel decoder. Just as with HSDPA, OFDM communications may be performed in an FDD mode or in a TDD mode.
One approach to improve spatial diversity of a multipath channel for MIMO communications systems is the vertical BLAST (Bell Laboratories Layered Space Time) or V-BLAST system as shown at FIG. 1. The V-BLAST system uses a vertically layered space-time architecture as described by Wolniansky et al., "V-BLAST: An Architecture for Realizing Very High Data Rates Over the Rich-Scattering Wireless Channel" (ISSSE, October 1998) and by Wolniansky et al., "Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture" ( IEEE Vol. 35, No. 1, January 1999). The modulation code scheme (MCS) of the V-BLAST circuit includes encoder 100, interleaver 102, and symbol mapper 104. Encoder 100 of the V-BLAST system encodes a serial data stream which is subsequently applied to interleaver circuit 102. The resulting interleaved data is then applied to symbol mapper 104 to produce a desired symbol constellation. The resulting symbols are then applied to serial-to-parallel circuit 106 and transmitted to remote user equipment via antennas 108. The V-BLAST system, therefore, improves communication with a single MCS by dividing a data stream into sub-streams that propagate differently over the wireless channel. The improvement, however, depends on the relative independence of these sub-streams. When there is a high correlation between the sub-streams, data may not be properly detected at the remote user equipment.
A further improvement over the V-BLAST system is shown in the per antenna rate control (PARC) circuit of FIG. 2. The PARC circuit includes four separate MCS circuits. Each MCS circuit includes an encoder 200, and interleaver 202, and a symbol mapper 204. The serial-to-parallel circuit 206 divides a data stream into four separate sub-streams. Each sub-stream is applied to a respective encoder circuit 200. Each encoder preferably allocates a different data rate according to the channel quality of each corresponding transmit antenna 208. For CDMA applications, each encoder circuit 200 may also multiply each sub-stream by a spreading code corresponding to the intended user equipment. The encoded sub-streams are subsequently interleaved, symbol mapped, and transmitted over transmit antennas 208. The PARC system, therefore, improves communication by dividing a data stream into sub-streams that propagate differently over the wireless channel and allocating specific data rates to each sub-stream corresponding to the quality of the respective wireless channel. The improvement, however, significantly increases signal processing complexity. A separate MCS circuit is required for each respective transmit antenna. Moreover, remote PARC receivers must identify and report the SINR for each transmit antenna.
While the preceding approaches provide steady improvements in wireless communications, the present inventors recognize that still further improvements may be made, including by addressing some of the drawbacks of the prior art. In particular, embodiments of the present invention improve communication quality and significantly reduce signal processing complexity compared to the PARC system. Some of these issues are described in co-pending U.S. patent application Ser. No. 10/230,003, filed Aug. 28, 2002, entitled, "MIMO HYBRID-ARQ USING BASIS HOPPING", and incorporated herein by reference. In this referenced application, multiple independent streams of data are adaptively transmitted with a variable basis selected to improve signal quality. Further, a receiver is provided that decodes the transmitted signals including the multipaths therein. While this improvement therefore provides various benefits as discussed in the referenced application, the inventors also recognize still additional benefits that may be achieved with such systems. Accordingly, the preferred embodiments described below are directed toward these benefits as well as improving upon the prior art.


A device is for introducing a stent into a hollow organ, in particular into the gastrointestinal tract of the body of a patient. The device includes a magnet system which covers the area of treatment of the patient and generates a 3D gradient field for remote-controlled movement and orientation of an endorobot. The endorobot is provided with a linear magnet and is freely movable in the hollow organ. Further, the stent, which can be uncoupled from the outside, is secured to the endorobot in a folded-down state so that it can be brought to the site of use and can there be opened out so as to bear firmly on the wall of the hollow organ.

Diseases in the area of the gastrointestinal tract often lead to narrowing (stenosis). The main causes are inflammations of the intestinal mucosa (Crohn's disease), but also space-occupying tumors which may be benign or malignant. The small intestine of humans is up to 11 meters long. Thus, diagnosis by conventional endoscopic techniques is not possible, or is possible only with a great many limitations. Endoscopic biopsy or even treatment of lesions of the small intestine is therefore not possible. A large part of the small intestine except for the upper jejunum and the terminal ileum is therefore not accessible from outside for introduction of a stent.
When fitting a stent in place with an endoscope, there is also a risk of damaging or even perforating the wall of the intestine. Moreover, an endoscopy procedure is very uncomfortable for the patient and in many cases is possible only under anesthesia, which involves a great deal of input in terms of personnel and technology and thus entails correspondingly high costs.

Device for introducing a stent into a hollow organ


The present invention forms and seals the top end of a container prior to filling and bottom sealing. The top end may have a fitment attached thereon at a variety of different positions on a form, fill and seal packaging machine. The fitment may be a screw cap, a push-in, a flip-cap type or similar fitments. The container may be a flat top, tetrahedral or similar type container. The fitment may be applied on the exterior or the interior of the container.

1. Field of the Invention
The present invention relates to a method and apparatus for forming the top of a container. Specifically, the present invention relates to a method and apparatus for forming the top of a container on a mandrel wheel of a form, fill and seal packaging machine.
2. Description of the Related Art
Many varieties of single-use containers exist for the packaging of liquids, powders or the like. The liquids may include milk or juice. The containers may be formed from blanks or sheets made of a variety of laminate materials having a substrate such as paperboard, strawboard, pasteboard, cardboard, and the like. The substrate may be laminated with a thermoplastic or similar liquid resistant coating to enable the container to retain liquids. The blanks may be folded into a variety of container cross-sections, such as tubular, rectangular, square, octagonal, hexagonal, and the like.
Traditionally, milk has been packaged in gable-top cartons that are torn open to reveal an integrated pouring device for accessing the product. Most recently, juice, such as orange juice, packaged in gable-top cartons with a fitment attached for accessing the product has gained favor with the consumer.
However, gable-top cartons have limitations that are dependent upon the circumstances. Gable-top cartons waste an enormous amount of material to form the gable-top that before the advent of fitments, and the technology for applying them, was necessary to access the product. Currently, with the popularity of fitments, the gable-top has become a non-functional aesthetic component of cartons.
Conventional containers have been proposed with flat upper ends having a spout and cap opening in the center of the top. However, flat-ended containers experience other limitations. In flat-ended containers, the adjoining edges of the folded end panels produce seams. These seams expose edges of the paperboard substrate material to the liquid product within the container. The product undergoes a wicking or capillary action and is soaked into the paperboard core of the container thereby degrading the seals and compromising the integrity of the package. In addition, conventional flat-ended containers are unable to achieve a hermetic seal along the seams produced at the upper end of the container. Thus, while conventional flat-ended containers are liquid tight, such containers are not hermetically sealed and, therefore, are unable to maintain a pressurized interior chamber, such as is required to preserve carbonated liquids. In addition, the non-hermetic seams in conventional paperboard-based containers are an unsatisfactory medium for storing liquids which are highly sensitive to oxygen, such as wine, orange juice, or the like.
A further problem has been forming containers without a top fin seal most readily apparent on a gable-top carton. For the most part, traditional form, fill and seal carton packaging machines do not lend themselves to high production of non-gable-top cartons. Some machines may flatten and seal the gable-top to provide an appearance of a flat top carton; however, this does not resolve the inefficient use of material.

Method and apparatus for forming the top of a container