Methods and systems are provided for a firearm. The firearm may include safety features having a trigger block preventing trigger actuation when a lever in the firearm is in a partially cocked position and/or a safety mechanism positioned in front of the trigger.

Civilian gun owners use firearms for a variety of purposes such as self-defense, hunting, target shooting, competitions, collecting, etc. Breech loading rifles are popular amongst many gun owners due to their quick and reliable cartridge loading action. One such breech-loading rifle that has gained in popularity in recent years is the Martini-Henry rifle. The Martini-Henry rifle is highly sought after and collectable and is likely to continue increasing in popularity.
The inventor, however, has recognized several drawbacks with previous Martini-Henry rifles. It will be appreciated that the deficiencies of previous Martini-Henry rifles are also exhibited in other styles of breech loading rifles and more generally in other types of firearms. Specifically, prior Martini-Henry rifles have a number of safety deficiencies. For instance, the original Martini-Henry rifle did not have a safety mechanism preventing accidental trigger actuation. Updated Martini-Henry rifles have included safety mechanisms in the action body of the rifle. However, due to the cumbersome nature of lever actuation on the action body, the operational efficiency of the firearm is decreased. Furthermore, the likelihood of unintended safety actuation may be increased when the safety lever is placed on the action body. Other attempts have been made, in Martini-Henry rifles, to incorporate safety mechanisms behind the trigger to prevent rearward movement of the trigger when activated. However, it may be difficult to actuate this type of trigger lock. Consequently, the firearm's operational efficiency is again negatively impacted, thereby decreasing customer satisfaction. Martini-Henry rifles can also be fired when the lever is in a partially cocked position, further increasing the risk of accidental firearm discharge.
The inventors herein have recognized the issues described above and designed a firearm with safety features to at least partially overcome the aforementioned issues. The safety features strive to reduce unintended firearm discharge by providing an easily accessible safety button and/or prevent trigger actuation when a lever in the action is partially cocked.
In one example, the firearm may include a trigger safety mechanism positioned in front of the trigger. The trigger safety mechanism may include a safety lever pivoting about a fulcrum allowing an angled face of the lever to selectively interfere with an angled face in the trigger. The safety lever therefore, in a first position, blocks the trigger from initiating firearm discharge and, in a second position, allows the trigger to be actuated to cause firearm discharge. In this way, a safety may be provided in front of the trigger (e.g., in a trigger guard) to facilitate efficient safety mechanism actuation. Furthermore, by providing a safety mechanism with a lever that pivots about a fulcrum and includes an angled face allows the safety mechanism to be compactly packaged in the trigger assembly.
The firearm may also include, in one example, a trigger block with a flange positioned on a rear side of a trigger. The trigger block prevents trigger actuation when the lever is in a partially cocked position. In this way, trigger actuation is prevented when the lever is not fully cocked. As a result, the likelihood of unintended firearm discharge is decreased. In such an example, the sear may be designed to independently rotate with regard to the trigger within a predetermined range, allowing a tumbler to engage with the sear when the lever is cocked.
It should be understood that the summary above is provided to introduce in simplified form, a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the subject matter. Furthermore, the disclosed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.

Firearm and methods for operation and manufacture thereof


A microfluidic device includes a substrate including multiple electro-hydraulic valves and/or electro-hydraulic pumps that each include a flow channel and one or more hydraulic control channels, actuators for controlling the electro-hydraulic valves and/or electro-hydraulic pumps, and a hydraulic pressure source operatively connected to the hydraulic control channels.

Developments in miniaturization and large-scale integration in fluidics have led to the concept of creating an entire chemistry or biology laboratory on a fluidic analog of the electronic microchip. Such integrated microfluidic devices (known as Micro Total Analysis Systems, or μTAS) are seen as key to automating and reducing costs in many biological analysis applications, including genetic analyses and medical diagnostics. Unlike the microelectronics industry, there is no general consensus in the analytical instruments industry about the most appropriate technologies for μTAS devices. Some companies are building μTAS devices by etching small glass plates or silicon chips. Others are working with either hard or soft polymeric materials fabricated by injection molding or by hot embossing. Producing reliable valves has turned out to be problematic with both types of devices. In etched solid chips, the valves tend to be very complicated, requiring multiple etching and deposition steps, and they suffer from a tendency to leak. Valves are easier to make in soft materials but, so far, they have been actuated only by pneumatic pressure, which presents difficulties for controlling the valves.
Traditional fluid valves operate by moving solid objects to obstruct the flow path. This requires sealing against a valve seat, and often leads to complicated geometries. Pneumatic valves used on μTAS devices are typically made by crossing two flow channels with a thin flexible membrane between them. One of the flow channels acts as a control to switch the flow on and off in the other channel. This is done by pressurizing the control channel, which leads to a deformation of the membrane separating the two channels. With a sufficiently high pressure in the control channel, the membrane completely closes the other channel. While this method has been shown to work for some applications, there are issues with the large number of pneumatic control lines required for large-scale integrated μTAS devices, as well as with concerns about leakage, and the limitations on operating pressure.

This patent is subject to a terminal disclaimer.


Disclosed is a method for controlling surface errors of a sample in a homogeneity measurement of infrared optical materials. In this invention, a calculation relationship among the surface errors, measurement principles and precision requirements is established. The wavefront distortion caused by the surface errors of the sample measured in infrared wavebands is converted to the surface errors of the sample which is processed and inspected under the visible light. Through establishing related algorithms and formulas for numerical calculations, a numerical table for controlling the surface errors of the sample is created to ensure the precision of the homogeneity measurement for the infrared optical material under short, middle and long wavebands. A case table for controlling the surface errors of the sample is also provided to ensure the precision of the homogeneity measurement for the specific infrared optical materials under short, middle and long wavebands.

The homogeneity measurement of infrared optical materials is a high-precision measurement, in which a refractive index homogeneity of the infrared optical material is measured. The measurement method is an interferometry in which a wavefront distortion of plane waves of test beams caused by inhomogeneity of the infrared optical material is obtained through an interferometer. The measurement precision is usually required up to 1×10−4-1×10−5 due to different measurement precision requirements. In order to ensure the high precision of the refractive index homogeneity measurement, a general approach is to improve the precisions of measurement equipment and measurement methods. In fact, the high-precision measurement cannot be achieved merely through improving the precisions of measurement equipment and measurement methods, even though the ambient temperature influence on the measurement precision in the measurement room is also required to be evaluated and controlled. In addition, the surface errors or flatness errors of the sample also greatly affect the measurement precision. The surface errors of the sample can cause wavefront distortion of the beam that transmits through the sample, which can be observed through an interferometer. However, the phenomenon of the wavefront distortion caused by the surface errors of the sample is the same as the that of the wavefront distortion caused by the refractive index inhomogeneity of the infrared optical material. Therefore, it is impossible to distinguish the wavefront distortion caused by the surface errors of the sample from the wavefront distortion caused by the refractive index inhomogeneity of infrared optical materials. Thus, in order to ensure the precision of the homogeneity measurement of the infrared optical material, it is required to find a method to calculate the impact of surface errors of the sample on refractive index homogeneity measurement of the materials and calculate a reference value for controlling the surface errors of the sample, so as to realize an accurate quantitative control for the surface processing of samples and guarantee that results of the homogeneity measurement for infrared optical materials are only influenced by the inhomogeneity of the optical materials, thereby making measurement results reflect actual situations of the material inhomogeneity.
In the prior art, there is no algorithm to quantitatively calculate the surface errors of the sample in the homogeneity measurement of infrared optical materials. Though it is known that the surface errors of the sample adversely affect the measurement precision, there is no algorithm to analyze how much the surface errors affect the measurement results. Therefore, the sample optical surface is merely required to be processed as well as possible, causing that the optical surface of the sample is prone to being insufficiently or excessively processed. When the optical surface of the sample is insufficiently processed, the homogeneity measurement of the infrared optical materials is carried out with the surface errors of the sample that is significantly higher than the surface errors required by the measurement precision, resulting in the unbelievable and useless results of the homogeneity measurement of the infrared optical materials. When the optical surface of the sample is excessively processed, high cost should be paid to process the sample, resulting in waste of money and time.

Method for controlling surface errors of sample in homogeneity measurement of infrared optical materials


Selecting a donor access node for a relay node includes identifying operating frequencies for carriers deployed by the relay node, and determining backhaul frequencies that minimize interference with the operating frequencies, including identifying frequency bands that are separated from the one or more operating frequencies by at least a threshold amount. Primary and secondary carriers can be identified and communicated with potential donor access nodes.

As wireless networks evolve and grow, there are ongoing challenges in providing high-quality service to increasing numbers of wireless devices in various coverage areas of a wireless network. One approach to improving service quality and coverage is to implement relay nodes for relaying communication between a base station or donor access node, and an end-user wireless device. Combinations of wireless devices designated as relays (henceforth, "relay wireless devices") that are co-located with relay access points may be used at the edge of a coverage area of a donor access node to improve coverage and/or service, as well as in crowded areas having a high number of other wireless devices to increase the available throughput to the end-user wireless devices being relayed. For the purposes of this disclosure, a wireless connection between a donor access node and a relay node or relay wireless device is referred to as a "backhaul connection" or simply "backhaul." Further, the relay node or relay access point deploys a carrier using an "operating frequency" to which the end-user wireless devices can attach.
With the increasing implementation of various access nodes and overlapping radio access technologies (RATs) such as 5G New Radio (NR) over existing RATs such as 3G and 4G Long Term Evolution (LTE), there are additional considerations regarding how relay nodes can effectively service wireless devices that are attached to it. In particular, when a relay node attaches to a donor access node over a backhaul connection that utilizes a frequency relatively close to the operating frequency of the relay node itself, interference may be caused to either the backhaul connection or to the end-user wireless devices attached to the relay node. This causes service interruptions to users of wireless devices connected to the relay node, and unnecessary signaling to disconnect and reconnect between donor access nodes. Further, there exists no means in the art for a donor access node to assign primary and secondary carriers (for relay nodes capable of carrier aggregation) that would not cause interference to operating frequencies deployed by relay nodes.

Donor selection for relay nodes based on frequency separation


A blood state analysis device, blood state analysis system, blood state analysis method, and program that enable analysis of the state of blood easily and precisely is provided. The blood state analysis device includes: an extraction unit configured to extract at least one feature from chronological change data of an electrical characteristic of blood in two or more frequency bands; an evaluation unit configured to evaluate a state of the blood on the basis of the at least one feature extracted by the extraction unit; and a classification unit configured to classify the blood on the basis of a result of evaluation conducted by the evaluation unit.

Anti-platelet aggregation agents or anti-coagulant agents are prophylactically administered to patients or healthy persons who have thrombosis risks. Examples of the patients having thrombus formation risks include patients with diabetes, arteriosclerosis, cancer, heart disease, and respiratory disease; perioperative patients; and patients taking immunosuppressants. Also, examples of the healthy persons having thrombus risks include pregnant women and elderly people. As the anti-platelet aggregation agents, acetylsalicylic acid and the like are used; and as the anti-coagulant agents, warfarin, heparin, activated blood coagulation factor Xa inhibitors, direct thrombin inhibitors, and the like are used.
The prophylactic administration of anti-platelet aggregation agents and anti-coagulant agents against thrombosis has the side effect that an excessively high administered dose increases a bleeding risk. In order to obtain a sufficient prophylactic effect while inhibiting this side effect, an administration management becomes important in which blood coagulability of an administered subject is timely evaluated, and the drug and dose to be administered are appropriately selected and determined.
A method for a blood coagulability test for managing drug administration includes the prothrombin time-international normalized ratio (PT-INR), the activated partial thromboplastin time (APTT), and the like. Also, a method for a platelet aggregation test includes adding a substance that induces aggregation of platelet to platelet rich plasma (PRP) obtained by centrifuging blood, and measuring a change in transmitted light levels or absorbance associated with the aggregation to determine good or poor in aggregation capacity.
In recent years, techniques for obtaining information related to a blood coagulation system from dielectric permittivity of blood have been proposed (see Patent Literatures 1 and 2). For example, in blood coagulation system analysis devices disclosed in Patent Literatures 1 and 2, blood to be analyzed is held in a container provided with electrodes so that a voltage can be applied to the blood, and an alternating current is applied to the electrodes to measure complex dielectric permittivity. In these devices, by analyzing a complex dielectric permittivity spectrum obtained by the measurement according to a predetermined algorithm, enhancement or reduction of blood coagulability such as a blood coagulation time is evaluated.

Blood state analysis device, blood state analysis system, blood state analysis method, and program


A rotatable tilling device for tilling ground material, the device consisting of a rotatable shaft having an upper end, a lower end, and having an axis of rotation extending from its upper end to its lower end; a plurality of ground tilling tines, each ground tilling tine having an upper end and a lower end; and, upper and lower tine mounting structure capable of attaching the ground tilling tines to the rotatable shaft so that they span between the tine mounting structure, so that upon rotation of the rotatable shaft the ground tilling tines orbit about the axis of rotation, so that on contact of the rotatable shaft with ground material, the ground tilling tines also contact the ground material, and so that the ground tilling tines may flexibly bend between the upper and lower tine mounting structure; the upper and lower tine mounting structure fixedly attaching the ground tilling tines to the rotatable shaft.

U.S. Pat. No. 3,129,771 issued Apr. 21, 1964, to Lidstone discloses a ground cultivating tool having an elongated drive shaft, the upper end of which is adapted for being rotatably driven by the chuck of an electric hand drill. At the lower end of the cultivating tool disclosed in Lidstone are a pair of ground agitating tines which are mounted upon the drive shaft so that they first extend perpendicularly from the drive shaft, and then extend downwardly at substantially right angles for engagement with ground material. A drawback or defect of the device disclosed in Lidstone is that the "elbow" or right angle of the tines is a structural weak point at which the tines tend to either permanently deform or fracture. Another drawback or deficiency of the cultivating tool disclosed in Lidstone is that the tool requires a diecast molding of the unitary tine and collar, which is not conducive to cost economy.
The instant inventive ground tilling device solves the above problems and deficiencies by providing a rotary drill driven ground tilling implement having a tine supporting structure which resists deformation and fracturing of tines and which is economically fabricated.


Certain types of holographic recording materials can be used to updateably record holographic stereograms formed when fringe patterns are generated through interference of an object laser beam containing image information with a reference laser beam. In this manner, calculation of fringe patterns is avoided, and instead perspective information is computed for a scene or object to be displayed, the information is downloaded to display hardware such as a spatial light modulator, and fringe patterns are subsequently generated through interference of an object laser beam containing this information with a reference laser beam in the classic hologram recording scheme. Previously recorded holographic stereograms or component hogels are updated by erasing the stereograms or component hogels and recording updated stereograms or component hogels, or by recording updated stereograms or component hogels in a separate portion of the holographic recording material.

1. Field of the Invention
The present invention relates in general to the field of hologram production and, more particularly, to production of updateable holograms.
2. Description of the Related Art
One-step hologram (including holographic stereogram) production technology has been used to satisfactorily record holograms in holographic recording materials without the traditional step of creating preliminary holograms. Both computer image holograms and non-computer image holograms can be produced by such one-step technology. In some one-step systems, computer processed images of objects or computer models of objects allow the respective system to build a hologram from a number of contiguous, small, elemental pieces known as elemental holograms or hogels. To record each hogel on holographic recording material, an object beam is typically directed through a spatial light modulator (SLM) displaying a rendered image and then interfered with a reference beam. Examples of techniques for one-step hologram production can be found in the U.S. Pat. No. 6,330,088 entitled "Method and Apparatus for Recording One-Step, Full-Color, Full-Parallax, Holographic Stereograms," naming Michael A. Klug, Mark E. Holzbach, and Alejandro J. Ferdman as inventors, ("the '088 patent") which is hereby incorporated by reference herein in its entirety.
In general, the techniques described in the '088 patent and other prior art techniques do not provide for both hologram recording and display in real-time. Moreover, these techniques are not designed to produce active or quickly-updateable displays. There are significant applications for a display that is capable of producing autostereoscopic holographic three-dimensional images that are interactive and update-able in a reasonable amount of time (e.g., on the order of seconds or minutes). However, there are three significant obstacles to producing such a display: (1) selecting a suitable display medium capable of recording, displaying, erasing or replacing, and updating the image; (2) communications bandwidth necessary to transfer the enormous amounts of data necessary to produce an image on the display; and (3) rendering hardware and software that is fast enough to produce a real-time or quasi-real time, interactive experience.
There have been a number of efforts to develop a real-time holographic display, most notably by Steve Benton's Spatial Imaging Group at the MIT Media Laboratory, and by a group at QinetiQ, a spin-off company from the UK's Defense Evaluation and Research Agency (DERA). These efforts have produced some promising but limited results.
The MIT effort resulted in a monochrome display with dimensions of approximately 75 mm×100 mm, and exhibiting horizontal parallax only. The system is based on first computing fringe patterns using physical simulation, displaying them piecewise in an acousto-optic modulator (AOM), and then raster scanning a demagnified image of the AOM to produce a larger display. Images produced on the MIT display have approximately 30 degrees of horizontal viewzone, and the vertical resolution is limited to 144 lines. Many of the image quality tradeoffs of the MIT system reflect a need to minimize the total data bandwidth of the system. As a result, each frame of the display contains approximately 36 megabytes of information. Custom and customized hardware enable the display to be updated at up to 2 to 3 frames per second with pre-stored image information. Since the system requires complex computational physical simulation to produce holographic fringe patterns, real-time updating is difficult.
The QinetiQ approach also relies on physical simulation to produce synthetic fringe patterns. These, however, are written onto an electrically-addressed spatial light modulator (EASLM), and are demagnified and re-imaged onto an optically-addressed spatial light modulator (OASLM) for final display. The approach is potentially capable of producing full-parallax images, and is scalable through tiling multiple EASLM/OASLM units together. The system has not been publicly demonstrated to date, and thus it is difficult to assess its characteristics and effectiveness. Computational elements of the QinetiQ display have been documented, but the performance of the system has not been demonstrated.
Both the MIT and QinetiQ approaches rely on complex physical simulation to calculate holographic fringe patterns which are then downloaded to the display hardware. Light being directed through that hardware diffracts from these fringes, and reproduces wavefronts, or approximations thereof, of the desired imaged object or scene. This approach has limitations because it relies on the need for a display device with extremely high resolution that can be electronically addressed in order to enable writing of the fringe pattern. Such approaches often have limited resolution, and rely on demagnification to achieve the high resolution necessary to diffract light. Limited space-bandwidth products of such approaches in turn limit the viewing angle and resolution of the final image.
Accordingly, it is desirable to have improved systems and methods for producing updateable or active hologram displays that avoid the need for complex physical simulation to produce synthetic fringe patterns. Moreover, it is desirable that such systems and methods high resolution images that possess adequate field of view properties.


An example ink cartridge for a stamp may comprise an image-forming component, a first ink-storage component made of an ink-absorbent material, a second ink-storage component made of an ink-absorbent material having one or more channels in it, and a frame made of a rigid, non-ink-absorbent material. The frame may comprise a floor having one or more holes in it. The frame may comprise an outer wall along its perimeter. The outer wall may extend up from the floor such that the outer wall is capable of retaining ink while the ink is being absorbed by the first ink-storage component and the second ink-storage component, thereby increasing the effective volume of the channel(s). The one or more holes may align with the one or more channels such that ink is enabled to flow through the hole(s) into the channel(s).

Existing methods and systems for ink stamps are often inefficient in terms of the processes and materials required for manufacturing them. Furthermore, existing methods and systems for ink stamps are often inefficient in terms of the need for frequent refilling and the manner of refilling. Further limitations and disadvantages of such methods and systems will become apparent to one of skill in the art, through comparison of such methods and systems with aspects of the method and system set forth in the remainder of the present disclosure with reference to the drawings.

Method and system for self-inking stamp cartridge


A discrete cosine transformer capable of real time processing without a multiplier having small circuit scale and small power consumption includes an adder/subtractor receiving a plurality of image data items for outputting a plurality of image data item addition/subtraction values in accordance with a prescribed rule, a bit distributor connected to the adder/subtractor, receiving the plurality of image data item addition/subtraction values for outputting a plurality of bit trains consisting of bits at same bit position of the plurality of image data item addition/subtraction values, a selection signal generating circuit for successively generating a selection signal of a DCT coefficient, and a DCT coefficient generating circuit connected to the bit distributor and to the selection signal generating circuit, receiving a plurality of bit trains and responsive to the successively generated selection signal, for performing calculation of the DCT coefficient in time-divisional manner.

1. Field of the Invention
The present invention relates to a discrete cosine transformer for performing discrete cosine transform in a device for compressing image data, and to an inverse discrete cosine transformer for performing inverse discrete cosine transform in a device for decompressing image data, for example. More specifically, the present invention relates to a discrete cosine transformer and an inverse discrete cosine transformer having small circuit scale and small power consumption.
2. Description of the Background Art
Image signals contain formidable amount of data. Therefore, it is a general practice to compress the amount of data for transmission or recording, and to decompress to the original data amount at the time of reception or reproduction. Generally, image data has much low frequency component but less high frequency component. Therefore, the low frequency component is subjected to fine quantization while the high frequency component is subjected to coarse quantization. For this purpose, it is necessary to transform the image data to frequency components. Discrete cosine transformation (hereinafter referred to as DCT) is used as a method for transforming image data to frequency component. Inverse discrete cosine transformation (hereinafter referred to as IDCT) is used as a method for reverse transformation.
Generally, image data is processed on a unit of 8.times.8 pixels, which requires two-dimensional DCT of 8.times.8 as well as a two-dimensional IDCT of 8.times.8. However, direct implementation of two-dimensional DCT or IDCT results in a considerably large circuit scale. Accordingly, the two-dimensional DCT or two-dimensional IDCT is realized by performing one-dimensional DCT or one-dimensional IDCT once for the longitudinal direction and once for the lateral direction of the image.
The one-dimensional DCT and one-dimensional IDCT will be described in the following. Let us represent 8 input signals as X.sub.j (j=0 to 7). The DCT can be represented by the following expression (1). ##EQU1## 8Y.sub.i (i=0 to 7) obtained by this expression are referred to as DCT coefficients.
The expression (1) can be represented by the following matrix representation (2). ##EQU2## where C.sub.k (k=1 to 7) represents cos (k .pi./16).
The following matrix representations (3) and (4) are derived from matrix representation (2). ##EQU3##
Meanwhile, one-dimensional IDCT for inverse transformation to one-dimensional DCT is represented by the following expression (5). ##EQU4##
The expression (5) can be represented by the following matrix representation (6). ##EQU5##
The following matrix representations (7) and (8) are derived from the matrix representation (6). ##EQU6##
When DCT and IDCT are to be performed actually, in order to reduce the number of multiplication, not the 8.times.8 matrix representations of (2) and (6) but 4.times.4 matrix representations of (3), (4), (7) and (8) of the representations for DCT and IDCT listed above are used.
For multiplication and accumulation implementing the matrix operation, a multiplier accumulator including a multiplier and an adder are often used. However, the multiplication and accumulation using the multiplier accumulator results in a large scale multiplier. Accordingly, a method for performing multiplication and accumulation using a memory instead of the multiplier has been proposed. Once such method of multiplication and accumulation using a memory and an adder is disclosed, for example, in A. Peled and B. Liu, "A New Hardware Realization of Digital Filters", IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-22, pp. 456-462, December 1974., in which distributed arithmetic method is discussed.
The distributed arithmetic method will be described in the following. Multiplication and accumulation of the variable X.sub.j (j=0 to M-1) and a fixed coefficient Cj(j=0 to M-1) of the following equation (9) will be considered. ##EQU7##
When Xj is represented by a 2's complement of N bits, Xj will be given by the following expression (10). ##EQU8## where X.sub.j (k) represents a bit at the kth bit position (lower by k than the most significant bit), which is either 0 or 1.
From the expression (10), the expression (9) can be modified to the expression (11). ##EQU9##
When the partial sum Z.sub.k is defined by the following expression (12), the expression (11) will be given by the following expression (13). ##EQU10##
In this manner, the result Y of multiplication and accumulation of variable X.sub.j (j=0 to M-1) and the fixed coefficient C.sub.j (j=0 to M-1) is given by the expression (13). Note the partial sum Z.sub.k defined by the expression (12). Components of this expression are C.sub.j (j=0 to M-1) and X.sub.j (k)(j=0 to M-1), that is, a bit train including M bits (X.sub.0 (k) X.sub.1 (k) X.sub.2 (k) . . . X.sub.M-1 (k)) which are the bits at the kth bit position of the variables X.sub.j (j=0 to M-1) (hereinafter, the bit train will be referred to as M bit train X.sub.j (k)(j=0 to M-1)). Here, C.sub.j is a fixed coefficient. Accordingly, the partial sum Z.sub.k is a function of the M bit train X.sub.j (k)(j=0 to M-1). Accordingly, values which the partial sum Z.sub.k can assume are stored in advance in a memory so that when the memory is accessed using (inputting) a bit train X.sub.j (k)(j=0 to M-1) as an address, a partial sum Z.sub.k corresponding to the bit train can be read (output). Multiplication and accumulation is possible when each of the partial sums Z.sub.k read from the memory is shifted as represented by the expression (13) in accordance with the bit position k of the bits of the bit train constituting the partial sum and the shifted sums are added.
Referring to FIG. 1, a one-dimensional DCT circuit (discrete cosine transformer) employing the distributed arithmetic is adapted such that 8 multiplication and accumulation operations implementing the matrix representations of (3) and (4) are performed by distributed arithmetic on input X.sub.j (j=0 to 7) and to output DCT coefficients Y.sub.i (i=0 to 7). Here, it is assumed that both X.sub.j (j=0 to 7) and Y.sub.i (i=0 to 7) are data of 9 bits, respectively.
The operation of the circuit will be described in the following. 8 data X.sub.0 to X.sub.7 input from an input terminal 401 are successively transferred to registers 402 to 409, and held in registers 409 to 402, respectively. Outputs X.sub.0 to X.sub.7 from registers 409 to 402 are added or subtracted in adder/subtractor 410. Results of addition X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are held by registers 411 to 414, respectively. Results of subtraction X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are held in registers 415 to 418, respectively. Since input X.sub.j (j=0 to 7) is data containing 9 bits, the results of addition X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 as well as the results of subtraction X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are data of 10 bits, respectively.
Referring to FIGS. 2A and 2B, operations of a bit distributor 419 receiving as inputs the outputs X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 from registers 411 to 414, and a bit distributor 420 receiving as inputs the outputs X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 from registers 415 to 418, respectively will be described in the following. In bit distributor 419, outputs from registers 411 to 414 are divided into ten signal lines corresponding to the most significant to the least significant bits (most significant bit 9! to least significant bit 0!). Ten sets of four signal lines representing 4 bits of signals of the same bit position are provided and connected to a selector 479. In response to a select signal output from a select signal generating circuit 479b, values of ten sets of 4 bit signal lines are successively selected by selector 479 starting from the set of the most significant bit, and output to multiplication and accumulation blocks 421 to 424. More specifically, the values of 4 bit signal lines are output to multiplication and accumulation blocks 421 to 424 in the order of signal lines 9!, 8!, . . . , 0!. Similarly, in bit distributor 420, the values of ten sets of 4 bit signal lines are provided from the outputs of registers 415 to 418, and 4 bit signal lines are connected to multiplication and accumulation blocks 415 to 418, in the order of signal lines 9!, 8!, . . . , 0!.
In summary, ten sets of 4 bit trains including bits of the same bit position of the outputs X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 which are outputs from registers 111 to 114, respectively, are output from bit distributor 419 to multiplication and accumulation blocks 421 to 424, starting from the set of the most significant bit. Similarly, from bit distributor 420, ten sets of 4 bit trains which include bits of the same bit position of X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4, which are outputs from registers 115 to 118, respectively, are output to multiplication and accumulation blocks 425 to 428 successively, starting from the set of the most significant bit.
Thereafter, the multiplication and accumulation blocks 421 to 424 successively receive ten sets of 4 bit trains from bit distributor 419, and carry out four multiplication and accumulation operations implementing the matrix representation of (3), to calculate Y.sub.0, Y.sub.2, Y.sub.4 and Y.sub.6, respectively. Multiplication and accumulation blocks 425 to 428 successively receive ten sets of 4 bit trains from bit distributor 420, perform four multiplications and accumulations implementing the matrix representation of (4), to calculate Y.sub.1, Y.sub.3, Y.sub.5 and Y.sub.7, respectively. These operations will be described taking calculation of Y.sub.0 by multiplication and accumulation block 421 as an example.
Referring to FIGS. 3A and 4A, ROM 429 provided in multiplication and accumulation block 421 is adapted to output 0 when the input 4 bit train is (0000), to output C.sub.4 when the 4 bit train is (0001), . . . and 4C.sub.4 when (1111), respectively. The respective bit values of the 4 bit trains are the values of bits of the same position of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4. An output from ROM 429 is, when a 4 bit train is an input, a partial sum of Y.sub.0 ={C.sub.4 (X.sub.0 +X.sub.7)+C.sub.4 (X.sub.1 +X.sub.6)+C.sub.4 (X.sub.2 +X.sub.5)+C.sub.4 (X.sub.3 +X.sub.4)}/2. Though not shown, in multiplication and accumulation block 421, output polarity of ROM 429 for every ten inputs is inverted. This corresponds to the fact that a partial sum having 4 bit trains of the most significant bit is negative. In the following, it is assumed that the ROM 429 is structured as described above.
First, 4 bit trains consisting of the most significant bits of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 from bit distributor 419 are input to ROM 429. From ROM 429, a partial sum of Y.sub.0 including as component 4 bit trains of the most significant bit will be output. The output from ROM 429 is input to adder 437 where it is added to an initial output value 0 of shifter 453, and the result is held in register 445. Namely, in this stage, a partial sum of Y.sub.0 having 4 bit trains of the most significant bit as a component is held in register 445.
Thereafter, 4 bit trains consisting of bits at a bit position 1 of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 from bit distributor 419 are input to ROM 429. Consequently, a partial sum of Y.sub.0 having 4 bit trains of the bits at bit position 1 is output from ROM 429. The output from ROM 429 is input to adder 437. Meanwhile, the value held in register 445 is shifted upward by 1 bit by shifter 453 and input to adder 437. The result of addition at adder 437 is held in register 445. Namely, in this stage, register 445 holds the result of addition of the partial sum (shifted upward by 1 bit) of Y.sub.0 having 4 bit trains of the most significant bit as a component and a partial sum of Y.sub.0 having 4 bit trains of the bits at bit position 1 as a component.
Thereafter, 4 bit trains of the bits at bit position 2, 4 bit trains of the bits at bit position 3, . . . 4 bit trains of the least significant bit (bits at bit position 9) of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 from bit distributor 419 are input in this order to ROM 429. Every time, the output from ROM 429 is added to the data (shifted by 1 bit upward by shifter 453) held in register 445 in adder 437, and the result of addition is held in register 445.
Ten sets of 4 bit trains consisting of bits of the same bit position of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are input from bit distributor 419 to multiplication and accumulation block 421 starting from the ones of the most significant bit. After the end of above described operation, the data held in register 445 is rounded to 9 bits by a rounding circuit 461, held in register 469 and then output from multiplication and accumulation block 421.
Now, assume that ten sets of 4 bit trains consisting of the bits of the same bit position of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are all input from bit distributor 419 to multiplication and accumulation block 421 and the above described operation is completed. At that time, determining from the content of operation and expression (13), the data held in register 445 is Y.sub.0. Namely, Y.sub.0 is output from multiplication and accumulation block 421.
Referring to FIGS. 3B to 3D, in multiplication and accumulation blocks 422 to 424, the relation between input/output of ROM 430 to 432 are as shown in FIG. 4A, respectively, and these blocks perform similar operation as in multiplication and accumulation block 421. Therefore, ten sets of 4 bit trains consisting of the bits at the same bit position of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are input starting from the ones consisting of the most significant bit, from bit distributor 419, and Y.sub.2, Y.sub.4 and Y.sub.6, are output, respectively.
Referring to FIGS. 3E to 3H, the relations between input/output of ROMs 433 to 436 of multiplication and accumulation blocks 425 to 428 are as shown in FIG. 4B, respectively, and the multiplication and accumulation blocks perform similar operation as in accumulation and multiplication block 421. Accordingly, ten sets of 4 bit trains consisting of bits at the same bit positions of X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are successively input starting the ones consisting of the most significant bits from bit distributor 420, and Y.sub.1, Y.sub.3, Y.sub.5 and Y.sub.7 are output, respectively.
Here, coefficient of each of the matrixes (3) and (4) is assumed to have 10 bits. Accordingly, the number of bits of the outputs ROMs 429 to 436 is 12 and the number of bits of the output from adders 437 to 444, registers 445 to 452 and shifters 453 to 460 is 21.
Finally, Y.sub.0, Y.sub.2, Y.sub.4, Y.sub.6, Y.sub.1, Y.sub.3, Y.sub.5 and Y.sub.7 output from multiplication and accumulation blocks 421 to 428, respectively, are input to an output selector 477. The respective input values are selected in a prescribed order, output from a successive output terminal 478, and one-dimensional DCT is completed.
Here, in the one-dimensional DCT circuit, X.sub.j (j=0 to 7) are input successively in 8 steps from input terminal 401. Meanwhile, for calculation of Y.sub.0 to Y.sub.7 in multiplication and accumulation blocks 421 to 428, ten steps, that is, same as the number of bits of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 as well as X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are necessary. Namely, the time of calculation is longer than the time of input. This means that the DCT circuit is not capable of real time operation. Therefore, when input is continuously given through input terminal 401 to the DCT circuit, calculation cannot catch up. Therefore, continuous output from input terminal 401 is not possible, which means that efficient image compression is impossible.
In order to solve this problem, a method has been proposed, for example, in S. Uramoto et al., "A 100-MHz 2-D Discrete Cosine Transform Core Processor", IEEE Journal of Solid-State Circuits, vol. 27, No. 4, pp. 492-499, April 1992, in which a plurality of 4 bit trains are processed two sets by two sets simultaneously, each train consisting of bits of the same bit position of the input data.
Referring to FIG. 5, a one-dimensional DCT circuit (discrete cosine transformer) is adapted such that matrix representations (3) and (4) are implemented by distributed arithmetic on input X.sub.j (j=0 to 7), and a DCT coefficient Y.sub.i (i=0 to 7) is output. Here, it is assumed that X.sub.j (j=0 to 7) and Y.sub.i (i=0 to 7) are data of 9 bits, respectively.
The operation of the circuit will be described in the following. 8 data X.sub.0 to X.sub.7 input from an input terminal 501 are successively transferred to registers 502 to 509 in the order of input, and held in registers 509 to 502, respectively. Outputs X.sub.0 to X.sub.7 of registers 509 to 502 are added or subtracted in an adder/subtractor 510, respectively. The result of addition X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are held in registers 511 to 514, respectively. The result of subtraction X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are held in registers 515 to 518, respectively. Since input X.sub.j (j=0 to 7) is data of 9 bits, the results of addition X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 as well as the results of subtraction X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are each data of 10 bits.
Referring to FIGS. 6A and 6B, operations of bit distributor 519 receiving outputs X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 of registers 511 to 514, respectively and bit distributor 520 receiving outputs X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 of registers 515 to 518, respectively, will be described in the following. In bit distributor 519, output from registers 511 to 514 are distributed to ten signal lines (most significant 9! to least significant 0!) from the most to least significant bits, and ten sets of 4 bits signal lines including a combination of four signal lines of the same bit position are provided. Of these, five sets of 4 bit signal lines 9!, 7!, 5!, 3! and 1! are connected to selector 603, while five sets of 4 bit signal lines 8!, 6!, 4!, 2! and 0! are connected to selector 604. In response to a select signal output from a select signal generating circuit 603b, the five sets of 4 bit signal lines are successively selected starting from the set of higher bit, by selectors 603 and 604. More specifically, two sets of 4 bit signal lines, that is, values of signal lines 9! and 8!, 7! and 6!, 5! and 4!, 3! and 2! and 1! and 0! are simultaneously output to multiplication and accumulation blocks 521 to 524. Similarly, in bit distributor 520, ten sets of 4 bit signal lines are provided based on the output from registers 515 to 518, and two sets of 4 bit signal lines, that is, the values of signal lines 9! and 8!, 7! and 6!, 5! and 4!, 3! and 2! and 1! and 0! are output to multiplication and accumulation blocks 525 to 528.
In summary, ten sets of 4 bit trains consisting of the bits of the same bit positions of four data X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 which are the outputs from registers 511 to 514 are output two sets by two sets starting from the most significant bit, to multiplication and accumulation blocks 521 to 524. Similarly, from bit distributor 520, ten sets of 4 bit trains consisting of bits of the same bit positions of four data X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 which are the outputs of registers 515 to 518 are output successively two sets by two sets starting from the most significant bit, to multiplication and accumulation blocks 525 to 528.
Then, multiplication and accumulation blocks 521 to 524 successively receive the ten sets of 4 bit trains two sets by two sets from bit distributor 519, perform four multiplications and accumulations implementing the matrix representation (3), and calculate Y.sub.0, Y.sub.2, Y.sub.4 and Y.sub.6, respectively. Multiplication and accumulation blocks 525 to 528 successively receive the ten sets of 4 bit trains two sets by two sets from bit distributor 520, perform multiplications and accumulations implementing the matrix representation (4) and calculate Y.sub.1, Y.sub.3, Y.sub.5 and Y.sub.7, respectively. These operations will be described, taking multiplication and accumulation block 521 calculating Y.sub.0 as an example.
Referring to FIG. 7A, ROMs 529 and 530 provided in multiplication and accumulation block 521 are adapted to output 0 when input 4 bit train is (0000), C.sub.4 when it is (0001), . . . , and 4C.sub.4 when it is (1111), as shown in FIG. 4A. The bit values of respective 4 bit trains are the values of the bits of the same bit position of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4. The outputs from ROMs 529 and 530 are partial sum of Y.sub.0 ={C.sub.4 (X.sub.0 +X.sub.7)+C.sub.4 (X.sub.1 +X.sub.6)+C.sub.4 (X.sub.2 +X.sub.5)C.sub.4 (X.sub.3 +X.sub.4)}/2, when a 4 bit train is input. In multiplication and accumulation block 521, though not shown, the output polarity of upper ROM (ROM 529) is inverted for every five inputs. This corresponds to the fact that a partial sum having the 4 bit train consisting of the most significant bit as a component is negative. The following description is on the premise that ROMs 529 and 530 are structured as described above.
First, 4 bit trains consisting of the most significant bit of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4, and 4 bit trains consisting of the bits at bit position 1 are input from bit distributor 519 to ROMs 529 and 530. Consequently, a partial sum of Y.sub.0 having 4 bit trains consisting of the most significant bit as a component is output from ROM 529. A partial sum of Y.sub.0 having 4 bit trains consisting of the bit at bit position 1 as a component is output from ROM 530. Two outputs from ROM 529 and 530 are added in adder 553 after the output of ROM 529 is shifted by 1 bit upward by shifter 545. The result of addition is added to initial output 0 of shifter 577 in adder 561, and the result of addition is held in register 569. More specifically, in this stage, register 569 holds the result of addition of a partial sum (shifted by 1 bit upward) having 4 bit trains of the most significant bit as a component and partial sum of Y.sub.0 having 4 bit trains of the bits at bit position 1 as a component.
Thereafter, 4 bit trains consisting of bits at bit position 2 of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 and 4 bit trains consisting of bits at bit position 3 of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are respectively input to ROMs 529 and 530 from bit distributor 519. Consequently, a partial sum of Y.sub.0 having 4 bit trains consisting of bits at bit position 2 as a component is output from ROM 529. A partial sum of Y.sub.0 having 4 bit trains consisting of bits at bit position 3 as a component is output from ROM 530. The two outputs from ROMs 529 and 530 are added in adder 553 after the output from ROM 529 is shifted by 1 bit upward by shifter 545. The result of addition is added to data held in register 569, which has been shifted 2 bits upward by shifter 577, and the result of addition is held in register 569. More specifically, in this stage, register 569 holds the result of addition of partial sum (shifted by 3 bits upward) of Y.sub.0 having 4 bit trains consisting of most significant bits as a component, a partial sum (shifted by 2 bits upward) of Y.sub.0 having 4 bit trains consisting of bits at bit position 1 as a component, a partial sum (shifted by 1 bit upward) of Y.sub.0 having 4 bit trains consisting of bits at bit position 2 as a component, and a partial sum of Y.sub.0 having 4 bit trains consisting of bits at bit position 3 as a component.
Thereafter, 4 bit trains consisting of bits at bit position 4, 4 bit trains consisting of bits at bit position 5, 4 bit trains consisting of bits at bit position 6, 4 bit trains consisting of bits at bit position 7, 4 bit trains consisting of bits at bit position 8 and thereafter 4 bit trains of least significant bits (bits at bit position 9) of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are input to ROMs 529 and 530, successively, in this order, from bit distributor 519, and at every input, the output from ROM 529 (shifted by 1 bit upward by shifter 545) and output from ROM 530 are added in adder 553. The result of addition is added to data (shifted by 2 bits by shifter 577) held in register 569 in adder 561. The result of addition is held in register 569.
Thereafter, ten sets of 4 bit trains consisting of bits at the same bit positions of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are all input two sets by two sets starting from those consisting of the most significant bits from bit distributor 519 to multiplication and accumulation block 521. After the end of the above described operation, the data held in register 569 is rounded to 9 bits in rounding circuit 585, held in register 593 and output from multiplication and accumulation block 521.
Now, assume that ten sets of 4 bit trains consisting of bits of respective same bit positions of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are all input two sets by two sets starting from the ones consisting of the most significant bits from bit distributor 519 to multiplication and accumulation block 521 and the above described operation is completed. At this time, determining from the content of operation and expression (13), the data held in register 569 is Y.sub.0, and hence Y.sub.0 is output from multiplication and accumulation block 521.
Further, in multiplication and accumulation blocks 522 to 524, the relation between input/output of ROMs 531 and 532, 533 and 534 and 535 and 536 are as shown in FIG. 4A, and these blocks operate in the similar manner as multiplication and accumulation block 521. Therefore, ten sets of 4 bit trains consisting of bits of the same bit positions of X.sub.0 +X.sub.7, X.sub.1 +X.sub.6, X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 are input two sets by two sets starting from those consisting of the most significant bit from bit distributor 519, and Y.sub.2, Y.sub.4 and Y.sub.6 are output, respectively.
Referring to FIG. 7B, in multiplication and accumulation blocks 525 to 528, the relations between input and output of ROMs 537 and 538, 539 and 540, 541 and 542 and 543 and 544 are as shown in FIG. 4B, and these blocks operate in the similar manner as multiplication and accumulation block 521. Therefore, ten sets of 4 bit trains consisting of bits of the same bit positions of X.sub.0 -X.sub.7, X.sub.1 -X.sub.6, X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4 are input two sets by two sets successively starting from the ones consisting of most significant bits from bit distributor 520, and Y.sub.1, Y.sub.3, Y.sub.5 and Y.sub.7 are output.
Now, each coefficient of the matrixes shown in (3) and (4) is assumed to have 10 bits. Accordingly, the number of bits of the outputs from ROMs 529 to 544 is 12, the number of bits of the outputs from adders 553 to 560 is 13, and that of adders 561 to 568, registers 569 to 576 and shifters 577 to 584 is 21.
Finally, Y.sub.0, Y.sub.2, Y.sub.4, Y.sub.6, Y.sub.1, Y.sub.3, Y.sub.5 and Y.sub.7 output from multiplication and accumulation blocks 521 to 528, respectively, are input to an output selector 601. The respective input values are selected in a prescribed order and output successively from an output terminal 602. Thus one-dimensional DCT is completed.
Now, in the one-dimensional DCT circuit, X.sub.j (j=0 to 7) are successively input in 8 steps from input terminal 501. Meanwhile, calculation of Y.sub.0 to Y.sub.7 in multiplication and accumulation blocks 521 to 528 requires 5 steps, that is, half the number of bits of X.sub.0 +X.sub.7,X.sub.1 +X.sub.6,X.sub.2 +X.sub.5 and X.sub.3 +X.sub.4 and X.sub.0 -X.sub.7,X.sub.1 -X.sub.6,X.sub.2 -X.sub.5 and X.sub.3 -X.sub.4. Namely, the time for calculation is shorter than the time for input. It means that the DCT circuit is capable of real time operation. Therefore, when input is continuously provided from input terminal 501 to the DCT circuit, calculation can be done in time without fail. This allows continuous input from input terminal 501, and image compression can be done efficiently.
In this manner, by using a memory and an adder, one-dimensional DCT is possible in real time without using a multiplier. However, in the one-dimensional DCT circuit, 8 multiplications and accumulations are performed in parallel, two partial sums including two sets of 4 bit trains consisting of bits of the same bit positions of the input data as components are successively generated for multiplication and accumulation respectively, and these are added and stored. Therefore, the number of adders is as large as 16, and the number of registers is also as large as 16. Further, it is necessary for the register to hold the final result of multiplication and accumulation. Therefore, it has the wide input/output bit width of 21. Accordingly, the output bit width of the adders related to the registers and the input/output bid width of the shifter are also 21, which means that the circuit scale is considerably large. Further, an output having a large bit width of the register is fed back to the adders through the shifter. This means that there are much changes in signals and much power consumption.

Discrete cosine transformer and inverse discrete cosine transformer


Provided is a peeling apparatus configured to suppress damage to a substrate, by forming a peeling start point. The peeling apparatus separates a superimposed substrate made by joining first and second substrates into the first and second substrates, and includes a blade configured to form a notch as a peeling start point between the first and second substrates, and an inspection unit configured to inspect a state of a cutting edge of the blade. The inspection unit includes an imaging unit configured to image the cutting edge of the blade, and an image processing unit configured to process an image of the imaging unit.

Recently, in a process of manufacturing a semiconductor device, for example, the diameter increase and thickness reduction of a substrate such as, for example, a silicon wafer or a compound semiconductor wafer, is progressing. A large and thin substrate may be warped or cracked during conveyance or polishing. Therefore, the conveyance or polishing is performed after gluing a separate substrate to the substrate to reinforce the substrate, and then a peeling process is performed so as to separate the substrates from each other. Further, in order to form a peeling start point when peeling the substrates from each other, a blade is inserted between the substrates to form a notch (see, e.g., Japanese Patent Laid-Open Publication No. 2014-165281).

Peeling apparatus, peeling system, and peeling method


A child's book stand is provided which includes a first support member, a second support member, and at least one elongated shelf which may be removably attached to either the first support member or the second support member. Each shelf has a protruding lip that extends along the front of the shelf, and each shelf is adapted for displaying a book in a forwardly facing orientation. The first support member may be removably connected to the second support member at their top and mid portions. The first support member and the second support member may also be separately mounted on a wall.

The present invention relates generally to a child's book stand, and more particularly to a child's book stand which displays books in a forwardly facing orientation.
Children below reading age can often select their own books by looking at descriptive pictures on the front covers of books. Therefore, many children's book stands display books in a forwardly facing orientation, i.e. with the front covers of the books facing the child. Double-sided children's book stands which can display books on either side of the unit are known in the art.
However, most conventional children's book stands are not adapted to be easily altered in any significant manner in order to serve a multi-purpose function. Furthermore, children's book stands are generally constructed of a relatively heavy material such as wood and thus are not easily transportable. These conventional book stands can be supplied with caster wheels in order to facilitate moving the book stands short distances, e.g. from room-to-room, but their weight still makes it difficult for these book stands to be transported any significant distance. Such book stands are not adapted to be easily lifted in the air and mounted on a wall.
In addition, conventional book stands are typically constructed of several panels of wood which are fitted together. It is not possible for a children's book stand that is constructed of wood to be formed as an integral unit. For example, a standard wood-framed book stand is comprised of at least four separate pieces of wood (two sides, a bottom, and a back) in addition to each shelf. Thus, manufacturing and assembling a wood-framed book stand may be relatively complex and costly.
Furthermore, most conventional children's book stands have shelves which are either permanently mounted in set positions relative to one another or may be somewhat adjustable to a very limited number of positions. This restriction, in addition to being inconvenient, may limit the height of books that may be displayed. Furthermore, the depth of shelves (i.e. the approximate distance from the front of the shelf to the book stand) in conventional children's book stands is generally not adjustable in size, which may limit the thickness, as well as the height, of books that may be displayed.


Techniques are provided which aggregate user selected content using a browser extension. A user may select content displayed in a web browser. The selected content may be captured, and the corresponding bibliographic information may be extracted by the browser extension. The user may input notes relating to the selected content. The selected content, bibliographic information and notes may be transmitted by the browser extension to one or more servers for storage, and may be associated with a user project entry. A subset of the bibliographic information may be presented to the user in accordance with a user selected bibliographic format.

Information research plays an expanding role in our economy and personal lives. For most of us, even the information research we conduct professionally today hails back to fundamental information research practices introduced to us in our educational years. But recent decades have seen huge changes in the sources and forms of information to be researched, and the student becomes a convenient example. Conventionally, students typically performed research for a school project by going to the library, and locating and photocopying books and magazine and newspaper articles that pertain to the topic of the school project. However, since the advent of the Internet and due to the popularity of search engines, students are now much more likely to perform such research online. For example, various search engines often serve as a launch pad for an educational research project. A student may collect web pages that pertain to the topic of the school project, for instance, in lieu of going to the library and locating relevant books and magazine and newspaper articles. However, given the convenience and speed of the Internet, as well as the characteristic operation of the tools used to access Internet data, the information obtained may quickly become unmanageable. Organizing this information may thus become overwhelming and time consuming.

Aggregating missing bibliographic information in a collaborative environment