An electrical card connector for receiving at least two different cards, comprises: an insulative housing; a plurality of contacts received in the housing; an L-shaped shell assembled on the housing defining a receiving space for receiving the card; and a guide member assembled on the shell with a spring plate extending into the receiving space. When an L-shaped electrical card inserts into the connector, it could be keep in the connector steadily because of the friction between the card and the spring plate.

1. Field of the Invention
The present invention generally relates to an electrical card connector, and more particularly to an electrical card connector having a high transmission speed.
2. Description of Prior Art
With the development of portable computer, the dimension gets more and more smaller so that it need more memory cards to meet the requirement. Accordingly, more and more electrical card connectors are widely used in the portable computer. Nowadays, the portable computer always is used in a jolty environment, so it is important to provide a stable signal transmission between the electrical card and the connector in the portable computer.
A prior art discloses such an electrical card connector comprising a housing, a shell covering the housing and a plurality of contacts received in the housing. Said shell is configured of an L-shape with a notch besides said housing, a guide member is attached to the shell near the notch for guiding the electrical card inserting. When the electrical card is inserted into the connector, a retaining force is formed between the contacts and the card to hold the card in the connector in a steady environment. But the retaining force is so limited that the electrical card may escape from the connector in a jolty environment to affect the normal using of the computer.
Hence, it is desirable to have an improved card connector to overcome the above-mentioned disadvantages of the prior art.

Electrical card connector with guide member


A field emission cold cathode comprises an n-type silicon substrate (1), a plurality of sharp-pointed emitter cones (2) formed on the n-type silicon substrate (1), and a buried insulator layer (3) formed in the n-type silicon substrate (1) to surround each of underlying regions right under each emitter cone (2). An insulator layer (4) is formed on the n-type silicon substrate (1) and has a plurality of insulator holes so as to surround each emitter cone (2). A gate electrode (5) is formed on the insulator layer (4) and has a plurality of gate holes for extracting electrons from the emitter cones (2).

This invention relates to a field emission cold cathode for emitting electrons in response to an electric field applied between an electron source or emitter and a gate electrode without heating the emitter.
Generally, a field emission cold cathode comprises a semiconductor substrate operable as a part of an emitter, a plurality of sharp-pointed emitter cones formed on the semiconductor substrate, and a gate electrode having a plurality of gate holes each of which is formed around a tip of each emitter cone. The field emission cold cathode is responsive to an electric field applied between the emitter cones and the gate electrode to emit electrons from the tip of each emitter cone.
Description will hereafter be made about a typical field emission cold cathode as a first conventional device.
Referring to FIG. 1, the first conventional device comprises an n-type silicon substrate 31, a plurality of sharp-pointed emitter cones 32 formed on the n-type silicon substrate 31 as an emitter array, and a gate electrode 34 having a plurality of gate holes for passage of electrons emitted from tips of the emitter cones 32. Typically, an insulator layer 33 is interposed between the n-type silicon substrate 31 and the gate electrode 34. The insulator layer 33 has a plurality of insulator holes so as to surround each emitter cone 32.
In the first conventional device of the above-mentioned structure, spike noise of a large amplitude may often be caused to occur when it is switched on. Following occurrence of the spike noise, discharge may instantaneously be caused between the gate electrode 34 and the emitter cones 32.
In case where the discharge is continued, the emitter cones 32 will generate heat and begin to melt. Melted portions of the emitter cones 32 are splashed and adhered to the gate electrode 34 to result in short circuit between the gate electrode 34 and the emitter cones 32.
In order to avoid such short circuit between the gate electrode and the emitter cones 32 resulting from the continuous discharge, proposal is made of modified field emission cold cathodes which will hereunder be described as second and third conventional devices.
Referring to FIG. 2, the second conventional device comprises a resistor layer 35 interposed between the n-type silicon substrate 31 and the emitter cones 32. The resistor layer 35 has a high resistance and serves to restrict an electric current flowing to the emitter cones 32. With this structure, the electric current is suppressed to a level such that the above-mentioned short circuit does not occur.
Referring to FIG. 3, the third conventional device disclosed in Japanese Unexamined Patent Publication (JP-A) No. 87957/1996 comprises a plurality of field effect transistors (FET) in one-to-one correspondence to the emitter cones 32. Specifically, for each emitter cone 32, two n-type regions 37 are formed in a p-type silicon substrate 36. One of the n-type regions 37 serves as an FET source region with an FET source electrode 39 mounted thereon while the other n-type region 37 serves as an FET drain region. The emitter cone 32 is located on the drain region. An FET gate electrode 38 is located on the insulator layer 33 between the FET source and the FET drain regions both of which are formed in the p-type silicon substrate 36.
With this structure, the electric current flowing to the emitter cone 32 can be controlled by an input voltage applied to the FET gate electrode 38 so as to flow a constant current to the emitter cone 32. It is thus possible to avoid occurrence of the discharge.
However, the above-mentioned second and the third devices have following disadvantages.
In the second conventional device, voltage drop becomes inevitably large due to the resistor layer 35. It is therefore required to increase a drive voltage applied between the gate electrode 34 and the emitter cones 32. As seen from the figure, the resistor layer 35 is continuously formed in common to the emitter cones 32, not separately in one-to-one correspondence thereto. If the emitter cones 32 are arranged at a smaller interval to increase the density, an electromagnetic interference between the emitter cones is inevitable in this structure. This makes it difficult to effectively control an emission current from each individual emitter cone 32. In addition, the resistor layer 35 has a central zone and a peripheral zone surrounding the central zone. The central zone is remote from the peripheral zone. In this connection the central zone of the resistor layer 35 has a higher resistance value than the peripheral zone. This results in an increase of voltage drop at the central zone. As a consequence, it is difficult to emit the electrons from the emitter cones 32 located nearer to the central zone.
On the other hand, the third conventional device comprises the FETs in one-to-one correspondence to the emitter cones 32. This inevitably requires a complicated manufacturing process and increases the production cost. In addition, the size of the device is increased because the FET is provided for each of the emitter cones 32. Furthermore, the density of the emitter cones 32 can not be increased.
Another field emission cold cathode is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 106846/1996 and will hereunder be described as a fourth conventional device. The fourth conventional device has a groove around the gate electrode surrounding the emitter array of the emitter cones. With this structure, it is possible to prevent occurrence of a leak current at an outer peripheral edge of the emitter array where the emitter cones and the gate electrode are exposed.
However, in the fourth conventional device, it is impossible to avoid decrease of the resistance value in the semiconductor substrate at portions right under the emitter cones.
In the meanwhile, an electron emission characteristic is affected by a contact resistance between the bottom of each emitter cone and the silicon substrate. The contact resistance is increased with a decrease in contact area therebetween, namely, a decrease in bottom area of each emitter cone. With development of the semiconductor technology, a more and more finer structure is sought. As the structure becomes fine, the bottom area of each emitter cone also becomes small in area. Such a small bottom area or contact area brings about an increase of contact resistance as described above. This unfavorably affects the electron emission characteristic.
In fact, a structure capable of avoiding the increase in contact resistance is already proposed in Japanese Unexamined Patent Publication (JP-A) No. 138636/1992 and will hereunder be described as a fifth conventional device. The fifth conventional device comprises a silicide layer as an interface between the silicon substrate and the emitter cones. The presence of the silicide layer serves to suppress the increase of contact resistance.
However, even with the fifth conventional device, it is difficult to overcome the increase of contact resistance resulting from drastic decrease in size of emitter cones following the rapid development in semiconductor technology.
In addition, if the silicide layer is excessively thick, the emitter cones may be inclined or lowered in height.

Field emission cold cathode with buried insulator layer


A semiconductor memory device for minimizing the resistance attendant on reaching as far as each sense amplifier connected to a memory cell. A first plurality of power supply lines are alternatively disposed between column select lines which is formed over a plurality of lines of semiconductor memory device in a column direction. The first plurality of power supply lines the first plurality of ground lines are connected to a second plurality of power supply lines and a second plurality of ground lines which are disposed under the column select lines in a row direction, to thereby provide a netlike power supply structure. Consequently, the operating speed of a chip is improved by minimizing the resistance attendant on reaching as far as the sense amplifiers connected to each memory cell and the efficiency of the semiconductor memory device is greatly promoted by suppressing a coupling phenomenon caused between the column select lines.

The present invention relates to a semiconductor memory device and particularly to a method for arranging power supply lines which are laid out so as to ensure that each memory element conducts sensing operations at high speed.
The more highly a semiconductor memory device is integrated, the greater the problem achieving high-speed operations. It is widely known in this field that sensing operations of a bit line must be conducted at a high speed rate for high-speed operations of a chip. However, the more highly a semiconductor memory device is integrated, the chip increases in size and a metal layer covering a memory array decreases in width. This causes its metal wiring resistance to grow and results in lowering its high-speed operations. Particularly, the resistance of the power supply lines which are connected between memory cells and a power supply voltage terminal and a ground voltage terminal is great considerably, and it is so directly related to lowering sensing speed that the study of the power supply line layout is now prosecuted earnestly.
The conventional memory array power supply line layout is illustrated in FIGS. 1A to 1D.
FIG. 1A takes a 1-Mega dynamic random access memory (DRAM) as an example. The memory is divided into a memory cell array area 10 and a periphery area 10'. A pull-up driver 2 for sensing is connected to a Vcc-pad to which a power supply voltage is applied; and a pull-down driver 1 for sensing is connected to a Vss-pad to which a ground voltage is applied. A plurality of memory cell sensing blocks 5 are in the memory cell array area 10, and the Vcc-pad and the Vss-pad are connected to the memory cell sensing blocks 5. In this case, a line connected to the Vcc-pad is called the power line and a line connected to the Vss-pad is called the ground line. The power and ground lines are commonly called the power supply line.
FIG. 1B takes a 4-Mega DRAM as an example. The memory is similar to FIG. 1A, having one difference from FIG. 1A in that the pull-down drivers for sensing 11, 12 are disposed in each sense amplifier within the memory cell array area 20.
FIG. 1C takes a 16-Mega DRAM as an example. Pull-up and pull-down drivers for sensing are within the memory cell array area. It is aptly shown in FIG. 1C which is a partially detailed view of block 18 in FIG. 1D. A column select line CSL for selecting a given corresponding column, a word line strap area are shown in FIG. 1C.
Now, the characteristics of FIGS. 1A to 1D will be described hereinafter.
In the case of 1-Mega DRAM in FIG. 1A, the pull-up and pull-down drivers 2, 1 for sensing are disposed in the periphery area 10' so that the power and ground lines 4, 3 respectively have a considerable amount of resistances R1, R2 and R3, R4 in the memory cell array area 10.
In the case of 4-Mega DRAM which is improved from the 1-Mega DRAM, as illustrated in FIG. 1B, a pull-up driver 13 for sensing is disposed in a periphery area 20' and the pull-down drivers 11, 12 for sensing is disposed in each sense amplifier within the memory cell array area 20 but, as a power line is and a ground line, 14 respectively connected to each driver 11, 12 are each a single path, there is a limit in reducing resistances R5, R7, R8, . . . , etc.
In the case of 16-Mega DRAM as illustrated in FIGS. 1C and 1D, since a pull-up and pull-down drivers 22, 21 for sensing separately is disposed in each word line strap area (which is possible because the width of word line strap area becomes relatively larger by a improvement of design rule), resistance between each sense amplifier 23 and the pull-up and pull-down drivers 22, 21 for sensing is thereby reduced to a considerable degree. However, as it is possible to connect the pull-up and pull-down drivers 22, 21 for sensing to each power supply line only in the word line strap area where there are several power supply lines, there is a limit in reducing total resistance. As illustrated in FIG. 1D, the column select lines CSL which select a column of memory cell within block 17 are so situated as to be adjacent to each other that it leads to erroneous operations by causing a coupling phenomenon between the column select lines CSL.

Semiconductor memory device having netlike power supply lines


A synthetic substrate used for quantitative analysis of a trace enzyme. The substrate has a molecular structure (B)-(A)-(C) comprising at least one structure (A) catalytically affected by the enzyme to be analysed, at least one photographically active labelling structure (B) linked to the structure (A) and at least one specific adsorbing structure (C) linked to the structure (A). The substrate is used in a quantitative analysis of a trace enzyme, in which the structure (A) or the linkage between the structure (A) and the structure (C), or the linkage between the structure (B) and the structure (A) is cleaved by the action of the analyte enzyme. The reaction product of the enzymatic reaction is separated by allowing the same to contact with an adsorbent for the structure (C). The separated reaction product is developed photographically and then the optical density of the resultant developed silver and/or colored dye is measured.

1. Field of the Invention
The present invention relates to a method for quantitative measurement of a trace enzyme, and particularly to a method for photochemical measurement of the activity of a trace enzyme and a substrate used therein.
2. Prior Art Statement
Various methods have hitherto been developed for measuring the activity of a trace enzyme. For example, there are: a turbidimetric method wherein the decrease in turbidity caused by an enzyme reaction is traced using a suspension of high molecular weight substrate; an absorptiometric method wherein a high molecular weight substrate is decomposed or cleaved by an enzyme and, after precipitating and removing undecomposed substrate, soluble component is determined by an absorbance measurement; a method wherein a dye or fluorescent substance is previously bound to a high molecular weight substrate, an enzymatic reaction is effected to decrease the molecular weight of the dye or fluorescent substance, and the fractionated dye or fluorescent substance of lower molecular weight is measured; and a method of quantitative assay wherein, using a substrate which is designed to change in absorption spectrum, one forms a color or forms a fluorescent substance, based on a splitting-off or change in part of the substrate after an enzymatic reaction, and the resulting absorbancy or fluorescent intensity is measured, etc. (SEIKAGAKU JIKKEN KOZA (Lectures on Biochemical Experiments), vol. 5, subtitled "Study on Enzymes", edited by the Japanese Biochemical Society, published by Tokyo Kagaku Dojin, 1975.)
Most of these methods, however, quantitatively determine an amount of enzyme on the order of, .mu.g/ml. Even utilizing a type of substrate releasing a fluorescent substance (e.g. derivatives of umbelliferone, etc.), which is recognized to be most sensitive among these conventional methods, it is only possible to measure an enzyme quantity on the order of ng/ml.
Therefore, in activity measurements of trace enzymes labelled in accordance with an enzyme immunoassay, the development of more stable and more highly sensitive enzyme activity measurement methods has been demanded.
Further, since the enzymes as biocomponents in blood, body fluids, urine and in tissues in the living body such as various organs, the brain, etc. mostly are present in a very small amount, except for certain enzymes (amylase, GOT, GTP, etc.) which exist in a large amount, such enzymes cannot be determined by conventional measurement methods. Therefore, a radioimmunoassay (hereinafter referred to as "RIA") which is an immunological measurement method using a radioactive isotope has recently been introduced. The principle of RIA is described in, for example, Kumahara and Shizume, RADIOIMMUNOASSAY, New Edition, pages 3 to 10 (1977), published by Asakura Publishing Co., Ltd., KISO SEIKAGAKU JIKKENHO (Basic Biochemical Experiments) (6), Biochemical Assay (1967), published by Maruzen Co., Ltd., Tokyo, METHODS IN ENZYMOLOGY, edited by Sidney P. Colowick et al., vols. I, II, III, V and VII, published by Academic Press, New York and The Enzyme, vols. 3, 4 and 5, Paul D. Boyer et al. (1071), published by Academic Press, New York.
However, RIA as a quantitative assay for enzymes has disadvantages such as: (1) since it is an immunoassay which detects a quantity of enzyme, there is a possibility that the activity of an enzyme -which is the functional characteristic of the enzyme- will not be actually reflected; (2) there is a possibility that analogous enzymes and precursors having a similar antigenic site might be included in analytical data; and (3) in the case where the enzyme to be measured, for example, such a label enzyme used for the enzyme immunoassay, is bound to an other component and not present in the free state, it is difficult to prepare an antibody against the aforesaid labelled antigen or antibody and the design for a method for measurement is practically difficult.
RIA has further disadvantages due to the use of radioisotopes. That is: (1) potential injury to the person dealing with radiation is a matter of concern; (2) special places and controls are required for storage and waste disposal of the radioactive substances used; (3) the amount of radiation from the radioisotope is reduced with the passage of time due to the half decay of the isotope; and (4) measurement of the amount of radioactivity requires expensive devices.
The information obtained by measuring enzyme activity using a specific substrate under given reaction conditions (e.g. concentration of substrate, total volume, reaction pH, reaction temperature, reaction time, ionic strength, salts co-existent, etc.) is generally classified as follows.
(1) The sum of enzyme activities having a catalytic action on the structure of the substrate in the system; or
(2) Under the condition of constant enzyme concentration, the degree of inactivation depending upon purity of the enzyme, the presence or absence of inhibitors, intensity of inhibition, denaturation, etc., i.e. measure of specific activity.
Finally, the purpose of measuring the activity of an enzyme as a component in the living body is frequently to obtain mainly information per (1) above and the purpose of activity measurements of enzyme-labelled materials exterior living body is to obtain mainly information per (1) and (2) above. As is well known, in any case, specific enzyme to the living body is to obtain mainly information per (1) and (2) above. As is well known, in any case, specific enzyme activity can only be measured by selecting a substrate corresponding to the enzyme specificity.
The term "specificity" used throughout the specification is art-recognized and defines selective reactivity between substances, e.g. of an enzyme with its corresponding substrate.
Japanese Patent Publication Nos. 1118/1986 (U.S. Pat. No. 4,414,325) and 1119/1986 (U.S. Pat. No. 4,414,323) disclose a method for quantitative measurement of a trace enzyme, wherein an enzyme substrate having therein a photographically active material (a spectroscopically sensitizing dye or a fogging agent) as a labelling material is used so that the activity of a trace enzyme is photochemically determined.
The method disclosed in U.S. Pat. No. 4,414,323 is a method for measurement of an emzyme activity and/or a quantity of an enzyme comprising the steps of providing a synthetic substrate comprising at least one photographically active labelling structure (B) serving as a labelling material by contacting it with silver halide grains to form nuclei capable of being developed (a spectroscopically sensitizing dye or a nucleating agent (fogging agent)) and at least one structure (A) to be specifically contacted with the enzyme to be measured; bringing either the reaction product containing the photographically active labelling structure (B) formed by the enzyme reaction or the unreacted synthetic substrate into contact with silver halide followed by development; and measuring the amount of developed silver and/or the amount of colored dye obtained as an optical density.
The method referred to in the preceding paragraph provides not only a very high sensitivity but also is effectively applied to the situation where an enzyme is in the form of a conjugate or complex thereof with other organic materials (e.g. polymers, latexes, microcapsules, membranes including membranes in living bodies and ion exchange membranes, bacteria, microorganisms, components in living bodies such as hormones, peptides, proteins, lipoproteins, glycoproteins, glucosides and lipids, toxic substances, drugs, antibiotics, etc.).
In a method for quantitative determination of an enzyme activity, the sensitivity of the method depends mainly on the following two factors. The first factor is the absolute sensitivity of the substance used for generating the detected signal, and the second factor is how to detect the signal from the product of the enzymatic reaction.
As to the absolute sensitivity limited by the used substance, the limit for detection is an the order of 10.sup.-6 mole/l when a dye is used as the product of the enzymatic reaction, and the limit for detection is an the order of 10.sup.-9 mole/l when a fluorescent material is used as detectable signal. On the other hand, when a photographically active material is used as above-described, the limit for detection is improved to the order of 10.sup.-11 mole/l.
In the actual determination of an enzyme activity while using a photographically active material, the limit for detection depends on the density of the produced signal material which is detectable as having a significant difference from the background. In the colorimetric method wherein a dye is used, the density of the background does not affect the result of determination and the sensitivity of the method is affected only by the molecular absorption coefficient of the used signal material. In the method wherein a fluorescent material is used, the density of the background is often increased by the purity of energized light, dusts contained in the medium, entangled particles, dispersed materials or contamination of other fluorescent materials to lower the sensitivity to the order of 10.sup.-8 mole/l. The sensitivity of the method wherein a photographically active material is used depends on the purity of the product of the enzymatic reaction separated from the unreacted synthetic substrate.
In the method wherein a photographically active material is used, contamination with materials exhibiting similar functions as that of the used photographically active material need not be taken into account in view of the structure of the photographically active material. This is because the background is induced by the contaminating unreacted synthetic substrate in the step of detecting the photographically active material in the product of the enzymatic reaction. In general, a substrate is used in a concentration of from 10.sup.-2 to 10.sup.-6 mole/l in ordinary enzymatic reaction, and the substrate is used in a relatively high concentration when a trace enzyme is to be detected. Although 10.sup.-7 to 10.sup.-9 mole/l of a product of the enzymatic reaction should be detected in the low sensitivity range (10.sup.-7 to 10.sup.-9 mole/l), separation can be effected relatively easily by the conventional methods wherein the differences in chemical and physical properties between the reaction product of the enzymatic reaction and the unreacted synthetic substrate are detected. For example, both components may be separated from each other, utilizing their difference in absorptive property to silver halide or using another proper separation method (for example, ion exchange chromatography, affinity chromatography, high speed liquid chromatography, TLC, salting out, centrifugal separation, co-precipitation with a polymer, decantation, ultrafiltration, use of an adsorbent such as activated charcoal, etc.) The details thereof are described in DATABOOK OF BIOCHEMISTRY, Chapter 10, second separate volume, edited by Japanese Biochemical Society, published by tokyo Kagaku Dojin, 1980.
In the maximum sensitivity range, it is necessary to detect 10.sup.-9 to 10.sup.-11 mole/l of a reaction product of enzymatic reaction. Namely, it becomes necessary to separate 10.sup.-9 to 10.sup.-11 mole/l of a pure reaction product from a solution or suspension containing 10.sup.-2 to 10.sup.-6 mole/l of a synthetic substrate.

Method for quantitative measurement of trace enzyme and substrate used therein


An IC card capable of effectively preventing electrostatic breakdown of an IC even when it is charged with static electricity is provided. In the IC card, a discharging member (2 to 5) of a non-insulator is provided at a portion of IC card (1). Thus, even when IC card (1) is charged with static electricity, discharge current of static electricity is discharged through discharging member (2 to 5), so that the discharge current is effectively prevented form flowing into IC (101). As a result, even when IC card (1) is charged with static electricity, electrostatic breakdown of IC (101) is prevented, whereby breakdown or malfunction of entire IC card (1) is avoided.

The present invention relates to IC cards, and more specifically to an IC card including an integrated circuit (IC) for performing data transmission.
Some IC cards perform data transmission with a terminal electrically connected to a control portion, while others perform data transmission in a non-contact state. In the non-contact type IC card, power is obtained form a radio wave from an antenna for transmission of information stored in the internal non-volatile memory. Such non-contact type IC card is used for a gate of the ski lift, gate at the station and sorting of parcels and the like.
FIG. 6 is a schematic diagram showing a structure of a conventional non-contact type IC card. As shown in FIG. 6, a conventional non-contact type IC card 1 includes an IC 101 and an antenna 102 connected to IC 101. IC 101 and antenna 102 are contained in IC card 1. IC card 1 is generally formed of an insulating material such as polyester or vinyl chloride. The non-contact type IC card as shown in FIG. 6 is generally referred to as an and antenna 102 are both conductive and have lower resistance as compared with IC card 1. Thus, when static electricity or the like is externally transferred to IC card 1, discharge current of the static electricity may flow into IC 101 and antenna 102. If the discharge current of static electricity flows into IC 101 and antenna 102, electrostatic breakdown of IC 101 is caused. As a result, breakdown and malfunction of the entire portion of IC card 1 are disadvantageously caused.
More specifically, as shown in FIG. 7, for example, assume that a portion A of IC card 1 is held by a person charged with static electricity when a portion B is grounded. In this case, discharge current of static electricity first flows into that portion of insulating material at the surface of IC card 1 which is positioned at A, and then into IC 101 and antenna 102 of IC card 1 for being discharged from portion B. This may lead to a problem associated with breakdown of the entire card including IC 101 and antenna 102. Such problem also arises, for example, when a ground rod is brought closer to the electrically charged card.
The present invention is made to solve the aforementioned problem, and it is an object to provide an IC card capable of effectively preventing electrostatic breakdown of an IC even when the IC card is charged with static electricity.
An IC card according to the present invention includes an integrated circuit (IC) and is characterized in that a portion thereof is provided with a discharging member of a non-insulator. Such provision of the discharging member of the non-insulator enables discharge current of static electricity to be discharged through the discharging member, thereby effectively preventing the discharge current from flowing into the integrated circuit even when the IC card is charged with static electricity. Thus, electrostatic breakdown of the integrated circuit is prevented even when the IC card is charged with static electricity, so that breakdown or malfunction of the entire IC card is prevented. In the above structure, the discharging member may be provided in a prescribed region other than that where the integrated circuit of the IC card is arranged. In the above structure, the discharging member may include a metal layer formed on an inner surface of a through hole in the IC card. In the above structure, the discharging member may have a thickness which is at least greater than those of the antenna and integrated circuit (IC). In the above structure, the discharging member may be provided at a periphery of the IC card. In the above structure, the discharging member may be provided on the surface of the IC card in a mesh like manner. More preferably, in the above structure, the discharging member is provided to surround the integrated circuit. Such provision of the discharging member to surround the integrated circuit also enables the static electricity to be discharged through the discharging member surrounding the integrated circuit when the IC card is charged with the static electricity, so that the discharge current is prevented from flowing into the integrated circuit. In other words, the discharging member functions as a shield for protecting the integrated circuit. More preferably, in any of the above mentioned structures, the non-insulator forming the discharging member may be any of conductive rubber, conductive resin, conductive coating and metal.


A method of performing cooperative transmission in a multi-node system including a Base Station (BS) and a plurality of nodes controlled by the BS is provided. The method comprises: transmitting a first signal generated using a first cell identifier (ID) from the plurality of nodes; and transmitting a second signal generated using a second cell ID from at least one of the plurality of nodes, wherein the first cell ID is identical with a cell ID used by the BS, and the second cell ID is different from the first cell ID.

1. Technical Field
The present invention relates to wireless communication and, more particularly, to a method and apparatus for performing cooperative transmission in a multi-node system.
2. Related Art
In a current wireless communication environment, the required amount of data for a communication network is rapidly increasing according to Machine-to-Machine (M2M) communication and the appearance and spread of various devices, such as smart phones and tablet PCs which require a great amount of data transmission. In order to satisfy a great amount of data transmission, communication technology is being developed into carrier aggregation technology for efficiently using a greater frequency band, cognitive radio technology, multi-antenna technology for increasing the data capacity within a limited frequency, multi-base station cooperation technology, and so on.
Furthermore, a wireless communication environment is evolving into an increase in the density of nodes which may access user peripheries. Here, the nodes refer to antennas or a group of antennas which are spaced apart from one another at specific intervals in a Distributed Antenna System (DAS). In the present invention, however, the nodes are not limited to the above meaning, but may be used in a broad sense. The node may include not only a macro base station in a cellular network, but also a device having a small coverage, such as a pico cell base station (PeNB), a home base station (HeNB), a Remote Radio Head (RRH), a Remote Radio Unit (RRU), a relay station, a distributed antenna, a WiFi Access Point (AP), a femto AP, or a pico AP.
A wireless communication system including a high density of nodes may have better system performance through cooperation between the nodes. That is, nodes cooperating with each other have more excellent system performance than nodes not cooperating with each other, each of which is operated as an independent Base Station (BS), Advanced BS (ABS), Node-B (NB), eNode-B (eNB), and AP.
There is a need for a method and apparatus which can perform cooperative transmission by utilizing each node in a multi-node system.

Method and apparatus for cooperative transmission in multi-node system


A bicycle display device is configured to accurately verify an amount of adjustment occurring when performing a fine adjustment of a transmission position of a transmission device. The bicycle display device is mounted on a bicycle, and includes a mounting part and a display element. The mounting part is attachable to a brake bracket of the bicycle. The display element is supported by the mounting part, and is configured and arranged to display a fine adjustment display screen for indicating the amount of adjustment when adjusting the transmission position of a transmission device such as a rear derailleur.

1. Field of the Invention
This invention generally relates to a bicycle display device configured to be mounted on a bicycle. More specifically, the present invention relates a bicycle display device that indicates an amount of adjustment when adjusting a transmission position of a transmission device such as a rear derailleur.
2. Background Information
Bicycling is becoming an increasingly more popular form of recreation as well as a means of transportation. Moreover, bicycling has become a very popular competitive sport for both amateurs and professionals. Whether the bicycle is used for recreation, transportation or competition, the bicycle industry is constantly improving the various components of the bicycle.
Currently, many bicycles are equipped with a display device that is mounted on a handlebar for displaying a transmission position (see, for example, Japanese Laid-Open Patent Publication No. 09-024876). Conventional bicycle display devices are sometimes fixed to a brake bracket that is mounted on the handlebar. A rider can be instantly alerted to the transmission gear ratio via such a display of the transmission position, and can rapidly perform gear shifting operations in accordance with changes in road conditions.
When the positional relationship between the sprocket and chain guide moving in the axial direction is misaligned in such transmission devices, and particularly in externally mounted transmission devices, the chain chatters and shifting can not be accomplished smoothly. To prevent this occurrence, consideration has been given to making fine adjustments of the position of the chain guide relative to the sprocket (e.g., by electrically actuating the chain guide in an electrically-driven derailleur capable of electrically controlling a derailleur).
When the amount of adjustment of the transmission gear position can not be correctly perceived when making this fine adjustment, the amount of completed adjustment, or the amount of possible further adjustment after this adjustment can not be known, such that the fine adjustment operation requires considerable time. Particularly when performing this fine adjustment while riding, the fine adjustment operation may cause delay since it is difficult to directly verify the chain guide position by visual inspection.
Furthermore, when the operation part for entering the fine adjustment mode to perform the fine adjustment of the chain guide is placed near the hand that performs the gear shifting operation, such as on the handlebar or the like, there is concern of mistakenly entering the fine adjustment mode by misoperation when shifting gears. When the fine adjustment mode is entered while operating the bicycle, the rider can not perform the gear shifting operation, and there is concern of devastating time loss, particularly when such misoperation occurs during a race.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved bicycle display device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.


A first host computer writes data as an object of transfer and its location information to a storage subsystem. A second host computer reads out the data as an object of transfer which has been written to said storage subsystem on the basis of the location information thus written thereto. As a result, the data transfer between the host computers can be carried out employing the storage subsystem.

The present invention relates to a method of transferring data between host computers employing a storage subsystem.
In recent years, xe2x80x9cthe down sizingxe2x80x9d for carrying out the operations of a business, conventionally carried out in a main frame, are now being performed by a small computer such as a personal computer or a workstation. A large amount of information generated as a result of operating the business is stored in the main frame and hence there is now a need for information stored on the main frame to be accessed by a small computer too. In addition, there is also the request that by using a high speed and highly reliable backup device connected to the main frame, backup for the data of the small computer is also desired.
Conventionally, with respect to the method of transmitting data between the different operating systems, there are well known an FTP (File Transport Protocol) and a distributed database.
In the above-mentioned prior art, a host computer of interest reads out temporarily data from a storage device such as a disk storage device and the data is delivered between the host computer through a network which has a protocol common to a plurality of host computers. But, the transfer rate of the network is relatively low and hence it is difficult to obtain a sufficient transfer rate. In addition, increase in the load on the network is not preferable in terms of the system.
In the light of the foregoing, the present invention was made in order to solve the above-mentioned problems associated with the prior art, and it is therefore an object of the present invention to provide a method of transferring data through a storage device such as a disk storage device instead of the network which has been conventionally used in the data transfer between the systems.
A computer system according to the present invention includes: a first computer; a second computer; a network for communication between the first and second computers; and a storage subsystem having a plurality of interfaces which are connected to the first and second computers.
The first and second computers are mutually accessible to data in the storage subsystem. When transferring the data from the first computer to the second computer, the first computer writes the transfer data to the storage subsystem. At the same time, the first computer writes to the storage subsystem the control information, which is required to transfer the data, such as the location in the storage subsystem to which the transfer data has been written. Then, the second computer reads out the control information which the first computer has written to the storage subsystem, and also on the basis of the control information thus read out, reads out the transfer data which the first computer has written to the storage subsystem.
After having read out the transfer data, the second computer writes to the storage subsystem the control information such as the location of the transfer data which the second computer has read out from the storage subsystem. Then, the first computer reads out the control information which the second computer has written to the storage subsystem, and recognizes that the second computer has completed the operation of reading out the transfer data, and also writes both of the transfer data and the control information to the storage subsystem again. In this connection, the transfer data can be overwritten to the region of the storage subsystem as long as the second computer has already read out the data from the region of interest. By repeating this processing, the data transfer from the first computer to the second computer can be realized. In addition, when writing the transfer data to the storage subsystem in this data transfer operation by the first computer, the data can be overwritten to the region of the storage subsystem as long as the second computer has already read out the data from the region of interest. For this reason, by utilizing repeatedly the same region of the storage subsystem, even in the case where the amount of transfer data is larger than the scale of the storage regions in the storage subsystem, the data transfer can be carried out. In addition, by replacing the roles of the first and second computers with each other, the data transfer from the second computer to the first computer is realized.
In addition, the above-mentioned data transfer can also be realized by carrying out only the delivery of the control information between the first and second computers through the network.

First host computer through a first interface sending to a second host computer a message including information about transfer data written to a storage subsystem through a second interface


A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.

Memory devices can use a voltage difference between differential bitlines to sense the current state of a memory cell. For designs with small differential bitline levels, the output noise can feedback onto the bitlines and may collapse the bitline and TBUS differential signal levels. Due to the collapsed TBUS differential signal, an incorrect state could be sensed by the sense amplifier which can cause an output glitch, or even multiple output glitches. Static bitline load designs have poor noise immunity for small bitline voltage swings. The bitline voltage swing is presented to the TBUS through a switch.
Referring to FIG. 1, a circuit 10 illustrates a static bitline load design block diagram. The circuit 10 comprises an address path block 12, a memory array block 14, a sense amplifier block 16 and an output path block 18. The address path block 12 presents a wordline signal WL in response to an address signal. The memory array block 14 presents a signal TBUS in response to the signal WL. The sense amplifier block 16 presents a signal SAOUT in response to the signal TBUS. The output path block 18 presents a signal OUTPUT in response to the signal SAOUT.
Referring to FIG. 2, a timing diagram of the signals of FIG. 1 is shown. A signal ADDRESS has a transition 20 that indicates an external address has changed state. The signal WL has a positive transition 22 that responds to the transition 20 of the signal ADDRESS. The signal TBUS has a transition 24 that responds to the positive transition 22 of the signal WL. The signal SAOUT has a transition 26 that responds to the transition 24 of the signal TBUS. The signal OUTPUT has a transition 28 that responds to the transition 26 of the signal SAOUT. The signal TBUS has a transition 30 that responds to the transition 28 of the signal OUTPUT. The transition 30 can cause a series of transitions in the signal SAOUT and the signal OUTPUT that may ultimately lead to the sensing of incorrect data. For example, the signal SAOUT has a transition 32 that responds to the transition 30 of the signal TBUS. The signal OUTPUT has a transition 34 that responds to the transition 32 of the signal SAOUT. After a state 35, the signal TBUS has a transition 36 where the TBUS recovers to the correct state. The signal SAOUT has a transition 38 that responds to the transition 36 of the signal TBUS. The signal OUTPUT has a transition 40 that responds to the transition 38 of the signal SAOUT. The signal OUTPUT presents incorrect data between the transition 34 and the transition 40. Furthermore, a collapse of the signal TBUS may occur at a point 42 in response to the transition 34.
A conventional approach to eliminating TBUS sensitivity to output noise is to utilize large bitline swings and use address transition detection circuitry. While such a design may provide better noise immunity than the circuit of FIG. 1, it has other undesirable effects such as limiting the ultimate size of the array due to current constraints.
Referring to FIG. 3, a circuit 50 is shown illustrating such a conventional approach. The circuit 50 comprises an address path block 52, a memory array block 54, a sense amplifier block 56, an output path block 58, an address transition detect block 60 and a control block 62. The address path block 52 presents a signal WL, the memory array block 54 presents a signal TBUS, the sense amplifier block 56 presents a signal SAOUT, the output path block 58 presents a signal OUTPUT, the address transition detect block 60 presents a signal ATD and the control block 62 presents a signal PRCHG and a signal SAEN.
Referring to FIG. 4, a timing diagram of the various signals of FIG. 3 is shown. An external address signal ADDRESS has a transition 64. The signal WL has a transition 66 that responds to transition 64 of the signal ADDRESS. The signal ATD has a positive transition 68 that responds to a transition 64 of the signal ADDRESS. The signal PRCHG has a positive transition 70 that responds to the positive transition 68 of the signal ATD. The signal SAEN has a negative transition 72 that responds to the positive transition 68 of the signal ATD. The signal TBUS has a transition 74 that responds to the positive transition of the signal PRCHG. The signal PRCHG also has a negative transition 76. The signal TBUS has a transition 78 that responds to the negative transition 76 of the signal PRCHG. The signal SAEN has a positive transition 80 that responds to the negative transition 76 of the signal PRCHG. The signal SAOUT has a transition 82 that responds to the positive transition 80 of the signal SAEN. The signal OUTPUT has a transition 84 that responds to the transition 82 of the signal SAOUT. The signal TBUS has a reduced differential portion 87 that responds to the transition 84 of the signal OUTPUT. The signal ADDRESS has a second transition 86. The signal ATD has a positive transition 88 that responds to the transition 86 of the signal ADDRESS. The signal WL has a transition 90 that also responds to the transition 86 of the signal ADDRESS. The signal PRCHG has a positive transition 92 that responds to the positive transition 88 of the signal ATD. The signal TBUS has a transition 94 that responds to the positive transition 92 of the signal PRCHG. The signal PRECHG also has a negative transition 96. The signal TBUS has a transition 98 that responds to the negative transition 96 of the signal PRCHG. The signal SAEN has a negative transition 100 that responds to the positive transition 88 of the signal ATD. The signal SAEN has a positive transition 102 that responds to the negative transition 96 of the signal PRCHG. The signal SAOUT has a transition 104 that responds to the positive transition 102 of the signal SAEN. The signal OUTPUT has a transition 106 that responds to the transition 104 of the signal SAOUT.
Additional conventional approaches may include using an output buffer reference control circuit. Such a reference control circuit may trade off noise control with speed. However, such a reference control circuit may be difficult to design over process corners. Glitch filters may be implemented as another approach to providing noise immunity. However, such glitch filters may have a negative impact on the speed of the device. The addition of split-power busses to isolate noisy power supplies may be implemented as another approach. However, such split-power busses increase the overall die size as well as make the overall power bussing more complex.

Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity


A method for dynamically controlling a driver of a nip roller in a web printing press includes controlling the speed of the driver in a tension-control mode during a phase of printing press operation and in a velocity-control mode during another phase of printing press operation. The controlling of the speed of the driver in the tension-control mode is based on the tension in the web upstream of the nip roller so as to maintain the tension at a desired tension value. The controlling of the speed of the driver in the velocity-control mode is based on a predetermined driver velocity ratio for maintaining the web tension. The tension-control mode may be employed during press start-up as the web accelerates to operating speed. The velocity-control mode may be used during printing operations of the press.

1. Field of the Invention
The present invention relates generally to web printing presses and more particularly to a method and apparatus for dynamically controlling a driver of a nip roller in a web printing press.
2. Background Information
Web printing presses print a continuous web of material, such as paper. Tension in the web must be maintained within a desired range in order to achieve smooth operation of the printing press. Paper differences, environmental conditions in the pressroom, as well as press evolutions such as web splicing and blanket washing, may cause web tension variations. At the same time, the velocity of the web, and hence the rotational speed of non-slip nip rollers moving the web, must be held relatively constant to achieve good print product quality. Some prior printing presses have controlled the speed of the non-slip nip rollers. These presses require the intervention of a skilled operator to achieve acceptable web tensions. Some prior printing presses have controlled the web tension. These presses may have compromised print product quality.
European Patent Document No. EP 0 933 201 A1 describes a method for controlling the nip roller driver in a web printing press based on a load torque adjusted according to load characteristic curve. hi this way, the driver purportedly produces a desired rotational speed of the nip roller and at the same time a desired web tension.
An object of the present invention is to provide a web printing press control scheme which changes according to the phase of printing press operation.
The present invention provides a method for dynamically controlling a driver of a nip roller in a web printing press, the method comprising: controlling a speed of the driver in a tension-control mode during a first phase of printing press operation, the controlling of the speed of the driver in the tension-control mode being based on a tension in the web upstream of the nip roller so as to maintain the tension at a first desired tension value; and controlling the speed of the driver in a velocity-control mode during a second phase of printing press operation, the controlling of the speed of the driver in the velocity-control mode being based on a driver velocity ratio.
According to the present invention, the control mode of the nip roller driver is thus adapted to the particular operating phase of the printing press.
The tension maintained according to the present invention may be a measured or estimated tension in the upstream web. The desired tension value may be derived from an operator input or from a previously determined set of tension set points which are a function of a type of paper of the web and/or an operating condition of the web printing press.
The first phase of printing press operation may include acceleration of the nip roller driver to a steady-state speed during a start-up of the printing press. Tension-control of the driver speed is desirable during start-up and acceleration to make-ready speed since printing has not yet commenced and print quality is therefore not an issue.
The second phase of printing press operation may include a printing operation of the printing press. Once printing has started, velocity control of the nip roller driver is implemented to maintain print product quality.
The driver velocity ratio used in the velocity-control mode is a ratio of the speed of the driver needed to produce a given desired web tension value to the value of the command, or nominal, velocity of the web printing press.
The driver velocity ratio may be determined during a transition phase of printing press operation when the driver is at the steady-state speed.
The method according to the present invention may further comprise: controlling the torque of the driver during a webbing-up phase of printing press operation at a torque value a given amount above a breakaway torque and below a web breaking torque; and controlling the speed of the driver during the webbing-up phase below a maximum velocity limit so as to prevent a driver overspeed condition when the tension in the web is low or zero.
During the webbing-up phase, the driver torque may thus be set to provide measurable tension in the upstream web span, but low enough to avoid web breaking. Since there may be no web yet present at the beginning of the webbing-up phase, an upper driver velocity limit is imposed to prevent overspeed of the driver when there is no web tension to match the driver torque. The press may remain in the webbing-up mode until measurable web tension had been developed.
Furthermore, according to the present invention, control of the driver speed may be switched from the velocity-control mode to the tension-control mode. This may be desirable when the web tension moves, or is likely to move, outside of an acceptable web tension limit band, or periodically. Times when the web tension is likely to move outside of an acceptable tension limit band include press blanket wash cycles and web splicing cycles. Also, the web tension may move out of an acceptable tension limit band due to temperature, humidity and paper changes. Additionally, control of the driver speed may be switched from the velocity-control mode to the tension-control mode in response to an operator input, or simply periodically.
Once the driver control has been switched back to velocity-control mode, a revised velocity ratio may be determined during a time when the driver is at a steady-state speed. Then driver control may be switched back to velocity-control mode using the new velocity ratio.
Furthermore, to reduce the likelihood of a web break, driver control may be switched to tension-control mode in the event of an emergency stop of the printing press.
The present invention also provides an apparatus for dynamically controlling a driver of a nip roller in a web printing press, the apparatus comprising a tension control device for modifying a speed of the driver based on a tension in the web upstream of the nip roller in a tension-control mode during a first phase of printing press operation so as to maintain the tension at a first desired tension value; and a speed control device for controlling the speed of the driver in a velocity-control mode during a second phase of printing press operation, the controlling of the speed of the driver in the velocity-control mode being based on a driver velocity ratio.

Method and apparatus for dynamically controlling a web printing press


A scanning optical apparatus includes a light source unit, a deflector for deflectively scanning a light beam from the light source unit, an optical box in which the deflector is accommodated and an optical system for focusing the light beam deflectively scanned by the deflector on a predetermined surface. The optical system is supported by the optical box and having upside-down prevention mechanism which interferes with a predetermined portion of the optical box to prevent upside-down mounting of the optical system.

1. Field of the Invention
The present invention relates to a scanning optical apparatus used for an image forming apparatus such as a laser printer or a laser facsimile apparatus.
2. Related Background Art
As shown in FIG. 1, a scanning optical apparatus used for an image forming apparatus such as a laser printer or a laser facsimile apparatus generally comprises a light source unit E which incorporates a semiconductor laser, a collimator lens, and the like, a rotary polygonal mirror R for deflectively scanning a laser beam L.sub.0, i.e., a collimated beam emitted from the light source unit E, and an imaging lens system F for forming the deflectively scanned laser beam into an image on a photosensitive material N serving as a recording medium on the surface of a rotary drum. The imaging lens system F has a spherical lens F.sub.1 and a toric lens F.sub.2. The rotary polygonal mirror R, the spherical lens F.sub.1, and the toric lens F.sub.2 are accommodated in an optical box H. The light source unit E is mounted on the side wall of the optical box H.
The upper opening of the optical box H is closed by a lid (not shown) after all necessary parts are mounted in the optical box H. A window M for extracting the laser beam defected and scanned by the rotary polygonal mirror R toward the external rotary drum is formed in the bottom wall of the optical box H.
The laser beam L.sub.0 emitted from the semiconductor laser of the light source unit E is collimated by the collimator lens in the light source unit E, linearly focused on the reflecting surface of the rotary polygonal mirror R through a cylindrical lens C, reflected downward by a deflecting mirror G through the imaging lens system F, and extracted from the window M of the optical box H toward the rotary drum. With this arrangement, the laser beam formed into an image on the photosensitive material N on the rotary drum is formed into an electrostatic latent image with the main scanning operation by the rotary polygonal mirror R and the sub-scanning operation by rotation of the rotary drum.
The imaging lens system F has a so-called f-.theta. function of setting the constant scanning speed of a point image formed on the photosensitive material N in the above-described manner. The spherical lens F.sub.1 and the toric lens F.sub.2 are strictly positioned with respect to the optical path of the laser beam (scanning light beam) scanned by the rotary polygonal mirror R, and then fixed in the optical box H by a known technique such as bonding.
In recent years, inexpensive plastic lenses have been developed as the toric lens F.sub.2. A plastic toric lens has an advantage in simplifying the assembly process of the scanning optical apparatus because a positioning projection D is integrally formed at a predetermined position of the toric lens and engaged with positioning pins P.sub.1 and P.sub.2 standing on the bottom wall of the optical box H, resulting in facilitation of positioning the scanning direction.
According to the above prior art, however, the toric lens has an aspherical shape asymmetrical about its optical axis, i.e., the center of the longitudinal direction, though this asymmetry cannot be easily recognized from the outer appearance. Therefore, the toric lens is often erroneously mounted upside down in the optical box.
Depending on the type of the scanning optical apparatus, the scanning direction of the scanning light beam is reversed to that described above, so that it is sometimes required to mount a toric lens having the f-.theta. function upside down. When bearing surfaces (reference surfaces) for mounting the lens to the bottom wall of the optical box are formed on both the upper and lower end faces of the toric lens, the toric lens can also be applied to a scanning optical apparatus of another type. For this reason, the application range (application purpose) of the part can be made wide to largely reduce the unit costs of parts. However, when similar bearing surfaces are formed on both the upper and lower end faces of the toric lens, upside-down mounting further increases.


A new and distinct Petunia plant named ‘USTUN69002’, characterized by its compact, outwardly spreading and mounding plant habit; freely branching habit; vigorous growth habit; early and freely flowering habit; lavender pink-colored flowers with yellow green-colored centers; and good garden performance.

The present invention relates to a new and distinct cultivar of Petunia plant, botanically known as Petunia×hybrida and hereinafter referred to by the name 'USTUN69002'.
The new Petunia plant is a product of a planned breeding program conducted by the Inventor in Higashiomi, Shiga, Japan and Bonsall, Calif. The objective of the breeding program is to create new freely-branching and uniformly mounding Petunia plants with early and freely flowering habit, unique attractive flowers and good garden performance.
The new Petunia plant originated from a cross-pollination made by the Inventor on May 20, 2012 in Higashiomi, Shiga, Japan of Petunia×hybrida 'Bluetta Pink Morn', not patented, as the female, or seed, parent with Petunia×hybrida 'Little Holiday Pink Morn', not patented, as the male, or pollen, parent. The new Petunia plant was discovered and selected by the Inventor as a single flowering plant within the progeny of the stated cross-pollination in a controlled greenhouse environment in Bonsall, Calif. on Jun. 5, 2013.
Asexual reproduction of the new Petunia plant by vegetative terminal cuttings in a controlled greenhouse environment in Bonsall, Calif. since Jun. 6, 2013 has shown that the unique features of this new Petunia plant are stable and reproduced true to type in successive generations.


A voltage multiplier for a power supply unit of an electronic insect-killing device includes a circuit board received in the electronic insect-killing device. A central line of the circuit board is formed as a score therein to allow the circuit board to be folded therealong. A plurality of copper foil circuits are respectively disposed on two sides of the central line of the circuit board. A voltage multiplier formed of electric elements is connected to the plurality of copper foil circuits. In this way, the power supply unit including the voltage multiplier has a sufficiently small volume to be received in a handle of the electronic insect-killing device and assures secure wiring.

1. Field of the Invention
The present invention relates to a power supply unit of an electronic insect-killing device, and more particularly to a voltage multiplier for the supply unit which is foldable and assures secure wiring of the electronic insect-killing device.
2. Description of Related Art
Conventional insect-killing devices include various kinds, such as an electronic fly-swatter, a fly-adhering paper, an electronic insect-killing light, and so on. A principle of the electronic fly-swatter is to kill the flies by electrified wire netting. A conventional power supply unit of a fly-swatter generally has dry batteries and a booster to assure the voltage is high enough to kill the insects. A circuit principle of the electrified wire netting is that a voltage output by the battery is multiplied by a voltage multiplier having an output terminal thereof connected to a metal grid. A circuit diagram of the voltage multiplier is shown in FIG. 5. It can be seen from the figure that a voltage circuit of the voltage multiplier is composed of a plurality of diodes and capacitors. To receive the plurality of diodes and capacitors in a handle of the fly-swatter, the wiring manner involved is to directly weld pins of each of the diodes and capacitors. This wiring manner has an obvious disadvantage that it results in unstable wiring and thus may cause defective contacts, or even a short circuit. Additionally, this wiring manner takes a long time during manufacturing so that it is not adapted for mass production.
The present invention provides an improved voltage multiplier for a power supply unit of an electronic insect-killing device to mitigate and/or obviate the aforementioned problems.

Voltage multiplier for a power supply unit of an electronic insect-killer device


Activating supports are prepared by (a) combining (i) fluorine-containing compounds having a reactive group and (ii) an organometallic compound, (b) contacting a porous mineral oxide support material with the mixture from step (a), (c) heating the functionalized support from step (b) under an inert gas and then under an atmosphere comprising oxygen, and (d) recovering the activating support. The fluorine-containing compounds may have the formula R(Fn)-X wherein R is hydrocarbyl, substituted hydrocarbyl, heterohydrocarbyl or substituted heterohydrocarbyl with up to 20 non-hydrogen atoms, n is 1-41, X is OH, SH or NR′2, R′ is hydrogen or hydrocarbyl. The activating supports are useful in combination with transition metal catalysts for polymerization of olefins, e.g., with metallocene complexes. Preparation of the activating supports is easier and more economic than prior methods and provides for supported polymerization catalyst systems having excellent activities. Polymers produced using the activating supports exhibit improved rheology properties.

In recent years there have been many advances in the production of polyolefin homopolymers and copolymers due to the introduction of single site catalysts such as metallocene catalysts. Metallo catalysts and are usually described as catalysts which are single site in nature.
The above single site catalyst systems such as metallocene complexes may be used for the polymerization of olefins in solution, slurry or gas phase. When used in the slurry or gas phase the metallocene complex and/or the activator are suitably supported. Typical supports include inorganic oxides eg. silica or polymeric supports may alternatively be used.
Examples of the preparation of supported metallocene catalysts for the polymerization of olefins may be found in WO 94/26793, WO 95/07939, WO 96/00245, WO 96/04318, WO 97/02297 and EP 642536.
The above supported polymerization c cene catalysts offer the advantage of generally a higher activity than traditional Ziegler catalyst systems may in some cases lead to certain disadvantages such as cost, instabilities as well as poor morphology of the resultant polymers as well as problems with gels and the like when subsequently transformed into films and other articles.
In recent years attempts have been made to replace the activator or cocatalyst components of the supported polymerization catalyst systems by use of activating supports.
EP 906920 describes fluorine-containing activator solid supports for metallocenes wherein the surface of the support has been modified by aluminium (or magnesium) Lewis-acid sites of formula Al—F or AlF2. The supports are prepared by a method comprising reaction of the surface —OH radicals with a functionalisation agent followed by fluorination.
WO 2005/075525 describes methods for preparing activating supports for metallocenes wherein the supports are treated with fluorinated functionalizing agents followed by heating and treatment with oxygen.
WO 2007/014889 describes similar supports prepared by functionalizing the support with an alkylating agent followed by heating under an inert gas then under oxygen and finally treatment with a fluorinating agent.
WO 2007/12465 describes fluorinated transition metal catalysts based on supports comprising bonding sequences selected from Si—O—Al—F, F—Si—O—Al, F—Si—O—Al—F.
WO 2007/131856 describes mono- or di-fluorinated metallocene catalyst components supported on fluorinated activating supports.
WO 2010/037808 describes activating supports based on perfluorinated boronic acids and aluminium alkyls and their use in the activation of metallocene complexes.
WO 2007/005676 describes activator compositions based on metal oxide supports having surface hydrogen-bonded hydroxyl groups and organoaluminium compounds having bulky functional ligands resulting in aluminate anions covalently bonded to the metal oxide via two chelating oxygen atoms.
US 2008/0319148 describes the use of halogenated alcohols or amines in the preparation of modified supports suitable for use in the polymerization of olefins.


A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.

In recent years, strain relaxed buffer (SRB) is grown on a bulk semiconductor substrate such as a silicon substrate, and used as a virtual substrates (VS) to epitaxially grow another semiconductor material of a different lattice constant than the bulk substrate. The SRB, however, suffers from defect issue, and the thickness of the epitaxially grown semiconductor material is limited by its theoretical critical thickness.

This patent is subject to a terminal disclaimer.

Semiconductor device and method for manufacturing the same

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.


The present invention significantly reduces the number of complex computations that must be performed in computing the discrete Fourier transform (DFT) and inverse DFT (IDFT) operations. In particular, the DFT and IDFT operations are computed using the same computing device. The computation operations are substantially identical for both operations with the exception that for the IDFT operation, the data are complex conjugated before and after processing. Using the same computing device/operations, both DFT and IDFT computations are optimized for maximum efficiency. A common transform process is selectively connected to first and second data processing paths. A DFT operation is performed on an N-point sequence on the first data processing path, and an IDFT operation is performed on an N-point sequence on the second data processing path using the same N-point fast Fourier transform (FFT).

Orthogonal transforms and transform properties are extraordinarily useful in solving new technological problems. Such transforms permit analysis of a signal given some knowledge of its constituent parts. For example, the Fourier transform has long been a powerful and principle analysis tool in diverse fields, such as linear systems, probabililty theory, boundary-valued problems, communications theory, signal processing, etc. The discrete Fourier transform (DFT) is the counterpart of the Fourier transform in the screte time domain. In general, the DFT may be defined as follows: ##EQU1## and the inverse DFT (IDFT) is expressed as: ##EQU2## where W.sub.N.sup.k =e.sup.-j2.pi.k/N. In equations (1) and (2), x(n) is the sample value in the time domain, and X(k) is the sample value in the frequency domain.
Direct computation of the DFT and the IDFT requires N.sup.2 complex multiplications and N(N-1) complex additions. Such data processing overhead is quite onerous. One helpful and important tool in modem digital signal processing applications is therefore the fast Fourier transform (FFT). The FFT is an efficient algorithm for computing the DFT by mapping an N-point complex sequence to its corresponding N-point complex frequency spectrum.
Although most FFT algorithms are designed to compute the DFT of a complex sequence, in many applications, the sequence to be transformed is real valued. Nevertheless, even in these real valued applications, the FFT algorithm performs multiple complex multiplications and additions. Even with the increased efficiency and speed provided using the FFT algorithm, there is an ongoing need to reduce the number of computations, and in particular, the number of complex multiplications that must be performed in order to more efficiently compute the DFT and the IDFT.
The present invention achieves a significant reduction in the number of complex computations that must be performed in computing the DFT and IDFT. In particular, the DFT and IDFT operations are computed using the same computing device with the computation operations being substantially identical for both operations with the exception that for the IDFT operation, the data are complex conjugated before and after processing. Using the same computing device/operations, both DFT and IDFT computations are optimized for maximum efficiency. Indeed, efficiency improvement is on the order of 50 percent compared with more traditional, brute force FFT/IFFT computations.
A data processing device employing the present invention includes first and second data processing paths. A transform process (in particular a DFT processor) is selectively connected to the first and second data processing paths, and selectively performs a DFT operation on an N-point complex sequence in the time domain present on the first data processing path and an IDFT on an N-point complex sequence in the frequency domain present on the second data processing path using the same N-point fast Fourier transform. For purposes of this invention, N is a positive integer, and the term point is the number of symbols in a sequence. Each such sequence symbol is considered a complex number whether or not the symbol includes both real and imaginary parts. In the frequency domain, a symbol may be viewed as a spectral component.
The first data processing path corresponds to the DFT operation, and the second data processing path corresponds to the IDFT operation. In a particularly advantageous application of the invention, a 2N-point, real sequence in the time domain is translated into the frequency domain via the first data processing path. The 2N-point real sequence is compressed into an N-point complex sequence before routing to the transform processor. The N-point complex data are transformed using an N-point DFT operation executed by the transform processor, and the transform processor output is then translated into an N-point spectral sequence in the frequency domain.
Along the second data processing path, an N-point, complex spectral sequence, instead of being extended to a 2N-point Hermite symmetric sequence as required to obtain a real sequence in the time domain, is processed to generate an N-point spectral input sequence, which when processed by the transform processor, results in an N-point sequence in the time domain. The N-point output sequence is complex conjugated, and then converted from an N-point complex sequence into a 2N-point real sequence.
In one advantagous application of the present invention to data communications, the first data processing path corresponds to a portion of a receiver, and the second data processing path corresponds to a portion of a transmitter. The receiver and transmitter may function for example as a modem. One preferred modem type is a discrete, multi-tone (DMT) modern. The transmit data processing path modulates a symbol sequence onto multiple carriers, and the receive data processing demodulates the multiple carriers and reconstructs the transmitted symbol sequence.
Because both transmitter and receiver data processing paths use the same DFT processor to perform frequency-to-time and time-to-frequency transformations, e.g., DMT modulation and demodulation, a more economic transceiver may be achieved in terms of efficiency, size, expense, complexity, and power dissipation. In the DMT modem example, the same, N-point Fourier transform performs IDFT modulation of a symbol sequence having in effect twice that number of points in the sequence as well as DFT demodulation of received signals also having 2N-points. It is in this fashion that the present invention is able to reduce the computational complexity of the transformation operations by approximately 50 percent, i.e., from 2Nlog.sub.2 2N complex multiplications to Nlog.sub.2 2N complex multiplications.
Thus while the primary object of the present invention is to provide a particulary efficient method and apparatus for DFT/IDFT computations, these and other objects and advances of the present invention will become apparent to those skilled in the art as described below in further detail, and in conjunction with the figures and the appended claims.

Method and apparatus for efficient computation of discrete fourier transform (DFT) and inverse discrete fourier transform


A power transmission set for tractioned axles of vehicles. The power transmission set includes at least one coupling/uncoupling device, a selector unit, a primary shaft, and a secondary shaft. The shafts are interconnected by the selector unit to select and control a type of motor propulsion applied to a tread axle of a vehicle. The shafts cooperatively with the coupling/uncoupling device are configured to provide a configuration in which only a combustion engine is responsible for propulsion; in which only an electric motor provides propulsion; in which both the combustion engine and the electric motor work together to generate torque; or in which the tread axle is uncoupled from the combustion engine and the electric motor and the combustion engine provides power to the electric motor to generate electricity. A vehicle for the transport of cargo and passengers including the power transmission set.

According to the state of the art, and as generally known by persons skilled in the art, there are already several models of electric and hybrid vehicles, which comprise a combined power transmission set, which is powered by an electric motor, by the combustion engine and also by activating both engines, thus enabling a vehicle to be obtained with fully electric propulsion, totally combustion, or hybrid in which the two engines work simultaneously.
Although it is a relatively new technology, it is noted that this type of combined power transmission set has been occupying increasing ground on the market, and certainly, as can be seen in the state of the art, in the near future, it will be protagonist for the various advantages it presents when compared to technologies that use only combustion engines, for example, fuel consumption and emission of pollutants into the environment.
In this sense, and according to the state of the art, some types of hybrid systems applied in vehicles are known, for example: (i) the serial hybrid, in which the entire traction of the automobile is always originated by the electric motor, and the combustion engine used only generates electric energy; (ii) the parallel hybrid, where the two engines, both electric and combustion, are used to generate power, but the electric only assists the engine to combustion at times when it requires more torque, considering that in these moments there is an increase in fuel consumption; and (iii) the combined hybrid, where the two engines can pull the vehicle, whatever the combination, its composition is similar to a serial hybrid, but the mechanical connection of the wheels is obtained through the two engines.
Additionally, the technology of vehicles with hybrid motorization systems can be classified into two other categories, rechargeable hybrids formed by vehicles equipped with batteries capable of being charged through connection with conventional electrical power outlets. Despite revealing a relatively low autonomy, along the route the electrical system operates alone, without the need to trigger the propellant to combustion. The other category is extended hybrid vehicles, which is similar to rechargeable, but activates the combustion engine to charge the battery, the operation of the combustion engine occurs on a constant basis to increase the autonomy of the vehicle.
As persons skilled in the art will likely appreciate, one of the main drawbacks of these technologies of electric and hybrid motorization is precisely related to the costs of application and implementation. More particularly, according to the technologies known and available in the state of the art the vehicle with the hybrid system are expensive because they require specific components, such as batteries, electric motors, gearboxes, complex and hard to build and assemble power transmission sets, among other numerous peripheral components responsible for providing the assembly and operation of these vehicles.
Furthermore, it is worth mentioning that in the case of cargo or passenger transport vehicles, the effort required by the engines and traction mechanisms are subjected to even greater strain than those usually observed in passenger and small vehicles. In these cases, it is noted that, while seeking solutions for the applicability of technologies with hybrid engines, the technologies currently available cannot meet the power need for these vehicles and, when possible, technologies become expensive and economically unviable.
Therefore, although the solutions known in the state of the art meet, in some way, some traction requirements, it is observed that the hybrid motorization systems present in the state of the art are formed by relatively complex arrangements and that require additional components and peripherals, substantially increasing the system and making it impractical from the economic point of view.
Thus, considering the above, it is possible to affirm that hybrid motorization systems, applied in cargo or passenger vehicles, need simple and effective solutions, but mainly capable of reducing the costs involved with the manufacture and assembly of vehicles. It is, therefore, these objectives that are intended to be achieved with the development of the present invention.

Power transmission unit for shafts and vehicle for carrying passengers and goods


An appliance includes a user interface assembly. The user interface assembly includes a plurality of indicator lights mounted on a printed circuit board. An opaque material is disposed between adjacent indicator lights of the plurality of indicator lights. The opaque material is positioned and configured such that the opaque material reduces illumination of the printed circuit board by at least one indicator light of the plurality of indicator lights.

Appliances generally include a control panel having a plurality of buttons, keys, or other input devices. Utilizing the control panel, an appliance user can input control commands to the appliance and operate the appliance. Certain control panels include a plurality of indicator lights mounted on a printed circuit board such that the indicator lights provide visual information about the status of the appliance, such as selected cycles or options input by the user.
In some appliances, illuminating one indicator light may also unintentionally illuminate the printed circuit board, or a portion of the printed circuit board, such as a surface of the printed circuit board, proximate to the illuminated indicator light. Such unintentional illumination may be aesthetically displeasing and/or may create confusing or conflicting visual information for the user.
Accordingly, user interface assemblies that include features for preventing unintended illumination of the printed circuit board therein would be useful.

Light blocking features for indicator lights in an appliance


A method of constructing or reconstituting a shaft and paddle assembly for mixers and processors wherein radially aligned paddles on parallel shafts revolving at the same speed in the same direction of rotation both co-wipe and completely wipe the interior of the barrel of the mixer or processor which has a mixer chamber comprising interconnecting cylindrical bores. The co-wiping paddles are formed with paddle bores of a configuration comprising alternating lobular projections and root recesses, and arcuate corner portions on the lobular projections and root recesses. The arcuate corner portions of the projections are tangential to the arcuate corner portions of the root recesses. The shafts are formed with intermeshing matching projections and root recesses.

The present invention has been developed for use in twin screw mixing-compounding machines of the type used in the plastics industry, for example, and illustrated in the present assignee's prior U.S. Pat. Nos. 3,195,868 and 4,82,6,323. The larger machines of this type utilize preferably hydraulic motor-driven shafts with radially mating co-wiping, individual paddles, or worm sections thereon, both of which, hereinafter, are to be included within the term "paddle", as used hereinafter. In machines of this character, the shafts which mount the paddles must be rotated at the same speed, and in the same direction of rotation, in order for the paddles to completely co-wipe one another, and, at the same time, completely wipe the interior of the barrel bore in which they are operative. Whether the paddle employed is of the single or multi-lobe type, the geometry of the surface of one of the paddle components must be generated by the mating paddle component for co-wiping to occur, and these geometric forms are a direct function of barrel bore diameter to shaft center-to-center distance. Normally, to increase the power supplied to the paddles of such machines for mixing purposes and increased output, it is necessary to increase the dimensions of both the paddles and the shafts which drive them, to carry the increased loads at acceptable stress levels. However, to increase shaft diameter for a machine having a given size barrel, it is necessary to alter the bore to center-to-center distance ratio of the twin screw-paddle assembly, which adds to its width. The paddle component wall thickness, accordingly, increases in relationship to the increased shaft diameter and, with thicker paddle elements, the open volume of the machine for the same bore diameter is significantly decreased. Thus, present day machines which are to produce an increased rate of processing product cannot tolerate the power increases which are necessary for processing the materials.
Typically, today, involute gear teeth splines are used to transfer the power from the shafts to the paddles, as disclosed in prior U.S. Pat. No. 4,591,487, but various keys, and hexagonal shaft configurations, have also been proposed. While all are not considered germane to the field of the present invention, applicants are aware of the following prior patents, which they incorporate herein by reference:
______________________________________ 2,668,756 Carney 2,777,353 Willis 3,584,667 Reiland 4,073,013 Blach 4,236,833 Blach 4,269,246 Larson et al 4,591,487 Fritsch 5,171,117 Seidl ______________________________________

Methods of constructing paddle and shaft assemblies for twin screw mixer and/or processors and the resulting apparatus


A rotary fluid machine suitable for transferring energy between a fluid and a rotor assembly is disclosed. The rotor assembly contains a shaft carrying one or more impellers which are located between axially spaced radial bearings in a beam-type arrangement. The rotary fluid machine is of the beam type--i.e. it has one end of the shaft extending beyond one end wall of the housing and one end of the shaft terminating within the housing. Two passages are formed in the housing to allow fluid to flow in and out of the machine. One passage is formed in the housing parallel to and coaxial with the rotational axis of the rotor assembly. Fluid moving between the passage parallel to and coaxial with the rotational axis does not have to be redirected thus reducing fluid turbulence and improving machine efficiency.

Rotary fluid machines are used in a wide variety of applications to transfer energy between fluid passing through the machine and a rotating mechanical assembly. In general, a rotary fluid machine has a housing with a fluid duct extending through the housing and one or more rotor assemblies which rotate within the fluid duct. In operation, the rotation of the rotor assemblies cause a difference in fluid pressure between the inlet and outlet of the fluid duct.
Rotary fluid machines are generally of either a beam-type configuration or of an overhung-type arrangement. U.S. Pat. No. 3,558,238 shows a typical rotary fluid machine of the overhung-type configuration. U.S. Pat. No. 3,758,226 shows a typical rotary fluid machine of the beam-type configuration.
In a typical beam-type machine, a shaft which forms part of the rotating assembly extends beyond both ends of the housing. Radial bearing assemblies are provided at each end of the housing to support the shaft in the housing while allowing the shaft to freely rotate about a rotational axis which extends along the length of the shaft and is generally parallel to the center of the shaft. A shaft seal assembly is located in either and of the housing at the point where the shaft passes through the housing. The shaft seal assembly restricts the passage of fluid between the inside and outside of the housing at the point where the shaft passes through the housing. Attached to and rotatable with the shaft are one or more impellers through which fluid passes. Rotary fluid machines of a beam-type configuration often have several impellers on the shaft. Several impellers are commonly used when a large difference between inlet fluid pressure and discharge fluid pressure exists. Typical impellers are designed such that fluid enters the impeller through an annular passage generally at the inner diameter of the impeller which is coaxial with the axis of rotation of the shaft. To provide a means for moving fluid in and out of the housing, inlet and discharge fluid passages are formed in the housing. Often these passages formed in the housing are positioned such that fluid entering the machine through the passage enters the fluid duct perpendicular to the axis of rotation of the shaft. After entering the fluid duct, the fluid must be aligned with the annular passage at the inlet of the impeller. The redirection of the fluid causes turbulence within the fluid stream which results in a pressure drop and a corresponding loss in machine efficiency.
A rotary fluid machine of the overhung configuration has a shaft forming part of the rotating assembly which extends beyond one end of the housing. Radial bearing assemblies are located in the end of the housing which the shaft passes through. The radial bearing assemblies support the shaft in the housing while allowing the shaft to freely rotate about the axis of rotation. The shaft is, therefore, supported in cantilever fashion. Attached to the section of shaft within the fluid duct are one or more impellers of similar design to the impellers of a beam-type machine. The impellers are typically of relatively large size and weight. When an impeller is mounted on the shaft being supported in cantilever fashion, high radial forces must be resisted by the bearing assemblies. Large bearing forces require large capacity radial bearings which are often undesirable. The problem of large radial bearing forces can be especially acute when more than one impeller is placed on the shaft to form a multistage rotary fluid machine. Overhung rotary fluid machines are therefore often limited to one or two impellers.
A fluid passage can be formed in the end of the housing the shaft does not extend through, such that fluid moving through the passage enters the machine parallel to and coaxial with the axis of rotation of the shaft, and therefore, does not have to be redirected into the impellers. The turbulence and associated loss of machine efficiency due to the redirection of the fluid is substantially avoided.
It is, therefore, apparent that a rotary fluid machine with a fluid passage coaxial with the shaft axis of rotation, and with the impellers located between the radial bearing assemblies, would be a useful addition to the art.


A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

In a structure of a fin-type FET (Field Effect Transistor) (hereinafter referred to as "FinFET"), it is possible to provide several channel plane directions by setting a crystal plane direction and a channel direction of a substrate. Furthermore, it is known that an optimal channel direction with respect to a crystal axis to improve carrier mobility is different between an n-type FinFET and a p-type FinFET. For example, in general, both of the n-type and p-type FinFETs are often configured so that a plane direction of a fin side surface is (100) and an axial direction of a channel region formed on the fin side surface is <110>, however, it has been known that the carrier mobility is improved by configuring the plane direction of the fin side surface to be (100) and the axial direction of the channel region formed on the fin side surface to be <100> for the n-type FinFET while configuring the plane direction of the fin side surface to be (110) and the axial direction of the channel region formed on the fin side surface to be <110> for the p-type FinFET.
A technique to form one conductivity type of FinFET inclined at 45° with respect to another conductivity type of FinFET around a height direction so as to make plane directions and channel directions of fin side surfaces of both n-type and p-type FinFETs to be directions which improve the carrier mobility as described above when mounting the n-type and p-type FinFETs together on a Si substrate of which plane direction of one principal surface is (100), is known. This technique, for example, is disclosed in a non-patent literary document of B. Doris et al., Symp. on VLSI Tech. Dig. of Tech. Papers, pp. 86-87, 2004.
Meanwhile, a technique, to give different crystal directions to an n-type and p-type device regions on the same substrate, in which semiconductor substrates having different plane directions are laminated, and then, a predetermined region of the upper substrate recrystallized so as to reflect a plane direction of the lower substrate after amorphizing the predetermined region of the upper substrate, is known. This technique, for example, is disclosed in U.S. Pat. No. 7,023,055.

Semiconductor wafer, semiconductor device and method of fabricating the same