A manufacturing method for a liquid crystal display apparatus according to an embodiment of the present invention includes a step (A) of preparing a first substrate including a pixel electrode and a first photoalignment film that has not been subjected to an alignment treatment, and a step (B) of exposing a region of the first photoalignment film which is to serve as a first alignment region through a plurality of first photomasks, while transporting the prepared first substrate in a predetermined transport direction, the plurality of first photomasks including two or more first photomasks arranged in a second direction intersecting the transport direction. Each first photomask includes a plurality of pairs of a light-transmitting portion and a light-blocking portion. Each first photomask is designed so that in the step (B), on a side closer to one end of the first photomask, a boundary between the light-transmitting portion and the light-blocking portion is offset from a domain boundary toward the one end, and on a side closer to the other end of the first photomask, the boundary between the light-transmitting portion and the light-blocking portion is offset from the domain boundary toward the other end.

Liquid crystal display apparatuses, the display characteristics of which have been improved, are being used in more and more applications such as a television set. The viewing angle characteristics of liquid crystal display apparatuses have been improved, but further improvements are desired. In particular, there is a strong demand for improvement of the viewing angle characteristics of a liquid crystal display apparatus employing a vertical alignment type liquid crystal layer (also called a "vertical alignment (VA) mode liquid crystal display apparatus").
At present, in VA mode liquid crystal display apparatuses used in large-size display apparatuses such as a television, the alignment division structure (multi-domain structure), in which a plurality of liquid crystal domains are formed in a pixel, is employed in order to improve the viewing angle characteristics. As a representative technique for forming the alignment division structure, the multi-domain vertical alignment (MVA) mode is known.
In the MVA mode, an alignment control structure is provided on the side facing the vertical alignment type liquid crystal layer of each of a pair of substrates facing each other with the vertical alignment type liquid crystal layer interposed therebetween, so that a plurality of liquid crystal domains (typically, four alignment directions) having different alignment directions (tilt directions) are formed in each pixel. As the alignment control structure, slits (openings) that are provided in electrodes or ribs (protrusion structures) are used. The alignment control structure exerts alignment control force from either side of the liquid crystal layer.
However, if slits or ribs are used, the linear shape of the slits or ribs leads to non-uniform alignment control force applied to liquid crystal molecules in the pixel, unlike the conventional twisted nematic (TN) mode, etc., in which pretilt directions are defined by alignment films. Therefore, a distribution of response speed occurs in the pixel.
In order to circumvent this problem, even in the VA mode liquid crystal display apparatus, the alignment division structure is preferably formed by defining pretilt directions using alignment films. Patent Document No. 1 discloses a liquid crystal display apparatus in which the alignment division structure is formed in such a manner.
In the liquid crystal display apparatus disclosed in Patent Document No. 1, a four-domain structure is formed by defining pretilt directions using alignment films. Specifically, when a voltage is applied to the liquid crystal layer, four liquid crystal domains are formed in a pixel. Such a four-domain structure is also simply called a 4D structure.
In addition, in the liquid crystal display apparatus disclosed in Patent Document No. 1, a pretilt direction defined by one of the pair of alignment films facing each other with the liquid crystal layer interposed therebetween is about 90° different from a pretilt direction defined by the other alignment film. Therefore, when a voltage is applied, liquid crystal molecules take twisted orientations. Thus, the VA mode in which twisted orientations of liquid crystal molecules are produced by a pair of vertical alignment films arranged so as to define orthogonal pretilt directions (alignment treatment directions) is also called a vertical alignment twisted nematic (or denoted as vertically aligned twisted nematic) (VATN) mode or a reverse twisted nematic (RTN) mode. As described above, in the liquid crystal display apparatus of Patent Document No. 1, the 4D structure is formed, and therefore, the display mode of the liquid crystal display apparatus of Patent Document No. 1 is also called a 4D-RTN mode.
As a specific technique of defining pretilt directions of liquid crystal molecules using alignment films, the photoalignment treatment is promising as described in Patent Document No. 2. The photoalignment treatment can be performed in a contactless manner, and therefore, unlike a rubbing treatment, there is no static electricity caused by friction, leading to an improvement in yield.
The photoalignment treatment is performed using a photomask and an exposure device. The size of the photomask has in recent years been increased with an increase in size of a substrate. Photomasks cost high, and therefore, an increase in size of a photomask leads to an increase in manufacturing cost. Under these circumstances, Patent Document No. 2 proposes an exposure device which performs scanning exposure using an array of small-size photomasks.

Method for manufacturing liquid crystal display device and photomask


[Problem to be Solved] In a plasma processing apparatus for executing a process using plasma, promoting the sharing of an apparatus in executing a plurality of different processes and plasma states amongst apparatuses in executing same processes in a plurality of apparatuses are provided.

In manufacturing processes of a semiconductor device, conventionally, dry etching has been performed on a substrate such as a semiconductor wafer (hereinafter, referred to as a wafer) for, e.g., separating capacitors or elements, or forming contact holes. A single sheet parallel plate type plasma processing apparatus is known as an apparatus performing such a process (see, e.g., reference patents 1 and 2).
The above-mentioned apparatus will be described briefly with reference to FIG. 28. The plasma apparatus includes an upper electrode 11 serving also as a gas shower head and a lower electrode 12 serving also as a mounting table at an upper side and lower side of an airtight vessel 1, respectively. Further, a silicon ring 13 at an inner side and a quartz ring 14 at an outer side are installed to surround the wafer W on the mounting table 12. The wafer on the mounting table (the lower electrode) is etched by applying a bias voltage to the lower electrode 12 from a high frequency power supply 16 and performing vacuum exhaust through a gas exhaust port 17 to keep a predetermined pressure, while, at the same time, a high frequency voltage is applied between the upper and lower electrodes 11 and 12 by a high frequency power supply 15; and a processing gas from the gas shower head (the upper electrode) 11 is converted into plasma.
Functions of the silicon ring 13 and the quartz ring 14 will hereinafter be described. The processing gas arriving at the proximity of the surface of the wafer W is diffused toward the periphery of the wafer W and exhausted from outside the periphery toward the bottom. Therefore, a gas flow of the processing gas at the peripheral portion (around the periphery) of the wafer W is different from that at the central portion of the wafer W, disturbing a balance of a predetermined composition in the processing gas at the peripheral portion of the wafer W. Further, the component of impedance, conductance or the like between the plasma and the lower electrode at an area on which the wafer W is disposed differs from those at outside the area, respectively. As a result, the plasma state above a nearby area of the wafer's periphery is different from that above inside of the wafer's periphery.
On the other hand, high in-surface uniformity of an etching rate needs to be achieved because of a strong need to form devices even in the area close to the periphery of wafer W in order to increase utilization. Accordingly, a ring member (referred to as a focus ring or the like) formed of a conductor, semiconductor or dielectric substance is disposed outside the wafer W to adjust the plasma density above the peripheral portion of the wafer W. Specifically, a focus ring material is selected; and width, height or the like of the ring is adjusted according to the material of a to-be-etched film, the magnitude of a supply power or the like when installing a focus ring suitable for the process (see, e.g., reference patent 3).
As one example in the above-mentioned reference patents, a silicon ring is used when etching a silicon oxide film, and, for example, an insulator, such as quartz or the like, is used when etching polysilicon.    reference patent 1: Japanese Patent Laid-Open Publication No. 8-335568 (pages 3-4, FIG. 2)    reference patent 2: Japanese Patent Laid-Open Publication No. 2000-36490 (page 5, FIG. 3)    reference patent 3: Japanese Patent Laid-Open Publication No. 8-162444 (page 5, FIG. 2)

Plasma processing apparatus, ring member and plasma processing method

Abstract: [Solution] A ring member formed of an insulating material is disposed to surround a to-be-treated substrate in a processing vessel and an electrode is installed in the ring member for adjusting a plasma sheath region. For example, a first DC voltage is applied to the electrode when a first process is performed on the to-be-treated substrate and a second DC voltage is applied to the electrode when a second process is performed on the to-be-treated substrate. In this case, the plasma state can be matched by applying an appropriate DC voltage according to each process or each apparatus executing the same process. Therefore, the sharing of an apparatus can be promoted and the plasma state can be readily adjusted.


An abnormality determination system includes: an autonomous moving object including at least one distance measuring unit that is disposed to face a road surface in a moving direction ant that measures a distance to the road surface; a charging unit including a connection terminal for charging a battery of the autonomous moving object; a stepped portion disposed on a road surface which is subjected to measurement by the distance measuring unit when the autonomous moving object is connected to the connection terminal of the charging unit and is positioned; and a determination unit configured to determine whether the distance to the stepped portion measured by the distance measuring unit at the time of positioning is less than a threshold value.

1. Field of the Invention
The present invention relates to an abnormality determination system determining abnormality in a distance measuring unit disposed in an autonomous moving object and a determination method thereof.
2. Description of Related Art
An autonomous moving object is known which prevents a drop or a fall due to a stepped portion or the like by detecting the stepped portion or the like and performing a stopping or avoiding operation when a distance to a road surface measured by a distance measuring unit is greater than a threshold value (for example, see Japanese Patent Application Publication No. 2012-130781 (JP 2012-130781 A)).

Abnormality determination system and determination method thereof


An extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. The extender card has an intercepting EEPROM chip that receives device-select lines from the motherboard. One of the device-select lines from the motherboard to a module EEPROM chip on the memory module is blocked by the extender card and altered so that the intercepting EEPROM chip is read by the motherboard rather than the module EEPROM chip. A memory configuration is read from the intercepting EEPROM chip. The memory module is tested by the motherboard using the configuration from the intercepting EEPROM chip on the extender card. The module EEPROM chip is then programmed with the configuration by altering the intercepted device-select address to select the module EEPROM chip and not the intercepting EEPROM chip.

This invention relates to testing of memory modules, and more particularly to testing memory modules having a configuration memory.
Electronic systems such as personal computers (PC's) often use small printed-circuit board (PCB) daughter cards known as memory modules instead of directly mounting individual memory chips on a motherboard. The memory modules are built to meet specifications set by industry standards, thus ensuring a wide potential market.
As more and more configurations of memory modules are specified, often with many different memory configurations being interchangeable with one another, the PC or other system must determine the exact configuration of any memory modules installed. Memory-sizing routines can be executed by the PC at boot-up, but more recently the configuration information is being stored on the memory module itself. A small programmable memory chip is added to these modules. The programmable memory is programmed with the specific configuration of that module. The PC can simply read the configuration from this memory rather than run the memory-sizing routine.
FIG. 1A shows a memory module having a programmable configuration memory. Memory module 10 includes one or more dynamic-random-access memory (DRAM) chips 18 that are accessible through one or more rows of metal contacts that fit into a socket on the PC motherboard.
Memory module 10 also contains an electrically erasable and programmable read-only memory, EEPROM chip 20. The configuration of memory module 10 is programmed into EEPROM chip 20 by the module manufacturer. When memory module 10 is inserted into a socket on the PC motherboard, the PC reads the configuration in EEPROM chip 20 to determine the configuration of memory module 10.
This configuration information is determined by the size, type, and arrangement of DRAM chips 18. For example, the total number of bytes of storage, the width of the data bus, the number of column and row address bits, and the number or arrangement of banks can be programmed into EEPROM chip 20. Other useful information can be included, such as the type of DRAM chips 18 (clocked, non-clocked, etc.), timing parameters such as cycle and access times, voltages used, and burst capabilities. Revision codes and other information can also be stored.
Such configuration information can be stored in a relatively small amount of memory, such as in a 64-byte or 256-byte memory. EEPROM chip 20 can be reduced in the number of pins and cost by using serial data access rather than a byte-wide access. The PC can detect the presence of such an EEPROM chip 20 on memory module 10, and then read the configuration data out serially. Such an EEPROM chip 20 is sometimes known as a serial-presence-detect (SPD) EEPROM.
An expensive electronic test system can be used by the module manufacturer to test DRAM chips 18, and to write the configuration data to EEPROM chip 20. However, less expensive testers are desirable to reduce test costs. For example, modified PC motherboards have been used as testers of memory modules. See for example U.S. Pat. Nos. 6,357,022 and 6,415,397 by Nguyen et al. and Co et al., and assigned to Kingston Technology Company of Fountain Valley, Calif., These motherboard testers can cost 100 to 1000 times less than a specialized electronic test system since they are made from inexpensive PC motherboards.
FIG. 1B shows pre-programming a configuration EEPROM chip during testing of a memory module. PC motherboards read the configuration data from EEPROM chip 20 on memory module 10, so EEPROM chip 20 must be pre-programmed before testing by PC motherboard tester 14. Programmer 12 is a specialized device that generates signals to write the configuration information of memory module 10 into EEPROM chip 20.
Once EEPROM chip 20 has been programmed by programmer 12, then memory module 10 can be removed from programmer 12 and inserted into a socket on PC motherboard tester 14. FIG. 1C shows a PC motherboard testing a memory module with a pre-programmed EEPROM chip. Once memory module 10 is inserted into a socket on PC motherboard tester 14, the motherboard is re-booted, causing the PC initialization routines to search for and read the configuration information from EEPROM chip 20 on memory module 10. Then a memory test is performed by writing to and reading from each memory location in DRAM chips 18 on memory module 10. Failing modules can be identified and discarded.
When a low-cost PC motherboard tester is used, two separate steps are required: pre-programming the configuration EEPROM with programmer 12, and testing the memory module using PC motherboard tester 14. Since two test machines are used, two test stations and two insertion/removals are required, doubling the amount of handling required compared with testing a memory module without a configuration EEPROM.
The additional step of pre-programming the configuration into EEPROM chip 20 is required before testing by PC motherboard tester 14. This additional step requires that each memory module be inserted and removed from a socket on programmer 12, as well as be inserted and removed from a socket on PC motherboard tester 14. Pre-programming by programmer 12 is thus undesirable.
What is desired is a PC-motherboard tester that can test memory modules before configuration is programmed into an EEPROM chip on the memory module. An integrated tester that can test memory modules and then program configuration into the EEPROM chip is desirable.

Extender card with intercepting EEPROM for testing and programming un-programmed memory modules on a PC motherboard


A remote controller for setting timer programming items wherein a display section is constructed in such manner that display items are provided in parallel with mechanical rotary switches, the distance between the rotary switches and their displays is adjacent and the relation between them becomes one to one correspondence, whereby an operator manipulates operational switches without making mistakes while looking at display items corresponding to the operational switches.

1. Field of the Invention
The present invention relates to a remote controller for controlling electrical systems such as a television, a video tape recorder (hereinafter referred as to VTR), an air conditioner and the like at hand, away from a main control unit of an electric appliance.
2. Description of the Prior Art
In such a remote controller, for example, the remote controller for a VTR is used to timer-program video recording of television broadcasts. And, in such timer programming, there are a type of system wherein a display section is provided on the remote controller and the setting of operation items is performed as looking at the operation items displayed on the display section and thereafter the settings being transferred to the main control unit, and another type of system wherein the operation items are displayed on a screen of a television and the setting is performed by using a remote controller.
However, in the conventional remote controllers referred to, the display section is designed to display various kinds of display items by switching over, and when setting the timer programming of television broadcasts, the setting contents are inputted while changing the various kinds of display items. In this manner, the display section changeably displays a plural of display items so that the relation between the switching operation and its display does not become one to one correspondence. Further, because most remote controllers employ push bottoms, in operating the push buttons, both the action of inputting ascending values and that of inputting descending values are performed by the same action of pressing the push buttons. Therefore, when setting values such as hours while putting a timer for timer programing forward or back by pressing push buttons, there is the case that thinking for operating does not become coincident with operation. This causes the operation to be complicated and the remote controller to be difficult to operate and then, it takes long time to be familiar with its operation. Furthermore, there is such problem that because of a mistake of timer programming, the video recording of television broadcasts at a pre-set time does not carry out satisfactorily.


A cleaning blade (11) is formed of a cured urethane composition of a polyisocyanate and a polyol. The cured composition has a crosslinking density of 8.5.times.10.sup.-4 to 11.0.times.10.sup.-4 mol/cm.sup.3 and a tan .delta. peak temperature of not greater than 10.degree. C.

An electrophotographic printer has a photosensitive drum with a photoconductive surface layer. In operation, a peripheral surface of the photosensitive drum is uniformly charged, the peripheral surface is exposed through an image of a subject to be copied so as to form an electrostatic latent image thereon, the toner is deposited on the electrostatic latent image for formation of a toner image, and the toner image is copied on a sheet of paper and the like. As shown in FIG. 2, since a toner 2 remains on a peripheral surface of a photosensitive drum 1 after copying, the toner 2 is removed by bringing a distal edge of an elastic cleaning blade 3 into sliding contact with the peripheral surface of the photosensitive drum 1. In the Figure, the cleaning blade 3 is supported by a holding plate 4, and one end of the holding plate 4 (the opposite end to the cleaning blade 3) is fixed on a resin case 5.
The service life of the cleaning blade 3 is determined by physical factors such as abrasion loss and damage through sliding contact, and chemical factors such as stain resistance against toner. A urethane rubber is generally used for formation of the cleaning blade due to its excellent properties against these factors. However, use of the cleaning blade formed of the urethane rubber for a long time causes an remarkable presence of time-course abrasion loss. Therefore, fog (toner is scattered in a non-image portion on a paper sheet), white spot, or the like occur. Accordingly, there have been attempts to enhance the wear resistance of the cleaning blade, such as a method for enhancement of hardness of urethane rubber which is disclosed in Japanese Patent Provisional Publication No. 2-208687.
The cleaning blade obtained according to the above method shows a better effect to some extent, however, the cleaning blade is so hard that it causes damage to the photosensitive drum. In order to enhance the wear resistance, the following methods have been proposed; 1 dispersing a lubricant in urethane rubber (Japanese Patent Provisional Publication No. 7-306616), (2 silicone-modifying urethane rubber (Japanese Patent Provisional publication No.5-224573), 3 providing a coating on a surface of a cured urethane rubber (Japanese Patent Provisional Publication No.4-260084), and 4 breaking the regularity(crystallinity) of a soft segment of the blade (Japanese Patent Provisional Publication No.8-44264). However, in methods 1 to 3, an additional process such as adding a lubricant is required, and in the method 4, the liquid composition for formation of the cleaning blade has a high viscosity, thereby deteriorating processability. In all the above methods, production costs will increase.
On the other hand, a good image forming characteristic is required under an environment of a low temperature as well as ordinary temperature, so that reliability for the electrophotographic printer is enhanced. Thus, it is important that the cleaning blade has a good low temperature cleaning performance.


In one embodiment of the present invention, a method for forecasting a Last Time Buy quantity for a service part using a low-pass filter approach is provided. The method includes accessing input data including: (1) a service lifespan beginning at the end of mass production of a product associated with the service part; (2) data reflecting past accumulated production of the associated product for at least a first period beginning at the end of mass production of the associated product; and (3) an order data series reflecting past quantities of the service part ordered in each of a succession of periods beginning with a second period that immediately follows the first period and ending with a current period. A low-pass filter is applied to at least a portion of the order data series to extract low frequency components representing a smoothed order data series. A local maximum is sought within the smoothed order data series subject to predetermined conditions. If a local maximum is found within the smoothed order data series, exponential forecasting is performed according to the smoothed order data series to generate an estimated Last Time Buy quantity for the service part over all remaining periods of the service lifespan following the current period. The estimated Last Time Buy quantity for the service part is made available for use in connection with one or more business analyses.

Business forecasting and analysis concerning products are fundamental tasks for many manufacturers, suppliers, retailers, and other enterprises that must furnish products in response to demand from purchasers. From a consumption perspective, products in industries such as automotive, high tech, electronics, appliances, and the like have consumption life cycles (e.g., the time between purchase of the product and the end of its useful life). From a manufacturing perspective, such products have production life cycles (e.g., the entire time of mass production of the product). A product may remain in use for quite some time after the end of mass production. During this time (between the end of the production life cycle and the end of the consumption life cycle), original parts within the product may need to be replaced with service parts to keep the products operating properly. However, manufacturers are typically only responsible to provide such service parts for a specified service lifespan, for example, according to law, regulations, business goals, or any other guidelines depending on the product. As an example, mass production of the 1996 FORD TAURUS model might have ended in April 1997, but as the manufacturer of the model FORD might still be responsible to supply necessary service parts for this model for at least a specified number of years after April 1997.
The phrase "Last Time Buy" quantity for a service part is generally used to refer to the total quantity of demand (such as in the form of purchaser orders) for the service part between a selected point in time after mass production of the associated product ends to the end of the service lifespan for the associated product. A service part is commonly referred as a Last Time Buy part when several years have passed after the end of mass production of the associated product and there is no longer any significant demand for the associated product or its parts. The trigger to start treating a service part as a Last Time Buy part is typically an announcement from the part manufacturer requesting purchasers to initiate final purchases of the service part, as the manufacturer will soon cease providing the service part for purchase.
Forecasting Last Time Buy quantities for service parts is an important issue for industries such as those mentioned above. For example, adequately forecasting Last Time Buy quantities for service parts may significantly reduce inventory costs, improve planning, and increase profitability. However, forecasting Last Time Buy quantities for service parts is a challenging task. Unfortunately, there has been little success developing suitable approaches for estimating future demand for Last Time Buy service parts. For example, one previous approach uses a moving average of order histories to detect a trend (e.g., up, flat, or down) and then uses a different technique to estimate future demand depending on the nature of the trend (e.g., an exponential technique for an up or flat trend or a "stair" technique for a down trend). Problems associated with this and other previous approaches make such approaches inadequate for many needs.

Forecasting a last time buy quantity for a service part using a low-pass filter approach


An adjustment mechanism for adjusting a formed staple height of a suture staple in a stapler comprises a first handle portion and a second handle portion. The first handle portion comprises a cartridge support located at a distal end, a cartridge assembly, a drive assembly, and the adjustment mechanism for adjusting a formed staple height of a suture staple, and the second handle portion comprises an anvil located at a distal end. The cartridge assembly comprises suture staples, and the drive assembly can drive a suture staple to leave the cartridge assembly to reach the anvil to be pressed and formed. The adjustment structure adjusts a distance between the drive assembly and the anvil to adjust a formed staple height of a suture staple in a stapler. This application further relates to a stapler, comprising the adjustment mechanism for adjusting a formed staple height of a suture staple in a stapler.

Currently, surgical staplers are increasingly widely applied to clinical surgeries and comprise linear staplers and circular staplers. The working principle of a surgical stapler is generally as follows: Two handle assemblies (one handle usually comprises an anvil assembly, and the other handle comprises a cartridge assembly) fitting each other are closed to hold tissue, and a suture staple in the cartridge assembly is then pushed out and formed to suture together the tissue. In some staplers, a cutting knife is further mounted. A plurality of rows of suture staples is stapled in body tissue and at the same time cut tissue between these rows of suture staples, so as to cut the sutured tissue.
A surgical stapler having the foregoing function comprises a first handle portion and a second handle portion. The first handle portion comprises a detachable cartridge assembly, a fixing rod, and a drive assembly. The cartridge assembly generally comprises a cartridge, several suture staples, several staple pushers. An upper surface of the cartridge is a tissue contact surface. A plurality of rows of holes is provided in the tissue contact surface. The suture staples are installed in the holes in advance. The second handle portion comprises an anvil. The anvil comprises a staple forming surface. A plurality of rows of staple forming slots is provided in the staple forming surface. The first handle portion and the second handle portion can be connected together, and are fixed through the fixing rod located at the first handle portion, so as to close tissue that needs to be sutured. The drive assembly in the first handle portion comprises a wedge-shaped push piece. When the drive assembly moves from a proximal end to a distal end of the stapler, the wedge-shaped push piece pushes the staple pushers, so as to push a suture staple in the cartridge out from a cartridge hole to penetrate closed tissue to reach the staple forming slots in the staple forming surface of the anvil to be pressed into a "B" shape. Generally, the drive assembly further comprises a cutting knife used to cut tissue between a plurality of rows of staple threads after the tissue is sutured with suture staples.
In many technical solutions, a formed staple height of a plurality of rows of suture staples in the stapler is fixed and is not adjustable. However, different parts of a human body portion have tissue with different thicknesses, and thicknesses also vary between people. Therefore, in some cases, if a formed staple height of a suture staple is excessively high, suture-hole bleeding may occur and a patient's life may be in jeopardy, and if a formed staple height of a suture staple is excessively low, tissue around cutting edges may die due to lack of blood supply, and as a result, the suture staples fall off and anastomotic leakage occurs.
Therefore, there is a pressing need for an improved surgical stapler with an adjustable formed staple height of a suture staple.

Adjustment mechanism for adjusting formed staple height of suture staple in stapler and stapler comprising same

SHANGHAI YISI MEDICAL TECHNOLOGY CO., LTD.

YISI (SUZHOU) MEDICAL TECHNOLOGY CO., LTD.


A vehicle braking system having a hydraulic booster which applies output hydraulic pressure of a hydraulic power source to a boosted hydraulic pressure chamber after regulating the output hydraulic pressure as a control piston balances a reaction force generated by hydraulic pressure of the boosted hydraulic pressure chamber with brake operating input. The boosted hydraulic pressure chamber faces a rear face of a master piston of a master cylinder; and a brake stroke simulator installed between a brake operating member and the control piston. The hydraulic booster includes a backup piston slidably housed in a casing with its front face turned to the boosted hydraulic pressure chamber and which can directly push the master piston in response to operation of the brake operating member when the hydraulic pressure of the boosted hydraulic pressure chamber decreases. The control piston and the brake stroke simulator are contained in the backup piston.

1. Field of the Invention
The present invention relates to a vehicle braking system comprising: a master cylinder in which a master piston with its back turned to a boosted hydraulic pressure chamber is slidably housed in a casing; a hydraulic booster which has a control piston for achieving a balance between reaction force generated by the hydraulic pressure of the boosted hydraulic pressure chamber and brake operating input from a brake operating member, and which applies output hydraulic pressure of a hydraulic power source to the boosted hydraulic pressure chamber after regulating the output hydraulic pressure as the control piston moves axially; and a brake stroke simulator installed between the brake operating member and the control piston in order for a driver to feel operating strokes of the brake operating member, the master cylinder being connected to wheel brakes.
2. Description of the Related Art
Such a vehicle braking system is disclosed, for example, in Japanese Patent Publication No. 52-187.
However, in the conventional vehicle braking system, when connecting a hydraulic booster and a brake stroke simulator to each other, the brake stroke simulator is mounted in a casing and then the hydraulic booster is mounted by connecting the brake stroke simulator to a control piston. This complicates the assembling, and it cannot be said that the efficiency in the assembling is high.


An ink jet recording apparatus having: a serial type recording head which has a plurality of ink jet openings for jetting photo-curable ink toward a recording medium, the ink jet openings being arranged in one or more lines; and an irradiation section which is provided adjacent to the recording head in a scanning direction of the recording head, for irradiating an ink jetted on the recording medium with light, the irradiation section having a plurality of irradiation elements which correspond to the ink jet openings, respectively, and which are arranged in one or more lines in approximately parallel with an arrangement direction of the plurality of ink jet openings, and an irradiation controller for controlling the irradiation elements to light at least an irradiation element which corresponds to an ink jet opening which jetted the ink, in the plurality of irradiation elements.

1. Field of the Invention
The present invention relates to an ink jet recording apparatus and, more particularly, to an ink jet apparatus in which photo-curable ink is used.
2. Description of the Related Art
Recently, as a method to record an image on a recording medium such as a paper, an ink jet recording method in which ink is jetted on a surface of the recording medium and a gravure printing method in which ink which is stored in a concave portion of a plate is copied to the recording medium have been well known. In these methods, the ink jet recording method makes it possible to form an image at low cost and easily in comparison with the gravure printing method which requires making a plate. As the ink jet recording method, there is a photo-curable ink jet method in which photo-curable ink is used. An ink jet recording apparatus of the ink jet method has a recording head 101 which has a plurality of ink jet openings 100, . . . for jetting ink toward the recording medium downward and an irradiation section 102 for irradiating ink jetted on a surface of the recording medium with light (see, for example, Japanese Application Patent Laid-Open Publication No. 2001-310454).
More particularly, the irradiation section 102 has one irradiation element 103 such as a mercury lamp which can diffuse light to irradiate a wide region with light for curing the whole ink jetted on the surface of the recording medium.
However, when curing the ink on the surface of the recording medium by the above described irradiation section 102, the irradiation element 103 irradiates a portion of the recording medium on which the ink is not jetted with light. Thus, there has a problem that it requires a large amount of power and the irradiation section 102 has a short life.
One irradiation element 103 diffuses light to irradiate a wide region with light, so that the light radiated from the irradiation section 103 becomes a reflected light with low lighting intensity on the surface of the recording medium and diffuses around. Therefore, specially, when using ink such as cationic polymerization ink which is cured by light with low lighting intensity, the ink which adhered to ink jet openings 100 is cured by the above described reflected light with low lighting intensity and obstructs ink jet.


A short shaft has: a rear socket for coupling with a drive; a front drive for receiving a socket; and locking components for locking the rear socket to the drive and the front drive to the received socket. A central bore enters the shaft from the rear. A locking bolt and biasing spring go in the central bore and are retrained by a set screw. The locking bolt front end engages a detent ball disposed in a radial cavity in the drive. A thumb lever, disposed in a bore, has an inner end including a bore for engaging the locking bolt rear section for moving the locking bolt and an outer end accessible to a user's thumb for axial movement for moving the bolt from a locking position wherein the detent ball protrudes out of the drive so as to engage a drive socket and prevent its removal to a releasing position wherein the detent ball resides substantially within the front drive so as not to engage a drive socket. In an alternate embodiment, a universal joint is interposed between the rear socket and the locking/front drive apparatus.

1. Field of the Invention
This invention relates, in general, to socket wrench systems and more particularly involves a locking adapter drive for releasingly locking a drive socket to a drive. An alternate embodiment of the locking adapter incorporates a universal joint.
2. Background of the Invention
The desirability of some type of locking drive for a socket wrench system has long been recognized as a means to prevent the system components from uncoupling. For example, U.S. Pat. No. 4,480,511 of M. F. Nickipuck titled "Locking Socket Wrench Drive Device" describes a socket wrench extension having drive end that locks onto a socket, and U.S. Pat. No. 4,502,365 of K. M. Hacker titled "Socket Wrench Extension" also describes an extension with a releasing locking device on the drive. U.S. Pat. No. 4,781,085 titled "Locking Socket Wrench Extension" of current co-inventor L. Fox III describes another such device.
The desirability of a locking ratchet drive is also seen in the prior art. U.S. Pat. No. 4,399,722 of V. Sardo titled "Socket Wrench Including Quick Release Adaptor" describes a ratchet drive including a mechanism for locking a socket to the drive head.
Due to the added complexity and expense of these devices most ratchet drives sold do not contain a locking feature and the conventional locking devices suffer from one or more shortcomings. They are overly complex, expensive, difficult to assemble, difficult to use, or jam or do not work when subjected to a dirty environment. Importantly, they require a considerable amount of space for their implementation which changes the handling characteristics of the tool.
Therefore, there has been a need for a short adapter for converting a conventional ratchet drive into a locking drive such that its addition to the drive does not noticeably alter the performance and handling of the ratchet driver.
Also, because of the non-axial forces exerted on a universal coupling, a universal coupling has more of a tendency to disengage. Therefore, a locking universal adapter is desirable, particularly if it results in no significant added length.


Examples of computing devices and assemblies for mounting computer components to an enclosure or other structure of the computing device are described. In some examples, the mounting assembly may include a compliant member having a plurality of corner portions configured to engage the corners of the component. The mounting assembly may also include a bracket configured to enclose at least a portion of the compliant member. The mounting bracket may be configured to mount the component at an angle relative to the enclosure or other structure, and may include one or more features adapted for improved cooling of the component mounted therein. The compliant member may include a plurality of ribs or other retaining elements for maintaining the component in a spaced apart position relative to the mounting bracket.

Computing devices generally include numerous internal components such as memory, storage devices (e.g. disk or solid state drives), processors, thermal management devices, and various input/output (I/O) circuitry and interfaces. The components of a typical computing device are generally enclosed within a housing or enclosure, which may be made of plastic, metal, glass, and/or any other material suitable for protecting the internal components of the computer and for achieving a desired aesthetic appearance.
Interaction between a user and a computer is typically effectuated through I/O devices such as keyboards, trackpads, mice, trackballs, various other pointer devices, monitors, printers, and still other peripheral devices. Frequently, I/O devices are external to the housing and the computing device may be adapted for connecting with peripheral devices using standardized I/O interfaces and/or connectors. I/O connectors for plugging in peripheral devices and their respective circuitry may be provided on the main logic board of the computing device or on auxiliary circuit boards plugged into the main logic board. In some instances, such as certain laptop and handheld computers, certain I/O devices may be at least partially integrated with the computer and accessible through the enclosure. An example of I/O device integration in laptop computers is the incorporation of a keyboard and a touchpad partially within the laptop's housing.
In some instances, desktop computers may also have components integrated within the same enclosure which houses the display device, for example. While such integration generally enhances the user experience, new challenges may be introduced through the implementation of such integration. For example, the compact nature of integrated devices generally results in a smaller design space within which the computer components must be accommodated. The compact design space not only may necessitate smaller sized components but may bring components closer together and likely may necessitate tighter tolerances. The proximity of certain components to others may have undesirable consequences, and last but not least, aesthetic considerations may also dictate design choices. Accordingly, improved devices for locating internal computer components and improved methods for assembling internal components of a computing device within the same enclosure may be needed.

Internal computer assembly features and methods


An azimuth measuring device is provided that can obtain offset information when the direction of the azimuth measuring device is arbitrarily changed. The offset information is calculated based on coordinates of a reference point obtained by a reference point estimating system. The azimuth measuring device can obtain the offset information without obtaining erroneous offset information when changing direction.

Azimuth measuring devices which detect earth magnetism to obtain azimuths are used for navigation in cellular phones, or the like. When using an azimuth measuring device of this kind, it is usually known that it would indicate an erroneous azimuth unless an azimuth is obtained by subtracting the offsets which are an output signal caused by a surrounding magnetic field other than earth magnetism detected by a magnetic field sensor and an offset for an output of a signal processing circuit at the time when no signal is inputted.
As methods for obtaining an offset, there are known methods, as one disclosed in Patent Document 1, in which an azimuth measuring device is kept horizontally and turned around once, and the maximum and minimum of output signal are searched in the meantime and the offsets is set to a midpoint thereof, and another one in which, as disclosed in Patent Document 2, an equation for the trajectory of output signal while an azimuth measuring device is turned around once is solved based on geomagnetic data which is obtained by directing an azimuth measuring device at arbitrary three points being perpendicular to each other, and then an offset is calculated. In addition, there is a method in which offset information is calculated based on geomagnetic data obtained while the direction of an azimuth measuring device is arbitrarily changed in a three dimensional space (the above method can be found in Patent Document 3, and is incorporated into the present application with reference thereto).
FIG. 3 is a view explaining the concept of a method for obtaining offset information in an azimuth measuring device. This method is disclosed in Patent Document 3.
In FIG. 3, the direction of an azimuth measuring device 1 is arbitrarily changed in a three dimensional space, and, in the meantime, x-axis geomagnetic measured data, y-axis geomagnetic measured data, and z-axis geomagnetic measured data are repeatedly obtained until the number of obtained data reaches a predetermined number N. Hereinafter, Sx, Sy, and Sz denote geomagnetic measured data on which sensitivity correction has been performed with a sensitivity correction calculation section provided to an azimuth measuring device 1, unless otherwise noted.
Individual data of Sx, Sy, and Sz having been repeatedly obtained are respectively set as P1(S1x, S1y, S1z), P2(S2x, S2y, S2z), P3(S3x, S3y, S3z), . . . , and as shown in FIG. 3. They are placed in a three dimensional space by relating the values of Sx, Sy, and Sz to the direction components of the respective axes.
Here, Sx, Sy, and Sz are expressed by the following equations.Sx=a·Mx+Cx  (1)Sy=a·My+Cy  (2)Sz=a·Mz+Cz  (3)where a is a sensitivity after performing a sensitivity correction for an x-axis hall element HEx, a y-axis hall element HEy, and a z-axis hall element HEz; Mx, My, and Mz are x, y, and z-axis direction components of earth magnetism; and Cx, Cy, and Cz are the offsets of Sx, Sy, and Sz, respectively.
On the other hand, the relationship between Mx, My, Mz and M is given as follows.
[Equation 1]M=√{square root over (Mx2+My2+Mz2)}  (4)Now, setting as,
[Equation 2]r=a√{square root over (My2+My2+Mz2)}  (5)then, the following equation is derived.(Sx−Cx)2+(Sx−Cx)2+(Sx−Cx)2=r2  (6)That is, (Sx, Sy, Sz) is certainly placed away from a reference point OP(Cx, Cy, Cz) with the same distance r.
Accordingly, the reference point OP can be estimated by calculating a point which has equal distances from all the points of P1(S1x, S1y, S1z), P2(S2x, S2y, S2z), P3(S3x, S3y, S3z), . . . , and the offsets Cx, Cy, and Cz can be obtained on the basis of the coordinate values thereof.
Although there are various kinds of methods for estimating the reference point OP, Sx, Sy, and Sz to be actually obtained are measured data of extremely weak earth magnetism which is of the order of 0.01 mT, and overlap with a significant amount of noise, and it is hence preferred that a statistical method be used after increasing the number of obtained data N as many as possible. Now, for example, according to a method described in Patent Document 3, as in the following equation, a system of linear equations with respect to Cx, Cy, and Cz can be solved, and thereby the reference point OP can be estimated in a good accuracy while suppressing the increase of the calculation time.
                    [                  Equation                                                              3                ]                                                                                [                                                                                ∑                                                                                Si                          x                                                                                (                                                                                Si                              x                                                        -                                                                                S                                x                                                            _                                                                                )                                                                                ∑                                                                                Si                              y                                                                                (                                                                                Si                                  x                                                                -                                                                                S                                    x                                                                    _                                                                                )                                                                                ∑                                                                                Si                                z                                                                                (                                                                                Si                                    x                                                                    -                                                                                S                                      x                                                                        _                                                                                )                                                                                ∑                                                                                Si                          x                                                                                (                                                                                Si                              y                                                        -                                                                                S                                y                                                            _                                                                                )                                                                                ∑                                                                                Si                              y                                                                                (                                                                                Si                                  y                                                                -                                                                                S                                    y                                                                    _                                                                                )                                                                                ∑                                                                                Si                                z                                                                                (                                                                                Si                                    y                                                                    -                                                                                S                                      y                                                                        _                                                                                )                                                                                ∑                                                                                Si                          x                                                                                (                                                                                Si                              z                                                        -                                                                                S                                z                                                            _                                                                                )                                                                                ∑                                                                                Si                              y                                                                                (                                                                                Si                                  z                                                                -                                                                                S                                    z                                                                    _                                                                                )                                                                                ∑                                                                                Si                                z                                                                                (                                                                                Si                                    z                                                                    -                                                                                S                                      z                                                                        _                                                                                )                                                                                ]                                          [                                                                                C                    x                                                                                C                    y                                                                                C                    z                                                                        ]                          =                            (        7        )                                                                                1            2                                          [                                                                                ∑                                                                  (                                                                              Si                            x                            2                                                    +                                                      Si                            y                            2                                                    +                                                      Si                            z                            2                                                                          )                                                                                (                                                                              Si                            x                                                    -                                                                                S                              x                                                        _                                                                          )                                                                                ∑                                                                  (                                                                              Si                            x                            2                                                    +                                                      Si                            y                            2                                                    +                                                      Si                            z                            2                                                                          )                                                                                (                                                                              Si                            y                                                    -                                                                                S                              y                                                        _                                                                          )                                                                                ∑                                                                  (                                                                              Si                            x                            2                                                    +                                                      Si                            y                            2                                                    +                                                      Si                            z                            2                                                                          )                                                                                (                                                                              Si                            z                                                    -                                                                                S                              z                                                        _                                                                          )                                                                                ]                                                          where
                    [                  Equation                                                              4                ]                                                                                S            x                    _                =                              1            N                                          ∑                          Si              x                                                          (        8        )
                    [                  Equation                                                              5                ]                                                                                S            y                    _                =                              1            N                                          ∑                          Si              y                                                          (        9        )
                    [                  Equation                                                              6                ]                                                                                S            z                    _                =                              1            N                                          ∑                          Si              z                                                          (        10        )            Moreover, r is expressed by following equation by using Cx, Cy and Cz.
                    [                  Equation                                                              7                ]                                                                      r          2                =                              1            N                                          ∑                          {                                                                    (                                                                  Si                        x                                            -                                              C                        x                                                              )                                    2                                +                                                      (                                                                  Si                        y                                            -                                              C                        y                                                              )                                    2                                +                                                      (                                                                  Si                        z                                            -                                              C                        z                                                              )                                    2                                            }                                                          (        11        )
FIG. 4 is a flowchart showing a method of obtaining offset information in an azimuth measuring device. This method is disclosed in Patent Document 3.
In FIG. 4, a data buffer section provided to an azimuth measuring device obtains geomagnetic measured data Sx, Sy, and Sz, and puts them into a buffer. (Step S1)
Next, it is determined whether the number of geomagnetic measured data Sx, Sy, and Sz retained in the data buffer section has reached the predetermined number N of data to be obtained. (Step S2)
When the number of geomagnetic measured data Sx, Sy, and Sz retained in the data buffer section has not reached the predetermined number N of data to be obtained, the process returns to Step S1.
On the other hand, when the number of geomagnetic measured data Sx, Sy, and Sz retained in the data buffer section has reached the predetermined number N of data to be obtained, a data processing section provided to an azimuth measuring device 1 reads geomagnetic measured data Sx, Sy, and Sz from the data buffer section to the number of which data correspond to the predetermined number N of data to be obtained; and the coordinates Cx, Cy, and Cz of the reference point OP are estimated such that the variation of the distances from individual data P1(S1x, S1y, S1z), P2(S2x, S2y, S2z), P3(S3x, S3y, S3z), . . . is minimized. (Step S3)
As the offsets of geomagnetic measured data Sx, Sy, and Sz, the coordinates Cx, Cy, and Cz of the reference point OP are stored in an offset information storing section provided to an azimuth measuring device. (Step S4)    Patent Document 1: U.S. Pat. No. 1,422,942 Specification    Patent Document 2: Japanese Patent Application Laid-open No. 2000-131068    Patent Document 3: International Application No. JP03/08293 Specification


In an aspect, an organic light emitting display device is provided. The organic light emitting display device may include a substrate; an organic light emitting unit arranged on the substrate; at least one inorganic layer, which encapsulates the organic light emitting unit and contains a low temperature viscosity transition (LVT) inorganic material; and at least one adhesive layer arranged between the organic light emitting unit and the inorganic layer.

1. Field
This disclosure relates to an organic luminescence emitting display device and a method for manufacturing the same, and more particularly, to an organic luminescence emitting display having excellent encapsulation characteristics and a method of manufacturing the same.
2. Description of the Related Technology
An organic light emitting display device is a self-luminescent type display device including an organic light emitting device including a hole injection electrode, an electron injection electrode, and an organic light emitting layer formed therebetween, where the organic light emitting display device emits light as excitons, which are generated as holes injected by the hole injection electrode and electrons injected by the electron injection electrode are combined at the organic light emitting layer, are switched from excited state to ground state.
Generally, an organic light emitting display is a self-luminescent type display device requiring no separate light source. Thus, the organic light emitting display device may be driven with a low voltage, may be embodied as a thin and lightweight display device, and may feature a wide viewing angle, high contrast, and fast response. Therefore, an organic light emitting display device is of interest as a next-generation display device.
An encapsulation structure for encapsulating the organic light emitting display device from the external environment is required since the device is vulnerable to external influences, such as oxygen and moisture.
Furthermore, a thin organic light emitting display and/or a flexible organic light emitting display are in demand for a variety of applications.

Organic light emitting display device and method for manufacturing the same


A system and method uses one or more repurposed data fields in a payment transaction message to pass the merchant consumable data from a mobile device to the merchant system using an existing channel. The merchant consumable data relate to loyalty or rewards.

Coupons are widely used at point of sale terminals. In a typical transaction, a consumer may present a paper coupon to a clerk at a merchant. The clerk may scan the paper coupon at the point of sale terminal. The discount provided by the coupon may be provided at the point of sale and the consumer may then pay the discounted amount to the merchant using a credit or debit card.
With the increasing use of mobile phones as payment devices at points of sale, there is a need to integrate coupons and other types of merchant consumable data. However, doing this would require significant changes at the existing point-of-sale systems.
Embodiments of the invention address these and other problems, individually and collectively.

This patent is subject to a terminal disclaimer.


A semiconductor device includes bit lines (14) provided in a semiconductor substrate (10), word lines (16) provided above the bit lines and running in a width direction of the bit lines (14), metal lines (22) provided above the word lines (16) and running in a length direction of the bit lines (14), and bit line contact regions (28) running in the length direction of the word lines (16) and located between word line regions (26) in which a plurality of word lines (16) are disposed. Each of the bit lines (14) is connected with every other metal line (22) in the bit line contact regions (28). It is thus possible to provide a semiconductor device and a fabrication method therefor in which an alignment margin can be ensured between a contact hole (18) and the bit line (14) to enable downsizing of a memory cell.

1. Field of the Invention
This invention relates generally to semiconductor devices and fabrication methods therefor, and more particularly, to a semiconductor device that serves as a non-volatile memory with the use of a transistor having multiple charge storage layers and a fabrication method therefor.
2. Description of the Related Art
Recently, non-volatile memories in which data is rewritable have been widely used. In the technical field of non-volatile memories, efforts are being made to miniaturize a memory cell for high memory capacity and to reduce fluctuation in electrical characteristics of a transistor incorporated in the memory. The non-volatile memories include Metal Oxide Nitride Oxide silicon (MONOS) flash memories and Silicon Oxide Nitride Oxide silicon (SONOS) flash memories, in which the charge is stored in an Oxide Nitride Oxide (ONO) film. In addition, another type of flash memory having two or more charge storage regions in one transistor has been developed for the purpose of high memory capacity.
U.S. Pat. No. 6,011,725 discloses an example of a transistor having two charge storage regions arranged between a gate electrode and a semiconductor substrate. In the transistor, a source and a drain are replaced by each other for symmetrical operation for a structure in which a source region and a drain region are not distinguished. In addition, a bit line also serves as the source region and the drain region and is embedded in a semiconductor substrate to further miniaturize the memory cell.
Referring now to FIG. 1, the aforedescribed conventional semiconductor device will be described. FIG. 1 is a top view of a conventional memory cell. Bit lines 44 are embedded in the semiconductor substrate and are arranged in an upward and downward direction. An ONO film (not shown) is provided over the semiconductor substrate. Word lines 46 are provided on the ONO film to run in a width direction of the bit line 44.
The bit line 44 is formed in a diffusion layer by implanting, for example, arsenic ions, and has a relatively high resistance value. The high resistance value of the bit line 44, however, deteriorates writing and erasing characteristics. Therefore, a contact hole 48 provided for multiple word lines 46 couples the bit line 44 to an interconnection layer (not shown). The interconnection layer is made of a metal and is low in resistance, making it possible to prevent writing and erasing characteristics from deteriorating.
The contact hole 48, which couples the bit line 44 and the interconnection layer, is provided in a bit line contact region 28. The bit line contact region 28 runs in a length direction of the word line 46. A word line region 26 is arranged between the bit line contact regions 28. The word line region 26 does not include the contact hole 48 that couples the bit line 44 and the interconnection layer, in multiple word lines 46 (e.g., two word lines in FIG. 1).
The bit line 44 includes a source region and a drain region of a transistor 50. The word line 46 includes a gate electrode of the transistor 50. The memory serves as a non-volatile memory by storing the charge in the ONO film below the word line 46 (gate electrode) arranged between the bit lines 44 (the source region and the drain region). The ONO film in the transistor 50 includes two charge storage regions.
Conventionally, however, if the contact hole 48 and the bit line 44 are misaligned and the contact hole 48 is out of the bit line 44, junction current will flow between the bit line 44 and the semiconductor substrate. To prevent such junction current, an alignment margin provided between the contact hole 48 and the bit line 44 is required, even though such alignment margin is contrary to the purpose of miniaturization of the memory cell, thereby rendering it difficult to downsize the memory cell.

Semiconductor device and programming method therefor


A high voltage plug-in and unplugged type gas immersed cable termination comprising a recess inside the blind end of the electrode to allow the extension of the locking pin to lock the connector with the electrode and thereby anchor the power cable. The locking pin is designed to anchor the power cable to safeguard against sliding down of the power cable during the operation period. The high voltage plug-in and unplugged type gas immersed cable termination can be unplugged manually. The locking pin can be replaced before re-plugging-in of the termination.

In the operation of high voltage equipment, the control of the electric field according to the physical positioning of the power cable is very essential. Movement of the power cable inside a termination may affect the electric field distribution, which will in turn affect the life of the cable termination and may even lead to the failure of the power supply system.
The mainstream technique at the current stage of suspending the power cable inside a high voltage plug-in and unplugged type gas immersed cable termination is to depend on the friction of the power cable with the outer layers. However, with large conductors, the heavy weight of the core increases the risk of its falling down.
For power cable with corrugated aluminium sheath, the friction between the core and the metallic sheath is rather low. There are cases of loosening due to poor manufacturing of cable cores for the corrugated aluminium sheath cable. In this respect, the suspension of the power cable by friction becomes ineffective. Such corrugated aluminum sheath cable is commonly used inside substations where vibration of the transformer under load exists.

High voltage plug in and unplugged type gas immersed cable termination with locking system


An improved system and method for disassembling the valve body assembly of a motor vehicle transmission. Air automatically ejects the internal components of a valve body assembly sub-assembly, thereby eliminating the need for an operator to manually “beat” the sub-assembly to remove said internal components. The process of separating the upper and lower sub-assembly, and of pre-washing the sub-assembly, remain the same as in the prior art. As before, the operator manually removes the valve retainers and plugs in each sub-assembly. The operator then loads either sub-assembly onto tooling specifically designed for that sub-assembly (either upper or lower). Once started, the tooling begins an automated, pre-programmed sequence of (1) clamping the sub-assembly, (2) injecting air into specific valve ports to eject internal components causing them to be automatically ejected into parts bins specified for each valve port, and (3) releasing the sub-assembly that no longer contains any internal parts.

1. Technical Field
The present invention relates to an improved method of remanufacturing motor vehicle transmissions. Specifically, the invention relates to a system and method for using air to eject the internal components of the valve body assembly in a transmission sub-assembly.
2. Description of Related Art
The life of a motor vehicle may be extended in some instances by remanufacturing its transmission. In the case of automatic transmissions the basic remanufacturing process includes disassembly of the core, cleaning and inspection of the individual components, sub-assembly of certain components, and then final re-assembly and test.
The valve body assembly is the heart of a motor vehicle transmission. It directs fluid flow to the appropriate areas. A complete valve body assembly consists of an upper and a lower sub-assembly that are bolted together. Traditionally, disassembly of the valve body involves the following steps: (1) removing the upper sub-assembly from the lower sub-assembly; (2) pre-washing both upper and lower sub-assemblies (when the sub-assemblies are pre-washed all components remain in their respective sub-assemblies); (3) for each sub-assembly, (a) manually removing the valve retainer clips and plugs, (b) manually "beating" the sub-assembly on a work table to eject the internal components of the sub-assembly (springs, valves, etc.), and (c) using a scribe or screwdriver to pry out any components that do not eject using the "beating" method.

Method for disassembling a transmission valve body assembly


An assembly for clamping electrical components against a heat-dissipating surface of a heat sink may include the heat sink, one or more electrical components, two or more springs, and a fastener. Each of the springs may include a first surface, and a second surface opposite the first surface. The second surface of each of the springs may include an attachment region and two contact regions. The attachment region may be between the two contact regions. The second surface of one of the springs may overlap the first surface of another one of the springs. Each of the springs may be positioned to hold the electrical components against the heat dissipating surface of the heat sink. Each of the two contact regions of each of the springs may be positioned to hold the electronic components against the heat-dissipating surface. The fastener may couple the springs together in the attachment region of each of the springs and may further couple the springs to the heat sink.

1. Technical Field
The field of invention relates generally to clamps. In particular, the invention relates to holding electrical components in thermal contact with a heat sink.
2. Related Art
Electrical components may be installed in many different configurations. An electrical component can be any now known or later discovered electrical device such as a transformer, an integrated circuit, a microchip, a semiconductor device, a central processing unit, a diode, a passive device, etc. Electrical components often generate heat. In some cases, if not effectively cooled, electrical components can overheat resulting in improper functioning of, damage to, or even destruction of the electrical components. Heat sinks may be used to cool electrical components to prevent overheating. A heat sink may be any heat-conducting material formed in a shape designed to draw heat away from a surface of the heat sink.
Configurations that include a heat sink may use surface mounted technology (SMT), where electrical components are mounted on the surface of a printed circuit board (PCB) that is interspersed between the electrical components and a heat sink. Other configurations may use lay down components, where electrical components pass through cutouts in the PCB so that the electrical components contact the heat sink. In still other configurations, lay down components are located close to the edge of the PCB so that the electrical components extend beyond the edge and contact the heat sink. Other example configurations use stand-up components where the heat sink may contact the electrical component on a side of the electrical component opposite of a side of the electrical component facing the PCB. In other configurations using stand-up components, the heat sink may contact a side of electrical component that is substantially perpendicular to the PCB, particularly if the electrical component is positioned near the edge of the PCB. It is understood that a given configuration may contain any combination or variation of the configurations described above.
In some configurations, clamping heat-generating electrical components against a surface of a heat sink—or against a surface in thermal contact with the heat sink—may increase the effectiveness of the heat sink. However, the characteristics of the given configuration may impose limitations on what apparatus may be used to clamp the heat-generating electrical components against the surface of a heat sink. For example, the limiting characteristics of a given configuration may include: the number of electrical components to be clamped, the amount of clamping force required for efficient heat transfer, the amount of force the electronic component is capable of sustaining and maintaining proper functionality (e.g., without the electronic component cracking or being crushed), the amount of space available for the clamping apparatus, the cost of manufacturing or installing the clamping apparatus, etc.

Harman International Industries Incorporated


Disclosed herein is a noise cancellation apparatus and method, which select in advance parameters to be used for noise cancellation in a reference voice signal section by generating a reference voice signal in advance before a voice signal is generated, thus improving noise cancellation effects. The noise cancellation apparatus includes a parameter initialization unit for determining an initial value of a parameter to be used for noise cancellation, based on reference signals filtered for respective frequencies, a parameter estimation unit for receiving the initial value of the parameter, and estimating the parameter in response to signals that are input after being filtered for respective frequencies, a gain estimation unit for calculating gains for respective frequencies based on the parameter from the parameter estimation unit, and a gain application unit for cancelling noise by applying the gains to the signals that are input after being filtered for respective frequencies.

1. Technical Field
The present invention generally relates to a noise cancellation apparatus and method and, more particularly, to an apparatus and method that remove noise based on voice characteristics.
2. Description of the Related Art
Since the 1950's, many technologies related to voice recognition have been developed.
Recently, with an increase in cloud-based network processing capacity, an increase in the capacity of a processor and memory for processing voice recognition, and an increase in the necessity of various user interface technologies, voice recognition has attracted attention in various application fields. Based on an increase in network processing capacity and device processing ability, various element technologies are applied, so that a voice recognition rate may be greatly improved in the processing of a natural language as well as an isolating language. By means of this, voice recognition technology may be applied even to application fields requiring the recognition of more words and phrases, and thus the application field of voice recognition technology is expanding.
To improve a voice recognition rate, methods based on various voice recognition technologies have been presented. However, a great variety of technical approaches have been made depending on language models, voice model learning and training, and database (DB) management, as well as application fields. Further, there have been extensive research and development of technology which effectively improves (from the standpoint of performance improvement and complexity reduction) a voice recognition rate by suppressing or cancelling noise contained in voice due to an environment in which voice (speech) is uttered. The present invention is focused on noise cancellation technology and is intended to make an approach to technology areas for improving a voice recognition rate.
Representative noise cancellation technology applied to voice processing (including voice recognition) includes Mel-Frequency Cepstral Coefficients-Minimum Mean Square Error (MFCC-MMSE) technology.
A device to which MFCC-MMSE noise cancellation technology is applied may include a frequency conversion unit for receiving a voice signal in a time domain and converting it into a voice signal in a frequency domain; a power calculation unit for calculating signal power in the frequency domain; a Mel-frequency filter unit for performing filtering in consideration of the frequency domain weight and nonlinearity of the voice signal; a noise cancellation unit for cancelling and suppressing a noise signal by applying an MFCC-MMSE algorithm to the voice signal; an inverse frequency conversion unit for converting the domain of the voice signal using a noise-cancelled signal; a normalization unit for normalizing the received signal by reflecting the gain thereof; and a parameter extraction unit for extracting parameters required for voice recognition using a normalized signal.
Here, the noise cancellation unit is indicated by reference numeral 20 in FIG. 1, and the noise cancellation unit 20 of FIG. 1 may include a parameter estimation unit 21 for receiving signals output from the respective filter banks 10a to 10n of the Mel-frequency filter unit 10 and estimating parameters based on the power (variance) of noise, phase, and voice signals; a gain estimation unit 22 for calculating a MFCC-MMSE gain using the estimated parameters; and a gain application unit 23 for receiving the output signal of the Mel-frequency filter unit 10 and the MFCC-MMSE gain estimated by the gain estimation unit 22 and then performing noise cancellation.
Meanwhile, a noise estimation procedure performed by the parameter estimation unit 21 will be described in detail with reference to the flowchart of FIG. 2.
First, the power of signals and power of noise are extracted (estimated) at step S10.
Then, whether to update noise is determined at step S12. For example, the ratio of signal power calculated in a current frame to the minimum value of signal power is calculated and is compared with a preset threshold value, and then it is determined whether to update noise, based on the results of comparison.
That is, when the ratio of signal power to the minimum value of signal power is equal to or greater than the threshold value, a current section is determined to be a section in which a voice signal is present, and previously estimated noise power is utilized without change at step S14.
In contrast, when the ratio of signal power to the minimum value of signal power is less than the threshold value, the current section is determined to be a section in which a voice signal is not present, and noise power is updated using noise power estimated in a previous frame and noise power calculated in a current frame at step S16.
By means of this scheme, noise power of the current frame is finally determined at step S18.
Here, when a procedure performed at step S12 of determining whether to update noise based on the signal power ratio is represented by an equation, it may be given by the following Equation (1):
                                                                                                                            m                    ...                                    y                                                                  (                  b                  )                                                                    t            2                                                                                                                  m                    ...                                    n                                                                  (                  b                  )                                                                    min            2                          >        ϑ                            (        1        )
In Equation (1), |y(b)|t2, denotes signal power calculated in the current frame and |n(b)|min2 denotes the minimum value of signal power.  denotes a threshold value and is a preset parameter.
Further, when a signal greater than the minimum value by a predetermined ratio is measured, the current section is determined to be a section in which a voice signal is present. That is, since noise power measured in the current frame has an estimated error, the previously estimated noise power is utilized without change. This operation is represented by the following Equation (2):σn2(b)t−1=σn2(b)t−1  (2)Meanwhile, when a signal less than the minimum value by a predetermined ratio is measured, the current section is determined to be a section in which the voice signal is not present, and thus noise power is calculated using the noise power measured in the current frame and the noise power estimated in the previous frame. When this operation is represented by an equation, it may be given by the following Equation (3):σn2(b)t=ασn2(b)t−1+(1−α)|my(b)|t2  (3)where α denotes a coefficient (forgetting factor) used to filter noise power estimated in the previous frame and noise power calculated in the current frame and has a value ranging from [0, 1].
However, a noise power estimation technique in the conventional noise cancellation method estimates the noise power of the current frame using the noise power of the previous frame, thus greatly influencing the entire noise cancellation performance depending on which value is to be set to an initial value of noise power. Therefore, a procedure of determining initial noise power most suitable for a current environment in which voice processing is performed is required.
Further, the conventional noise cancellation method utilizes an Infinite Impulse response (IIR) filter that uses the noise power of a previous frame and noise power calculated in a current frame in a section, in which a voice signal is not present, in order to estimate noise power. As an estimation coefficient (forgetting factor) used at this time, an experimentally determined fixed value is used. In this way, when the fixed forgetting factor is used, there is a problem in that it is difficult to effectively cope with noise characteristics (noise power variation or the like) in various environments. That is, when a forgetting factor of a very large value (≈1) is used in an environment in which noise varies very sharply, it is difficult to track rapidly varying noise power. In contrast, when a forgetting factor of a very small value (≈0) is used in an environment in which noise varies very slowly, a noise estimation error increases, thus negatively influencing noise cancellation performance.
Therefore, in noise cancellation technology for voice processing, there is required a method and apparatus capable of maximizing noise cancellation performance by setting parameters such as an initial noise power value and an IIR filter coefficient to values optimized for an environment.
As related preceding technology, U.S. Patent Application Publication No. 2011-0300806 (entitled "User-Specific Noise Suppression for Voice Quality Improvements") discloses technology in which an application device used by a single user, such as a cellular phone, improves the performance of voice recognition by performing noise suppression based on the voice features of the user.
As another related preceding technology, there is provided technology related to methods of estimating signal and noise levels because the most important factor upon selecting noise cancellation parameters is to estimate signal and noise levels. That is, as such a method, technology for estimating parameters when a voice signal is not present, and utilizing a fixed value when a voice signal is present is published in a paper by Dong Yu, Li Deng, Jasha Droppo, Jian Wu, Yifan Gong, and Alex Acero, "A Minimum-Mean-Square-Error Noise Reduction Algorithm on Melfrequency Cepstra for Robust Speech Recognition", ICASSP 2008 1-4244-1484-9/pp.4014-4044.
As further related preceding technology, technology for improving Cochlear Implant (CI) adaptability to background noise by performing noise suppression adaptively to an environment so as to prevent the performance of CI from being degraded in a noise environment is published in a paper by Vanishree Gopalakrishna, Nasser Kehtarnavaz, Taher S. Mirzahasanloo, "Real-Time Automatic Tuning of Noise Suppression Algorithms for Cochlear Implant Applications", IEEE Trans. on Biomedical Engineering Vol.00, No.00, 2012.

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors.

The present invention relates to a semiconductor device for wireless communication, and particularly to a technology which is effective when applied to a semiconductor device for wireless communication which implements an NFC (Near Field Communication) function in a mobile phone.
For example, in Patent Document 1, a non-contact IC card is shown in which a rectifying circuit, two demodulating circuits, and a modulating circuit are coupled in parallel to the both ends of an antenna coil. Also, in Patent Document 2, a non-contact data storage system is shown which can selectively couple a rectifying circuit and a signal reception node or a transmission node to an antenna coil.

Semiconductor device for wireless communication


The present disclosure includes a computing device, a system, and method for performing a spreadsheet recalculation algorithm. In one embodiment, the computing device includes an electronic processor, and a memory coupled to the electronic processor. The memory includes Directed Acyclic Graph (DAG) data having a plurality of nodes, each node of the plurality of nodes having at least one of a constant value or one or more inputs, and program instructions. The program instructions, when executed by the electronic processor, cause the electronic processor to change the plurality of nodes, and update one or more affected nodes of the plurality of nodes based on the change to the plurality of nodes, the one or more affected nodes being less than all of the plurality of nodes.

The present disclosure relates to direct acyclic graph processing, and more specifically, the present disclosure relates to a topographical sort for directed acyclic graph (DAG) processing.
Spreadsheets, for example, are widely used by non-programmers to perform computational tasks that would ordinarily require the knowledge and skills of a programmer. This is largely a result of the fact that spreadsheet software automatically determines the computational steps to determine a result from data dependencies, rather than requiring a human programmer to specify those steps. This is easily accomplished due to the fact that the contents of the spreadsheet can be represented as a directed acyclic graph (DAG) and the proper order of evaluation can be determined by performing a topological sort on the DAG.
Spreadsheet software employs a conventional topological sort method to determine the order of evaluation of cell formulas. While the conventional topographical sort method is guaranteed to produce correct results, the conventional topographical sort method is also inefficient in many practical use cases. The inefficiency of the conventional topographical sort method stems from the superfluous evaluation of cell formulas. The inefficiency also increases substantially in large spreadsheets (i.e., a large number of cells across a large number of sheets) with complex formulas.

Spreadsheet recalculation algorithm for directed acyclic graph processing