In a decoding/displaying device, the memory capacity or mapping to B pictures is set in consideration of a decoding waiting period, thereby avoiding the competition between a write-in operation and a read-out operation for a memory. Therefore, the decoding operation of coded picture data can be performed with no decoding waiting period.

1. Field of the Invention
The present invention relates to a decoding/displaying device for decoding and displaying coded picture data which are generated by high-efficiency coding means using interframe correlation, and particularly to a device which can perform a continuous decoding operation and is suitable for use in implementing a function of converting 16:9 signals to letter-box signals, an audio data decoding function and an OSD (On Screen Display) function.
2. Description of Related Art
The data amount of picture data has recently increased more and more. In order to reduce the transmission or recording cost, these data are compressed by high-efficiency coding means for removing redundancy, etc., and then the coded picture data are transmitted or recorded. The high-efficiency coding means is briefly described in "MPEG Video Coding" Journal of the Television Society, vol. 49, No. 4 (1995), pp.435-466, by Nakajima et al., "Fundamentals of Digital Picture Compression" written by Yasuda and Watanabe, published by Nikkei BP Publication Center (Jan. 20, 1996), pp 135.varies.200, etc. The MPEG system which is standardized in ISO/SC29/WG11 has been well known. A decoding/displaying device for MPEG streams based on the MPEG system is disclosed in Japanese Patent Application Publication (Laid-open:KOKAI) No. Hei-8-18953 and No. Hei-8-23514.
In the coding based on the MPEG system, each frame of picture data is sectioned into an I picture (Intra Picture) which is coded without using a reference picture to be referred to as a prediction value, a P-picture (Predictive Picture) which is coded by using only pictures located at the forward side in the display order as reference pictures, and a B-picture (Bi-directional Picture) which is coded by using pictures located at the forward and rearward sides in the display order as reference pictures. In the actual coding operation, two reference pictures located at the forward and rearward sides must exist in the decoding operation of the B-picture, and the coding is performed after the pictures are skillfully rearranged (the order of the pictures is changed). Therefore, as shown in FIG. 15, it is necessary to decode the coded picture data (hereinafter a data stream containing coded picture data is referred to as "an MPEG stream") and then rearrange the data (i.e., arrange the data in a difference sequence) for display.
Therefore, in the decoding/displaying device, coded pictures which are transmitted in the coding order are successively decoded. However, the decoded data are temporarily stored in a memory and then rearranged so as to be in the display order. The decoded data of I and P pictures are required to be used as reference data for the subsequent decoding of B pictures, and thus it is necessary to store the picture data of two pictures in the memory. Further, in the case where one frame comprises two interlaced fields like television signals, even B pictures cannot be displayed simultaneously with the decoding operation thereof because one frame is coded as one picture. The frame data must be converted to field data, and thus the display operation must be delayed from the decoding operation by at least 0.5 frame period as shown in FIG. 15. Therefore, the decoded data are required to be temporarily stored in the memory to convert the frame data to the field data, and in order to satisfy this requirement, an extra memory area corresponding to one picture (=frame) is needed.
FIG. 14 is a diagram showing a memory which is required for the decoding of coded picture according to the MPEG system. The memory shown in FIG. 14 has a data width of 16 bits and a 16-Mbit memory capacity of 512 columns.times.2048 rows. One row corresponds to 1 Kbyte (=1024 bytes). The 16-Mbit capacity memory is used as a general memory chip in various fields, and the fabrication of a decoding/displaying device within the memory capacity range of 16 Mbytes is significant in cost.
The NTSC system of 720 horizontal pixels.times.480 vertical scan lines.times.the frame frequency of 30 Hz, and the PAL system of 720 horizontal pixels.times.576 vertical scan lines.times.the frame frequency of 25 Hz are used for picture signals to be compressed according to the MPEG system. FIG. 14 also shows a memory area sectioning style when the coded picture data corresponding to the PAL system having a large picture size are decoded. In the PAL system, 405 rows for brightness signals and 203 rows for color signals (the fractional portion is rounded up), a total of 608 rows, are needed for one frame, and the residual portion corresponding to three frames is used as a coded picture data buffer for temporarily storing the coded picture during the decoding operation. The capacity of the coded picture data buffer is equal to 1,835,008 bits (224 rows). This capacity value is the absolute minimum capacity which must always be maintained to ensure the optimum coding/decoding operation even in combination with a coding device and a decoding/displaying device which are manufactured by different makers, and it is determined according to the MPEG system.
FIG. 13 shows a conventional decoding/displaying device for coded picture data. In FIG. 13, reference numeral 1 represents a timing/operation mode control circuit, reference numeral 2 represents a parser/variable-length decoding circuit of MPEG streams, reference numeral 3 represents an inverse quantization/IDCT (Inverse Cosine Transform) circuit, reference numeral 4 represents a motion compensation circuit, reference numeral 5 represents a display circuit, reference numeral 6 represents a coded picture data write-in control circuit, reference numeral 7 represents a coded picture data read-out control circuit, reference numeral 8 represents a reference data readout control circuit, reference numeral 9 represents a decoded data write-in control circuit, reference numeral 10 represents a display picture data read-out control circuit, and reference numeral 11 represents a memory.
An MPEG stream is input to the parser/variable-length decoding circuit 2, and coded picture data are stored through the coded picture data write-in control circuit 6 into a coded picture data buffer area of the memory 11. The timing/operation mode control circuit 1 has not only a function of setting an operation mode, etc. for each block, but also a function of adjusting competition of data buses of the memory 11. The coded picture data read-out control circuit 7 reads out the coded picture data stored in the coded picture data buffer area in a stored order at a rate of approximately one picture (=frame) per frame period in synchronism with a synchronous signal of a display system.
The coded picture data which are read out from the memory 11 through the coded picture data read-out control circuit 7 are input into the parser/variable-length decoding circuit 2 again. The parser portion of the parser/variable-length decoding circuit 2 extracts system header information of the MPEG stream and coded mode information in a header portion of the coded picture data, and the information thus extracted is used in an internal variable-length decoding portion. In addition, the parser portion outputs the information to the timing/operation mode control circuit 1 to set the operation mode of each of the inverse quantization/IDCT circuit 3, the motion compensation circuit 4, and the display circuit 5. The variable-length decoding portion of the parser/variable-length decoding circuit 2 mainly decodes the coefficient data, etc. of the cosine transformation which have been subjected to the variable-length coding, and transmits the data thus decoded to the inverse quantization/IDCT circuit 3. Further, the inverse quantization/IDCT circuit 3 returns the coefficient data to a suitable scale in an inverse quantization portion, and converts the data to picture data in an IDCT portion.
The motion compensation circuit 4 reads out from the memory 11, through the reference data read-out control circuit 8, reference data (the decoded data of reference pictures) for motion compensation by using motion vector information in the coded mode information which is obtained by the parser/variable-length decoding circuit 2. The reference data are added to the picture data which are generated in the inverse quantization/IDCT circuit 3 to obtain decoded data. The decoded data are written into the memory 11 through the decoded data write-in control circuit 9. However, when the decoded data are the picture data of the I or P picture, one of the two reference picture areas of the memory in which older reference data are stored is updated. When the decoded data are the picture data of the B picture, the data are written into the B picture area.
The decoded data which are decoded and written into the memory 11 as described above are read out as display data by using the display data read-out control circuit 10, and transmitted to the display circuit 5. The display circuit 5 outputs the display data read out as decoded picture data from the memory 11 in synchronism with a synchronous display signal.
The operation of the conventional device will be described on the basis of the write-in and read-out operations of picture data of the above-described three pictures into the memory area (hereinafter referred to as "frame memory") with reference to FIG. 17.
In the MPEG system, there have been known a coding case in which the coding is performed in the order of I1, B2, B3, P4, B5, B6, P7, . . . (numeral represents the display order) and a coding case in which the coding is performed with only I and P frames in the order of I1, P2, P3, P4, . . . However, an irregular arrangement pattern which does not conform to the regular order as described above is also permitted. FIG. 7 shows such an irregular arrangement pattern.
As shown in (e) of FIG. 17, each frame is assumed to be coded in the display order of I1, B2, B3, P4, P5, P6, . . . Further, in FIG. 17, the decoding operation of writing the decoded picture data into each frame memory (hereinafter referred to as FM1, FM2, FM3) is shown as being performed twice.
Each frame memory FM1, FM2, FM3 is illustrated as being divided into memory images of two field memories M1, M2 at the upper and lower sides. The upper half M1 corresponds to a field memory for a first field, and the lower half M2 corresponds to a field memory for a second field. A memory image in which the address is increased in the raster scanning order from the upper side to the lower side in the direction of arrows is shown for each of the field memories M1, M2.
The frame memories FM1, FM2 are used as frame memories for reference pictures, and the frame memory FM3 is used as a frame memory for B pictures. The arrows which are directed downwardly from (a) of FIG. 17 to (b), (c) or (d) of FIG. 17 indicate decoding and writing operations, the arrows which are directed upwardly from (b), (c) or (d) of FIG. 17 to (a) of FIG. 17 indicate a reference read-out operation, and the arrows which are directed downwardly from (b), (c) or (d) of FIG. 17 to (e) of FIG. 17 indicate a display read-out operation.
In the prior art, the decoding operation is progressed on a macro block basis according to a fixed time slot, and three types of memory accesses occur during the progress of the decoding operation. The decoding and writing operation is performed to write decoded picture data which are decoded on a macro block basis. The writing progress in the decoding and writing operation is not continuous, but discontinuity of addresses occurs during the progress. However, in the decoding and writing operation over one frame, the writing address is gradually increased. In (b), (c) and (d) of FIG. 17, dense crosshatched lines each having a broad width (for example, line 1 in (b) of FIG. 17) indicates the writing progress in the decoding and writing operation.
The reference read-out operation is performed to read out the decoded picture data of a reference frame as reference picture data on a macro block basis when the P frame and the B frame are decoded. The reading progress in the reference read-out operation is the same as the decoding and writing operation. In (b) and (c) of FIG. 17, thin crosshatched lines each having a broad width (for example, line 2 in (b) of FIG. 17) indicate the reading progress in the reference reading operation. A positive or negative offset value is added to the read-out address in accordance with the value of the motion vector indicating the shift amount of the macro block, and thus the width is generally broader than in the case of the decoding and writing operation.
The display read-out operation is performed to read out the decoded picture data which are held in the frame memory. The reading progress in the display read-out operation is continuous. However, the display read-out operation is temporarily stopped during a vertical blanking period between first and second fields. In (b), (c) and (d) of FIG. 17, a bold solid line (for example, line (3) in (b) of FIG. 17) indicates the reading progress of the display and read-out operation.
First, in a period T1 (one frame period), when an I1 frame is decoded, the respective data of the two fields of the decoded I1 frame are simultaneously written into the different field memories M1 and M2 of the frame memory FM1 as shown in (b) of FIG. 17 (decoding and writing operation 1).
In a next period T2 (one frame period), a P4 frame is decoded. In this case, as shown in (b) of FIG. 17, the II frame which is decoded from the frame memory FM1 is read out (reference read-out operation 2), and the P4 frame is decoded by using the read-out I1 frame as a reference frame. As shown in (c) of FIG. 17, the respective data of two fields of the decoded P4 frame are simultaneously written into the different field memories M1, M2 of the frame memory FM2.
In the last one field period of the period T2, as shown in (b) and (e) of FIG. 17, the first field of the I1 frame decoded from the upper half field memory M1 of the frame memory FM1 is read out (display read-out operation 3), and set as the first field of the I1 frame in the decoded picture data to be displayed.
In a next period T3 (one frame period), the B2 frame is decoded. In this case, as shown in (b) and (c) of FIG. 17, the I1 frame decoded from the frame memory FM1 and the P4 frame decoded from the frame memory FM2 are respectively read out, and the B2 frame is decoded by using the I1 frame and the P4 frame thus read-out as reference frames. The data of two fields of the decoded B2 frame are simultaneously written into the different field memories M1 and M2 of the frame memory FM3 as shown in (d) of FIG. 17. In this period T3, as shown in (b) and (e) of FIG. 17, the second field of the I1 frame which is decoded from the lower half field memory M2 of the frame memory FM1 are read out during the first half of period T3 (first field period), and as shown in (d) and (e) of FIG. 17, the first field of the B2 frame which is decoded from the upper half field memory M1 of the frame memory FM3 is read out during the last half of period T3 (second field period). These fields thus read out are set as the second field of the I1 frame and the first field of the B2 frame respectively in the decoded picture data to be displayed.
In a next period T4 (one frame period), the B3 frame is likewise decoded, and written into the frame memory FM3 as shown in (d) of FIG. 17. At this time, the second field of the B2 frame decoded from the lower half field memory M2 of the frame memory FM3 is read out in the first half of the period T4 (first field period), and the first field of the B3 frame decoded from the upper field memory M1 of the frame memory FM3 is read out in the last half of period T4 (second field period). These fields are set as the second field of the B2 frame and the first field of the B3 frame respectively in the decoded picture data to be displayed.
In a next period T5 (one frame period), the P5 frame is decoded. In this case, as shown in (c) of FIG. 17, the P4 frame decoded from the frame memory FM2 is read out, and the PS frame is decoded by using the P4 frame as a reference frame. The data of the two fields of the decoded P5 frame are simultaneously written into the field memories M1, M2 of the frame memory FM1 as show in (b) of FIG. 17. In the first half of the period T5, the second field of the B3 frame decoded from the lower half field memory M2 of the frame memory FM3 is read out as shown in (d) and (e) of FIG. 17, and in the last half of the period T5, the first field of the P4 frame decoded from the upper half field memory M1 of the frame memory FM2 is read out as shown in (c) and (e) of FIG. 17. These fields are set as the second field of the B3 frame and the first field of the P4 frame respectively in the decoded picture data to be displayed.
In a next period T6 (one frame period), the P6 frame is decoded. The P5 frame written into the frame memory FM1 is used as a reference frame for the P6 frame. In this case, the P5 and P6 frames correspond to the I1 and P4 frames respectively, and the same decoding processing as the I1 and P4 are performed on the P5 and P6 frames. Further, the decoding of an I or P frame subsequent to the above frames is performed by using the decoded P6 frame as a reference frame.
As described above, the frame decoding order as shown in (a) of FIG. 17 is converted to a frame display order which is suitable for the display as shown in (e) of FIG. 17.
FIG. 16 relates to the case where the B frames are sequential in the decoding/displaying processing, and shows the motion of the memory address of the frame memory FM3 for B frames. In FIG. 16, the memory address increases upwardly with the time lapse as indicated by arrows (this is just inverse to FIG. 17). The most minute grid on the ordinate axis in FIG. 16 corresponds to the block size for coding (8 lines in field). In FIG. 16, the number of blocks in one frame is not accurately illustrated. As shown in FIG. 16, the read-out of the display data is performed by reading out the data while successively incrementing the addresses of areas which are exclusively allocated to the respective fields in correspondence to the display period of each field. On the other hand, the write-in operation of the decoded data is performed over two fields and with an address width corresponding to the width of a block as indicated by a rectangle, because the coding is performed on a two-dimensional block basis after two fields are integrated into one picture (=frame). Further, the decoding operation is stopped (suspended) for a period containing a vertical blanking period at the switch point between the pictures in order to avoid competition between the read-out address and the write-in address in which the read-out address outpaces the write-in address.

Decoding/displaying device for decoding/displaying coded picture data generated by high efficiency coding for interlace scanning picture format


The invention relates to an improved method for operating a phase-controlled group antenna as well as an associated phase shifter assembly and a phase-controlled group antenna, characterized by, inter alia, the following features: the phase shifter assembly is designed such that at least one of the following two conditions is met: RN: R1≧n+k ud/or PhN: Ph1≧n+k, where RN is the largest radius, and R1 is the smallest radius of a conductor segment (11) relative to the phase shifter assembly (7), where k is a value of 0.2 and particularly 0.25, 0.30, or preferably 0.40.

Phase-controlled group antennas are known, for example, from mobile communications technology.
Mobile communications antennas are normally used for base stations and consist of one or more columns arranged side by side, in each of which a plurality of radiators or sub-groups of radiators are arranged above one another. The radiators may be single polarised or dual polarised radiators. The antennas may be formed as mono-band, dual-band or as multi-band antennas which comprise radiators which can transmit and receive in a plurality of frequencies or frequency ranges (frequency bands). In terms of the structure of such group antennas as well as radiators and radiator arrangements, reference is made in this regard to previously known solutions, for example to prior publications WO 00/39894 A1, DE 197 22 742 A1, DE 198 23 749 A1, DE 101 50 150 A1 or, for example, U.S. Pat. No. 5,710,569.
Since, in a mobile communications system, the number of available channels is limited, the same frequencies are used again at specific distances. The range of a base station, defining a "mobile communications cell", is therefore to be limited so that the cells of the mobile communications system do not disturb one another, that is to say are not subject to interferences.
It is therefore known to set the group antennas for such base stations with a different downtilt angle depending on requirements.
Whilst in the early days of mobile communications technology this downtilt angle could be set in different ways by mechanical measures, systems are now preferred in which, for example, a different downtilt angle can be set remotely and, depending on requirements and traffic level, can also be changed constantly.
On this basis phase shifters and, more precisely, phase shifter systems are preferably used to control the individual radiators using different phase positions, whereby a different downtilt angle can be set electrically.
For example, it is thus known to use differential phase shifters, as are known in principle from EP 1 208 614 B1. An odd number of radiators or sub-groups of radiators can be controlled by such a single phase or multi-phase shifter, wherein a central radiator or a central radiator group is preferably fed directly without phase shift. For example, two radiators or radiator groups can be controlled at the outputs thereof by a differential phase shifter with different phase shift. If, in each case, two further radiators or sub-groups of radiators are to be controlled, again with increased propagation-time changes and therefore with different phase positions, a further single phase shifter is required in each case, or a multi-phase shifter is used, as proposed in accordance with EP 1 208 614 B1.
Instead of group antennas, which comprise at least one radiator or a radiator group and which are operated without phase shift, group antennas which comprise an even number of radiators or radiator groups and/or do not comprise a radiator group and are operated without phase shift are also considered in principle.
The use of a single phase shifter to control sub-groups of radiators can be inferred, for example, from U.S. Pat. No. 5,917,455 A.
WO 03/019723 A1 describes an adjustable antenna feed network comprising a phase shifter means which is constructed in such a way that identical phase differences can be generated at the ports leading to the radiators by a movable dielectric.
WO 02/35651 A1 also describes the use of phase shifters in which a dielectric is moved along a stripline. The shift path is always the same. However, since the effective dielectricity numbers are different, phase shifts which each have the same phase differences from one another can be performed at the radiator ports. A substantially straight wave front with a different downtilt angle can thus be produced.
The corresponding phase shifter elements which can be used with the same objective as explained above are also to be inferred as being known in principle from WO 96/37922 A1.
Lastly, an antenna arrangement for lowering a downtilt angle or for setting the direction of radiation of the primary beam in the azimuth direction is also to be inferred as being known from US 2005/0219133 A1. In this prior publication an antenna arrangement comprising a phase shifter assembly with use of differential phase shifters is described, wherein the outputs of a first phase shifter arrangement are connected to the inputs of a respective second phase shifter assembly in order to thus control the radiator elements. A further possibility of a phase shifter network according to the prior art is also described in this prior publication and comprises a phase shifter assembly which includes two circular-segment-shaped phase shifter line portions which are arranged concentrically and are fed by a common feed arm which can be pivoted in a pointer-shaped manner about a common centre point.
By contrast, as an improved variant the prior publication cited above suggests using phase shifters, the two outputs of each of which are directly connected to radiator elements. In other words, a single-stage construction is thus used which is provided a number of times for two radiator elements in each case. For an antenna arrangement comprising a plurality of radiators which are to be fed with different phases, different phase shifters are therefore used in each case and are controlled by means of a transmission drive in such a way that different phase delays can be set for the individual radiator elements or radiator groups. A specific ratio between the pivoting of the phase shifters, for example of 1:3, 1:3:5, 1:3:5:7 and so on, to achieve a correspondingly fixed predetermined phase delay value is to be maintained in accordance with the number of phase shifters used and the arrangement of the radiators. Tolerances of +/−5% are acceptable. In order to optimise a radiation pattern, for example in the form of secondary lobes, it may be desirable in an alternative embodiment to vary the aforementioned ratios.
However, the correspondingly different adjustment of a downtilt angle in order to change the size of a corresponding mobile communications cell does not always lead to the desired success since the secondary lobes are nevertheless also shifted by the tilting (downtilt) of the primary radiation lobe. For example, the situation may arise that the first secondary lobe above the primary beam direction arrives in the vicinity of the horizontal plane (or even therebeneath) with increasing tilting of the main beam direction, with the result that mobile communications devices and base stations then act as interferers from another coverage area. A low secondary lobe level would thus be desirable.
On the other hand, however, the antenna gain is also to be as high as possible so as to guide the available transmission power effectively to the desired coverage area. A high antenna gain means a high bundling of the energy. In terms of the feed of group antennas, it is known however from the specialist literature that the optimisation of the antenna gain is often accompanied by an increase in the secondary lobe level.
The object of the present invention is therefore to provide an improved method for operating a phase-controlled group antenna as well as an improved phase-controlled group antenna itself, in which the first secondary lobe above or adjacent to the primary lobe has the lowest possible level, in particular with substantial beam tilt (large downtilt angle) or large beam pivoting (in order to suppress interference) and/or generally has a maximum antenna gain with slight beam tilt (that is to say with large cell expansion and illumination) or with slight beam pivoting.
It is highly surprising that, within the scope of the invention, the aforementioned objectives can be achieved by relatively simple means which are almost mutually exclusive. A tilting of the level of the first secondary lobe above the primary lobe with a considerably lowered downtilt angle often results in the antenna gain not being of the desired magnitude with a less pronounced adjustment of the tilting angle of the antenna gain or, conversely, in the level of the first secondary lobe above the primary lobe proving to be too great when optimising the antenna gain when tilting the primary lobe of the radiation diagram of the antenna (lowering the downtilt angle).
With the beam shaping by electronic means, the radiation diagram could now be changed in a relatively versatile manner, more specifically with free selection of the amplitudes and the phases. However, in particular in base station antennas for a mobile communications system, efficiency and price may be key factors. For this reason, mechanical phase shifters are generally often used for such antenna systems to adjust the downtilt angle differently. These mechanical phase shifters can directly extend the line length in a feed line ("Posaunen" principle, in which the entire line path can be reduced or increased by moving a line path). It is also possible to change the diffusion rate of the electromagnetic wave over a line path, for example by inserting a dielectric material in the region of the line path and thus changing the electrical conditions, or else a movable or displaceable coupling point can be used which can be displaced along a fixed line so as to shift the point of engagement. The possibilities for jointly changing the individual signals are considerably limited in this case, however.
Within the scope of the present invention a path is proposed which nevertheless offers the possibility of obtaining a much improved result in terms of solving the stated problem with minimal effort.
The principle of the invention is based on the fact that the radiators or radiator sub-groups arranged farthest away in a group antenna (for example in a group antenna the uppermost and lowermost radiators or radiator sub-groups) or controlled with the greatest phase difference are subjected to an additional phase shift, in other words are controlled by a disproportionately high phase shift in contrast to conventional systems.
In accordance with the invention, this does not occur with an additional means for generating an additional shift, but instead a correspondingly disproportionate phase shift with an additional phase shift proportion is generated by the same phase shifter which is also otherwise responsible in principle for beam pivoting.
Alternatively and in addition, in contrast to conventional systems, it is also possible to operate the radiators or radiator sub-groups which are arranged in a group antenna in the central region most densely in relation to one another (controlled by a differently adjustable phase position) using a disproportionately low phase shift with adjustment of a downtilt angle or an amended beam angle so that, in particular, the ratio of the phase position between the radiators operated with the greatest phase shift to the radiators operated with the lowest phase position change is characterised by a disproportionately large value.
This can be achieved when using a multiple differential phase shifter, as is known in principle for example from EP 1 208 614 B1, in that the outermost stripline, generally shaped in the arc of a circle, for feeding the farthest radiator or radiator sub-group lies further away from the concentric centre of a correspondingly pivotable, pointer-shaped tapping element and/or lies closer to the feedline centre, that is to say the pivot axis of the feedline arm at the next, arc-shaped stripline of this pivot axis.
In essence, this principle applies to an antenna system having an even or odd number of radiators and/or radiator sub-groups. An antenna system having an odd number of radiators or radiator groups is a system in which at least one radiator or at least one radiator group is provided which is fed with a bypassing of a differently adjustable phase shift system without changeable phase shift (normally arranged in the central region of the group antenna) so that no phase change is experienced at this radiator or this radiator group when the primary beam direction is pivoted (different adjustment of the downtilt angle).
An even radiator system is a system in which a group antenna having an even number of radiators or radiator sub-groups is provided (or, naturally, in this case a mixed system thereof) which are fed via the phase shift system, that is to say in particular do not comprise a central system which is controlled without phase shift.
In a supplementary or alternative embodiment of the invention it is also possible to position the pivot axis of the generally pointer-shaped, pivotable phase shift adjustment element closer to the striplines shaped as a segment or arc of a circle so that this pivot axis lies closer to the striplines than the centre point of the circular-segment-shaped striplines. As a result, a disproportionately large change in propagation time is generated by the farthest circular-segment-shaped stripline portion at the opposing connection points, and the phase shift change and therefore the propagation time change is reduced proportionately at the innermost circular-segment-shaped stripline portions, whereby the success according to the invention is achieved.
In particular, the invention is specifically based on the fact that at least one radiator or at least two pairs of radiators or radiator sub-groups fed via a differential phase shift are operated with an additional phase shift compared to the other radiators or radiator sub-groups in terms of the transmitting or receiving signal, which has a positive effect on an additional beam shaping within the meaning of the invention. The contribution of the additional phase shift is dependent on the adjustment of the beam pivoting. Owing to the fact that the most simple additional beam deformation is to be achieved, it is ensured that the size of the secondary lobe located above the primary lobe is smaller in the tilted state with increasingly advanced tilting of the primary lobe of a group antenna compared to a system not according to the invention (interference with adjacent cells is thus avoided) and/or that the antenna gain of this primary lobe is relatively greater in the case of a primary lobe oriented in the horizontal direction (that is to say with a tilting or pivoting angle which is not so pronounced) than with conventional antenna systems.
The example non-limiting technology herein provides illustrative non-limiting advantages and features at least some of which are:                with an antenna array having an even number of radiator arrangements (1) and/or without a phase-neutrally controlled central radiator arrangement (1x), the following inequality is satisfied:PhN: Ph1≧SN:S1+0.4        with an odd number of radiator arrangements (1) and/or a phase-neutrally controlled central radiator arrangement (1x), the following inequality applies:PhN: Ph1≧SN:S1+k in which k is 0.25 or preferably 0.30 and in particular 0.40        with an even number of radiator arrangements (1) and/or without a phase-neutrally controlled central radiator arrangement (1x), the following inequality applies:PhN: Ph1≧SN:S1+k in which k is 0.5 or preferably 0.6 and in particular 0.8,        with an odd number of radiator arrangements (1) and/or a phase-neutrally controlled central radiator arrangement (1x), the following inequality applies:PhN: Ph1≧n+min which n is a natural number 2, 3, 4 . . . N, corresponding to the number of radiator arrangements (1) provided on an antenna array half above or below the centre (Z) of the antenna array, and m corresponds to 2.0 or in particular 1.5 or 1.0,        with an even number of radiator arrangements (1) and/or without a phase-neutral centre feed of a radiator arrangement (1x) close to the centre, the following inequality applies:PhN:Ph1≦2n+m in which n is a natural number 2, 3, 4 . . . N, corresponding to the number of radiator arrangements (1) provided on an antenna array half above or below the centre (Z) of the antenna array, and m corresponds to 3.0 or preferably 2.5 or preferably 2.0.
The example non-limiting technology herein provides illustrative non-limiting advantages and features some of which are:                with an antenna array having an even number of radiator arrangements (1) and/or without a phase-neutrally controlled central radiator arrangement (1x), the following inequality is satisfied:PhN: Ph1>SN:S1+0.4        the group antenna consists of an even number of radiator arrangements (1) and/or does not comprise a phase-neutrally controlled radiator arrangement (1x) provided in the region of the centre (Z) of the group antenna,        the group antenna is equipped in particular with an odd number of radiator arrangements (1) having a phase-neutrally controlled radiator arrangement (1x) arranged close to the centre or in the centre (Z) of the group antenna,        with an odd number of radiator arrangements (1) and/or a phase-neutrally controlled central radiator arrangement (1x), the following inequality is satisfied:PhN: Ph1>SN:S1+k in which k is 0.25 or preferably 0.30 and in particular 0.40,        with an even number of radiator arrangements (1) and/or without a phase-neutrally controlled central radiator arrangement (1x), the following inequality applies:PhN: Ph1>SN:S1+k in which k is 0.5 or preferably 0.6 and in particular 0.8,        with an odd number of radiator arrangements (1) and/or a phase-neutrally controlled central radiator arrangement (1x), the following inequality applies:PhN: Ph1<n+m in which n is a natural number 2, 3, 4 . . . N, corresponding to the number of radiator arrangements (1) provided on an antenna array half above or below the centre (Z) of the antenna array, and m corresponds to 2.0 or in particular 1.5 or 1.0,        with an even number of radiator arrangements (1) and/or without a phase-neutral centre feed of a radiator arrangement (1x) close to the centre, the following inequality applies:PhN: Ph1<2n+m in which n is a natural number 2, 3, 4 . . . N, corresponding to the number of radiator arrangements (1) provided on an antenna array half above or below the centre (Z) of the antenna array, and m corresponds to 3.0 or preferably 2.5 or preferably 2.0,        at least the stripline portion (11, 11a) having the largest radius (RN) is provided with a dielectric, which is not air, on one or preferably on both sides, which dielectric is provided with constant or different or varying thickness over the entire length of the stripline portion or over one or over more partial lengths.

Method for operating a phase-controlled group antenna and phase shifter assembly and an associated phase-controlled group antenna


The invention relates to a two-stage design for a water purification system, with water to be purified first passing through a first stage containing particulate filtration media, and a second stage containing a porous filtration block. The particulate filtration media can be the same as, or different from, material included in the porous block. Either material may be any material that removes contaminants from water by, e.g., absorption, adsorption, ion exchange, sequestration, or other mechanism, or any combination of these.

1. Field of the Invention
This invention relates to apparatus and systems for efficient and effective purification of water to provide improved pressure drop characteristics and capacity as compared to purification systems using conventional carbon blocks.
2. Description of Related Art
Water filtration media containing extruded or molded carbon blocks (particles of granulated activated carbon held together formed into a desired shape and held together with a polymeric binder) have been known in the art. For instance, U.S. Pat. Nos. 5,189,092; 5,249,948; and 5,331,037 disclose carbon blocks used to purify water prepared by extruding carbon particles with a polymeric resin.
These conventional carbon blocks, while functional, present several disadvantages in use. First, the capacity of the blocks is limited by the kinetics of adsorption onto the carbon surfaces and into the pores of the bound carbon particles. Because so much of the surface area of the carbon particles is occluded by binder resin, the capacity of filters of reasonable size and number to treat water is rather limited in terms of volumetric flow rate. In addition, the total volume of water treated is limited because of clogging of the filter due to the presence of small particulates and other detritus in the water being filtered, as well as because of the saturation of the limited number of active sites on the carbon particulate.
Second, both the volumetric flow rate and the total volume of water treated can be limited by the structural integrity of the carbon block. Many conventional carbon blocks degrade over a fairly short period of time as the flow of water erodes them, breaking them into smaller blocks that can move around in the flow system and cause clogging.
Third, carbon blocks, in particular extruded carbon blocks, can be difficult to manufacture with high consistency, leading to unpredictable performance results. The binder resins must be heated, either directly or by shear in an extruder, which can passivate some of the carbon, rendering the blocks less effective.
Fourth, existing carbon block formulations are not particularly effective at removing chloramines, rendering them less than desirable for use in water purification systems used in the food processing industry. In particular, catalytic carbonaceous chars can be used for chloramine removal, as disclosed in U.S. Pat. No. 6,342,129, the entire contents of which are incorporated herein by reference. However, the inventor has found that including this material in a carbon block results in a substantial amount of deactivation of the catalytic activity of the carbon, believed to result from the need to heat the binder resin to form the carbon block.
Moreover, chloramine reduction is very complex to achieve by carbon block filters made from regular granulated activated carbon, be it molded or extruded, etc. For example, extruded carbon block can remove chlorine with one pound of highly activated coconut shell carbon at a flow rate of approximately 2 gpm with 80×325 mesh carbon particles and 15% polymeric binder for approximately 7,000 gallons to meet NSF Standard 42 at 2 ppm influent chlorine and 0.5 ppm effluent. Where the same filter needs to reduce chloramine at 2 ppm, its capacity is barely 200 gallons at the same flow rate.
Special catalytic carbons have been developed to remove chloramine, but when they have been molded or extruded into carbon block, they lose 90% of their efficiency for chloramines removal. Different carbons have different adsorption capacities; however, coconut shell carbon, coal based carbon and other nut-derivative materials all demonstrate a ratio of 20:1 or 30:1 capacity between their ability to remove chlorine and their ability to reduce chloramine.
Water pH is also a factor in the effectiveness of the chloramines removal media. The pH of chloramine in water is extremely high, generally between about 8.5 and about 9.6. At this pH level, most carbon loses its removal efficiency quite rapidly, if not immediately. Since a water filter requires a minimum amount of water flow to function effectively and economically, the size of the filter becomes critical. With regular carbon, to achieve chloramine reduction at the same capacity as chlorine with the same filter, a sufficiently long contact time is needed such that the filter must be about 10 to about 20 times larger than is necessary if only chlorine is to be removed.
Carbon block filtration results in other disadvantages as well. It is often difficult to prepare carbon blocks with adequate control over the particle size of the particulate carbon used to make the blocks. This can result in the use of carbon containing significant quantities of dust, which can migrate through the carbon block, clog pores, and create unduly large pressure drops through the block, which can block as much as 50% to 90% of the rated flow rate through the filter block. Plugging of the filter also creates inconsistencies in water flow. Carbon made from coconut shell, in particular, can swell in the presence of VOC, further constricting fluid flow and increasing pressure drop.
An alternative to carbon block technology is the use of granulated carbon and other filtration media, generally having a particle size distribution ranging from about 50 mesh to about 28 mesh, in a canister through which the water to be purified flows. Again, while this arrangement is functional, particularly when coupled with a downstream carbon block purification step, the capacity of the system is generally limited to around 6,000 to 7,000 gallons.
Accordingly, there remains a need in the art for a water purification apparatus and system that does not suffer from the disadvantages of carbon block based systems, that can purify water at high capacity, and that can be adapted to effectively remove chloramines from water. In addition, there remains a need for an essentially modular system, which provides effective water purification through the use of a single cartridge, yet which provides sufficient flexibility in manufacture that different filtration media can be used without multiplying the inventory of parts needed to produce the system.


A portable computer enclosure includes a main body, a cover body pivotably attached to the main body, and an outer plate detachably attached to the cover body for covering an outer surface of the cover body opposite to the main body. The cover body defines at least one opening therein, and the outer plate forms at least one latch detachably engaging in the at least one opening in the cover body.

1. Field of the Invention
The present invention relates to portable computers, and more particularly to a portable computer with a replaceable enclosure.
2. Description of Related Art
Along with rapid development of electronic technology, performance of computers is enhanced day by day. A new computer can quickly become out-of-date. In order to keep up with technology, computers should be upgraded frequently.
To upgrade a computer means to change some internal components of the computer and thus enhance the performance of the computer. Upgrades help prolong the useful life of a computer. However, the appearance of the computer is usually not upgraded and will appear 'old-fashioned' to users when compared with the latest computers on the market. It is a waste to replace a computer only because of its appearance.
Accordingly, a need exists for a portable computer with a replaceable casing to resolve the above mentioned problem.

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


In a coffee extracting apparatus in which coffee essence is extracted from coffee powder (200) in a container (51), an air feeding arrangement (43) is provided for feeding pressed air into the container. After the coffee essence is extracted from coffee powder, coffee grounds (200') are remained in the container. It is assumed that the coffee grounds are adhered to an inner surface of the container. In order to expel the coffee grounds from the container, the air feeding arrangement is controlled so that the pressed air is fed into the container after extracting the coffee essence from the coffee powder.

This invention relates to a coffee extracting apparatus and a method for extracting coffee essence from coffee material or powder.
An apparatus for extracting coffee essence from coffee powder by means of percolation has been in popular use to date. Such a percolating type coffee extracting apparatus comprises an extracting container for receiving coffee powder herein and a hot water feeding device for feeding hot water into the container. When the hot water is fed into the container, the coffee essence is extracted from the coffee powder in the container in the manner known in the art. A mixture of the coffee essence and the hot water is discharged as a liquid coffee extract from the container. After the liquid coffee extract is discharged from the container, coffee grounds are remained in the container. In order to expel the coffee grounds, the container is exposed to a shock or is shaken in a conventional percolating type coffee extracting apparatus.
However, the conventional percolating type coffee extracting apparatus has such problems as emitting noise when the container is caused to expel the coffee grounds by being exposed to the shock or being shaken. In addition, it is assumed that the coffee grounds are remained adhering to an inner surface of the container even after the container is exposed to the shock or is shaken.

Coffee extracting apparatus and method in which coffee grounds are expelled from an extracting container by pressed air


A method and apparatus for collecting and evaluating powered vehicle operation utilizing on-board diagnostic components and location determining components or systems. The invention creates one or more databases whereby identifiable behavior or evaluative characteristics can be analyzed or categorized. The evaluation can include predicting likely future events. The database can be correlated or evaluated with other databases for a wide variety of uses.

1. Field of Use
The invention pertains to a method and apparatus for evaluating recorded data of a driver's operation of a motor vehicle. The invention is not limited to trucks and automobiles but includes all powered equipment such as boats, airplanes and railroads. The invention utilizes time marked data that can be correlated with information from separate databases, particularly data that is also time marked. The recorded data may facilitate the vehicle owner monitoring the use of the vehicle by others, e.g., employees, automobile renters or family members, e.g., teenage drivers. The recorded data may also provide an objective behavioral data collection system for third parties, e.g., life and health insurance companies, lending institutions, credit rating companies, product and service marketing companies, potential employers, to evaluate an individual's behavioral characteristics in a real life and commonly experienced situation, i.e., driving a motor vehicle.
2. Prior Art
Several commercial mechanisms are available on the market that provide means to monitor vehicle use. One example is the Alltrackusa product that relies on a global positioning satellite (GPS) system to track vehicle operation. Such systems employ a calculating methodology to determine speed and acceleration by using the position differential implied by the GPS. Conversely, Davis Technologies markets the CarChip product which is a passive OBD data recorder for hobbyists and car enthusiasts who want to record their engine performance. The shortcomings of the Alltrackusa "GPS only" application is that actual speed information is not available during intermittent losses of the GPS signal, which are frequent. This limits the product's usefulness for creating a complete dataset suitable for developing a useful and objective driver safety ratings. The shortcoming of the CarChip product is that the unit does not provide GPS capability and the target market is for car enthusiasts who want to monitor engine diagnostics. Both existing technology developments have the inherent shortcoming of local data storage and reporting. This feature limits the usefulness of the data and does not allow for the development of an independent rating system.
U.S. Pat. No. 6,064,970, assigned to Progressive Casualty Insurance Company, discloses a method and system for determining the cost of automobile insurance based upon monitoring, recording and communicating data representative of operator and vehicle driving characteristics. The system includes use of a wireless up-link to a central control station to communicate "triggering events".
U.S. Pat. No. 6,064,970 defines a methodology for private insurance quotes based on endogenous driver variables that are acquired from the customer or collected by the insurance company. U.S. Pat. No. 6,064,970 does not teach an apparatus and business process that allows customers to voluntarily create datasets that are then objectively interpreted by a third party and converted to objective safety ratings, much as credit payments or delinquencies are converted to an objective credit rating, or company debt histories converted to a bond rating. This distinction is vital in order to promote the adoption of driver monitoring technology and guarantee that it is utilized in a manner that promotes the most societal good, rather than simply being the exclusive purview of one company's insurance premium pricing structure.
Other devices and methods are disclosed in published patent applications. Included is the application Ser. No. 10/764,076 assigned to Progressive Casualty Insurance Company filed Jan. 23, 2004. Another device is disclosed in a published application Ser. No. 10/281,330 assigned to Davis Instruments, and filed Oct. 25, 2003.
The existing systems and devices also ignore the profound behavioral characteristics exhibited by drivers in operating motor vehicles, e.g., aggressiveness or patience, caution or recklessness, compliance with laws, etc. These characteristics are relevant to each individual's behavior in other situations including performance of job duties, behavior in stress, and meeting obligations owed to others. These behaviors cannot be ascertained unless the information is uploaded to a central server to create a comprehensive database for comparison and development of useful profiles. Existing technology applications do not centrally store the data and interpret it in context to provide a useful service to society.

Motor vehicle operating data collection and analysis


A latch assembly has a casing, a housing, a latch bolt, a slide, a connecting member, a lever holder, a lever and an adjusting pin. A slot is longitudinally defined in the housing. Two detents are respectively defined in opposite ends of the slot. The slide is connected to the fixed member with the connecting member that engages one of the notches in the fixed member. A notch is defined in the bottom of the slide. A biasing member is arranged between the slide and the connecting member to provide a biasing force to the connecting member to engage the fixed member. The adjusting pin extends through one of the detents, aligns with the notch in the slide and abuts the bottom of the connecting member. With such an arrangement, only one hand is needed to adjust the latch assembly.

1. Field of the Invention
The present invention relates to a latch assembly, and more particularly to an adjustable latch assembly that can be used for different types of locks and can be adjusted easily.
2. Description of Related Art
With reference to FIG. 7, a conventional latch assembly in accordance with the prior art comprises a casing (80), a latch bolt (81), a housing, a fixed plate (83), a connecting member (84), a lever holder (85), a lever (86) and an adjusting member (88). The latch bolt (81) is retractably received in the casing (80). The housing is securely attached to the casing and is composed of two half-housings (82, 822). The fixed plate (83) is mounted in the housing and is attached to the latch bolt (81). Two notches (832, 834) are defined in the top of the fixed plate (83). The connecting member (84) is slidably mounted on the fixed plate (83). A protrusion (842) is formed on the bottom of the connecting member (84) to selectively engage with one of the notches (832, 834) in the fixed plate (83). A first resilient member (844) is connected between the fixed plate (83) and the connecting member (84) to provide a force on the connecting member (84) to press the protrusion (842) to securely engage with the corresponding notch (832, 834).
The lever holder (85) is moveably received in the housing. The lever (86) is pivotally attached to the lever holder (85). The lever (85) is connected to the connecting member (84) with a link (87). A link pin (862) is slidably mounted through the lever (86) and engages with a recess (852) defined in the lever holder (85). A second resilient member (864) is attached to the lever holder (85) and abuts the bottom of the lever (86). The adjusting member (88) has a shaft (882) extending through the lever holder (85) below the connecting member (84). An oblique face (not numbered) is formed on the top of the adjusting member (88) to abut the bottom of the connecting member (84). A third resilient member (884) is mounted between the lever holder (85) and the adjusting member (88).
When the adjusting member (88) is pushed, the connecting member (84) will be lifted up by the oblique face on the adjusting member (88). The protrusion (842) of the connecting member (84) will disengage from the corresponding notch (832, 834) in the fixed member (83), and the connecting member (84) can slide relative to the fixed member (83). The lever (86) and the lever holder (85) will simultaneously move relative to the housing with the connecting member (84). The latch assembly is adjusted to fit with different size of door or lock.
However, the conventional latch assembly is very complex. To manufacture or assemble the conventional latch assembly is difficult. The cost for manufacturing the conventional latch assembly is expensive. In addition, the conventional latch assembly needs three resilient members (844, 864,884) to assist the actions of the connecting member (84), the lever (86) and the adjusting member (88). When one of the resilient members (844, 864, 884) loses its resilience, the latch assembly cannot operate properly and must be repaired or replaced. Furthermore, the retraction of the latch bolt (81) relative to the casing (80) is actuated by rotating the lever (86), which moves the link (87), the connecting member (84) and the fixed member (83). However, because the link (87) is pivotally connected between the connecting member (84) and the lever (86), there could be two dead points at the transmission mechanism arranged between the connecting member (84) and the lever (86).
With reference to FIG. 8, another conventional latch assembly in accordance with the prior art comprises a casing (90), a latch bolt (91), a housing (92), a fixed member (93), a connecting member (94), a slide (97), a lever holder (95), a lever (96) and an adjusting pin (98). The latch bolt (91) is retractably received in the casing (90). The housing (92) is securely attached to the casing (90). The fixed member (93) is received in the housing (92) and is connected to the latch bolt (91). The slide (97) is slidably mounted in the housing (92). A slot (972) is laterally defined in the slide (97). Two detents (974) are respectively defined in two ends of the slot (972). The connecting member (94) is pivotally attached to the fixed member (93). An engaging pin (942) is connected to the free end of the connecting member (94) to be selectively received in one of the detents (974) in the slot (972). A first resilient member (944) is arranged between the fixed member (93) and the connecting member (94) to provide a force on the connecting member (94) to press the engaging pin (942) to securely engage with the corresponding detent (974).
The lever holder (95) is moveably received in the housing (92). The lever (96) is pivotally attached to the lever holder (95). The uppermost end of the lever (96) engages with a recess (976) in the slide (97). A second resilient member (962) is attached to the lever holder (95) and abuts the bottom of the lever (96). The adjusting pin (98) extends through the lever holder (95) and is located below the connecting member (94).
When the adjusting pin (94) is lifted up, the connecting member (94) will be pivoted up to disengage the pin (942) from the corresponding detent (974) in the slide (97). The slide (97), the lever holder (95) and the lever (96) can be moved relative to the housing (92) to fit a different size door or lock.
Although the structure of the conventional latch assembly shown in FIG. 8 has been simplified, the user must use two hands to adjust the conventional latch assembly, one hand to lift up the adjusting pin (98) and the other hand to pull or push the lever holder (95). To adjust the conventional latch assembly is tedious.
To overcome the shortcomings, the present invention tends to provide an improved latch assembly to mitigate or obviate the aforementioned problems.
The main objective of the invention is to provide an improved latch assembly that can be adjusted easily. The latch assembly has a casing, a housing, a latch bolt, a slide, a connecting member, a lever holder, a lever and an adjusting pin. The housing is attached to the casing. A slot is laterally defined in the housing. Two detents are respectively defined at opposite ends of the slot. The latch bolt is retractably mounted in the casing. The fixed member is securely attached to the latch bolt. The fixed member has two notches defined in the top of the fixed member and a slot laterally defined in the fixed member. The slide is slidably mounted in the housing and is connected to the fixed member with the connecting member. The connecting member is slidably mounted on the fixed member and engages with one of the notches in the fixed member. A recess is defined in the bottom of the slide. A biasing member is arranged between the slide and the connecting member to provide a biasing force on the connecting member to engage with the fixed member. The lever holder is slidably mounted in the housing. The lever is pivotally attached to the lever holder and engages with the slide with the uppermost end of the lever. The adjusting pin extends through one of the detents in the housing, aligns with the notch in the bottom of the slide and abuts the bottom of the connecting member. When the adjusting pin is disengaged from the corresponding detents in the housing, the connecting member can be pushed to disengage from the corresponding one of the notches in the fixed member and the adjusting pin will engage with the notch in the slide. The slide with the lever holder and the lever can be pushed to move relative to the housing with the hand of the user, which lifts up the adjusting pin. To adjust the latch assembly is easier.
Other objects, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.


An industrial control system includes a plurality of control devices providing control signals to direct an industrial process and a web access module including a web server, an Internet interface and a control network interface. Each of the control devices includes web page data concerning a respective web page associated with the respective control device. The Internet interface is couplable to a remote device via the Internet, and the control network interface is coupled to the control devices. The web access module is able to receive requests from the remote device to access the web pages associated with the control devices. In response to the requests, the web access module obtains the web page data concerning the web pages for which access has been requested, processes the data at the server, and sends data signals related to the data onto the Internet to be received by the remote device.

Industrial control systems used to control and monitor industrial processes often employ programmable logic controllers, which are special purpose computers that operate based upon stored control programs and typically read inputs and provide outputs to the controlled industrial processes based upon the logic of their control programs. PLCs differ from conventional computers in two major respects. First, PLCs operate to produce highly reliable and predictable control outputs. The architecture and programming of PLCs are designed so as to provide predictable maximum response times, as well as a reduction in errors caused by race conditions and sensitive detection of hardware and communication errors. Second, PLCs differ from conventional computers in that PLCs are highly customizable so as to fit the demands of the particular industrial processes being controlled.
Depending upon the particular industrial process being controlled, an industrial control system can take a variety of forms. In some circumstances, the industrial control system includes numerous I/O modules that are all in communication with a single PLC. In other circumstances, multiple PLCs are employed in the industrial control system. The multiple PLCs can be networked together, and each PLC is typically in communication with its own particular associated I/O modules. In still additional circumstances, industrial control systems can take other forms that can include, for example, other types of control devices.
Although it is the PLCs of industrial control systems that primarily govern the operation of the industrial control systems with respect to the industrial processes of interest, in a variety of circumstances it is desirable to be able to remotely monitor (and, in some instances, control) the operation of the industrial control systems and the progress of the industrial processes. Conventional industrial control systems allow for communications between PLCs and remote human machine interfaces such as computer terminals by way of proprietary communication links or dedicated phone lines.
However, recently a new communications medium known as the Internet or World Wide Web (or simply the "web") has emerged as an important if not dominant communications medium for networking among computers and computer systems around the world. Given the ubiquity and simplicity of using the web, it has become desirable that industrial control systems be capable of communications with remote computer terminals or other remote devices by way of the web.
Yet conventional industrial control systems are not readily configured for web communications. On the one hand, the control devices commonly implemented within industrial control systems typically do not have the large amounts of memory and processing powers that are necessary for implementation of web server programs/applications. On the other hand, implementation of a single web server program for an entire industrial control system can impose significant programming burdens, particularly when the operation or configuration of the individual control devices is frequently changing. In practice, implementation of a single web server for an entire industrial control system can render it difficult to provide sufficient independent accessibility of the individual control devices of the industrial control system
It would therefore be advantageous if a new industrial control system could be developed that allowed remote computer terminals and other remote devices to communicate with individual control devices of the industrial control system by way of the web. It would also be advantageous if the new industrial control system allowed web communications with the various individual PLCs, I/O modules and/or other control devices of the industrial control system despite any memory or processing power limitations of those control devices.

Proxied web access for control devices on industrial control systems


Compounds, methods of use, and processes for making inhibitors of complement Factor D are provided comprising Formula I, or a pharmaceutically acceptable salt or composition thereof. The inhibitors of Factor D described herein reduce the excessive activation of complement, and are useful to treat disorders mediated by the complement system.

An immune disorder occurs when the immune system is not performing in a normal manner. Inflammation is a protective response that involves the immune system, blood vessels, and molecular mediators. A wide variety of medical disorders are caused by detrimental immune or inflammatory responses, or the inability of a cell to respond to a normal immune or inflammatory process.
The complement system is a part of the innate immune system which does not adapt to changes over the course of the host's life, but instead is recruited and used by the adaptive immune system. For example, it assists, or complements, the ability of antibodies and phagocytic cells to clear pathogens. This sophisticated regulatory pathway allows rapid reaction to pathogenic organisms while protecting host cells from destruction. Over thirty proteins and protein fragments make up the complement system. These proteins act through opsonization (enhancing phagocytosis of antigens), chemotaxis (attracting macrophages and neutrophils), cell lysis (rupturing membranes of foreign cells) and agglutination (clustering and binding of pathogens together).
The complement system has three pathways: classical, alternative and lectin. Complement Factor D plays an early and central role in activation of the alternative pathway of the complement cascade. Activation of the alternative complement pathway is initiated by spontaneous hydrolysis of a thioester bond within C3 to produce C3(H2O), which associates with Factor B to form the C3(H2O)B complex. Complement Factor D acts to cleave Factor B within the C3(H2O)B complex to form Ba and Bb. The Bb fragment remains associated with C3(H2O) to form the alternative pathway C3 convertase C3(H2O)Bb. Additionally, C3b generated by any of the C3 convertases also associates with Factor B to form C3bB, which Factor D cleaves to generate the later stage alternative pathway C3 convertase C3bBb. This latter form of the alternative pathway C3 convertase may provide important downstream amplification within all three of the defined complement pathways, leading ultimately to the recruitment and assembly of additional factors in the complement cascade pathway, including the cleavage of C5 to C5a and C5b. C5b acts in the assembly of factors C6, C7, C8, and C9 into the membrane attack complex, which can destroy pathogenic cells by lysing the cell.
The dysfunction of or excessive activation of complement has been linked to certain autoimmune, inflammatory, and neurodegenerative diseases, as well as ischemia-reperfusion injury and cancer. For example, activation of the alternative pathway of the complement cascade contributes to the production of C3a and C5a, both potent anaphylatoxins, which also have roles in a number of inflammatory disorders. Therefore, in some instances, it is desirable to decrease the response of the complement pathway, including the alternative complement pathway. Some examples of disorders mediated by the complement pathway include age-related macular degeneration (AMD), paroxysmal nocturnal hemoglobinuria (PNH), multiple sclerosis, and rheumatoid arthritis.
Age-related macular degeneration (AMD) is a leading cause of vision loss in industrialized countries. Based on a number of genetic studies, there is evidence of the link between the complement cascade and macular degeneration. Individuals with mutations in the gene encoding complement Factor H have a fivefold increased risk of macular degeneration and individuals with mutations in other complement factor genes also have an increased risk of AMD. Individuals with mutant Factor H also have increased levels of C-reactive protein, a marker of inflammation. Without adequate functioning of Factor H, the alternative pathway of the complement cascade is overly activated leading to cellular damage. Inhibition of the alternative pathway under these circumstances is thus desired.
Paroxysmal nocturnal hemoglobinuria (PNH) is a non-malignant, hematological disorder characterized by the expansion of hematopoietic stem cells and progeny mature blood cells which are deficient in some surface proteins. PNH erythrocytes are not capable of modulating their surface complement activation, which leads to the typical hallmark of PNH—the chronic activation of complement mediated intravascular anemia. Alexion Pharmaceutical's anti-C5 antibody eculizumab (Soliris®) is currently the only complement-specific antibody on the market, and is the first and only approved treatment for paroxysmal nocturnal hemoglobinuria (PNH). Exciluzimab is also approved for atypical hemolytic uremic syndrome (aHUS). However, many of the patients treated with eculizumab remain anemic, and many patients continue to require blood transfusions. In addition, treatment with eculizumab requires life-long intravenous injections. Thus, there is an unmet need to develop novel inhibitors of the complement pathway.
Other disorders that have been linked to the complement cascade include aHUS, hemolytic uremic syndrome (HUS), abdominal aortic aneurysm, hemodialysis complications, hemolytic anemia, or hemodialysis, neuromylitis (NMO), myasthenia gravis (MG), fatty liver, nonalcoholic steatohepatitis (NASH), liver inflammation, cirrhosis, liver failure, dermatomyocitis, and amyotrophic lateral sclerosis.
Factor D is an attractive target for inhibition or regulation of the complement cascade due to its early and essential role in the alternative complement pathway, and its potential role in signal amplification within the classical and lectin complement pathways. Inhibition of Factor D effectively interrupts the pathway and attenuates the formation of the membrane attack complex.
While initial attempts have been made to develop inhibitors of Factor D, there are currently no small molecule Factor D inhibitors in clinical trials. Examples of Factor D inhibitors or prolyl compounds are described in the following disclosures.
Biocryst Pharmaceuticals U.S. Pat. No. 6,653,340 titled "Compounds useful in the complement, coagulat and kallikrein pathways and method for their preparation" describes fused bicyclic ring compounds that are potent inhibitors of Factor D. Development of the Factor D inhibitor BCX1470 was discontinued due to lack of specificity and short half-life of the compound.
Novartis PCT patent publication WO2012/093101 titled "Indole compounds or analogues thereof useful for the treatment of age-related macular degeneration" describes certain Factor D inhibitors. Additional Factor D inhibitors are described in Novartis PCT patent publications WO2014/002051, WO2014/002052, WO2014/002053, WO2014/002054, WO2014/002057, WO2014/002058, WO2014/002059, WO2014/005150, and WO2014/009833.
Bristol-Myers Squibb PCT patent publication WO2004/045518 titled "Open chain prolyl urea-related modulators of androgen receptor function" describes open chain prolyl urea and thiourea related compounds for the treatment of androgen receptor-associated conditions, such as age-related diseases, for example, sarcopenia.
Japan Tobacco Inc. PCT patent publication WO1999/048492 titled "Amide derivatives and nociceptin antagonists" describes compounds with a proline-like core and aromatic substituents connected to the proline core through amide linkages useful for the treatment of pain.
Ferring B. V. and Yamanouchi Pharmaceutical Co. lTD. PCT patent publication WO1993/020099 titled "CCK and/or gastrin receptor ligands" describes compounds with a proline-like core and heterocyclic substituents connected to the proline core through amide linkages for the treatment of, for example, gastric disorders or pain.
Alexion Pharmaceuticals PCT patent publication WO1995/029697 titled "Methods and compositions for the treatment of glomerulonephritis and other inflammatory diseases" discloses antibodies directed to C5 of the complement pathway for the treatment of glomerulonephritis and inflammatory conditions involving pathologic activation of the complement system.
On Feb. 25, 2015, Achillion Pharmaceuticals filed PCT Patent Application No. PCT/US2015/017523 and U.S. patent application Ser. No. 14/631,090 titled "Alkyne Compounds for Treatment of Complement Mediated Disorders"; PCT Patent Application No. PCT/US2015/017538 and U.S. patent application Ser. No. 14/631,233 titled "Amide Compounds for Treatment of Complement Mediated Disorders"; PCT Patent Application No. PCT/US2015/017554 and U.S. patent application Ser. No. 14/631,312 titled "Amino Compounds for Treatment of Complement Mediated Disorders"; PCT Patent Application No. PCT/US2015/017583 and U.S. patent application Ser. No. 14/631,440 titled "Carbamate, Ester, and Ketone Compounds for Treatment of Complement Mediated Disorders"; PCT Patent Application No. PCT/US2015/017593 and U.S. patent application Ser. No. 14/631,625 titled "Aryl, Heteroaryl, and Heterocyclic Compounds for Treatment of Complement Mediated Disorders"; PCT Patent Application No. PCT/US2015/017597 and U.S. patent application Ser. No. 14/631,683 titled "Ether Compounds for Treatment of Complement Mediated Disorders"; PCT Patent Application No. PCT/US2015/017600 and U.S. patent application Ser. No. 14/631,785 titled "Phosphonate Compounds for Treatment of Complement Mediated Disorders"; and PCT Patent Application No. PCT/US2015/017609 and U.S. patent application Ser. No. 14/631,828 titled "Compounds for Treatment of Complement Mediated Disorders."
Given the wide variety of medical disorders that are caused by detrimental immune or inflammatory responses, new uses and compounds are needed for medical treatment. In one aspect, new uses and compounds are needed to mediate the complement pathway, and for example, which act as Factor D inhibitors for treatment of disorders in a host, including a human, associated with dysregulation of the complement cascade, or with undesired result of the complement cascade performing its normal function.

Disubstituted compounds for treatment of medical disorders


A stored data processing apparatus comprises: a calculation section that performs calculation for each bit position using data of all first blocks in a second block that has been specified as an update target on a storage medium and outputs a result of the calculation as calculation data; a write section that writes the calculation data in the third block associated with the update target; and a read section that reads out data from the first block specified as a read target. In the case where it is determined that a plurality of data can be read out from the read target, the read section sets the read target as a duplication block, reads out data from the first blocks other than the duplication block which belong to the second block including the read target so as to set the read out data as determination data, reads out data from the third block corresponding to the read target so as to set the read out data as redundant data, sets one of the plurality of data that can be read out from the duplication block as selection data, and determines whether the selection data is correct data using the determination data, redundant data, and selection data.

1. Field of the Invention
The present invention relates to a storage apparatus that performs recovery operations associated with a read error and a stored data processing apparatus and stored data processing program used for the storage apparatus.
2. Description of the Related Art
The recording capacity of an HDD (Hard Disk Drive) has been increasing, and hard disks of 200 G bytes or more are now available. Along with the increase in recording capacity, the degree of damage becomes severe in the case where a read error occurs in one given sector. In particular, in the case where a read error occurs in one given sector corresponding to a location where directory information concerning to data management in an HDD has been recorded, enormous numbers of data may be damaged. The seriousness of the damage increases as the recording amount increases.
As a means for avoiding troubles specific to such an HDD, a system in which one HDD is configured as part of an array has been available. In this system, if there exists any drive that has got a read error, another HDD provided for increasing redundancy is used to recover the drive data. In order to enhance the resistance of a single HDD against such an error, a method that adds an ECC (Error Correcting Code) to the information in the sector has been adopted. Each sector on a disk medium is composed of SB (syncbyte), DATA, and ECC.
Assume that a read error occurs in a given sector. At this time, a data buffer in an HDD retains data received from a sector at which readout operation is started to a sector which is one sector before a sector where the read error has occurred. If the data readout operation from the sector at which the read error has occurred does not succeed even when retry is attempted, the HDD cannot load effective data into the data buffer and therefore cannot send the effective data to a higher-level device. When the data recovery fails eventually, the HDD notifies the higher-level device of a read error and ends the readout operation.
As a prior art relating to the present invention, there is known a file control apparatus (refer to e.g., Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 5-35416) that prepares a buffer corresponding to the size of data of each the track and performs data check processing in units of tracks. Further, there is known a data recording method (refer to e.g., Patent Document 2: Jpn. Pat. Appln. Laid-Open Publication No. 8-124318) that adds a parity forming LCD (Long Distance Code) to each sector, adds parity sector data to each predetermined number of sectors, calculates parity sector data for each predetermined number of sectors, and uses the parity sector data to make correction when correction using the parity forming the LDC is disabled at reproduction time.
Although the error correction capability itself using the ECC gradually increases, a new data correction method has not been adopted and conventional techniques have continued to be used in recent years. However, in a state where the recording capacity of a single HDD has been increasing, it can be said that the risk of data loss relatively increases with the conventional data error correction capability using the ECC.
Further, as described above, the mechanism in which, in the case where error correction cannot be made using the ECC, the conventional HDD notifies the higher-level device of a read error and ends the readout operation remains basically unchanged since the birth of a disk drive.
Further, in the technique like Patent Document 1, data corresponding to one track needs to be read out every time one writing processing is performed, thus doubling command processing time to deteriorate the performance. As a result, the use of this technique is not realistic. Further, in the technique like Patent Document 2, redundant data needs to be prepared when write data is received from the higher-level device to thereby deteriorate the performance, making it difficult to use this technique practically.

Data storage apparatus having error recovery capability


The invention relates to a closure cap (1) for a container (2) for receiving a pharmaceutical substance, in particular for an infusion or transfusion bottle, with a flanged cap (4) which is suitable for engagement around a container neck (8) and which has a metal film layer, wherein the flanged cap (4) also has a recess (5) that is covered by a plastic lid (3), the plastic lid (3) is connected to the flanged cap (4) by means of at least one connection element (9) formed on the underside, and the plastic lid (3) is removable at least in part. In order to provide a closure cap for a container for receiving a pharmaceutical substance, which container is safe to handle and meets strict demands regarding its tamper-proofing, it is proposed that the plastic lid (3) is connected to the flanged cap (4) via a plurality of connection elements (9) which are formed on its underside and pass through associated connection openings (11) formed in the flanged cap (4), and that the plastic lid (3), in order to expose the recess (5), has a tear-off tab (12) which extends from a coverage of the recess (5) as far as an edge of the plastic lid (3), wherein no connection between the plastic lid and the flanged cap (4) is formed in the area of the tear-off tab (12).

1. Field of the Invention
The invention relates to a closure cap for a container for receiving a pharmaceutical substance, in particular for an infusion or transfusion bottle, having a flanged cap which is suitable for engaging around a container neck and which has a metal foil layer, the flanged cap also having a cut-out which is overlaid by a plastics cover, the plastics cover being connected in a holding manner to the flanged cap by means of at least one connecting element formed on the underside, and the plastics cover being removable at least in part.
2. the Prior Art
Reference is made initially to DE 76 24 855 U1 as prior art. In the case of the closure cap known from this, when the plastics cover formed in the shape of a loop is lifted off, an end region of the flanged cap, which covers over the closure stopper and is provided by break lines, is torn off, in order to allow the closure stopper that is covered-over by the flanged cap to be pierced by a cannula. Reference is also made to WO 01/60699 A2. The flanged cap of this known closure cap has a cut-out in which on the one hand the closure stopper is exposed, but which on the other hand also forms an encircling edge for connecting elements extending from the plastics cover. In order to be able to pierce into the closure stopper through the cut-out, the plastics cover is to be torn in at the edge and then removed as a whole from the flanged cap. In this way, there also results a separation of the connecting elements from the flanged cap.


An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other.

1. Field
Example embodiments relate to semiconductor memory devices and methods of manufacturing the same. More particularly, example embodiments relate to magnetoresistive random access memory (MRAM) devices and methods of manufacturing the same.
2. Description of the Related Art
A transistor having a vertical channel has been developed in order to increase the integration density of MRAM devices. The vertical channel transistor may, for instance, be used as a selection transistor of a memory cell in an MRAM device. A highly integrated MRAM device having good operating characteristics is needed, along with a method of manufacturing the same.

Magnetoresistive random access memory devices and methods of manufacturing the same


The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.

Design verification is essential to virtually any very large scale integration (VLSI) design project. One of the popular verification methods is logic simulation. Logic simulation software reports on how a circuit under design responds to a sequence of input vectors, so the designer can judge whether the circuit behaves as expected over the input sequence. The more vectors simulated, the greater confidence the designer has in the correctness of the designing circuit.
As circuit complexity increases and the time to market shortens, inadequate simulation speed becomes a major bottleneck in the design process. As a result, several special purpose machines have been built to simulate/emulate complex logic designs in hardware, rather than software. Such emulation/acceleration devices can provide several orders of magnitude of speed improvement during the simulation/emulation process. Thus, the necessity and usefulness of emulation/acceleration devices has increased enormously with growth in the complexity of integrated circuits.
An emulation/acceleration engine operates to mimic the logical design of a set of one or more integrated circuit chips. The emulation of these chips in terms of their logical design is highly desirable for several reasons which are discussed in more detail below. It is, however, noted that the utilization of emulation/acceleration engines has also grown up with and around the corresponding utilization of design automation tools for the construction and design of integrated circuit chip devices. In particular, as part of the input for the design automation process, logic descriptions of the desired circuit chip functions are provided. The existence of such software tools for processing these descriptions in the design process is well mated to the utilization of emulation/acceleration engines which are electrically configured to duplicate the same logic function that is provided in a design automation tool.
Utilization of emulation/acceleration devices permits testing and verification, via actual electrical circuits, of logical designs before these designs are committed to a so-called "silicon foundry" for manufacture. The input to such foundries is the functional logic description required for the chip, and its output is initially a set of photolithographic masks which are then used in the manufacture of the desired electrical circuit chip devices. However, it is noted that the construction of such masks and the initial production of circuit chips, which operate in accordance with the designed for functional logic requirements, is expensive. Any passage of a given device having the prescribed logic functionality though such a foundry is an expensive and time consuming process which clearly should be undertaken only once. It is the purpose of emulation/acceleration engines to ensure such a single passage from the functional logic design stage through the stage of chip production via such a foundry.
Verifying that logic designs are correct before committing a design to manufacturing, therefore, eliminates the need for costly and time-consuming multiple passes through a silicon foundry. Debugging logic errors deep inside a logic chip can be extremely difficult because of very limited observability. Emulation provides two very significant advantages. Firstly, the proper verification of a functional logic design eliminates the need for a second costly passage through the foundry, and, secondly, and just as importantly, getting the design "right the first time" means that the design does not have to be corrected in the foundry. Accordingly, production delays are significantly reduced and the time to market for the particular technology/technology improvements embedded in the integrated circuit chip is greatly reduced, thus positively impacting the ability to deliver the most sophisticated technological solutions to consumers in as short of time as possible.
An additional advantage that emulation/acceleration systems have is that they act as a functioning system of electrical circuits which makes possible the early validation of software which is meant to operate the system that the emulator/accelerator is mimicking. Thus, software can be designed, evaluated and tested well before the time when the system is embodied in actual circuit chips. Additionally, emulation/acceleration systems can also operate as simulator-accelerator devices thus providing a high speed simulation platform.
FIG. 1A illustrates a high-level block diagram of a typical emulation/acceleration system 10 (hereinafter referred to as emulation system 10), which is controlled by a host workstation 12. Emulation system 10 includes at least one emulation board 14, which, in turn, contains a plurality of emulation modules 16, as shown in FIG. 1B. Each emulation module 16 contains a plurality of emulation processors 18, as shown in FIG. 1C. Each emulation processor 18 is programmed to evaluate a particular logic function (for example, AND, OR, XOR, NOT, NOR, NAND, etc.). The programmed emulation processors 18, together as a connected unit, emulate the entire desired logic design under test 19 (i.e., the programmed emulation processors form part of a simulation "model" 15 for the logic design). This simulation model 15 may also include some additional controllability/observability logic to aid in the simulation/emulation process.
The overall simulation throughput of such a system is limited by the interface between the simulation model running on the emulation system 10 and a control program 20 running on a host workstation 12. Transactions between control program 20 and the emulation board 14 include reading and writing the values of logic facilities contained within the simulation model and the execution of cycles to recalculate the model state by toggling the value of clock signals that propagate to latch facilities within the simulation model.
The propagation of a "clock" command from control program 20 to emulation system clock distribution circuitry 24 through a normal network interface 26 incurs a substantial latency, particularly if the number of cycles specified by the "clock" command is low, and the speed of emulation system 10 is high.
In order to address this shortcoming, some systems provide an alternate communication path between control program 20 and the emulation board 14 that bypasses normal network interface 26. This path includes a custom stimulus card 28 (e.g., Cadence Design System's Direct Access Stimulus "DAS" card) plugged into a PCI slot in host workstation 12. A special high-speed multi-strand cable 30 is connected between custom stimulus card 28 and the emulation board 14 containing the model. This cable 30 is much more efficient than the network interface 26 because of the more direct connection. To use this cable 30 most efficiently, a single "cycle forever" command is issued from control program 20 to emulation board 14 via network interface 26. Emulation system 10 then continuously evaluates the model state. Read and write accesses from control program 20 through custom stimulus card 28 then directly accesses the model facilities as they are being evaluated.
In order to keep control program 20 synchronous with the evaluation of the emulation model, precise control of the clocking signals to all latches within the model is required. In order to prevent an undesired change in model state, the clock signals should be disabled while the emulation system 10 is cycling. This condition where in the emulator is cycling but the model is prohibited from changing state is known as "idling". Clock signals should be enabled for the precise number of emulator cycles in order to allow the model to change state. In one implementation, one of the signals on cable 30 is assigned to a clock signal that, when toggled, produces a 1-emulator-cycle pulse in the model, advancing the model to the next sequential state. Control program 20 then executes a loop that toggles the clock signal for the required number of cycles.
While this technique provides an improvement over the network interface 26 method of clocking, it still does not provide optimum obtainable throughput. There is a need for an enhanced apparatus and method for controlling the clock inputs to all latches within the simulation model. Such an apparatus should reside within the emulation board 14, so that work previously performed by a clock control loop in control program 20 is now performed by logic within the emulation board 14 itself.

Method and apparatus to use clock bursting to minimize command latency in a logic simulation hardware emulator / accelerator

International Business Machines Corporation