Provided are an EMI characteristic derivation unit which derives an EMI characteristic radiated from a cable based on design information of a circuit board connected with the cable; a determination standard database which stores an EMI tolerance condition which is a tolerance condition for the EMI characteristic; an EMI condition determination unit which determines whether the EMI characteristic satisfies the EMI tolerance condition; an improvement effect database which stores a modification guideline to modify a configuration of the circuit board necessary to satisfy the EMI tolerance condition when the EMI characteristic does not satisfy the EMI tolerance condition and an improvement effect corresponding to the modification guideline; a restriction item database which stores a restriction item applied when the configuration of the board is modified; and a configuration modification unit which performs the configuration modification of the board in accordance with the modification guideline and the restriction item.

In a circuit board (hereinafter, described also as a "PCB"), a cable and a semiconductor integrated circuit (hereinafter, described also as an "LSI") are mounted. It is desirable to design such a circuit board so as to have a low level of electromagnetic wave radiation (hereinafter, described also as "EMI" or "unnecessary electromagnetic wave radiation") radiated from the circuit board and operate stably. For such a desire, a circuit board is configured and a layout is designed so as to allow an EMI amount generated from the circuit board to be at a low level.
The main cause of EMI is electromagnetic coupling between current flowing through a wiring of a circuit board and a cable connected to the circuit board. Such electromagnetic coupling causes common-mode current to flow through the cable and as a result, the cable acts as an antenna, resulting in occurrence of unnecessary electromagnetic wave radiation. Therefore, when current flowing through the wiring increases and electromagnetic coupling increases due to an increase in circuit operation speed and the like, the radiation amount of unnecessary electromagnetic waves also increases.
To suppress unnecessary electromagnetic wave radiation, it is necessary to take countermeasures for a configuration such as a layer structure, a layout, and the like of a circuit board, a characteristic of current flowing through a wiring, a length and connection location of a cable, addition of a countermeasure component, and the like. However, it is difficult to modify a design and add a countermeasure component for EMI suppression after production of a circuit board, and even when such countermeasures are taken, design cost and the like increases to a large extent.
Therefore, it is important to estimate an electrical characteristic in a design stage of a circuit board and take a countermeasure for EMI suppression from the result, as necessary. As a method for evaluating an unnecessary electromagnetic wave radiation amount in the design stage of the circuit board, a method for analyzing an electrical characteristic based on information of a board configuration and a mounted component is cited.
As a method for analyzing an electrical characteristic, there are cited an electromagnetic field analysis method such as an FDTD (Finite Difference Time Domain) method, a moment (MOM) method, a finite element (FEM) method, and the like and a circuit analysis method such as SPICE (Simulation Program with Integrated Circuit Emphasis) and the like.
However, it is difficult for SPICE to directly evaluate common-mode current and therefore, a special circuit model for causing current considered as common-mode current to flow is necessary. Further, to create the special circuit model, those with knowledge about electrical circuits and electromagnetic waves need to execute special processing, but it is difficult for those without in-depth knowledge to execute such processing. Further, even when such a special model is created, there is a risk in which a sufficient guarantee in terms of analysis accuracy is unobtainable. Therefore, it is very difficult to estimate common-mode current using SPICE.
On the other hand, in the electromagnetic field analysis method, the entire system to be a target is modeled and therefore, it is possible to calculate electromagnetic wave radiation based on common-mode current flowing through a cable. However, when the entire circuit board including a cable is modeled and a radiation electromagnetic field is calculated, enormous calculation cost is necessary. In general, there is a trade-off relation between calculation cost and analysis accuracy and therefore, when calculation cost is simply decreased, analysis accuracy is decreased, resulting in an insufficient guarantee for an analysis result.
From such a reason, there is needed a method in which to predict an unnecessary electromagnetic wave radiation amount in a design stage of a circuit board, a characteristic where common-mode current flowing through a cable is included can be predicted speedily with necessary analysis accuracy.
In addition, this method needs to be usable by those without in-depth knowledge about electrical circuits and electromagnetic waves.
As a technique for improving unnecessary electromagnetic wave radiation from a cable, various proposals have been made. For example, in Patent Literature 1, to speedily obtain a design guideline for suppressing EMI from a cable, an electronic device, a wiring, and a ground plane are converted into a model for electromagnetic field analysis from layout information of a circuit board and then a distribution of an electric field intensity generated in the vicinity of the ground plane associated with the operation of the electronic device is calculated. A portion where this electric field intensity is weak is connected with a cable and thereby, EMI from the cable is suppressed.
Further, Patent Literature 2 has proposed an electromagnetic field intensity calculation device including a model creation unit which creates a model of electrical circuit equipment for electromagnetic field intensity calculation by setting input data. There are provided a navigation file which stores a procedure for inputting external dimensions of the electrical circuit equipment and inputting an analysis frequency for analyzing the electrical circuit equipment via meshing and a display unit which sequentially displays the procedure stored in the navigation file; and in accordance with the procedure displayed on the display unit, a user sets input data conversationally.
Further, Patent Literature 3 has made a proposal for obtaining optimum analysis input data independent of the skill level of an input data creator, with respect to the electromagnetic field intensity dealt with in Patent Literature 2.

Board design method and board design device


A ferroelectric capacitor having a bottom electrode (9a), a ferroelectric film (10a) and a top electrode (11a) is formed above a semiconductor substrate (1). The ferroelectric film (10a) is constituted of CSPZT with 0.1-5 mol % of La and 0.1-5 mol % of Nb.

With the development of digital technologies, there is an increasing trend of high-speed processing or preservation of a large capacity data. Because of this, large-scale integration and high performance are required in semiconductor devices for use in electronic equipments.
Accordingly, to realize large-scale integration of a semiconductor memory device (DRAM), extensive studies and development are carried out on the techniques using a ferroelectric material or a high-permittivity material, in place of a silicon oxide or a silicon nitride, as a capacitor insulating film for a capacitance element constituting the DRAM.
Also, to realize a nonvolatile RAM capable of performing high-speed write/read operation at a low voltage, studies and development are being conducted actively in regard to a ferroelectric memory (FeRAM) using a ferroelectric film having a spontaneous polarization characteristic, as a capacitor insulating film.
The ferroelectric memory (FeRAM) stores information utilizing a hysteresis characteristic of a ferroelectric substance. The ferroelectric memory includes in each memory cell a ferroelectric capacitor having a ferroelectric film, as a capacitor dielectric film disposed between a pair of electrodes. In the ferroelectric substance, polarization occurs depending on a voltage applied between the electrodes, and spontaneous polarization remains even after the applied voltage is removed. Also, when the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read out by detecting the spontaneous polarization. Further, as compared with a flash memory, the ferroelectric memory is operable at a low voltage, and capable of high-speed writing with reduced power.
The ferroelectric film of the ferroelectric capacitor is formed of a PZT-based material, such as lead zirconate titanate (PZT) and La-doped PZT (PLZT), a compound having a bismuth layer structured ferroelectrics, such as SrBi2Ta2O9 (SBT,Y1) and SrBi2(Ta,Nb) 2O9 (SBTN,YZ) Conventionally, as a film-forming method of the ferroelectric film, there has been used a sol-gel method, a sputtering method or an MOCVD method. By means of such the film-forming method, a ferroelectric film of an amorphous phase is formed on a bottom electrode film, and thereafter, the ferroelectric film is crystallized to a crystal of perovskite structure by a thermal treatment. A crystallinity of the ferroelectric film is subject to a crystallinity of the bottom electrode film, the film-forming condition and the crystallization condition of the ferroelectric film, and the like. Therefore, conventionally, by adjusting such the conditions, it has been intended to improve the crystallinity of the ferroelectric film. However, in recent years, it has become unable to satisfy the requirements of further improvement on the crystallinity. As a result, a ferroelectric capacitor having sufficient characteristics cannot be obtained any more, nor variation in the performance of the memory cell in an identical chip can be suppressed sufficiently.
Also, for example, in Patent document 1 (Japanese Patent Application Laid-open No. 2003-2647), there is disclosed the adoption of a variety of compositions of ferroelectric films for the purpose of decreasing a crystallization temperature of the ferroelectric film. However, there is no such method that can obtain sufficient crystallinity.
Patent document 1: Japanese Patent Application Laid-open No. 2003-2647

Semiconductor device and manufacturing method therefor


A method of determining a passive Round Trip Time, RTT, delay in a telecommunications system for exchanging data packets in accordance with a data transmission protocol between a first device and a second device. The first and second devices are identified by first and second device identifications, respectively. The data packets include an address part including a source address and a destination address. The method is performed in a node by modifying the address part of a received data packet from the first device, and creating a first timestamp before transmitting the modified data packet to the second device. Upon receiving, at the node, from the second device in response to the modified data packet, a data packet having the modified address part of the modified data packet, the node creates a second timestamp that provides for passively measuring the RTT delay.

Round-Trip-Time, RTT, is the duration, generally measured in milliseconds, from when a first or client device, such as a server or node in a telecommunications system, sends a request to a second device, such as another server or another node in the telecommunications system, and when the first device receives a response from the second device. RTT is a key performance metric in telecommunications systems for network load and network latency, for example. RTT is generally measured per flow or 5-tuple, with higher order aggregations being possible, RTT between the User Equipment, UE, and a network node etc.).
For the purposes and applications of telecommunications systems and in bi-directional communications between a client and a server, the RTT is generally calculated directionally, that is from the telecommunications system towards the client, called RTTc, and from the telecommunications system towards the server, called RTTs, and per flow or 5-tuple. The RTT may also be measured between equally capable peers such as between two servers or between two clients.
In the case of a communication between a client and a server in the telecommunications system wherein the client accesses the telecommunications system through an access network, such as a Radio Access Network, RAN, RTTc can be calculated as the time between a segment or data packet transmitted by the server towards the client in the downlink, crosses a monitoring point, such as a node, in the access network and the time the acknowledgment towards the server crosses the same monitoring point in the uplink.
In such communication, RTTs can be calculated as the time between a segment or data packet node towards the server in the uplink crosses the monitoring point in the access network and the time the acknowledgment towards the client crosses the same monitoring point in the downlink.
Applications and use cases using RTT measurements may include:
a. Quality of Experience measurements and Analytics: for instance, in a telecommunications system like a mobile telecommunications system, the RTTc represents the distance to the client including the access network, such as a RAN. High RTTc values may indicate a problem in the transmission of information to the client, such as excessive buffering of data packets, too many transmission hops as a result of incorrect routing, low data rate transmission lines, etc. Similarly, high RTTs values may also point to excessive buffering and slow transmission lines, but may also indicate that clients are accessing servers that are either remote or highly loaded (there is a delay in the responses) which can indicate a problem supplying the content.
b. Traffic Optimizations: implementation of several Active Queue Management, AQM, techniques such as the CoDel algorithm—based on a controlled delay approach relay—per 5-tuple or flow RTT measurements both towards the client and the server require RTT knowledge.
There are several other applications and use cases in telecommunications system that use per flow or 5-tuple RTT measurements.
RTT calculations from the telecommunications system can be done actively, wherein the telecommunications system sends a data packet or message to a node, waits for the response and measures the time elapsed, or passively, using subscriber traffic that is already being carried by the telecommunications system.
Active RTT measurements include Internet Control Message Protocol, ICMP, messages (typically called sending a "ping"). Passive RTT measurements are available on certain transport protocols like the Transport Control Protocol, TCP, by measuring the time it takes the receiver of a data packet to confirm its reception, Such techniques are covered in the prior art.
Active RTT measurements require the telecommunications system to send additional traffic and requires the receiver of the packet or message to support its processing and to answer to it. It is therefore a coordinated procedure not supported by all network elements. Also, it is an obvious procedure—when implemented it is clear that the telecommunications system is performing a measurement—which can lead to information leakage and can be vulnerable to tampering.
Passive RTT measurements do not require support from the endpoints, since the telecommunications system re-uses existing traffic to calculate the RTT wherein all endpoints support passive RTT measurements. Passive RTT measurements are also 'silent'—it is impossible to tell if a telecommunications system is performing an RTT measurement on a certain flow. Passive RTT measurements also do not generate additional traffic and do not rely on intermediary elements to forward the required messages.
Passive prior art RTT measurements may only work on certain protocols. The telecommunications system requires the protocols carrying the underlying traffic to allow for the measurement of RTT in order to be able to implement the measurements transparently.
TCP is one of such protocols allowing passive prior art RTT measurements. Passive RTT measurements are possible in telecommunications systems with subscriber TCP traffic because the telecommunications system can inspect—using for instance Deep Packet Inspection, DPI, techniques—sequence numbers of certain TCP nodes and later on correlate acknowledgments to those nodes.
Since TCP contains sequence numbers and acknowledgments, it is relatively easy (and well known) to measure RTT as the time it takes a client or a server to acknowledge a certain sequence number. TCP is bidirectional and allows therefore calculation of RTTc and RTTs.
Assuming that the inspected node generates an acknowledgement on the other end and disregarding the time it takes the TCP stack on the other end to produce the acknowledgement, it can be assumed that the difference in time is the RTT on that direction. This is true since transmission times are generally several orders of magnitude bigger than processing times.
Other major Transport level protocols, are the User Datagram Protocol, UDP, and the Quick UDP Internet Connections, QUIC, protocol, for example. QUIC is a "half-transport" protocol that runs on top of User Datagram Protocol, UDP. The addition of UDP and QUIC delivers all the characteristics and functionality of a transport protocol including in order delivery, retransmissions, congestion control and end-to-end encryption.
QUIC is resilient to changes on the Access Network. An internal identifier is defined in QUIC that allows the server to link two 5-tuples UDP flows from different source IP addresses and ports in to the same conceptual QUIC (transport level) flow.
The use case for this resilience is to maintain QUIC flows (and statuses) across telecommunications system changes—when a subscriber disconnects from a telecommunications system and re-joins a different telecommunications system the QUIC flow can be recovered, no renegotiation is required, the encryption context is retrieved and reused and application data exchange can continue un-affected.
QUIC can implement this resiliency by linking the two 5-tuple UDP flows (with different source IP addresses and ports) to the same QUIC flow.
UDP and QUIC, for example, are examples of protocols that do not include sequence numbers or acknowledgment numbers, and when included they are encrypted, like in the case of QUIC, which makes prior art passive RTT measurements over UDP or QUIC impossible. This means that some of the use cases listed above, such as Quality of Experience, QoE, measurements or some Traffic Optimizations, using prior art passive RTT measurements, cannot be applied to QUIC traffic.

Method of determining passive round trip time, RTT, delay in a telecommunications system


A metrology apparatus for measuring a parameter of a microscopic structure on a substrate, the apparatus comprising a supercontinuum light source arranged to generate a measurement beam, an optical system arranged to direct the measurement beam onto the substrate and a sensor for detecting radiation reflected and/or diffracted by the structure.

A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the "scanning"-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
During and after various steps in the production of devices using lithographic methods, it is necessary to make measurements on the devices that have been produced to assess whether the production process has proceeded correctly. Such measurements are collectively referred to as metrology. In view of the scale of devices produced by lithography, metrology methods generally involve illuminating the device structure or a test structure with a measurement beam and detecting the returning radiation. One such method is scatterometry, in particular angle-resolved scatterometry in which the spectrum of the radiation reflected by the structure under inspection is measured at different angles using a sensor such as a CCD in the pupil plane of an objective lens.
The sensitivity and speed of operation of most metrology devices is limited by the radiation source used to generate the measurement beam. Presently available sources include: Xe lamps, which have a good, wide bandwidth but poor luminance and poor spatial coherence; SLED lasers, which have good luminance and spatial coherence but not a particularly wide bandwidth and are not capable of generating wavelengths below about 400 nm.

Metrology apparatus, lithographic apparatus, process apparatus metrology method and device manufacturing method


A hierarchical, multi-dimensional, strategy board game apparatus includes game boards having game spaces, posts for supporting the board members, and game pieces including a static piece, a pawn-like piece, a first promotion piece, and a second promotion piece. In playing the game, a base board is designated, along with a riser space, a promotion space, and a return space. Each player starts with a designated number of pieces, and takes turns to move their pieces in prescribed ways via the designated spaces as available. The players thereby attempt to attain higher levels for their pieces with respect to the boards, with means for promotion and demotion of the pieces and an in-hand ability to return them to play via the return space. The pieces may thus gain expanded movement capabilities for capturing other players' pieces and, ultimately, the static piece to win the game.

Board games, sometimes referred to broadly as "parlor games", are well known and have historically enjoyed popularity among game enthusiasts and wide commercial success. Strategy board games such as the well known games of chess and checkers have traditionally been played on a single 8×8 square planar game board totaling 64 equally sized square spaces. In such games, opponents arrange a number of game pieces in predetermined locations on the board and "attack" each other in an effort to capture and remove the opponent's pieces according to well-established rules of play. In chess, individual pieces are designated as having particular movement and capture capabilities. Both chess and checkers allow promotion of a lowest level or basic piece, to a highest level or most powerful piece, once the opposite side of the game board is reached through forward movement of the piece on the board according to established rules of play. In these well known games there are, however, no rules or provisions for allowing demotion of game pieces. Rather, in these games there is only capture and removal of pieces according to the rules. Furthermore, the single game board, singular direction of play, and single promotion of pieces, all create limits to overall strategies and depths of playing the games.
In response to such limitations, three-dimensional and multiple flat game board concepts have been utilized to expand playing areas and necessitate increased complexity in successful game playing strategies as may be desired by those who have developed a modicum of sophistication in playing the games. Often the multiple boards are the same size and generally offer multiple versions of the same basic two-dimensional game, such as provided in the so-called "three-dimensional chess" game made famous by the character "Mr. Spock" in the original Star Trek television series. For example, U.S. Pat. No. 3,767,201 to Harper et al. discloses a game field with multiple levels, which includes elements of tic-tac-toe. U.S. Pat. No. 3,937,471 to Brennan provides a second board for chess and expanded rules of play to have pieces traverse both game boards. Likewise, U.S. Pat. No. 5,112,056 to Ching infuses classic chess with an Egyptian theme and expands the otherwise flat chess game field to a four-tiered pyramid shape. Other varieties of three-dimensional game boards offer designated playing pieces that emphasize piece movements and generally mimic chess piece movement (e.g. of the Rook, Bishop, and Queen pieces) thereby adding vertical movement across several game boards (each typically being identical to the "standard" 64 square game board) to traditional movements on the single game board. In U.S. Pat. No. 6,276,685 to Sterling, a game is disclosed which has designated game pieces that are permitted to move, in play, vertically and diagonally across multiple game boards. U.S. Pat. No. 5,678,818 to Underwood teaches three square game boards and a selection of pieces that are moved like chess pieces across the boards.
In these patented games, the game pieces generally have a static set of functions for the additional cross-board movements, but do not relate piece movement across game boards to promotion of game pieces thereby.
Considering, now, rules of promotion of game pieces, in both chess and checkers a promotion feature is utilized in play as aforesaid. In typical embodiments of each of these games, the promotion of a piece occurs when it traverses the field of play in one direction. U.S. Pat. No. 4,019,746 to Hare, U.S. Pat. No. 4,032,152 to Johnson, and U.S. Pat. No. 5,340,114 to Wester, each reference promotion of pieces that are pawn-like and traverse a single game board in one direction to attain promotion. In the game of checkers, stacking of game pieces to designate promotion occurs under that game's rules by "kinging" the piece as is well known. This concept of stacking of pieces to designate promotion is disclosed in U.S. Pat. No. 4,032,152 to Shifman, U.S. Pat. No. 5,472,208 to Barry, U.S. Pat. No. 6,135,452 to Yurchey, and in U.S. Pat. Applic. Pub. No. 2001/0011798 of Anderson. In Shifman, so-called key markers are utilized for stacking on stationary posts positioned on a single game board. In Barry, opponents each have different game pieces, with one player having a set of rings and the other a set of peg-shaped pieces. The stacking action occurs upon capture of the opponent's piece. Yurchey describes two types of game pieces that may, in turn, be combined to achieve a more powerful third type of game piece with advanced movement and capture attributes. Anderson's game pieces have predefined movements and capture features, with predefined sets of movements for each piece. Stacking occurs when an opponent's piece is captured. The capturing piece adds the game piece and its attributes to its own movements. It is to be also noted that Yurchey utilizes the promotion and demotion of game pieces, by way of the aforedescribed concept of having two different types of pieces which may be combined in play to make the third, more powerful piece. Specifically, in Yurchey the two types of game pieces are positioned on a single-level game field, and they can be combined in play to attain the higher, third level of movement and capture attributes. Players may combine and un-combine the two types of pieces at will throughout the game. Promotions and demotions in Yurchey are not related, however, to pieces landing on predetermined promotion spaces on the board; and attaining promotion of a piece is not conditioned upon movement of the piece to another board.
Additionally, the prior, known games have relied upon generally cumbersome and rigid game board apparatuses. These constructions were typically not suited for compact storage and transportation, and they also had structural members such as support posts and the like which interfered with or obstructed play on portions of the boards adjacent to them.
Thus, despite past efforts, there has not been heretofore a hierarchical, multi-dimensional, strategy board game apparatus and playing method having an easily constructible and collapsible apparatus, and game pieces which, in play, attain promotion by ascending game board levels and may also be demoted by an opponent while effectively remaining in play.

Hierarchical, multi-dimensional, strategy board game apparatus and playing method


An information processing apparatus acquires a structured document containing a plurality of elements, specifies, in accordance with an instruction from a user, a partial element group from the plurality of elements contained in the acquired structured document, and selects, in accordance with the content of each of the plurality of elements included in the specified element group, an output-target element from the plurality of elements included in the element group.

1. Field of the Invention
The present invention relates to an information processing apparatus, an information processing method and a non-transitory computer-readable storage medium.
2. Description of the Related Art
By accessing Web pages on the Internet, users acquire a variety of information. A Web page is composed of a structured document described in a structured language such as HTML (HyperText Markup Language) or XHTML (Extensible HyperText Markup Language). A user refers to a Web page using software referred to as a "browser", which corresponds to a display of such a structured document.
When a Web page is printed, there are cases where the user desires to print not the entire Web page but only a region that is a portion thereof. Many techniques for printing such a partial region of a Web page are known. An example of such a known technique is to adopt only the region of the Web page that is being displayed in the browser window at the time of print execution as the object of printing and to perform printing that is based upon image data representing the region that is the object of printing (see the specification of Japanese Patent Laid-Open No. 2002-351636).
If the user is to cause a desired region of a Web page to be output in accordance with the technique described in Japanese Patent Laid-Open No. 2002-351636 cited above, the user must first cause only the region of the Web page that is desired as the object of output to be displayed in the browser window.

Information processing apparatus, information processing method and non-transitory computer-readable storage medium


A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.

The semiconductor manufacturing industry continually seeks to improve the processing capabilities and power consumption of integrated circuits (ICs). Traditionally, this has been achieved by shrinking the minimum feature size. However, in recent years, process limitations have made it difficult to continue shrinking the minimum feature size. Therefore, the stacking of multiple device layers into three-dimensional (3D) ICs has emerged as a potential approach to continue improving processing capabilities and power consumption of ICs. One type of 3D IC is a monolithic 3D IC in which multiple device layers are formed directly on a single semiconductor substrate (e.g., a wafer).

Method for manufacturing monolithic three-dimensional (3D) integrated circuits

Taiwan Semiconductor Manufacturing Co., Ltd.