A fish net constructed of conventional open mesh flexible net material is provided with an aperture having an escape panel secured therein. The escape panel is comprised of extruded plastic net material which is substantially rigid to maintain the mesh configuration while permitting slight bending of the panel. Thus, undersized fish can escape through the mesh of the escape panel without being gilled.

The present invention is directed to a flexible fish net having an escape panel wherein the escape panel is provided with a substantially rigid mesh having a mesh size greater than the mesh size of the flexible fish net.
In various types of fishing involving the use of nets, the largest problem involves the netting of a plurality of different types of marine life in addition to the desired species. Even if the catch consists substantially of the desired species of fish, there is still the problem of sorting undersized fish and returning them to the ocean for continued growth. In most instances the sorting of the undersized fish from the desired fish takes place after the catch has been completely removed from the water. Depending upon the efficiency of the sorting operation, the time lapse could prove fatal to a large number of small fish. Furthermore, the sorting of the undersized fish from the desired fish involves a considerable amount of time and effort which the fishing industry would like to eliminate. Therefore, it would be clearly desirable to cull the undersized fish of various species from the net as it fishes.
In the past, netting having a larger mesh has been used experimentally in a pound head in an attempt to achieve this result. However, due to the flexibility of the netting, the size of the individual mesh openings varied considerably resulting in too many fish being gilled to make this a feasible solution to the problem.
While various sorting devices and escape hatches have been devised for various species of marine life, such devices are not directed to sorting undersized fish from the fish of desirable size and permitting the undersized fish to escape during the netting operation.
The patent to Savoie (U.S. Pat. No. 4,043,068) is directed to an escape hatch for a fish net wherein a substantially rectangular panel is pivotally mounted in the upper side of a conventional type fishing net such as used in trolling operations to catch shrimp and the like. The hinge for the panel is located in the leading direction of movement of the net so tat during a trolling operation, the force of the water will keep the panel closed. When the trolling operation ceases, the panel will tend to lower to an open position due to gravity thereby allowing the more active species of fish, crabs and the like, to escape out through the opening. The remaining catch will be the desired shrimp. While the escape hatch which is used in conjunction with a conventional fish net, has a plurality of rigid openings, the size of the openings is substantially smaller than the mesh openings of the net and there is no discussion of sorting fish by size.
The patent to West et al. (U.S. Pat. No. 4,805,335) is directed to a sorting device for troll nets. The sorting device enables capturing of preselected marine life and harmlessly separating non-selected marine life. However, the sorting device is comprised of a substantially funnel-shaped outlet located in the side of the troll net to allow the escape of undesirable species. There is no discussion or suggestion of sorting a particular species by size.


In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.

High performance processors currently used in data processing systems today may be capable of superscalar operation and may have pipelined elements. A superscalar processor has multiple elements which operate in parallel to process multiple instructions in a single processing cycle. Pipelining involves processing instructions in stages, so that the pipelined stages may process a number of instructions concurrently.
In a typical first stage, referred to as an instruction fetch stage, an instruction is fetched from memory. Then, in a decode stage, the instruction is decoded into different control bits, which in general designate i) a type of functional unit for performing the operation specified by the instruction, ii) source operands for the operation and iii) destinations for results of operations. In a dispatch stage, the decoded instruction is dispatched per the control bits to a unit having an execution stage. This stage processes the operation as specified by the instruction. Executing an operation specified by an instruction includes accepting one or more operands and producing one or more results.
While instructions may originally be prepared for processing in some programmed, logical sequence, it should be understood that for concurrent processing of multiple instructions, the instructions may be processed, in some respects, in a different sequence. However, since instructions are not totally independent of one another, complications arise. That is, the processing of one instruction may depend on a result from another instruction. For example, the processing of an instruction which follows a branch instruction will depend on the branch path chosen by the branch instruction. In another example, the processing of an instruction which reads the contents of some memory element in the processing system may depend on the result of some preceding instruction which writes to that memory element.
As these examples suggest, if one instruction is dependent on a first instruction and the instructions are to be processed. concurrently or the dependent instruction is to be processed before the first instruction, an assumption must be made regarding the result produced by the first instruction. The state of the processor, as defined at least in part by the content of registers the processor uses for execution of instructions, may change from cycle to cycle. If an assumption used for processing an instruction proves to be incorrect then, of course, the result produced by the processing of the instruction will almost certainly be incorrect, and the processor state must recover to a state with known correct results up to the instruction for which the assumption is made. (Herein, an instruction for which an assumption has been made is referred to as an "interruptible instruction", and the determination that an assumption is incorrect, triggering the need for the processor state to recover to a prior state, is referred to as an "interruption" or an "interrupt point".) In addition to incorrect assumptions, there are other causes of such interruptions requiring recovery of the processor state. Such an interruption is generally caused by an unusual condition arising in connection with instruction execution, error, or signal external to the processor.
A "completion" stage deals with program order issues that arise from concurrent execution, wherein multiple, concurrently executed instructions may deposit results in a single register. It also handles issues arising from instructions subsequent to an interrupted instruction depositing results in their destination registers. In connection with the prior art completion stage, information about instructions is typically kept in dispatch order in a completion buffer (also known as a reorder buffer) so that the instructions can be reordered in dispatch order after having been executed out of order. Also, the results of instruction execution are temporarily held in one or more backup buffers (also known as rename buffers). Once it is known that such execution results are committed they are ultimately written back to architected registers in accordance with the sequence of instructions in the completion buffer. After execution results corresponding to completion buffer entries have been written back to architected registers from rename buffers, completion and rename buffer entries are then released so that they can be filled with information for subsequently dispatched instructions.
Certain timing aspects of the above described dispatching, completion and writeback are shown in FIG. 1 for two exemplary instructions. In the example, the two instructions are fetched, decoded and dispatched in corresponding cycles. It is assumed in the example that the second instruction is not dependent on the first instruction for its source operand, and that the second instruction executes more quickly than the first. Nevertheless, completion of the second instruction requires execution and completion of the first. So, FIG. 1 shows completion and writing back of the second instruction being held up until execution and completion of the first. Instruction 2 executes in cycle 3, but a number of cycles are spent before the first instruction is executed. This could be due to waiting for data access, branch resolution, etc. Then, in cycle 6 of the example, instruction 1 completes. In response, instruction 2 completes. In the example, instruction 2 is shown completing in cycle 7, although it is understood that it might be possible, in a machine that has the capability to complete numerous instructions in a single cycle, for instruction 2 to complete in cycle 6 in response to the completion in that same cycle of instruction 1. The instructions are shown writing back results of execution in cycles 7 and 8 respectively.
As the example illustrates, the present method and apparatus for dispatching, completing and writing back instructions may delay release of completion and rename buffer entries for a second instruction, due to waiting for execution and completion of a preceding instruction. This may delay dispatching of subsequent instructions. Therefore a need exists for improving the method and apparatus for processing instructions.

Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched

International Business Machines Corporation


A vehicle brake controller is capable of executing limit control when a driver is performing a brake pedal operation during turning of a vehicle, to limit an increase in a braking force applied to an inner wheel that is a wheel positioned on the inner side of the turn. The vehicle brake controller is configured to start the limit control when a wheel state value that becomes greater as deceleration of the inner wheel becomes greater exceeds a start determination value that is set to a value greater than zero.

The invention relates to a vehicle brake controller and a vehicle brake control method that adjust braking force of wheels provided in a vehicle.
Generally, in a case where lateral acceleration acting on a vehicle during turning is great, the center of gravity of the vehicle tends to move to the outer side of the turn, and vertical load of the wheels positioned on the inner side of the turn (hereinafter referred to as inner wheels) tends to be small. When the vertical load of the inner wheel becomes small, gripping force in the front-back direction and gripping force in the lateral direction of the inner wheels both decrease, and the vehicle easily may slip sideways. Further, even if a starting condition of an anti-lock braking control (hereinafter referred to as an ABS control) under such a situation is satisfied and slip ratio of the inner wheels is controlled, there is a risk of not being able to sufficiently stabilize the behavior of the vehicle due to a gripping force of the inner wheel that has been decreased by the reduction of the vertical load not being sufficiently recovered.
As a brake controller that can solve such a problem, a device described for example in Japanese Laid-Open Patent Publication No. 4-237660 has conventionally been proposed. In the brake controller, in a case where the starting condition of the ABS control is satisfied while the vehicle is turning, the stabilization of the behavior of the vehicle is attempted by differentiating a manner of control for the wheels positioned on the outer side of the turn (hereinafter referred to as an outer wheels) and a manner of control for the inner wheels. Specifically, in the ABS control for the outer wheels, brake fluid pressure in wheel cylinders corresponding to the outer wheels is controlled such that the slip ratio of the outer wheels becomes optimal. At this time, the brake fluid pressure in the wheel cylinder corresponding to the outer wheels (hereinafter referred to as an outer wheel fluid pressure) is detected.
With respect to this, in the ABS control for the inner wheels, a gain value that is set to a smaller value as a lateral acceleration becomes greater is calculated due to the vertical load of the inner wheel becoming smaller as the lateral acceleration becomes greater. A control fluid pressure for the inner wheels is calculated by multiplying the gain value to the detected outer wheel fluid pressure, and a brake fluid pressure in a wheel cylinder corresponding to the inner wheels is controlled to be the control fluid pressure for the inner wheels.
Incidentally, in the above solution (hereinafter referred to as a first solution), costs of the controller are high because pressure sensors for detecting the brake fluid pressure in the wheel cylinders are necessary. Further, the optimal slip ratio of a wheel is different depending on the μ value of the road surface that the wheel contacts. Due to this, for example, in a case where the vehicle runs on a road surface in which the μ value of the road surface that the outer wheels contact and the μ value of the road surface that the inner wheels contact are different, the slip ratio of the inner wheels does not necessarily become optimal even if the control fluid pressure for the inner wheels is set based on the outer wheel fluid pressure. This is because deceleration of a wheel changes depending on the μ value of the road surface that the wheel contacts, even if the brake fluid pressure in the wheel cylinder corresponding to the wheel is constant. When the slip ratio of the inner wheels is deviated far off from being optimal as above, the gripping force of the inner wheels also does not sufficiently recover.
Further, the vertical load of the inner wheels changes depending on the loading of the vehicle even if the lateral acceleration is constant. Due to this, the control fluid pressure for the inner wheels set without taking the loading of the vehicle into consideration is not necessarily optimal for the inner wheels at that time.
Thus, in recent years, a method for achieving stabilization of the behavior of a turning vehicle (hereinafter referred to as a second solution) in a method different from the above first solution has been proposed. In the second solution, it is determined that a vehicle is performing a high-G turning, in which the vehicle turns in a state under a great lateral acceleration when the lateral acceleration acting on the turning vehicle exceeds a high-lateral G determination value, and limit control to limit an increase in braking force of the inner wheel is started. Due to this, the decrease of the gripping force of the inner wheel is reduced, and the behavior of the vehicle is stabilized.
Even during the execution of the limit control, the ABS control is executed on the inner wheels if the starting condition of the ABS control is satisfied. In this case, the braking force of the inner wheels may be increased by the ABS control being executed.
In the above second solution, the decrease in the gripping force of the inner wheel is suppressed by maintaining the braking force of the inner wheels when it is determined that the vehicle is performing the high-G turning. In this case, if the driver starts a brake pedal operation after the vehicle has been determined to be performing the high-G turning, the braking force is not applied to the inner wheel. Due to this, although the stability of the behavior of the vehicle is ensured by executing the limit control, the actual deceleration of the vehicle becomes small compared to required deceleration corresponding to the amount of the brake pedal operation by the driver.

Vehicle brake controller and vehicle brake control method


A discharge opening for a reheat furnace is shielded with a pair of metal woven wire mesh curtains each secured above the discharge opening and hanging to the bottom of the opening. Each curtain preferably is formed from multiple parallel coplanar ribbons, each extending from above the discharge opening to the bottom of the discharge opening. The mesh curtains are fabricated from a sag resistant metal alloy. Embodiments are described for accommodating slots which receive discharge lifter members for removing heated metal workpieces from the furnace. A preferred mounting apparatus employs one or more fibrous thermal insulation strips above the discharge opening. A counterweight mounting apparatus urges the fibrous thermal insulating strips against the outer wall of the furnace.

1. Field of the Invention
The present invention relates to a closure for the discharge opening of a steel reheat furnace comprising sag-resistant metal alloy mesh curtains formed from plural steel mesh ribbons. The metal alloy mesh curtains also may be employed in the charging opening of certain reheat furnaces. The purpose of the metal alloy mesh curtains is to retain heat energy within the reheat furnace by reducing the opportunities for heat to leave the furnace.
2. Description of the Prior Art
Steel reheat furnaces are employed to reheat steel workpieces to a temperature at which the steel may be mechanically worked outside the reheat furnace. U.S. Pat. Nos. 3,148,868; 3,716,222; 3,749,550; 4,427,371. The steel workpieces are heated to temperatures of 2000.degree. F. and higher. The reheat furnaces have refractory ceilings, side walls and floors and include plural heat sources such as gas burners or radiant gas burners. Horizontal rails are mounted within the furnace to support steel workpieces as they move through the furnace from a charging opening at one end to a discharge opening at the other end. The temperature gradient across most reheat furnaces develops the highest temperatures adjacent to the discharge opening and usually significantly lower temperatures adjacent to the charging opening. A refractory slab customarily is positioned within the furnace adjacent to the discharge opening. Multiple slots are presented within the refractory slab to receive fingers for directing and withdrawing the forward-most workpiece from the refractory slab through the discharge opening.
With the advent of high temperature radiant heaters, it is now possible to develop high temperatures within a reheat furnace adjacent to the charging openings. Reheat furnaces provided with high temperatures adjacent to the charging openings will benefit from the curtains of this invention. Such installation will be separately discussed in this specification which is principally concerned with discharge openings.
Heated steel workpieces are removed from the reheat furnace through the discharge opening, and new workpieces are introduced through the charging opening whereby a continuous inventory of steel workpieces at gradually increasing temperatures is maintained inside the reheat furnace. Customarily the discharge opening is in line with the movement of steel workpieces through the furnace; however the discharge opening may be angled with respect to the line of movement, e.g., U.S. Pat. No. 4,492,565.
Customarily one or more vertical steel or composite assemblies are provided to function as doors at the charging opening and at the discharge opening. U.S. Pat. No. 4,669,939. The doors are raised vertically by cables to expose the charging opening or discharge opening and the doors are maintained in an elevated position until a steel workpiece or workpieces enters the charging opening or is withdrawn through the discharge opening. Immediately thereafter the doors are lowered to obstruct heat loss through the openings. A significant heat loss occurs during the time when the doors are elevated and the openings are exposed. The heat loss is usually greatest at the discharge opening where the temperatures the highest in the structure.
It is known to employ steel mesh curtains at the charging opening of a reheat furnace which heretofore experienced elevated temperatures of the order of 1500.degree. F. At these temperatures, woven mesh curtains of ordinary steel are not adversely affected by the temperature exposure. However steel mesh curtains have not been employed at the discharge opening of reheat furnaces where the furnace heat loss can be severe.
Some reheat furnaces may experience much higher temperatures as a result of recently available radiant heat sources which can be located adjacent to the charging opening of reheat furnaces. In such reheat furnaces, the curtains of this invention will provide reliable heat retention.

Heat retaining curtains for reheat furnace discharge openings and charging openings


An apparatus for removing liquid from a composite mixture of liquid and solids comprising a hopper 16 mounted atop a compactor ram assembly 10, having a snout section 12 and an extruder section 14 mounted in a generally axial direction to the compactor ram assembly 10. Wet waste material is loaded into the hopper 16 and falls onto a loading floor 158. A hydraulically operated ram 208 compresses the wet material into the snout and extruder sections 12, 14. Under pressure from the ram 208, liquid in the waste material escapes from numerous drainage slots 25 in the loading floor, the snout section top, bottom and sides 24, 22, 20, and the extruder section top, bottom and sides 30, 28, 26. A platen 80, pivotally mounted to the extruder top plate 30 near the exit of the device and biased with a constant pressure, controls the back pressure in the extruder and snout sections 14, 12. A first embodiment has a converging extruder section 14, having a narrower cross section at the exit of the section, which aids in compacting the material being dewatered. A second embodiment has a slightly diverging extruder section to prevent impaction of dewater material inside the device when operating with certain composite mixtures such as paper pulp.

1. Field of the Invention
This invention relates to compression-operated liquid extraction devices and, more particularly, to an extraction device having elongated drainage openings.
2. Description of Related Art
Batch process, compression-driven liquid extraction devices have been well known for many years. Existing devices compress wet waste in a compression chamber below a loading hopper. A hydraulic ram provides pressure to the wet waste. Drainage holes or grates in the sides of the compression chamber permit liquid to escape from the wet waste. Typically, the liquid is extracted directly under the loading hopper. A few designs provide a short extension of the compression chamber past the loading hopper to improve the liquid extraction efficiency. A door on the exit of the chamber is sometimes used to increase the back pressure and obtain a higher degree of compression.
The existing designs generally provide inadequate or incomplete moisture extraction for some important purposes. For example, the moisture content of paper pulp waste, after being processed through existing compression-driven extracting devices, typically exceeds 65% which is not acceptable for many landfills or incinerators. In addition, liquid in the remaining mass is largely unevenly distributed; there is more liquid remaining in the top and bottom of the mass than at the sides. With existing devices, liquid from inside the mass of wet waste must take a longer path to reach a drainage exit. To compensate, the grate design of existing devices provides additional area for drainage but allows a higher percentage of solids to escape with the liquid and also clog the grates. In addition, the grate design of existing devices is unsuitable for high-pressure service.

Apparatus for extracting liquid from a composite mass


The invention relates to a method of transmitting digital data exhibiting a rate T by means of a frequency modulator able to modulate as a function of the data, a central carrier frequency f0 at a first frequency value f0+¼T and/or a second frequency value f0−¼T. It comprises the step consisting in modulating the carrier frequency from one of the frequency values to the other during a time interval T, via successive frequency stages.

In the GPS system, the signal emitted by a satellite is coded and the time taken by the signal to reach the point to be located is used to determine the distance between this satellite and this point, preferably called the pseudo-distance so as to take account of synchronization errors between the clock of the satellite and that of the station. These synchronization errors are conventionally eliminated by calculation when the signals are received from at least four different satellites. The determination of the distance between the point to be located and several satellites makes it possible, knowing the geographical coordinates of the satellites, to calculate the coordinates of the point to be located, usually coordinates expressed as latitude, longitude and altitude in a fixed terrestrial reference frame.
To determine the precise position of a mobile (accuracy of from a centimeter to a meter, as the case may be), a so-called "differential GPS" procedure is used, which consists in using, at the level of the mobile, for the calculation of its position, the errors noted with regard to each pseudo-distance at the level of a so-called reference station of known position.
This procedure makes it possible to correct the position calculation errors due in particular to trajectory deformations and to propagation. These errors are corrected, for example, by comparing for the reference station its known position and its calculated position arising from the measurement of the propagation time between the satellite and the reference station.

Frequency modulator for digital transmissions


A jet boat comprising an engine-balance system, the engine-balance system comprising a first impeller and a second impeller, wherein water can be driven out of the first impeller for forward motion and water can be selectively driven out of the second impeller, regulated by a balance detecting device, wherein water from the second impeller can provide balance to the jet boat.

A jet boat is a boat propelled by a jet of water ejected from the back of the craft. Unlike a powerboat or motorboat that uses a propeller in the water below or behind the boat, a jet boat draws the water from under the boat into a water jet inside the boat where it passes through as series of impellers and stators (also known as stages), which increase the velocity of the water flow. The water jet delivers a high pressure push and expels the water (jet stream) through a nozzle at the rear of the jet boat either above or below the waterline, which pushes the boat forward. Steering is accomplished by moving this nozzle to either side, or less commonly, by small gates on either side that direct the jet stream. For reverse motion, a water jet will continue to pump normally, but a deflector is lowered into the jet stream leaving the nozzle. This deflector redirects thrust forces forward to provide reverse motion.
The present invention features an engine-balance system for a jet boat. The engine-balance system comprises a first impeller for providing forward motion and a second impeller for providing balance to the jet boat.
Without wishing to limit the present invention to any theory or mechanism, it is believed that the boat of the present invention provides controlled operation for minimal resistance, a smooth car-like ride, and comfort for the occupants. The jet boat of the present invention may also provide comfort for the occupants by protecting them from hot or cold temperatures as well as splashing water while riding.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.


The present invention is related to patent-related tools, and methodologies involving those tools, for assisting in all stages of the merger and acquisition process. The IPAM server may be used in conjunction with the tools and methodologies to aid in the merger and acquisition process. These tools or methods include, but are not limited to, a topographic map, a technology classification, a SIC classification, a radar diagram, a patent citation tree, a citation root tree, a citation count report, a citation frequency graph, a citation frequency report, a patent count/year, an application count/year, a patent aging graph, a U.S. primary class/subclass, an international patent class, an assignee patent count report by primary class/subclass, a patent count graph by number of patents, a top assignees primary class/subclass by percent of total, a months to issue patents, a features grouping, a document annotation, an inventor patent count/assignee, an inventor patent count graph, and inventor data.

1. Field of the Invention
The invention is generally directed to methodologies related to the merger and acquisition process, and more particularly directed to patent-related tools and methodologies involving those tools for assisting in all stages of the merger and acquisition process.
2. Related Art
The merger and acquisition process typically goes through a variety of stages before Company A and Company B come to an agreement regarding the merger of the two, or the acquisition of one of the companies. A flowchart, as shown in FIG. 1, is the classic way to look at the merger and acquisition process. FIG. 1 illustrates that the merger and acquisition process may have, but is not limited to, four (4) stages. The four stages include an identify potential targets stage 102, an evaluate/analyze stage 104, a due diligence stage 106 and a negotiation/consummation/integration stage 108 (hereafter "negotiation stage 108").
Prior to Company B even considering a merger and/or acquisition of another company, Company B determines that it needs growth and/or profits. Once this is determined, Company B may decide to consider a merger and/or acquisition of another company to satisfy its desired growth and/or profits. Management of Company B then sets relationship/selection criteria for any merger or acquisition of another company it will consider.
The first stage in the merger and acquisition process is the identify potential targets stage 102. Here, the management of Company B has set the relationship/selection criteria for any merger and/or acquisition of another company it will consider.
The second stage is the evaluate/analyze stage 104. Here, various companies are evaluated and analyzed for Company B to approach for possible mergers and/or acquisitions. The management of Company B will make one or more recommendations of other companies to approach for a merger and/or acquisition.
The next stage is the due diligence stage 106. Here, due diligence is conducted on each of the companies the management of Company B made a recommendation on in the evaluate/analyze stage 104.
The final stage is the negotiation stage 108. In this stage, Company B conducts negotiations and/or consummation and/or integration of one or more companies that passed due diligence in the due diligence stage 106. The outcome of this stage is the possible merger or acquisition of another company that Company A has determined will satisfy its desire for growth and/or profit.
It is possible to facilitate, expedite, and enhance the merger and acquisition process by building upon work that has been performed in the past. However, there are little if any automated tools for assisting in this process. There are even less automated tools that utilize patent-related tools for assisting in the merger and acquisition process.

Patent-related tools and methodology for use in the merger and acquisition process


A magnetic element that can be used in a memory array having high density includes a pinned layer, a half-metallic material layer, a spacer (or a barrier) layer and a free layer. The half-metallic material layer is formed on the pinned layer and preferably has a thickness that is less than about 100 Å. The half-metallic material layer can be formed to be a continuous layer or a discontinuous on the pinned layer. The spacer (or barrier) layer is formed on the half-metallic material layer, such that the spacer (or barrier) layer is nonmagnetic and conductive (or insulating). The free layer is formed on the spacer (or barrier) layer and has a second magnetization that changes direction based on the spin-transfer effect when a write current passes through the magnetic element.

1. Field of the Invention
The invention relates to magnetic memory systems. More particularly, the present invention relates to a method and system for providing an element that employs a spin-transfer effect in switching and that can be used in a magnetic memory, such as a magnetic random access memory ("MRAM").
2. Description of the Related Art
Magnetic memories are used for storing data. One type of memory element of interest utilizes magnetoresistance properties of a magnetic element for storing data. FIGS. 1A and 1B respectively depict cross sectional views of a conventional spin valve magnetic element 100 and a conventional spin tunneling junction magnetic element 100′. As shown in FIG. 1A, conventional spin valve magnetic element 100 includes a conventional antiferromagnetic (AFM) layer 102, a conventional pinned layer 104, a conventional spacer layer 106, and a conventional free layer 108. Conventional pinned layer 104 and conventional free layer 108 are ferromagnetic. Conventional spacer layer 106 is nonmagnetic and is conductive. AFM layer 102 is used to fix, or pin, the magnetization of the pinned layer 104 in a particular direction. The magnetization of free layer 108 is free to rotate, typically in response to an external field.
Portions of conventional spin tunneling junction magnetic element 100′ are analogous to conventional spin valve magnetic element 100. Accordingly, conventional spin tunneling junction magnetic element 100′ includes an AFM layer 102′, a conventional pinned layer 104′, an insulating barrier layer 106′ and a free layer 108′, as shown in FIG. 1B. Conventional barrier layer 106′ is thin enough for electrons to tunnel through.
Depending upon the orientations of the magnetizations of free layer 108 (or 108′) and pinned layer 104 (or 104′), the resistance of conventional magnetic element 100 (or 100′) changes. For example, when the magnetizations of free layer 108 and pinned layer 104 are parallel, the resistance of conventional spin valve 100 is low. When the magnetizations of free layer 108 and pinned layer 104 are antiparallel, the resistance of conventional spin valve 100 is high. Similarly, when the magnetizations of free layer 108′ and pinned layer 104′ are parallel, the resistance of conventional spin tunneling junction 100′ is low. When the magnetizations of free layer 108′ and pinned layer 104′ are antiparallel, the resistance of conventional spin tunneling junction 100′ is high.
In order to sense the resistance of either conventional magnetic element 100 or 100′, current is driven through the magnetic element. For conventional magnetic element 100, current can be driven through the magnetic element 100 in one of two configurations: current-in-plane (CIP) and current-perpendicular-to-the-plane (CPP). For conventional spin tunneling junction 100′, however, current is driven through conventional spin tunneling junction 100′ using only the CPP configuration. For the CIP configuration, current is driven parallel to the layers of conventional spin valve 100. Thus, as viewed in FIG. 1A, current is driven from left to right or right to left for the CIP configuration. For the CPP configuration, current is driven perpendicular to the layers of conventional magnetic element 100 (or 100′). Accordingly, as viewed in FIG. 1A or 1B, current is driven up or down for the CPP configuration. The CPP configuration is used in MRAM having a conventional spin tunneling junction 100′ in a memory cell.
FIG. 2 depicts a conventional memory array 200 using conventional memory cells 220. Each conventional memory cell 220 includes a conventional magnetic element 100 (or 100′). Conventional array 200 is shown having four conventional memory cells 220, which are typically spin tunneling junction magnetic elements 100′. As shown in FIG. 2, each memory cell 220 includes a conventional spin tunneling junction 100′ and a transistor 222. Memory cells 220 are coupled to a reading/writing column selection 230 via bit lines 232 and 234 and to row selection 250 via word lines 252 and 254. Write lines 260 and 262, which are also depicted in FIG. 2, carry currents that generate external magnetic fields for the corresponding conventional memory cells 220 during writing. Reading/writing column selection 230 is coupled to a write current source 242 and a read current source 240, which are each coupled to a voltage supply Vdd 248 via line 246.
In order to write to conventional memory array 200, a write current Iw 242 is applied to bit line 232 (or 234), which is selected by reading/writing column selection 230. A read current Ir 240 is not applied. Both word lines 252 and 254 are disabled, and transistors 222 in all memory cells 220 are disabled. Additionally, one of the write lines 260 and 262 corresponding to the selected memory cell 220 carries a current used to write to the selected memory cell. The combination of the current in write line 260 (or 262) and the current in bit line 232 (or 234) generates a magnetic field that is large enough to switch the direction of magnetization of free layer 108′ of the selected cell and thus write to the selected cell. Depending upon the data written to the selected cell, the resulting resistance of the conventional magnetic tunneling junction 100′ will be high or low. When reading from a selected cell 220 in array 200, a read current Ir 240 is applied instead. The memory cell selected for reading is determined by row selection 250 and column selection 230. The output voltage of the selected cell is read at output line 244.
Although conventional magnetic memory 200 using conventional spin tunneling junctions 100′ can function, there are obstacles at higher memory cell densities. In particular, conventional memory array 200 is written using an external magnetic field that is generated by currents driven through bit line 232 (or 234) and write line 260 (or 262). That is, the magnetization of free layer 108′ is switched by the external magnetic field that is generated by currents driven through bit line 232 (or 234) and the write line 260 (or 262). The magnetic field required to switch the magnetization of free layer 108′, known as the switching field, is inversely proportional to the width of the conventional magnetic element 100′. As a result, the switching field increases for conventional memories having smaller magnetic elements 100′. Because the switching field is higher for a smaller magnetic element 100′, the required current that is to be driven through bit line 232 (or 234) and, in particular, through write line 260 (or 262) increases dramatically for a higher magnetic memory cell density. This relatively large current can cause a host of problems in a conventional magnetic memory array 200. For example, cross talk and power consumption increases accordingly. Additionally, the driving circuits required for driving the current that generates the switching field at a selected memory cell 220 also increase in physical area and complexity. Furthermore, the conventional write currents must be sufficiently large to switch a magnetic memory cell, but not so large that neighboring cells are inadvertently switched. The upper limit on the magnitude of the write current can lead to reliability issues because cells that are relatively harder to switch than others based on fabrication and material non-uniformity will fail to write consistently.
To overcome some of the obstacles associated with high-density magnetic memories described above, a recently discovered phenomenon, the spin-transfer effect, has been utilized. Details of the spin-transfer effect (and the spin-injection method) are disclosed in J. C. Slonczewski, "Current-driven Excitation of Magnetic Multilayers," Journal of Magnetism and Magnetic Materials, Vol. 159, pp. L1–L5 (1996); L. Berger, "Emission of Spin Waves by a Magnetic Multilayer Traversed by a Current," Phys. Rev. B, Vol. 54, p. 9353 (1996), and in F. J. Albert et al., "Spin-polarized Current Switching of a Co Thin Film Nanomagnet," Appl. Phys. Lett., vol. 77, No. 23, pp. 3809–3811 (2000), each of which is incorporated by reference herein.
The spin-transfer effect offers an alternative switching mechanism that has the advantage of being highly localized. In a multilayer structure consisting of ferromagnetic (or ferrimagnetic) layers that are separated by non-magnetic conducting spacer or an insulating barrier, spin transfer refers to the transferring of spin-angular momentum from the spin-polarized conduction electrons, via quantum-mechanical exchange field, into a ferromagnetic (or ferrimagnetic) layer when an electric current is driven across the multilayers. The spin-transfer effect causes the magnetization vector of the affected ferromagnetic layer to rotate. At high enough current, such a rotation can grow sufficiently large to produce switching (i.e. 180° of rotation). Successful application of the spin-transfer effect to magnetic switching has been demonstrated. Spin-transfer switching has been achieved in a simple giant-magnetoresistance (GMR) spin-transfer structure consisting of Co[thick]/Cu/Co[thin] layers where the Cu layer serves as a spacer separating the two magnetic layers. See, for example, F. J. Albert et al., "Spin-polarized current switching of a Co thin film nanomagnet," Appl. Phys. Lett., vol. 77, No. 23, pp. 3809–3811 (2000) and J. Grollier et al. "Spin-polarized current induced switching in Co/Cu/Co pillars," Applied Physics Letters, Vol. 78, No. 23, p. 3663–3665 (2001). If the thickness of the Cu layer is much less than the spin relaxation length, electrons traveling across the Cu layer retain much of their spin polarization. When electrons travel from the thick to the thin Co layer (with the current flowing in the opposite direction), the thick Co layer serves as a spin reservoir that injects spins into the thin Co layer. Transfer of spin-angular momentum causes the magnetization of the thin Co layer to align parallel to that of the thick Co layer.
When electrons travel from the thick to the thin Co layer, on the other hand, electrons having spins that are parallel to the magnetization direction of the thick Co layer pass without much scattering through the thick Co, but electrons having antiparallel spins are reflected. The reflected antiparallel spins cause the magnetization of the thin Co layer to align antiparallel to the magnetization of the thick Co layer. Thus, by changing the flow direction of the spin-polarized current, the magnetization of the thin Co layer can be repeatedly switched to be parallel and antiparallel.
The spin-transfer effect can be used in a CPP configuration as an alternative to or in addition to using an external switching field to switch the direction of magnetization of free layer 108 (or 108′) of a conventional spin valve 100 (or a conventional spin tunneling junction 100′). The spin-transfer effect dominates other mechanisms and thus becomes observable when the dimensions of conventional magnetic element 100 (or 100′) are small, in the range of few hundred nanometers. Consequently, the spin-transfer effect is suitable for higher density magnetic memories having smaller magnetic elements 100 (or 100′).
For example, switching the magnetization of a conventional free layer 108 in conventional spin valve 100 using spin transfer can be carried out as follows. Current can be driven from conventional free layer 108 to conventional pinned layer 104 to switch the magnetization of conventional free layer 108 so that it is parallel to the magnetization of conventional pinned layer 104. The magnetization of conventional free layer 108 is assumed to be initially antiparallel to conventional pinned layer 104. When current is driven from conventional free layer 108 to conventional pinned layer 104, conduction electrons travel from conventional pinned layer 104 to conventional free layer 108. The majority electrons traveling from conventional pinned layer 104 have their spins polarized in the same direction as the magnetization of conventional pinned layer 104 and interact with the magnetic moments of conventional free layer 108 near the interface between conventional free layer 108 and conventional spacer layer 106. As a result, the electrons transfer their spin-angular momentum to conventional free layer 108. Thus, angular momentum corresponding to spins that are antiparallel to the magnetization of conventional free layer 108 (and parallel to conventional pinned layer 104) is transferred to the conventional free layer. If the electrons transfer sufficient angular momentum, the magnetization of conventional free layer 108 is switched to be parallel to the magnetization of conventional free layer 104.
Alternatively, current can be driven from conventional pinned layer 104 to conventional free layer 108 to switch the magnetization of conventional free layer 108 to be antiparallel to the magnetization of conventional pinned layer 104. In this situation, the magnetization of free layer 108 is assumed to be initially parallel to the magnetization of pinned layer 104. When current is driven from conventional pinned layer 104 to conventional free layer 108, conduction electrons travel in the opposite direction. The majority electrons have their spins polarized in the direction of magnetization of conventional free layer 108, which is originally magnetized in the same direction as conventional pinned layer 104. The majority electrons are transmitted through conventional pinned layer 104. The minority electrons, however, which have spins that are polarized antiparallel to the magnetization of conventional free layer 108 and conventional pinned layer 104, will be reflected from conventional pinned layer 104 and travel back to conventional free layer 108. The minority electrons reflected by conventional pinned layer 104 interact with magnetic moments of conventional free layer 108 and transfer at least a portion of their spin-angular momentum to conventional free layer 108. If the electrons transfer sufficient angular momentum to conventional free layer 108, the magnetization of free layer 108 is switched to be antiparallel to the magnetization of conventional pinned layer 104.
In the CPP configuration, therefore, a current driven through a conventional magnetic element 100 (or 100′) can switch the direction of magnetization of free layer 108 (or 108′) using the spin-transfer effect. That is, the spin-transfer effect can be used to write to magnetic element 100 (or 100′) in a magnetic memory by driving a current through a conventional magnetic element 100 (or 100′) in a CPP configuration. Thus, writing using the spin-transfer effect is more localized and, consequently, generates less cross talk. Spin-transfer effect is also more reliable because spin-transfer results in a high effective field in a conventional magnetic element 100 (or 100′) in a device, such as MRAM. Additionally, for a magnetic element 100 (or 100′) having a small enough size, the current required to switch the magnetization using the spin-transfer effect can be significantly less than the current required to generate a switching field in conventional magnetic memory array 200. Accordingly, there is less power consumption when writing.
Although the spin-transfer effect can be advantageously used to switch the direction of the magnetization of conventional free layer 108 (or 108′), there are barriers to using the spin-transfer effect for a conventional magnetic element 100 (or 100′) in a memory. For a conventional spin valve magnetic element 100, the CPP configuration results in a significantly reduced signal. For example, the magnetoresistance ratio for the CPP configuration of a conventional spin valve 100 is only approximately two percent. Moreover, the total resistance of a conventional spin valve magnetic element 100 is low. Thus, the read signal output by a conventional spin valve magnetic element 100 is very low. Consequently, although the spin-transfer effect can be used to write to a conventional spin valve magnetic element 100, the output signal when reading from the conventional spin valve 100 is so low that it is difficult to use a conventional spin valve magnetic element 100 in a magnetic memory that is written using the spin-transfer effect.
On the other hand, a conventional spin tunneling junction magnetic element 100′ has a large resistance-area product (Ra) that is typically on the order of kΩ μm2. The high current density that is required for inducing the spin-transfer effect, however, could destroy the thin insulating barrier due to ohmic dissipation. Moreover, the spin-transfer effect has not been observed in a conventional spin tunneling junction magnetic element 100′ at room temperature. Thus, an MRAM having conventional spin tunneling junction magnetic elements 100′ that have a high Ra value may not be able to be used with the spin-transfer effect for writing to the magnetic memory cells.
As used herein, the term "spin-transfer stack" is defined to be any two-terminal multilayer structure that utilizes the spin-transfer effect for switching the magnetization of a ferromagnetic (ferrimagnetic or sperimagnetic) layer. The term "two-terminal multilayer structure (or device)", as used herein, is defined to be a multilayer structure (or device) that has one bottom lead in contact with a bottom layer of a multilayer structure and one top lead in contact with a top layer of the multilayer structure, and with current driven between the bottom and top lead through the multilayer structure. In contrast, U.S. Pat. No. 5,695,864 to Slonczewski discloses a three-terminal device using spin-transfer for switching. The structure and operational principles of such a three terminal device are different from the spin-transfer stack devices described herein. All spin-transfer stack devices referred to herein will be assumed to be two-terminal, unless otherwise noted.
To date, several types of two-terminal spin-transfer stack devices have been proposed. A first type of two-terminal spin-transfer stack device is referred to herein as a single-spacer spin-transfer stack device. A second type of two-terminal spin-transfer stack device is referred to herein as a single-barrier & dual barrier spin-transfer stack device. A third type of two-terminal spin-transfer stack device is referred to herein as a spacer-barrier spin-transfer stack device.
An exemplary single-spacer spin-transfer stack device is formed having a fixed magnetic layer/Cu spacer/Free magnetic layer. Variations of a single-spacer spin-transfer stack device include additions of antiferromagnetic layers for pinning and synthetic layers (such as CoFe[20A]/Ru[8,4A]/CoFe[22A]) for reducing magnetostatic coupling between the layers. The single-spacer spin-transfer stack type suffers numerous disadvantages, including an extremely small signal, a low resistance, and a high switching current.
An exemplary single-barrier stack device is formed having a Fixed magnetic layer/Tunnel barrier/Free magnetic nanoparticle. See, for example, U.S. Pat. No. 6,256,223 to Sun. An exemplary dual-barrier stack device is formed having a Fixed magnetic layer/Tunnel barrier/Free magnetic nanoparticle/Tunnel barrier/Fixed magnetic layer. See, for example, U.S. Pat. No. 6,256,223 to Sun. Variations to this type of two-terminal spin-transfer stack device include additions of antiferromagnetic layers for pinning and synthetic layers for reducing magnetostatic coupling between the layers. The single-barrier and dual-barrier spin-transfer stack devices suffer from numerous disadvantages, including an extremely high resistance, a high switching current, an unreliable method of fabrication, and a lack of working experimental evidence of spin-transfer effect switching across tunnel barrier(s) at room temperature.
An exemplary spacer-barrier stack device is formed having a Fixed magnetic layer/Conducting spacer/Free magnetic layer/Low-resistance tunnel barrier/Fixed magnetic layer. See, for example, copending and co-assigned U.S. patent application Ser. No. 10/213,537, filed Aug. 6, 2002, entitled Off-Axis Pinned Layer Magnetic Element Utilizing Spin Transfer And An MRAM Device Using The Magnetic Element, which is incorporated by reference herein. Variations to a spacer-barrier spin-transfer stack device include additions of antiferromagnetic layers for pinning and synthetic layers for reducing magnetostatic coupling between the layers. The spacer-barrier stack types address most of the problems of the other spin-transfer stack types. The low-resistance tunnel barrier significantly increases the read signal, but yet keeps the total stack resistance low. Unlike spin-transfer switching across a tunnel barrier, spin-transfer switching across a conducting spacer at room temperature has been experimentally observed. Consequently, a spacer-barrier spin-transfer stack is guaranteed to switch because it contains a conducting spacer arrangement.
Giant magnetoresistive (GMR) and tunnel magnetoresistive (TMR) ratios are strongly dependent on the spin polarization P of the magnetic layers. Spin polarization P can be defined straightforwardly as the percentage of up (down) spins minus the percentage of down (up) spins in a ferromagnetic material at the Fermi level. Most common magnetic materials, such as Fe, Co, Ni and their alloys have a rather low P of less than 50%. Half-metals are ferromagnets having a very high P (approaching 100%) that are metallic in one spin orientation and insulating in the other spin orientation. Because of their potential application to GMR and TMR devices, half-metals recently have been actively researched. Some half-metallic materials that have been discovered are CrO2, Sr2FeMoO6, (La0.7Sr0.3)MnO3, Fe3O4, and NiMnSb, of which Fe3O4 has the highest Curie temperature resulting in very high spin polarization P at room temperature.
The low spin-polarization materials have a significant number of minority spins that have an orientation that is opposite to that of the majority spins, despite a display of permanent magnetization. When these low spin-polarization materials are used in magnetic layers in a spin-transfer stack, the spin-transfer effect is reduced as the transferred angular momentum from the minority spins negates much of the transferred angular momentum from the majority spins. As a result, the switching current must be large to induce switching. On the other hand, when high spin-polarization half-metallic materials are used as magnetic layers in a spin-transfer stack, the opposing angular momentum negation from the small (theoretically zero for a perfect half-metal) number of minority spins is also small, resulting in a small switching current requirement. The decrease in the switching current can be significant, i.e., by more than a factor of 5, when going from materials of spin polarization of 35% to materials of spin polarization of 80% assuming coherent electron scattering in the free magnetic layer. See, for example, J. C. Slonczewski, "Current-driven excitation of magnetic multilayers," Journal of Magnetism and Magnetic Materials, Vol. 159, L1–L7 (1995).
Previously, half-metals have been introduced, at least conceptually, for improving performance of spin valves and spin tunneling junctions. Typical improvement goals for the introduction of half-metals have been higher GMR and TMR ratios. Half-metals can be introduced in various forms, such as a total replacement of all non-half-metallic ferromagnetic layers, a partial replacement, a thin coating at the appropriate interfaces between the layers, and as thin film insertion within ferromagnetic layers. Introduction of half-metals to spin valves and spin tunneling junctions, however, provide devices that do not involve spin-transfer switching or writing.
Partial introduction of half-metals to single-spacer spin-transfer stack has also been proposed previously. U.S. Pat. No. 5,696,864 to Slonczewski discloses that all of the pinned and/or free magnetic layers in a single-spacer spin-transfer stack device can be replaced with high spin-polarization or half-metallic magnetic materials. Replacing a magnetic layer with a high spin-polarization of half-metallic material, though, can lead to problems related to the material characteristics of the new material. For instance, if the half-metallic material, such as Fe3O4, has extremely high resistivity, the total resistance of the spin-transfer stack would be extremely high, thereby resulting in a very small signal. The half-metallic material may also have large surface roughness that would affect the other layers in the spin-transfer stacks. Finally, if the half-metallic material has high magnetic anisotropy and coercivities (e.g., greater than 1000 Oe), the half-metallic material cannot be practically used for replacing the free layer.
Nevertheless, all of the spin-transfer stacks described above suffer from a high switching current. Consequently, what is needed is a way to reduce the high switching current exhibited by a conventional spin-transfer stack. Additionally, what is still needed is a magnetic memory element that can be used in a memory array having high density, that provides low power consumption, low cross talk, and has high reliability, while providing a useable read signal.

This patent is subject to a terminal disclaimer.

Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element


An optical apparatus has a holder which integrally holds a light source for emitting a divergent beam, and a finite focus lens (or a collimator lens) for converting the divergent beam to a convergent one (or a parallel one). The holder is made of a material having a linear expansion coefficient which can cause change of the distance between the light source and the finite focus lens so as to correct a change in the focal distance of the lens. When there is a change in temperature, the holder changes the distance between the light source and the finite focus lens by an amount corresponding to the change in temperature, thereby correcting that shift in the image forming position of the finite focus lens, which is caused by the change in temperature.

This invention relates to an optical apparatus, more particularly to a multi-beam optical scanning apparatus for performing scanning using plural beams, which is applicable to an image forming apparatus such as a color printer of a tandem type, a color copy machine of a tandem type, a high-speed laser printer and a digital copy machine, which have plural photosensitive drums.
Image forming apparatuses, such as color printers of a tandem type or color copy machines of a tandem type, which have plural photosensitive drums, each incorporate image forming sections corresponding to color components resulting from color separation, and an optical scanning apparatus, i.e. a laser exposure apparatus, for emitting plural laser beams associated with image data items for corresponding color components.
It is known that those image forming apparatuses include ones which have plural optical scanning devices associated with corresponding image forming sections, and ones which have a single optical scanning device adapted to emit plural laser beams to corresponding image forming sections.
In general, the optical scanning apparatus comprises plural semiconductor laser elements as a light source; a first lens group, i.e. a pre-deflection optical system, for converging beams emitted from the laser elements, to a predetermined diameter; a light-deflecting unit for continuously reflecting the beams converged by the first lens group, to a predetermined portion (i.e. an image surface) of a recording medium which is situated in a main scanning direction perpendicular to a sub-scanning direction in which a recording medium is transferred; and a second lens group, i.e. a post-deflection optical system, for converging the laser beams deflected by the light-deflecting unit so that the image surface of the recording medium will coincide with a line on which the laser beams are actually converged.
The pre-deflection optical system of the optical scanning apparatus includes a semiconductor laser, and a finite focus lens for converging a divergent beam emitted from the semiconductor laser, to a predetermined diameter, or a collimator lens for converting the laser beam to a parallel beam.
When the image forming apparatus with the optical scanning apparatus is used at a high temperature or a low temperature, or when the temperature of the image forming apparatus rises due to the heat generated therein, each lens in it may well be influenced by the heat. In this case, it is possible that the refraction index of the lens will vary to thereby vary its focal distance. A change in focal distance, due to a change in the refraction index of the finite focus lens or collimator lens for converging the divergent beam emitted from the semiconductor laser or converting it to a parallel beam, will increase the beam-spot diameter on a photosensitive drum incorporated in the image forming apparatus, thereby degrading the quality of an image formed on the drum.
In other words, the laser beam emitted from each semiconductor laser is usually converged by a group of lenses to a minimum diameter in an image formation position, i.e. on the photosensitive drum. However, if the focal distance of each lens increases or decreases to shift the focus from the image formation position, the beam-spot diameter on the photosensitive drum will increase, with the result that an image of a high resolution and quality cannot be obtained.
Moreover, in a multi-beam optical system for simultaneously deflecting plural laser beams, the corresponding light sources, finite focus lenses or collimator lenses are located in respective positions of different temperatures. Accordingly, the focal distance of each lens varies due to a change in ambient conditions, in particular, temperature, and hence the beam-spot diameters on the photosensitive drum will vary. As a result, the properties of the optical system will degrade, thereby degrading the quality of an image formed.


A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins. The operations to recolor the nets preferably include coloring a first pin of a child cell within a parent cell using a pin coloring operation that is a function of a device value of the child cell and a color of each of the pins of the child cell that are independently swappable with the first pin, but is independent of a color of a second pin of the child cell that is dependently swappable with the first pin.

This invention relates to the design, layout, testing and manufacture of microelectronic circuits and systems, and more particularly to apparatus and methods for verifying microelectronic circuits and systems prior to manufacture.
Present day ultra-large-scale integration (ULSI) circuits may include hundreds of thousands or millions of interconnected active electronic devices on an integrated circuit chip. The large capital investment required to fabricate and test large scale integrated circuits prior to sale to a customer and the difficulty, expense and loss of goodwill associated with reworking and replacing integrated circuits which fail to operate as planned, have increased the need to accurately characterize the electrical behavior of integrated circuits prior to their manufacture.
Moreover, now that submicron and deep-submicron (0.5 xcexcm and below) technologies have begun to dominate silicon chip manufacturing and the prospect of million-plus-gate chips operating at clock rates of 100 MHZ has become a reality, fundamental changes have had to be made to conventional integrated circuit design methodologies and the electronic design automation (EDA) tools based thereon. To meet the challenges posed by such large-scale circuits, techniques have been developed to represent integrated circuit designs at various levels of abstraction. According to these techniques, an integrated circuit design may be represented by an electrical schematic containing devices and nets interconnecting the devices and by geometric layout data that describes patterns of regions or elements to be formed in and/or on an integrated circuit substrate (e.g., wafer).
Techniques for managing highly integrated circuit designs include hierarchical design techniques. Using such techniques, a particular design is partitioned into functional cells and cells-within-cells, etc., so that at a given level of hierarchy the design may be analyzed as a set of cells and their respective interconnections, without being concerned with all the details of the contents of the cells (e.g., subcells within each cell).
These hierarchical techniques can be essential to the efficient performance of computer-assisted integrated circuit design verification. Such verification may include operations to perform layout versus schematic comparison (LVS) using computer-based design tools. As will be understood by those skilled in the art, tools to perform layout versus schematic comparison may include extraction software to extract a layout netlist from geometric layout data. An extracted layout netlist is then compared to an electrical schematic netlist to determine functional equivalence between the original integrated circuit schematic and the integrated circuit layout. One difficulty associated with the performance of these operations may be caused by a dissimilarity in the labeling of nets and devices in the extracted layout netlist relative to the electrical schematic netlist.
Conventional methods for determining correspondence between an electrical schematic netlist and a layout netlist are described in U.S. Pat. No. 5,249,133 to Batra entitled xe2x80x9cMethod for the Hierarchical Comparison of Schematics and Layouts of Electronic Componentsxe2x80x9d; U.S. Pat. No. 5,463,561 to Razdan entitled xe2x80x9cHigh Capacity Netlist Comparisonxe2x80x9d; and U.S. Pat. No. 5,243,538 to Okuzawa et al. entitled xe2x80x9cComparison and Verification System for Logic Circuits and Method Thereof.xe2x80x9d Another conventional method for determining correspondence includes operations to represent the electrical schematic netlist and the layout netlist as a schematic graph and a layout graph, respectively. Each of these graphs may be represented as bipartite graphs having vertices (also referred to herein as xe2x80x9cnodesxe2x80x9d) that represent devices and nets within their respective netlists. LVS software is then used to determine an isomorphism between the bipartite graphs.
The unambiguous determination of isomorphism between two arbitrary graphs may be a computationally intractable problem. To address this problem, heuristic methods for identifying graph isomorphisms with acceptable reliability and efficiency for ULSI designs have been developed. One generally established heuristic method is an iterative graph-coloring method described in articles by C. Ebeling and O. Zajicek entitled xe2x80x9cValidating VLSI Circuit Layout By Wirelist Comparison,xe2x80x9d Proceedings of ICCAD, pp. 172-173 (1983); and by C. Ebeling entitled xe2x80x9cGemini II: A Second Generation Layout Validation Program,xe2x80x9d IEEE ICCAD-88, Digest of Technical Papers, pp. 322-325, Nov. 7-10 (1988), the disclosures of which are hereby incorporated herein by reference. As described in these articles, an integer node value (color) is assigned to each node of a bipartite graph of the electrical schematic netlist and the extracted layout netlist, based on a graph invariant such as xe2x80x9cnumber of nearest neighborsxe2x80x9d (i.e., number of adjacent nodes/vertices). Each node is iteratively recolored as a function of the colors of its neighbors, until the maximum number of unique colors is achieved (i.e., an equilibrium state is achieved). Because these operations are independent of labeling, equivalent schematic and layout netlists generally will be represented by the same set of colors. A one-to-one correspondence may then be achieved by simply matching up each node in the schematic graph with a node in the layout graph that has the same color.
Unfortunately, some circuits may exhibit symmetry that may cause different nodes to receive the same color because the xe2x80x9cneighborhoodsxe2x80x9d associated with these nodes are similar. When two or more nodes have the same color, ambiguities in selecting matching nodes may arise. Typically, this situation is handled by making a guess as to which ones of the nodes in the schematic graph correspond to the same colored nodes in the layout graph, then assigning new colors to the matched nodes and then recoloring. If the guess was incorrect, a number of nodes may fail to match when the matching is applied at the next level of hierarchy, even though an alternate guess might have resulted in a complete one-to-one mapping.
For example, the AND-OR-INVERT (AOI) cell of FIG. 1 exhibits a number of symmetries with respect to input A because input A may be independently swapped with input B or input A may be swapped with input C if and only if input B is also swapped with input D. Similar symmetries also exist with respect to inputs B, C and D. FIG. 2 illustrates an original electrical schematic (S1) of the AOI cell and an extracted layout schematic (L1) of the AOI cell. FIG. 3 illustrates an original electrical schematic (S2) which contains the AOI cell S1 of FIG. 2 as a child cell and an extracted layout schematic (L2) which contains the AOI cell L1 of FIG. 2 as a child cell. As will be understood by those skilled in the art, verification of the schematics of FIG. 3 will only be concerned with the mapping of ports (W,X,Y,Z) of the AOI cell L1 of FIG. 2 to the ports (Q,R,S,T) of the schematic S2 of FIG. 2. However, because the symmetry of the design may cause the ports of each AOI child cell in FIG. 2 to acquire the same color when the schematic and layout graphs of the AOI child cells have been colored to an equilibrium state, a conventional LVS tool may make an arbitrary mapping which may be incorrect (e.g., Qxe2x86x92W, Rxe2x86x92Y, Sxe2x86x92X, Txe2x86x92Z). A consequence of this arbitrary mapping may be manifested at the next level of hierarchy.
For example, as illustrated by FIG. 3, an incorrect choice in the mapping of S1 to L1 (i.e., the child cells) may cause S2 and L2 (i.e., the parent cells) to be reported as nonequivalent after a coloring algorithm has been performed on the schematic and layout graphs at the parent level. Here, devices D1-D4 are distinct devices that are connected between the ports of the AOI xe2x80x9cchildxe2x80x9d cell and the ports of the xe2x80x9cparentxe2x80x9d cell. Thus, LVS software may report a mismatch between an original electrical schematic netlist and an extracted layout netlist, even though it is possible to make assignments among symmetric nodes that will result in a match. Typically, a consequence of this limitation in LVS software is that the software user must manually intervene by providing the LVS software with specific assignments to resolve ambiguities due to symmetry. Since it is not always clear where an erroneous guess was made, such manual intervention may be time consuming. For large and highly symmetric designs such as memories and gate arrays, these limitations may significantly reduce the utility of conventional LVS tools including hierarchical LVS tools using general-purpose graph isomorphism algorithms. In particular, the high degree of symmetry associated with large memories may force numerous arbitrary matchings or guesses to be made between layout and schematic. These guesses may preclude matching in the parent cells of the memories if the parent cells use permutations of the memory ports that are valid by virtue of the symmetries, but are inconsistent with the guesses.
To address some of these limitations associated with conventional verification tools, an LVS software tool 100 has been developed to determine equivalency between an integrated circuit schematic and an integrated circuit layout, using the operations 102-114 illustrated by the flow diagram of FIG. 4. This LVS software tool may be embodied in a commercially available product from the assignee of the present application, Avant! Corporation of Fremont, Calif. This software product, which is marketed under the tradename Hercules(trademark), is more fully described in an instruction manual by the same name, Release 2.1, January (1997), the disclosure of which is hereby incorporated herein by reference. In particular, the LVS software tool of FIG. 4 can perform the operations of generating a hierarchical electrical schematic netlist having at least one parent cell and a plurality of child cells in the parent cell, Block 102, and extracting a corresponding integrated circuit layout as a hierarchical layout netlist, Block 104. An operation is also performed to generate at least one color symmetrizing matrix corresponding to a child cell in the schematic netlist, Block 106. Here, the child cell may have a number of symmetries which, when taken alone or in combination, may result in a number of electrically equivalent permutations of the child cell. As illustrated by Block 108, operations are then performed to generate schematic and layout graphs of the parent cells in the schematic and layout netlists, respectively. These graphs are similar to the above-described bipartite graphs. The nodes in the schematic graph are then colored and a first color symmetry vector is generated for a child cell in the schematic graph. Similarly, the nodes in the layout graph are colored and a second color symmetry vector is generated for a child cell in the layout graph, Block 110.
An operation is then performed to determine an equivalency between the colors of the nodes in the schematic and layout graphs based on a selected permutation of the child cell in the layout graph, Block 112, and then an operation is performed to determine a vector equivalency between a product of the color symmetrizing matrix and the first color vector and a product of the color symmetrizing matrix and the second color vector, Block 114. Finally, a membership test is automatically performed at Block 116 to determine whether the selected permutation of the child cell can be derived from the valid symmetries associated with that child cell. As described in a textbook authored by G. Butler, entitled Fundamental Algorithms for Permutation Groups, Springer-Verlag, p. 144 (1991), a Furst-Hopcroft-Luks version of a Schreier-Sims method may be performed. Unfortunately, although the software tool of FIG. 4 typically requires no human intervention and works well with most designs exhibiting symmetry, the automatic performance of membership test to validate the accuracy of the matched layout and schematic may incur an unduly large computational expense and limit the applicability of the above software to large integrated circuit designs having large degrees of symmetry.
Thus, notwithstanding the above described attempts, there continues to be a need to provide verification tools which have the capability of automatically resolving ambiguities in symmetric circuits. Such tools should be conservative in the identification of graph isomorphism, in the sense that if any ambiguities remain after the verification operations are performed, a nonisomorphism result should be generated and the circuits should be designated as non-equivalent even if they may be equivalent. This is because the penalty for erroneously identifying equivalent circuits as nonequivalent (i.e., manual intervention by the user) is far less onerous than the penalty for misidentifying non-equivalent circuits as equivalent (i.e., the expense of prototyping and manufacturing an incorrect design).
It is therefore an object of the present invention to provide improved methods, apparatus and computer program products that can perform post-layout verification of microelectronic integrated circuits.
It is also an object of the present invention to provide improved methods, apparatus and computer program products that can perform layout versus schematic comparison of integrated circuits.
It is another object of the present invention to provide methods, apparatus and computer program products that can perform layout versus schematic comparison of hierarchical integrated circuits having symmetrical cells therein.
These and other objects, features and advantages can be provided, according to embodiments of the present invention, by preferred methods, apparatus and computer program products for determining equivalency between integrated circuit schematics and integrated circuit layouts. These methods, apparatus and computer program products are particularly useful as layout versus schematic (LVS) comparison tools when handling hierarchical designs that exhibit high degrees of overall symmetry and/or have large numbers of cells therein having symmetrical properties. These LVS tools preferably perform the operations of coloring a graph of an integrated circuit to an equilibrium state and then identifying a xe2x80x9cprovisionalxe2x80x9d swap group of nodes having the same color within the colored graph. The colored graph may be a colored layout graph or a colored schematic graph of the integrated circuit. The colored graph may be a colored bipartite graph having both net and device nodes therein. This xe2x80x9cprovisionalxe2x80x9d swap group of nodes corresponds to pins of a device that may be swappable by virtue of the fact that the nodes associated with the pins have the same color after a graph coloring operation has been performed. A new (e.g., unique) color is then assigned to a node within the identified swap group. An operation is then performed to recolor the layout graph (with the new colored node) until another equilibrium state has been achieved. During this recoloring operation, the node receiving the assigned color may be held at the assigned color. This recoloring operation may include operations to repeatedly partition nets and devices in alternating sequence until an equilibrium colored state is achieved. At this point, a determination of whether the swap group of nodes are independently swappable can be made by evaluating whether all the nodes within the swap group, with the exception of the node that received the assigned color, have the same color. If they do, then all the nodes in the swap group can be treated as independently swappable nodes.
Preferred embodiments of LVS comparison tools may also perform an operation of identifying at least one connected group within the swap group. This operation preferably comprises determining a first connected group of nodes as nodes within the swap group that are linked together (and to the node receiving the assigned color) by other nodes that have non-unique colors within the graph. Then, after the graph has been recolored to an equilibrium state, an operation can be performed to determine whether the nodes within the first connected group that did not received the assigned color all have the same color. If so, these nodes within the first connected group can be treated as being independently swappable (i.e., as their own swap group), even if all the nodes within the xe2x80x9cprovisionalxe2x80x9d swap group are not independently swappable.
Once nodes that belong to respective connected groups have been identified, subsequent or concurrent operations may also be performed to generate a first vector of first colors corresponding to a first swap group of nodes associated with a first child cell in an integrated circuit schematic graph having symmetric pins that include independently swappable pins and dependently swappable pins. Operations may also be performed to generate a second vector of second colors corresponding to a second swap group of nodes associated with a second child cell in an integrated circuit layout graph. These graphs may be graphs of first and second parent cells containing the first and second child cells, respectively, and nets connected to input nodes of the respective child cells. To resolve symmetries identified by the presence of duplicate colors within the first and second vectors, an assignment of a new color is made to a node within the first swap group of nodes in the schematic graph and a corresponding assignment is made to a node within the second swap group of nodes in the layout graph. This new color is preferably a unique color that is not within the first vector. This assignment of a new color to a node of a child cell is, when viewed at the parent level, actually an assignment of a color to a net that may be connected to one or more pins of a child cell(s). At the parent level, this net may be treated as a single node of the graph having a single color and each pin of a child cell that is connected to the net may be treated herein as having an effective xe2x80x9ccolorxe2x80x9d equal to the color of the net. Operations are then performed to generate a third vector of third colors corresponding to the first swap group by determining a new color for one of the nodes within the first swap group using a coloring operation that is a function of a device value of the first child cell and a color of another node in the first swap group. A fourth vector of fourth colors corresponding to the second swap group are also generated by determining a new color for one of the nodes within the second swap group using a coloring operation that is a function of a device value of the second child cell and a color of another node in the second swap group.
In particular, an embodiment of the operation to generate a third vector includes generating a new color for a first node in the first swap group using a coloring operation that is a function of a device value of the first child cell and., a respective color of each of the other nodes in the first swap group. To reduce computational expense, this node/pin coloring operation is independent of the colors of nodes that are dependently swappable with the first node. Similarly, the operation to generate a fourth vector includes generating a new color for a second node within the second swap group using a coloring operation that is a function of a device value of the second child cell and a respective color of each of the other nodes in the second swap group. Again, to reduce computational expense, this node coloring operation is independent of the colors of nodes that are dependently swappable with the second node. More preferably, the operation to generate a third vector comprises generating a new color for a node within the first swap group using the following relationship: New Color=Existing Node Colorxe2x88x92(Device Value)xc3x97(xcexa3 Colors of Other Nodes in Respective Swap Group). An identical relationship is also preferably used to generate a fourth vector.
Preferred coloring operations performed by LVS tools of the present invention may also include initially determining a first vector of first colors corresponding to a first swap group of nodes associated with a child cell in an integrated circuit layout graph and then assigning a unique node color not within the first vector of colors to a first node within the first swap group. Operations are then performed to generate a second vector of colors corresponding to the first swap group by generating a new color for the first node using the following relationship: New Color=Unique Node Colorxe2x88x92(Device Value of Child Cell)xc3x97(xcexa3 Colors of Other Nodes in the First Swap Group). Preferably, this relationship does not require the computational expense associated with conventional operations to generate a product of a color symmetrizing matrix and a vector of node colors for a child cell.
Operations to perform layout versus schematic comparison may also include operations to color a schematic graph of a parent cell to an equilibrium state and then recolor nets connected to first and second child cells having the same device value. The operation to recolor the nets preferably uses a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Operations are then performed to generate distinct device values for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins. These operations to determine distinct device values are preferably performed in order to prevent an incorrect mapping of these child cells in the schematic and layout during subsequent device coloring operations. These operations preferably include determining a new device color for one cell (e.g., AOI cell) in the schematic by evaluating a product of the symmetric pin colors. In particular, the new device value for the child cell can be determined using the following relationship: New Device Value=Old Device Value+Π (Colors of Symmetric Pins of Cell). Alternatively, the new device value may be determined as the product of the colors of the symmetric pins. As determined by the inventors herein, merely determining an algebraic sum of the colors of the symmetric pins may not distinguish the AOI cells during subsequent coloring operations.

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuits using advanced symmetry resolution techniques


The invention relates to a method for cleaning exhaust gases from a combustion engine, in which method humid air is fed into the combustion chamber of the combustion engine. In order to reduce nitrogen emissions effectively, particularly when a diesel engine is running at partial power, and in order for the method to be very accurately adjustable to meet the requirements of each particular engine application and use, in accordance with the invention, a mixture of gas and aqueous mist is fed with a spray head (3) into a space (2), which leads to the combustion chamber. The method can be readily implemented by an apparatus, which can be mounted in a small space without having to make substantial changes in the combustion engine. The invention also relates to an apparatus for cleaning exhaust gases from a combustion engine.

The invention relates to a method for cleaning exhaust gases from a combustion engine, in which method humid air is fed into a combustion chamber of the engine, whereby a mixture of gas and aqueous mist is fed with a spray head into a space that leads to the combustion chamber.
The invention also relates to an apparatus for feeding humid air into a combustion engine, the apparatus comprising a spray head for feeding aqueous mist into a space in the combustion engine, gas feeding means for feeding gas into the spray head, liquid feeding means for feeding aqueous liquid into the spray head and mixing means for providing a mixture of gas and aqueous mist from the spray head into said space, which is arranged to be in flow connection with the combustion chamber of the combustion engine and to supply the mixture of gas and aqueous mist into the combustion chamber. This kind of apparatus is known in connection with gas turbine engines, and the purpose of the apparatus is to prevent power and efficiency of the engine from declining when the temperature is high around the turbine, as is the case on hot days.
One aim of environmental protection is to reduce exhaust gas emissions from combustion engines. The present invention provides a solution, by which exhaust gas emissions from diesel engines, in particular, but also from other combustion engines will be reduced.
Exhaust gases from diesel engines contain various harmful combustion products, of which oxides of nitrogen, i.e. NOx, are the most harmful to the environment. The oxides of nitrogen considerably contribute to smog formation, green house effect and soil acidification as well as retard the growth of forests, for instance.
The diesel engines of ships are great polluters of air. According to an American study, published a few years ago, 14% of the nitrogen emissions in the world and 16% of the sulphur emissions originate from marine traffic. Soot/carbon emissions from the diesel engines, which are produced most when the engine runs at a low power level, also pose a problem. Considerable nitrogen emissions are also produced when the engine runs at a low power level. Typically, ship engines are run at a low power level when the ships are in ports, so the emissions are a considerable problem also when the ship is in port.
In diesel engines, nitrogen emissions can be reduced in a known manner by lowering the combustion temperature, whereby emissions are reduced while being produced. The combustion temperature can be lowered in a variety of ways. It can be lowered by injecting water into the combustion chamber or by using an aqueous emulsion in fuel.
According to some studies, injecting water into the combustion chamber may increase smoke emissions. Fuel consumption may also rise, if large amounts of water are injected into the engine. However, other studies show that the so-called HAM (Humid Air Motor) method, in which humid air is fed into the motor, yields good results regarding emissions. In this method the charge air of the diesel engine is humidified by an evaporator and the fuel burns in the engine cylinders in humid air instead of normal air. The HAM method has a drawback that the load capacity of the diesel engine is considerably reduced. A further drawback of the method is that water cannot be dispersed into sufficiently small drops in the evaporator, but the drops produced therein are relatively large, and consequently they do not vaporize quickly and readily. Quick vaporization of the drops is a prerequisite for lowering the emissions and making the engine run smoothly also in other respects.
The use of an aqueous emulsion in fuel reduces nitrogen oxides without that the amounts of carbon dioxides would increase. According to some studies, the obtained results are not so good as those obtained by a method, in which water is injected into the cylinders. However, a problem with the "aqueous emulsion method" is that a sufficient amount of water cannot be mixed with the fuel.
U.S. Pat. Nos. 4,459,943 and 4,411,224 disclose systems for feeding gas and water mist into the intake air of a combustion engine. The amount of gas and water mist are each increased directly proportionally to the load of the engine.
An alternative and also complementary method to air humidification is to remove exhaust gas nitrogen emissions with a catalytic converter. With the catalytic converter the oxides of nitrogen are reduced to nitrogen and water vapour by spraying a mixture of urea and water into the exhaust gases. The catalytic converters reduce nitrogen emissions efficiently but in naval applications they are very expensive: they cost about 30% of the engine price and in large engines even more than that. Moreover, in a ship the catalytic converter takes a lot of space and considerable operating costs are incurred from servicing, etc.

Method and apparatus for reducing combustion engine emissions


Nanoscale molecularly imprinted polymers (MIP) having polymer features wherein the size, shape and position are predetermined can be fabricated using an xy piezo stage mounted on an inverted microscope and a laser. Using an AMF controller, a solution containing polymer precursors and a photo initiator are positioned on the xy piezo and hit with a laser beam. The thickness of the polymeric features can be varied from a few nanometers to over a micron.

Molecular imprinting is a process for synthesizing polymeric materials that contain highly specific recognition sites for small molecules. The preparation of molecularly imprinted polymers is a process in which host-guest complexes are produced between a template or target molecule (T) and functional monomers (M). Referring to FIG. 1, these host-guest complexes are then fixed by copolymerization with an excess of cross-linking monomer. The template molecule is then removed from the polymer leaving behind voids within the matrix, which are complementary to the template molecule in size, shape and functional group orientation.
Either covalent and/or non-covalent forces such as hydrogen bonding, electrostatic and hydrophobic interactions enable the organization of functional monomers by the template. In addition, the use of metal coordination complexes as the template for polymer bound functionality has also been investigated.
These Molecularly Imprinted Polymers (MIPs) are to a large degree, thermally and chemical stable and have been shown to retain their recognition properties for several years without loss of selectivity or capacity. As a result, they have advantages over more fragile biological systems for molecular recognition and have been referred to as "plastic antibodies." Under the proper conditions, MIPs have shown the ability to function as selective binding materials capable of enantiomeric separations, micro-reactors, facilitated transport membranes and catalysts. While MIPs have been successful for a variety of applications, little if any regard has been given to surface confinement and miniaturization of these materials. Typically, MIPs are prepared by bulk polymerization that creates a polymer monolith, which is then ground to produce polymer particles. These particles are then used for a variety of applications such as chromatographic stationary phases, selective catalysts or as the recognition elements in chemical sensors.

Nanoscale molecularly imprinted polymers and method thereof

Lawrence Livermore National Security, LLC