An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a thin film transistor including a gate electrode of the gate line, a gate insulating layer over the gate electrode, an active layer on the gate insulating layer and ohmic contact layers on the active layer, and source and drain electrodes over the ohmic contact layers, a pixel electrode electrically connected to the drain electrode, a data line electrically connected to the source electrode and crossing the gate line, a common electrode spaced apart from the pixel electrode, and a passivation layer directly between the pixel electrode and the common electrode and directly between the source and drain electrodes.

1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are driven based on optical anisotropy and polarization characteristics of a liquid crystal material. Liquid crystal molecules have a long and thin shape, and the liquid crystal molecules are regularly arranged along in an alignment direction. Light passes through the LCD device along the long and thin shape of the liquid crystal molecules. The alignment of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment of the liquid crystal molecules changes, and images are displayed. Active matrix liquid crystal display (AMLCD) devices, which include thin film transistors as switching devices for a plurality of pixels, have been widely used due to their high resolution and ability to display fast moving images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer is interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face one another. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field. The direction of the electric field is perpendicular to the substrates. The LCD device has relatively high transmittance and a large aperture ratio. However, the LCD device may have a narrow viewing angle. To increase the viewing angle, various modes have been proposed. Among these wide angle viewing modes, an in-plane switching (IPS) mode LCD device of the related art will be described with reference to accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the IPS mode LCD device according to the related art includes a lower substrate 10 and an upper substrate 40, and a liquid crystal layer LC interposed between the lower substrate 10 and the upper substrate 40. A thin film transistor T, a common electrode 30 and a pixel electrode 32 are formed in each pixel P on the lower substrate 10. The thin film transistor T includes a gate electrode 14, a semiconductor layer 18, and source and drain electrodes 20 and 22. The semiconductor layer 18 is disposed over the gate electrode 14 with a gate insulating layer 16 therebetween. The source and drain electrodes 20 and 22 are formed on the semiconductor layer 18 and are spaced apart from each other. Each of the common electrode 30 and the pixel electrode 32 includes a plurality of patterns. The common electrode 30 and the pixel electrode 32 are spaced apart from and alternate with each other.
Although not shown in FIG. 1, a gate line is formed along a first side of the pixel P, and a data line is formed along a second side of the pixel P substantially perpendicular to the first side. A common line is further formed on the lower substrate 10. The common line provides the common electrode 30 with voltage.
The upper substrate 40 is spaced apart from the lower substrate 10. A black matrix 42 and a color filter layer including red and green color filters 34a and 34b are formed on an inner surface of the upper substrate 40. The color filter layer further includes a blue color filter (not shown). The black matrix 42 is disposed over the gate line, the data line and the thin film transistor T. The color filter layers 34a and 34b are each disposed in a respective pixel P.
The lower substrate 10, including the thin film transistor T, the common electrode 30 and the pixel electrode 32, may be referred to as an array substrate. Liquid crystal molecules of the liquid crystal layer LC are driven by a horizontal electric field 45 induced between the common electrode 30 and the pixel electrode 32. The upper substrate 40, including the black matrix 42 and the color filter layer 34a and 34b, may be referred to as a color filter substrate.
An array substrate for an IPS mode LCD device of the related art will be described with reference to FIG. 2. More specifically, FIG. 2 is a plan view schematically illustrating an array substrate for an IPS mode LCD device manufactured through 4 mask processes according to the related art. As shown in FIG. 2, a gate line 54 is formed along a direction on an insulating substrate 50. A data line 92 crosses the gate line 54 to define a pixel region P. A gate pad 56 is formed at one end of the gate line 54, and a data pad 92 is formed at one end of the data line 92. A common line 58 is spaced apart from and parallel to the gate line 54. The common line 58 is disposed along a side of the pixel region P. A gate pad terminal GP is formed on the gate pad 56 and contacts the gate pad 56. A data pad terminal DP is formed on the data pad 94 and contacts the data pad 94.
A thin film transistor T is formed adjacent to where the gate line 54 crosses the data line 92. The thin film transistor T includes a gate electrode 52, an active layer 84, an ohmic contact layer (not shown), and source and drain electrodes 88 and 90. The gate electrode 52 is connected to the gate line 54. The active layer 84 and the ohmic contact layer are sequentially disposed on the gate electrode 52. The source and drain electrodes 88 and 90 are disposed on the ohmic contact layer. The source electrode 88 is connected to the data line 92. An intrinsic amorphous silicon pattern 72 is disposed under the data line 92. The drain electrode 90 is spaced apart from the source electrode 88.
A pixel electrode PXL and a common electrode Vcom are formed in the pixel region P. The pixel electrode PXL contacts the drain electrode 90, and the common electrode Vcom contacts the common line 58. The pixel electrode PXL and the common electrode Vcom are spaced apart from each other.
In the array substrate for an IPS mode LCD device according to the related art, the source and drain electrodes 88 and 90, the data line 92 and the active layer 84 are formed through the same process. Therefore, the active layer 84 and the source and drain electrodes 88 and 90, and the intrinsic amorphous silicon pattern 72 and the data line 92 are sequentially layered, wherein the active layer 84 and the intrinsic amorphous silicon pattern 72 are exposed at sides of the source and drain electrodes 88 and 90 and the data line 92.
Here, the active layer 84 and the intrinsic amorphous silicon pattern 72 are exposed to light such that photocurrents may occur therein. The photocurrents in the active layer 84 act as leakage currents, which flow when the thin film transistor is OFF, and causes incorrect operation of the thin film transistor T. The photocurrents in the intrinsic amorphous silicon pattern 72 cause coupling with electrodes adjacent thereto, and liquid crystal molecules (not shown) are improperly arranged due to the coupling. Accordingly, a wavy noise occurs on displayed images. The off-currents in the thin film transistor and the appearance of wavy noise in the display typically occur in an LCD device in which the source electrode, drain electrode and the active layer are patterned through the same process.
FIGS. 3A to 3H, FIGS. 4A to 4H, FIGS. 5A to 5H, and FIGS. 6A to 6H illustrate processes of manufacturing an array substrate for an IPS mode LCD device according to the related art. FIGS. 3A to 3H are cross-sectional views along the line II-II of FIG. 2. FIGS. 4A to 4H are cross-sectional views along the line III-III of FIG. 2. FIGS. 5A to 5H are cross-sectional views along the line IV-IV of FIG. 2. FIGS. 6A to 6H are cross-sectional views along the line V-V of FIG. 2.
FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A show a first mask process. As shown in FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A, a switching region S, a pixel region P, a gate region G, a data region D, and a common signal region CS are defined on a substrate 50. A gate line 54 of FIG. 2 and a gate electrode 50 are formed on the substrate 50 including the regions S, P, G, D and CS. The gate line 54 is disposed in the gate region G and extends along a first direction. The gate line 54 includes a gate pad 56 at one end thereof. The gate electrode 52 is connected to the gate line 54 and is disposed in the switching region S. Simultaneously, a common line 58 is formed in the common signal region CS. The common line 58 is spaced apart from and parallel to the gate line 54.
The gate line 54, the gate pad 56, the gate electrode 52 and the common line 58 are formed by depositing one or more material selected from a conductive metallic group including aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo). The gate line 54, the gate pad 56, the gate electrode 52 and the common line 58 may be a single layer of the above-mentioned metallic material or may be a double layer of aluminum (Al)/chromium (Cr) or aluminum (Al)/molybdenum (Mo).
FIGS. 3B to 3F, FIGS. 4B to 4F, FIGS. 5B to 5F and FIGS. 6B to 6F show a second mask process. As shown in FIG. 3B, FIG. 4B, FIG. 5B and FIG. 6B, a gate insulating layer 60, an intrinsic amorphous silicon layer (a-Si:H) 62, an impurity-doped amorphous silicon layer (n+ or p+ a-Si:H) 64, and a conductive metallic layer 66 are formed over the entire surface of the substrate 50, including the gate line 54, the gate pad 56, the gate electrode 52 and the common line 58. The gate insulating layer 60 is formed by depositing one or more material selected from an inorganic insulating material group, including silicon nitride (SiNx) and silicon oxide (SiO2). The conductive metallic layer 66 is formed by depositing one or more material selected from the above-mentioned conductive metallic group.
A photoresist layer 68 is formed by coating the entire surface of the substrate 50, including the conductive metallic layer 66 with photoresist. A mask M is disposed over the photoresist layer 68. The mask M includes a light-transmitting portion B1, a light-blocking portion B2, and a light-half transmitting portion B3. The light-transmitting portion B1 transmits substantially all light. The photoresist layer 68 below the light-transmitting portion B1 is entirely exposed to light to thereby chemically change. The light-blocking portion B2 completely blocks the light. The light-half transmitting portion B3 includes slits or a half transparent layer to decrease the intensity of light or transmittance of the light. Thus, the photoresist layer is partially exposed to light through the light-half transmitting portion B3.
The light-half transmitting portion B3 is disposed over the gate electrode 52 in the switching region S. The light-blocking portion B2 is disposed over the photoresist layer 68 in the switching region S and in the data region D. In the switching region S, the light-blocking portion B2 is disposed at both sides of the light-half transmitting portion B3. The light-transmitting portion B1 is disposed in other regions except form the switching region S and the data region D. The photoresist layer 68 is exposed to light through the mask M and then is developed.
Referring to FIG. 3C, FIG. 4C, FIG. 5C and FIG. 6C, first and second photoresist patterns 70a and 70b are formed in the switching region S and the data region D, respectively. The first photoresist pattern 70a has a first portion corresponding to the gate electrode 52 and a second portion corresponding to the switching region S except form the gate electrode 52. The second portion is thicker than the first portion.
Next, the conductive metallic layer 66, the impurity-doped amorphous silicon layer 64, and the intrinsic amorphous silicon layer 62 are selectively removed by using the first and second photoresist patterns 70a and 70b as an etching mask. The conductive metallic layer 66 may be removed simultaneously with the under layers 64 and 62 according to a material of the conductive metallic layer 66. Alternatively, the conductive metallic layer 66 may be wet-etched. Then, the impurity-doped amorphous silicon layer 64 and the intrinsic amorphous silicon layer 62 may be dry-etched.
As shown in FIG. 3D, FIG. 4D, FIG. 5D and FIG. 6D, a first metallic pattern 78 and a second metallic pattern 82 are formed under the first and second photoresist patterns 70a and 70b, respectively. A first semiconductor pattern 76 and a second semiconductor pattern 80 are formed under the first metallic pattern 78 and the second metallic pattern 82, respectively. Each of the first and second semiconductor patterns 76 and 80 includes an intrinsic amorphous silicon pattern 72 and an impurity-doped amorphous silicon pattern 74.
As shown in FIG. 3E, FIG. 4E, FIG. 5E and FIG. 6E, an ashing process is performed to remove a first portion of the first photoresist pattern 70a corresponding to the gate electrode 52, and the first metallic pattern 78 corresponding to the gate electrode 52 is exposed. At this time, other parts of the first photoresist pattern 70a and the second photoresist pattern 70b are also partially removed. The first and second metallic patterns 78 and 82 are partially exposed at peripheries of the first and second photoresist patterns 70a and 70b. Then, the exposed first metallic pattern 78 and the impurity-doped amorphous silicon pattern 74 of the first semiconductor layer 76 are removed.
Referring to FIG. 3F, FIG. 4F, FIG. 5F and FIG. 6F, a source electrode 88, a drain electrode 90 and a data line 92 are formed. The data line 92 is formed in a second direction crossing the first direction. A data pad 94 is formed at one end of the data line 92. The intrinsic amorphous silicon pattern 72 of the first semiconductor pattern 76 of FIG. 3E over the gate electrode 52 functions as an active layer 84, and the impurity-doped amorphous silicon pattern 74 of the first semiconductor pattern 76 of FIG. 3E, which is now divided into two parts, acts as an ohmic contact layer 86. When the impurity-doped amorphous silicon pattern 74 of the first semiconductor pattern 76 of FIG. 3E is partially removed, the intrinsic amorphous silicon pattern, i.e., the active layer 84, is over-etched so that particles may not remain on the surface of the active layer 84. Next, the photoresist patterns 70a and 70b are removed.
FIG. 3G, FIG. 4G, FIG. 5G and FIG. 6G show a third mask process. As shown in FIG. 3G, FIG. 4G, FIG. 5G and FIG. 6G, a passivation layer 96 is formed substantially over an entire surface of the substrate 50, including the source and drain electrodes 88 and 90 and the data line 92 including the data pad 94. The passivation layer 96 may be formed by depositing one selected from an inorganic insulating material group, including silicon nitride (SiNx) and silicon oxide (SiO2). Alternatively, the passivation layer 96 may be formed by coating the substrate 50 with one selected from an organic insulating material group, including benzocyclobutene (BCB) and acrylic resin.
Subsequently, the passivation layer 96 is patterned to thereby form a drain contact hole 98a, a common line contact hole 98b, a gate pad contact hole 98c, and a data pad contact hole 98d. The drain contact hole 98a partially exposes the drain electrode 90. The common line contact hole 98b partially exposes the common line 58. The gate pad contact hole 98c partially exposes the gate pad 56. The data pad contact hole 98d partially exposes the data pad 94.
FIG. 3H, FIG. 4H, FIG. 5H and FIG. 6H show a fourth mask process. As shown in FIG. 3H, FIG. 4H, FIG. 5H and FIG. 6H, a pixel electrode PXL and a common electrode Vcom are formed in the pixel region P by depositing one selected from a transparent conductive metallic group, including indium tin oxide (ITO) and indium zinc oxide (IZO), on the substrate 650 including the passivation layer 96, and then patterning it. The pixel electrode PXL contacts the drain electrode 90, and the common electrode Vcom contacts the common line 58. Each of the pixel electrode PXL and the common electrode Vcom includes a plurality patterns parallel to the data line 92. The common electrode Vcom alternates with the pixel electrode PXL. A gate pad terminal GP and a data pad terminal DP are formed simultaneously with the pixel electrode PXL and the common electrode Vcom. The gate pad terminal GP contacts the gate pad 56. The data pad terminal DP contacts the data pad 94.
The array substrate for an IPS mode LCD device may be manufactured through the above-mentioned four mask processes. Since the active layer and the source and drain electrodes are formed through the same process, the manufacturing costs and time can be reduced. The probability that problems may occur also decreases. However, in the array substrate manufactured through four mask processes, the second semiconductor pattern 80 is formed under the data line 92, and the intrinsic amorphous silicon pattern 72 of the second semiconductor pattern 80 is exposed at sides of the data line 92. As stated above, the exposed intrinsic amorphous silicon pattern 72 is affected by light and causes wavy noise in images that are displayed. In addition, the active layer 84 also goes beyond the gate electrode 52 and is exposed to light. Thus, photocurrents in the active layer 84 occur which cause the thin film transistor works incorrectly.

Array substrate for liquid crystal display device and method of manufacturing the same


Text messages with alphanumeric addresses are delivered to mobiles and external short message entities (ESMEs) which do not support alphanumeric addressing, providing meaningful fallback handling. Additionally, the invention enables delivery of SMPP messages from ESME or SMPP networks which can only originate numeric addresses, yet provide for mapping to alphanumeric addresses for delivery to the mobile. A two-way mapping is provided between alphanumeric addresses and SMS short-codes to enable delivery of text messages with alphanumeric addressing in networks which contain mobiles and/or ESME's that lack support of alphanumeric addressing. An ESME can send a text message using an alphanumeric origination address, without knowing which handsets support the capability, and which do not, or whether handsets are on CDMA, or GSM, or UMTS, or networks, or can continue to send using a numeric origination address. The SMSC provides conversions to alphanumeric addresses on behalf of the ESME and the mobile.

1. Field of the Invention
This invention relates generally to telecommunications. More particularly, it relates to wireless based technologies.
2. Background of the Related Art
When a short message service center (SMSC) operates in a long term evolution (LTE)/CDMA (or GSM/CDMA, or UMTS/CDMA) dual mode network, the vast majority of GSM, UMTS and LTE mobiles support alphanumeric addressing where as many or most CDMA mobiles may not. This impacts the display of the originator of the message to the end-user of the mobile phone (or conversely the terminator, when the user is replying). Many corporations would like messages that they send to an end-user to appear with some form of corporate branding. E.g. ABXCorp would rather have the end user see a message from ABXCorp, rather than see that they have a message from 12345, and then have to figure out what those numbers represent.
A similar issue is also found in supporting external short message entities (ESMEs) from two different vendors. Some ESMEs support alphanumeric addressing while others do not.
Currently, if the mobile or ESME does not allow for message delivery with alphanumeric addresses encoded, the message to the mobile or the ESME may be discarded.
Alternatively, for messages destined to a Mobile, a generic numerical address may be substituted for the alphanumeric address, but a substituted generic numerical address is not meaningful to the Mobile end-user.
Many GSM/UMTS/LTE handsets support alphanumeric addresses. Some CDMA handsets may support alphanumeric (IA5) addresses. SMPP standard supports alphanumeric addresses, but many ESMEs/SMPP gateways have not fully implanted that portion of the standard. Thus, while end-points (some handsets and some ESMEs) may support alphanumeric addressing, the support for end-to-end alphanumeric addressing is not always complete.
ESMEs that are aware that a particular end-user handset has the alphanumeric capability could attempt delivery using that format, but that would require the ESME to maintain information about every phone number that it is sending to. Moreover, an ESME maintaining information about every phone number that it is sending to would be very susceptible to the user changing handset models.
Messages that are deleted due to protocol errors (e.g. handset cannot decode an address with alphanumeric characters) result in non-delivery to the subscriber. Messages that have had generic 'alphanumeric to generic' translation rules applied arrive at the handset without allowing the handset device to obtain the identity of the originator, thus also preventing the user device from responding.

Alphanumeric address mapping for non-homogeneous short message networks


Devices, methods, and systems for facilitating heat transfer and cooling electronic components are presented. A system for cooling an electronic component includes a cold core, a plurality of solid state cooling devices, and a plurality of heat sinks. The cold core may define one or more cavities for receiving electronic components. The system may include an air mover and a duct. In operation, the system may cool an electronic component to sub-ambient temperatures. In other embodiments, the system may include multiple cold cores connected by liquid conduits for facilitating a flow of a cooling fluid.

The following disclosure relates generally to heat transfer systems for cooling electronic components. Electronic components such as microchips and microprocessors generate large amounts of heat relative to their size during normal operation. As processor speed increases, the concomitant increase in heat energy represents a serious design challenge. Moreover, the current trend toward the miniaturization of electronic devices means that less physical space is available for cooling systems.
The semiconductor industry is also developing three-dimensional integrated circuits in which several microchips are placed together in a stack. Stacked chips further concentrate the generation of heat energy in a smaller space, creating a greater need for a better cooling performance in a smaller space.
The accumulation of heat energy is a serious limiting factor on the overall speed and performance of electronic devices. Existing systems are either too large for the physical space available or fail to provide satisfactory cooling performance.

Multidimensional heat transfer system for cooling electronic components

BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM


A magnetic resonance imaging apparatus reconstructs proton image data and chemical shift image data of, for example, a phosphorous compound from first and second magnetic resonance signals obtained from the same position of an object under examination. Display/non-display region decisions are made for the chemical shift image data by referring to the proton image data. Of the chemical shift image data, data present in display regions are displayed together with the proton image data.

1. Field of the Invention
The present invention relates to a magnetic resonance imaging apparatus and, more particularly, to a magnetic resonance imaging apparatus for imaging information on spin density, chemical shifts, etc., of specific atomic nuclei existing within a local region of an object under examination.
2. Description of the Related Art
Magnetic resonance imaging apparatus is apparatus which acquires chemical and physical information of substances in the form of magnetic resonance signals and reconstructs an image from the signals by utilizing resonance absorption of radio-frequency magnetic field energy at specific frequencies by atomic nuclei having intrinsic magnetic moments and placed in a static magnetic field.
In living biological tissue there exist chemical substances having atomic nuclei, such as .sup.1 H, .sup.13 C, .sup.23 Na and .sup.31 P, which produce such magnetic resonance signals. These substances take part in the metabolism of the biological tissue. Especially, .sup.31 P compounds, such as PCr (creatine phosphate), ATP (adenosine triphosphate), ADP (adenosine diphosphate), etc., and .sup.31 P (phosphorus) existing in biological tissue as Pi (inorganic phosphorous) take part in various types of energy metabolism (acquisition, conservation and consumption of energy), The measurement of density ratios and density distributions of these substances is very useful in evaluating the physiological activity of biological tissues. The use of magnetic resonance imaging apparatus makes it possible to identify and quantitatively determine specific atomic nuclei, such as .sup.1 H, .sup.13 C, .sup.23 Na and .sup.31 P, for each of their compounds. By imaging those atomic nuclei as chemical shift images, a spatial distribution of each of the compounds can be obtained.
In diagnosis using a chemical shift image of a phosphorous compound, it is usual practice to display a proton image and a chemical shift image of a phosphorous compound and make a comparison between them for identification and quantitative determination of the phosphorous compounds. The detection sensitivity for magnetic resonance signals of phosphorous compounds is so low as to be about 1/10.sup.5 of that of protons. In order to acquire magnetic resonance signals of a phosphorous compound with required signal-to-noise ratios, therefore, it is necessary to increase the volume of a voxel. A chemical shift image of a phosphorous compound is small in the total number of voxels within an imaging region as compared with a proton image, resulting in reduction of spatial resolution.
This problem will be discussed taking, by way of example, chemical shift imaging which was actually conducted by the inventors of the present invention using a phantom. Such a phantom as shown in FIG. 6 was prepared. This phantom has an annular-type container 60 which is partitioned into four compartments 61, 62, 63 and 64, the rooms 61 and 63 being filled with a highly concentrated solution of phosphoric acid and the compartments 62 and 64 being filled with a lowly concentrated solution of phosphoric acid. In FIG. 12A there is shown a proton image obtained from a slice of the phantom, which is parallel to the drawing sheet, taking the phantom as a sample to be examined. In FIG. 12B there is shown a chemical shift image of the phosphorous compound which was obtained from the same slice as the proton image of FIG. 12A using the conventional imaging method. In order to indicate a correspondence in position between the images, grid lines (indicated by broken lines) representing an imaging matrix (data acquisition matrix) of the chemical shift image are displayed on the proton image as shown in FIG. 12A. A doctor performs identification and quantitative determination while making a comparison between the chemical shift image of FIG. 12B and the proton image of FIG. 12A.
As can be seen from FIG. 12B, however, the chemical shift image of the phosphorous compound is coarse and low in spatial resolution as compared with the proton image of FIG. 12A. The reason is that the volume of each voxel is made large as described above in order to make the signal-to-noise ratio high in obtaining magnetic resonance signals of a phosphorous compound. As a result, it becomes difficult to understand the positional relationship between a chemical shift image of a phosphorous compound and an object to be measured. Thus, there arises a problem that it is difficult to accurately understand the distribution of a phosphorous compound which is a candidate for chemical shift imaging.


A power consumption controller includes (a) a power consumption calculation section which sequentially calculates the power consumption level of a self-luminous display device based on a video signal input from the beginning of each frame up to the time of calculation, (b) a power consumption status determination section which determines whether the calculated power consumption level exceeds a reference value for comparison by constantly comparing the two levels. If this is the case, the same section detects the timing at which the power consumption exceeds the reference value for comparison and (c) a peak brightness control section which controls the peak brightness of the self-luminous display device if the power consumption level exceeds the reference value for comparison based on the detected timing.

A self-luminous display device has the property that the power consumption changes at all times depending on the image displayed. Therefore, the establishment of a technique is required which can control the power consumption of a self-luminous display device to within an allowable range.
Among examples of power consumption control techniques is that descried in Japanese Patent Laid-Open No. 2004-354762.
Japanese Patent Laid-Open No. 2004-354762 discloses an arrangement which estimates the power consumption of the entire screen based on a video signal (gray level) per frame stored in a frame memory and converts the video signal (gray level) stored in the frame memory according to the estimated power consumption.

Power consumption controller, image processor, self-luminous display apparatus, electronic equipment, power consumption control method and computer program


The present disclosure relates to an advantageous system and related methods for distributed deduplication of encrypted chunks. One embodiment relates to a method for storing encrypted chunks in which an encryption key is generated independently from a chunk payload. With this method, two encrypted chunks are identifiable as having identical chunk payloads even when the chunk payloads are encrypted with different encryption keys. Other embodiments, aspects and features are also disclosed.

Technical Field
The present disclosure relates generally to data storage systems. More particularly, the present disclosure relates to data storage systems supporting cloud storage system protocols and providing inline distributed deduplication services.
Description of the Background Art
With the increasing amount of data is being created, there is increasing demand for data storage solutions. Storing data using a cloud storage service is a solution that is growing in popularity. A cloud storage service may be publicly-available or private to a particular enterprise or organization. Popular public cloud storage services include Amazon S3™, the Google File System™, and the OpenStack Object Storage (Swift) System™.
Cloud storage systems may provide "get" and "put" access to objects, where an object includes a payload of data being stored. The payload of an object may be stored in parts referred to as "chunks". Using chunks enables the parallel transfer of the payload and allows the payload of a single large object to be spread over multiple storage servers.
With the increasing need for archival data storage, it is highly desirable for a cloud storage system to be efficient in storing large data sets. Deduplication is one technique for substantially improving the efficiency of a cloud storage system. Deduplication identifies identical data chunks in a storage system so as to avoid storing duplicative copies of the same chunk. Distributed Deduplication is a more advanced form of deduplication that also avoids transferring duplicative copies of the same chunk over the network.
For reasons of data security and privacy for users, it is also highly desirable provide end-to-end encryption of data chunks in a cloud storage system. End-to-end encryption requires chunks to be stored and transmitted only when they are encrypted.
However, it is challenging to only store and transmit encrypted chunks in a distributed system while, at the same time, retaining the ability to determine whether two chunks are identical for data deduplication. The present disclosure provides an advantageous solution to this challenge.

System and method for distributed deduplication of encrypted chunks


Applications and methods for DRAM technology compatible non-volatile memory cells are presented. An example illustrating the applications and methods includes a circuit switch. The circuit switch has a non-volatile memory cell which a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, a capacitor, and a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET. A wordline is coupled to a top plate of the capacitor in the non-volatile memory cell. A sourceline is coupled to a source region of the MOSFET in the non-volatile memory cell. A bit line is coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to a logic/select circuit.

The present invention relates generally to semiconductor integrated circuits and, more particularly, to applications for non-volatile memory cells.
Many products need various amounts of memory. Two of the most useful types of memory are high speed, low cost memory typically implemented as dynamic random access memory (DRAM) and non-volatile memory typically implemented as electrically erasable and programmable read only memory (EEPROM) or Flash memory.
This invention relates to non-volatile memory cells being used in conjunction with DRAM memory cells. Micron Technology, Inc. taught in U.S. Pat. No. 5,324,681 which issued to Lowrey et al. on Jun. 28, 1994, that one time programmable (OTP) memory cells could be used to replace laser/fuse programmable memory cells for applications such as OTP repair of DRAMs using redundant rows and columns of DRAM memory cells and OTP selection of options on a DRAM (such as fast page mode (FPM) or extended data out (EDO)). One of the key advantages of that capability is the ability to program the OTP memory cells after the DRAM memory chip is packaged (a decided advantage over previous solutions).
The antifuse integrally combines the functions of a switching element which makes the interconnection and a programming element which stores the state of the switching element, either xe2x80x9coffxe2x80x9d or xe2x80x9con.xe2x80x9d Thus an antifuse occupies little space on the integrated circuit, but has the disadvantage of not being reprogrammable. This single-time programmability makes the antifuse difficult to test and unsuitable for a large class of applications where reprogrammability is required.
Alternative programmable interconnects use a metal oxide semiconductor field programmable transistor (MOSFET) as the switching element. The MOSFET is controlled by the stored memory bit of a programming element. Most commonly, this programming element is a dynamic random access memory (DRAM) cell. Such DRAM based FPGAs are reprogrammable, but the programming of the switching elements is lost whenever power is turned off. A separate, non-volatile memory cell must be used to store the programmed pattern on power down, and the FPGA must be reprogrammed each time the device is powered back up.
It is further desirable to implement non-volatile memory cells along with DRAM cells to provided shadow RAM cells. An example of conventional shadow RAM cells is taught in U.S. Pat. No. 5,196,722 issued to Bergendahl et al. on Mar. 23, 1993. However, the process steps involved there are lengthy and do not fit well with an optimized DRAM technology process flow.
The ability to combine DRAM and non-volatile, e.g. EEPROM, styles of memory, especially if little or no additional manufacturing complexity is required, would facilitate a number of cost effective applications, as described above, which do not currently exist or that, heretofore were too costly to be commercially viable.
Thus, there is a need for additional applications for DRAM technology compatible non-volatile memory cells. It is desirable that such DRAM technology non-volatile memory cells be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. It is further desirable that such DRAM technology non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
The above mentioned problems for merging additional applications for DRAM technology compatible non-volatile memory cells onto the DRAM chip as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention includes a compact non-volatile memory cell structure formed using a DRAM process technology.
The present invention employs DRAM technology compatible non-volatile memory cells for implementations which dramatically improves on the prior art. An example of one such application includes a circuit switch. The circuit switch has a non-volatile memory cell which has a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, a capacitor, and a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET. A wordline is coupled to a top plate of the capacitor in the non-volatile memory cell. A sourceline is coupled to a source region of the MOSFET in the non-volatile memory cell. A bit line is coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to logic/select circuit.
Another example of an application includes a shadow random access memory (RAM) cell. The shadow RAM cell has a non-volatile memory cell with the structure described above. Other implementations of the present invention may similarly be included.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

Applications for non-volatile memory cells


In a mobile communications system each radio unit (14, 16) is associated with a respective base station (12) as its `home` base station; any radio unit can communicate with any base station in whose service area it is located. Each base station has a radio interface (20) for communication with radio units, a telephone interface (24) for connection to a telephone line, for example via a PABX (44), and a LAN interface (28) for connection to a local area network (40) to which all the base stations are coupled. Voice communications for a handset are always routed through the home base station for that handset, e.g. to another handset or to the PABX, irrespective of the identity of the base station in whose service area the handset is currently located.

Various kinds of apparatus and methods for providing mobile communications are known. Thus, for example, mobile telephone systems are now available which enable a user to place telephone calls over the public switched telephone network (PSTN) without having a physical wired link to the network. These systems include so-called cordless or in-building services, based for example on the CT-2 or Digital European Cordless Telecommunications (DECT) standards, which provide relatively short-range services within an area such as a user's workplace. A unit implementing the DECT air interface typically comprises a base station, including a low-power radio transceiver, and a mobile radio handset module containing a second transceiver for communicating with the base station. The base station is connected by a telephone line to the PSTN, either directly or via a private automatic branch exchange (PABX). This has the disadvantage that although each additional DECT unit installed in an organization requires either a dedicated PSTN line or a PABX line, it offers no more than a mobile extension to the respective user's phone line. Providing additional facilities such as the ability to contact any mobile handset wherever it is currently located in a building requires significant capital investment by way of installation or upgrading of a PABX. Furthermore, if an organization invests in additional DECT units, the only benefit is the simple incremental expansion of the number of DECT base stations there is no interaction between the DECT base stations to exploit the extended area of coverage provided by the base stations considered together.
It is also known to provide mobile communications in systems involving a local area network (LAN). Thus European patent application No. 0 479 477 describes a distributed switching cellular communication system in which signals intended for a radio module are routed between base stations via a LAN as the radio module moves from the service area of one base station into the service area of another.
Disclosure of Invention
According to one aspect of this invention there is provided a base station for a telecommunications system, comprising:
a wireless interface;
a LAN interface;
a third interface;
a switching device arranged selectively to interconnect said interfaces for transfer of signals therebetween in any of the following arrangements:
(a) said wireless interface is connected for transfer of signals directly to and from said third interface;
(b) said wireless interface is connected for transfer of signals directly to and from said LAN interface;
(c) said LAN interface is connected for transfer of signals directly to and from said third interface,
said switching device also converting signals between respective forms appropriate for each interface in accordance with prevailing selection of the interfaces for interconnection;
means for identifying origin of signals received via said wireless interface or said LAN interface; and
means for controlling said switching device for transfer to said third interface of only those signals having a predetermined origin.
The third interface may be, for example, any of a public switched telephone network interface, a serial communications interface or an integrated services digital network interface. Where the third interface is a public switched telephone network interface, the wireless interface may be arranged to support wireless communications with a wireless telephone handset specifically associated with the base station.

Base station for a telecommunications system


A method and apparatus for predicting a mouth-shape feature, and an electronic device are provided. A specific implementation of the method comprises: recognizing a phonetic posterior gram (PPG) of a phonetic feature; and performing a prediction on the PPG by using a neural network model, to predict a mouth-shape feature of the phonetic feature, the neural network model being obtained by training with training samples and an input thereof including a PPG and an output thereof including a mouth-shape feature, and the training samples including a PPG training sample and a mouth-shape feature training sample.

With the rapid development of artificial intelligence, digital communication and other technologies, virtual image gradually becomes an important development direction of the next generation of artificial intelligence interaction. Here, a mouth-shape feature in the virtual image is a key technical feature. At present, a phoneme, a syllable, etc. are mainly used as phonetic features, and the mouth-shape feature is determined through a series of mouth-shape mapping rules defined by an expert in the field. However, the accuracy of the method of predicting the mouth-shape feature is poor.

Method and apparatus for predicting mouth-shape feature, and electronic device

Baidu Online Network Technology (Beijing) Co., Ltd.


A method for analyzing a digital image channel comprising the steps of providing a digital image channel, extracting a signal from the digital image channel, and using the extracted signal to determine whether the digital image channel is an interpolated digital image channel or a non-interpolated digital image channel. More specifically, the extracted signal comprises a signal related to differences between the values of neighboring pixels of the digital image channel, and the periodicity of the extracted signal is analyzed by computing a Fourier Transform signal of the extracted signal and looking for peaks in the Fourier Transform signal.

In the field of image processing, it is often the case that an image must be resized for a desired application. For example, the pixels per inch (or dpi dots per inch) of many display devices are fixed. A particular printer may have a resolution of 250 dpi, for example. In order to print an image consisting of 500 by 750 pixels to a 4 by 6 inch print on such a printer, the image must be resized by a factor of 2. In other words, the values of the image at locations between the original samples must be determined. This process of determining the value of an image signal at locations which are not coincident with the original samples of the image is called interpolation. The factor of interpolation, N, refers to the ratio of the sampling rate of the output image to the sampling rate of the input image. In the previous example, the interpolation factor N=2.
The process of interpolation produces an image of a desired number of rows and columns of pixels. However, the interpolation process involves "guessing" the signal value at many locations. As a result the interpolated image is generally not as high quality as an image originally captured at the desired resolution. For example, an image captured at 500×750 pixels and then interpolated to 1000×1500 pixels will generally appear softer and of lower quality than an image resulting from capturing that same scene at 1000×1500 pixels originally.
Because of the generally lower quality of interpolated images, it would be a desirable and valuable goal for an image processing system to have knowledge of whether an image had been interpolated. More precisely, it would be valuable for an image processing system to be able to distinguish a non-interpolated image from an interpolated image. Additionally, it would be desirable for the image processing system to have knowledge of the factor of interpolation N.
Consequently, it would be desirable to determine directly from the data contained within a digital image (the pixel locations and values) whether an image has been interpolated. It would further be desirable to determine the factor of interpolation directly from the data contained within the digital image.

Method for detecting image interpolation


A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.

In recent years, demands for miniaturizing semiconductor devices have been increasing along with the increase in the degree of integration, functionality and speed thereof. In view of this, various device structures have been proposed in the art, aiming at the reduction in the area of the substrate taken up by transistors. Among others, attention has been drawn to field effect transistors having a fin-shaped structure. A field effect transistors having the fin-shaped structure is commonly called a fin-shaped FET (field effect transistor), and has an active region consisting of thin wall (fin)-like semiconductor regions perpendicular to the principle plane of the substrate. In a fin-shaped FET, the side surface of the semiconductor region can be used as a channel surface, whereby it is possible to reduce the area on the substrate taken up by the transistor (see, for example, Patent Document 1 and Non-Patent Document 1).
FIGS. 17A-D show a structure of a conventional fin-shaped FET, wherein FIG. 17A is a plan view, FIG. 17B is a cross-sectional view taken along line A-A in FIG. 17A, FIG. 17C is a cross-sectional view taken along line B-B in FIG. 17A, and FIG. 17D is a cross-sectional view taken along line C-C in FIG. 17A.
As shown in FIGS. 17A-D, a conventional fin-shaped FET includes a supporting substrate 101 made of silicon, an insulating layer 102 made of silicon oxide formed on the supporting substrate 101, semiconductor regions 103a to 103d each formed into a fin shape on the insulating layer 102 (hereinafter referred to as the "fin-shaped semiconductor regions"), a gate electrode 105 formed on the fin-shaped semiconductor regions 103a to 103d with gate insulating films 104a to 104d interposed therebetween, insulative sidewall spacers 106 formed on side surfaces of the gate electrode 105, extension regions 107 formed on opposing regions of the fin-shaped semiconductor regions 103a to 103d sandwiching the gate electrode 105 therebetween, and source-drain regions 117 formed on opposing regions of the fin-shaped semiconductor regions 103a to 103d sandwiching the gate electrode 105 and the insulative sidewall spacer 106 therebetween. The fin-shaped semiconductor regions 103a to 103d are placed on the insulating layer 102 so as to be arranged at regular intervals in the gate width direction. The gate electrode 105 is formed so as to extend across the fin-shaped semiconductor regions 103a to 103d in the gate width direction. The extension region 107 includes a first impurity region 107a formed in an upper portion of each of the fin-shaped semiconductor regions 103a to 103d, and a second impurity region 107b formed in a side portion of each of the fin-shaped semiconductor regions 103a to 103d. The source-drain region 117 includes a third impurity region 117a formed in an upper portion of each of the fin-shaped semiconductor regions 103a to 103d, and a fourth impurity region 117b formed in a side portion of each of the fin-shaped semiconductor regions 103a to 103d. Note that pocket regions are not described herein or shown in the figure.
FIGS. 18A-D are cross-sectional views showing step by step a conventional method for producing a semiconductor device. Note that FIGS. 18A-D correspond to the cross-sectional structure taken along line C-C in FIG. 17A. In FIGS. 18A-D, like elements to those shown in FIGS. 17A-D are denoted by like reference numerals and will not be described redundantly.
First, as shown in FIG. 18A, there is provided an SOI (silicon on insulator) substrate, in which the insulating layer 102 made of silicon oxide is provided on the supporting substrate 101 made of silicon, and a semiconductor layer made of silicon is provided on the insulating layer 102. Then, the semiconductor layer is patterned to form the fin-shaped semiconductor region 103b to be the active region.
Then, as shown in FIG. 18B, the gate insulating film 104 is formed on the surface of the fin-shaped semiconductor region 103b, after which a polysilicon film 105A is formed across the entire surface of the supporting substrate 101.
Then, as shown in FIG. 18C, the polysilicon film 105A and the gate insulating film 104 are etched successively to form the gate electrode 105 on the fin-shaped semiconductor region 103b with the gate insulating film 104b interposed therebetween. Then, using the gate electrode 105 as a mask, the semiconductor region 103b is ion-implanted with an impurity to form the extension region 107 and the pocket region (not shown).
Next, as shown in FIG. 18D, an insulating film is formed across the entire surface of the supporting substrate 101, and then the insulating film is etched back by using anisotropic dry etching to thereby form the insulative sidewall spacer 106 on the side surface of the gate electrode 105. Then, using the gate electrode 105 and the side wall 106 as a mask, the semiconductor region 103b is ion-implanted with an impurity to form the source-drain region 117.
Through the steps described above, it is possible to obtain a fin-shaped MISFET (metal insulator semiconductor field effect transistor) having the gate electrode 105 formed on the fin-shaped semiconductor region 103b with the gate insulating film 104b interposed therebetween.
In recent years, it has been drawing attention to use a plasma doping method in order to conformally dope the upper surface and the side surface of a fin-shaped semiconductor region. For example, a pulsed DC plasma technique has been proposed in the art (Non-Patent Document 1) as a plasma doping method used for conformal doping. This is a method in which a plasma is generated on and off, and has an advantage in that etching is unlikely to occur. However, if the method is used for doping a fin-shaped semiconductor region, the specific resistance of the side surface of the semiconductor region will be larger than that of the upper surface of the semiconductor region.
Note that in addition to the pulsed DC plasma technique of Non-Patent Document 1, plasma doping methods include a method disclosed in Patent Document 2 as a representative method. Patent Document 2 proposes a technique using an inductively coupled plasma (ICP) method. This is a method desirably capable of uniformly doping into the surface of a large substrate such as a wafer having a diameter of 300 mm, for example, by employing a longer time region (doping time) than that used in a pulsed DC plasma method.
Patent Document 3 discloses a plasma doping method for conformally doping the trench side surface. Note however that this is a technique for doping only the trench side surface, and it is not an object of the technique to dope the upper surface and the side surface of a fin-shaped semiconductor region. Specifically, with a method doping only the side surface as disclosed in Patent Document 3, doping is performed while masking the upper surface, thus failing to realize effects of the present invention to be described later, such as the realization of conformal doping on the upper surface and the side surface, and the prevention of chipping of the upper corner of a fin-shaped semiconductor region.    Patent Document 1 Japanese Laid-Open Patent Publication No. 2006-196821    Patent Document 2 International Publication WO2006/064772    Patent Document 3 Japanese Laid-Open Patent Publication No. 1-295416    Non-Patent Document 1 D. Lenoble, et al., Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions, 2006 Symposium on VLSI Technology Digest of Technical Papers, p. 212

Semiconductor device and method for producing the same


Plasma treatment is performed on an exposed portion of an undoped amorphous silicon layer in a thin film transistor, after etching source/drain contacts and a doped amorphous silicon layer. The plasma treatment can repair damage caused during the etching. The plasma treatment is preferably a hydrogen plasma treatment, and more preferably a helium plasma treatment. These treatments are particularly useful in repairing damage when the source/drain electrodes comprise molybdenum or molybdenum/tungsten alloy, and etching is performed by dry etching the doped amorphous silicon layer using CF.sub.4 and HCl gases.

Liquid Crystal Displays (LCDs) are widely used flat panel display devices. As is well known to those having skill in the art, an LCD generally includes two spaced apart substrates with liquid crystals therebetween. A plurality of spaced apart gate lines are formed on one substrate, and a plurality of spaced apart data lines are formed on the substrate that intersect the plurality of spaced apart gate lines. Accordingly, the gate lines and data lines define an array of pixels. An array of pixel electrodes is provided, a respective one of which is in a respective one of the pixels. An array of thin film transistors is also provided, each comprising a gate electrode that is connected to one of the spaced apart gate lines, a gate insulator on the gate electrode, and an amorphous silicon layer on the gate insulator. Spaced apart source and drain electrodes are provided on the amorphous silicon layer. The source electrode is connected to one of the spaced apart data lines. The drain electrode overlaps a pixel electrode, and is electrically connected thereto through a contact hole therebetween.
As is well known to those having skill in the art, the thin film transistors generally include an undoped hydrogenated amorphous silicon layer that forms the channel region. A doped hydrogenated amorphous silicon layer that may be heavily doped, for example, with n-type impurities, is formed on the undoped amorphous silicon layer. The doped amorphous silicon layer can decrease the contact resistance between the amorphous silicon layer and source/drain electrodes. The doped amorphous silicon layer is then selectively etched using patterned source/drain electrodes as an etch mask. However, the source/drain electrodes may also be undesirably etched during etching of the doped amorphous silicon layer.
In order to reduce etching of the source/drain electrodes, a photoresist pattern that is used to form the source/drain electrodes may also be used as an etch mask to etch the doped amorphous layer. The photoresist pattern is then stripped. Unfortunately, however, the amorphous silicon layer may be damaged when stripping the hardened photoresist pattern. This may degrade the performance of the thin film transistors and liquid crystal displays.

Methods of manufacturing thin film transistors and liquid crystal displays by plasma treatment of undoped amorphous silicon


The invention provides an improved method of vibration welding of thermoplastic joints. Such welding is conducted by vibrating two fiber reinforced thermoplastic parts under pressure along their common interface to generate frictional heat to melt and fuse their surfaces together. Fibers from at least one surface penetrate both into the weld and into the other surface. As a result, the welded, fiber reinforced thermoplastic surfaces have increased tensile strength than heretofore achievable. Vibration welds of reinforced thermoplastic surfaces according to this invention achieve a maximum tensile strength as high as about 120% of a weld formed by the unreinforced surfaces of corresponding thermoplastic materials.

The present invention relates to vibration welding or more particularly to vibration welding of thermoplastic joints.
The ongoing demand to use thermoplastics to replace metals in automotive vehicle applications such as air induction systems has increased in recent years. It is estimated that by the year 2010, 21.4 million air intake manifold components will be produced using welding techniques. This invention concerns an improved method of vibration welding thermoplastic joints, and the vibration welded articles produced by the method. Vibration welding of thermoplastics such as nylon 6 and nylon 66 is well known in the art. See V. K. Stokes, "Vibration Welding of Thermoplastics, Part I: Phenomenology of the Welding Process", Polymer Engineering and Science, 28, 718 (1988); V. K. Stokes, "Vibration Welding of Thermoplastics, Part II: Analysis of the Welding Process", Polymer Engineering and Science, 28, 728 (1988); V. K. Stokes, "Vibration Welding of Thermoplastics, Part III: Strength of Polycarbonate Butt Welds", Polymer Engineering and Science, 28, 989 (1988); V. K. Stokes, "Vibration Welding of Thermoplastics, Part IV: Strengths of Poly(Butylene Terephthalate), Polyetherimide, and Modified Polyphenylene Oxide Butt Welds", Polymer Engineering and Science, 28, 998 (1988) and C. B. Bucknall, et al, "Hot Plate Welding of Plastics: Factors Affecting Weld Strength", Polymer Engineering and Science, 20, 432 (1980).
Vibration welding may be conducted by vibrating two parts under pressure along their common interface to generate frictional heat, and thereby melting and fusing their surfaces together. Vibration welding is a quick and inexpensive way to join irregularly shaped parts of various sizes. In the past, vibration welding has been used in low load-bearing applications. In automobile underhood applications such as air intake manifolds, air filter housings, and resonators, the expanded use of engineered plastics would be desirable to achieve savings and weight and cost. However, heretofore it has not been possible to achieve adequate weld strengths for such uses. Welding results are extremely sensitive to parameter uniformity and slight variations in them can result in significant changes in weld quality. Vibration welding parameters of pressure, frequency, amplitude, oscillation (welding) time, hold time and weld thickness all affect tensile strength of welds. It is an object of the present invention to provide a method for vibration welding fiber reinforced thermoplastic surfaces to provide welds having greater tensile strengths than have been heretofore achievable.
U.S. Pat. No. 4,844,320 teaches that weld strength are not affected by weld amplitude or weld time above a certain level. In conventional vibration welding, welds are formed at a vibration amplitude of 0.03 to 0.70 inch. In contrast we have found that weld amplitude and weld time are extraordinarily important criteria for increasing weld strength. The vibration welding of this invention uses a vibration amplitude of at least about 0.075 inch. It has been determined that conventional vibration welds of reinforced thermoplastic surfaces achieve a maximum tensile strength of approximately 80% of a weld formed by the unreinforced surfaces of corresponding thermoplastic materials. For glass fiber reinforced thermoplastics, this lowered tensile strength is attributed to a change in the glass fiber orientation at the welded joint. According to this invention, vibration welds of reinforced thermoplastic surfaces achieve a maximum tensile strength of as high as about 120% of a weld formed by the unreinforced surfaces of corresponding thermoplastic materials. This is because fibers from at least one of the surfaces are caused to penetrate both into the weld and into the other surface. This provides added, unexpected tensile strength to the weld.

Performance of vibration welded thermoplastic joints


A multi-layer insulation (MLI) blanket with enhanced contamination inhibiting properties and a method for inhibiting the formation of organic residues on the outer surface of a MLI blanket are provided. In one embodiment, a MLI blanket (10) attachable to a spacecraft or other structure includes a plurality of metallized layers (20, 30, 40, 50) separated by mesh layers (60, 62, 64). An anti-contamination coating (80) comprised of a photocatalytic material is disposed between a high emittance layer (70) that overlies the outer surface (20A) of the outer metallized layer (20) and an outer electrically conductive layer (90). When exposed to ultraviolet or near-ultraviolet radiation components present in solar radiation, the anti-contamination coating (80) catalyzes the breakdown of organic residues on the outer surface of the MLI blanket (10) thereby maintaining the reflective properties of the MLI blanket (10) and ensuring that solar absorptance of the MLI blanket (10) is maintained at or below an acceptable threshold level.

Multi-layer insulation (MLI) blankets are useful in a number of applications. One application is insulating spacecraft. In this regard, remote sensing scientific spacecraft as well as commercial communications spacecraft require highly insulative MLI blankets to minimize undesirable heat intrusion and diurnal temperature swings. The insulative value of MLI blankets is generally determined by factors such as the overall number of layers included in the blanket, the extent of conductive shorting between adjacent layers, the quality of edge seams and closures, and the number and extent of penetrations through the blanket. However, these are not the only factors that can affect the insulative value of a MLI blanket.
The solar absorptance of the outer layer of a MLI blanket is also an important factor in determining the overall insulative value of the MLI blanket. In this regard, limited attention has been paid to the optical properties of the outer layer of MLI blankets, other than typically designing the blanket to achieve a high infrared emittance value of approximately 0.80. However, the solar absorptance of the outer layer, either after long-term contamination and ultraviolet (UV) degradation effects or due to inherent beginning-of-life (BOL) properties typically approaches the infrared emittance value, yielding an equivalent black body surface with steady-state temperatures of around 125° C. when directly illuminated with solar radiation in space.

Anti-contamination coated multi-layer insulation


In an electron source manufacturing apparatus, the quantity of heat generated from an electron source substrate is measured. A temperature of a support member for the electron source substrate is controlled based on the measured quantity of heat generated. A variation in performances of electron source substrates is suppressed, which increase their life.

1. Field of the Invention
The present invention relates to an apparatus for manufacturing an electron source used for a display panel or the like and a method of manufacturing the electron source.
2. Related Background Art
Conventionally, as an electron-emitting device, there are generally known two types, namely, a thermoelectron-emitting device and a cold-cathode electron-emitting device. The cold-cathode electron-emitting device includes a field-emission electron-emitting device, a metal/insulator/metal electron-emitting device and a surface conduction electron-emitting device.
For example, there are surface conduction electron-emitting devices that utilize the phenomenon in which electron emission is caused by allowing an electric current to flow in a thin film formed with a small area on a substrate and in parallel to the film surface. Its basic structure and manufacturing method are disclosed, for example, in Japanese Patent Application Laid-Open No. H7-235255, and Japanese Patent Application Laid-Open No. H8-171849.
The surface conduction electron-emitting device is characterized by including on a substrate a pair of device electrodes opposing each other and an electroconductive film that is connected to the pair of device electrodes and has an electron-emitting region in a part thereof. In addition, a fissure is formed in a part of the electroconductive film and a deposited film containing at least one of carbon and a carbon compound as a main component is formed at the end of the fissure.
A plurality of such electron-emitting devices are arranged on a substrate and are connected to one another by wirings, whereby an electron source provided with the plurality of electron-emitting devices can be manufactured. In addition, a display panel of an image-display apparatus can be manufactured by combining the electron source with a phosphor.
When the electron source is manufactured, for example, a plurality of electroconductive members are formed on a substrate, and the substrate is placed on a support member having a cooling unit and covered with a vacuum chamber. The vacuum chamber includes a closed space formed by the support member and the vacuum chamber using a seal member such as a packing.
Next, after the vacuum chamber is exhausted, a voltage is applied to each of the electroconductive members through external terminals under a depressurized atmosphere to form an electron-emitting region in each of the electroconductive members. At the application of the voltage, heat generated from the substrate is recovered by the support member having the cooling unit.
According to a conventional manufacturing method, a temperature control performed by the support member is an open control. For example, a cooling medium having a predetermined temperature is allowed to flow into the cooling unit of the support member or a temperature of the cooling medium is changed so as to obtain a preset temperature profile.
However, when performances, such as an electron-emitting characteristic and a life, of the manufactured electron source are to be improved, it is necessary to control a temperature of the surface of the substrate with higher precision. In particular, when a variation in resistances of the electroconductive members or wirings connected with the electroconductive members is changed for each substrate, the quantity of heat generated from the surface of the substrate during an electron source manufacturing process is also changed for each substrate. Therefore, it is also required to control the temperature of the surface of the substrate to a predetermined temperature in consideration of the change in the quantity of heat generated.

Electron source manufacturing apparatus and electron source manufacturing method


An optical system including a telescope and a principal pointing device for selecting a direction of observation is disclosed. The system furthermore includes at least one secondary pointing device arranged ahead of a part of the entrance of the telescope and oriented fixedly with respect to the principal pointing device. A set of photodetectors records a secondary image formed by the telescope from light rays directed by the secondary pointing device toward the entrance of the telescope The secondary image makes it possible to accurately determine the direction of observation.

The present invention relates to an optical system with variable pointing, as well as to a method implementing such a system.
Identifying the direction of observation of an optical system is necessary in numerous applications, such as, for example, mapping of the sky, terrestrial observation performed from a satellite, especially for meteorological study purposes, the establishing of an optical transmission link with a satellite, etc.
Devices for identifying the direction of observation of an optical system already exist. French patent applications 2 713 785 and 2 724 013 disclose such devices which comprise a light source and a detector associated with the latter. In these devices, a light signal moves over the detector as a function of the orientation of the observation system. These devices are complex, especially on account of the light source which requires a suitable energy supply, and on account of further optical elements that they incorporate. They are also bulky, in particular since they are external to the observation system. Finally, with these devices, variations in the relative positions of the light source and/or the light detector on the one hand, and of the observation system on the other hand, cause errors in the determination of the direction of observation. Such variations in position are due, in particular, to deformations or to thermal expansions of the supports of the detector, of the light source and/or of the observation system.
An aim of the present invention is to make possible determining the direction of observation of an optical system precisely and accurately, while not requiring any complex or bulky equipment.

Optical system with variable pointing and method implementing such a system


The particular status of a Multiple Network Interface Mobile Device (MID) is identified and particular problems associated with that status are addressed by activating different modes of operation depending upon whether the MID is stationary or in motion. In particular, when the mobile device is in motion, the multiple network interfaces are used to prevent packet loss, and when the mobile device becomes stationary, the multiple network interfaces are used to enhance bandwidth to achieve superior Quality of Service (QoS). MIDs thus are allowed to utilize multiple interfaces simultaneously for bandwidth incremental increases if the mobile device is stationary. MIDs also are allowed to utilize multiple interfaces simultaneously for packet loss recovery and smooth and seamless transitioning from one interface to another when the mobile device is in motion.

1. Field of the Invention
The present application relates generally to wireless networking, and more particularly to systems and methods for supporting the use of mobile devices having multiple heterogeneous network access interfaces, whereby such mobile devices may connect to different wireless networks and/or make use of various network access technologies, for multiple purposes such as preventing the loss of data transmission packets and also to enhance the useable bandwidth of such mobile devices.
2. General Background Discussion
Internet Protocol
IP is a connectionless protocol. The connection between end points during a communication is not continuous. When a user sends or receives data or messages, the data or messages are divided into components known as packets. Every packet is treated as an independent unit of data.
In order to standardize the transmission between points over the Internet or the like networks, an OSI (Open Systems Interconnection) model was established. The OSI model separates the communications processes between two points in a network into seven stacked layers, with each layer adding its own set of functions. Each device handles a message so that there is a downward flow through each layer at a sending end point and an upward flow through the layers at a receiving end point. The programming and/or hardware that provides the seven layers of function is typically a combination of device operating systems, application software, TCP/IP and/or other transport and network protocols, and other software and hardware.
Typically, the top four layers are used when a message passes from or to a user and the bottom three layers are used when a message passes through a device (e.g., an IP host device). An IP host is any device on the network that is capable of transmitting and receiving IP packets, such as a server, a router or a workstation. Messages destined for some other host are not passed up to the upper layers but are forwarded to the other host. In the OSI and other similar models, IP is in Layer-3, the network layer. The layers of the OSI model are listed below.
Layer 7 (i.e., the application layer) is a layer at which, e.g., communication partners are identified, quality of service is identified, user authentication and privacy are considered, constraints on data syntax are identified, etc.
Layer 6 (i.e., the presentation layer) is a layer that, e.g., converts incoming and outgoing data from one presentation format to another, etc.
Layer 5 (i.e., the session layer) is a layer that, e.g., sets up, coordinates, and terminates conversations, exchanges and dialogs between the applications, etc.
Layer-4 (i.e., the transport layer) is a layer that, e.g., manages end-to-end control and error-checking, etc.
Layer-3 (i.e., the network layer) is a layer that, e.g., handles routing and forwarding, etc.
Layer-2 (i.e., the data-link layer) is a layer that, e.g., provides synchronization for the physical level, does bit-stuffing and furnishes transmission protocol knowledge and management, etc. The Institute of Electrical and Electronics Engineers (IEEE) sub-divides the data-link layer into two further sub-layers, the MAC (Media Access Control) layer that controls the data transfer to and from the physical layer and the LLC (Logical Link Control) layer that interfaces with the network layer and interprets commands and performs error recovery.
Layer 1 (i.e., the physical layer) is a layer that, e.g., conveys the bit stream through the network at the physical level. The IEEE sub-divides the physical layer into the PLCP (Physical Layer Convergence Procedure) sub-layer and the PMD (Physical Medium Dependent) sub-layer.
Typically, layers higher than layer-2 (such as layers including the network layer or layer-3 in the OSI model and the like) are referred to as the higher-layers.
Wireless Networks
Wireless networks can incorporate a variety of types of mobile devices, such as cellular and wireless telephones, PCs (personal computers), laptop computers, wearable computers, cordless phones, pagers, headsets, printers, PDAs, etc. For example, mobile devices may include digital systems to secure fast wireless transmissions of voice and/or data.
Wireless LANs (WLANs) in which a mobile user can connect to a local area network (LAN) through a wireless connection may be employed for wireless communications. Wireless communications can include communications that propagate via electromagnetic waves, such as light, infrared, radio, microwave. There are a variety of different WLAN standards that currently exist, such as Bluetooth, IEEE 802.11, and HomeRF.
For example, Bluetooth products may be used to provide links between mobile computers, mobile phones, portable handheld devices, personal digital assistants (PDAs), and other mobile devices and connectivity to the Internet. Bluetooth is a computing and telecommunications industry specification that details how mobile devices can easily interconnect with each other and with non-mobile devices using a short-range wireless connection. Bluetooth creates a digital wireless protocol to address end-user problems arising from the proliferation of various mobile devices that need to keep data synchronized and consistent from one device to another, thereby allowing equipment from different vendors to work seamlessly together. Bluetooth devices may be named according to a common naming concept. For example, a Bluetooth device may possess a Bluetooth Device Name (BDN) or a name associated with a unique Bluetooth Device Address (BDA). Bluetooth devices may also participate in an Internet Protocol (IP) network. If a Bluetooth device functions on an IP network, it may be provided with an IP address and an IP (network) name. Thus, a Bluetooth Device configured to participate on an IP network may contain, e.g., a BDN, a BDA, an IP address and an IP name. The term "IP name" refers to a name corresponding to an IP address of an interface.
Similarly, IEEE 802.11 specifies technologies for wireless LANs and devices. Using 802.11, wireless networking may be accomplished with each single base station supporting several devices. In some examples, devices may come pre-equipped with wireless hardware or a user may install a separate piece of hardware, such as a card, that may include an antenna. By way of example, devices used in 802.11 typically include three notable elements, whether or not the device is an access point (AP), a mobile station (STA), a bridge, a PCMCIA card or another device: a radio transceiver; an antenna; and a MAC (Media Access Control) layer that controls packet flow between points in a network.
Wireless networks also may involve methods and protocols found in Mobile IP (Internet Protocol) systems, in PCS systems, and in other mobile network systems. With respect to Mobile IP, this involves a standard communications protocol created by the Internet Engineering Task Force (IETF). With Mobile IP, mobile device users may move across networks while maintaining their IP Address assigned once. See Request for Comments (RFC) 3344. Mobile IP enhances Internet Protocol (IP) and adds means to forward Internet traffic to mobile devices when connecting outside their home network. Mobile IP assigns each mobile node a home address on its home network and a care-of-address (CoA) that identifies the current location of the device within a network and its subnets. When a device is moved to a different network, it receives a new care-of address. A mobility agent on the home network can associate each home address with its care-of address. The mobile node can send the home agent a binding update each time it changes its care-of address by using a protocol such as Internet Control Message Protocol (ICMP).
In basic IP routing, routing mechanisms typically rely on the assumptions that each network node always has a constant attachment point to the Internet and that each node's IP address identifies the network link it is attached to. In this document, the terminology "node" includes a connection point, which can include a redistribution point or an end point for data transmissions, and which can recognize, process and/or forward communications to other nodes. For example, Internet routers can look at an IP address prefix or the like identifying a device's network. Then, at a network level, routers can look at a set of bits identifying a particular subnet. Then, at a subnet level, routers can look at a set of bits identifying a particular device. With typical mobile IP communications, if a user disconnects a mobile device from the Internet and tries to reconnect it at a new subnet, then the device has to be reconfigured with a new IP address, a proper netmask and a default router. Otherwise, routing protocols would not be able to deliver the packets properly.
Handoffs of Mobile Devices
In the context of a mobile device with an IP-based wireless network interface, the mobile device needs to perform roaming or handoffs when it moves from one network to another network, or from one access point of a network to another. With existing handoff methodologies, handoff is typically accomplished by performing the following sequence of protocol layer specific handoffs:                First, handoff takes place at the physical layer. In this regard, the mobile device switches its radio channel to a wireless base station or wireless access point in the target network.        Second, handoff takes place at layer-2. In this regard, the mobile device switches its layer-2 (i.e., link-layer) connections to the target network. As explained above, the link layer or layer-2 refers to the protocol immediately below the IP-layer that carries user traffic. The mobile device performs layer-2 authentication with the target network if the target network requires such authentication.        Third, handoff takes place at the IP-layer. In this regard, the mobile device obtains a local IP address from the target network, performs IP-layer authentication if required by the target network, and then performs IP-layer location update so that IP packets destined to the mobile device can be routed by the IP network to the mobile device via the target network. In some instances, one way to support IP layer location update is to use Mobile IP defined by the Internet Engineering Task Force (IETF).        Fourth, handoff takes place at the application-layer. The mobile device performs necessary steps at the application layer to ensure that its application traffic will flow correctly to the applications on the mobile device via the target network. For example, when the mobile device uses the Session Initiation Protocol (SIP) defined by the IETF to manage its application-layer signaling, an application layer handoff can be achieved by the mobile device updating its current location with its home SIP server. The mobile device may also need to carry out application-layer authentication with the target network if required by the target network. This is the case, for example, when the mobile device is using the IP Multimedia Subsystem (IMS) in a visited 3GPP (3rd Generation Partnership Project) wireless network, where the IMS is a SIP-based system supporting application-layer signaling and management for multimedia applications over 3GPP networks.Multiple Network Access Interface Mobile Devices
As the popularity and proliferation of wireless network access grows, more and more mobile devices are expected to have Multiple Interface Device (MID) capabilities. MIDs are mobile devices that contain two or more independent network interfaces, thus allowing the MID to have connectivity with two or more separate networks and/or make use of different network access technologies. The MID may have an IP address and a common IP (network) name associated with the IP address.
For example, an MID may have different wireless local-area (WLAN) interfaces such as 802.11x (i.e., IEEE 802.11a, 802.11b or 802.11g), BlueTooth, HomeRF, or Wi-Fi, different wide-area (WAN) radio interfaces such as GPRS (General Packet Radio Service), 3G, 3GPP, 3GPP2, GSM (Global System for Mobile Communications), EDGE (Enhanced Data for GSM Evolution), TDMA (Time Division Multiple Access), or CDMA (Code Division Multiple Access), both WLAN and WAN wireless network interfaces, or both wireless and wireline network interfaces.
Each network interface may contain addresses of varying types, such as an IP address, a Bluetooth Device Address, a Bluetooth Common Name, a Bluetooth IP address, a Bluetooth IP Common Name, an 802.11 IP Address, an 802.11 IP common Name, or an IEEE MAC address.
MIDs therefore provide flexibility in allowing a user to gain access to more than one type of wireless network with a single mobile device. However, additional benefits could be reaped if the MID mobile device could use the multiple network interfaces to optimize the user's communication experience. For example, when a mobile device is traveling (either in a vehicle or being carried by the user on foot) in an active session through regions of different network providers or different access point technologies, it is prone to losing data packets, which may impair real-time sensitive applications such as VoIP (Voice Over IP) or streaming media applications. In this situation, the multiple interfaces could be used beneficially for packet loss recovery. On the other hand, when a mobile device user is stationary, packet loss is not as much of a concern. Therefore in a stationary situation, the multiple interfaces could be used advantageously to increase or enhance bandwidth. The enhanced bandwidth may be useful, for example, in running high data rate applications or in sharing the load of a congested network.
FIG. 7 shows an example of a MID mobile device 1 including a plurality of interfaces. In the illustrated example, three interfaces are shown: Interface 1; Interface 2 and Interface 3. However, any number of interfaces can be employed. In illustrative embodiments, a MID device can include portable computers, personal desk-top computers, PDAs, portable voice-over-IP telephones and/or other devices. Typically, such mobile devices will include a transceiver (including an antenna for communication with the access point), a processor, memory (including program memory and Random Access Memory). As also shown, the memory can include a program or module, such as a QoI Comparison Module for carrying out functionality as described hereinafter. In various embodiments, processes to be carried out by the MID can be performed via software, hardware and/or firmware as may be appropriate based on circumstances.
As shown in FIG. 7, mobile MID 1 is capable of communication over a plurality of heterogeneous networks via separate interfaces 1-3. For example, the mobile device can communicate via an Access Point 22 (such as a wireless LAN (WLAN) access point) or via a Base Station 2 (such as a WAN base station). Although not specifically applicable to the concepts of the present invention, FIG. 7 also shows that the MID 1 may also be able to communicate with a wired network. The Access Point 22 can be within a wireless local area network (WLAN) connected to a wireline network 20. The wireline network 20 can include the Internet or a corporate data processing network. The access point 22 also can be a wireless router having a network interface 25 linked to the wireline network 21 and a wireless transceiver in communication with the mobile device 1 as well as with other mobile devices. The wireless transceiver 26 can include an antenna 27 for radio or microwave frequency communication with the mobile devices. The Access Point 22 preferably also has a processor 28, a program memory 29, and a random access memory 31.
In general, processes are known that address packet loss prevention or Quality of Interface (QoI) measurement. Several solutions have been suggested to take advantage of heterogeneous radio technologies. These can be grouped into two categories. One considers QoI comparisons at the Physical Layer. These solutions primarily take into account Signal Strength, SNR, or sending probes to network(s) and obtaining a series of measurements of available bandwidth from different interfaces. The other category considers IP Packets received at the IP Layer. Such solutions mainly take into account a quantitative comparison of the number of IP packets received on each IP stream. However, such processes represent partial solutions only, and do not provide a solution to the issues discussed above with respect to the dynamic use of multiple network interfaces for different purposes depending upon the stationary/moving status of the mobile device. Additionally, the known solutions pertaining to both categories each have various drawbacks or weaknesses. Consequently, there remains a need in the art for solutions to the above issues and problems related to improved and enhanced functionality of wireless MIDs.

Dynamic use of multiple IP network interfaces in mobile devices for packet loss prevention and bandwidth enhancement


A cleaning tape for cleaning a magnetic tape head and tape path, having a non-abrasive cleaning surface with abrasive segments applied on the non-abrasive surface to form an alternating pattern. The abrasive segments may be angled across the surface of the non-abrasive cleaning surface. The abrasive segments loosen adhered debris and the non-abrasive segments carry the loose and loosened debris away from the head and the tape path.

The present invention relates generally to cleaning tapes, and specifically to cleaning tapes for cleaning magnetic tape heads.
There are two basic types of cleaning tapes used to clean magnetic tape heads of audio cassette decks and players, video cassette recorder heads, read/write heads of computer drives, and the like. The two types of cleaning tapes are abrasive and non-abrasive. The abrasive cleaning tapes use an unpolished or uncalendared magnetic tape media or an abrasive coating on a polyester base to lap or sand debris off of a head. Abrasive tapes do not have the ability to remove loose debris from the tape head. In harsh environments where many magnetic tape heads are located, such as areas where dust, saw dust, wood chips, and other debris and particulate matter may be in the air, abrasive tapes serve only to lap, sand, or loosen debris off of the head. Carrying away of the debris from the bead is not accomplished using an abrasive cleaning tape. In areas such as a machine shop, wood shop, or any area where a magnetic tape head may be located in which the environment contains free floating particles or debris, an abrasive cleaning tape will not be able to carry debris away from the tape head. Further, abrasive cleaning tapes tend to aggressively wear the head, shortening the life span of the head.
The non-abrasive type of cleaning tape is able to carry loose debris and particles away from the tape head and tape path. Non-abrasive cleaning tapes use a non-abrasive substance as a cleaning medium. Non-abrasive cleaning media include woven or non-woven nylon, non-woven polyester, woven silk, tyvek, and the like. Non-abrasive cleaning tapes can loosen some debris from a tape head. However, non-abrasive cleaning tapes are not able to effectively loosen debris which may adhere or affix itself to the tape head, such as organic polymers, known as brown stain, and heavy deposits of debris. Over time, oxide particles and the like become affixed to the tape head, degrading performance, unless they are removed. A non-abrasive cleaning tape, while it can remove loose debris, cannot effectively loosen all debris from the head.
It would be desirable to provide a cleaning tape that could not only loosen debris from the tape head, but could also remove loose debris and particles from the tape head and path, especially the particles or debris that it has just removed from the tape head.
It would also be desirable for such a cleaning tape to not aggressively or excessively wear the head.

Magnetic head and tape path cleaning tape


The invention refers to a device for inhibiting the neural activity of a carotid sinus nerve (CSN) or carotid body of a subject, the device comprising: one or more transducers configured to apply a signal to the CSN or associated carotid body of the subject, optionally at least two such transducers; and a controller coupled to the one or more transducers, the controller controlling the signal to be applied by the one or more transducers, such that the signal inhibits the neural activity of the CSN or carotid body to produce a physiological response in the subject, wherein the physiological response is one or more of the group consisting of: an increase in insulin sensitivity in the subject, an increase in glucose tolerance in the subject, a decrease in (fasting) plasma glucose concentration in the subject, a reduction in subcutaneous fat content in the subject, and a reduction in obesity in the subject.

The rapid increase in prevalence of metabolic disorders such as type 2 diabetes mellitus (T2D, or T2DM), obesity, impaired glucose tolerance (where patients go on to develop T2DM if left untreated) constitutes a severe unmet medical need. Currently available treatments for these disorders are insufficient to control the disease in a significant number of patients, and often produce unwanted side effects.
The carotid bodies (CB) are peripheral chemoreceptors that sense changes in arterial blood O2, CO2 and pH levels. Hypoxia, hypercapnia and acidosis are known to activate the CB. Upon sensing changes, the CB modulates the neural activity (i.e. the action potential pattern and frequency) in their sensory nerve, the carotid sinus nerve (CSN). CSN activity is interpreted by the elements of the brain stem that control efferent reflexes including normalization of blood gases via hyperventilation, and the regulation of blood pressure and cardiac performance via sympathetic nervous system (SNS) activation. Consistent with this notion, CB de-afferentation through carotid sinus nerve denervation reduces the overactive sympathetic activity in spontaneously hypertensive rats (McBryde et al, Nat Commun. 2013; 4:2395).
Recently, the carotid body have been implicated in the control of energy homeostasis and regulation of whole body insulin sensitivity (Riberio et al. (2013) Diabetes. 62: 2905-16, Limberg Med Hypotheses. 2014 June; 82(6):730-5). Riberio et al. (supra) demonstrated that healthy animals fed a high fat or high sugar diet develop insulin resistance and hypertension, but that if healthy rats undergo carotid sinus nerve (CSN) resection prior to beginning the diet, the development of insulin resistance and hypertension is prevented. However these procedures were performed on otherwise healthy animal that do not carry any of the associated symptoms or pathologies of metabolic disorders known to affect the metabolic system and perpetuate disease. No data are available from animals more representative of an active disease state.

Neuromodulation device and method for treating metabolic disorders

Faculdade De Ciências Médicas Da Universidade Nova De Lisboa