An output stage driver circuit comprising two parallel class AB stages running at slightly different quiescent currents, the difference of which is scaled up through a current mirror is disclosed which provides a temperature stable precisely controlled quiescent current for the output stage. A current limited voltage source is provided to ensure inherent short circuit protection with instantaneous response to short circuit or excessive load current conditions.

1. Field of the Invention
The present invention relates to output stages of amplifiers. More particularly, the present invention relates to methods and apparatus for setting and controlling quiescent (bias) current and cross over distortion independently in amplifier output stages. In addition, the present invention relates to amplifier output stages with inherent short circuit protection.
2. Description of the Related Art
An output stage, as the final stage of amplifiers, generally deals with relatively large signals. The most challenging requirement in the design of the output stage is that it deliver the required amount of power to the load in an efficient manner. This implies that the power dissipated in the output stage transistors must be as low as possible. This is primarily due to the fact that the power dissipated in a transistor raises its internal junction temperature, and there is a maximum temperature (in the range of 150.degree. C. to 200.degree. C. for silicon devices) above which the transistor is destroyed. Other reasons for requiring high-power conversion efficiency are to prolong the life of the batteries used in battery-powered circuits, to permit a smaller, lower-cost power supply, or to obviate the need for cooling fans.
The output stage of an amplifier is generally designed to deliver a substantial amount of power into a low-impedance load with acceptably low levels of signal distortion. Therefore, the amplifier output stages are generally designed to have one or more of the following properties: large output current swing, large output voltage swing, low output impedance, and low standby power. Additionally, the output stage is further designed to have sufficiently good frequency response such that it will not present a limitation to the rest of the amplifier circuit.
The output stage power transistors are generally several hundred to thousand times bigger than the diode connected transistors that is used for their quiescent current setting, and thus, their base-emitter voltage V.sub.BE is different. Therefore, emitter degeneration resistors are used in both output stage power transistors and diode connected transistors to help in setting the quiescent current. However, as the temperature of output stage power transistors rises, the quiescent current changes as a result since the diode connected transistors are not at the same temperature as the output stage power transistors. Therefore, setting and controlling a temperature stable quiescent current has been a major challenge.
One conventional approach to this problem is through several mask changes to properly adjust the quiescent current. However, the quiescent current adjusted through several mask changes still exhibit variations among the different wafers due to process tolerances. Moreover, several mask changes to properly adjust the quiescent current takes significant amount of time, substantially prolonging the time to market period.
Furthermore, one of the major failures of these output stages is the possible burn-out of the output devices or interconnections due to accidental or transient overload conditions given that the output stages are designed to handle large signal swings at relatively high current levels. A typical example of such an overload condition would be the accidental short circuit of the output to the power supply or the ground terminals. In such cases, the burn-out of the output devices or other permanent damage to the monolithic circuit can be avoided by limiting the maximum available output current to a safe value. This safe value is determined by the size and layout of the output devices and by the maximum allowable power dissipation considerations.
FIG. 1 shows a conventional class AB output stage with short circuit protection which operates in the event of an output short circuit while the output voltage V.sub.OUT is positive. As shown, two resistors R.sub.E1 and R.sub.E2 in series are coupled between the emitter terminal of transistor T.sub.1 and the emitter terminal of transistor T.sub.2. Furthermore, the base terminal of transistor T.sub.3 is coupled to the emitter terminal of transistor T.sub.1, while the base terminal of transistor T.sub.1 is coupled to the collector terminal of transistor T.sub.3. As further shown in FIG. 1, the emitter terminal of transistor T.sub.3 is coupled to the output node of the class AB output stage. Also shown in FIG. 1 are two diodes D.sub.1 and D.sub.2 coupled in series between the collector terminal of transistor T.sub.3 and the base terminal of transistor T.sub.2.
Accordingly, in the manner described above, a large current which flows through transistor T.sub.1 in the event of a short circuit will develop a voltage across resistor R.sub.E1 having a sufficient value to turn transistor T.sub.3 on. The collector of transistor T.sub.3 will then conduct most of the bias current I.sub.BIAS taking transistor T.sub.1 out of its base drive. The current through transistor T.sub.1 will therefore be reduced to a safe operating level. Thus, this short circuit protection approach ensures device safety.
However, the above short circuit protection approach has the disadvantage that under normal operating conditions, about 0.5 volt drop may appear across each resistors R.sub.E1 and R.sub.E2. This translates into an equivalent reduction in voltage swing at the output in each direction, thus resulting in reduction in efficiency.
FIG. 2 shows a conventional thermal shutdown circuit. As shown, a zener diode Z.sub.1 is coupled between the base terminal of transistor T.sub.1 and the emitter terminal of a turn-on transistor T.sub.2. Transistor T.sub.2 is normally configured to be off. As the chip temperature rises, the combination of the positive temperature coefficient of zener diode Z.sub.1 and the negative temperature coefficient of transistor T.sub.1 base-emitter voltage V.sub.BE1 cancels each other such that the emitter voltage V.sub.E1 of transistor T.sub.1 remains unchanged.
Since the base voltage V.sub.B of transistor T.sub.2 is obtained from the emitter voltage V.sub.E1 of transistor T.sub.1 with a resistor divider (comprising resistors R.sub.1 and R.sub.2), the base voltage V.sub.B of the of transistor T.sub.2 likewise remains unchanged. On the other hand, the base-emitter voltage V.sub.BE2 of transistor T.sub.2 decreases with the increase in temperature at a rate of approximately 2 mV/.degree. C. and transistor T.sub.2 begins conducting. Naturally, the precise point at which transistor T.sub.2 begins conducting would largely depend upon the parameters of the transistor T.sub.2 itself. Thus, by setting the temperature of the base voltage V.sub.B of transistor T.sub.2 at 150.degree. C., thermal shutdown can be achieved.
In this manner, the turn-on transistor T.sub.2 is configured to absorb the bias current of the amplifier, therefore virtually shutting down its operation in the event that the temperature exceeds a safe preset value.
The conventional output stages are generally voltage drivers and therefore lack inherent current limitation. To cure this, the output stages require some type of feedback for short circuit protection. The traditional method uses a resistor across the emitter-base junction of the short circuit protection transistor to turn it on once a threshold load current is passed. This, in turn, consumes the drive current of the output stage and therefore shuts it down. This approach, however, is not very precise since the exact value of the short circuit protection transistor base-emitter voltage V.sub.BE is not known at the elevated temperature beyond the safe preset value, and where the value of the resistor is too small to be accurately manufactured. For example, a resistor having a value of 0.25 Ohms is necessary for a threshold current of 2 amperes and a base-emitter voltage V.sub.BE of the short circuit protection transistor at 0.5 Volts.
In accordance with another approach, the output stage power transistor base current I.sub.B is used along with a complicated circuitry to perform the short circuit protection. However, since this latter approach involves the .beta. of the power transistor, the total accuracy (for example, a desired accuracy of .+-.20% for a short circuit current of 2 A) protection in this manner significantly decreases. More particularly, since the base current I.sub.B of a bipolar transistor is approximately equal to the emitter terminal current I.sub.E divided by the .beta., the variation in the bipolar transistor emitter current I.sub.E is correspondingly reflected in the base terminal current I.sub.B. Therefore, the .beta. of the output stage power transistor significantly decreases the total accuracy since the .beta. for a bipolar transistor varies greatly (for example, from 30 to 200) depending upon the specific wafer.

High power output stage with temperature stable precisely controlled quiescent current and inherent short circuit protection


A method of processing a workpiece in the chamber of a plasma reactor includes capacitively coupling plasma source power using a ceiling gas distribution plate as the electrode while inductively coupling plasma source power through the ceiling gas distribution plate, and flowing process gas through the gas distribution plate from a gas input to plural gas injection orifices, distributing the gas flow within the gas distribution plate through a succession of arcuate paths joined at respective junctions, dividing gas flow at each junction from a first respective one of said gas flow paths into a respective pair of said gas flow paths in opposite gas flow directions, and restricting the arcuate length of each of the arcuate paths to less than half-circles.

In semiconductor fabrication processes, conventional sources of plasma source power, such as inductively coupled RF power applicators or capacitively coupled RF power applicators, introduce inherent plasma density non-uniformities into the processing. In particular, inductively coupled plasma sources are characterized by an "M"-shaped radial distribution of plasma ion density over the semiconductor workpiece or wafer. As device geometries have continued to shrink, such non-uniformities become more critical, requiring better compensation. Presently, the non-uniformity of an overhead inductively coupled source is reduced or eliminated at the wafer surface by optimizing the coil design and the ceiling-to-wafer distance of the chamber. This distance must be sufficient so that diffusion effects can overcome the effects of the non-uniform ion distribution in the ion generation region before they reach the wafer. Generally, for an inductively coupled plasma source power applicator (e.g., a coil wrapped around the side wall) located near the ceiling, a large ceiling-to-wafer distance is advantageous. However, a large ceiling-to-wafer distance can prevent the beneficial gas distribution effects of a ceiling gas distribution showerhead from reaching the wafer surface, due to diffusion over the large distance. For such large ceiling-to-wafer distances, it has been found that the gas distribution uniformity is not different whether a gas distribution showerhead is employed or a small number of discrete injection nozzles are employed. In summary, the wafer-ceiling gap is optimized for ion density uniformity, which may not necessarily lead to uniform gas distribution.
One limitation of such reactors is that not all process parameters can be independently controlled. For example, in an inductively coupled reactor, in order to increase reaction (etch) rate, the plasma source power must be increased to increase ion density. But, this increases the dissociation in the plasma, which can reduce etch selectivity and increase etch microloading problems, in some cases. Thus, the etch rate must be limited to those cases where etch selectivity or microloading is critical.
Another problem arises in the processing (e.g., etching) of multi-layer structures having different layers of different materials. Each of these layers is best processed (e.g., etched) under different plasma conditions. For example, some of the sub-layers may be best etched in an inductively coupled plasma with high ion density and high dissociation (for low mass highly reactive species in the plasma). Other layers may be best etched in a capacitively coupled plasma (low dissociation, high mass ions and radicals), while yet others may be best etched in plasma conditions which may be between the two extremes of purely inductively or capacitively coupled sources. However, to idealize the processing conditions for each sub-layer of the structure being etched would require different process reactors for each of the different sub-layers, and this is not practical.
Gas distribution is most effectively controlled by injecting the process gas into the reactor chamber through a gas distribution showerhead forming a portion of the ceiling overlying the wafer pedestal. Inductively coupled power distribution across the wafer is most effectively controlled by providing an inductively coupled power applicator (coil antenna) over the ceiling facing the wafer support pedestal. The problem is that if a ceiling gas distribution showerhead is combined with an overhead (ceiling) coil antenna, power from the coil antenna ionizes the process gas inside the showerhead, which degrades process control. Thus, there has seemed no way to combine the overhead gas distribution showerhead with an overhead coil antenna.

Plasma process for inductively coupling power through a gas distribution plate while adjusting plasma distribution


A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.

1. Field of the Invention
The present invention relates generally to a forward error correction apparatus and method in a digital communication system, and in particular, to a forward error correction apparatus and method in a digital communication system for high-speed data transmission.
2. Description of the Related Art
Generally, in a digital communication system, errors occur due to the noise generated in a transmission link, and various error correction techniques are used to correct the errors. In a wireless communication system adopting the 3GPP (3rd Generation Partnership Project) or 3GPP2 (3rd Generation Partnership Project 2) standard, use of a convolutional code has been proposed for transmission of voice and control signals, and use of a turbo code has been proposed for effective transmission of high-speed data. Of the codes stated above, the turbo code for transmission of high-speed data is advantageous in that it has a very low bit error rate (BER) at a low signal-to-noise ratio (SNR). However, the turbo code has several shortcomings in terms of its performance and implementation, discussed below.
First, the turbo code has a relatively short minimum distance. Therefore, during decoding of a signal coded with the turbo code, an error floor phenomenon may occur at a desired bit error rate. In addition, undetected error probability for a codeword in which an error has occurred during decoding is relatively high.
Second, in the decoding process of the turbo code, efficient decoding stop is needed to reduce decoding time and power consumption during the decoding process. Therefore, in order to provide an efficient decoding stop, a CRC (Cyclic Redundancy Code) check process for error detection at each iterative decoding, or an additional algorithm for the decoding stop is required.
Third, an algorithm for decoding the turbo code cannot be realized in a parallel architecture, so there are limitations in increasing the decoding rate.
Recently, a low density parity check code (hereinafter referred to as "LDPC code") has attracted public attention as a code that is similar or superior to the turbo code in performance, and can resolve the above problems. The LDPC code has a very small number of '1's in each row and column of a parity check matrix defining a code, and its structure can be defined by a factor graph consisting of a check node, a variable node, and an edge connecting the nodes. The LDPC code has a longer minimum distance than a turbo code with the same length. Therefore, it is generally known by those skilled in the art that in the LDPC code, compared with the turbo code, an error floor occurs at a very low bit error rate and the undetected error probability for a defective codeword is very low; experimentally, it has been shown to be close to zero. In addition, the LDPC can be implemented in a parallel architecture, contributing to a drastic reduction in decoding time, and can enable efficient decoding stop through parity check performed at each iterative decoding without some overhead, such as an additionally added CRC or a decoding stop algorithm.
The decoding process of the LDPC code is performed by iterative decoding based on a "sum-product" algorithm. An optimum sum-product algorithm includes a somewhat complicated arithmetic expression. Therefore, when the sum-product algorithm is used, a large amount of calculation is required in the decoding process. Accordingly, the use of the sum-product algorithm undesirably increases hardware complexity.
Therefore, when the LDPC code is used, there is necessity to further simplify the optimum decoding algorithm in an actual implementation. In order to minimize performance degradation due to the simplified algorithm, a weighting factor is applied to extrinsic information generated in the decoding process.
A detailed description will first be made of the LDPC code. The LDPC code can be defined by a factor graph. The factor graph consists of a check node indicating a parity check expression of a predetermined LDPC code, a variable node indicating each code symbol, and an edge indicating dependency between the nodes. The edge connects each check node to a variable node corresponding to a code symbol included in the parity check expression indicated by the check node. If the number of variable nodes connected to all check nodes is fixed to dc and the number of check nodes connected to all variable nodes is fixed to dv, a corresponding LDPC code is called "regular LDPC code." In addition, if the number of edges connected to each check node and variable node is not constant, the corresponding LDPC code is referred to as "irregular LDPC code." Herein, only the regular LDPC code will be considered.
A process of decoding the LDPC code is performed by iterating a process in which a variable node and a check node on a factor graph exchange messages generated and updated for each node. In this case, each node updates a message by using a sum-product algorithm. A sum-product algorithm defined using a log likelihood ratio (hereinafter referred to as "LLR") for decoding of the LDPC code, and an LDPC code iterative decoding process based on the sum-product algorithm will be described herein below.
First, initialization (j=0) is performed as follows. An initial message of a variable node n is defined as the channel reliability of an nth symbol of a received codeword, and this is shown by
                              q          mn                      (            0            )                          =                              l            n                          (              0              )                                =                      ln                                      (                                                p                  0                                /                                  p                  1                                            )                                                          Equation                                                            (          1          )
In Equation (1),
  q  mn      (    0    )  is an initial value of an initially defined variable node message, and
  l  n      (    0    )  is an initial LLR value for the initially defined variable node. In addition, P0 and P1 are transmission link transition probabilities for a symbol '0' and a symbol '1', respectively.
After the initialization process, iterative decoding must be carried out. A description will now be made of iterative decoding at jth iteration. At the jth iteration, a check node message is updated (check node message update process). That is, the check node message becomes a message transmitted from a check node n to a variable node n. This can be expressed by
                              r          mn                      (            j            )                          =                  ln                                (                                          1                +                                                      ∏                                          i                      =                      1                                                                                d                        c                                            -                      1                                                                                tanh                                                              (                                                                        q                          i                                                      (                            j                            )                                                                          /                        2                                            )                                                                                1                -                                                      ∏                                          i                      =                      1                                                                                d                        c                                            -                      1                                                                                tanh                                                              (                                                                        q                          i                                                      (                            j                            )                                                                          /                        2                                            )                                                                                )                                              Equation                                                            (          2          )
In Equation (2),
  r  mn      (    j    )  is a value obtained in a jth iterative decoding process in an iterative decoding process, and represents a message transmitted from a check node m to a variable node n. In addition,
  q  i      (    j    )  represents a message transmitted from a variable node i to a check node m in a jth iterative decoding process. Here, i indicates a value determined by rearranging variable nodes connected to a check node m from 0 to dc−1. Therefore, when i=0, it means a variable node n.
When a variable node is updated by Equation (2), the variable node transmits a new message to a check node. The transmitted message becomes a message transmitted from a variable node n to a check node m, and this can be expressed by
                              q          mn                      (                          j              +              1                        )                          =                              q            mn                          (              0              )                                +                                    ∑                              i                =                1                                                              d                  v                                -                1                                                                                r              i                              (                j                )                                                                        Equation                                                            (          3          )
In Equation (3),
  q  mn      (          j      +      1        )  is a value obtained in a jth iterative decoding process, and represents a message transmitted from a variable node n to a check node m. At this point,
  r  i      (    j    )  represents a message transmitted from a check node i to a variable node n in a jth iterative decoding process, and i indicates a value determined by rearranging check nodes connected to a variable node n from 0 to dc−1. Therefore, when i=0, it means a check node m.
After initialization is carried out as illustrated in Equation (1) to Equation (3), the LLR update is performed through a process of exchanging messages between a check node and a variable node after an iterative decoding process. The LLR update is achieved by
                              l          n                      (                          j              +              1                        )                          =                              l            n                          (              0              )                                +                                    ∑                              i                =                1                                                              d                  v                                -                1                                                                                r              i                              (                j                )                                                                        Equation                                                            (          4          )
In Equation (4),
  l  n                              (              j        +        1            )      indicates an LLR value defined for a variable node n in a jth iterative decoding process.
After the LLR update is carried out by Equation (4), a decision process is performed. The decision process is achieved according to an LLR update result calculated by Equation (4), and is performed for all code symbols. A method for performing the decision process can be represented byIf ln≧0, {circumflex over (x)}n=0 and else, {circumflex over (x)}n=1  Equation (5)
In Equation (5), ln is an LLR value defined for a variable node n at a particular decoding time. That is, ln is equivalent to
  l  n                              (              j        +        1            )      of Equation (4), and {circumflex over (x)}n represent a codeword symbol estimated through a decoding process.
After the decision process is performed as shown by Equation (5), if a decoded codeword satisfies all parity check expressions, iteration is stopped. However, if the decoded codeword fails to satisfy all parity check expressions, the j value is increased by 1 and then, the process of Equation (2) to Equation (5) is iterated. Such iteration can be performed as many times as a predetermined iteration number. Even after the iteration is performed as many times as a predetermined maximum iteration number, if the codeword fails to satisfy all parity check expressions, the decoding is stopped and then, decoding failure is declared.
In the foregoing description, a sum-product algorithm used by each node in the message update process is called "optimum sum-product algorithm." The optimum sum-product algorithm can be simply derived through a theoretical calculation process without a certain approximation process.
However, the check node message update process shown by Equation (2) can be simplified as shown in Equation (6) below, for approximation.
                                                                                r                            mn                                                          (                              j                              )                                                                                =                                                                                CHK                                                                                (                                                                                q                                    1                                                                    ,                                                                      q                                    2                                                                    ,                                                                                …                                                                                ,                                                                      q                                                                                d                                        c                                                                            -                                      1                                                                                )                                                                                =                                                          CHK                                                                                (                                                                                q                                    1                                                                                CHK                                                                                (                                                                                q                                          2                                                                                ,                                                                                …                                                                                ,                                                                                q                                                                                d                                              c                                                                                -                                            1                                                                                )                                                                                )                                                                                CHK                                                                                (                                                                                q                                    x                                                                    ,                                                                      q                                    y                                                                                )                                                                                =                                                          ln                                                                                (                                                                                1                                    +                                                                                tanh                                                                                (                                                                                q                                              x                                                                                /                                            2                                                                                )                                                                                tanh                                                                                (                                                                                q                                              y                                                                                /                                            2                                                                                )                                                                                1                                    -                                                                                tanh                                                                                (                                                                                q                                              x                                                                                /                                            2                                                                                )                                                                                tanh                                                                                (                                                                                q                                              y                                                                                /                                            2                                                                                )                                                                                )                                                                                ≈                                                                                sgn                            (                                                          q                              x                                                        )                                                                                sgn                            (                                                          q                              y                                                        )                                                                                min                                                                                (                                                                                |                                                                      q                                    x                                                                    |                                                                ,                                                                  |                                                                      q                                    y                                                                    |                                                                                )                                                                                +                                                  c                                                                                (                                                          c                              :                                                                                correction                                                                                factor                                                                                )                                                                                c              =                              {                                                                                -                        0.5                                                                                if                                                                                (                                                              |                                                                                q                                    x                                                                    +                                                                      q                                    y                                                                                |                                                                  >                                  2                                                                |                                                                                q                                    x                                                                    -                                                                      q                                    y                                                                                |                                                            )                                                                                and                                                                                |                                                                                q                              x                                                        -                                                          q                              y                                                                                |                                                      <                            2                                                                                0.5                                                                                if                                                                                (                                                              |                                                                                q                                    x                                                                    -                                                                      q                                    y                                                                                |                                                                  >                                  2                                                                |                                                                                q                                    x                                                                    +                                                                      q                                    y                                                                                |                                                            )                                                                                and                                                                                |                                                                                q                              x                                                        +                                                          q                              y                                                                                |                                                      <                            2                                                                                0                                                              otherwise                                                                                Equation                                                            (          6          )
In Equation (6), qx and qy represent variable node messages applied to the check node. In addition, sgn(x) is a function having a value of 1 for x>0 and a value of −1 for x<0.
Equation (6) shows an optimum sum-product algorithm in which a check node message update process is simplified through an approximation process. For a message updated in a particular check node m, signs of variable node messages on two particular edges are multiplied by each other, and then, the result is used as a sign of a temporary result message. In addition, when compared to the absolute values of the variable node messages, a smaller value is selected and defined as a size of the temporary result message. In order to correct an error caused by the approximation process, the temporary result message is updated by adding a correction factor c determined by a predetermined rule to the temporary result message. Further, a check node message is finally updated by iteratively applying such a process to other edges connected to a check node m except the edges connected to a variable node n. A sum-product algorithm using this is called 'sum-product algorithm with correction factor'. The approximated LDPC code iterative decoding, based on the 'sum-product algorithm with correction factor', shows superior performance with regards to the decoding performance that can be obtained by an optimum sum-product algorithm, without performing the somewhat complicated calculation of tanh( ) in a check node message update process in an LDPC code decoding process based on the optimum sum-product algorithm.
The optimum sum-product algorithm, as can be noted from Equation (2), must perform calculation of tanh( ) function for each of check node messages applied to a check node in order to update a check node message at a particular iterative decoding time. This increases complexity during hardware implementation due to the complicated calculation of tanh( ) function. In order to solve these problems, there has been proposed an algorithm for simplifying a check node message update process through an approximation process and applying a correction factor to the approximation process to minimize performance degradation due to the approximation process. However, the 'sum-product algorithm with correction factor' must determine a correction factor for all edges connected to a check node according to a variable node message delivered from the edges in order to finally update the check node message. Since such an operation must be performed on all edges in sequence, each check node undesirably requires a relatively large amount of calculation and a long calculation time.

Forward error correction apparatus and method in a high-speed data transmission system


An electronic system is provided for stimulating a segmented transducer with resonant electrical signals to produce a nonsinusoidal transducer output. In an illustrative embodiment, the transducer comprises a segmented piezoelectric actuator. The actuator comprises stacked piezoelectric dimorphs forming the actuator segments, each of which reacts electrically as a capacitance. Each segment (capacitance) is connected in a loop in electrical series with an external capacitor or a corresponding segment of a second actuator. An electrical controller stimulates each loop with a separate resonant electrical signal related to the others in frequency, phase, amplitude, and polarity. The resulting output of each actuator is the vector sum of the mechanical outputs of the individual dimorphs of that actuator. In an ideal resonant drive system for a segmented transducer, the only electrical energy used is that which is converted directly to mechanical work by the actuator. All other temporarily stored electric and elastic energy is recycled within the loops for high efficiency. When the electrical waveforms drive a pair of actuators, electrical charge oscillates between the actuators. Thus, loop currents flow between essentially lossless reactive components rather than through high-loss output devices.

The output capability of electrical transducers can be modified and expanded by selectively stimulating joined transducer segments. For example, piezoelectric actuators, an illustrative class of electrical transducers, can be constructed of stacked segments to provide a three-dimensional mechanical output. By combining cyclically alternating traction strokes of two or more piezoelectric actuators, "walking" motion can be produced.
At the start of tractional contact in conventional resonant actuators, such as resonant ultrasonic traveling wave motors, relative velocity between the actuator and a movable object results in initial sliding until firm contact is established. At the end of the traction portion of the cycle, sliding occurs again in preparation for the lift-off and retrace portions of the cycle. In such a system efficiency of electromechanical power conversion is reduced by sliding friction, particularly on retrace when the relative velocity is greatest. The electromechanical conversion efficiency of an actuating device with a conventional resonant drive is generally less than about 40%, with most of the loss caused by sliding friction. Rotors of resonant traveling wave piezoelectric motors are known to become uncomfortably hot to the touch after a few minutes of operation. Furthermore, resonant actuators that use circular or elliptical traction paths impart a time-varying normal force and a time-varying tangential (traction) force to the positioned object or rotor. As a result, linear motion is jerky and motors have torque ripple.
The speed of action of resonant actuators may be adjusted by altering the magnitude of the voltage swings or the mechanical strokes. However, resonant devices operate most efficiently at full power and full speed. Speed reduction by reducing amplitude also reduces efficiency because the energy allocated to sliding friction becomes an increasing fraction of the total available energy. As the size of the circular or elliptical motion is decreased, rubbing during retrace is exacerbated. The lower limit of speed is determined by the resonant amplitude at which traction cycling becomes intermittent or ceases altogether. Holding a controlled stationary position and applying a static traction force are beyond the operating scope of a resonant actuator.
Resonantly excited piezoelectric actuators of the prior art employ the thickness or extension piezoelectric deformation mode, wherein ferroelectric polarization is parallel to the applied electric field. Such polarization is degraded or even reversed if the applied potential causes an electric field anti-parallel to the direction of polarization. Resonance requires that large voltage swings be substantially symmetric about a floating median potential value. Elevation of the floating median value by at least half the peak-to-peak voltage swing above electrical ground avoids depolarization. This requires that the electrical circuitry operate at a relatively high voltage above ground, resulting in a safety hazard in large actuators.
Slowly varying direct current electrical sources, such as programmable DC power supplies, for example, have been used to control piezoelectric positioners. These power sources emulate class A amplifiers but have a restricted frequency response. All the reactive capacitive current flows through the amplifier output devices. A class A amplifier dissipates all of the available power internally under null excitation. The variable DC voltage is essentially free of superimposed high frequency ripple, and it provides smooth control and piezoelectric positioning at slow speeds (including zero speed) with relatively good positioning accuracy. At modest frequencies and voltages, programmable DC power supplies operate piezoelectric actuators as smooth walkers without losses from sliding friction. However, high efficiency is beyond the capability of a programmable DC power supply emulating a class A or class B amplifier. Operation becomes more difficult and less efficient above a few traction cycles per second or with voltages above about 200 volts. Furthermore, none of the known class A or class B linear amplifiers remain stable when driving an entirely capacitive load. Therefore, they ar not applicable to electromechanically efficient piezoelectric walking actuators except at the lowest portion of the amplifier's frequency band.
An electronic drive described in U.S. Pat. No. 4,628,275 issued to Skipper, et al. emulates a class A amplifier. The amplifier provides the high bipolar voltage swings necessary to operate piezoelectric shear actuators. However, the ultrasonic charge transfer cycles of the amplifier, even when holding a steady voltage, accelerate the rate of wear and fatigue in all mechanisms connecting the actuator to positioned objects. Furthermore, the amplifier requires high voltage DC power supplies, large and heavy transformers, and very fast switching devices to achieve modest electrical efficiencies. The use of AC-to-DC power converters and the presence of large reactive currents in output switching devices preclude efficiencies above about 80%.
Piezoelectric actuators capable of smooth walking are inherently well suited to operation in a vacuum, such as in orbiting space stations, because lubrication is not required. The high electromechanical efficiency of piezoelectric actuators, which exceeds 98% neglecting internal electrical losses, also precludes excessive heating during operation, thus eliminating the need for ancillary cooling that reduces overall system efficiency. Furthermore, piezoelectric actuators require no additional energy from the power source to maintain a stationary force.
Operation in a vacuum imposes similar thermal management requirements on the drive electronics. The need for heat removal decreases dramatically with increasing efficiency. Internal heat generation by an ideal electrical power source is negligible when piezoelectric actuators apply a stationary force or operate at low velocities. Ideally, the energy supplied by the drive system should equal the energy converted to useful mechanical work by the actuators. Thus, there is a need for a highly efficient electrical system to supply appropriate resonant waveforms for nonsinusoidal transducer output such as smooth walking motion by piezoelectric actuators.

Electrical drive for a segmented transducer


The invention relates to (among other things) oligomer-containing hydantoin compounds. A compound of the invention, when administered by any of a number of administration routes, exhibits one or more advantages over corresponding compounds lacking the oligomer.

Epilepsy is a common chronic neurological disorder characterized by recurrent unprovoked seizures. These seizures are transient signs and/or symptoms of abnormal, excessive or synchronous neuronal activity in the brain. About 50 million people worldwide have epilepsy, with almost 90% of these people being in developing countries. Epilepsy is more likely to occur in young children or people over the age of 65 years; however, it can occur at any age. Epilepsy is usually controlled, but not cured, with pharmacotherapy, although surgery may be indicated in exceptional cases. Despite the reliance on pharmacotherapy as the primary approach in controlling the disease, over 30% of people with epilepsy do not have seizure control even with the best available medications. Not all epilepsy syndromes are life-long; some forms are confined to particular stages of childhood. Epilepsy should not be understood as a single disorder, but rather as a group of syndromes with vastly divergent symptoms, but all involving episodic abnormal electrical activity in the brain.
In addition to its approved use in the treatment of individuals suffering from epilepsy, phenyloin has been used clinically as an antiarrhythmic agent, an agent to treat preeclampsia, and an agent to treat trigeminal neuralgia. Pharmacokinetically, however, phenyloin exhibits a rate and extent of absorption that can vary widely and is metabolized greatly in the liver. Thus, although phenyloin possesses unique pharmacological properties, the ability to safely and efficaciously utilize the drug for other indications is believed to have been hampered by the drug's wide pharmacokinetic variations following administration.
Therefore, pharmacotherapy with hydantoins, such as phenyloin, could be improved if compounds that retained some degree of the pharmacology of these drugs, yet possessed different chemical structures that could result in different pharmacokinetic profiles. As a consequence, there is an unmet need for developing novel hydantoin compounds.
The present invention seeks to address these and other needs in the art.


A method and apparatus for sorting mail to delivery point sequence includes providing a first sortation assembly adapted to performing a first sort pass to mail articles supplied to it and a second sortation assembly adapted to performing a second sort pass to mail articles supplied to it. Mail articles are supplied to the first sortation assembly which identifies the mail articles and performs a first sort pass to sort the mail articles. The mail sorted by the first sortation assembly is conveyed to the second sortation assembly which performs a second sort pass to sort the mail articles to delivery point sequence depth of sort.

The invention relates generally to an article sorting method and apparatus and, more particularly, to sortation of mail. The invention is especially adapted to sort flat mail to delivery point sequence or carrier walk sequence, but may also apply to a mix of flat mail and letter mail.
Mail is received in a distribution warehouse from typically two sources. One is local mail which is to be delivered within the local area. This is known as turnaround mail. Local mail may also be sorted for delivery to other distribution centers. The other source of mail is out-of-area mail received from other distribution centers. Mail which is to be delivered locally must, ultimately, be sorted to delivery point sequence, also known as xe2x80x9ccarrier walk sequence.xe2x80x9d A Dual Bar Code Sequenced (DBCS) machine is capable of achieving delivery point sequence for letter mail. However, it requires two or more passes of the mail through the same sequence. A first depth of sort is achieved with the first pass. The letters are then loaded into trays and the trays loaded onto manual carts. The trays are then unloaded from the manual carts and reprocessed during a second pass. An alternative to manual handling of the trays of mail between passes is disclosed in U.S. Pat. No. 5,385,243 which utilizes a storage and retrieval machine to stage the letter trays for the second pass.
Flat mail is mail which ranges in length of from 5 inches to 15 inches, height of from 6 inches to 12 inches, thickness of from 0.009 inches to 0.75 inches, and weight of from 0.01 pound to 1.0 pound. It may include paper envelopes, plastic wrappers, bound catalogs, banded newspapers, open mail pieces without wrappers, and the like. Such flat mail has traditionally been sorted to the distribution center level automatically, such as utilizing a model AFSM 100 flat sorting system manufactured by Mannesmann Dematic Postal Automation and marketed in the United States by Mannesmann Dematic Rapistan Corp. The sortation from distribution center to carrier walk sequence has traditionally been performed manually utilizing pigeon-hole bins. Such manual sorting of flat mail to the delivery point sequence may take several hours, up to half of the time available for a carrier to deliver his/her route.
It would be desirable to provide a carrier walk sequence for mail, especially for flat mail. It would be most desirable if the carrier walk sequence of flat mail is accomplished irrespective of source or type of the mail. In particular, it would be desirable to be able to sort turnaround mail to carrier walk sequence.
The present invention provides a method and apparatus for sorting flat articles which is capable of sorting to delivery point sequence. The invention is capable of sorting to delivery point sequence irrespective of the source of the articles.
According to an aspect of the invention, an article sortation apparatus for sorting mail includes a first sortation assembly, a second sortation assembly, and a conveying assembly. The first sortation assembly includes a first induct, a first sortation mechanism which sorts articles from the first induct to a plurality of containers. The second sorting assembly includes a second induct, a second sortation mechanism which sorts articles from the second induct to an output. The conveying assembly conveys containers from the first sortation mechanism to the second induct. The first sortation assembly may be programmed to resolve the address of each article, apply a pseudo identification to the article, which is retained in a control, and sort the article to bins or containers. The second sortation assembly calls for containers from the first sortation assembly in the control by the first sortation assembly in a particular order and carries out a delivery point sequence sortation on the articles in those containers using the information stored in the control by the first sortation assembly. Preferably, the delivery point sequence sortation is to 9 zip code digits and, most preferably, to 11 zip code digits.
A method of sorting mail to delivery point sequence, according to another aspect of the invention, includes providing a first sortation assembly that is adapted to performing a first sort plan to mail articles supplied thereto and a second sortation assembly adapted to performing a second sort plan to mail articles supplied thereto. Mail is supplied to the first sortation assembly identified and sorted to bins or containers. The mail articles sorted by the first sortation assembly are supplied to the second sortation assembly in a particular sequence and sorted to delivery point sequence.

Delivery point sequencing mail sorting system with flat mail capability


A non-aqueous liquid electrolyte suitable for use in a non-aqueous liquid electrolyte secondary battery comprising a negative electrode and a positive electrode, capable of intercalating and deintercalating lithium ions, and the non-aqueous liquid electrolyte, the negative electrode containing a negative-electrode active material having at least one kind of atom selected from the group consisting of Si atom, Sn atom and Pb atom, wherein the non-aqueous liquid electrolyte comprises a carbonate having at least either an unsaturated bond or a halogen atom.

In recent years, with the reduction in weight and size of electrical appliances, development of a non-aqueous liquid electrolyte secondary battery having high energy density, for example lithium secondary battery, has been advanced. Also, as application field of lithium secondary battery is expanded, further improvement in its battery characteristics has been desired.
In this situation, a secondary battery based on metal lithium as negative electrode has been studied as a battery capable of achieving higher capacity. However, there is a problem that metal lithium grows as dendrite on repeated charges and discharges, and when this reaches the positive electrode, short circuit in the battery occurs. This has been the greatest obstacle in putting a lithium secondary battery based on metal lithium as negative electrode to practical use.
On the other hand, a non-aqueous liquid electrolyte secondary battery has been proposed, in which carbonaceous material capable of intercalating and deintercalating lithium, such as coke, artificial graphite or natural graphite, is used for the negative electrode in place of metal lithium. In such a non-aqueous liquid electrolyte secondary battery, growth of metal lithium as dendrite can be avoided and therefore, battery life and safety can be improved. When graphite of this kind is used as negative electrode, capacity is known to be usually of the order of 300 mAh·g−1, 500 mAh·cm−3.
In recent years, proposals have been made for the negative-electrode active material based on simple metal element capable of forming an alloy with lithium such as silicon (Si), tin (Sn) and lead (Pb), an alloy containing at least one of these metal elements, or metal compound containing these metal elements (hereafter referred to as "negative-electrode active material containing Si, Sn, Pb and the like", as appropriate). The capacity of these materials per unit volume is of the order of 2000 mAh·cm−3 or larger, which is about 4 times that of graphites or even larger. Therefore, higher capacity can be obtained by using these materials.
Although a secondary battery using negative-electrode active material containing Si, Sn, Pb and the like is suitable for realizing higher capacity, there is a decrease in safety, and negative-electrode active material deteriorates on repeated charges and discharges, leading to reduced charge-discharge efficiency and deterioration of cycle performance.
Therefore, in order to secure safety and prevent a decrease in discharge capacity, a proposal has been made to include cyclic carbonate ester or a polymer of carbonate ester and phosphoric acid triester in the non-aqueous liquid electrolyte used for a secondary battery (refer to Patent Document 1). Furthermore, a proposal has been made to add, in the non-aqueous liquid electrolyte, a heterocyclic compound having sulfur atom and/or oxygen atom in the ring structure and to form a protective layer on the surface of the negative-electrode active material, thus improving charge-discharge cycle performance (refer to Patent Document 2). Moreover, another proposal has been made to add, in the non-aqueous liquid electrolyte, LiB(C2O4)2 to form a protective layer on the negative electrode, thus improving cycle performance (refer to Patent Document 3).    [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 11-176470    [Patent Document 2] Japanese Patent Laid-Open Publication No. 2004-87284    [Patent Document 3] Japanese Patent Laid-Open Publication No. 2005-228565

Non-aqueous liquid electrolyte and non-aqueous liquid electrolyte secondary battery


The present disclosure provides a sealing apparatus for use in a hypertube, which includes a first tube, a second tube having one end connected to an end of the first tube, and a gasket including a seal made of a fiber structure formed with a space that is filled with a sealing fluid, wherein the gasket is configured to seal a space between the first tube and the second tube.

The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.
There are efforts to realize a hypertube system which is an ultra-high-speed vacuum train system capable of greatly improving a vehicle speed by minimizing air resistance through a vehicle tube conditioned close to a vacuum. To install the hypertube system requires constructing a vacuum or near-vacuum tunnel (tube). Such a tube needs to be formed to a greatly extended length, which involves connecting a plurality of tube units. The tunnel is vulnerable at fittings between tube units to an inflow of external air which is supposed to be blocked to maintain the near-vacuum state inside the tunnel. The primary interest of the hypertube system is to closely maintain the sealing of the tube.
Among well known sealing technologies are welding together tubes of metals such as carbon steel, stainless steel, aluminum or the like, arranging tube sections of a groove type, a metal bellows type, polyethylene or other polymer materials with an elastomer gasket interposed to establish a closed tunnel, and a method of filling gaps between the tube sections by using an adhesive such as epoxy, silicone, or the like.
However, the sealing methods using welding or adhesive are susceptible to thermal deformation occurring in the tube due to the temperature difference between the seasons and between day and night, leading to degraded buffering and damage at the fittings accompanied by their premium construction costs. On the other hand, the gasket-based sealing method bears the property of an elastomer such as epoxy, silicone, etc. which when subjected to an extended fastening pressure exhibits a compression deformation that reduces the thickness of the sealing areas, thereby degrading sealing performance.


An impervious corrosion resistance nickel-chromium coating on a metallic substrate, such as an iron-containing alloy substrate that protects the substrate from a corrosive media and the process for producing the coating on the substrate.

Iron-containing alloys, such as different grades of steel and stainless steels, are subject to corrosion when exposed to aqueous environments. Thermally-sprayed coatings are frequently used in corrosive environments to provide wear resistance. There are many thermal spray coatings whose corrosion characteristics are superior to iron-containing alloys. The use of such wear and corrosion resistant coatings may be limited by the corrosion behavior of the substrate. This is because of the interconnected porosity which is inherently present in thermally-sprayed coatings. This interconnected porosity may allow the corrosive media to reach the coating substrate interface. An example of the problem is the use of a plasma-sprayed Cr.sub.2 O.sub.3 coating on a 300 series stainless steel substrate in sea water. This coating/substrate combination is frequently used for applications such as mechanical seals. The Cr.sub.2 O.sub.3 coating itself has good wear and corrosion resistance, but the stainless steels are susceptible to crevice corrosion. Consequently, Cr.sub.2 O.sub.3 coatings on 300 series stainless steels frequently fail in a sea water environment. The fabrication of mechanical seals from nickel base corrosion resistant alloys is expensive. Weld deposited overlays of nickel base corrosion resistant alloys on iron base alloys have both technical and cost problems.
It is an object of the present invention to provide an impervious coating for a metallic alloy substrate, such as an iron-containing alloy, a copper-containing alloy, a cobalt-containing alloy, an aluminum-containing alloy, or a nickel-containing alloy, that can be used in aqueous environments.
It is another object of the present invention to provide a process for protecting a metallic alloy from aqueous corrosion by applying an impervious coating to such alloy.
The foregoing and additional objects will become more apparent from the description and disclosure hereinafter.

Nickel-chromium corrosion coating and process for producing it


A method of diagnosis comprises determining genotype of a TGF-.beta.1 promoter-specific polmorphisms that have been identified are at positions -800bp and -509bp. The genotype determined is then used to assess predisposition or susceptibility to a number of diseases: osteoporosis, atherosclerosis, cancer and immune disorders.

1. Field of the Invention
This invention relates to diagnostic method and apparatus based upon a polymorphism in a TGF-.beta. gene. More specifically, this invention relates to a method for diagnosis of pre-disposition to certain disease states, by screening for the presence of this polymorphism. The invention also relates to apparatus for screening for the polymorphism. The invention further relates to TGF-.beta. genes containing the polymorphism and to a probe therefor.
2. Related Art
A number of major disease states are associated with or correlated with concentration of transforming growth factor .beta. (TGF-.beta.) in circulating plasma. Diseases that have been correlated in this way include atherosclerosis, certain forms of cancer, osteoporosis and a number of auto immune disorders, such as rheumatoid arthritis, multiple sclerosis, systemic lupus erythematosus, late on set diabetes and others.
In a number of cases, therapy is available for these disease states. However, a problem common to many of these therapies is that whilst the therapy is capable of halting further development of the disease, the therapy is nevertheless not capable of reversing or curing the diseased state to a significant extent.
Hormone replacement therapy is an established treatment for osteoporosis and has proved successful in halting further decline in bone density that is characteristic in women suffering from this disease. Hormone replacement therapy is generally not, however, able to bring about a reversal of osteoporosis, that is to say it is not capable of inducing an increase in the bone density of sufferers.
It would, accordingly, be of particular advantage to be able to identify with increased accuracy those individuals having a predisposition or increased susceptibility to osteoporosis. Suitable therapy could then be put into place before the effects of osteoporosis set in.
A similar situation obtains in respect of atherosclerosis and cancer. In the latter case, treatment of cancer often involves severe side effects. If it were possible to identify individuals with a predisposition or increased susceptibility to cancers then there would be advantage in providing those individuals with preventative therapy to reduce or prevent or delay the onset of cancer as part of a therapy having reduced side effects to those seen with the standard cancer treatments available.

Methods of diagnosis by detecting polymorphisms in the TGF-.beta.1 promoter


Power amplifier (PA) apparatus that includes: a PA device operating at a fundamental frequency and having a maximum operating frequency that is higher than the fundamental frequency, an output current having a fundamental component at the fundamental frequency and a plurality of harmonic components at different harmonic frequencies of the fundamental frequency, and an output voltage based on the output current; a first matching circuit coupled to the PA device and corresponding to the fundamental component; and a second matching circuit coupled between the PA device and the first matching circuit and corresponding to at least one of the harmonic components, wherein the first and second matching circuits maintain the PA output voltage at a value that is no more than a predetermined maximum value, which is less than a breakdown voltage for the PA device.

Radio frequency (RF) devices, e.g., RF transistors and RF power amplifiers ("PAs") containing RF power transistors, are used in a wide variety of communications and other electronic applications, such as cellular handsets and base radio repeaters. RF power amplifiers are typically made up of one or more cascaded amplifier stages, each of which increases the level of the signal applied to the input of that stage by an amount known as the gain of the stage. It should be noted that the terms RF device, PA device and power transistor device are used herein interchangeably to describe a device that includes one or more power transistors operating as a power amplifier in an application.
In recent years, manufactures of PA apparatus that includes a PA device comprising one or more power transistors have generally focused efforts on increasing the maximum operating frequency of those devices to accommodate higher frequency markets such as, for instance, 2 GHz markets. Companies that develop applications that span a range of operating frequencies may, for reasons such as leveraging volume and cost considerations, desire to use a single PA design, transistor or power-integrated circuit (IC) 'device' for all or a significant portion of their applications. However, designers are confronted with a new challenge when using readily available power amplifier devices in "lower frequency designs" than what the power amplifier or device is otherwise capable of or intended for. A power transistor device within the power amplifier can self-destruct as the amplifier output power is increased. This self-destruction phenomenon is also referred to as a "lack-of-ruggedness" and can occur at power levels of varying degrees below the power level at which the device is rated.
FIGS. 1 and 2 will be used to further describe this self-destruction phenomenon. FIG. 1 illustrates exemplary power amplifier apparatus 100 as described above that may be used in applications having a maximum operating frequency of 1 GHz for instance. Apparatus 100 comprises at least one power transistor 110 that functions as a power amplifier and a matching network 120 connected to the output of transistor 110. In this illustrated embodiment, power transistor 110 is a power field effect transistor (FET) such as a lateral diffused metal-oxide-semiconductor (LDMOS) transistor having a drain at a node 112, a gate at a node 114 and a source at a node 116. The matching network 120 is connected to nodes 112 and 116.
In operation, the gate of transistor 110 is coupled to an RF input waveform at a given fundamental or main frequency, which typically comprises an RF carrier modulated with information to be communicated over the air or a cable. Transistor 110 then generates an amplified RF signal at its output, which creates a voltage response between the drain and source (Vds). Vds is a function of a drain current Id generated in the transistor and an impedance, which is based on matching network 120 as "seen" by Id. Generally, Id comprises a spectral component at the fundamental frequency (also referred to herein as the fundamental component) and spectral component(s) at one or more harmonic frequencies (also referred to herein as harmonic components), where a harmonic frequency is defined as an integral (whole-number) multiple of the fundamental frequency.
In a typical application, transistor 110 is operated near its maximum operating frequency. Therefore, it is usually sufficient to design matching network 120 to correspond to or "dominate" only the fundamental component of Id to cause the transistor to operate within whatever design specifications are required for the application. Dominate herein means to specifically or overtly load a given spectral component of the output current of a PA device with a desired impedance to create a corresponding desired spectral component of the voltage response at the output of the PA device. Those skilled in the art will realize that in a physical circuit impedance is affected by many factors. In addition, the impedance is the inverse of a complex admittance value, wherein the real part of the admittance value is directly related to the slope of the load line.
FIG. 2 illustrates an exemplary Vds output waveform 220 generated by transistor 110 over time where transistor 110 is being operated at a fundamental frequency that is substantially less than the maximum operating frequency of the transistor. In this illustration, transistor 110 has a Vds specification (or maximum breakdown voltage rating) of about 65 volts and is being operating at a fundamental frequency in the VHF frequency range, in this case about 146 MHz. However, as FIG. 2 shows, operating the transistor in this manner generates a Vds output waveform 220 comprising high instantaneous voltage peaks (e.g., 222 and 224) that exceed the maximum Vds voltage specification of the transistor. These voltage peaks are caused by the additive effects of harmonic component(s) of Id, in turn generating harmonic Vds components, and are what causes transistor 110 to self-destruct when it is being operated at certain frequencies that are less than the maximum operating frequency of the transistor. In other words, the power transistor has available gain at a number of harmonics, which may create the undesirable time-domain RF voltage waveform. Currently, there exists no suitable method for the application designer to address this lack-of-ruggedness problem.
Embodiments of the present invention as described below in detail provide for techniques that address the need for eliminating elevated peaks in the Vds output voltage of a power transistor that exceed the maximum break down voltage of the transistor to enable it to be operated for a larger range of frequencies that are substantially lower than a given predetermined maximum operating frequency of the transistor.

Method and apparatus for controlling an output voltage in a power amplifier


A tracking control unit for an optical disk drive comprises a TES detection circuit for detecting a tracking error signal (TES) in an output of a photodetector included in a stationary optical system, a frictional state prediction circuit for predicting a frictional state between guide shafts and a carriage on the basis of the TES detected by the TES detection circuit, a phase compensation filter for compensating for a phase difference of the TES detected by the TES detection circuit so as to stabilize a tracking control system on the basis of the result of the prediction performed by the frictional state prediction circuit, and a driver for moving the carriage in a direction in which a tracking error can be corrected for according to an output of the phase compensation filter and for thus controlling tracking.

1. Field of the Invention
The present invention relates to a tracking control unit for an optical disk drive capable of controlling tracking using an actuator of a fine-and-coarse driving integrated type.
2. Description of the Related Art
For realizing cost reduction for an optical disk drive, a method using the thrust of the same coil to control both tracking and access is effective. Specifically, as disclosed in Japanese Unexamined Patent Publication No. 63-224037, one tracking actuator is used for both fine driving and coarse driving instead of including a fine-driving actuator (designed for controlling tracking and movable in a narrow range) and a coarse-driving actuator (designed for controlling access and movable in a wide range).
For materializing such an actuator of a fine-and-coarse driving integrated type, a bearing may be placed between guide rails for supporting a carriage having a focus actuator and reflection mirror mounted thereon. In this case, there arises problems that a movable portion becomes large in size, a weight increases, and a resonant frequency for a high-order mode of resonance falls accordingly. A support for the carriage is therefore designed to be of a sliding type (sliding bearing) in practice.
When a bearing is of the sliding type, every time the carriage moves, frictional force works on the carriage and guide rails. When frictional force is present, a phenomenon that a deviation remains with a control residual derived from frictional force and driving force generated by a tracking servo system against the control residual balanced takes place. The residual is referred to as an individual frictional distance.
When tracking is controlled in an optical disk drive, a control residual corresponding to the individual frictional distance is observed at two points during one rotation of a disk depending on an eccentric state of a track.
To be more specific, as shown in FIG. 17, since information tracks on an optical disk are generally eccentric, when the disk is rotated, a certain information track is seen shifting in a direction substantially orthogonal to the tracks according to a rotational frequency ("eccentric position" in FIG. 17). Owing to tracking control, a light beam attempts to follow the eccentricity. As shown in "eccentric speed" in FIG. 17, when a moving speed is zero, that is, when a magnitude of eccentricity reaches peak, a state of static friction is attained. A control residual therefore increases transiently ("control residual" in FIG. 17). In some eccentric state, a residual may occur at many instants of time.
A control residual of a certain magnitude adversely affects the data writing/reading characteristic of an optical disk drive.
A way of reducing the residual is to increase a loop gain of a tracking control system. It is difficult for an actuator of a fine-and-coarse driving integrated type to set the resonant frequency for a high-order mode of resonance to a high frequency for structural reasons. Since it is hard to raise a frequency band to which servo system is sensitive, it is difficult to increase the loop gain.
By the way, for coping with a phenomenon that a residual resulting from tracking control increases transiently due to vibration or the like, a method in which when a window comparator or the like detects that the control residual becomes equal to or larger than a given value, a gain to be produced by a control system is increased is known. One approach has been disclosed in Japanese Unexamined Patent Publication No. 6-139588.
However, the approach described in the Japanese Unexamined Patent Publication No. 6-139588 is intended to reset a moving device for a short period of time when a relatively large residual such as a servo failure derived from external vibration or a flaw on a disk occurs or when a servo loop is disabled. It is difficult to suppress a relatively small residual such as a transient increase in control residual derived from friction which is critical for an actuator of a fine-and-coarse driving integrated type supported by a sliding bearing.
For suppressing a small residual, a threshold is lowered so that a servo system can sensitively react on the small residual. In the approach described in the Japanese Unexamined Patent Publication No. 6-139588, judgment is made from the level of a residual alone. In case a tracking control system oscillates due to an increase in gain, since a tracking error signal whose level gets higher because of oscillation is detected, the gain remains increased. Consequently, the oscillation may be maintained.
Furthermore, in general, the tracking control system is susceptible to the state of a disk employed. For example, the distortion of a tracking error signal occurring at a pre-pit area or the occurrence frequency of a control residual derived from the eccentricity of the disk depends greatly on the state of a disk. When an attempt is made to design the tracking control system so that it can tolerate such factors and be kept off malfunctions including oscillation, if the approach described in the Japanese Unexamined Patent Publication No. 6-139588 is adopted, since a threshold must be set to a large value, the ability to suppress a microscopic control residual such as a residual derived from friction hardly works.

Tracking control unit for optical disk drive capable of suppressing control residual derived from disturbance


An arcuate shield having a concave interior surface is formed as a semi-conical configuration having first and second side edges converging towards a forward edge. The shield structure is arranged to mount a pneumatic hose medially and in contiguous communication with an inner concave surface of the shield. A modification of the invention further includes fan blades arranged for mounting adjacent a rear edge of the shield structure to enhance coverage of the shield, as well as providing for adjustment to modify the arcuate configuration of the shield structure to afford adjustment of the confronting surface of the shield structure.

1. Field of the Invention
The field of invention relates to shield apparatus, and more particularly pertains to a new and improved debris shield apparatus wherein the same is arranged to deflect debris relative to pneumatic hoses.
2. Description of the Prior Art
The use of pneumatic hoses in various cleaning procedures effects the scattering of various airborne particles. To afford protection to an operator, the instant invention provides for a convenient and readily mounted structure relative to a pneumatic hose structure. Pneumatic nozzles of various types are directed in the prior art and exemplified in U.S. Pat. No. 4,842,203 to Kohn.
The U.S. Pat. No. 4,867,380 to Sibbersten sets forth a compressed air blower structure typically utilized in a cleaning type procedure.
As such, it may be appreciated that there continues to be a need for a new and improved debris shield apparatus as set forth by the instant invention which addresses both the problems of ease of use as well as effectiveness in construction and in this respect, the present invention substantially fulfills this need.


A method for characterizing complexity of rock fracture based on fractal dimension and a device thereof are provided. The method includes steps of: collecting rock fracture samples of a rock, and collecting basic parameters of the rock; determining a fractal dimension of a rock fracture morphology of the rock; calculating the fractal dimension of the rock; calculating a complexity coefficient Fc of rock fracture of the rock; and characterizing a complexity of rock fracture of the rock based on the complexity coefficient Fc of rock fracture of the rock. In the present invention, combined with the fractal geometry theory, fracture complexity coefficient of shale rocks is redefined and calculated to accurately characterize rock fracture morphology, so that characteristics of rock fracture morphology is correctly understood and affecting factors of fracture morphology is analyzed.

The fracture of shale rocks is generally divided into three failure/fracture modes, namely, tensile splitting failure, multi-slit shear failure and single-slit shear failure. However, this division of sub-categories of fracture modes is relatively simple and may not accurately reflect the true fracture morphology of rocks, because the rock fracture morphology is not a single mode of absolute tensile splitting or single-slit shearing, but a complex fracture morphology with multiple fracture modes, and further because the complexity of rock fracture is different under different degrees of single fracture mode.
Therefore, it is necessary to accurately characterize the rock fracture morphology in order to correctly understand the characteristics of the rock fracture morphology and analyze the affecting factors of the fracture morphology.
It should be noted that the above description of the technical background is merely for the purpose of facilitating a clear and complete description of technical solutions of the present invention, and is convenient for understanding by those skilled in the art. The above technical solutions should not be considered to be well-known to those skilled in the art, simply because these aspects are set forth in background section of the present invention.

Method for characterizing complexity of rock fracture based on fractal dimension and device thereof


A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask layer to form a projection electrode of the second metal; and removing the stopper mask layer after the metal supplying step.

1. Field of the Invention
The present invention relates to a semiconductor device production method and a semiconductor device. Particularly, the invention relates to a semiconductor device having electrodes arranged at a reduced pitch on a semiconductor substrate and to a production method therefore.
2. Description of Related Art
The semiconductor device mounting technology includes so-called flip-chip connection by which a semiconductor chip is directly connected to a wiring board without packaging thereof. The semiconductor chip for the flip-chip connection includes projection electrodes which are provided on a surface of the chip formed with an active layer including a functional device and interconnections. The projection electrodes are respectively bonded to electrode pads provided on the wiring board to establish the flip-chip connection. In this case, the semiconductor chip per se is a semiconductor device.
FIGS. 26(a), 26(b), 26(c) and 26(d) are schematic sectional views for explaining a production method for a conventional semiconductor device having projection electrodes.
An active layer 102 including a functional device and interconnections is formed in one surface of a semiconductor substrate 101, such as a semiconductor wafer, preliminary plagiarized, and electrode pads 103 for electrically connecting the functional device in the active layer to an external device are formed at predetermined positions on the active layer 102.
Subsequently, a passivation film 107 is formed on the semiconductor substrate 101 so as to expose the electrode pads 103. Then, a barrier metal layer (UMP: under bump metal) 104 for protection of the electrode pads 103 and the active layer 102 is formed over the surface of the resulting semiconductor substrate 101 on the side of the active layer 102. This state is shown in FIG. 26(a).
In turn, a resist film (photoresist) 105 is formed on the barrier metal layer 104 as having apertures 105a in association with the electrode pads 103 (see FIG. 26(b)). The apertures 105a each have an interior sidewall generally perpendicular to the semiconductor substrate 101.
Thereafter, projection electrodes 106 are respectively formed in the apertures 105a of the resist film 105 by electrolytic plating. At this time, an electric current is applied to a plating liquid via the barrier metal layer 104. Thus, the barrier metal layer 104 serves as a seed layer, whereby a metal such as copper is deposited on the barrier metal layer 104 to form the projection electrodes 106 (see FIG. 26(c)).
In turn, the resist film 105 is removed. Further, the barrier metal layer 104 is removed with portions thereof between the electrode pads 103 and the projection electrodes 106 being left. Thus, the projection electrodes 106 projecting from the semiconductor substrate are provided. This state is shown in FIG. 26(d).
As required, low melting point metal layers 108 are respectively formed on the projection electrodes 106 as covering at least distal end faces of the projection electrodes 106. Where the low melting point metal layers 108 are formed by electroless plating after the removal of the resist film 105, for example, the low melting point metal layers 108 cover the entire exposed surfaces of the projection electrodes 106 as shown in FIG. 27(e). That is, the low melting point metal layers 108 cover the side faces of the projection electrodes 106 as well.
Alternatively, the formation of the projection electrodes 106 by the electrolytic plating is completed with the apertures 105a partly left unfilled, and then the low melting point metal layers 108 are formed by the electrolytic plating before the removal of the resist film 105 and the barrier metal layer 104. In this case, the low melting point metal layers 108 are provided only in the apertures 105a as shown in FIG. 28(f). Thereafter, the resist film 105 is removed, and the barrier metal layer 104 is removed with the portions thereof between the electrode pads 103 and the projection electrodes 106 being left. Thus, the projection electrodes 106 are provided as having the low melting point metal layers 108 formed only on the distal end faces thereof as shown in FIG. 28(g)
Then, the semiconductor substrate 101 is diced to provide a plurality of semiconductor chips (semiconductor devices) each having projection electrodes 106. Where the projection electrodes 106 are respectively formed with the low melting point metal layers 108, the semiconductor device can easily be bonded to electrode pads of a wiring board by melting and solidifying the low melting point metal layers 108. Such a semiconductor device production method is disclosed, for example, in the following literature: Yoshiaki Yamamoto, "Chisso's Wafer Bumping Service", Densi Zairyo (Electronic Materials and Parts), May, 1995, p.101–104.
However, the projection electrodes 106 formed by the plating are non-uniform in length (or height as measured from the barrier metal layer 104). The growth rate of the projection electrodes 106 is generally proportional to the amperage of the electric current flowing between the barrier metal layer 104 and the plating liquid. However, the amperage of the electric current flowing between the barrier metal layer 104 and the plating liquid is not uniform throughout the plane of the semiconductor substrate 101 (e.g., between the center and periphery of the semiconductor substrate 101).
If the projection electrodes 106 are non-uniform in length, the distal ends of the projection electrodes 106 are not located within the same plane. When the semiconductor chip formed with the projection electrodes 106 is bonded to the electrode pads and the like formed on the wiring board, some of the projection electrodes 106 having a smaller length cannot properly be brought into contact with the electrode pads of the wiring board. This results in a mechanical bonding failure and an electrical connection failure.
The barrier metal layer 104 serving as a base for the plating has steps due to the presence of the passivation film 107. Therefore, the distal end faces of the projection electrodes 106 each have a recessed center portion as shown in FIGS. 26(c), 26(d), 27(e), 28(f) and 28(g). In such a case, the projection electrodes 106 cannot properly be brought into contact with the electrode pads of the wiring board, resulting in a mechanical bonding failure and an electrical connection failure.
During the plating, the projection electrodes 106 grow as expanding the apertures 105a to deform the resist film 105, whereby the projection electrodes 106 each have a width progressively increased toward the distal end thereof. As a result, the projection electrodes 106 each have an inverted trapezoidal section as shown in FIG. 26(d). Where the adjacent electrode pads 103 are spaced a smaller distance (pitch), the distal ends of the projection electrodes 106 provided on the adjacent electrode pads 103 are located in close relation. Therefore, when the semiconductor device is connected to the wiring board, the adjacent projection electrodes 106 are readily brought into contact with each other thereby to be electrically short-circuited. Therefore, it is impossible to arrange the projection electrodes 106 (electrode pads 103) in closer relation, i.e., to reduce the pitch of the projection electrodes 106.
Since limited kinds of metals are usable for the film formation by the plating, there is a limited choice of materials for the projection electrodes 106.
Where the low melting point metal layers 108 are formed by the electroless plating after the removal of the resist film 105, the low melting point metal layers 108 are formed on not only the distal ends but also the side faces of the projection electrodes 106. Since the semiconductor device for the flip-chip connection is connected to the external device via the distal ends of the projection electrodes 106, portions of the low melting point metal layers 108 except those formed on the distal end faces of the projection electrodes 106 are not contributable to the connection, but may cause a short-circuit between the adjacent projection electrodes 106.
Where the low melting point metal layers 108 are formed by the electrolytic plating, the low melting point metal layers 108 are non-uniform in thickness within the plane of the semiconductor substrate 101, like the projection electrodes 106. Therefore, the distal end faces of the projection electrodes 106 including the low melting point metal layer 108 are not located within the same plane, resulting in a bonding failure.
After the projection electrodes 106 are formed by the electrolytic plating, the barrier metal layer 104 is removed by wet etching. However, it is difficult to control the etching amount at this time. Therefore, portions of the barrier metal layer 104 present between the projection electrodes 106 and the passivation film 107 and between the projection electrodes 106 and the electrode pads 103 may partly be removed (over-etched). This results in reduction of the bonding strength of the projection electrodes 106 to the electrode pads 103. Where the portions of the barrier metal layer 104 between the electrode pads 103 and the projection electrodes 106 are etched, the electrode pads 103 are partly exposed (or uncovered). This leads to corrosion of the electrode pads 103, thereby reducing the reliability of the semiconductor device.