A miniature signal booster element is inserted into the conductive path along a pair of wires leading between the slider end of a flexure member in a disk drive and the mounting end of the flexure. The signal booster element comprises an integrated circuit amplifier or a ferrite core transformer. The ferrite core transformer may comprise two separate coils: one coupled to the transducer and the other coupled to the output side of the wire pair; or a single coil with an intermediate tap connection. The signal booster element is single coil with an intermediate tap connection. The signal booster element is encapsulated within an electrically insulative sheath to provide electrical insulation and mechanical isolation of the signal booster element from the flexure member.

This invention relates to miniature transducers and signal booster elements used in small computer disk drives.
Miniature transducers are known which are used in disk drives to write data to and read data from magnetic storage disks. One such miniature transducer type is a thin film magnetic transducer, which comprises a pair of pole pieces joined at a first region, usually termed the back gap region, and spaced at an opposing region, usually termed the pole tip region. In between the back gap region and the pole tip region, the pole pieces diverge in order to accommodate an electrical coil which is electrically insulated from the pole pieces. The coil is electrically connected to associated read/write circuitry. The transducer is typically fabricated on a relatively thick substrate, usually termed a slider, with the pole tip region terminating at a surface termed the air bearing surface (ABS). A typical example of such a transducer is described and illustrated in U.S. Pat. No. 4,458,279 and the additional references cited therein, the disclosures of which are hereby incorporated by reference.
Another miniature transducer type is termed a composite magnetic transducer, which is shown in co-pending, commonly assigned U.S. patent application Ser. No. 07/772,981 filed Oct. 7, 1991, the disclosure of which is hereby incorporated by reference. Essentially, a composite magnetic transducer comprises a two piece magnetic core element fabricated from a suitable material, such as ferrite, which is formed separately and then glass-bonded to a hard ceramic slider. The ferrite core element is bonded to the same surface as the support surface on which the thin film transducer is formed, the ferrite core being bonded to an ABS rail lobe or in a position intermediate the two spaced lobes. The ferrite core element has a gap which functions in a manner similar to the pole tip region of a thin film magnetic transducer, with the gap dimensions being defined by the glass bonding material and the process employed. An improvement over the composite head is termed the MIG head, which is an abbreviation for metal-in-gap. In this type of miniature transducer, a thin film of metal (typically Fe-Al-Si) is provided in the gap on the gap confronting surface of the downstream ferrite core piece. This arrangement provides for improved performance in general. Two typical examples of MIG heads are described and illustrated in the publication entitled "Recording Characteristics of MIG Heads", Shinohara, et al., IEEE Transactions on Magnetics, Vol. 24, No. 6, November, 1988, pages 2626-2628, and the additional references cited therein, the disclosures of which are hereby incorporated by reference. In all such composite heads, the ferrite core has an aperture, and a multi-turn coil of wire is wound about the core through the aperture, the coil being electrically connected to the associated read/write circuitry.
The demand for increasing data density on magnetic media has led to the requirement for substantially smaller track widths and transducers with correspondingly smaller gap dimensions. With decreasing gap size, the amplitude of the signal output by the transducer coil is corresponding reduced. This is undesirable, since noise signals increasingly mask the data signals generated by the coils during a read operation, which leads to erroneous data retrieval. In the past, attempts have been made to compensate for this decrease in signal amplitude by adding more turns to a transducer coil. For thin film transducers this solution is less than desirable, however, since it leads to an increased thickness of the transducer: in particular, in order to accommodate more turns, the coil is fabricated in several layers. This increased thickness of the transducer is highly undesirable because of a corresponding increase in noise, resistance and power consumption. Moreover, additional process steps are required, which increase production cycle time and decrease the yield rate, thereby contributing to higher cost per unit. For composite transducers, the additional turns solution is less feasible, since the coil is composed of individual turns of a continuous wire which cannot be decreased in diameter without sacrificing tensile strength, which leads to greater difficulty in fabricating such transducers and a lower manufacturing yield.
An improvement in the signal amplitude generated by such miniature transducers has been afforded by the use of a miniature thin film transformer to boost the electrical signal output from the thin film transducer. In our U.S. Pat. No. 5,072,324, issued Dec. 10, 1991 for Thin Film Transducer/Transformer Assembly, the disclosure of which is hereby incorporated by reference, a suitable thin film transformer is described which is formed on one of the two slider lobes in the position normally occupied by one of the thin film transducers in the prior art devices. This thin film transformer includes a bottom pole member, a top pole member forming a closed magnetic path with the bottom pole member, and a coil. The top and bottom pole members are fabricated of a magnetically permeable material. The electrically conductive coil is positioned between the top and bottom pole members, the coil having a pair of ends and a tap connection between the ends. The bottom pole member of the transformer includes first and second end portions and an intermediate body portion extending therebetween. The top pole member includes first and second end portions and an intermediate body portion extending therebetween and disposed above the intermediate body portion of the bottom pole member to provide an interior space for accommodating the coil, and the first and second end portions of the bottom pole member are coupled to the first and second portions of the top member, respectively. In addition to being located on one of the two lobes, the transformer can also be positioned elsewhere on the same substrate as the thin film transducer, or can be formed as a separate unit. The transformer coil is electrically connected to the transducer coil and to the follow on electrical circuitry by means of conductive leads. Like the transducer, the thin film transformer is fabricated using integrated circuit fabrication techniques.
The above-referenced co-pending U.S. patent application Ser. No. 07/772,981 discloses a further extension of the invention disclosed and claimed in the U.S. Pat. No. 5,072,324 by substituting a discrete booster element for the monolithically formed thin film transformer, the signal booster element having a pair of input terminals and a pair of output terminals. A coupling means is provided which includes a first conductive path coupled between one of the transducer coil ends and one of the signal booster element input terminals, and a second conductive path coupled between the other one of the transducer coil ends and the other signal booster element input terminal. The output signals from the transducer/signal booster assembly are taken from the output terminal of the signal booster element. The signal booster element may comprise a thin film transformer as described in the above-referenced '324 patent or an integrated circuit amplifier. In either form, the signal booster element serves to boost the amplitude of the signal generated by the transducer coil, with the amount of amplitude boost being dependent upon the turns ratio of the two portions of the transformer or the gain of the amplifier. The transducer and the signal booster element are supported by the substrate/slider in closely adjacent fashion, either on the same surface or on different surfaces. Each of these two major elements may be formed either independently or (in the case of the thin film transducer and transformer or integrated circuit amplifier embodiments) concurrently.
While the above describe signal amplitude arrangements provide improved performance for miniature transducers in small computer disk drives, these arrangements can only be applied to existing transducer/slider designs by changing the manufacturing process, which is not always economical to do for well established designs. Consequently, the need exists for a signal booster which is directly compatible with existing transducer designs, amenable to use with future designs and which is relatively inexpensive to implement.

Thin film transducer suspension assembly with flexuro mounted booster element


The creations of objects by files that have not been previously identified as malware are tracked. The security reputations of specific created objects are determined. Based on the determined security reputations of specific created objects, the security risks concerning the specific files that created the objects are determined. Responsive to whether a determined security risk concerning a specific creating file meets a given threshold, it is determined whether the specific creating file comprises malware. Responsive to determining that a specific creating file comprises malware, the creating file is blocked from performing the activity associated with the creation of the associated object. Responsive to determining that a creating file comprises malware, the creating file can be disabled, and an alert concerning the creating file can be transmitted to a central security server.

Malware is often engineered to remain on a computer it has infected even after the computer is rebooted. To do so, the malware registers itself with the operating system, such that it is automatically loaded when the operating system restarts. In an effort to evade detection by anti-malware products, malware is often polymorphic in nature. Polymorphic malware changes the file in which it resides (known as the backing file) with every infection (or at other frequencies), so as to avoid detection by signature based scanning. As the backing file changes between infections, so too does its fingerprint (hash). Thus, scanning files for signatures of known malware can fail to identify a changed backing file. Different tools of varying effectiveness do exist for detecting polymorphic malware, but it would be desirable to further address these issues, practically in the context of polymorphic malware that registers itself with the operating system to remain on an infected computer after reboot.

Determining file risk based on security reputation of associated objects


A retractable safety syringe may have a needle, a syringe body, a shaft seal, and a plunger assembly. A proximal portion of the body and a piston of the plunger may define a vacuum chamber. The plunger assembly may comprise a shaft coupled to a piston. The shaft may have at least one non-engaging portion and at least one engaging portion. The plunger assembly is movable between a storage position and working positions. In the storage position, little or no force is exerted on the shaft seal by the non-engaging portion. In the working positions, the engaging portion is in sealing engagement with the shaft seal to seal the vacuum chamber. Stopper movement of the retractable safety syringe may be reduced or eliminated if the retractable safety syringe is prefilled.

In recent years, the public (e.g., medical personnel and healthcare providers, drug addicts, drug users, and the like) has become increasingly aware of the health hazards associated with needle reuse and accidental needle prickings. For example, at least twenty blood-borne pathogens may be transmitted by the reuse of needles or accidental needle prickings. For example, these blood borne pathogens may include and are not limited to Human Immunodeficiency Virus (HIV), Acquired Immunodeficiency Syndrome (AIDS), Hepatitis B, Hepatitis C, syphilis, malaria, tuberculosis, and herpes. Despite the awareness of the risk of needle reuse and accidental needle prickings, at least 36 percent of HIV/AIDS cases and more than 50 percent of Hepatitis B and Hepatitis C cases in the United States may be linked to the sharing of needles among drug addicts. Accordingly, there is a need to curb the practice of sharing needles among drug addicts.
The problem of needle sharing or needle reuses is further amplified when viewed in relation to the world population. For example, approximately 30 percent of reported HIV/AIDS cases in Brazil, Chile, Uruguay, Paraguay and Argentina are directly related to the sharing of contaminated needles among drug addicts. Approximately 70 percent of the HIV cases reported in China are directly linked to the sharing of contaminated needles. In eastern European countries, 80 percent of injection drug addicts admit to sharing contaminated needles. Approximately 43 percent of HIV/AIDS cases reported in Poland and Yugoslavia are linked to the sharing of contaminated needles among drug addicts.
Accidental needle prickings also pose a threat to healthcare workers. In particular, approximately one million accidental needle prickings are reported by healthcare workers in the United States annually. However, it is believed that at least three million accidental needle prickings occur each year, of which about two million are unreported. Various studies estimate that out of all the accidental needle pricking injuries that occur to nurses, approximately 40 percent to 53 percent go unreported. Various studies also estimate that out of all the needle pricking injuries that occur to laboratory technicians, approximately 92 percent go unreported. Various studies further estimate that out of all the needle pricking injuries that occur to physicians, approximately 70 percent to 95 percent go unreported.
In 1997, the Center for Disease Control and Prevention (CDC) sponsored a study that found that approximately 76 percent of needle pricking injuries could be avoided by using safety needles. Presently, there are at least 250 types of safety syringes. Unfortunately, the retractable safety syringes that currently exist have been criticized for various problems associated in operating the retractable safety syringe and its ineffectiveness.
One type of safety syringe is a vacuum assisted safety syringe wherein the needle of the syringe is retracted into a syringe body after a piston engages a needle holder due to a retraction force of a variable vacuum compartment. The retraction force of the variable vacuum compartment is a function of the surface area of the piston as it is traversed from a retracted position to an engaged position. Various types of seals may be used to create an airtight barrier around the plunger shaft. The seal or seals used to produce the variable vacuum compartment may begin to break down, become less resilient, or otherwise fail over time or due to various environmental conditions. For example, when various components of a syringe, such as the seal, are exposed to a prolonged force, the components may conform to an undesirable shape thereby reducing the effectiveness of the component and hamper the overall operation and function of the syringe. Additionally, the seals, or other components, of some safety syringes are prone to react negatively to hot climates. The exposure of these syringes to hot temperatures, cold temperatures, or temperature cycling during storage or shipment can lead to an operational failure of the syringe.
Furthermore, it is often desirable to prefill a safety syringes during an automated process prior to shipment. The process of manufacturing prefilled syringes typically includes sterilizing the syringe. The prefilled and sterilized syringe may then be shipped via at least one air shipment. If the shipment of prefilled syringes is shipped a long distance, such as to a developing country, the shipment of prefilled syringes may be carried via numerous air shipments. During the air shipment of the prefilled syringe the prefilled syringe may be exposed to numerous changes in atmospheric pressures. In some cases, shipping a prefilled syringe via air may exposed the syringe to a reduced pressure equivalent to an elevation of approximately 8,000 feet. If a gas bubble is present in the fluid chamber of the syringe, the gas bubble may increase in volume due to the decreased atmospheric pressure. As the gas bubble increases in volume, the stopper of the syringe may be proximally displaced, which may ultimately cause a sterility failure in the syringe. When the syringe returns to normal atmospheric conditions, the gas bubble returns to its starting volume and the stopper will return to its original location. Thus, a visual inspection of the stopper may not indicate stopper movement has occurred and a sterility failure may have transpired during shipment.
Accordingly, there is a need in the art for an improved safety syringe.

This patent is subject to a terminal disclaimer.

Retractable safety syringe with non-loaded seal


Apparatuses and methods for non-invasively detecting and classifying transcranial electrical signals are disclosed herein. In an embodiment, system for detecting and interpreting transcranial electrical signals includes: a headset including a plurality of electrodes arranged for detection of the user's transcranial electrical signals; a display configured to display information to the user while the user wears the headset; and a control unit programmed to: (i) receive data relating to the transcranial electrical signals detected by the electrodes of the headset; (ii) create a data matrix with the received data; (iii) convert the data matrix into one or more user values; (iv) define a user output state based on the one or more user values; and (iv) cause alteration of an aspect of the display based on the user output state.

Electroencephalography (EEG) is typically used in research involving neural engineering, neuroscience, and biomedical engineering. With EEG sensors, cognitive states can be detected and broken down into data which can be useful for a variety of purposes.
Although emotional states are often outward and evident, demonstrated by crying, laughing, blushing, and a variety of other facial expressions and body language, emotional states may not always be obvious by appearance and actions in certain persons even though psychological changes are taking place. Many people also exhibit emotional states in different manners, or attempt to hide their emotional states from those around them, making it difficult to interpret emotional states based on appearance alone. Further, there are often minor differences between different emotional states which may not cause different physical reactions in a person.
Thought patterns other than emotional states, such as desires to make intentional kinetic motions, also result in brain wave activity detectable with EEG sensors while not outwardly evident.

System and apparatus for non-invasive measurement of transcranial electrical signals, and method of calibrating and/or using same for various applications


An auto-flushing drainage filter system including a drum filter fastened to the lowest bottom of a fishpond, cylindrical brushes fastened inside the drum filter to remove debris and impurities from the water passing through, a first water pump to pump water from the fishpond through a clean water recycling pipe via the drum filter for circulation and filtration, a second water pump to pump a sudden rush of water from the fishpond into a drain pipe through the drum filter for carrying debris and impurities away from the drum filter.

The present invention relates to a drainage filter system for a fishpond and more particularly to an auto-flushing drainage filter system fastened to a fishpond at the bottom to automatically circulate the water through a drum filter and also to automatically flush the drum filter at a predetermined frequency.
In farming fishes in fishponds, the fishponds must be regularly cleaned so that the optimum natural conditions for fishes can be maintained. However, it is neither easy nor economic to completely change the water of a fishpond. In order to keep a fishpond clean at less cost, a drain filter is commonly used. If a drain filter is used, the filter materials (such as charcoals, pebbles, sands, palm coirs, etc.,) of the drain filter should be replaced regularly. Forgetting to replace the filter materials will deteriorate the performance of the drain filter and shorten its service life.


One embodiment of the present invention provides a system that implements a content-addressable memory (CAM) which has multiple banks. During operation, the system receives a request to insert an item into the CAM, wherein the request includes a key which is used to index the item and a body containing data. Next, for each bank in the CAM, the system calculates a different hash function based on the key to produce an index and a tag. The system then uses the calculated index and the tag for each bank to lookup an entry in each bank. If the lookups do not generate a hit in any bank, the system stores an entry for the request into a highest priority bank which does not contain a valid entry in the location accessed by the lookup. In one embodiment of the present invention, the multiple banks in the CAM have varying sizes.

1. Field of the Invention
The present invention relates to the design of content-addressable memories (CAMs) within computer systems. More specifically, the present invention relates to the design of a CAM with multiple banks that achieves a high average capacity by implementing a priority ordering for insertions into the multiple banks.
2. Related Art
Content-Addressable Memories (CAMs) are used for many purposes in computer systems. For example, CAMs are routinely used to implement commonly-occurring structures in computer systems, such as cache memories, store queues and translation-lookaside buffers (TLBs). However, as computer system performance continues to increase, such CAM structures need to become larger to deal with the performance-limiting effects of growing memory latencies.
However, as CAMs become larger, it is no longer practical to use a "fully-associative" CAM design which has a separate comparator for each memory element. Instead, it is more efficient to use a "set-associative" design, which uses "index bits" in the address to partition the memory elements into subsets, and which provides a small fully-associative memory for each subset. Unfortunately, in cases where the CAM must store everything the system attempts to store (such as in a store queue), if any one of these small fully-associative memories exceeds its capacity, the system has to stall. This "capacity problem" can be somewhat alleviated by using a skewed-associative cache design, which uses a different hash function from each memory bank in the CAM (see A. Seznec, "A Case for Two-Way Skewed-Associative Caches, Proceedings of the 20th International Symposium on Computer Architecture, San Diego, Calif., May 1993.) However, in spite of the advantages of the skewed-associative design, the capacity problem still remains.
Hence, what is needed is a practical CAM design that efficiently handles the capacity problem.

Content-addressable memory that supports a priority ordering between banks of differing sizes


A fuel system for fuel injectors of an internal combustion engine is provided with a hydromechanical timing valve having a valve body assembly with a barrel and plunger arrangement. The plunger is displaceable within the barrel under the counterbalancing forces of rail fuel pressure (load) and one or more timing valve springs. The relative position of the barrel and plunger determines the effective size of the port through which timing fluid can flow. In accordance a first embodiment, the plunger has a tapered head which covers and uncovers ports in the barrel to a greater or lesser extent, thereby creating a variable flow-through cross section. Alternatively, in accordance with other embodiments, the barrel has ports with slot-like orifices of progressively changing widths which coact with a metering groove on the spool to define a variable flow cross section through which the timing fluid must pass. Optionally, for highway motor vehicle applications, to increase fuel economy, a delayed timing advance feature can be incorporated into the timing valve. More specifically, by a controlled leakage effect, the valve plunger can be caused to shift in a direction causing timing to be advanced (timing fluid supply increased) only after a predetermined period of time has elapsed. This delayed timing advance can be produced, in accordance with the invention, via a second, internal plunger, or via a second, diaphragm-operated external plunger.

1. Field of the Invention
The present invention relates generally to controls for fuel injection systems for internal combustion engines. More specifically, the invention relates to a control for regulating injection timing in fuel injectors for compression ignition type internal combustion engines, wherein fuel is supplied to unit fuel injectors which operate on a pressure-time metering principle.
2. Background Art
Unit fuel injectors which operate on a pressure-time metering principle have been in use for some time now (see U.S. Pat. Nos. 4,721,247; 4,986,472 and the patents mentioned therein), and have contributed greatly to the ability of internal combustion engine designers to meet the ever increasing demands for improved pollution control and increased fuel economy. In fuel supply systems using such injectors, fuel is supplied by a gear pump to all of the injectors via a common fuel rail and the same is true for timing fluid used to control the degree that the timing of the injection event is advanced or retarded, with the quantity of fuel and timing fluid delivered to each injector being a function of the supply pressure from the common rail and the time period during which the metering and timing chambers are in communication with the respective supply rails. Examples of gear pump type fuel supply systems for P-T type unit fuel injectors can be found in U.S. Pat. Nos. 4,909,219 and 5,042,445.
However, for the continuing demands for improved pollution control and increased fuel economy to be met, it becomes increasingly essential to be able to optimize the combustion process, not only by precisely controlling the quantity of fuel injected into each cylinder, but also by precisely regulating the timing thereof, and this has become increasingly more difficult as the level of combustion efficiency to be obtained is raised. Ultimately, increased precision means that the controller must be infinitely variable as well as responsive to the various parameters affecting fuel quantity and timing. Furthermore, since the governmental demands for emissions are less stringent for engine operation under steady-state (cruise) conditions than they are for transient (city/acceleration) conditions, increased fuel economy is obtainable if the controller can distinguish between transient and steady state operating conditions, and modify the engine timing accordingly. Ideally, such a controller would not require significant redesign of existing systems, so that it could be retrofit installed on them, not merely incorporated into new units.
U.S. Pat. No. 4,869,219 discloses an air fuel control for P-T fuel systems which uses a diaphragm-type operator to provide a controlled, optimum amount of fuel as a function of intake manifold pressure, and which can be retrofit installed on previously existing engines. However, no equivalent control for regulating engine timing is provided, nor is any delay function provided for enabling a modified effect to be produced once steady-state operation has been achieved.
U.S. Pat. Nos. 3,486,492 and 4,408,591 show fuel injection pumps which have a built-in timing control which can delay advancing of injection timing upon acceleration. However, these disclosures relate to distributor-type pumps not gear pumps, and are not adapted to the needs of P-T fuel injectors and the fuel systems therefor.

Infinitely variable hydromechanical timing control


A nitride semiconductor power device includes an AlGaN multilayer, which has changeable Al composition along a depositing direction, and SixNy layer, so as to minimize an increase in a leakage current and a decrease in a breakdown voltage, which are caused while fabricating a heterojunction type HFET device. A semiconductor device includes a buffer layer, an AlGaN multilayer formed on the buffer layer, a GaN channel layer formed on the AlGaN multilayer, and an AlGaN barrier layer formed on the AlGaN multilayer, wherein aluminum (Al) composition of the AlGaN multilayer changes along a direction that the AlGaN multilayer is deposited.

1. Field of the Disclosure
This specification relates to a nitride semiconductor device and a fabricating method thereof.
2. Background of the Disclosure
An importance of power semiconductor is rising in response to an emphasis of green energy. Power semiconductors which are employed in inverters of electric vehicles, air conditioners, refrigerators and the like are fabricated using silicon. However, a new type of nitride semiconductor attracts attentions in view of a high threshold electric field, low on-resistance, and high temperature and high frequency operation characteristic, as compared with silicon. Thus, there are precedent researches for the new type of nitride semiconductor as a material of a next-generation power semiconductor device.
In recent time, mainstream high power devices include MOSFET and IGBT, and also devices such as GaN-based HEMT, HFET, MOSFET and the like are under studies.
The HEMT which uses high electron mobility is employed for communication devices exhibiting high frequency performance.
Also, the HEMT is used in power semiconductors, communication devices showing high frequency performance, and the like. In recent time, developments of hybrid/fuel cell cars are ongoing, and various overseas corporations are releasing hybrid vehicles. Reliable operations at high temperature are required for semiconductor switches, which are disposed within voltage booster converter and inverter for connecting a motor to a generator within a hybrid vehicle, due to heat generated from an engine. Gallium nitride (GaN) may allow for the reliable operations at the high temperature owing to its wide bandgap, so as to be proper as the next generation semiconductor switch within hybrid cars.
Among others, Furukawa Electrics in Japan has issued an AlGaN/GaN high-electron-mobility transistor (HEMT) discrete, which has a high breakdown voltage of 750V and a low on-resistance of 6.3 mΩ-cm2. The company has thusly proved that the HEMT has superior characteristics to the conventional Si MOSFET, Si superjunction MOSFET and SiC MOSFET. Also, the issued GaN discrete has shown a stable switching operation at a high temperature of 225° C.
FIG. 1 is an exemplary view showing a general structure of Heterojunction Field Effect Transistor (HFET).
As shown in FIG. 1, a general HFET 10 may switch a 2 DEG current, which flows from a drain electrode to a source electrode, through a schottky gate electrode.
The general HFET 10 may include a substrate (not illustrated), a first GaN layer 11 formed on the substrate, an AlGaN layer 12 on the first GaN layer 11, a second GaN layer 13 on the AlGaN layer 12, and a gate electrode 14, a source electrode 15 and a drain electrode 16 all formed on the second GaN layer 13.
However, when the high-power semiconductor device is implemented on a small chip, a problem relating to a leakage current level is getting more important to handle.
That is, upon fabricating the AlGaN/GaN HEMT, a leakage current increases due to defective GaN, which accordingly makes it difficult to produce a high-power nitride semiconductor device.
To improve a leakage current characteristic, a growth condition of a GaN buffer layer is used. The use of the growth condition of the GaN buffer layer brings about a reduction of the leakage current, but the reduction of the leakage current may cause a direct affection on strain and quality of an epitaxial (Epi) layer.

Nitride semiconductor device and fabricating method thereof


Strips of coherent, exposed and developed film frames are advanced past, and discrete frames are placed onto, a window at a monitoring station where successive increments of the film frames are monitored by a device having photocells forming at least one row which extends transversely of the path of advancement of strips. The monitoring device is at a standstill during advancement of strips but is transported past a discrete frame at the monitoring station. Such monitoring device can ascertain the density of film frames, and its photocells generate signals which are used to image the frames onto photographic paper.

The invention relates to improvements in methods of and in apparatus for ascertaining the characteristics of sections of photographic material, and more particularly to improvements in methods of and in apparatus for ascertaining the characteristics of shorter and longer sections of exposed and developed photographic films. Still more particularly, the invention relates to improvements in methods and apparatus which can be resorted to with advantage to ascertain the density of shorter and longer sections of photographic material, for example, (a) the density of successive frames forming part of strips or webs of coherent frames or (b) the density of discrete frames.
Commonly owned U.S. Pat. No. 4,627,719 (granted Dec. 9, 1986 to Nitsch et al. for "Method of and apparatus for reproducing the images of film frames") discloses a method of and an apparatus for ascertaining the density of running webs of exposed and developed photographic films. The films are advanced in a first direction along a predetermined path through a monitoring station to be scanned by a system of photocells which generate signals for storage in the memory of a microprocessor. Such signals are utilized to properly image the frames of the respective films onto photographic paper while the films are moved along the same path but in a second direction counter to the first direction. A pivotable mirror is provided at the monitoring station to intercept light passing through successive increments of a film which is being advanced in the first direction, and the intercepted light is directed toward the photocells so that the photocells can transmit appropriate signals to the microprocessor. The mirror is pivoted out of the way preparatory to copying so that light which passes through the frames during advancement of the film in the second direction and is modified in accordance with the respective signals can impinge upon successive increments of a running strip of photographic paper.
The method and apparatus of Nitsch et al. are quite satisfactory in connection with the monitoring and copying of relatively long sections of photographic material, i.e., one or more elongated customer films each of which comprises a long series or file of exposed and developed film frames with customary frame lines between neighboring film frames. However, the patented method and aparatus are less suited for monitoring and copying of relatively short sections of photographic material, e.g., of discrete film frames. The length of sections which can be monitored and copied in the patented apparatus is determined by the distance between the film advancing devices upstream and downstream of the monitoring station (which constitutes the copying station during advancement of a film in the second direction). The aforementioned distance exceeds the length of a single film frame; therefore, if a single film frame is to be monitored and copied, it must be provided with an extension in the form of a strip or tongue extending from and serving to permit introduction of the film frame into the patented apparatus. The necessity to provide the individual or discrete film frames with extensions contributes significantly to the cost of the copying operation, not only because the extensions must be separately produced and affixed to discrete film frames but also because the periods of time which are required for the monitoring and copying of a discrete film frame are too long.

Method of and apparatus for ascertaining the characteristics of shorter and longer sections of photographic material


A cosmetic composition is provided which includes from 0.01 to 10% of single-crystal platy barium sulfate, from 0.5 to 10% of a water insoluble powdered acrylic polymer in porous particle form and a carrier. The compositions have soft focus optics imparting radiance to the applied skin area without excessive shininess or opacity and have excellent skinfeel properties.

1. Field of the Invention
The invention relates to compositions for improving the appearance of skin, particularly to provide good coverage over imperfections such as pores and uneven skin tone, while retaining a natural skin appearance.
2. The Related Art
A matte effect is often sought from facially applied cosmetics. The matte finish overcomes the shiny effect engendered by greasy skin, particularly under hot and humid conditions. Absorbent fillers such as talc, silica, kaolin and other inorganic particulates have been used to achieve the effect by their optical properties.
Imperfect skin can be hidden in two ways through manipulation of light transmission. In the first, components of the cosmetic may simply reflect light back toward the source. An alternative approach is referred to as achieving a soft focus effect. Here the incoming light is distorted by scattering (lensing). Components of the color cosmetic in this mechanism operate as lenses to bend and twist light into a variety of directions.
While it is desirable to hide imperfect skin through a matte effect, there is also a desire to achieve a healthy skin radiance. A cosmetic covering that is too opaque hides the skin under a paint-like coating. Imperfections are hidden but there is no radiance. Some refer to this as whitening. Where light transmission is insufficiently hindered, the opposite occurs. Here the glow may be healthy but aesthetically displeasing skin topography and color may now be apparent.
U.S. Pat. No. 5,997,890 (Sine et al.), U.S. Pat. No. 5,972,359 (Sine et al.), and U.S. Pat. No. 6,174,533 B1 (SaNogueira, Jr.) are all directed to topical compositions to provide good coverage of skin imperfections. The solution proposed by these documents is the use of a metal oxide with a refractive index of at least about 2 and a neat primary particle size of from about 100 to about 300 nm. Preferred particulates are titanium dioxide, zirconium oxide and zinc oxide.
A significant disadvantage of titanium dioxide and zinc oxide is the whitening effect upon the skin. An undesirable ashen appearance is unfortunately created.
U.S. Patent Application 2005/0287092 A1 (Liechty et al.) reports make-up and skincare compositions in powder form which allow the natural grain of the skin to show through. These powders are based upon barium sulfate particles coated with an N-acylamino acid such as lauroyllysine. Also present is at least one elastomeric organopolysiloxane powder or a polymethylmethacrylate powder.
U.S. Patent Application 2005/0079190 A1 (Polonka) discloses the use of solid single-crystal flat platy particles which in cosmetic skin care compositions provide consumer-desired properties of the appearance of natural skin radiance. Suitable platy particles include bismuth oxychloride, aluminum oxide, zirconium oxide and boron nitride.
U.S. Pat. No. 6,495,123 (Faryniarz et al.) and U.S. Pat. No. 6,432,389 B1 (Hansenne et al.) describe cosmetic compositions with improved skinfeel properties delivered through polymeric porous particles such as methyl methacrylate crosspolymers.
A challenge which has not been fully met by the known art is delivery of a composition with appropriate optics to achieve both soft focus and radiance properties in a system that still provides excellent skinfeel. Still further there is a need which has not previously been fully met for a soft focus system that reduces "red wavelength" to hide fine lines and wrinkles.

Single-crystal platy barium sulfate in cosmetic compositions


A lightguide for illuminating keypads within electronic devices, such as radiotelephones, supports additional components and is maintained in spaced apart relationship with a circuit board hosting electronic components. The number of separate components required within a radiotelephone is decreased and the amount of circuit board real estate available for electrical components is increased.

Radiotelephones, such as cellular telephones, have become increasingly popular for both personal and commercial use. Radiotelephones have also become smaller to facilitate storage and portability. Consequently, space or "real estate" on circuit boards hosting electronic components within radiotelephones has become somewhat limited.
A lightguide within a radiotelephone may be utilized to illuminate a keypad of translucent keys via a light source internal to the radiotelephone. A lightguide may also be utilized to support a keypad and a liquid crystal display (LCD) for the radiotelephone. The lightguide may be placed directly on a circuit board hosting electronic components for generating and receiving telecommunications signals. As a result, a lightguide can occupy a significant amount of circuit board real estate. As a result, circuit board space beneath a lightguide may be generally unusable for hosting electronic components thereon. Furthermore, circuit board space beneath a lightguide may be unusable for vias because contact pads associated with the keypad of the radiotelephone are located on the circuit board.
The speaker and microphone of a radiotelephone are typically mounted within the front cover of the radiotelephone housing and are hard-wired to the circuit board. Reflective tape is typically placed on the back of a lightguide to reflect light from a light source into the LCD and keypad. Shielding of electromagnetic interference (EMI) generated within the radiotelephone is often achieved using a shield can soldered to the circuit board. In addition, the inside surface of the housing top cover may be coated with a conductive material to provide EMI shielding.
The number of components mounted to a radiotelephone top cover as well as the addition of conductive material for EMI shielding can complicate and increase the costs associated with radiotelephone assembly. Furthermore, mounting radiotelephone components to housing covers does not facilitate interchangeability of housing covers between various radiotelephone models.

Keypad lightguides including compartments


A method for producing a cadmium negative electrode for alkaline batteries according to the present invention comprises a step of obtaining a cadmium active-substance impregnated electrode plate by impregnating said electrode substrate with a cadmium active substance; and a step of adding polyethylene glycol for forming a polyethylene glycol coating on the surface of said cadmium negative electrode or on the surface of said active substance by coating or impregnating said active-substance impregnated electrode with polyethylene glycol.

The present invention relates to a cadmium negative electrode for use in alkaline batteries such as a nickel-cadmium battery, and to a method for producing the same.
Cadmium negative electrodes for use in nickel-cadmium batteries known heretofore are classified into sintered negative electrodes and non-sintered negative electrodes. A sintered negative electrode is produced by filling a nickel-sintered substrate with a negative electrode active substance made of cadmium oxide or cadmium hydroxide. On the other hand, a non-sintered negative electrode is produced by first preparing a paste by kneading a negative electrode active substance comprising cadmium oxide or cadmium hydroxide with synthetic fibers, glue material, etc., and then coating the resulting paste to an electrically conductive core body (substrate) such as a punching metal and the like.
In case an alkaline storage battery using a cadmium negative electrode of the type above is charged and discharged, the product obtained at the cadmium negative electrode on charging changes into metallic cadmium, and that on discharging changes into cadmium hydroxide. In an alkali electrolyte of high concentration, which is generally used in an ordinary alkaline storage battery, the products obtained on discharging are crystal precipitates of hexagonal β-cadmium hydroxide (β-Cd(OH)2) that are stable in an alkaline electrolyte of high concentration. The β-cadmium hydroxide (β-Cd(OH)2) crystals possess thin platy hexagonal crystal structure, and even with a small amount, they may cause clogging at the apertures of fine pores of the cadmium negative electrode, or cover the surface of the active metallic cadmium.
If a case as such stated above occurs even in case non-discharged metallic cadmium (Cd) still remains inside the cadmium negative electrode, the non-discharged metallic cadmium finds difficulty in achieving ion conductivity with the electrolyte, and this makes discharging impossible. Furthermore, if the platy crystals of β-cadmium hydroxide (β-Cd(OH)2) as above grow into coarse grains, the surface of the particles decreases as to lower the rate of charge-discharge reaction. Then, difficulties occur on charging the coarse particles in the product on discharging, i.e., β-cadmium hydroxide (β-Cd(OH)2))
The coarse particles of β-cadmium hydroxide (β-Cd(OH)2) remaining without being charged further grow into coarser grains during discharging, and make the discharge of metallic cadmium (Cd) remaining inside the cadmium negative electrode still more difficult by clogging the numerous pores in the cadmium negative electrode or by covering the surface of the active metallic cadmium (Cd). In this manner, metallic cadmium (Cd) remaining non-discharged or cadmium hydroxide (Cd(OH)2) remaining non-charged tended to increase in amount with progressive charge-discharge reaction, and this gradually lowered the usability factor of the active substance to result in a problematic decrease in discharge capacity.
In the light of the aforementioned circumstances, there has been proposed, in JP-A-Sho61-158664 (the term "JP-A" as referred herein signifies "an unexamined published Japanese patent application") or in JP-A-Sho61-158666, to form a coating of poly(vinyl alcohol) (PVA) or methyl cellulose (MC), which prevents the diffusion of hydoroxide ions, on the surface of the cadmium negative electrode or on the surface of the negative electrode active substance. In the cadmium negative electrode proposed in the published patent applications above, a coating of poly(vinyl alcohol) (PVA) or methyl cellulose (MC) formed on the surface of the cadmium negative electrode or on the negative electrode active substance functions as to hinder the diffusion of the hydroxide ions.
Since the concentration of the hydroxide ions decreases in the vicinity of the active substance during discharging, there grows γ-cadmium hydroxide (γ-Cd(OH)2), which is stable in an aqueous alkaline solution of high concentration. Since γ-cadmium hydroxide (γ-Cd(OH)2) generates in the form of monoclinic acicular single crystals, the surface of the metallic cadmium (Cd) is less covered by γ-cadmium hydroxide (γ-Cd(OH)2). Accordingly, not only the drop in usability factor of the active substance, but also the decrease in discharge capacity can be prevented from occurring as to suppress the degradation in charge-discharge cycle characteristics.
However, since poly(vinyl alcohol) (PVA) is sparingly soluble in water at room temperature, it must be dissolved in hot water in case of forming the coating on the surface of the cadmium negative electrode, and the resulting solution of poly(vinyl alcohol) (PVA) must then be applied or impregnated to the surface of the cadmium negative electrode. This caused a problem of making the production of cadmium negative electrode complicated. Furthermore, there was found another problem that a coating of poly(vinyl alcohol) (PVA) cannot sufficiently suppress the degradation of charge-discharge characteristics.
Further, in JP-A-Sho63-195963 is proposed a method of adding a polysaccharide, such as methyl cellulose (MC), or a derivative thereof into the cadmium negative electrode, and, although a polysaccharide such as methylcellulose (MC) certainly dissolves into an alkaline solution, it was unable to sufficiently exhibit the effect of suppressing the degradation. Hence, there occurred a problem that it insufficiently suppress the degradation of the charge-discharge characteristics. There was also proposed a method of adding poly (vinyl pyrrolidone) (PVP), which easily dissolves into water at room temperature, into the cadmium negative electrode. However, since poly(vinyl pyrrolidone) (PVP) swells in an alkaline solution, it could not sufficiently exhibit the effect of suppressing the degradation, and this also led to a problem of exhibiting insufficient effect on suppressing the degradation of the charge-discharge characteristics.

Cadmium negative electrode for alkaline storage battery and method for producing the same


A seed tank assembly for an agricultural implement including an exhaust opening configured to exhaust seeds from the seed tank assembly, in which at least one webbing extends across the exhaust opening forming a plurality of apertures, the at least one webbing is integrally molded into the seed tank assembly, and the at least one webbing is configured to provide structural support to the seed tank assembly and to reduce seed head pressure into an inductor box positioned beneath the exhaust opening.

The invention relates generally to ground working equipment, such as agricultural equipment, and more specifically, to exhaust webbing for an agricultural implement tank.
Generally, planting implements (e.g., planters) are towed behind a tractor or other work vehicle via a mounting bracket secured to a rigid frame of the implement. These planting implements typically include multiple row units distributed across the width of the implement. Each row unit is configured to deposit seeds at a desired depth beneath the soil surface, thereby establishing rows of planted seeds. For example, each row unit may include a ground engaging tool or opener (e.g., an opener disc) that forms a seeding path for seed deposition into the soil. In certain configurations, a gauge wheel is positioned a vertical distance above the opener to establish a desired trench depth for seed deposition into the soil. As the implement travels across a field, the opener excavates a trench into the soil, and seeds are deposited into the trench. In certain row units, the opener is followed by a packer wheel that packs the soil on top of the deposited seeds.
Certain planting implements include a central seed tank, and a pneumatic distribution system configured to convey seeds from the tank to each row unit. For example, the pneumatic distribution system may include an inductor box positioned beneath the seed tank. The inductor box is configured to receive seeds from the tank, to fluidize the seeds into an air/seed mixture, and to distribute the air/seed mixture to the row units via a network of pneumatic hoses/conduits. Each row unit, in turn, receives the seeds from the pneumatic hoses/conduits, and directs the seeds to a metering system. The metering system is configured to provide a flow of seeds to a seed tube for deposition into the soil. By operating the metering system at a particular speed, a desired seed spacing may be established as the implement traverses a field.
The central seed tank may exhaust the seeds from the seed tank to the inductor box through an exhaust opening. As the seeds are exhausted, the weight of the seeds may apply an undesirably large pressure on the inductor box, thereby reducing the efficiency of the air/seed fluidization process. In addition, a large exhaust opening may reduce the structural rigidity of the tank, thereby increasing the difficulty of implement manufacturing process.

Exhaust webbing for an agricultural implement tank


A lead frame includes a base, a substantially rectangular device hole formed in the base, an island formed in the device hole and offset a predetermined distance from the base, a plurality of inner leads arranged at predetermined intervals to extend toward a pair of opposing edges of the island, and suspension pins formed to extend toward a pair of edges of the island not opposing the end portions of the inner leads. The island is used to mount a semiconductor chip, and the suspension pins connect the island and the base. A pair of dummy leads extended from the base toward the island is formed on the both sides of at least one suspension pin. The distance from the side edge of the suspension pin to the side edge of the dummy lead is equal to or smaller than the distance from the end portions of the inner leads to the side edge of the island. This prevents the island of the upper lead frame from being clamped between the lower surfaces of the inner leads and the chip mounting surface of the island of the lower lead frame.

1. Field of the Invention
The present invention relates to a lead frame and a semiconductor device in which a semiconductor chip is mounted on the lead frame and, more particularly, to techniques suitably applicable to a semiconductor device lead frame used to mount a resin-encapsulated semiconductor device and a semiconductor device using the lead frame.
2. Description of the Related Art
Generally, a semiconductor device in which a semiconductor chip is die-bonded to an island of a lead frame uses a lead frame processed so that the upper surface of the island is lower by a predetermined thickness than the upper surfaces of the inner leads. The lead frame is thus processed principally to prevent a bonding wire connecting the upper surface of an electrode formed on a semiconductor chip and the upper surface of an inner lead of the lead frame from contacting the edge of the semiconductor chip. It is preferable to decrease any level difference in the direction of thickness of the semiconductor chip between the electrode upper surface and the inner lead upper surface.
For example, FIG. 7A is a plan view showing a lead frame used in a so-called SOP (Small Outline L-Leaded Package) semiconductor device in which outer leads extend in two directions from the package main body. FIG. 7B is a sectional view taken along a line VI-VI' of FIG. 7A. Note that a plurality of such lead frames are continuously formed in a single frame so that a plurality of semiconductor chips can be mounted. FIG. 7A shows one of these lead frames corresponding to one semiconductor chip.
As shown in FIG. 7A, a nearly rectangular device hole 21 is formed in a central portion of the lead frame. In this device hole 21, a flat, essentially rectangular island 22, inner leads 23, outer leads 24, tiebars 25, and a pair of suspension pins 27 are formed. The inner leads 23 are aligned at predetermined pitches to extend toward a pair of opposing edges of the island 22. The outer leads 24 are connected in a one-to-one correspondence with the inner leads 23. Each tiebar 25 is formed to cross the boundary between the inner leads 23 and the outer leads 24. The suspension pins 27 connect those two edges of the island 22, which do not oppose the end portions of the inner leads 23, and a base 26. The lead frame usually has a thickness T1 of about 0.2 mm.
A bent portion 29 is formed in a predetermined portion of each suspension pin 27. Consequently, as shown in FIG. 7B, the island 22 is offset a distance Td from the base 26. This offset Td is usually set to an amount corresponding to the thickness of the semiconductor chip used. The offset Td is generally around 0.3 to 0.5 mm although it also depends upon the type of product.
FIG. 8 is a flow chart showing a process of mounting a semiconductor chip on the island 22 of the lead frame. First, several tens of lead frames to about a hundred lead frames are stacked to improve the working efficiency (step S21). The stacked lead frames are supplied to an automatic semiconductor chip mounter (step S22). In the mounter, a suction pad is lowered toward the lead frames, and the upper surface of the base 26 of the topmost lead frame is chucked by the suction pad (step S23). The suction pad is raised to separate the topmost lead frame (step S24). The upper surface of the island 22 of the separated lead frame is coated with an adhesive such as silver paste (step S25). A semiconductor chip is placed on the surface of the island 22 coated with the silver paste, and the island 22 and the chip are adhered (step S26). Through these steps the semiconductor chip is mounted on the island 22 of the lead frame.
Between steps S21 and S24 of the above process, vibrations sometimes act on the stacked lead frames which then become displaced from each other. If this is the case, in a direction parallel to the direction in which the suspension pins extend, the bent portion of the suspension pin functions as a stopper to prevent displacement in this direction. However, nothing functions as a stopper in a direction perpendicular to the extending direction of the suspension pins, i.e., in a direction parallel to the direction in which the inner leads extend. Consequently, as shown in a sectional view of FIG. 9, the island 22 of the upper one of two stacked lead frames sometimes enters between an inner lead 33 and an island 32 of the lower lead frame. If the upper lead frame is pulled up by the suction pad in this state in step S24, the inner leads 33 of the lower lead frame may deform, or the lead frame may drop from the suction pad during the pulling makeing it impossible to separate the lead frames from each other.

Lead frame and a semiconductor device having the same


The present invention provides driver circuitry for commutated inductive loads, and in particular, inductive loads employed in multi-pole DC brushless motors. The preferred embodiment of the present invention typically implements three pull-up and three pull-down drivers for motor control. The pull-down driver circuit described in the present invention can be configured to be adjusted by an external component of the integrated circuit implementation in order for controlling turn-off transients. Voltage transients due to changes in load current in the control loop of the pull-down driver circuit can be minimized or deterministically controlled by controlling the rate of change of the input voltage. For the case of when the load current is to be completely switched from one inductor to another inductor, an additional unity gain buffer coupled to the input voltage is inserted into the control loop of the pull-down driver circuit for reducing the voltage transients that can result. The output voltage rise and fall times of the pull-up driver circuit of the present invention can be controlled by means of an accurate clock rate, a capacitance ratio value, an arbitrary voltage supply or by any combination of the above means. The present invention also provides circuitry for controlling the pull-up driver circuit and the pull-down driver circuits as required to assert the floating operation and as well dynamic breaking operation. The present invention is able to assert these operations by operating from either the power supply or from an energy storage capacitor that is charged to a value closely approximating the power supply voltage should the power supply be removed.

1. Field of the Invention
This invention is directed to the field of providing commutation control of inductive loads, and in particular, circuitry for use in controlling multi-pole DC brushless motors.
2. Background Art
There are many applications which require the control of current in inductive loads where the current must be switched (commutated) from one value to another value or from one inductive load to another load. When the current through an inductor is reduced rapidly, a reverse voltage is generated that is proportional to the rate of the current change (di/dt). If the current passing through an inductive load is abruptly interrupted, the voltage generated by the inductor can be of sufficient magnitude to damage other components. Even if the transient is not destructive to other components, it may generate undesirable electromagnetic interference (EMI) which can interfere with the operation of adjacent electronic circuits.
It is therefore desirable to control these transients in such situations. Prior art has employed special networks attached to the inductive load to suppress or reduce the transients. In the past, such devices as flyback diodes or varistors have been used to suppress transients and capacitor or resistor-capacitor networks have been employed to reduce transients.

Driver circuitry for commutated inductive loads


A multi-component attachment system, including a first clamp that attaches to a bed-rail, and a second component which connects to a lighting system or other accessory, allows a sterile drape to go over the bed-rail attachment, while allowing a lamp or other accessory to magnetically attach through the drape, thereby preventing interruption of the sterile field.

It is often difficult for surgeons and other medical practitioners to adequately visualize procedures without appropriate lighting. It has been found that flexible or "gooseneck" lights are advantageous for this purpose, as they may be flexed or snaked to guide illumination directly to an area of interest. The problem, however, is that once a sterile field is created, these lamps must be clamped to the bed-rail, or the like, thereby interrupting the sterile fields and creating a potential source of germs and pathogens.

Magnetic bed-rail attachment particularly suited to sterile environments


A programmable logic device (PLD) implementing an SDRAM controller is provided. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. The configurable logic of the PLD also forms a state machine to operate the controller and the interface. In accordance with the present invention, dedicated circuits of the PLD optimize performance of the SDRAM controller. These dedicated circuits include two delay locked loops (DLLs) which eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock.

1. Field of the Invention
The present invention relates to synchronous dynamic random access memory (SDRAM), and particularly to an SDRAM controller implemented in a programmable logic device (PLD).
2. Description of the Related Art
The clock rates of the first microprocessors were limited to a range between 1 and 10 Mhz. Typically, even the simplest of instructions, required several clocks to execute. Assuming a main memory cycle time of 250 nanoseconds, approximately 4 million accesses to main memory were needed every second to maintain the first processors at their maximum speed. Asynchronous dynamic random access memory (DRAM) chips, having an access time of 80-100 nanoseconds, met these requirements.
Next generation microprocessors advanced to internal clock speeds in excess of 100 Mhz. However, the DRAM of the time, which had advanced to 60 nanosecond access time, thereby still requiring 10-12 clock cycles to fill a cache line, could not keep pace with those microprocessors. To solve this problem, Fast Page Mode (FPM) DRAMs and EDO (Extended Data Out) DRAMs were developed which provided some performance improvement.
Eventually, improvements in semiconductor processing technology enabled microprocessors to operate beyond 133 Mhz. However, development of a memory device to take full advantage of this speed proved more difficult. Virtually all then available DRAM devices used asynchronous clocking systems, i.e. the clocking signals necessary to perform memory access functions were not synchronized to the associated microprocessor. Specifically, although memories were accessed by signals sent by the microprocessor, the exact time interval between the time a request was sent to a memory and the time a response was received was dependent on the particular internal features of the memory. Thus, system designers had to allow for the xe2x80x9cworst casexe2x80x9d response time between requests for information and the anticipated time the information would be available. This xe2x80x9cworst casexe2x80x9d response time necessarily wasted time in handling many memory functions.
After extensive research, a type of memory called synchronous DRAM (SDRAM) was developed to operate with these megafast microprocessors. SDRAM is a generic name for various kinds of DRAM that are synchronized with the optimal clock speed of the microprocessor. In this manner, an SDRAM can increase the number of instructions that the microprocessor can perform in a given time.
Typically, SDRAMs are fabricated as separate integrated circuits from other system components. The SDRAMs, microprocessor, and other components of the system are interconnected via a system bus. An SDRAM controller, which is placed between the system bus and the SDRAM, facilitates communication between the microprocessor and the SDRAM, as well as provides a xe2x80x9cwindowxe2x80x9d into the functioning of the SDRAM.
Currently, many of these SDRAM controllers are application specific integrated circuits (ASICs), which provide specific functionality for predetermined SDRAMs. Unfortunately, the extensive engineering necessary to develop and the long lead time associated with the manufacture of these custom devices render ASIC SDRAM controllers an expensive component of the system. This disadvantage is further exacerbated by the continuing fast pace of SDRAM technology development. Thus, by the time an ASIC SDRAM controller is placed in the system and the system is commercially available, new features are introduced on the next generation of SDRAM devices, thereby necessitating another expensive, ASIC development.
Therefore, a need arises for a device to implement an SDRAM controller which reduces the current lead time development of the controller as well as the time to market.
In accordance with the present invention, a programmable logic device (PLD) implements the SDRAM controller. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. For example, in one embodiment, the number of locations as well as the sequence of memory access in the burst mode are programmable in the PLD.
The state machine, implemented by the configurable logic of the PLD, includes the following steps during a Write operation. If the system issues a WRITE command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Write Wait for Ras-to-Cas Delay state. However, if the system issues a WRITE command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Write Command state in which the controller issues data and a WRITE command to the SDRAM. After the WRITE command is issued, the controller continues to provide data in a Write state until burst end, at which time the controller returns to an Idle state.
The state machine includes the following steps during a Read operation. If the system issues a READ command, but a Ras-to-Cas Delay time in the SDRAM has not been met, then the controller enters a Read Wait for Ras-to-Cas Delay state. However, if the system issues a READ command, and the Ras-to-Cas Delay time in the SDRAM has been met, then the controller enters a Read Command state and issues a READ command to the SDRAM. After the Read Command state, the controller automatically enters a Read Command, Wait for Cas Latency state. After the Read Command, Wait for Cas Latency state, the controller reads data in a Read state until burst end, at which time the controller enters an Idle state.
Specific PLDs, such as the Xilinx Virtex field programmable gate arrays (FPGAs), provide features which optimize the design of the SDRAM controller. In accordance with the present invention, dedicated circuits of the PLD eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock. These dedicated circuits include a first delay locked loop (DLL) receiving the system clock and outputting the SDRAM clock and a first feedback signal to the first DLL, and a second DLL receiving the system clock and outputting a second feedback signal to the second DLL. Of importance, the first feedback signal is external to the PLD and the second feedback signal is internal to the PLD.
In one embodiment, a global clock buffer on the PLD drives the system clock to the first and second DLLs. Other global clock buffers on the PLD drive the feedback signals to the DLLs.
Other dedicated circuits that optimize the SDRAM controller include a flip-flop associated with each input and output buffer of the input/output (I/O) blocks in the PLD. The present invention registers the input signals from and output signals to the SDRAMs. The I/O block further includes a programmable delay connected to the D input of the flip-flop registering the input signals to the PLD. The delay in matched to the internal clock distribution delay of the PLD, thereby eliminating pad-to-pad hold time.


A pulse generation circuit (11) generates a pulse signal (S11) of xe2x80x9cLxe2x80x9d with a rise of a clock signal (CLOCK) as a trigger. A latch circuit (12) changes a latch signal (S12) fry xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d on the basis of the pulse signal (11) of xe2x80x9cLxe2x80x9d. Inverters (G10, G11) output a signal (XDEC) on the basis of the latch signal (S12). Even when the generation of the xe2x80x9cLxe2x80x9d pulse of the pulse signal (S11) is terminated and the pulse signal (S11) returns to xe2x80x9cHxe2x80x9d, the latch circuit (12) is in a data holding state to sustain the latch signal (S12) of xe2x80x9cHxe2x80x9d during a period while the signal READY takes xe2x80x9cHxe2x80x9d. With this constitution, it is possible to provide a semiconductor integrated circuit having a control unit which can output an operation control signal in synchronization with the clock signal without being constrained by the time length of xe2x80x9cHxe2x80x9d (xe2x80x9cLxe2x80x9d) period of the clock signal.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a semiconductor memory device, and more particularly to a clock-synchronous RAM and the like.
2. Description of the Background Art
FIG. 11 is a block diagram showing an overall constitution of an SRAM (SP-SRAM) with one read/write port. As shown in FIG. 11, the SP-SRAM consists of a word line driver 2, an I/O circuit 3, a memory cell array 4, a timing generation circuit 6 and a delay circuit 7.
The memory cell array 4 consists of a plurality of memory cells (not shown) arranged in matrix, and connected to a common word line (not shown) in a unit of row and connected to a common bit line (not shown) in a unit of column. The word line driver 2 receives a signal XDEC serving as a word line drive control signal, comes into an active state when the signal XDEC takes xe2x80x9cHxe2x80x9d (High Level), and selectively activates (opens) the word line on the basis of an externally-received address signal AD.
The I/O circuit 3 includes an input/output buffer, a sense amplifier, a write driver and a precharge circuit (all of which are not shown) therein. The sense amplifier comes into an active state when a sense amplifier activation signal SE takes xe2x80x9cHxe2x80x9d, and when in the active state, it detects and amplifies read data given from a selected memory cell in the memory cell array and externally outputs the data as output data. The write driver comes into an active state when a driver control signal WE takes xe2x80x9cHxe2x80x9d, when in the active state, it outputs write data based on externally-received input data to the selected memory cell through a pair of bit lines. The precharge circuit comes into an active state when a precharge control signal PC takes xe2x80x9cHxe2x80x9d, and when in the active state, it precharges the pair of bit lines in the memory cell array 4 to a predetermined potential.
The timing generation circuit 6 receives a clock signal CLOCK, a signal WEC and a signal READY and outputs the signal XDEC, the: signal SE, the signal WE, the signal PC and a signal DUM_XDEC all of which serve as control signals.
The delay circuit 7 outputs the signal READY of xe2x80x9cLxe2x80x9d (Low Level) after a delay time xcex94T2 passes from the point of time when the signal DUM_XDEC changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d and outputs the signal READY of xe2x80x9cHxe2x80x9d immediately after the signal DUM_XDEC changes from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d. The delay time xcex94T2 is so set as to satisfy both a time required to activate the word line in the memory cell array 4 and detect and amplify the read data by the sense amplifier in a read mode and a time required to store the write data given from the write driver into the selected memory cell in a write mode.
FIG. 12 is a circuit diagram showing an internal configuration of the timing generation circuit 6 shown in FIG. 11. As shown in FIG. 12, inverters G51 and G52 are connected in series, and an input of the inverter G51 receives the clock signal CLOCK. One input of a NAND gate G54 receives an output from the inverter G52 and the other input receives the signal READY. An input of an inverter G56 receives an output from the NAND gate G54 and an input of an inverter G57 receives an output from the inverter G56.
On the other hand, an input of an inverter G55 receives the signal READY. One input of a NAND gate G58 receives an output from the inverter G55 and the other input receives the output from the inverter G52. An input of an inverter G59 receives an output from the NAND gate G58. One input of a NOR gate G60 receives the signal XDEC and the other input receives an output from the inverter G59.
Further, an input of an inverter G53 receives the signal WEC. One input of a NOR gate G61 receives the signal WEC and the other input receives the output from the NAND gate G54. One input of a NOR gate G62 receives an output from the inverter G53 and the other input receives the output from the NAND gate G54. Inverters G63 and G64 are connected in series, and an input of the inverter G63 receives an output from the NOR gate G61. Inverters G65 and G66 are connected in series, and an input of the inverter G65 receives an output from the NOR gate G62.
An output of the inverter G57 is outputted as the precharge control signal PC. An output of the inverter G56 is outputted as the signal XDEC. An output of the NOR gate G60 is outputted as the signal DUM_XDEC. An output of the inverter G64 is outputted as the sense amplifier activation signal SE. An output of the inverter G66 is outputted as the driver control signal WE.
FIG. 13 is a timing chart showing a generating operation of the timing generation circuit 6 shown in FIG. 12. Referring to FIG. 13, the operation of the timing generation circuit 6 will be discussed below.
First, in an initial state, the signal XDEC is set to xe2x80x9cLxe2x80x9d, the signal READY is set to xe2x80x9cHxe2x80x9d and the signal DUM_XDEC is set to xe2x80x9cHxe2x80x9d. Further, it is assumed here that the timing generation circuit 6 is in a read mode with the write control signal WEC of xe2x80x9cLxe2x80x9d. In the read mode, the driver control signal WE is fixed to xe2x80x9cLxe2x80x9d.
In the initial state, when the clock signal CLOCK rises to xe2x80x9cHxe2x80x9d, the signal XDEC changes to xe2x80x9cHxe2x80x9d (change CH11) with rise of the clock signal CLOCK to xe2x80x9cHxe2x80x9d as a trigger since the signal READY takes xe2x80x9cHxe2x80x9d.
At the same time as the change CH11, the precharge control signal PC and the signal DUM_XDEC fall to xe2x80x9cLxe2x80x9d and the sense amplifier activation signal SE rises to xe2x80x9cHxe2x80x9d.
When the signal XDEC takes xe2x80x9cHxe2x80x9d, the word line driver 2 comes into an active state and selectively drives the word line (into the active state) on the basis of the externally-received address signal AD.
At the same time, the precharge circuit comes into an inactive state with the precharge control signal PC of xe2x80x9cLxe2x80x9d, and the sense amplifier comes into an active state with the sense amplifier activation signal SE of xe2x80x9cHxe2x80x9d to externally output the read data from the selected memory cell as the output data which is detected and amplified, starting a read operation.
Then, after the delay time xcex94T2 passes from the rise of the signal XDEC (the fall of the signal DUM_XDEC), the signal READY falls to xe2x80x9cLxe2x80x9d (change CH12).
The signal XDEC falls to xe2x80x9cLxe2x80x9d (change CH13) with the fall of the signal READY to xe2x80x9cLxe2x80x9d. At the same time, the precharge control signal PC rises to xe2x80x9cHxe2x80x9d and the sense amplifier activation signal SE falls to xe2x80x9cLxe2x80x9d.
With the signal XDEC of xe2x80x9cLxe2x80x9d, the word line driver 2 comes into an inactive state to stop driving all the word lines, and with the sense amplifier activation signal SE of xe2x80x9cLxe2x80x9d, the sense amplifier comes into an inactive state, terminating the read operation. On the other hand, with the precharge control signal PC of xe2x80x9cHxe2x80x9d, a precharge operation on the pair of bit lines restarts.
Further, since the signal READY takes xe2x80x9cLxe2x80x9d, the signal DUM_XDEC sustains xe2x80x9cLxe2x80x9d even when the signal XDEC falls to xe2x80x9cLxe2x80x9d.
After that, when the clock signal CLOCK falls to xe2x80x9cLxe2x80x9d, the signal DUM_XDEC rises to xe2x80x9cHxe2x80x9d (change CH14) with fall of the clock signal CLOCK to xe2x80x9cLxe2x80x9d as a trigger.
Further, after the signal DUM_XDEC rises to xe2x80x9cHxe2x80x9d, the signal READY rises to xe2x80x9cHxe2x80x9d (change CH15) immediately. As a result, the signal XDEC comes into xe2x80x9cLxe2x80x9d and the signal READY and the signal DUM_XDEC come into xe2x80x9cHxe2x80x9d, returning to the initial state. After that, in synchronization with the clock signals CLOCK, the above operation is repeated.
Thus, the timing generation circuit 6 generates the signal XDEC, the precharge control signal PC and the sense amplifier activation signal SE all of which serve as the operation control signals, performing a timing control of the read operation.
Further, with the signal WEC of xe2x80x9cHxe2x80x9d, the timing generation circuit 6 comes into a write mode. Specifically, the timing generation circuit 6 generates the sense amplifier activation signal SE which is fixed to xe2x80x9cLxe2x80x9d, the driver control signal WE which changes like the sense amplifier activation signal SE in the read mode, and the signal XDEC and the precharge control signal Pc which change like those in the read mode, performing a timing control of the write operation.
Since the timing generation circuit 6 in the background art has a circuit configuration in which the logics and the clocks are combined as discussed above, the timing of generating the control signals (XDEC, WE, SE and PC) generated in the timing generation circuit 6 is constrained by the time length of xe2x80x9cHxe2x80x9d (xe2x80x9cLxe2x80x9d) period of the clock signal CLOCK and a high-speed operation of RAM is disadvantageously impeded.
For example, during a period while the signal XDEC takes xe2x80x9cHxe2x80x9d and the signal READY takes xe2x80x9cHxe2x80x9d after the signal change CH11 of FIG. 13 and the word line is driven to perform the read operation (write operation), when the clock signal CLOCK falls to xe2x80x9cLxe2x80x9d, the signal XDEC falls to xe2x80x9cLxe2x80x9d and accordingly the driving operation of the word line is forcedly terminated, to fail the read operation (write operation). Therefore, at least until the signal XDEC falls with the fall of the signal READY as a trigger, the clock signal CLOCK needs to sustain xe2x80x9cHxe2x80x9d.
The present invention is directed to a semiconductor integrated circuit. According to a first aspect of the present invention, the semiconductor integrated circuit comprises: a control unit for generating an operation control signal in synchronization with a clock signal; an operation unit for operating on the basis of the operation control signal, and in the semiconductor integrated circuit of the first aspect, the control unit outputs the operation control signal which is timing-controlled only by a single predetermined kind of signal shift of the clock signal.
According to a second aspect of the present invention, in the semiconductor integrated circuit of the first aspect, the control unit comprises a pulse generation circuit receiving the clock signal, for generating a pulse signal taking a first level or a second level, the pulse signal coming into the first level for a predetermined period from the single predetermined kind of signal shift of the clock signal; a latch circuit receiving the pulse signal, for outputting a latch signal having a signal value based on the first level in response to the pulse signal of the first level, and after that coming into a data holding state for a predetermined period to hold the signal value of the latch signal regardless of the level of the pulse signal; and a control signal generation circuit for generating the operation control signal on the basis of the latch signal.
According to a third aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the control unit further comprises an operation control signal high-speed setting circuit for making the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal, when the pulse signal takes the first level.
According to a fourth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the control unit further comprises an auxiliary signal outputting circuit for outputting an auxiliary signal on the basis of the operation control signal, and the latch circuit releases the data holding state when the auxiliary signal takes a predetermined signal value.
According to a fifth aspect of the present invention, in the semiconductor integrated circuit of the fourth aspect, the control unit further comprises an operation control signal high-speed setting circuit for making the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal, when the auxiliary signal takes the predetermined signal value.
According to a sixth aspect of the present invention, in the semiconductor integrated circuit of the fourth or fifth aspect, the auxiliary signal outputting circuit includes a delay circuit receiving the operation control signal, for outputting the auxiliary signal of the predetermined signal value on the basis of a delayed signal of the operation control signal.
Preferably, the operation unit includes a semiconductor memory unit constituted of a memory cell array having a plurality of memory cells arranged in matrix.
Preferably, the operation control signal includes an operation control signal for selecting the memory cells of the memory cell array.
Preferably, the operation control signal high-speed setting circuit includes a first transistor having one electrode receiving a fixed potential, the other electrode connected to a node which determines a signal value of the operation control signal, and a control electrode receiving a pulse-related signal which takes a signal value corresponding to a signal value of the pulse signal, and the first transistor comes into an on state when the pulse-related signal takes a signal value set correspondingly to the first level of the pulse signal.
Preferably, the latch circuit has a first NAND gate and a second NAND gate, the first NAND gate has one input receiving the pulse signal and the other input receiving an output from the second NAND gate and outputs the latch signal, the second NAND gate has one input receiving the latch signal and the other input receiving the auxiliary signal, the first level includes xe2x80x9cLxe2x80x9d level, and the predetermined level includes xe2x80x9cLxe2x80x9d level.
Preferably, the latch circuit has a first NOR gate and a second NOR gate, the first NOR gate has one input receiving the pulse signal and the other input receiving an output from the second NOR gate and outputs the latch signal, the second NOR gate has one input receiving the latch signal and the other input receiving an inverted signal of the auxiliary signal, the first level includes xe2x80x9cHxe2x80x9d level, and the predetermined level includes xe2x80x9cLxe2x80x9d level.
Preferably, the operation control signal high-speed setting circuit includes a second transistor having one electrode receiving a fixed potential, the other electrode connected to a node which determines a signal value of the operation control signal, and a control electrode receiving an auxiliary-related signal which takes a signal value corresponding to a signal value of the auxiliary signal, and the second transistor comes into an on state when the auxiliary-related signal takes a signal value set correspondingly to the predetermined level of the auxiliary signal.
In the semiconductor integrated circuit of the first aspect of the present invention, since the control unit can output the operation control signal which is unconstrained by a signal level sustain period of the clock signal by outputting the operation control signal which is timing-controlled only by the single predetermined kind of signal shift of the clock signal, it is possible to achieve a high-speed operation of the operation unit.
In the semiconductor integrated circuit of the second aspect of the present invention, the latch circuit of the control unit receives the pulse signal which comes into he first level for a predetermined period from the single predetermined kind of signal shift of the clock signal, with the pulse signal of the first level unconditionally taken, outputs the latch signal having the signal value based on the first level, and then comes into the data holding state for a predetermined period to hold the signal value of the latch signal regardless of a signal value of the pulse signal.
Therefore, it is possible to generate the operation control signal on the basis of the signal value of the latch signal at a timing depending only on the single predetermined kind of signal shift of the clock signal.
In the semiconductor integrated circuit of the third aspect of the present invention, since the operation control signal high-speed setting circuit makes the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal when the pulse signal takes the first level, it is possible to set the signal value of the operation control signal at high speed with the single predetermined kind of signal shift (change of the pulse signal from the second level to the first level) of the clock signal as a trigger.
In the semiconductor integrated circuit of the fourth aspect of the present invention, since the latch circuit releases the data holding state when the auxiliary signal takes the predetermined signal value, it is possible to control the timing of terminating the output of the latch signal having the signal value based on the first level with the auxiliary signal.
In the semiconductor integrated circuit of the fifth aspect of the present invention, since the operation control signal high-speed setting circuit makes the control signal generation circuit generate the operation control signal which is generated by the control signal generation circuit in response to the latch signal in advance before the control signal generation circuit is driven by the latch signal when the auxiliary signal takes the predetermined signal value, it is possible to set the signal value of the operation control signal at high speed with a signal change of the auxiliary signal to a predetermined signal value as a trigger.
In the semiconductor integrated circuit of the sixth aspect of the present invention, since the delay circuit outputs the auxiliary signal having the predetermined signal value on the basis of the delayed signal of the operation control signal, it is possible to set the timing of outputting the auxiliary signal of predetermined level, depending on a signal change of the operation control signal.
An object of the present invention is to provide a semiconductor integrated circuit having a control unit which generates an operation control signal in synchronization with a clock signal for an operation unit of a RAM such as a memory cell array, a word line driver and an I/O circuit and is unconstrained by the time length of xe2x80x9cHxe2x80x9d (xe2x80x9cLxe2x80x9d) period of the clock signal.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


A derailleur comprises a base member, a movable member, a link member, and a biasing mechanism. The movable member is configured to be movable with respect to the base member between a retracted position and an extended position. The link member is configured to movably couple the movable member to the base member. The biasing mechanism is configured to bias the link member such that the movable member is disposed at one of the retracted position and the extended position. The biasing mechanism comprises a biasing member and an intermediate member. The biasing member has a first end portion. The intermediate member is separately provided from the movable member and the link member so as to transmit biasing force of the biasing member from the first end portion to one of the movable member and the link member through the intermediate member.

1. Field of the Invention
The present invention relates to a derailleur.
2. Discussion of the Background
Bicycling is becoming an increasingly more popular form of recreation as well as a means of transportation. Moreover, bicycling has become a very popular competitive sport for both amateurs and professionals. Whether the bicycle is used for recreation, transportation or competition, the bicycle industry is constantly improving the various components of the bicycle. One component that has been recently redesigned is a derailleur. The derailleur laterally shifts a bicycle chain to change gears of the bicycle. A front derailleur and a rear derailleur are known as the derailleur.


The present application is directed to set screws used with fasteners to capture and engage an elongated member. The set screws include a body sized to attach to a receiver of the fastener. A deformable member may be attached to an end of the set screw and provides for the set screw to more fully engage the elongated member to prevent potential damage to the elongated member and prevent the set screw from backing out of the fastener. In one embodiment, just the deformable member contacts the elongated member. In another embodiment, the deformable member and the body contact the elongated member. In yet another embodiment, a contact member is attached to the deformable member to contact against the elongated member.

The present application is directed to set screws used for use with fasteners to attach an elongated member to a bone and, more particularly, to set screws with a deformable member that increases the contact with the elongated member to prevent back-out of the set screw from the fastener and/or damage to the elongated member.
Set screws are often used with fasteners to attach an elongated member to a bone within a patient. Examples of fasteners include but are not limited to multi-axial screws, fixed-angle screws, and offset screw connectors. The fasteners may include a receiver with a receptacle to receive the elongated member, and an anchor (e.g., screw, hook) that attaches to the bone. The fasteners may be constructed as a single piece, or may include multiple pieces that are attached together such as a multi-axial screw that includes a receiver body that attaches to a head of bone screw. The elongated member fits within the receptacle of the receiver, and the set screw attaches to the receiver to prevent escape of the elongated member. The set screw may also apply a force to the elongated member to maintain the attachment within the receiver. The fasteners may be configured to receive a variety of different elongated members, including but not limited to rods, cables, and wires.
Often times the receiver is configured to allow the elongated member to be positioned at a variety of angles within the receptacle. This is problematic as the set screw does not fully contact against the elongated member. This may lead to the loosening of the set screw from the receiver and/or backing out of the set screw from the receiver. Additionally, this incomplete contact may damage the elongated member and causing notching or deformation.


There is disclosed an apparatus for precisely regulating, with a simple structure, a state of charge of each of cells constituting a battery set. In the apparatus, a detection circuit, a plurality of discharge circuit connected to corresponding one of the cells, respectively, and a control circuit are provided. The detection circuit detects open-circuit voltage of each of the plurality of cells, the plurality of discharge circuit discharges a charging electricity charged in the cells, and the control circuit controls to uniform the state of charge of each of the cells, utilizing the discharge circuit respectively corresponding to each of the cells, based on the open-circuit voltage of each of the cells detected by the detection circuit.

1. Field of the Invention
The present invention relates to an apparatus for regulating a state of charge of cells of a battery set, which is preferably used for regulating a state of charge of each cell of a battery set for an electric automotive vehicle, for example.
2. Description of the Related Art
Conventionally, an apparatus has been proposed for regulating to uniform each of the states of charge of a plurality of secondary cells serially connected in a battery set. The state of charge of the secondary cell is shown as SOC and the secondary cell is shown as cell, hereinafter.
For example, in an apparatus disclosed in Japanese Patent Application Unexamined Laid-open publication No. 7-336905, a constant-voltage circuit having a constant voltage control section and a current saturation detecting section is provided so as to be connected in parallel with each of the cells constituting a battery set. Here, electric current is charged from a charger to the cells while bypassing a portion of the current in accordance with a difference between a voltage of each of the cells and a set voltage, the voltage of each of the cells is controlled using the constant-voltage circuit such that the voltage becomes equal to the set voltage, and the SOC of each of the cells are uniformly regulated.
More specifically, the flow of charging current to each of the cells is suppressed by bypassing in order of SOC having a higher value, and, to unsuppressed cells, all of the charging current is charged, because the charging current is not bypassed.
When the current saturation detecting section detects that the bypassed cell whose charging current is suppressed is saturated, a current reducing signal is sent to the charger in order to reduce the charging current.
Then, the charging current is reduced stepwisely by repeating the above operation, and when a predetermined minimum charging current is achieved, the charging of the cell is completed.
However, in such an apparatus, the constant-voltage circuit is operated to regulate the SOC in each of the cells just before the charging is completed, and in the case that the charging is not conducted until the predetermined minimum charging current is achieved before the charging is completed, the SOC of each of the cells can not be regulated sufficiently.
Further, in this apparatus, the charging current is suppressed by flowing great bypass current of about maximum 1(A) in a short time about 30 minutes. Therefore, a heating value of the constant-voltage circuit is great and it is necessary to provide a radiator of large volume.
Further, in this apparatus, to put it in an extreme way, the SOC is regulated by flowing the same charging current to each of the cells or by stopping the flow of the charging current, and for example, since a magnitude of electric amount (Ah) to be charged can not independently be varied for a cell except the electrically bypassed cell, it is difficult to precisely regulate the SOC for each of the cells with respect to a target SOC, and regulating precision is not excellent.

Apparatus for regulating state of charge of cells of battery set