A method of fabricating a reflective type LCD, having the steps of: (a)providing a substrate; (b) forming a polymer resin layer on the substrate; (c) forming a positive-type photoresist layer on the polymer resin layer, wherein the upper surface of the photoresist layer has a convex/concave profile; and (d)performing a dry etching process to completely remove the photoresist layer and partially remove the polymer resin layer so as to shape the upper surface of the polymer resin layer into a convex/concave profile.

1. Field of the Invention
The present invention relates in general to a method of fabricating reflective type liquid crystal display (LCD). In particular, the present invention relates to a method of fabricating a concave/convex profile on a reflective film of the reflective type LCD.
2. Description of the Related Art
Currently, liquid crystal display (LCD), having the advantages of low power consumption, thin type, light weight and low driving-voltage, has been put to practical use, such as with personal computers, archival treatments, navigation systems, Gameboys, projectors, view finders and portable machines (watches, electronic calculators and televisions). In particular, a reflective type LCD can display bright images and high contrast by the reflection of the incident light, and thereby achieves lower power consumption, thinner type and lighter weight.
Mostly, the reflective type LCD employs the twisted nematic (TN) crystals or the super-twisted nematic (STN) crystals. However, the polariscope disables more than half of the illuminant and therefore darkens the brightness of the display images. In order to enhance the use efficiency of the illuminant, now the reflective type LCD employs the guest-host (GH) type crystals, that is, a combination of the nematic crystals and dichroic dyes, to change the arrangement of the crystal molecules and adjust the light-absorbency of the dyes by a electric field. Also, for further enhancing the brightness and contrast, a reflective film with a gently curved profile serving as a white scattered surface is needed because the concave/convex on the upper surface of the reflective film can increase the intensity of the incident light.
As shown in FIG. 1, an LCD 10 according to the prior art comprises a semiconductor substrate 1 and a metal wiring layer 2 formed on the substrate 1. The metal wiring layer 2 electrically connects elements (not shown) formed in the substrate 1 for driving the LCD 10, such as transistors, resistors or capacitors. A polyimide resin layer 3 is coated on the semiconductor substrate 1 and has a contact hole 4 for exposing a predetermined area of the metal wiring layer 2. A display electrode 5, made of aluminum and serving as a reflective film, is formed on the polyimide resin layer 3 and connects to the metal wiring layer 2 through the contact hole 4. The polyimide resin layer 3 has an upper surface with small protrusions or depressions having a gently curved profile, and accordingly the display electrode 5 has an upper surface with small protrusions or depressions having a gently curved profile for making a white scattered surface. The LCD 10 further comprises a transparent glass substrate 8 and a transparent conductive film 7 formed on the transparent substrate 8. A Guest-Host type liquid crystal 6 is filled in a gap between the display electrode 5 and the transparent conductive film 7.
However, if the protrusions or depressions of the display electrode 5 have sharp-pointed edges, the incident light generates multiple reflective effects and thus darkens the brightness of the display images. In order to solve this problem, the U.S. Pat. No. 4,519,678 provides two methods of fabricating the gently curved profile of the display electrode 5. In the first method, as shown in FIG. 2, the polyimide resin layer 3 is firstly coated on the semiconductor substrate 1, and then cured by a heat treatment about 100xcx9c200xc2x0 C. Next, by using a mask 9 with a spot-like resist pattern wherein the openings are arranged at a pitch of 1 to 50 microns, an etching process is performed on the polyimide resin layer 3 to form a plurality of small protrusions and depressions having the concave/convex profile. Concerning the materials of the polyimide resin layer 3, if a thermosetting resin is used, it is desirable to perform an isotropic etching process, such as a wet etching method. If a thermoplastic resin is used, it is desirable to perform an anisotropic etching process, such as a dry etching or a reactive ion etching (RIE) method and then a heat treatment about 150xcx9c500xc2x0 C. is necessary for rounding the edges of the protrusions or depressions after removing the mask 9. Next, a photolithography process is needed to pattern the contact hole 4 on the polyimide resin layer 3 for exposing the predetermined area of the metal wiring layer 2. Next, after covering the display electrode 5 on the upper surface of the polyimide resin layer 3, a selective etching process is performed to shape the upper surface of the display electrode 5 into the desired curved profile.
In the second method, as shown in FIG. 3A, an insulating layer 12 is first formed on the substrate 1. Then, as shown in FIG. 3B, the insulating layer 12 is etched to become a plurality of separated bumps 16 by using a mask 14. Next, as shown in FIG. 3C, after removing the mask 14, the polyimide resin layer 3 is coated on the substrate 1 by a high-speed spin coating process at 2000xcx9c5000 rpm. Since the viscosity of the polyimide resin layer 3 differs from the change in speed, the upper surface of the polyimide resin layer 3 shows a concave/convex profile depending on the arrangement of the bumps 16. Finally, as shown in FIG. 3D, the display electrode 5 is deposited on the polyimide resin layer 3 and accordingly has the gently curved profile.
From the above description, the two conventional methods are thought to be too complex to ensure the process reliability. For this reason, a third conventional method provides a simpler process for fabricating the concave/convex profile. As shown in FIG. 4A, a polyimide resin layer 22 with photosensitive and thermosetting characteristics is formed on a semiconductor substrate 20. Next, an exposure process is performed on the polyimide resin layer 22 by using a mask (not shown) with a spot-like pattern, and then a development process is performed to remove the exposed areas of the polyimide resin layer 22 so as to form the upper surface as a plurality of continuous bumps 221 or concaves 222, as shown in FIG. 4B. Next, a heat treatment is necessary for changing the viscosity of the polyimide resin layer 22 and reflowing thereof. At the same time, owing to the polyimide resin layer 22 made of thermosetting resin, the edges of the bumps 221 and the concaves 222 are rounded to become a gently curved profile 22xe2x80x2, as shown in FIG. 4C. Finally, another heat treatment is utilized to cure the polyimide resin layer 22.
However, by the request of the high aperture ratio, the polyimide resin layer 22 with a thickness of 2xcx9c4 is needed but which always causes each bump 221 to have different thicknesses during the development process. The lack of uniformity will make the profile 22xe2x80x2 have unsymmetrical concaves/convexes during the sequential heat treatment and reflowing. Also, the quality of the reflective film is accordingly reduced.
An object of the present invention is to provide a method of forming a reflective type LCD to solve the above-described problems.
Another object of the present invention is to provide a method of fabricating a reflective type LCD, including the steps of: (a) providing a substrate; (b) forming a polymer resin layer on the substrate; (c) forming a positive-type photoresist layer on the polymer resin layer, wherein the upper surface of the photoresist layer has a convex/concave profile; and (d) performing a dry etching process to completely remove the photoresist layer and partially remove the polymer resin layer so as to shape the upper surface of the polymer resin layer into a convex/concave profile.
Another object of the present invention is to provide a method of fabricating a reflective type LCD, including the steps of: (a) providing a substrate on which a metallic wiring layer is covered; (b) forming a polymer resin layer on the substrate to cover the metallic wiring layer; (c) forming a contact hole on the polymer resin layer to expose a part of the metallic wiring layer; (d) forming a positive-type photoresist layer on the polymer resin layer to fill the contact hole; (e) forming the upper surface of the photoresist layer as a convex/concave profile; (f) performing a dry etching process to completely remove the photoresist layer and partially remove the polymer resin layer so as to make the upper surface of the polymer resin layer have a convex/concave profile; and (g) covering a metallic reflective layer on the polymer resin layer so as to have an upper surface with a convex/concave profile.
It is an advantage of the present invention that the polymer resin layer with the concave/convex profile in the present invention is shaped by etching the photoresist layer without etching and rounding the polymer resin layer. Consequently, the method is simplified and the uniformity of the upper surface of the polymer resin layer is well controlled. This can ensure the property of the formation the reflective film.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.

Method of fabricating a reflective type LCD


The present invention discloses a link motion-based food swallowing simulator comprising a swallowing module including a bionic oral cavity assembly, a shred collecting assembly and a supporting assembly wherein two side plates of a maxillary base of the bionic oral cavity assembly connect to a mounting plate of the supporting assembly, wherein the shred collecting assembly is positioned on a mounting base of the supporting assembly; an adjusting module, positioned under the mounting base, includes a bearing assembly and an adjusting assembly wherein the bearing assembly is disposed on the adjusting assembly, achieving the simulation of the food swallowing mechanism from static to dynamic. The adoption of the driving module realizes the swallowing action through link motion simulation, simulating the swallowing process of the human body and the swallowing process of the patient lying on the back through adjusting modules, improving the swallowing situation with higher adaptability.

With the growth of aging population and the gradually deteriorating swallowing function of the elderly, dysphagia becomes more common in the society. However, due to the complexity of the structure and nervous system of the human swallowing system, it is difficult to obtain the in vivo measurement data of food flow in the swallowing system, which directly leads to the failure of applying medicine according to the indications, and hinders the research on the influence of the material characteristics of food to the swallowing process and the development of safe food. In order to improve the medical diagnostic level of dysphagia, a link motion-based food swallowing simulator is proposed, which can provide an in vitro test environment to study the flow characteristics of food when it is swallowed, which is of great significance for the research and treatment of dysphagia, so as to improve the quality of life of patients with dysphagia.
Most of the current structural models of swallowing system are static structural models, which is not able to demonstrate the swallowing process dynamically. Some of the dynamic structural models are relatively simple in structure and cannot correctly express the food swallowing process. Through the link motion mechanism, the swallowing simulator according to the present invention is able to simulate the curves of movement of the tongue, and further provides multiangle swallowing simulation with a variable inclination angle device, a collection box and a collection tank. The variable inclination angle device can well simulate the real swallowing status of people as their heads may move while swallowing. Therefore, the simulator is of great significance for the study of the real swallowing status in human body.

Link motion-based food swallowing simulator


A system for offshore treatment of drill cuttings that includes a first pressurized vessel configured to receive contaminated drill cuttings and adapted to allow a compressed gas be introduced therein as the sole means for inducing movement of said contaminated drill cuttings in the first pressurized vessel, whereby at least a portion of the contaminated drill cuttings is discharged from the first pressurized vessel; and a reactor unit in fluid connection with the first pressurized vessel for separating the contaminated drill cuttings into drill cuttings and contaminants, wherein the reactor unit includes a processing chamber having at least one inlet and outlet; and a rotor mounted in the processing chamber, the rotor including a shaft; and a plurality of fixed rotor arms extending radially from the shaft is disclosed.

1. Field of the Invention
Embodiments disclosed herein relate generally to methods and systems for the offshore thermal treatment of drill cuttings.
2. Background Art
When drilling or completing wells in earth formations, various fluids ("well fluids") are typically used in the well for a variety of reasons. Common uses for well fluids include: lubrication and cooling of drill bit cutting surfaces while drilling generally or drilling-in (i.e., drilling in a targeted petroleum bearing formation), transportation of "cuttings" (pieces of formation dislodged by the cutting action of the teeth on a drill bit) to the surface, controlling formation fluid pressure to prevent blowouts, maintaining well stability, suspending solids in the well, minimizing fluid loss into and stabilizing the formation through which the well is being drilled, fracturing the formation in the vicinity of the well, displacing the fluid within the well with another fluid, cleaning the well, testing the well, implacing a packer fluid, abandoning the well or preparing the well for abandonment, and otherwise treating the well or the formation.
As stated above, one use of well fluids is the removal of rock particles ("cuttings") from the formation being drilled. However, because of the oil content in the recovered cuttings, particularly when the drilling fluid is oil-based or hydrocarbon-based, the cuttings are an environmentally hazardous material, making disposal a problem. That is, the oil from the drilling fluid (as well as any oil from the formation) becomes associated with or adsorbed to the surfaces of the cuttings.
A variety of methods have been proposed to remove adsorbed hydrocarbons from the cuttings. U.S. Pat. No. 5,968,370 discloses one such method which includes applying a treatment fluid to the contaminated cuttings. The treatment fluid includes water, a silicate, a nonionic surfactant, an anionic surfactant, a phosphate builder and a caustic compound. The treatment fluid is then contacted with, and preferably mixed thoroughly with, the contaminated cuttings for a time sufficient to remove the hydrocarbons from at least some of the solid particles. The treatment fluid causes the hydrocarbons to be desorbed and otherwise disassociated from the solid particles.
Furthermore, the hydrocarbons then form a separate homogenous layer from the treatment fluid and any aqueous component. The hydrocarbons are then separated from the treatment fluid and from the solid particles in a separation step, e.g., by skimming. The hydrocarbons are then recovered, and the treatment fluid is recycled by applying the treatment fluid to additional contaminated sludge. The solvent must be processed separately.
Some prior art systems use low-temperature thermal desorption as a means for removing hydrocarbons from extracted soils. Generally speaking, low-temperature thermal desorption (LTTD) is an ex-situ remedial technology that uses heat to physically separate hydrocarbons from excavated soils. Thermal desorbers are designed to heat soils to temperatures sufficient to cause hydrocarbons to volatilize and desorb (physically separate) from the soil. Typically, in prior art systems, some pre- and post-processing of the excavated soil is required when using LTTD. In particular, cuttings are first screened to remove large cuttings (e.g., cuttings that are greater than 2 inches in diameter). These cuttings may be sized (i.e., crushed or shredded) and then introduced back into a feed material. After leaving the desorber, soils are cooled, re-moistened, and stabilized (as necessary) to prepare them for disposal/reuse.
U.S. Pat. No. 5,127,343 (the '343 patent) discloses one prior art apparatus for the low-temperature thermal desorption of hydrocarbons. FIG. 1 from the '343 patent reveals that the apparatus consists of three main parts: a soil treating vessel, a bank of heaters, and a vacuum and gas discharge system. The soil treating vessel is a rectangularly shaped receptacle. The bottom wall of the soil treating vessel has a plurality of vacuum chambers, and each vacuum chamber has an elongated vacuum tube positioned inside. The vacuum tube is surrounded by pea gravel, which traps dirt particles and prevents them from entering a vacuum pump attached to the vacuum tube.
The bank of heaters has a plurality of downwardly directed infrared heaters, which are closely spaced to thoroughly heat the entire surface of soil when the heaters are on. The apparatus functions by heating the soil both radiantly and conventionally, and a vacuum is then pulled through tubes at a point furthest away from the heaters. This vacuum both draws the convection heat (formed by the excitation of the molecules from the infrared radiation) throughout the soil and reduces the vapor pressure within the treatment chamber. Lowering the vapor pressure decreases the boiling point of the hydrocarbons, causing the hydrocarbons to volatize at much lower temperatures than normal. The vacuum then removes the vapors and exhausts them through an exhaust stack, which may include a condenser or a catalytic converter.
Hammermill processes are often also used to recover hydrocarbons from a solid. In the typical hammermill process, the friction principle is used to generate sufficient energy for the oil fractions to be evaporated off. Specifically, a hammer mill with swinging rotor arms are used to finely crush all the particles, which results in the generation of heat, and allows for the evaporation of the oil in the material at a temperature lower than normal evaporation.
U.S. Patent Publication No. 2004/0149395 discloses a rotomill process, based on the hammermill technology, by which adsorbed oil may be evaporated at a temperature lower than its atmospheric boiling point. The presence of a vapor phase of a second component (typically water) allows for a substantial reduction in the partial pressure of the hydrocarbons, and thus a decrease in their boiling point.
Thermal desorption units are typically set up as fixed, land-based installation due to the off shore limitations associated with size, weight, and processing capacity. Thus, to avoid contamination by oil-coated drill cuttings, cuttings are typically transported onshore for processing.
Further complicating the treatment of drill cuttings, when a wellbore fluid brings cuttings to the surface, the mixture is typically subjected to various mechanical treatments (shakers, centrifuges, etc) to separate the cuttings from the recyclable wellbore fluid. However, the separated drill cuttings, which still possess a certain portion of oil from the wellbore fluid absorbed thereto, are in the form of a very thick heavy paste, creating difficulties in handling and transportation. Thus, frequently, in offshore applications, the thick drill cuttings paste is slurrified with a carrier fluid, typically an oil-based fluid, to allow for ease in pumping and handling the drill cuttings paste.
Accordingly, there exists a continuing need for improvements in the offshore treatment of drill cuttings.

Offshore thermal treatment of drill cuttings fed from a bulk transfer system


A semiconductor device having an internal voltage down converter includes a circuit operating with an externally applied power supply voltage, a circuit operating with an external stepped-down voltage as an operation power supply voltage, and substrate voltage generators for generating a substrate potential, or a substrate bias voltage according to a state of the internal stepped-down voltage. The first substrate voltage generator includes a first generating circuit operating with the externally applied power supply voltage, a second generating circuit operating with the internal stepped-down voltage, and a circuit for operating the first generating circuit in a period from turn-on of the external power supply until the internal stepped-down voltage becomes stable, and for operating the second generating circuit thereafter. The second substrate voltage generator includes first and second generating circuits, and a circuit responsive to the substrate voltage for selectively activating the first and second generating circuits. Those constructions make it possible to stably apply a substrate voltage corresponding to an operation voltage to the substrate region.

1. Field of the Invention
The present invention relates to a substrate voltage generator for applying a prescribed bias voltage to a semiconductor substrate and particularly to a substrate voltage generator and a method therefor in a semiconductor device having an internal voltage down converter for lowering an external power supply voltage, thereby generating an internal stepped-down power supply voltage.
2. Description of the Background Art
Recently, 4 M (mega) bit static random access memories (SRAMs) and 16 M (mega) bit dynamic random access memories (RAMs) utilizing micro-lithography of 0.5 .mu.m level have been developed and made public. It is pointed out that if a short channel MOS (insulated gate field effect) transistor of a gate length of less than 0.6 .mu.m is operated by a power supply voltage 5 V in the same manner as in a MOS transistor of a gate length of about 1 .mu.m to 0.8 .mu.m used in a 4 M bit DRAM or the like, transistor characteristics are deteriorated considerably due to time dependent dielectric breakdown of a gate insulating film or the like, causing reliability to be lowered.
In order to use a short channel MOS transistor having a gate length of 0.5 .mu.m not causing such deterioration of transistor characteristics, it may be considered to change the power supply voltage from 5 V to 3.3 V for example. However, in view of adaptability to the 5 V power supply system widely used conventionally, a problem is involved in the change of the power supply voltage. Therefore, there has been proposed a system of operating an internal circuit of a semiconductor memory device by a stepped-down voltage of e.g. 3.3 V while maintaining the external power supply voltage at 5 V as in the prior art.
FIG. 1 is a functional block diagram of a conventional semiconductor device having an internal voltage down converter. Referring to FIG. 1, the semiconductor device includes a function circuit 101 formed by a memory for example for performing a prescribed function, and an input/output circuit 102 for transfer of data between the function circuit 101 and an external unit. The semiconductor device further includes an internal voltage down converter 103 for lowering an externally applied power supply voltage Vocc and generating a prescribed internal power supply voltage Vicc, and a substrate voltage generator (V.sub.BB generator) 104 responsive to the external power supply voltage Vocc for generating a prescribed bias voltage and applying the same to a semiconductor substrate 100.
The semiconductor device shown in FIG. 1 contains the internal voltage down converter 103 integrated on the semiconductor substrate 100, and the external power supply voltage Vocc is converted to be stepped down by the internal voltage down converter 103, whereby the prescribed internal power supply voltage Vicc is generated. In some cases, the prescribed internal power supply voltage Vicc is supplied to only the function circuit 101, and in some cases, it is supplied to both the function circuit 101 and the input/output circuit 102.
FIG. 2 is a block diagram of the internal voltage down converter shown in FIG. 1, which is disclosed for example by Furuyama et al. in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, June, 1987, pp. 437-441. Referring to FIG. 2, the internal voltage down converter 103 includes: a reference voltage generating circuit 110 for generating a prescribed reference voltage Vref from the external power supply voltage Vocc; a differential amplifier 111 operating with the external power supply voltage Vocc as the operation power supply voltage for comparing the internal power supply voltage Vicc and the reference voltage Vref and generating a control signal (regulation signal) .phi..sub.x according to the result of the comparison; and an output circuit 112 responsive to the regulation signal .phi..sub.x from the differential amplifier 111 for receiving current from the external power supply voltage Vocc and generating the internal power supply voltage Vicc.
The differential amplifier 111 amplifies differentially the reference voltage Vref and the internal power supply voltage Vicc, thereby generating the regulation signal .phi..sub.x.
FIG. 3 is a diagram showing a specific construction of the internal voltage down converter shown in FIG. 2. Referring to FIG. 3, the reference voltage generating circuit 110 includes: three p channel MOS transistors P1, P2, P3 seriesly-connected between the external power supply voltage vocc and a second power supply voltage Vss as a ground potential for example; a p channel MOS transistor P4 connected between the external power supply voltage Vocc and a node N2 and receiving a potential of a node N1 at its gate; and a p channel MOS transistor P5 connected between the node N2 and the second power supply potential (referred to simply as the ground potential) Vss. The p channel MOS transistors P1 to P3 have their gates and drains connected together to function as a resistor, so that a voltage according to the on resistance thereof is supplied to the node N1. The p channel MOS transistor P4 receives the potential of the node N1 at its gate and has a resistance value according to the gate potential, and it transmits current from the external power supply voltage Vocc to the node N2. Those p channel MOS transistors P1 to P4 constitute a constant current load with respect to the p channel MOS transistor P5. Operation of this reference voltage generating circuit will be briefly described.
Now, let us assume a case in which the external power supply voltage Vocc is increased. In this case, a large amount of current flows into a path formed by the transistors P1 to P3, whereby the potential of the node N1 increases. In response to the increase of the potential of the node N1, the gate potential of the transistor P4 increases. Thus, the resistance value of the transistor P4 increases, making it difficult for current to flow in the transistor P4.
Conversely, if the external power supply voltage Vocc is decreased, the current flowing in the path formed by the transistors P1 to P3 becomes small. Thus, the potential of the node N1 is lowered and the resistance value of the transistor P4 becomes small, whereby current can easily flows through the transistor P4. The gate potential of the transistor P4 is regulated according to change in the external power supply voltage Vocc, whereby constant current always flows into the node N2 and the constant reference voltage Vref proportional to an absolute value of threshold voltage V.sub.TP of the transistor P5 appears at the node N2 (in the case where a plurality of transistors P5 are provided).
The differential amplifier 111 includes: a p channel MOS transistor P10 provided between the external power supply voltage Vocc and a node N3, and receiving a clock signal .phi.c at its gate; a p channel MOS transistor P11 provided between the external power supply voltage Vocc and the node N3 and having its gate connected to the ground potential Vss; a p channel MOS transistor P12 provided between the node N3 and a node N4 and receiving the reference voltage Vref at its gate; a p channel MOS transistor P13 provided between the nodes N3 and N5 and receiving the internal power supply voltage Vicc at its gate; an n channel MOS transistor NT1 provided between the node N4 and the ground potential Vss and having its gate connected to the node N5; and an n channel MOS transistor NT2 provided between the node N5 and the ground potential Vss and having its gate connected to the node N5 and the gate of the transistor NT1.
The transistor P10 has a relatively large current supplying capability, while the transistor P11 has a small current supplying capability to allow a very small current to flow. The control signal .phi.c is set to a logical low (L) level of an activated state during a period in which the function circuit 101 (as shown in FIG. 1) of the semiconductor device operates, and it is set to a logical high (H) level of an inactivated state during a period in which the internal circuit does not operate. Thus, the transistor P10 having the large current supplying capability is in a conducting state during the operation of the internal circuit to improve the response characteristics of a current mirror type amplifier (i.e., a circuit stage formed by the transistors P12, P13, NT1 and NT2), and only the transistor P11 is in a conducting state in the period of non-operation of the internal circuit, thereby reducing consumption current. Switching between the operation and non-operation of the internal circuit is effected in the following manner. For example, if the function circuit 101 is a memory, the control signal .phi.c is generated in response to a signal (e.g., a signal RAS) indicating whether a memory cycle is started or not.
The output circuit 112 is provided between the external power supply voltage Vocc and the internal power supply voltage line Vicc (a signal line and a signal transmitted thereon being shown by the same reference characters) and it includes a p channel MOS transistor P15 having its gate receiving the potential of the node N4 of the differential amplifier 111 as the regulation signal .phi..sub.x. Next, operations of the differential amplifier 111 and the output circuit 112 will be described.
Let us now assume that the internal power supply voltage Vicc becomes larger than the reference voltage Vref.
In this case, current flowing through the transistor P12 becomes larger than the current flowing through the transistor P13. The node N5 is connected to the gates of the transistors NT1 and NT2, and the transistors NT1 and NT2 constitute a current mirror circuit. The potential of the node N5 proportions to a value of the current flowing through the transistor P13. The larger the current flowing through the transistor P13 is, the higher the potential of the node N5 is, while the smaller the current is, the lower the potential is. The values of the current flowing in the transistors NT1 and NT2 become equal and accordingly the transistor NT1 does not allow the large current to sufficiently flow in the transistor P12, causing the potential of the node N4 to rise. In response to the rise of the potential of the node N4, namely, the regulation signal .phi..sub.x, the transistor T15 is brought into a shallow on state or an off state. As a result, the supply of the current from the external power supply voltage Vocc to the internal power supply voltage line Vicc is stopped or suppressed and the internal power supply voltage Vicc is lowered.
If the internal power supply voltage Vicc is smaller than the reference voltage Vref, the regulation signal .phi..sub.x is lowered oppositely to the above-mentioned case and the transistor P15 is brought into a conducting state or a deeply conducting state. Thus, a sufficient current is supplied from the external power supply voltage Vocc to the internal power supply voltage line Vicc, whereby the internal power supply voltage Vicc is increased.
As described above, the output level of the output circuit 112 is fed back to the differential amplifier 111, whereby the internal power supply Vicc is made constant. In this case, if there is a large delay in the feedback path of the differential amplifier 111, the output level of the output circuit 112, namely, the internal power supply voltage Vicc is brought into an oscillating state and a ripple component is superimposed onto the potential level. However, such oscillation of the output level of the output circuit is suppressed by sufficiently reducing the delay of feedback in the differential amplifier 111.
FIG. 4 is a graph showing a dependency characteristic of the internal power supply voltage Vicc generated by the internal voltage down converter shown in FIG. 3 on the external power supply voltage Vocc, as disclosed by Furuyama et al in the above-mentioned document. Referring to FIG. 4, the ordinate represents the internal power supply voltage Vicc and the abscissa represents the external power supply voltage Vocc. As seen from FIG. 4, the internal power supply voltage Vicc obtained by voltage conversion is maintained at a constant value of about 3.5 V set as the reference voltage Vref, in the range where the external power supply voltage Vocc is about 3.5 V or more. It is also seen that in the case of the external power supply voltage Vocc of 7 V, the internal power supply voltage Vicc is about 4 V.
If the semiconductor device is a memory device such as a DRAM, that is, if the function circuit in FIG. 1 includes a memory cell array, a substrate voltage generator 104 is provided in general as shown in FIG. 1. The substrate voltage generator 104 applies a prescribed negative potential to the substrate 100 if the semiconductor substrate 100 is a P type substrate. The purposes of applying such constant negative bias voltage to the P type semiconductor substrate are (1) to prevent injection of electrons into the substrate due to undershoot of a signal on a signal line, (2) to make stable the threshold voltage and operation characteristics by attenuation of the substrate effect of n channel MOS transistors, (3) to enhance the speed of operation of MOS transistors by reducing the stray capacitance involved in the junction capacitance between the substrate and an N type impurity layer, (4) to prevent generation of a parasitic MOS transistor by preventing formation of an inversion layer at an insulating film portion for element isolation (a field oxide film), (5) to prevent rise of the substrate potential due to a capacitance coupling between the power supply voltage line and the substrate, etc. The above-mentioned substrate effect is a phenomenon in which the threshold voltage and drain current etc. of an n channel MOS transistor formed on the surface of the semiconductor substrate vary according to the potential of the semiconductor substrate.
FIG. 5A shows a specific construction of a generally used substrate voltage generator. Referring to FIG. 5A, the substrate voltage generator 104 includes a ring oscillator 201 performing oscillation at a prescribed frequency, and a charge pump circuit 202 responsive to an oscillation signal from the ring oscillator 201 for injecting electrons into the semiconductor substrate and biasing the substrate at a prescribed negative potential (in the case of the semiconductor substrate of the P type). The ring oscillator 201 includes inverters I1, I2 . . . , Im cascade-connected by an odd number of stages. An output of the inverter Im of the final stage is connected to an input portion of the inverter Il of the first stage. The oscillation frequency of the ring oscillator 201 is determined mainly by the number of stages of the connected inverters, and the delay time in each of the inverters I1 to Im.
The charge pump circuit 202 includes a capacitor C1 having one electrode receiving an output signal f from the ring oscillator 201, an n channel MOS transistor NT11 having its gate and one electrode (drain) connected to the other electrode (node N20) of the capacitor C1, and the other conduction terminal connected to the ground potential Vss, and an n channel MOS transistor NT10 having one conduction terminal and a gate connected to the semiconductor substrate, and the other conduction terminal connected to the node N20. A connection point between the gate and one conduction terminal of the transistor NT10 is an output portion of the substrate bias voltage V.sub.BB. Next, operation of this substrate voltage generator will be described.
Let us now assume a case in which the threshold voltage of the MOS transistors NT10 and NT11 is Vtn, H level of the oscillation signal f is Vcc (i.e., the operation power supply voltage level), and L level is Vss. When the oscillation signal f rises to H level, a charge determined by a product of the capacitance of the capacitor C1 and the H level of the oscillation signal f is injected into the node N10 due to the capacitance coupling of the capacitor C1, whereby the potential of the node N10 rises. As a result, the transistor NT10 is brought into an off state and the transistor NT11 is brought into an on state. The increased potential of the node N20 is discharged by the transistor NT11 in the on state and the potential of the node N10 becomes equal to Vss+Vtn at the time of the first charge injecting operation.
Then, when the oscillation signal f falls to L level, the charge at the node N20 is drawn by the capacitance coupling of the capacitor C1, whereby the potential of the node N20 is lowered. At this time, the transistor NT10 is turned on and the transistor NT11 is turned off. Thus, the charge is drawn from the semiconductor substrate and the potential of the semiconductor substrate is slightly lowered.
By repeating the above-mentioned operation, the potential of the semiconductor substrate is gradually lowered by the drawal of the charge, namely, injection of electrons, and finally the potential attains the following negative potential: EQU 2.multidot.Vtn-Vcc.
Normally, the inverters I1 to Im included in the ring oscillator 201 as described above are formed by CMOS transistors (i.e., inverters including p channel MOS transistors PQ and N channel MOS transistors NQ) in the conventional structure as shown in FIG. 5B, and the external power supply voltage Vocc is used as the operation power supply voltage.
Now, the semiconductor device will be described by taking an example of a DRAM. It is possible to utilize two types of voltages, i.e., the external power supply voltage Vocc and the internal power supply voltage Vicc as the operation power supply voltage of the semiconductor device having the internal voltage down converter. Thus, either of the following voltages:
(1) the externally applied power supply voltage Vocc,
(2) the internal power supply voltage Vicc stepped-down by the internal voltage down converter can be used as the operation power supply voltage of the substrate voltage generating circuit.
A method of supplying the operation power supply voltage to the DRAM may be either of the following two methods.
A: Only a circuit of an input/output portion such as a data input/output buffer or an address buffer communicating signals with an external device is operated by the external power supply voltage Vocc, and other peripheral circuit and memory array portion are all operated by the internal power supply voltage Vicc. This is based on the following features. If the external device includes a MOS transistor operating with an operation power supply voltage of 5 V, the input/output circuit needs to input and output a signal having a swing of 5 V to 0 V, and in the internal circuit (including both the peripheral circuitry and the memory array portion), the use of the internal power supply voltage Vicc makes it possible to improve reliability and to attain a low power consumption characteristic and high-speed operability for the below described reasons.
The change amount of the internal power supply voltage Vicc is smaller than the change amount of the external power supply voltage Vocc. In addition, it is not necessary to give a large tolerance to operation timing in the semiconductor memory device. More specifically stated, the operation speed of the peripheral circuitry proportional to the driving capability of the transistor greatly depends on the power supply voltage, particularly the gate voltage. The circuit components such as the memory array and the sense amplifiers have a large load capacitance and accordingly the operation speed thereof is determined by a CR time constant of the load capacitance and the resistance, and have not so large voltage dependency as in the peripheral circuitry. Consequently, if the internal power supply voltage Vicc is used as the operation power supply voltage of the peripheral circuitry, it becomes possible to make the operation speed of the peripheral circuitry and that of the memory array portion coincide and to shorten the access time.
B: Only the memory array portion is operated by the internal power supply voltage Vicc stepped-down and other input/output circuits and peripheral circuitry are all operated by the external power supply voltage Vocc. This method is a method of designing a DRAM based on the conventionally used design method with as little change as possible. In the memory array portion, a reliability problem often occurs in memory cells due to a word line receiving the highest voltage and the drive circuit thereof, etc. and it is necessary to operate the memory array portion by the internal power supply voltage Vicc.
From the foregoing considerations, there are four combinations in the power supply voltage applying system for the DRAM and the voltage applying system for the substrate voltage generator. Discussions will be made in the following on the combinations of the respective power supply voltage applying systems.

Substrate voltage generator and method therefor in a semiconductor device having selectively activated internal stepped-down power supply voltages


An image-capturing apparatus of the present disclosure includes a focus lens, an image sensor that captures an object image formed via the focus lens and generates image data, and a controller that calculates a value relating to an in-focus position based on (i) first image data generated by the image sensor when the focus lens is at a first position and (ii) second image data generated by the image sensor when the focus lens is moved from the first position by a first moving amount and located at a second position, and the controller changing a next moving amount of the focus lens from the first moving amount based on the calculated value relating to the in-focus position.

Japanese Patent Laid-Open Publication No. 2011-15163 discloses an image-capturing apparatus that employs a system of depth From Defocus (DFD) method. This image-capturing apparatus implements a focus control that obtains plural defocusing, and includes an image-capturing device for capturing plural images defocusing differently from each other. The image-capturing apparatus then determine an object distance based on the plural images defocusing differently from each other. The image-capturing apparatus performs the focus control based on the determined object distance.

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A method of initializing a set of node addresses by using an apparatus having a CPU, a ROM and a NVSRAM for use in an electronic switching system comprises the steps of: (a) checking if there is a request to change the set of node addresses; (b) updating the NVSRAM with a new set of node addresses, and then going to step (f) if there is the request at the step (a); (c) checking if a flag in the NVSRAM is set or not when there is no request at the step (a); (d) going to the step (f) if the flag in the NVSRAM is determined to be set at the step (c); (e) copying the node addresses stored in the ROM to the NVSRAM if the flag in the NVSRAM is determined not to be set at the step (c); and (f) copying the set of node addresses stored in the NVSRAM onto the corresponding nodes.

A distributed control architecture is a state-of-the-art control architecture for use in an ESS(Electronic Switching System), wherein a number of processors performing a variety of functions are involved and practical and useful cooperations between the processors are achieved by using a so-called IPC(Inter-Processor Communications) network.
For an efficient inter-processor communications system based on the IPC network, there are employed nodes at some intermediate points of the IPC network in order to route and arbitrate a data flow between the processors. To each of the nodes, an independent and unique node address is assigned. Whenever the ESS is turned on, an initialization of the node address is required: that is, the assigned address must be stored at an address register residing therein upon turning on the ESS.
In FIG. 1, there is illustrated a conventional node address initialization apparatus which is capable of initializing a single node address. In FIG. 1, the conventional node address initialization apparatus comprises a set of jumper straps 10 and a buffer 11, wherein the number of the jumper straps depends on the word size of the node address and the buffer is connected to the address register residing in each node. One side of each jumper strap is grounded and the other side thereof is connected to the buffer and a voltage source Vcc of, e.g., 5 V, via a pull-up resistor.
If the jumper strap is bridged, 0 V or a logic "0" is inputted to the buffer; otherwise, 5 V or a logic "1" is inputted to the buffer. If the ESS is turned on, a node address word formed by manipulating the jumper straps is stored in the buffer. Then, the node address in the buffer is transferred to the address register 12 at the node. Since the conventional node address initialization apparatus shown in FIG. 1 can initialize only a single node, there are needed as many node address initialization apparatus as the number of nodes involved therein to accomplish the initialization process, thereby making the apparatus complex and costly.
There are other drawbacks in the conventional node address initialization apparatus: for instance, the node address must be manually and individually assigned to every node involved; and, it is difficult to realize a high integrity node board due to the non-electronic nature of the jumper straps; and, furthermore, an alteration of the node addresses cannot be performed while the ESS is in operation.

Method and apparatus for communication node address initialization by using NVSRAM


The invention relates to an insoluble anode for electrolytic plating, the insoluble anode having two or more phases comprising an anode base body and a screen wherein the anode base body of steel, stainless steel, nickel, nickel alloy, cobalt, and cobalt alloy.

Electrolytic plating methods, for example copper-plating, nickel-plating, cobalt and cobalt alloy-plating, zincing, or tinning, are carried out by means of soluble or insoluble anodes. When soluble anodes, also known as active anode systems, are used in an electrolytic plating operation, the anode dissolves during plating. The anode comprises a salt of the metal ion being plated. Accordingly, a balance between the dissolution of the soluble anode during plating to yield additional metal ion in the plating bath and metal ion reduction at the cathode allows for careful control of a steady state concentration of metal ion in solution. Insoluble anodes, also referred to as inert anode systems, do not dissolve during the electrolysis because insoluble anodes are constituted of an inert material. Typically, insoluble anodes comprise a carrier material coated with an active layer material. Typical carrier materials, including titanium, niobium, stainless steel, and other inert metals such as valve metals, become passive, i.e., non-corroding, under electrolysis conditions. Typical active layer materials, which are electron-conductive materials, include platinum, iridium, ruthenium, other precious metals, mixed oxides thereof, or compounds of these elements. Herein, the active layer can either be directly applied on the surface of the carrier material or can be placed on a substrate, which is spaced with respect to the carrier material. Substrate materials include the same types of materials appropriate for use as carrier materials, for example stainless steel, titanium, and the like.
Generally, electrolytic plating can be carried out by means of direct-current, pulse current, or pulse reverse current.
Additives are typically added to electrolytic plating baths, which additives act, for example, as brighteners, to increase the deposit hardness and/or the dispersion. Herein, organic compounds are preferably used as additives.
During the electrolytic plating operation, gases, for example oxygen or chlorine, are generated at the insoluble anode. These gases can oxidize organic additives contained in the electrolytic plating bath, which can lead to partial or even complete decomposition of these additives. Decomposition of the organic additives is disadvantageous for at least a couple reasons. First, the additives have to be periodically replenished. Second, degradation products of the additives cause disturbances, such that it becomes necessary to frequently renew or purify or regenerate the electrolytic plating baths, which is neither economically nor ecologically reasonable.
EP 1 102 875 B1 discloses a method for inhibiting organic additive oxidation in an alkaline electrolytic plating bath by separating the anode from the cathode with an ion exchanger membrane. This design has the advantage that organic compounds are isolated from the anode, which effectively prevents oxidation of the additives. However, this design requires more instrumentation, since the electrolytic plating bath requires a closed box with an anolyte around the anode and a catolyte around the cathode. Additionally, a higher voltage is required, which questions the economic efficiency of the design. Importantly, the structural solution proposed by EP 1 102 875 B1 is not applicable to every anode-cathode geometry, such as for coating the interior of tubes.
DE 102 61 493 A1 discloses an anode for electrolytic plating, which comprises an anode base body and a screen. The anode base body comprises a carrier material and a substrate having an active layer. The screen of the anode base body is located at a fixed distance from the anode base body and reduces the mass transport towards the anode base body and away from it. In contrast to the design according to EP 1 102 875 B1, the use of such an anode requires less instrumentation and also has the advantage that the additives contained in the electrolytic plating bath do not oxidize to such a high extent.
However, the anode described in DE 102 61 493 A1 is expensive. The anode base body of the anode is formed by combining two parts, and the fabrication process is both effort-intensive and expensive. The anode base body comprises a carrier material and an active layer. Titanium is typically used as carrier material. The active layer, however, comprises expensive noble materials such as platinum, iridium, mixed oxides of platinum metals, and diamonds. The anode described in DE 102 61 493 A1 is comparatively expensive, whereby the economic efficiency of an electrolytic plating method using such an anode is doubtful.


A display for displaying an image to a viewer, capable of highlighting specific locations selected by a user. This display comprises:                a) a punchable layer such as a foam board having a first surface and a second surface,        b) an image affixed to the first surface of the punchable layer. The punchable layer and the image form a sandwich dubbed display cover which is partially transparent and is observed by a viewer located on the image side of the display cover,        c) a light source illuminating the second surface of the punchable layer,        d) a piercing means for enabling the user to punch at least one hole into the punchable layer, and        e) a plurality of pegs equal in number to the number of holes. The pegs are longer than the thickness of the display cover and furthermore are significantly more translucent than the display cover, such that when inserted into the holes by the user, they operate as light pipes and channel light generated by the light source, across the display cover, and scatter light toward the viewer, thereby allowing the pegs to operate as highlighters over the lesser illuminated display cover.

Backlit static displays are well known devices that have been used in a wide diversity of applications. These devices, which typically comprise a translucent slide placed in front of a light source, provide a uniform rendition of the image on the slide. While useful, devices as described in the prior art do not offer the opportunity for highlighting locations of interest by allowing the user or viewer to increase or decrease at will the transparency of the slide at those locations.
A device capable of displaying a backlit image with a controllable degree of transparency is described in U.S. Pat. No. 6,032,393. It comprises a peg board mounted in front of a polarized light source. The peg board is a rectangular array of equally spaced holes into which translucent pegs can be inserted. The distribution of pegs in the array and their orientation with respect the angle of polarization can give rise to interesting colored light patterns. These patterns however, are limited to the discrete combinations of peg placements in the regularly spaced holes. In addition, this device does not give the user the opportunity to superimpose an image on the light pattern generated by the pegs.
Further features, aspects, and advantages of the present invention over the prior art will be more fully understood when considered with respect to the following detailed description claims and accompanying drawings.

Backlit static display on foam board using light piping pegs as highlighters


An antenna set includes a first antenna, a second antenna, and a neutralized line. Each of the first antenna and the second antenna has a low frequency resonant path and a high frequency resonant path. The neutralized line is couple to the low frequency resonant path of the first antenna and the low frequency resonant path of the second antenna. The low frequency resonant path of the first antenna and the low frequency resonant path of the second antenna correspond to a first frequency band, the high frequency resonant path of the first antenna and the high frequency resonant path of the second antenna correspond to a second frequency band, and the two low frequency resonant paths do not overlap the two high frequency resonant paths.

a. Field of the Invention
The invention relates to an antenna set and an isolation enhancement method for use with different systems having dual-band antennas, where the dual-band antennas achieve high isolation when the different systems operate in an identical frequency band.
b. Description of the Related Art
An antenna is a key component for wireless communications systems. Because significant progress has been made on multiple entry/exit systems and integrated access devices, the number of antennas provided for a single apparatus is increased by several times to result in antenna coupling effects and thus reduce radiation efficiency. Besides, signal interference among different antenna systems may occur, and the signal interference is particularly severe when different antenna systems operate in an identical frequency band. Accordingly, it is desirable to design an antenna system confined in a limited space to have high radiation efficiency and isolation, which is the main subject of the invention.
In conventional wireless communications systems, communication bands of 2.4 GHz-2.5 GHz and 5.15 GHz-5.85 GHz are reserved for a wireless communication protocol 802.11ac for faster communications; however, these communication bands are open, and the communication band of 2.4 GHz-2.5 GHz is also available to other wireless communication interfaces such as blue tooth, cell phone, etc.
As illustrated in FIG. 1, a conventional dual-band antenna set 100 includes a first dual-band antenna 101 and a second dual-band antenna 102 that are the same in structure and characteristic.
In case the right-side second dual-band antenna 102 serves as a excitation source, an induced electric field may be formed to influence the left-side first dual-band antenna 101. Note since a low-frequency band of 2.4-2.5 GHz is in open use, the first dual-band antenna 101 is influenced by resonance effects induced by the second dual-band antenna 102 when the antennas 101 and 102 operate in an identical frequency band. The distribution of dense hatched areas illustrated in FIG. 1 indicates low-frequency signal interference is more significant when the antennas 101 and 102 operate in an identical frequency band.
Because the separation provided by passive elements such as filters fails to resolve the signal interference occurs in an identical frequency band, the amount of coupling between antennas is reduced to decrease the signal interference caused by other system operating in the same frequency band. Accordingly, it is highly desirable to provide an antenna system with high antenna isolation and improved radiation efficiency.

Dualband antenna with isolation enhanced and method thereof


Drying of wet ground surfaces provided with stalks includes removing droplets from stalks with comb-shaped slitted, cubical or squared projections provided on an underside of a broad plank, and guiding the removed droplets along the slitted, cubical or squared projections toward lower edges of the slitted, cubical or squared projections and from there onto the ground surface.

The present invention deals with a method of and a device for drying wet ground surfaces with stalks, in particular lawn surfaces. Also, similar structured artificial ground surfaces can be considered suitable for the inventive solution.
Such ground surfaces are frequently wet in the early morning hours from dew and at all times from rain or from required artificial watering. People must frequently walk over these ground surfaces, and as a result footwear becomes wet. When the ground surfaces are used for sports or as playing grounds for kids, not only the footwear but also the clothes become wet. Moreover, such ground surfaces are smooth and therefore become dangerous, first of all when used for sports which involve a fast running. Falls and injuries hinder and endanger a sportsman, unless he must not use few hours for performing the sports activities. For a natural lawn surface which is wet and must be mowed in this condition, considerable difficulties arise during mowing, and in particular during mowing with such lawn mowers which collect the cut grass in an accumulating device. In these cases the passages for guiding the grass are clogged by the cut grass stalks which due to their moisture stick to one another and to the walls of the lawn mower and first of all block its expelling opening. The mowing process must be continuously interrupted for removal of the clogging grass. Moreover, a great part of the cut grass is not collected in the accumulating device but instead remains on the lawn surface and must be removed in a second working step.

Method of and device for drying grass surfaces


To increase a measurement range of a measurement system taking measurement samples of an object moving with respect to said measurement system, the measurement system is configured to take measurement samples at different sample positions while the object accelerates with respect to the measurement system. In particular, a measurement timing for taking samples is determined corresponding to a selected acceleration and velocity of the object as a function of time with respect to the measurement system.

A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. including part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Conventional lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at once, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the "scanning"-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
Before exposure of the substrate to transfer the pattern onto the substrate, a height level of the substrate may be determined and mapped. A resulting height map of the substrate may be employed to position the substrate with respect to a projection system, for example.
In a conventional lithographic apparatus, the height map may be generated by sampling the height of the substrate at predetermined equidistant positions, e.g. positions lying on a rectangular measurement grid. A height level sensor and the substrate may be moved with respect to each other along a trajectory, which trajectory is selected along the predetermined positions. In the conventional lithographic apparatus, the measurement samples are taken while the substrate and the height level sensor move with respect to each other at a constant velocity. Thus, the height level sensor samples the equidistant measurement positions by sampling at a constant sampling rate. It is noted that in the measuring process the substrate or the height level sensor or both may move.
Before reaching a constant velocity a moving part, e.g. the substrate, first needs to accelerate. While accelerating, no samples are taken. The acceleration is performed over a run-in distance, i.e. a first part of a measurement trajectory. Over the run-in distance, to obtain a full map of the substrate, the height level sensor and the substrate are not positioned with respect to each other such that samples may be taken, i.e. the run-in distance may be positioned outside a substrate measurement area. In a second part of the measurement trajectory, the velocity may be constant. The second part of the measurement trajectory is positioned in the substrate measurement area such that the height level sensor may take samples at the predetermined positions. Next, during a third part of the measurement trajectory positioned outside the substrate measurement area, no samples are taken and the moving part, e.g. the substrate, may decelerate. The above-described sampling method, i.e. accelerating; sampling, while moving at a constant velocity; and decelerating, may be repeated, until a sample has been taken at every predetermined position.
In the above-described method, a run-in distance may be required to reach a predetermined constant velocity before sampling. The moving part needs to move over a moving distance that is larger than a required sampling distance. To decrease a measurement time period, a higher measurement velocity may be required. For a higher measurement velocity, however, a larger run-in distance may be required and therefore the moving distance should be larger. Such a larger moving distance may require additional space in the apparatus, and may require additional time for the completion of the measuring process.

Measurement method, device manufacturing method and lithographic apparatus


A group robot and a method for controlling a collective movement of a group robot that realize a combination of autonomous distributed control and centralized control according to the environment are provided. A group robot is formed of at least two robots that have powers and autonomously move obtains mutual position information among the robots and with respect to an object that exists in a movable area of the robots, presets a virtual object temperature for the object and a virtual initial robot temperature that is lower than the virtual object temperature for the robot, calculates a virtual robot temperature, which changed by a virtual heat transfer, from the virtual object temperature, the virtual initial robot temperature, and a distance between the robot and the object, calculates virtual attractive-repulsive force from a distance between the robots to keep the distance between the robots and virtual repulsive force acting between the object and the robot from a virtual robot temperature by using a thermodynamics mathematical model, and controls a movement direction and velocity of the robot by using a sum of the virtual attractive-repulsive force and the virtual repulsive force.

A multi-robot system formed by a number of robots to work as a group is expected to have many applications such as transportation of objects, monitoring of construction sites and the like by using the property as a group and an individual.
In order to realize the multi-robot system, it is necessary to have a control system that had been fully considered its routes, existence of objects, width of its routes and the like in operation environments.
For example, a method in which state variables of only one robot constitute MARCOV state space used for machine learning (see patent literature 1), a method for regulating relationship between robots that constitute a group robot (see patent literature 2 and nonpatent literature 1), a method for controlling a multi-robot movement by using a method that incorporates molecular dynamics method and hydrodynamic property into a robot movement, and the like had been proposed.

Group robot and collective movement controlling method for group robot


A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III–V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.

The present invention generally relates to semiconductor materials and to a method of reducing the propagation of threading dislocations from plastic deformation in mismatched epitaxial layers into active areas of optoelectronic devices and, more particularly, to a method for reducing the propagation of such dislocations for solar energy conversion and other photovoltaic devices.
The interest in photovoltaic (PV) cells in both terrestrial and non-terrestrial applications continues as concerns over pollution and limited resources increases. Irrespective of the application, and as with any energy generation system, efforts have been ongoing to increase the output and/or increase the efficiency of PV cells. To increase the electrical power output of such cells, multiple subcells comprising layers having different energy band gaps have been stacked so that each subcell or layer can absorb a different part of the wide energy distribution in the sunlight. This situation is advantageous, since each photon absorbed in a subcell corresponds to one unit of charge that is collected at the subcell operating voltage, which is approximately linearly dependent on the band gap of the semiconductor material of the subcell. An ideally efficient solar cell would have a large number of subcells, each absorbing only photons of energy negligibly greater than its band gap.
Many optoelectronic devices are formed by thin film epitaxial growth of III–V compound semiconductors upon a mechanical substrate. This substrate—typically of GaAs, InP, Ge or other bulk material—acts as an atomic template for the formation of the epitaxial layers. The atomic spacing or lattice constant in the epitaxial layers is typically fixed by that of the substrate.
Devices are formed only at or near the lattice constant of an available substrate material. FIG. 1 shows the band gap of binary materials connected by lines of ternary alloys (e.g., InGaAs is a line between GaAs and InAs), as well as showing the lattice constants for most common substrate materials. A basic problem is that devices are optimal for applications in regions of band gap where there is no available substrate. For example, the theoretically most efficient solar cells are composed of alloys with band gaps that have lattice constants between GaAs and InP substrates. A similar dilemma continues to most optoelectronic devices—such as lasers, LEDs, HBTs, and others—where the most suitable band gaps are not the ones easily available near a lattice constant of an available substrate.
Another restriction this imposes is in the cost of the available substrates for a given device. For example, InP is available, but is very costly and may make certain optoelectronic designs too expensive to be commercially practical. There are two main approaches to overcoming this restriction. One approach is to grow layers that are lattice-mismatched to the substrate, but are thin enough that they are fully-strained, i.e., unrelaxed. Such layers are known as pseudomorphic layers. In such layers, the band gap and other properties may be adjusted by virtue of the ability to alter the lattice constant and semiconductor composition, as well as by the strain state of the pseudomorphic layers, thereby allowing the device performance to be improved. But the thickness of these layers that can be grown before plastic deformation occurs is typically limited. A second approach is to grow an inactive buffer that is completely or nearly completely relaxed, and then growing the rest of the device on top of this layer as if it were a substrate with a new lattice constant. These layers which transition from the lattice constant of the growth substrate to a new lattice constant upon which strain-free layers can be grown are known as metamorphic layers. In general, devices grown with such intentionally relaxed layers are known as metamorphic devices.
Pseudomorphic layers are routinely used in optoelectronics to enhance performance in all device types. The device designs are limited to layers where no relaxation or limited relaxation has occurred and thus limited to certain amounts of strain and thickness. That strain and thickness relationship is typically dictated by the Matthews-Blakeslee relationship (described in Matthews, J. W. and Blakeslee, A. E.: "Defects in epitaxial multilayers, I. Misfit dislocations", J. Crystal Growth, 1974, 27, pp. 118–125 and incorporated herein by reference) which describes the equilibrium thickness, which may be exceeded depending on kinetics. In the Matthews-Blakeslee model, dislocation formation occurs when an epilayer exceeds a critical strain energy density. Once formed, dislocations move as an atomic level crack through the remaining epitaxial layers in a form known as a threading dislocation. When plastic deformation occurs, it may occur to a limited degree (partial relaxation) or completely (total relaxation). Both are generally termed as "metamorphic" layers.
In epitaxy, when a layer relaxes, it does so by forming edge dislocations at the boundary between the strained layer and the substrate. The conventional view of the process is called the dislocation glide model. As the thickness of the growing mismatched layer increases, the surface strain increases. When the strain energy reaches a critical value, the layer begins to relax by forming a loop or ½ loop made up of two threading dislocation segments and an edge dislocation segment at the free surface of the strained layer. In vapor-phase epitaxy, this free surface is the growth front or solid-vapor interface. The loop then propagates the edge dislocation to the strain layer/unstrained layer interface where the edge segment stops. The threading segments extend from that interface to the free surface. Continued growth of the mismatched layer builds additional strain. Simultaneously, the additional strain may be relieved by the extension of the existing edge segments or by the formation of more dislocation loops. Once formed, the threading dislocations then propagate throughout the rest of the growth layers, whether the layers exceed the critical strain energy or not. In other words, the defects become a permanent feature of the upper epitaxial layers. Understanding how to control this relaxation and the limitation it presents is essential in growing mismatched epitaxial layers.
The density of edge-dislocations required for 100% relaxation at the strain layer/unstrained layer interface is determined by the difference in lattice constant of the two layers. The number or density of loops is a kinetic or rate problem. The final threading dislocation density generated is determined by the balance between the extension of existing dislocation loops and the nucleation of new loops. One may extend the thickness and/or strain of a pseudomorphic mismatched layer beyond that described by the Matthews-Blakeslee limit by slowing down this rate of loop formation.
The presence of threading dislocations in the active regions of a device may act as a loss mechanism, degrading the performance of the device. Unbonded atoms at threading dislocations act as recombination centers reducing the minority-carrier lifetime in the device active regions. This is especially true for devices where minority carrier lifetime is important such as photovoltaic (PV) cells, laser diodes (LDs), light emitting diodes (LEDs), and heterojunction bipolar transistors (HBTs). The need for low recombination rates in such devices usually necessitates that these devices be grown at lattice-matched conditions. However, if the layer is thin enough, no dislocations are formed. This thickness requirement restricts the usefulness of intentionally engineering the strain within a given device to near atomic layer dimensions for large strains. Alternatively, for thicker epitaxial structures required for entire devices, the mismatch in lattice constant must be very small. Typically, the inplane strain, ε∥, is limited by ε∥<0.1%, where ε∥ is of a mismatched epitaxial layer defined by ε=|alayer−asubstate|/alayer, and where alayer and asubstate are unstrained lattice constants of the layer and substrate, respectively.
One may attack the problem of strained, mismatched active device layers by controlling the growth conditions and composition to keep the designed layers below the strain and thickness parameters. As stated above, this limits the available alloys and thicknesses for device designs and may be highly disadvantageous for device performance. The other extreme in this problem is to intentionally form 100% relaxed layers, but confine the relaxation to inactive regions of the device. This method is the metamorphic buffer layer approach. In this method, layers are grown in a manner that "forces" relaxation to occur, such as growing at large mismatches and thicknesses. The remaining layers are grown lattice-matched to this new lattice constant. The drawback to this method is that forcing the relaxation to occur typically leads to large densities of threading dislocations in the remaining layers, which then propagate into the upper, active regions of the device, lowering performance of any device grown on top of it. Many methods of prior art exist in attempting to control the density of dislocations in the active regions of metamorphic devices.
general method that has been found to minimize the threading dislocation density in a metamorphic device is to grow a buffer layer with a graded lattice constant. The strain at the surface during growth may be kept less than one percent with respect to the already relaxed portion of the grade. This low strain typically produces relaxation by the dislocation glide mechanism rather than the three-dimensional islanding often seen at high strains. Minimization of threading dislocation density is a complicated optimization process as evidenced by Fitzgerald et al in U.S. patent application Ser. No. US2001/0040244. The rates of dislocation glide, dislocation pinning and dislocation nucleation are all dependent on the chosen process parameters. The rates generally increase with temperature, but it is the competition between them which determines the result. Thus, process design to obtain low dislocation density is not straight forward. Other design parameters such as heavy (>˜1018 cm−3) n-type doping may affect the structure by hardening the material, hindering both dislocation glide and possibly nucleation.
Multijunction photovoltaic cells are a specific category of optoelectronic devices that would benefit strongly from the freedom to choose semiconductor band gaps for its constituent layers, independent of the band gaps of semiconductor compositions that can readily be grown on available growth substrates such as Ge, GaAs, InP, Si, and GaSb. Lattice-matched 2-junction GaInP/GaAs solar cells [Olson, U.S. Pat. No. 4,667,059; Olson and Kurtz, U.S. Pat. No. 5,223,043] and 3-junction GaInP/GaInAs/Ge solar cells [King et al., "High-Efficiency Space and Terrestrial Multijunction Solar Cells Through Bandgap Control in Cell Structures," Proc. 29th IEEE Photovoltaic Specialists Conf., May 20–24, 2002] have been described in the literature. Lattice-mismatched 2-junction GaInP/GaInAs/GaAs cells [Dimroth et al., "25.5% Efficient Ga0.35In0.65P/Ga0.83In0.17As Tandem Solar Cells Grown on GaAs Substrates," IEEE Electron Device Lett., Vol. 21, p. 209 (2000)] and lattice-mismatched 3-junction GaInP/GaInAs/Ge solar cells [King et al., "Metamorphic GaInP/GaInAs/Ge Solar Cells," Proc. 28th IEEE Photovoltaic Specialists Conf. (IEEE, New York, 2000), p. 982] have also been described. Additionally, lattice-mismatched multijunction cells with III–V subcells combined with an active silicon substrate, such as 3-junction GaInP/GaInPAs/Si cells; transparent, graded buffer layers such as GaPAs or GaInP to transition from the substrate lattice constant to the device lattice constant in such cells; and multiple graded buffer layers placed between upper and lower subcells, as well as between substrate and lower subcells, to provide maximum flexibility in subcell lattice constant and band gap, are also described in the literature [King et al., U.S. Pat. No. 6,340,788]. All of the above lattice-mismatched multifunction photovoltaic cell designs have a need for, and would benefit from, a structure or method which inhibits propagation of dislocations from the metamorphic (lattice-transitioning) layers into the active regions of the device, since these dislocations act to reduce minority-carrier lifetime, and thereby reduce photovoltaic cell performance.
In the case of 2- or 3-junction (2J or 3J) GaInP/GaInAs/Ge solar cells, the entire epitaxial stack is typically grown at or near lattice-matched conditions with respect to the Ge substrate. In terms of the epitaxial materials, this means limiting the indium content to approximately 1 atomic percent in the GaInAs layers and keeping the indium content of the GaInP layers to near 49.5 atomic percent, +/−1 percent. Since the epitaxial layers are much thicker than the critical thickness for threading dislocation formation, strong deviation from these alloy concentrations leads to losses of open circuit voltage (Voc), voltage at maximum power (Vmp), fill factor, and hence, of efficiency. However, the band gaps of GaInAs and GaInP grown lattice-matched to a Ge (or GaAs) substrate are not exactly tuned to the solar spectrum to produce the most efficient device possible. If GaInAs and GaInP can be grown at a different lattice constant than that of the Ge substrate, thereby modifying the GaInAs and GaInP subcell bandgaps, the photovoltaic conversion of the space and terrestrial solar spectra is theoretically much more efficient. The maximum theoretical AMO efficiency for GaInP/GaInAs/Ge triple-junction solar cells in which the top and middle subcells are lattice-matched to each other is approximately 38%, attained at a GaInAs middle cell indium content of 12%, i.e., a Ga0.40In0.60P/Ga0.88In0.12As/Ge triple-junction solar cell. These intentionally lattice-mismatched devices are categorized as metamorphic photovoltaics. These mismatched structures are considerably less mismatched than the structures of other metamorphic InGaAs devices. The demands for structural perfection in minority-carrier devices such as solar cells are higher than those for most other devices.
Solar cell device performance is a good indicator of relative defect density in the epitaxial layers. The open circuit voltage (Voc) is determined by the minority-carrier lifetime through the relationship:
      V    oc    =            nkT      q                  ln                    (                                            J              sc                                      J              sat                                +          1                )            where k is the Boltzmann constant, T is the temperature, q is the electronic charge, Jsc is the short circuit current density, n is the diode ideality factor, and Jsat is the saturation current density of the diode which depends directly on the minority-carrier lifetime. Since the minority-carrier lifetime depends strongly on the relative defect density, so will the open-circuit voltage. Similar relations follow for other device parameters such as fill factor (FF), and short circuit current (Jsc). Small changes in open-circuit voltage result from an exponential change in defect density. Qualitatively, an increase in dislocation density decreases all of the basic solar cell parameters in illuminated current-voltage (I–V) measurements: Voc, FF, and Jsc.
Previous research into middle-cell-active-only Ga0.88In0 12As epitaxial layers grown on a relaxed buffer layer graded from the Ge lattice constant to that of the middle cell has shown that the best performing devices lose 200 mV of voltage as compared to the lattice-matched cells. Only 100 mV of loss is expected due to the reduction of band gap due to the increased indium. Additionally, the cells lose fill factor as well. These effects demonstrate the losses in performance due to recombination in threading dislocations propagating into the middle cell from the relaxed GaInAs buffer layer. Overall, these losses combine to limit the performance of full 3J metamorphic devices to approximately 27 to 28 percent efficient, much less than the theoretical predictions for no-loss devices.
There has been considerable interest in the growth of highly mismatched epilayers in both the SiGe and III–V material systems. Typical attempts to grow highly strained epilayers result in a transition to three-dimensional growth "islanding" after a few monolayers soon after exceeding the Matthews-Blakeslee thickness.
A method of avoiding this "islanding" in the system of Ge on a Si substrate has been discovered by Copel et al., U.S. Pat. No. 5,628,834. They show the use of dopants in Ge and Si such as arsenic or antimony, which act as surfactants, to maintain two-dimensional growth of highly strained Ge/Si structures at temperatures between 400 and 700° C., with greater layer thicknesses than possible by other methods. However, Copel et al. use surfactants in the system of Ge on a Si substrate where the Ge layer exceeds 3 to 6 monolayers. Accordingly, the process by Copel et al. is used for extremely lattice-mismatched layers where large strains cause a transition to islanding growth. But there is no suggested application to significantly different material systems or to layers with small strains to maintain pseudomorphic layers and control plastic extended-line defect nucleation.
In III–V semiconductor growth, dopants have been used as surfactants in work performed by Massies et al. "Surfactant mediated epitaxial growth of InxGa1−xAs on GaAs (001)," Appl. Phys. Lett., Vol. 61 (1992) p. 99, where tellurium , an n-type dopant in III–V semiconductors, was added to InGaAs to extend the critical thickness of the epitaxial layers. Tellurium has been seen as the analog in III–V systems to the antimony used in the group-IV SiGe system, since they are both n-type dopants in these respective semiconductor systems, which interact strongly with the surface. Both also strongly segregate at the growing surface of growing films. This analogy was reinforced by the failure of tin, an isoelectronic element in group-IV systems, which segregates on the growing surface of Si to suppress islanding in the SiGe system.
In a variation of this method, U.S. Pat. No. 6,139,629 to Kisielowski et al. disclose the use of bismuth and similar group-V atoms to reduce the growth temperature for high-quality group-III/nitride (III-N) semiconductors. As disclosed, bismuth acts to reduce the onset of islanding growth in III-N epitaxy at reduced growth temperatures. Again, however, there is no suggested application to small strains to maintain pseudomorphic layers and control plastic extended-line defect nucleation. A similar idea of using an isoelectronic surfactant to extend the two-dimensional growth regime of III–V semiconductors has been used in extending the strain in InGaAs and InGaAsN quantum wells for laser diodes by Shimizu et al. in "1.2 μm Range GaInAs SQW Lasers Using Sb as Surfactant," Electron Dev. Lett., Vol. 36, (2000) p. 1379, and references therein. However, the authors never offer that an isoelectronic surfactant changes the dislocation kinetics. In other words, they do not teach the application of this work to metamorphic, relaxed epitaxial layers. They only deal directly in applying the idea to create highly strained, unrelaxed layers. Their principal observation is that the Sb suppresses the transition to three-dimensional growth.
Another attempt to minimize threading dislocations is shown by Liu et al., "High-quality Ge films on Si substrates using Sb surfactant-mediated graded SiGe buffers," Appl. Phys. Lett., Vol. 79, No. 21, 19 Nov. 2001 (3431). The graded SiGe films were grown at about 500° C., and Sb was used as an n-type dopant surfactant. Conditions were expected to result in a highly n-doped SiGe buffer. Liu et al., however, did not suggest applying the process beyond their IV—IV material system to other material systems, such as a III–V material system. Their explanation of the effect is that the n-type surfactant aids the motion of the misfit dislocations. They did not suggest that any surfactant would have an impact upon the dislocation nucleation kinetics.
An excellent overview of the current state of the art of processes to maintain a low threading location density and relaxed growth template in III–V semiconductors by fabrication of relaxed InGaAs buffers on GaAs substrates is disclosed in U.S. patent application Ser. No. US2001/0040244 to Fitzgerald. The disclosed process utilizes metalorganic chemical vapor deposition (MOCVD) to grow the relaxed graded layers at a temperature ranging upwards from about 600° C. However, Fitzgerald does not suggest the use of surfactants (e.g., Te) for n-type doping even though the disclosure follows after Copel et. al. and Liu et. al. which teach the use of surfactant doping. A similar discussion of the growth of InGaP/GaP alloys is given in is given in Kim and Fitzgerald US2001/0047751.
As can be seen, there is a need for a method of reducing the propagation of threading dislocations from plastic deformation in mismatched epitaxial layers into active areas of optoelectronic devices, particularly III–V devices. Such a method preferably can be applied to improve the performance of devices utilizing metamorphic layers. Further, such a method preferably can be applied to reduce substrate costs by improving the performance of lattice-matched layers upon poorer quality or less expensive substrates.

This patent is subject to a terminal disclaimer.

Isoelectronic surfactant suppression of threading dislocations in metamorphic epitaxial layers


A system is described for providing communication services and this system comprises a communication network with a number of exchanges and a number of connection points. Each connection point is connected by a fixed line to an exchange and is adapted to connect at least one communication terminal to the corresponding exchange. First connection points of the number of connection points are in an operative state and second connection points of the number of connection points are in an inoperative state. Operative connection points allow a communication terminal connected thereto access to at least one communication service through the system by having been assigned a unique address from a first group of unique addresses to each of the operative connection points. The inoperative state of the second connection points includes a standby state and the exchanges are adapted to recognize the standby state of an inoperative connection point used by a communication terminal to access the system and to allow the communication terminal connected to this inoperative connection point access to a transaction server through the corresponding exchange. The transaction server is adapted to switch an inoperative connection point into the operative state by assigning a unique address from the first group of unique addresses to this inoperative connection point so that the inoperative connection point is changed into an operative connection point.

1. Field of the Invention
The invention relates to a system for providing communication services, comprising a communication network with a number of exchanges and a number of connection points, each connection point being connected by a fixed line to an exchange and being adapted to connect at least one communication terminal to the corresponding exchange, wherein first connection points of said number of connection points are in an operative state and second connection points of said number of connection points are in an inoperative state, wherein operative connection points allow a communication terminal connected thereto access to at least one communication service through said system by having been assigned a unique address from a first group of unique addresses to each of the operative connection points.
2. Description of the Prior Art
An example of such a system is a fixed line telephone network, wherein telephone terminals connected to the first connection points allow subscribers to call other subscribers connected through first connection points to the same telephone network or to other telephone networks interconnected to the first telephone network.
In order to switch a second connection point from the inoperative to the operative state, the operator of the telephone network has to determine through his network administrative system which of the large number of fixed lines connected to the corresponding exchange is connected to the second connection point to be switched to the operative state. This operation is complex and time consuming. Moreover, in particular at locations with a large number of connection points this operation easily leads to errors in the selection of the fixed line of the connection point to be switched into the operative state.

System for providing communication services


A multiuser, collaborative augmented reality (AR) system employs individual AR devices for viewing real-world anchors, that is, physical models that are recognizable to the camera and image processing module of the AR device. To mitigate ambiguous configurations when used in the collaborative mode, each anchor is registered with a server to ensure that only uniquely recognizable anchors are simultaneously active at a particular location. The system permits collaborative AR to span multiple sites, by associating a portal with an anchor at each site. Using the location of their corresponding AR device as a proxy for their position, AR renditions of the other participating users are provided. This AR system is particularly well suited for games.

Augmented reality (AR) toys have been introduced. The basic hardware required, an AR device, is a smartphone, laptop, tablet computer, dedicated device, or the like, that views the real world with a camera, and displays that view on a display to a user. Additionally, the AR device runs software that recognizes certain objects (herein termed "anchors") in the camera's field of view, including the anchor's apparent distance and orientation relative to the camera, and then augments the image from the camera with computer generated graphics that seem to appear in, on, or near the anchor. The resulting modified image is displayed to the user (often, a game player, in which case, the AR device may also be executing game code).
An example of such toys include a line of jigsaw puzzles, by Ravensburger AG of Ravensburg, Germany which when viewed with the corresponding AR app on an smartphone or tables replaces a portion of the puzzle with animated figures. Another one is called "AR Games" by Nintendo Co., Ltd. of Kyoto, Japan, which provides preprinted paper cards as anchors and plays on their Nintendo 3DS handheld gaming system. The Eclipse AR Card Game by MoOn-Studio of also uses preprinted cards as anchors, and allows two players to interact by manipulating the cards, however the two players share a single camera, and display attached to a personal computer provides the same view to both players.

Collaborative augmented reality presentation method