A backlight unit with high heat transfer rate disposed under a display panel. The backlight unit includes a light source generator for generating light beams, a diffusing plate positioned between the light source generator and the display panel for scattering the light beams to the display panel, and a reflecting sheet position under the light source generator for reflecting the light beams upward. The reflecting sheet has at least one opening for increasing the heat transfer rate of the backlight unit.

1. Field of the Invention
The present invention relates to a back light unit of a display panel, and more particularly, a back light unit having a high heat transfer rate.
2. Description of the Prior Art
A back light unit, which is a key element in the fabrication of liquid crystal displays, is widely used in digital cameras, PDAs, vehicle satellite navigation systems, computer monitors, flat panel TVs, and so on. Typically, a back light unit, which is generally installed underneath a display panel, comprises a light source (or multiple light sources) and a light diffusion plates for providing users with diffused and uniform light beams. Light beams penetrate the overlying display panel and form various images controlled by pixel electrodes densely arranged on the display panel. Back light units are typically divided into two major categories: direct-type, in which the light source is generated form underneath the display panel directly, and edge light type, in which the light source generator is located adjacent to the edge of the display panel. The direct-type backlight unit can provide higher intensity of light and is thus more suited for large size display panels such as computer monitors and TV panels than the edge light type.
Please refer to FIG. 1 of a cross-sectional view of a conventional back light unit 10. The back light unit 10 is installed underneath a display panel 12 and comprises a light source generator 14, a diffusing plate 16 interposed between the light source generator 14 and the display panel 12, and a reflecting sheet 18 disposed under the light source generator 14 and fixed on a housing 20. The light source generator 14 is used to provide a light source to the display panel 12. The reflection plate 18 is used to reflect light generated by the light source generator 14 upward to the overlying diffusing plate 16, thereby increasing light use efficiency of the back light unit 10 and obtaining a better brightness output. The diffusing plate 16 is used to diffuse light (or reflected light) by means of shielding, scattering, or refraction so as to provide a uniform light to the display panel 12. The housing 20, which is disposed beneath the reflecting sheet 18 and surrounding the reflecting sheet 18, is used to fix the diffusing plate 16, the reflecting sheet 18, and the light source generator 14. In addition, a diffusing sheet 22 and an optic focusing film 24 are typically provided above the diffusing plate 16 for enhancing the back light unit 10 so as to output light beams with uniform luminous intensity to the display panel 12. The number and the position of the diffusing sheet 22 and the optical focusing film 24 can be varied according to the requirements of the products.
The light source generator 14 in the back light unit 10 is typically composed of a plurality of light tubes. To meet the requirements of high brightness and low weight, the aforementioned light source generator 14 is often installed in a closed chamber which is very narrow and small. Thus, the heat generated during operation accumulates rapidly, leading to a high temperature near the light tubes after operating for a period of time. The high temperature interferes with the normal operation of the display panel 12 and deteriorates the display performance. For example, distortion easily occurs on the screen. This leads to a decrease in the lifetime of devices nearby.
Consequently, there is a strong need to provide a back light unit with a high heat transfer rate to improve the display performance and lengthen the lifetime of devices in the back light unit.

Back light unit with high heat transfer rate


A resealable container and closure package includes a container and a closure cap. The container has a longitudinal center axis, and a finish. The finish includes an external thread, an annular lip, and a sealing surface. The external thread includes 1.5 turns of a complete thread having symmetrical flank angles of about 13 degrees. The lip extends radially inwardly from a neck at an angle from about 0 degrees to about 5 degrees from a plane orthogonal to the center axis. The sealing surface is on an exterior surface of the lip. The closure cap includes an end wall defining a circumferential edge, an annular skirt projecting from the end wall, and an internal thread defined on an inner surface of the annular skirt. The internal thread is threadingly engageable with the external thread. The internal thread has an “M” style cross section for an SP 400 Finish.

Some dispersion-based colorants, such as universal colorants, are packaged in quart metal cans. The metal cans require a variety of tools to be opened in order to fill colorant dispensers. Such colorant dispensers are used to provide one or more colorants to a base paint to provide a paint of a desired color. A common method used to open the metal cans of universal, dispersion-based colorant is with the use of a carpet knife and a "church key" type triangular can opener. Both opening tools and methods of use leave small openings in the top of the can from which the colorant has to be poured. This results in slow addition time to the dispensers, does not allow the metal containers to fully empty, and does not allow for access to properly clean the containers for environmentally sound disposal.
In the daily filling of the colorant dispensers, a large number of quart containers are required. This process of refilling the dispensers requires a considerable time commitment. Typically, prior to filling the dispensers, the containers holding the colorant are shaken, such as in conventional paint mixing equipment, to mix and provide a uniform colorant. Examples of conventional paint mixing equipment clamp the container between top and the bottom plates and vigorously shake the container to mix the contents. In some cases, a tray shaker holds and mixes a plurality of containers simultaneously. Mixing in such equipment takes about 3-5 minutes. If a full quart of colorant is not used, the containers are stored until the next day. There is no way to reseal the partially filled open containers, subjecting the containers to potential contamination, spillage, evaporation of components, and inability to remix. Upon completion of filling all dispensing canisters, all the quart cans are disposed of as normal waste. There is no ability to recycle.

Resealable container and closure package


A method performed by a first hardware element in a hierarchical arrangement of hardware elements in an object storage system is described. The method includes performing a hash on a name of an object of the object storage system. The name is part of a request that is associated with the object. A result of the hash is to identify a second hardware element directly beneath the first hardware element in the hierarchical arrangement. The request is to be sent to the second hardware element to advance the request toward being serviced by the object storage system.

With the emergence of cloud computing and high performance data centers as an infrastructure environment for modern day computing, innovations are being made in large scale data storage. One particular emerging storage approach, referred to as object storage, is characterized by a highly versatile input namespace, ease of operation with distributed storage nodes and corresponding large scale storage capacity. When attempting to physically build the hardware and/or software needed to implement an actual, working object storage system, however, issues of practical implementation may be observed resulting in an opportunity for practical innovation improvements.

Object storage system with multi-level hashing function for storage address determination


A diode circuit in a dielectric waveguide device designed to improve the facility with which a circuit substrate is mounted in the dielectric waveguide, to make matching between a dielectric waveguide and a diode easier, and to reduce conversion losses, and a detector and a mixer using such a diode circuit. A conductor pattern is disposed so as to intersect a pair of dielectric strips substantially perpendicularly to the same, and two filter circuits are formed in the dielectric pattern on opposite sides of the dielectric strips, thereby forming a resonance circuit. A diode is mounted in the resonance circuit in series with the conductor pattern.

1. Field of the Invention
The present invention relates to a diode circuit in a dielectric waveguide device for use in, for example, a transmitter-receiver for a millimeter wave or microwave band, and to a detector and a mixer using the diode circuit.
2. Description of the Related Art
A diode circuit in a nonradiative dielectric waveguide (hereinafter referred to as "NRD guide"), and a detector and a mixer using the diode circuit have been disclosed in (1) Kuroki and Yoneyama, "Nonradiative Dielectric Waveguide Circuit Elements Using Beam Lead Diode", Collected Papers of The Institute of Electronics, Information and Communication Engineers, C-1, vol.J73-C-I No.2, pp.71-76, February 1989. Also, a detector arranged in an H guide has been disclosed in (2) F. A. Benson, P. A. Cudd, F. J. Tischer, "Solid-State Device In H-Guide, Groove Guide and Fence Guide", Electron. Lett., 18th August 1983, Vol.19, No.17, pp.657-658.
In the structure shown in document (1), a circuit substrate on which a diode is mounted is disposed so as to intersect a dielectric strip in a direction perpendicular to the lengthwise direction of the dielectric strip, and electromagnetic waves propagating through the dielectric strip are coupled with the diode on the circuit substrate. In the arrangement described in document (2), a circuit substrate on which a linear electrode pattern is formed is interposed between central portions of an H guide, and diodes are mounted on the electrode pattern on the opposite sides of a dielectric strip at distances of 1/10 wavelength from the dielectric strip, thus forming a detector.
In the structure shown in document (1), however, the circuit substrate cannot easily be fixed in the device and is liable to incline, since the circuit substrate on which the diode is mounted is disposed in a direction perpendicular to the lengthwise direction of the dielectric strip. Thus, this structure is disadvantageous in terms of mounting. Moreover, there is a need to insert a high-dielectric-constant thin plate or to form a gap in the NRD guide for the purpose of matching. Therefore, the device using this structure is difficult to design and manufacture. In document (2), no structure is described for stopping propagation (leakage) of millimeter waves at the opposite ends of the suspended line (described as a "stripline" in the document) in which the diodes are mounted, and matching between the H guide and the diodes is not considered. Consequently, the loss due to leakage of millimeter waves out of the suspended line is so large that the diodes cannot receive sufficient energy, resulting in a large conversion loss.

Diode circuit in dielectric waveguide device, and detector and mixer using the diode circuit


A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.

In synchronous systems, devices in the system are clock clocked by an external clock signal and perform operations at predetermined times relative the rising and falling edges of the clock signal. For example, in a typical memory system, a memory controller applies commands to synchronous memory devices and data is transferred between the memory devices and the controller in synchronism with an external clock signal applied to the controller and memory devices. In the memory system, the memory controller must place write data being transferred to the memory devices on a data bus at the proper times relative to rising and falling edges of the external clock signal to ensure that the memory devices successfully capture the data. Similarly, the memory devices must place read data being transferred to the controller on the data bus at proper times relative to rising and falling edges of the clock signal to ensure the controller successfully captures the data.
FIG. 1 is a simplified block diagram of a conventional memory system 100 including a synchronous memory 102, such as a DDR SDRAM, coupled to a memory controller 104 through an address bus ADDR, data bus DATA, and control bus CONT. An external clock signal CLK is applied to the memory 102 and controller 104, and the transfer of data over the ADDR, DATA, and CONT busses occurs at proper times relative to edges of the CLK signal to ensure a receiving device successfully captures the data being transferred. The data bus DATA includes a data strobe signal DQS that the memory 102 applies on the data bus DATA along with a read data word DQ1–N, and the memory controller 104 uses the DQS signal to successfully capture the read data word. During write operations, the memory controller 104 applies the DQS signal on the data bus DATA along with a write data word DQ1-N, and the memory 102 uses the DQS signal to successfully capture the write data word. The memory controller 104 also supplies a data masking signal DM to the memory 102 over the data bus DATA to control the masking of write data being transferred to the memory.
In operation, the memory controller 104 applies a data transfer command to the memory 102 in the form of appropriate address and control signals on the ADDR and CONT busses, respectively. The memory latches the applied command in response to a rising edge of the CLK signal, and thereafter decodes and processes the latched command. In response to a read command, the memory 102 accesses the addressed data, places the data on the data bus DATA as one or more read data words DQ1–N, and strobes or drives the DQS signal. The memory controller 104 captures read data words DQ1–N in response to rising and falling edges of the DQS signal. During write operations, in addition to applying a write command to the memory 102, the memory controller 104 places write data words DQ1–N on the data bus DATA and drives the DQS signal. In response to the write command, the memory 102 captures write data words DQ1–N in response rising and falling edges of the DQS signal, and stores the write data words in locations corresponding to the supplied address. The memory 102 also masks the DM signal applied coincident with each write data word DQ1–N, and masks or does not transfer the captured write data word to the addressed location when the DM signal is activated.
To successfully capture the data words DQ1–N being transferred over the data bus DATA, the DQS signal must be synchronized with the data words. During read operations, the memory 102 places each read data word DQ1–N on the data bus DATA in synchronism with a rising or falling edge of the DQS signal. In modern memory devices, the speed of the data bus is increasing, meaning that the frequency of the DQS signal is greater and the duration for which data words placed on the data bus are valid is decreasing (i.e., shorter read and write cycle times). As a result, shifts between the DQS signal and the data words become more critical since a smaller shift may now result in spurious data being captured. This is true because a smaller shift in the DQS signal relative to the data words may result in the memory 102 or controller 104 capturing the data words when the words are no longer valid, as will be appreciated by those skilled in the art.
A width N of the data bus DQ is being increased in modern synchronous memory devices to transfer more data to and from the memory 102 each cycle of the CLK signal, where the width N of the data bus is defined as the number of signals or bits N in a data word DQ1–N. This increase in the width N of the data bus DATA can result in an undesirable skew or shift of the read data words DQ1–N relative to the DQS signal. Such a shift can occur as more data drivers (not shown in FIG. 1) in the memory 102 draw more current from a power supply (not shown) in driving more bits in each data word DQ1–N from a first logic state to the complementary logic state when a new data word is being placed on the data bus DATA. Such a shift is known as simultaneous switching outputs (SSO) pushout, as will be understood by those skilled in the art. For example, if a first read data word DQ1–N includes all 0's and the next read data word includes all 1's, each data driver draws current from the power supply in driving the corresponding bit from a voltage level corresponding to a logic 0 to a voltage level corresponding to a logic 1. The larger the width N of the data bus DATA, the more data drivers required and the more current demanded from the power supply in this situation, and the larger the voltage drop across each data line due to an increased inductance L of each data line, as will be discussed in more detail below.
As the width N increases, the cumulative current required by all data drivers can exceed a maximum current capable of being supplied by the power supply. In this situation, the data drivers receive less current than required to drive the corresponding bits from a voltage level corresponding to a first logic state to a voltage level corresponding to the complementary logic state according to specified timing characteristics of the memory 102. One such timing characteristic is an access time, which defines a timing window around the transition of the DQS signal in which transitions of the bits in the data words must occur in order to allow the memory controller 104 to successfully capture the data words in response to the DQS signal. The reduced current causes the data drivers to drive the corresponding bits to the complementary logic states more slowly and thereby undesirable shifts the data word DQ1–N relative to the DQS signal, possibly shifting the data word outside the specified access time for the memory 102. The shift between the transition of the DQS signal and each data word DQ1–N depends on the number of bits changing logic state and the logic state to which the bits are changing, as will be understood by those skilled in the art. In addition to a reduced current being supplied to the data drivers, physical constraints on the size of the power lines (not shown) that supply power to the data drivers can result in the power lines having an inductance that causes a relatively large voltage drop to develop across the power lines when the data drivers demand a maximum current over a short period of time (V=Ldi/dt). Such a voltage drop can also slow the rate at which the data drivers drive the corresponding bits to the required voltage levels and shift the data words outside the specified access time.
FIG. 2 is a signal timing diagram illustrating shifts in the read data words DQ1–N relative to the DQS signal as the number of bits transitioning from a first logic state to the complementary logic state varies. In FIG. 2, three situations are illustrated where a new data word D0–2 is being placed on the data bus DATA with the prior data word on the data bus in each instance designated PD0–2, respectively. In the first situation, no bits are transitioning or changing state from the PD0 word to the D0 word (PD0=D0), and the data drivers place the D0 word on the data bus DATA in synchronism with the DQS signal at a time T0 and within a specified access time TAC of the memory 102. In the second situation, one half the bits change from a first logic state to the complementary logic state between the data words PD1 and D1. The data drivers place the D1 word on the data bus DATA at a time T1 just after the transition of the DQS signal at the time T0, which is also within the specified access time TAC. Thus, the data drivers place the data word D1 on the data bus more slowly relative to the data word D0 due to more bits changing from a first logic state to the complementary logic state.
In the third situation shown in FIG. 2, all bits change state between the data words PD2 and D2, and the data word D2 is placed on the data bus DATA at a time T2 after the transition of the DQS signal at the time T0. In this situation, the data word D2 is placed on the data bus DATA outside the specified access time TAC of the memory 102 due to the slower operation of the data drivers resulting from all N bits in the data word changing state. If the width N of the data bus DATA is increased, the data words will be delayed even more relative to the transition of the DQS signal when all or a large number of bits change from a first logic state to the complementary logic state, assuming the same power is supplied to the data drivers. Additional power could be supplied to the data drivers to eliminate these undesirable shifts, but it is not always practicable or cost effective to increase the power, as will be appreciated by those skilled in the art. The concepts described above have been discussed with reference to read operations because timing budgets for read cycles are typically tighter (less margin) than for write cycles and thus timing shifts are more critical, but the concepts are equally applicable to write cycles.
An approach that has been utilized in microprocessors, such as the Intel® Pentium® 4, is to include additional pins in the data bus for transferring one or more data bus inversion signals DBI generated by the processor. Each data bus inversion signal is associated with a group of bits, such as a byte, of data on the data bus. In operation, the processor determines whether more than half the bits in each byte would change logic state from a current byte on the data bus to a next byte to be placed on the data bus. If more than one half the bits in the byte would change logic state, the processor inverts the data bits in the next byte and activates the DBI signal associated with the byte. A receiving device, such as a memory controller, thereafter receives the next byte and the active DBI signal, and inverts the data in the next byte in response to the active DBI signal, thus returning the inverted data to its actual values. This approach requires the inclusion of additional pins on the processor and receiving devices, which increases the cost of the processor and receiving devices due to the increased number of pins, as will be appreciated by those skilled in the art. Moreover, as the width of the data bus increases, more DBI signals and associated pins are required, which consumes even more pins on the processor and receiving devices.
There is a need for a system and method for providing data words in synchronism with a clock signal in integrated circuits having wide data busses independent of the number of bits the data words changing from a first logic state to a complementary logic state.

Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing


A coil spring 103 is wound around a rotational shaft 15 with its one end portion 103a being inserted into an engagement groove 100a formed in a side wall of a direct-coupled gear 100 and with its other end portion 103b being inserted in an engagement groove 93a provided in a front wall 93 of a paper cassette 6. The elastic force generated by the coil spring 103 functions as a pressing force for restraining the torque of the rotational shaft 15 that is generated by the driving force from a DC motor 70. The amount of the elastic force increases as the height of a paper pressing plate 8 increases. Accordingly, a variation in the height of the topmost sheet 3, which will possibly occur due to changes in the amount of recording medium 3 placed on a mounting plate 8, can be restrained.

1. Field of the Invention
The present invention relates to an image forming device and a recording medium supply device that supplies a recording medium to the main body of the image forming device.
2. Description of Related Art
Japanese Unexamined Patent Application Publication Nos. 5-208734 and 8-73055 disclose a paper-supply device of a type that is provided with a mounting plate, on which is placed a plurality of sheets of paper in a stack, and a lifting or elevating member that pivots upon receiving the driving force of a drive motor to push the mounting plate upward. A controller executes an on/off control of supplying a drive current to the drive motor while monitoring the position of the height of the topmost sheet of paper stacked on the mounting plate. The controller stops supplying the drive current to the drive motor when the height of the topmost sheet of paper reaches a predetermined height that corresponds to a supply port for receiving the sheet of paper from the paper-supply device and for supplying the sheet of paper into an image forming device.

Recording medium supply device and image forming device


This invention comprises the use of compounds of formula (I)

Proliferation of smooth muscle cells of the arterial wall in response to local injury is an important aetiologic factor of vascular proliferative disorders such as atherosclerosis and restenosis after angioplasty. The incidence of restenosis after percutaneous transluminal coronary angioplasty (PTCA) has been reported to be as high as 45% within three to six months after PTCA treatment (Indolfi et al., Nature medicine, 1, 541-545 (1995)). Hence, compounds that inhibit smooth muscle cell proliferation can be very useful to prevent or treat vascular proliferative disorders such as atherosclerosis and restenosis.
Heparin is a well known compound to inhibit proliferation of smooth muscle cells after coronary angioplasty (Buchwald et al., J. Cardiovasc. Pharmacol., 28, 481-487 (1996)).
In our co-pending application PCT/EP96/04515, published on 19 Jun. 1997 as WO-97/21701, the compounds of formula (I), their preparation and compositions containing them are disclosed as famesyl transferase inhibitors useful for the treatment of ras dependent tumors.

This patent is subject to a terminal disclaimer.

Method of use of (imidazol-5-yl)methyl-2-quinolinone derivatives to inhibit smooth muscle cell proliferation

Abstract: wherein the dotted line represents an optional bond; X is oxygen or sulfur; R1 is hydrogen, C1-12alkyl, Ar1, Ar2C1-6alkyl, quinolinylC1-6alkyl, pyridylC1-6alkyl, hydroxyC1-6alkyl, C1-6alkyloxyC1-6alkyl, mono- or di(C1-6alkyl)aminoC1-6alkyl, aminoC1-6alkyl, or a radical of formula -Alk1-C(═O)—R9, -Alk1-S(O)—R9 or -Alk1-S(O)2—R9; R2, R3 and R16 each independently are hydrogen, hydroxy, halo, cyano, C1-6alkyl, C1-6alkyloxy, hydroxyC1-6alkyloxy, C1-6alkyloxyC1-6alkyloxy, aminoC1-6alkyloxy, mono- or di(C1-6alkyl)aminoC1-6alkyloxy, Ar1, Ar2C1-6alkyl, Ar2oxy, Ar2C1-6alkyloxy, hydroxycarbonyl, C1-6alkyloxycarbonyl, trihalomethyl, trihalomethoxy, C2-6alkenyl; R4 and R5 each independently are hydrogen, halo, Ar1, C1-6alkyl, hydroxyC1-6alkyl, C1-6alkyloxyC1-6alkyl, C1-6alkyloxy, C1-6alkylthio, amino, hydroxycarbonyl, C1-6alkyloxycarbonyl, C1-6alkylS(O)C1-6alkyl or C1-6alkylS(O)2C1-6alkyl; R6 and R7 each independently are hydrogen, halo, cyano, C1-6alkyl, 4,4-dimethyl-oxazolyl, C1-6alkyloxy or Ar2oxy; R8 is hydrogen, C1-6alkyl, cyano, hydroxycarbonyl, C1-6alkyloxycarbonyl, C1-6alkylcarbonylC1-6alkyl, cyanoC1-6alkyl, C1-6alkyloxycarbonylC1-6alkyl, carboxyC1-6alkyl, hydroxyC1-6alkyl, aminoC1-6alkyl, mono- or di(C1-6alkyl)aminoC1-6alkyl, imidazolyl, haloC1-6alkyl, C1-6alkyloxyC1-6alkyl, aminocarbonylC1-6alkyl, or a radical of formula —O—R10, —S—R10, —N—R11R12; R17 is hydrogen, halo, cyano, C1-6alkyl, C1-6alkyloxycarbonyl, Ar1; R18 is hydrogen, C1-6alkyl, C1-6alkyloxy or halo; R19 is hydrogen or C1-6alkyl; for the manufacture of a medicament to inhibit smooth muscle cell proliferation.


Charging a first device by a second device. The first device determines a first position of the first device relative to the second device. Based on the charging position, automatically moving, by the first device, into a second position on the second device. The first device comprises a first motor and a second motor. The first motor is capable of moving the first device along a first axis. The second motor is capable of moving the first device along a second axis.

The present disclosure relates generally to devices, such as mobile devices, and more specifically, to vectored motion in devices.
Traditional mobile phones and pagers incorporate a vibrational motor that work on a rotational means to provide a single form of vibrational motion control over this device. This form of vibrational motion control results in a limited set of user feedback options which can be generated from the restrictive nature of the vibrational mechanisms incorporated in present systems. Attempts to provide a fine grained motion control or vibration based feedback are limited to pulsing a single mode of operation on an off for arbitrary periods of time.

Multi axis vibration unit in device for vectored motion

International Business Machines Corporation


An undershoot eliminating circuit is provided between a pulse transformer of a pulse transmitter coupled to a transmission line and a pulse transformer driving circuit for driving the pulse transformer. The pulse transformer driving circuit has an impedance high enough to cause the pulse transmitter to be substantially isolated from the transmission line. The undershoot eliminating circuit includes a capacitor, and a switching unit. The switching unit is connected to the capacitor, and has the function of selectively connecting the capacitor to the pulse transformer driving circuit and the pulse transformer in parallel on the basis of a voltage based on a pulse wave generated by the pulse transformer driving circuit and applied across the switching unit.

1. Field of the Invention
The present invention generally relates to an undershoot eliminating circuit for eliminating an undershoot of a pulse waveform, and more particularly to an undershoot eliminating circuit which provides a high impedance when the impedance of a pulse transmitter which is inactive (transmits no signal) is measured. Furthermore, the present invention is concerned with a pulse transmitter having such an undershoot eliminating circuit.
2. Description of the Related Art
Recently, there has been a requirement to transmit data at a high bit rate. For this requirement, data is converted into a high-bit-rate digital pulse waveform and transferred between communication devices. There has also been a requirement to simplify transmission lines between communication devices. To satisfy this requirement, a bus is shared by a plurality of communication devices. In order to realize the bus sharing communications, a transmitter output pulse mask is defined by, for example, CCITT Recommendation I. 430 (see FIG. 12/I. 430), the disclosure of which is hereby incorporated by reference. The pulse waveform should be within the pulse mask. Further, in order to realize the bus sharing communications, it is required that each transmitter has a high impedance to substantially isolate each transmitter from the shared bus when each transmitter is inactive or does not transmit any signal. According to the CCITT Recommendation I. 430, when each transmitter is inactive, the output impedance thereof shall exceed the template in FIG. 10/I. 430 in the frequency range of 2 kHz to 1 MHz. That is, it is required that the transmitter of each communication device connected to the shared bus meets both, the mask requirement when it is active and the impedance requirement when it is inactive.
FIG. 1A shows a pulse transmitter that employs a transformer. A pulse transmitter 100 shown in FIG. 1A is connected across a load 2 having a load resistor RL via interface points A and B, and includes a pulse transformer driving circuit 11 and a pulse transformer 12. The pulse transformer 12 has a turns ratio N, a primary inductor (winding) LP, and a secondary inductor (winding) LS. The secondary winding LS is connected to a transmission line functioning as a shared bus.
FIG. 1B is a circuit diagram showing an equivalent circuit of the pulse transmitter shown in FIG. 1A obtained when the pulse waveform has a peak. At this time, a switch S1 of the pulse transform driving circuit 11 is ON, while a current IR flows through the load resistor RL (RL/N.sup.2), and a current LP flows through the primary winding of the pulse transformer 12. The ON state of the switch S1 indicates that the pulse transmitter 100 is transmitting a pulse. The OFF state of the switch S1 indicates that the pulse transmitter 100 is inactive or transmitting no signal.
FIG. 2A shows a waveform of the pulse developed across the load resistor RL (RL/N.sup.2) in the equivalent circuit shown in FIG. 1B) when the switch S1 is initially ON and then turned OFF at time T. The instance the switch S1 turns OFF, a reverse voltage develops across the load resistor RL. This reverse voltage causes an undershoot of the pulse waveform output by the pulse transformer 12.
The manner in which the above problem comes about is as follows. The current IL is continuously passing through the primary inductor LP of the pulse transformer 12 until a time T. The instance the switch S1 turns OFF, the current IL is forced to flow continuously because of the magnetic characteristics of the pulse transformer 12. However, the switch S1 is turned OFF at this time, and the equivalent circuit of the pulse transmitter 100 is changed to a closed circuit as shown in FIG. 2B. Hence, the current IL forced to flow in the primary inductor LP develops a reverse voltage across the load resistor RL (RL/N.sup.2). This reverse voltage corresponds to an undershoot of the pulse waveform.
In order to eliminate the above undershoot, an undershoot eliminating circuit 131 is connected in parallel to the primary winding LP of the pulse transformer 12, as shown in FIG. 3A. The undershoot eliminating circuit 131 includes a capacitor C connected in parallel to the primary winding LP. As shown in FIG. 3B, a voltage E is applied across the capacitor C until the aforementioned time T. Hence, the capacitor C is charged so that it has polarities as shown in FIG. 3B. At the time T, the switch S1 turns OFF. At this time, the pulse transmitter 12 shown in FIG. 3A has an equivalent circuit shown in FIG. 3C. The capacitor supplies the load resistor RL (RL/N.sup.2) with a backward current IC reverse to the current IL forced to pass through the load resistor RL (RL/N.sup.2) due to the function of the primary inductor LP. Hence, the current IL is canceled by the current IC and no current passes through the load resistor RL (RL/N.sup.2). In this manner, the undershoot can be eliminated from the pulse waveform.
FIG. 4A shows an equivalent circuit of the pulse transmitter shown in FIG. 3A obtained when the impedance of the inactive pulse transmitter is measured. In this measurement, an impedance meter 3 is connected in parallel to the pulse transformer 12 via the interface points A and B. The impedance meter 3 is made up of a synthesizer 31, and a level meter 32. The synthesizer 31 comprises a resistor R and an oscillator OC connected in series. The synthesizer 31 generates a sine wave having a predetermined frequency and a predetermined power level. The level meter 32 measures a voltage level developed across the load (in this case, the interface points A and B of the pulse transmitter 100). The impedance of the load (the pulse transmitter 100 in this case) is calculated from a voltage level indicated by the level meter 32. The frequency and the voltage of the sine wave generated by the synthesizer 31 can be varied, and the impedance of the load connected to the impedance meter 3 can be obtained by measuring a current passing through the impedance meter 3.
When the switch S1 is OFF, the impedance Z of the pulse transmitter 100 is written as follows: EQU Z=1/{(1/j.omega.LS)+j.omega.C.times.N.sup.2 } (1)
where .omega. is equal to 2.pi.f, f denotes the frequency of the sine wave, and LS denotes the inductance of the pulse transformer 12.
When the frequency is high, the expression (1) can be made to approximate to expression (2): EQU Z=1/j.omega.C.times.N.sup.2.
It can be seen from the expression (2) that there is a tendency such that as the capacitance of the capacitor C, provided for eliminating an undershoot of the pulse waveform, increases or as the measurement frequency increases, the impedance of the pulse transmitter 100 decreases.
FIG. 4B shows the aforementioned impedance characteristic of an NT (Network Termination unit) pulse transmitter for use in the bus connection prescribed in the CCITT Recommendation I. 430. The above impedance characteristic is indicated by symbol P. It is required that the pulse transmitter has an impedance exceeding the impedance defined by the impedance characteristic curve P in the range of 2 kHz to 1 MHz.
Recently, there has been a requirement to use a compact transformer in order to miniaturize the pulse transmitter and reduce the production cost. In general, such a compact transformer has an impedance characteristic indicated by lines (1) shown in FIg. 4B. That is, the compact transformer does not have a large impedance margin with respect to the impedance characteristic prescribed by the CCITT Recommendation I. 430. When the capacitor C for eliminating an undershoot of the pulse waveform is connected as shown in FIG. 3A, the impedance characteristic of the pulse transmitter 100 changes as shown by a line indicated by (2) in a high-frequency range (the impedance characteristic obtained in a low-frequency range is omitted for the sake of clarify). It can be seen from FIG. 4B that the impedance characteristic in the high-frequency range does not meet the impedance characteristic prescribed by the CCITT Recommendation I. 430. As the capacitance of the capacitor C for eliminating an undershoot of the pulse waveform increases in order to meet the pulse mask defined by the CCITT Recommendation I. 430, the impedance margin with respect to the prescribed impedance characteristic decreases and finally the impedance characteristic of the pulse transmitter fails to meet the prescribed impedance characteristic.
In the conventional technique, the capacitance of the capacitor is manually adjusted during the production process so that both the pulse mask requirement and the impedance characteristic requirement are satisfied. However, this needs a large number of production steps and test steps.

Pulse transmission circuit with undershoot eliminating circuitry


A method includes buffering a plurality of video streams within a buffer of a video server and generating a unicast video output and a multicast video output at the buffer.

In a typical analog type cable broadcast video service, channel switching is nearly instantaneous. In a digital cable system, the channel change time may be somewhat greater, because of the time to tune to the correct frequency and to extract the digital bit stream from the transport stream. In a typical system, the video program stream is identified, extracted and decoded for display. Channel change times for a satellite based Direct Broadcast System may be similar to the times for the digital cable system. The channel change time can be affected by the location of the channel in the transponder and the satellite. For example, if the next channel is on a separate transponder and on a separate satellite, then the switch matrix may have to make a transition between satellites before delivering the channel bit stream to the decoder and hence further increasing the channel change time.
Video content may be delivered over an Internet protocol (IP) network. In an IP network, each channel of a broadcast TV service may be delivered as an IP multicast stream. A set top box connected to the network can request the network for membership to a member of a multicast group/channel. After receiving a channel change request from a user, the set top box leaves the multicast group channel and joins a new multicast group channel associated with the channel change request. This process can take several seconds longer than the channel change times for other video delivery formats. This delay time between channel changes may result in a poor user experience.

System and method of managing video content streams


The present invention provides a propylene-ethylene copolymer which is excellent in a balance between a heat resistance and an elasticity recovering property and has a good transparency and which is improved in peel whitening brought about by mutual adhesion in storing specific to soft materials, a resin composition for a transparent elasticity recovering film or sheet comprising the above copolymer, a transparent elasticity recovering film or sheet and a wrap film.

The present invention relates to a propylene-ethylene copolymer suited as a material for a transparent film or sheet having elasticity recovering property in which conversion to non-polyvinyl chloride proceeds, a resin composition for a transparent film or sheet having elasticity recovering property comprising the above copolymer and a transparent elasticity recovering film or sheet and a wrap film comprising the above resin composition.

Resin composition, transparent film or sheet having elasticity recovering property, and wrap film


The invention relates to a method for detecting a threshold-crossing of a back electromotive force (bemf) measured in one phase of a multiple-phase motor, the one phase being set at a high impedance while at least one other phase is supplied by pulse-width modulation signal. The method includes the step of comparing the bemf with a threshold. The method includes, prior to the step of comparing, the steps of sampling the bemf during on-periods of the pulse-width modulation signal, and holding the bemf during off-periods of the pulse-width modulation signal.

FIG. 1 schematically shows the connections of three phases of a conventional hard disk drive spindle motor. The motor comprises three windings WA, WB and WC, each having one terminal connected to a common center tap N. Three remaining terminals A, B and C of the three windings, respectively, are controlled by a three-phase switch bridge. Each of the terminals A, B and C is coupled to a low supply voltage GND through a low side switch SL, and is also coupled to a high supply voltage Vcc through a high side switch SH.
FIG. 2A shows exemplary voltage waveforms at the terminals A, B and C, illustrating a conventional control cycle for the switches SH and SL coupled to each of the terminals A, B, and C. Each of the terminals A, B and C is successively connected to the voltage Vcc when SH=1 and SL=0, and then is set at a high impedance or "tri-stated" when SH=0 and SL=0, and is finally connected to the low voltage GND when SH=0 and SL=1. As shown in FIG. 2A, the time intervals in which the terminals A, B, or C are connected to the voltage Vcc or to the low voltage GND are twice as long as the time intervals in which the terminals A, B, or C are tri-stated. Furthermore, the control cycles of the terminals B and C are phase shifted by 120.degree. and 240.degree., respectively, relative to the control cycle of the terminal A, so that, for each sixth of a full switching cycle, while one winding is in turn tri-stated, the two other windings are connected in series between the voltages Vcc and GND.
The voltage across the winding which is tri-stated is representative of the bemf of the motor. This voltage is measured and its zero-crossing, relative to the voltage at the center tap N, is detected to provide information of the speed of the motor which is used for servo-controlling the motor. As shown, the voltage at the terminal of a tri-stated phase begins with a spike due to inductive recirculation and continues with an increasing or decreasing portion of a sinusoid. The zero-crossing detection is enabled only during the sinusoidal portions.
In low power motors, the speed of the motor is adjusted by varying the conductance of the high side switches SH or the low side switches SL. This method of speed control causes a power loss in the switches which may be acceptable for low power motors but becomes excessive in higher power motors.
To reduce the power losses, the switches SH and SL are controlled to be switched on and off by a pulse-width modulation signal. However, control of the switches SH and SL by a pulse-width modulation signal affects the reliable detection of the bemf zero-crossings.
FIG. 2B illustrates an enlarged portion of the waveform shown in FIG. 2A, in a case where a pulse-width modulation signal is used to control the switches SH and SL. During the supply time interval of a pair of the windings, the voltage at one terminal of the pair of windings is chopped between the voltages Vcc and GND. When this terminal is tri-stated, its voltage is affected by the chopping which continues on the next terminal. As shown, the voltage at this terminal is chopped between the bemf value and a lower value. A false zero-crossing detection occurs at a time t.sub.1 well before the zero-crossing of the bemf which occurs at a time t.sub.0.
Some circuits, like circuit L6232B manufactured by SGS-Thomson Microelectronics, regulate the nominal speed of a motor by adjusting the conductance of the low side switches SL and, when the motor is started, the circuits use a pulse-width modulation signal in order to reduce the current drawn from the power supply. As indicated above, these circuits are only adapted to low power motors.

Bemf zero-crossing detection system of a multiple-phase motor


The invention provides an immunostimulant for a lactating bovine mammary gland, said immunostimulant containing lactoferrin or pharmaceutically acceptable salt thereof as an active ingredient.

Dairy cattle become pregnant by fertilization during a lactation period. Five months after fertilization, the cattle begin to actively secrete hormones, such as estrogen, from their placentas and milk secretion decreases. As a result, part of the mammary gland tissue and cells start to regress.
As mammary glands in mother cattle regress, milk productivity is decreased while the fetal cows grow. Dairy farmers stop milking at an appropriate time in the precalving period in order to induce the mammary gland to enter the dry period. This will facilitate smooth parturition by dairy cattle and resumption of postcalving lactation.
During the dry period, new mammary tissue is generated and differentiated for suckling and feeding to newborn calves. This generation and differentiation occurs due to regression of the old mammary epithelium in the mucosal mammary tissue by apoptosis and the replacement ingression of various blood cells. When the generation and differentiation begins, mammary cells and tissues comprise extremely diverse constituent cells, including granulocytes, monocytes, macrophages, dendritic cells, NK cells, T-cells, B-cells and mast cells. Phagocytic cells such as granulocytes and macrophages are distributed in the mammary tissue and milk. Lymphocytes, such as helper CD4+ T-cells derived from the bloodstream and antibody-producing B-cells, are also distributed (Vet. Immunol. & Immunopathol., Vol. 65, 51–61, 1998; J. Dairy Sci., Vol. 82, 1459–1464, 1999). Thus, mammary gland resistance to infection is increased in the dry period.
The current method of inducing dairy cows to enter the dry period is to stop milking the cows in order to increase pressure within the mammary glands. However, in reality, some mammary glands of lactating cows struggle in the smooth transition to the dry period even with of the performance of this method. In such case, the cows encounter the problem that exogenous bacteria may easily infect the mammary glands resulting in an increased incidence of mastitis.
If the transition is delayed and troubled, the mammary gland of mother cows may be retarded. Further, when the mother cow raises calf, the calf may also encounter problems such as defective development, or be affected by infectious diarrhea caused by various bacteria or viruses.
These problems are serious to dairy farmers, and the earliest possible resolution of these problems is desired. However, no useful means to solve them has been found.

Immunopotentiator for mammary gland of dairy cows containing lactoferrin as an active ingredient


Certain embodiments of the invention may be found in a method for memory management for a mobile multimedia processor. The method may comprise receiving within a mobile multimedia processor chip a plurality of memory requests. The plurality of memory requests may be handled by allocating memory from at least one on-chip memory block and/or at least one off-chip memory block. The memory may be allocated based on a priority level of each of the plurality of memory requests and at least one dynamically settable global memory allocation priority threshold. A new dynamically settable global memory allocation priority threshold may be dynamically determined based on a new application and/or by monitoring at least one software process in at least one present application. Additionally, new memory request priority level may be dynamically determined for each memory request in at least one software process in a new application.

Mobile communications have changed the way people communicate and mobile phones have been transformed from a luxury item to an essential part of every day life. The use of mobile phones today is dictated by social situations, rather than hampered by location or technology. While voice connections fulfill the basic need to communicate, and mobile voice connections continue to filter even further into the fabric of every day life, various integrated mobile multimedia applications, utilizing the mobile Internet, may be the next step in the mobile communication revolution.
Third generation (3G) cellular networks offering various high speed access technologies and mobile telephones that have been specifically designed to utilize these technologies, fulfill demands for integrated multimedia applications supporting TV and audio applications utilizing advanced compression standards, high-resolution gaming applications, musical interfaces, peripheral interface support, etc. The processing requirements are being increased as chip designers take advantage of compression and higher bandwidths to transmit more information. 3G wireless applications support bit rates from 384 kilobits (Kbits)/second to 2 megabits (Mbits)/second, allowing chip designers to provide wireless systems with multimedia capabilities, superior quality, reduced interference, and a wider coverage area.
As mobile multimedia services grow in popularity and usage, factors such as power consumption, cost efficient optimization of network capacity and quality of service (QoS) will become even more essential to cellular operators than it is today. These factors may be achieved with careful network planning and operation, improvements in transmission methods, and advances in receiver techniques and chip integration solutions. To this end, carriers need technologies that will allow them to increase downlink throughput for the mobile multimedia applications support and, in turn, offer advanced QoS capabilities and speeds for consumers of mobile multimedia application services. Additionally, the mobile device itself may need to increase its ability to handle the various mobile multimedia applications. One way to do this may be to use more powerful processors. Another way may be to use the memory available in a more efficient manner.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Memory management for a mobile multimedia processor


An immersion microscope objective lens includes, in the following order from an object side to an image side, a first lens group having positive refractive power as a whole, including a first lens component composed of a first meniscus lens and a second meniscus lens cemented to each other with their concave surfaces facing the object side, a second lens composed of a single lens having positive refractive power and a third lens composed of a negative lens and a positive lens cemented to each other, a second lens group having positive refractive power as a whole, including a fourth lens component composed of a negative lens and a positive lens cemented to each other, and a third lens group having a negative refractive power as a whole. Predetermined conditions are satisfied.

1. Field of the Invention
The present invention relates to an immersion microscope objective lens, and more particularly relates to an immersion, high magnification, apochromat microscope objective lens.
2. Related Background Art
In immersion microscope objective lenses having high magnifications, in order to correct curvature of field, a plano-convex lens having an refractive index lower than that of the frontmost lens (i.e. the lens closest to the object) is inlaid in-the frontmost lens with the planer surface facing the object side to give to the cemented surface therebetween a negative refractive power utilizing the refractive index difference between these lenses so as to reduce the Petzval sum. In addition, a so-called Gauss type lens configuration in which concave surfaces opposed to each other are disposed at a position at which the diameter of the light flux becomes small to reduce the Petzval sum by their strong negative refractive power is also known. The combination of these structures is well known as a structure that can effectively reduce curvature of field.
For example, high magnification, apochromat microscope objective lenses disclosed in Japanese Patent Application Laid-Open Nos. 7-230038, 2000-35541 and 2002-148519 have been known as examples of immersion microscope objective lenses having the above-described structure. In the immersion microscope objective lenses disclosed in these patent documents, the surface of the inlaid lens (i.e. a small diameter lens inlaid in the frontmost lens) that is in contact with the immersion liquid is designed as a planar surface in order to facilitate operations of removing air bubbles and foreign matters etc. in the immersion liquid or in view of ease of processing of the lens itself. In the case that the immersion liquid is oil, the refractive index of the immersion liquid and the refractive index of the inlaid lens can be made substantially equal to each other. (The refractive indices of the oil and the glass are approximately 1.5.) Therefore, even when the surface of the inlaid lens that is in contact with the immersion liquid (which surface will be referred to as the first lens surface) is a planer surface and the incidence angle of incident light is larger than 60°, aberrations generated at that surface are insignificant and errors in the dimension of the aforementioned first lens surface and the thickness of the center have little influence on aberrations.
However, it is preferable for some kinds of specimens to be stored and observed in a state immersed in water. For such specimens it is preferable to use water as the immersion liquid of the immersion microscope objective lens. In the case of the water immersion liquid, its refractive index is as low as 1.33, which is smaller than that of the lens (made of a glass). Thus, there arises the problem that spherical aberrations occur at the interface due to the refractive index difference with the lens. In particular, in designing a lens having a large field of view with a numerical aperture (NA) more than 1.2 while ensuring a minimum necessary working distance, significant high order spherical aberration occurs, and it is difficult to correct the aberration by the succeeding lens groups. In practice, it has been very difficult to correct the spherical aberrations if the difference in the refractive index between the immersion liquid and the lens (or the water and the glass) is larger than 0.1, the aforementioned first lens surface is planar and the numerical aperture of is larger than 1.2.


The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.

Voltage regulators are an increasingly more important and vital component in today's power sensitive electronic systems. Specifically, mobile systems (e.g., in smart phones, tablets, etc.) relying on a finite power source (e.g., battery) might have a dozen or more voltage regulators that provide a targeted power supply level to each subsystem such that the power consumption of the overall system is optimized. Further, high speed data communication systems (e.g., 100 Gigabit Ethernet) might also implement voltage regulators that exhibit a wide bandwidth and high power supply rejection (PSR) to not only manage power consumption, but also to block or "reject" power supply voltage variations (e.g., switching noise from one or more system switching regulators) from the data signals on the data receive channels.
More specifically, such high speed data communication systems might deploy one or more low dropout (LDO) voltage regulators that exhibit a high PSR performance in a frequency range of 100 kHz to 100 MHz. Legacy LDO voltage regulator designs approach a high PSR in this range by implementing a high gain and high bandwidth front end operational amplifier (e.g., error amplifier). However, this technique increases the power consumption and noise of the LDO voltage regulator. Further, such techniques require a large amount of decoupling capacitance at the LDO voltage regulator output to suppress the peak PSR, adding costly die area to the design.
Techniques are needed to address the problem of implementing a wideband low dropout voltage regulator that exhibits high power supply rejection, and low power and low die area consumption, enabling the advancement of high speed data communication systems and other electronic systems.
None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed techniques for a wideband low dropout voltage regulator with power supply rejection boost. Therefore, there is a need for improvements.

Wideband low dropout voltage regulator with power supply rejection boost


A method of routing communications over a network includes routing the communications to an intermediate destination, for example, a “universal proxy,” using a first transport control protocol (TCP), and then routing the communications from the intermediate destination to a recipient using a second TCP. The intermediate destination optionally masks the source when transmitting information to the recipient, and performs packet loss recovery. Optionally, the second TCP includes TCP acceleration not utilized by the first TCP.

Network protocols and equipment are continuously being evolved to keep pace with ever increasing demands. Problems exist, however, which limit the ability of a host to always offer the fastest, most effective service possible. For example, a host that wishes to deliver content, such as a web page, video stream or other type of information, may be using outdated equipment or software that does not keep pace with new developments, and this may constrain information delivery.
What is needed is a way to enable a host or other Internet equipment or service provider to offer better service. Ideally, such a solution would permit any distributor of information the ability to easily deploy specific protocols or equipment without having to invest in new equipment or software, or substantially altering the information to be delivered or its associated structure. The present invention addresses these needs and provides further, related advantages.

Network communication through a specified intermediate destination


A structural mechanism for an aircraft includes a support, a hinged surface, and a hinge assembly joining the hinged surface to the support. An actuation system includes an actuator shaft engaged to the hinges and lying coincident with a hinged-surface hinge axis and extending through the aligned center passageways of the hinges of the hinge assembly. A lock is selectively operable to lock the hinged surface to the support when the actuator shaft engages the lock. An actuator structure is controllably operable to move the actuator shaft longitudinally along the hinge-surface hinge axis between a first shaft axial position wherein the actuator shaft engages the lock and the hinges, and a second shaft axial position wherein the actuator shaft does not engage the lock but does engage the hinges, and is controllably operable to rotate the actuator shaft about the hinged-surface hinge axis.

Unmanned surveillance air vehicles, glide munitions, winged missiles, and other types of air vehicles are sometimes configured to be carried internally or externally on a larger mother aircraft. Because the carried air vehicle itself is usually small and typically has a limited range, it is flown to a location near to where it is to perform its mission, as cargo on the mother aircraft, and then air launched to perform the mission. The carried air vehicle may later be recovered, or it may be considered expendable and destroyed at the completion of the mission.
The carried air vehicle has laterally extending wings, which make it awkward to store the carried air vehicle on the mother aircraft. To facilitate the internal or external storage and transport on the mother aircraft, the carried air vehicle may be provided with folding wings. The folding wings are in a folded storage position during carriage, and then are unfolded to a deployed flight position either shortly prior to launch or shortly after launch from the mother aircraft.
In most of these carried air vehicles, the wings have hinged control surfaces pivotably attached to the trailing edges. These control surfaces must be retained in a fixed position when the wing is in the folded storage position so that they do not flutter and do not become pivotably displaced to some unknown angle. After deployment, the control surfaces must be in a known, defined position ready to perform their function in aiding in the control of the air vehicle.
Accomplishing the positioning of the control surfaces with wing-mounted structure is not difficult in conventional circumstances. However, with increasing air vehicle speeds and smaller air vehicles, design considerations have mandated the use of thinner wings, in some cases about 3 inches or less thick. The conventional locks, structures, and drives required for the control surfaces cannot be sufficiently miniaturized to be accommodated within these very thin wings.
Consequently, there is a need for an approach to positioning and moving the control surfaces of wings that is suitable for use with thin wings. The present invention fulfills this need, and further provides related advantages.

Structural mechanism for unlocking and engaging a controllable surface on a hinged platform (Wing)


Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. A manufacturing method of a semiconductor device according to one embodiment is to carry out resin sealing using a metal member such as leadframe which has been subjected to alloying treatment of a base material and Zn plated on the surface thereof.

The present invention relates to a semiconductor device, particularly, a technology effective when applied to, for example, a resin-sealing type semiconductor device using a metal member.
Semiconductor devices used in the automotive field and the like are used under a severe usage environment so that they are required to have much higher reliability compared with those for consumer use or industrial use. In resin-sealing type semiconductor devices using a metal member, peeling of the sealing resin from the metal member (metal lead or the like) occurs due to moisture absorption of the resin and thermal stress in the sealing body (package). This peeling becomes a cause for generation of cracks at the joint between a semiconductor element and the metal member, leading to formation of defective semiconductor devices.
As a conventional method for firmly bonding a metal member and a sealing resin, a method of roughening the surface of the metal member by plating or etching is known.
For example, Japanese Patent Laid-Open No. 148508/1997 (Patent Document 1) discloses as follows relating to a resin-sealing type semiconductor device. A needle-like or dendritic roughened layer is formed by electroplating a Cu-based or Fe-based leadframe with Cu, CuNi, Zn, Ni, or the like at a current density exceeding the critical current density. A covering layer is then formed on the resulting roughened layer by electroplating it with two Cu and Zn layers, CuZn, Cr, ZnCr, two Ni and InZn layers, NiP, or two Ni and CuZn layers at a current density not greater than the critical current density. The roughened layer and the covering layer cooperatively contribute to improvement in bond strength between the leadframe and the resin and improvement in reliability such as moisture resistance, thermal shock resistance, or the like.
Japanese Patent Laid-Open No. 2002-299538 (Patent Document 2) discloses as follows relating to a leadframe and a semiconductor package using it. The surface of the leadframe to be brought into contact with a sealing resin is subjected to roughening plating, followed by plating, with a metal, a portion on the plated leadframe and necessary for wire bonding.
Japanese Patent Laid-Open No. 46116/1996 (Patent Document 3) discloses as follows relating to a leadframe. Either one of the following methods is used for forming a roughened surface on at least a portion of the surface of the leadframe to be molded. One of them is etching Cu or Ar in an aqueous solution containing a water soluble reducing agent such as ferric chloride or hydrazine. The other one is electrolytic etching with a nitrate-based electrolyte under treatment conditions of a voltage of 10V or greater but not greater than 50V and an anode current density of 40 A/dm2 or greater but not greater than 200 A/dm2. Formation of such a roughened surface improves adhesion between the leadframe and the molding resin.    Patent Document 1: Japanese Patent Laid-Open No. 148508/1997    Patent Document 2: Japanese Patent Laid-Open No. 2002-299538    Patent Document 3: Japanese Patent Laid-Open No. 46116/1996

Semiconductor device and method of manufacturing the same


The invention provides a frozen product of boiled noodles of Japanese buckwheat, which has an improved feel in eating and can sustain the improved feel in eating for a long term, and a chilled or frozen product of raw noodles of Japanese buckwheat, which has an improved feel in eating when boiled and can sustain the improved feel in eating for a long term. The frozen product of raw or boiled noodles of Japanese buckwheat employs, as dough materials, a mixture of at least gluten, partially decomposed substances of wheat protein, an edible oxidant and/or an edible reductant, and trehalose. More specifically, the noodles contain, as dough materials, 90-30 weight parts of buckwheat flour, 10-65 weight parts of wheat flour, 0.5-5 weight parts of gluten, 0.5-5 weight parts of an edible oxidant and/or an edible reductant, 0.5-5 weight parts of partially decomposed substances of wheat protein, and 0.5-5 weight parts of trehalose. The frozen product of boiled noodles of Japanese buckwheat is adaptable for microwave cooking.

1. Field of the Invention
The present invention relates to a frozen product of raw or boiled noodles of Japanese buckwheat (soba).
2. Description of the Related Art
In boiled noodles, a proper resistance to the teeth, i.e., a certain level of stiffness with a sufficient elasticity, is generally demanded and medium or rather-hard wheat flour having a relatively high protein content is used as a main material. To improve the feel in eating, for example, potato starch, waxy cornstarch, tapioca starch, etc. are added to wheat noodles (udon) for increasing glutinosity, and vital gluten separated from wheat flour is added to Chinese noodles and soba for increasing the resistance to the teeth. Also, an agent for improving the noodle quality is proposed in which viscosity-increasing polysaccharides, whey minerals, and starches are mixed with whey protein.
Meanwhile, recent widespread use of microwave ovens has increased the number of kinds and the amount of frozen products. However, when noodles are frozen, icy crystals grow during preservation in the frozen state, which eventually causes separation of free water. This raises a problem that starch contained in the noodles deteriorates and the stiffness of the noodles is lost.
In commercially available boiled noodles of Japanese buckwheat (soba), because a long time is required for the production process in a factory and the distribution process after the production, the feel in eating is remarkably reduced during such a long time. Also, it is known that, in the case of eating soba in soup, for example, since noodles are dipped in the soup too long, the noodles are too softened, whereby the feel in eating is deteriorated and the taste is degraded. Further, there are quick-cooking noodles that can be cooked just by heating them with a microwave oven or hot water, or by mixing an attached source or soup with the noodles before or after heating them. Those quick-cooking noodles are required to have a long-term preservative ability at the normal temperature, and hence are sterilized under heating in an acidic range. As a result of such sterilization, soba loses its specific resistance to the teeth, i.e., stiffness, and the feel in eating becomes a rather crumbly. In addition, since those raw noodles are subjected to treatment for conversion to α-starch, they inherently contain water at a high content. This leads to disadvantages that the noodles tend to stick to each other, are hard to separate individually even upon pouring of hot water, and are less convenient when eating. Thus, there have been various problems that noticeably degrade the value of noodle products.

Frozen product of raw or boiled noodles of Japanese buckwheat (


Methods and architectures for implementing a scalable multi-database event processing system are provided. In one embodiment, selected account data is aggregated for all subscribers (aggregated subscriber-specific data) and a copy included on each database. In one embodiment, selected data that is not subscriber specific and that may apply to many accounts (“global data”) is also maintained and copied to each database. The global data preferably includes business data that is frequently required during operation of the system, such as pricing data. A transaction that requires business data and access to an account is processed using the copy of the business data that is on the database on which the account is located. In an embodiment, the aggregated subscriber-specific data is used in performing searches.

The present invention relates to event processing systems and systems that are suitable for electronic business. More specifically, the invention relates to event processing systems which use multiple databases.
With the increasing growth of on-line business and globalization of business, very large accounting systems have become necessary. Such large accounting systems typically require multiple databases, or very complicated programming. In general, the accounting systems must be high performance and able to process an event, as well as access data, very quickly.
It is known to maintain several separate distributed databases having customer-specific data. An additional database having non-customer-specific data may also be maintained. Processing a transaction often requires data that is located in more than one database. For example, a system may need pricing data stored on one database, as well as account information stored on a separate distributed database on which the account resides. When two databases are accessed, a "two-phase commit" procedure is used in order to maintain consistency of the data, as will be appreciated by those skilled in the art. A two=phase commit procedure synchronizes the data and locks both databases for the duration of the transaction. The two-phase commit slows down the transaction, and also makes the databases involved unavailable for other uses. The data synchronization process involves a high overhead that applies to many transactions. Such systems are generally not capable of delivering the fast performance that is increasingly being demanded in large event processing systems.
An additional problem with conventional distributed databases is that operations requiring data from multiple databases are often cumbersome to program. For example, to run billing on all accounts typically requires that a programmer create a billing computer program that is tailored to query each database.
In addition, accounts are typically assigned to a particular database based on an account characteristic, such as billing address. This makes it relatively easy to find the correct database if the characteristic, e.g., billing address, is known. However, finding an account based on a different characteristic, such as a login name, may require a full search. Another disadvantage is that, once chosen, the criteria on which accounts are assigned to a database are inflexible, in order to allow searching based on the criteria to be relatively easy, among other reasons. This creates a potential single point of failure for creation of new accounts and other administrative functions. For example, when each database is assigned to a geographic region, if a database is down, no users from that region may be added to the database.
Accordingly, implementing a multi-database system that is scalable to very large systems; i.e., that has low overhead per transaction and does not use the two-phase commit, would be desirable. It would further be desirable if the system provided data location transparency, and if some flexibility were available in the assignment of customers to a database so that a database is substantially always available for adding new users.

Scalable multi-database event processing system using universal subscriber-specific data and universal global data


Compounds of formula (I): ##STR1## [in which: either (a) the dotted line ( ) is a single bond; A=is oxygen; and B is a group of formula (II): ##STR2## (in which m is 0 and n is 0 or 1) or (b) the dotted line ( ) is a double bond; A=is said group of formula (II) in which m is 1 and n is 0 or 1; and B is absent; and R.sup.1 is hydrogen, halogen, alkyl, alkenyl, alkynyl, optionally substituted benzyl or optionally substituted phenyl; R.sup.2 is hydrogen, halogen, alkyl, optionally substituted phenyl or heterocyclic; or R.sup.1 and R.sup.2, together with the carbon atoms to which they are attached, are a hydrocarbon ring fused to the isoxazole ring; R.sup.3 and R.sup.4 are each hydrogen, alkyl, optionally substituted benzyl or optionally substituted phenyl; or R.sup.3, R.sup.4 and the nitrogen atom to which they are attached together represent an alicyclic amino group]; and salts thereof may be used for the treatment of cerebral circulatory problems and for use as centrally acting muscle relaxants.

The present invention relates to a series of new isoxazole derivatives, which are regarded as derivatives of isoxazolones, and which may be used for the treatment of cerebral circulatory problems and for use as centrally acting muscle relaxants. The invention also provides methods of using these compounds and processes for preparing them.
Cerebrovascular disorders, including stroke infarction, are among the main causes of death in the world today. Moreover, although the patient may survive in such cases, cognition impairment, which may be one of the sequelae of the disease, is a substantial social problem at present. For this reason, the development of therapeutic agents for the treatment of such disorders (commonly referred to as "cerebro-active drugs") is required.
Moreover, rigidity and/or spasticity are often observed as the sequelae of cerebrovascular disorders, such as cerebral stroke infarction, or as cerebrotraumatic sequelae, and make rehabilitation difficult. Centrally-acting muscle relaxants are available which can relieve such spasrigido hemiplegia, and act on the central nervous system. Examples of existing centrally-acting muscle relaxants include eperisone hydrochloride and afloqualone.
An object of the present invention is to provide new compounds which can be used as cerebro-active drugs and as centrally-acting muscle relaxants. Such compounds are needed which can treat cerebral circulatory problems and alleviate myotony and spasrigido hemiplegia, preferably without giving rise to accompanying drowsiness.
It is also a related object to provide a method of treating cerebrovascular disorders by the administration to a mammal, which may be human, suffering from or prone to cerebrovascular disorders of at least one cerebro-active drug.
Certain isoxazolone derivatives within the scope of formula (I) of the present invention are known which have the required effect. For example, Japanese Patent Application Kokai (i.e. as laid open to public inspection) Sho. No. 56-34674, discloses such compounds having anti-inflammatory, analgesic and anti-pyretic activities.
Additionally, certain compounds closely related to those of the present invention are disclosed in Japanese Patent Application Kokai Sho. No. 52-31070 (published March 1977) as discussed in detail below.

Isoxazole derivatives for use as cerebro-active drugs and central muscle relaxants


A special type of random access memory referred to as video random access memory (VRAM) is used through to provide multiple access to the memory in a timely manner. The VRAM is characterized by a random access port which enables random accessing to the memory array and a serial port comprising a shift register for outputting a large group of bits of data, such as pixels representative of a scan line of a video image, which are rapidly output by the memory. In the present invention, the VRAM is utilized in a different manner to provide more efficient use of memory without degradation in system performance. The VRAM provides for communications between processors as well as the memory utilized by the coprocessor for storage of code and data. Communications between processors is performed through the serial port; therefore, data is communicated via blocks of data transfers minimizing the frequency of access to the memory array. The co-processor, which utilizes the memory for processing and code storage, communicates with the memory through the random access port in order for the co-processor to perform its functions in a timely manner. The co-processor will only be interrupted in its access of the memory when it is determined that blocks of data are to be transferred into the or out of the memory via the serial port.

1. Field of the Invention
The method and apparatus of the present invention is directed to a co-processor de-coupling bus for communications between processors.
2. Art Background
To increase the efficiency of a system, it is quite common to provide multiple or co-processors in addition to a main processor and off-load predetermined functions or computations to the co-processors in order to decrease the processing overhead of the main processor. These co-processors are often specialized for a particular task or type of task. For example, math co-processors and graphics co-processors are widely used. The co-processor typically functions as a slave to the master or main CPU. Communications between the co-processors are achieved through a bus, shared memory or a combination of the two.
Typically, a separate shared memory is provided for communication of data and instructions between processors. A polling and/or interrupt mechanism is provided in each processor such that each processor knows when instructions and/or data is placed in the shared memory to be accessed by the processor. To save on space and achieve the greatest memory utilization, a single memory such as a dynamic random access memory (DRAM) is used to provide memory for storage of code and data utilized by the co-processor to perform its tasks. The memory functions as the shared memory utilized for communications between the host processor and co-processor. For example, as shown in FIG. 1, DRAM 10 is used for storing data communicated between the main processor 20 and co-processor 30 via a shared memory 40 as well as for storing the code and data utilized by co-processor 30.
As the co-processor 30 is using the memory for storage of code to be executed by the co-processor as well as storage of data to perform the functions, the co-processor will be accessing the memory quite frequently. However, while the co-processor 30 is accessing the DRAM 10 to retrieve code or data 50, the main processor 20 is attempting to also access the DRAM 10 in order to communicate information to the co-processor 30 or retrieve information from the co-processor 30 through the shared memory 40. Thus, an arbitration mechanism 60 is required to determine which access will be permitted as only one access to the physical DRAM chip may be performed at any time.
However, both processors are slowed down measurably due to the inefficient utilization of the DRAM subsystem. For example, it is likely that the physical locations of memory accessed by the main processor and co-processor are far apart in the address space of the memory. The accesses by the main processor and co-processor are therefore likely to result in a large number of "far" cycles. A far cycle occurs when the page mode of the memory subsystem cannot be used. Thus, the number of far accesses to the memory array by both processors is increased.
In order to gain the system performance benefit from the use of a co-processor, the time required for communicating instructions and data from the main processor 20 to the co-processor 30, executing the instruction by the co-processor 30 and communicating the results of the execution to the main processor 20 must be less than the time required for the main processor itself to execute the instructions. Therefore it is quite important that the communications are performed as efficiently as possible with minimal effect on the performance of the co-processor 30.


An apparatus disclosed relates to a technique for applying adhesive tape to a workpiece. The apparatus includes a chuck table for receiving and holding the workpiece, a tape feeding device for feeding adhesive tape in strip form toward the workpiece held by the chuck table, an applying device for placing an applicator roller in contact with a surface of the adhesive tape and applying the adhesive tape to a surface of the workpiece, and a vibration generating mechanism for vibrating the applicator roller.

(1) Field of the Invention
This invention relates to a technique for applying adhesive tape such as protective tape to surfaces of workpieces such as semiconductor wafers, lead frames or various printed circuit boards.
(2) Description of the Related Art
Methods of planarizing semiconductor wafers (hereinafter simply called "wafers") include mechanical methods such as grinding and polishing (CMP), and chemical methods using etching. When these methods are used to planarize the wafers, protective adhesive tape (hereinafter simply called "protective tape") is applied to the front surfaces of the wafers to protect the wafer surfaces having circuit patterns formed thereon.
In a back-grinding apparatus, for example, the front surface (pattern surface) of a wafer loaded therein is suction-supported by a chuck table and the back surface of the wafer is ground with a grinder. At this time, the back surface of the wafer is ground, with the protective tape applied to the front surface of the wafer to avoid the pattern being damaged under the stress of grinding and to avoid contamination of the pattern.
In processing the back surface of the wafer, the protective tape may not be applied to the front surface of the wafer to have the adhesive of the protective tape filling irregularities, particularly depressions, on the front surface, and to have the surface of the tape in a substantially planar state. Then, the following problems are encountered.
The water used in time of back-surface processing infiltrates into spaces in the depressions. Further, the wafer has a greater overall thickness at elevated portions than at depressed portions. The thicker portions may be ground to be the thinner, resulting in the inconvenience of lowering the accuracy of processing thickness over the wafer surface.
In order to avoid such an inconvenience, it has been conventional practice to increase the pressure of an applicator roller for pressing the adhesive tape on the wafer surface, to heat the wafer through the chuck table and soften the adhesive, thereby facilitating filling of the depressions, or to combine these measures. In this way, an attempt has been made to apply the protective tape reliably even to the irregularities on the patterned surface.
However, both of these measures of increasing the pressure of the applicator roller and heating the wafer invariably apply the protective tape by forcibly deforming the protective tape itself. Consequently, the wafer processed to be thin could be subjected to an increased curvature under the influence of a stress stored in the protective tape forcibly deformed.
Moreover, there have been increased cases in recent years of back-surface processing of wafers, such as flip chips, having bumps formed thereon. Such wafers tend to have increased level differences on the surfaces. Thus, a desire exists for an adhesive tape applying technique capable of coping with such large level differences.

Adhesive tape applying method and apparatus


A multi-channel receiver automatically determines the noise floor of each channel and resets the channel threshold based thereon while avoiding undesirable bias from weak non-noise signals. The power probability of uncharacterized input signals (non-noise content unknown) is computed and normalized to have a known probability that the power exceeds a first threshold. A second probability of exceeding a second threshold is determined and compared to a predetermined reference probability for a noise-only signal at the same threshold. If the computed second probability is not higher than the reference probability, then the uncharacterized signal is a noise only signal whose average is the noise floor for the channel. The threshold detection level is then set a predetermined amount above the noise floor. The process is automatic and compensates for receiver aging and ambient noise fluctuations with time and from channel to channel and for other changes.

There is a great need in communication and other electronic systems for obtaining maximum sensitivity to information signals in the presence of noise. As used herein, the word "noise" is intended to refer to random electrical signals and the word "non-noise" is intended to refer to signals which are not random noise. Non-limiting examples of noise signals are Gaussian noise signals. Nonlimiting examples of non-noise signals are coherent signals, carrier signals and modulated signals.
It is common in the electronic art, particularly the communication art to provide a detection threshold gate at the apparatus input to prevent noise signals from triggering false alarms in the apparatus. Often the threshold is adjusted according to the needs of the user, sometimes being set to a low level (i.e., close to the ambient noise level) when great sensitivity is desired and at other times being set to a higher level (i.e., substantially above the ambient noise level) when blanking a strong source is more important than great sensitivity.
In some communication systems where maximum sensitivity is desired, the threshold is set close to the ambient noise level. That is, the ambient noise level is determined and the threshold level (i.e., the level at which the input gate opens to admit a received signal) is set above the ambient noise level by a small pre-determined amount. This ambient noise level is referred to in the art as the "noise floor". When the amplitude of the input signal exceeds the noise floor by the predetermined amount, the gate "opens" admitting the incoming signal to the receiver (i.e., "enabling" the receiver), and when the input signal is less than the predetermined amount, the gate "closes" thereby blocking the input signal from the receiver. The foregoing arrangement for muting receivers is well known in the art.
Despite the widespread use of detection threshold systems in the prior art, several problems remain:
First, in many instances, manual real time adjustment of the threshold level is not possible. In these situations, individual threshold levels are generally preset at conservative levels and thereafter remains unchanged. One of the difficulties with this approach is that it does not take into account aging of the receiver components or changes in supply voltage or other time dependent effects which may cause the signal appearing at the input signal detector to vary in amplitude. While the receiver may still be capable of amplifying these input signals to useful levels, they now fall below the preset fixed detection threshold and are no longer admitted to the receiver. Thus, as the receiver ages, the detector no longer admits such signals and they are lost. Conversely, a drop in the detection threshold due to receiver aging or a rise in the background noise level will trigger the detector, leading to false alarms, i.e., false signal detection.
Second, the threshold level cannot be set to optimally enable the receiver unless the ambient noise floor is known with some precision. Unfortunately, the noise floor is not constant but varies with time. Unless a means is available for conveniently measuring the noise floor and recalibrating the system, the threshold level must be set sufficiently high so that even under the worst anticipated noise conditions, the probability of false alarm is still acceptable, This results in much more conservative threshold settings than is desired.
Third, in multichannel receivers, the individual channels usually have variations in front-end receiver sensitivity, especially in receivers built to operate at very high frequencies and wide bandwidths. This is illustrated in FIG. 1 wherein undulating curve 12 shows the variation in receiver sensitivity (e.g., input gain) across channels 1-N of a multichannel receiver operating, for example, in the 2.0-4.0 GHz range. Curve 12 also depicts the channel-to-channel variation in the noise floor presented to the detector or receiver. As a consequence of such input sensitivity (or noise floor) variations, the signal levels presented to the threshold detection circuitry vary from channel to channel.
In the prior art it has been customary to assign one fixed noise floor threshold, e.g., line 14 in FIG. 1, for each of the channels irrespective of any input sensitivity (or noise floor) variations over time. Detection threshold 14 exceeds the largest anticipated noise signal from channel 16 by some predetermined amount 18. Noise margin 18 is chosen to provide a predetermined false alarm rate for noise triggering of the channel 16 detector. A result of this prior art approach is that while detection threshold 14 and margin 18 are initially appropriate, the optimum threshold level will change because of receiver aging and changes in the ambient noise levels, so that after a time, the detection threshold is no longer optimum.
Thus, there is an ongoing need to dynamically adjust the detection threshold of receiver channels automatically so as to take into account, for example, aging of receiver input components, and/or channel-to-channel sensitivity and noise floor variations in multichannel receivers with time from channel to channel.
As used herein the word "gain" is intended to include attenuation, the word "receiver" is intended to include any type of apparatus for processing or detecting or measuring or analyzing input signals, the word "signal" or "signals" is intended to include signals of any kind, including but not limited to noise signals, modulated signals, carrier signals and combinations thereof, and the word "uncharacterized" with respect to input signals is intended to refer to signals whose non-noise content is unknown, i.e., which may be either substantially pure noise or noise plus non-noise.

Automatic noise characterization for optimally enabling a receiver


In one embodiment, a cryocooler assembly for cooling a heat load is provided. The cryocooler assembly includes a vacuum vessel surrounding the heat load and a cryocooler at least partially inserted into the vacuum vessel, the cryocooler including a coldhead. The assembly further includes an actuator coupled to the cryocooler. The actuator is configured to translate the cryocooler coldhead into thermal engagement with the heat load and to maintain constant pressure of the coldhead against the heat load to facilitate maintaining thermal engagement with the heat load as the heat load shrinks during a cool down process.

The field of the disclosure relates generally to cooling assemblies and, more particularly, to cryocooler assemblies.
Known cryocoolers can achieve low temperatures at their coldheads for removing heat from an electrical machine such as a superconducting generator. Typically, the coldheads in a two stage cryocooler are located at the end of the first and second stage portions of the cryocooler. In some known applications, the cryocooler coldheads are connected to surfaces, such as radiation shields, from which heat is to be removed. During a cool down process, the cryocooler coldheads may eventually become a source of heat and the heads may be manually detached from the cooled surfaces by an operator to further facilitate cooling operations. However, manual movements of cryocoolers located in remote locations, for example in a wind turbine nacelle, are costly, time consuming and inconvenient.

Remote actuated cryocooler for superconducting generator and method of assembling the same