A plasma enhanced CVD apparatus includes a processing chamber, a pumping system for evacuating the processing chamber, a gas inlet system for introducing a source gas, and a plasma generating electrode provided in the processing chamber for depositing a film on a substrate in the processing chamber by plasma generated by electrical power supplied to the plasma generating electrode; the plasma generating electrode has two terminals, one of the terminals is connected to a radio frequency power source and other of the terminals is grounded through an electrode potential controlling system; and the processing chamber is grounded through an inner wall potential controlling system. The present invention is further directed to a plasma enhanced CVD process, a dry etching apparatus, and a dry etch process.

1. Field of the Invention
The present invention relates to a plasma enhanced CVD apparatus having a plasma generating electrode in its processing chamber and a process for using it. The present invention further relates to an apparatus for dry etching having a plasma generating electrode in its processing chamber, and a process for using it.
2. Description of the Related Art
Plasma enhanced CVD is a thin film deposition method in which a film is deposited on a substrate by the chemical reaction of source gases using plasma. Plasma enhanced CVD has been widely applied to various thin film deposition processes, e.g., semiconductor IC devices, superconductive devices, various electronic devices, metal films comprising various sensors, semiconductor films, insulation films, photoconductor films, barrier films, and adhesion films. In addition, dry etching is a widely used method for etching such thin films by the chemical reaction of an etching source gas using plasma. In recent years, low-pressure, high-density plasma has attracted the attention of semiconductor engineers in such plasma processing methods. Low-pressure, high-density plasma enables novel processing which has not been realized, and improves processing efficiency.
Prior art will be explained using a plasma enhanced CVD apparatus as an example below. In general, a plasma generating electrode is used to generate plasma in a processing chamber and a radio frequency power is applied to the plasma generating electrode. Plasma generating electrodes are classified as either capacitively coupling types or inductively coupling types, or from a different viewpoint, as external electrode types each having an electrode outside its processing chamber, and internal electrode types each having an electrode inside its processing chamber. Among them, capacitively coupling and internal electrode-type parallel plate plasma enhanced CVD apparatus have been most widely used.
In a parallel plate plasma enhanced CVD apparatus, two electrodes are oppositely provided to each other so as to apply radio frequency power, low frequency power, direct current power, and time-modulated powers thereof to one of them, and to ground the other. Another electrode may be grounded through a capacitor, coil (inductor), or a combination of the capacitor and coil. These parallel plate electrodes are provided to generate and sustain plasma by the interaction caused by collisions between charged particles and between charged particles and the two electrodes after accelerating charged particles by means of an electrostatic field between the two electrodes. The parallel plate plasma enhanced CVD apparatus can hardly generate and sustain plasma under a pressure of 100 mtorr or less. Thus, low-pressure, high-density plasma cannot be generated in such an apparatus.
Inductively coupling types of plasma generating methods have been widely used to generate low-pressure, high-density plasma, as described in, for example, "Novel Development in Low-Pressure, High-Density Plasma" by Hideo Sugai (Applied Physics, Vol. 63, No. 6, pp. 559-567, (1994)). In the inductively coupling-type apparatus, plasma is generated and sustained by the electromagnetic induction caused by current variance of a plasma generating antenna. That is, the plasma is generated and sustained by the interaction between electromagnetic waves and charged particles. Thus, this type can provide low-pressure, high-density plasma since it can generate and sustain plasma even under a pressure of 100 mtorr or less.
In the inductively coupling types, external antenna types have been widely used, wherein a plasma generating antenna is provided outside the processing chamber. In detail, a coil or deformed loop plasma generating antenna is provided around the outside of the discharge chamber, which is made of dielectric materials, to generate the low-pressure, high-density plasma. However, such external antenna types have a drawback. When a film having relatively high conductivity, such as a conductive film or a semiconductive film (hereinafter "conductive film"), is prepared, some of the conductive film is deposited on the inner wall of the dielectric discharge chamber so that electromagnetic waves radiated from the plasma generating antenna provided around the discharge chamber are shielded by the conductive film deposited on the inner wall. Such deposition often causes unstable plasma in the discharge chamber or sometimes causes a failure in plasma generation. Accordingly, the inner wall of the discharge chamber must be frequently cleaned when a conductive film is deposited on a substrate with an external antenna-type plasma generating apparatus.
A method in which an inductively coupling-type antenna is placed inside the processing chamber (hereinafter "internal antenna type") is known as the method compensating for the drawback of the external antenna type, as described in "Hideo Sugai, Kenji Nakamura, Keiji Suzuki: Japanese Journal of Applied Physics Vol. 33(1994) pp. 2189-2193", as well as the above Sugai's article. A sputtering apparatus using such an internal antenna is disclosed in Japanese Laid-Open Patent No. 7-18433.
In the internal antenna-type plasma generating apparatus disclosed in the above article by Sugai et al., an antenna comprising substantially a loop coil of one-turn is provided inside the processing chamber. One terminal of the antenna is connected to a radio frequency power, and the other terminal is grounded. The antenna surface is covered with a dielectric so as to stabilize the plasma. When a conductive film is deposited on a substrate with such a plasma generation apparatus, the following problems will occur. A conductive film deposits on the antenna surface when the conductive film is deposited on the substrate by plasma enhanced CVD. Further, when a metal substrate is etched by dry etching, gaseous metal compounds adhere to the antenna surface and deposit on the antenna surface as a metal film. After the conductive film deposits on the antenna surface covered with a dielectric, the plasma generating state changes with the progress of the substrate processing. Thus, the reproducibility of the substrate processing is lost after a long time batch processing of the substrate. Further, the plasma is unstably generated due to a decreased effect of the dielectric cover. Thus, the antenna surface must be frequently cleaned.
In the plasma generating apparatus disclosed in the aforementioned article by Sugai, a negative direct current bias voltage is induced on the surface of the dielectric cover of the antenna by means of a radio frequency power applied to the antenna. A potential difference between the direct current bias voltage and the plasma potential accelerates positive ions to an extent that the positive ions impinge the dielectric cover on the antenna surface to sputter the dielectric cover. As a result, when such a plasma generating apparatus is used for film deposition, the deposited film may be contaminated with materials from the dielectric cover so it is difficult to deposit a highly pure film.
When the dielectric cover is not provided on the antenna surface in the plasma generating apparatus in Sugai et al., although the above-mentioned problems do not occur, other problems will occur as follows. Since one end of the antenna is grounded so as to pass through a direct current, no direct current bias potential occurs in the antenna, but the antenna potential symmetrically varies between positive and negative with time from the ground potential as the standard due to the radio frequency power applied to the antenna. Charged particles such as electrons and positive ions flow into the antenna due to the variability of the antenna potential with time. Since the mass of electrons is extremely smaller than those of positive ions, electrons have a higher kinetic energy in the electric field. Thus a much greater amount of electrons flows into the antenna than positive ions. On the other hand, since no direct current bias potential occurs in the antenna, the plasma potential necessarily shifts to a positive potential side so that the overall charge of charged particles flowing into the antenna is balanced. The electric field increases between the inner wall of the processing chamber and the plasma, and thus the positive ions are further accelerated toward the inner wall. As a result, a larger amount of secondary electrons are generated by the collision of accelerated positive ions with the processing chamber, and local continuous self-discharge occurs in any place of the inner wall. The inner wall is heated by the continuous discharge, resulting in hot cathode arc discharge. In such an arc discharge mode, a large current flows between the plasma and the inner wall of the processing chamber. Although the space potential in the plasma decreases thereby to temporarily cease the continuous discharge, the space potential in the plasma increases again to cause the continuous discharge between the plasma and the inner wall. In such a way, since the space potential in the plasma periodically and significantly varies, stable plasma cannot be achieved. Further, because the inner wall of the processing chamber is locally overheated by the hot cathode arc discharge, the metal material comprising the processing chamber evaporates to result in the contamination of the processed substrate. When no dielectric cover is provided as described above, the electron density in the plasma is remarkably low compared to the case with a dielectric cover even if the input power is increased. Thus, low-pressure, high-density plasma cannot be achieved by such a method.
In the above sputtering apparatus in Japanese Laid-Open Patent No. 7-18433, a loop antenna of one-turn is provided inside the processing chamber, a terminal of the antenna connects to the radio frequency power and the bias direct current power, and another terminal is grounded through a direct current-blocking capacitor. The antenna itself is used as the target material of the sputtering apparatus. If regarding this apparatus as a plasma generating apparatus and comparing this with the above apparatus by Sugai, there are two differences between them. In the former apparatus no dielectric cover is used for the antenna and one terminal of the antenna is grounded through a capacitor so as not to cause direct current to flow. As a result of such differences, the problems of the apparatus by Sugai are solved in the former apparatus.
However, the present inventors found the following problems when a film is deposited on a substrate by plasma enhanced CVD using the plasma generating apparatus disclosed in Japanese Laid-Open Patent No. 7-18433. That is, in that apparatus, a high bias direct current is applied to the antenna for sputtering the antenna. The film deposition by plasma enhanced CVD using such a high bias direct current causes an excessive sputtering effect. Thus, excellent conformal step coverage of fine contact holes inherent in CVD cannot be achieved. Further, the antenna cannot be used for a long time period due to etching prompted by sputtering. When the direct current bias power and the direct current-blocking capacitor are removed from this apparatus in order to reduce the sputtering effects, other new problems occur, i.e., discharge is unstable and low-pressure, high-density plasma cannot be achieved.
Japanese Unexamined Patent Publication No. 7-254500 discloses a plasma processing device having a plasma generating coil. The position of the plasma generating coil is adjustable. In addition, the surface of the plasma generating coil may be covered with an insulating member, or the plasma generating coil may be formed from a pipe to allow a heating medium to pass therethrough.

Plasma enhanced CVD apparatus and process, and dry etching apparatus and process


A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

1. Field of the Invention
The present invention relates to a semiconductor memory device and to a circuit technology through which a low-voltage operation is implemented.
2. Background Art
Conventional art semiconductor memory devices include, for example, a semiconductor memory device disclosed in Patent Document 1, the configuration of a contact-type mask ROM is disclosed.
FIG. 12 is a circuit diagram showing the configuration of the contact-type mask ROM. With the contact-type mask ROM, whether the drains of memory cell transistors are connected to bit lines corresponds to the "1" and "0" states of storage data.
The conventional art semiconductor memory device shown in FIG. 12 includes a memory cell array 1, a column decoder 15, and a read circuit 16.
The memory cell array 1 includes memory cells M(i, j) (i=1 to m, and j=1 to n) each composed of a N-type MOS transistor and arranged in matrix form. As for the memory cells M (i, j), the gates of the memory cells M(i, j) whose positional symbols (i) represent the same numeric value, that is, the gates of the memory cells M(i, j) aligned in the row direction are together connected to common word line selection signal lines WLi (i=1 to m). Also, the sources of the memory cells M (i, j) are connected to a wiring having a ground potential.
When the drains of the memory cells M(i, j) (i=1 to m, and j=1 to n) are connected to bit lines BLj (j=1 to n), output data read from the memory cells M(i, j) (i=1 to m, and j=1 to n) to an output terminal MDATA becomes "1", while in a floating state in which the connections are not made, output data read to the output terminal MDATA becomes "0".
The column decoder 15 includes N-type MOS transistors QNCj (j=1 to n). The drains of the N-type MOS transistors QNCj (j=1 to n) are connected with one another, their sources are connected to the bit lines BLj (j=1 to n), and their gates are each connected to column selection signal lines CDj (j=1 to n).
The read circuit 16 includes P-type MOS transistors QPPS and QPL, a N-type MOS transistor QNRS, and an inverter INVA. With the P-type MOS transistor QPPS, its gate is connected to a precharge control signal line PCLK, its source is connected to a power supply potential line, and its drain is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15.
With the N-type MOS transistor QNRS, its gate is connected to a reset control signal line RSTS, its source is connected to a ground potential line, and its drain is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15.
With the inverter circuit INVA, its input end is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15, and its output end is connected to the output terminal MDATA.
With the P-type MOS transistor QPL, its gate is connected to the output end of the inverter INVA, its source is connected to the power supply potential line, and its drain is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15.
The ON-state current of the P-type MOS transistor QPL is set so as to become smaller than those of the memory cells M(i, j) (i=1 to m, and j=1 to n) and to become equal to or larger than the total OFF leakage current of all the memory cells aligned on the single bit line.
The reading operation of data of, for example, the memory cell M(1, 1) of the semiconductor memory device having such a configuration will be described with reference to a FIG. 13 timing chart.
Among the column selection signal lines CDj (j=1 to n), the column selection signal line CD1 is brought high and the column selection signal lines CD2 to CDn are brought low. As a result, among the transistors constituting the column decoder 15, the transistor QNC1 is turned on and the other transistors QNC2 to QNCn are turned off.
Also, the reset control signal line RSTS is brought low and the transistor QNRS is turned off. Furthermore, all the word lines WL1 to WLm are brought low and all the memory cell transistors M(i, j) (i=1 to m, and j=1 to n) are turned off.
Then the precharge control signal line PCLK is held high for a fixed time period and the transistor QPPS is held on for a fixed time period, thereby the bit line BL1 is charged to the high level.
After the bit line BL1 has brought to high, the word line WL1 is shifted from the low level, which means a non-selected state, to the high level which means a selected state.
As a consequence, when the drain of the memory cell M(1, 1) is connected to the bit line BL1, electric charge supplied to the bit line BL1 is discharged by the memory cell M(1, 1), so that the bit line BL1 is brought low. In contrast to this, the drain of the memory cell M(1, 1) is not connected to the bit line BL1, the electric charge supplied to the bit line BL1 is not discharged by the memory cell M(1, 1), so that the bit line BL1 is held high.
Because of this, when the drain of the memory cell M(1, 1) is connected to the bit line BL1 to brought the bit line BL1 low, the low-level signal is inputted to the inverter INVA via the on-state transistor QNC1. As a result, the inverter INVA inputs a high-level signal to the gate of the transistor QPL to turn the transistor QPL off, thereby charging to the bit line BL1 is stopped and the high-level signal is outputted to the output terminal MDATA.
In contrast to this, when the drain of the memory cell M(1, 1) is not connected to the bit line BL1 to brought the bit line BL1 high, the high-level signal is inputted to the inverter INVA via the on-state transistor QNC1. As a consequence, the inverter INVA inputs a low-level signal to the gate of the transistor QPL to turn the transistor QPL on, thereby charging is effected to compensate for electric charge discharged from the bit line BL1 due to the OFF leakage currents of the memory cells M(i, 1) (i=1 to m) connected to the bit line BL1. As a result, the bit line BL1 is held high and a low-level signal is outputted to the output terminal MDATA.
Patent Document 1: Japanese Unexamined Patent Publication H06-176592. (page 2, paragraphs 0002 to 0006 and FIG. 2)
Problems brought about by the conventional art semiconductor memory device will be described below. With the configuration of the conventional art semiconductor memory device, the drains and sources of the transistors QNCj (j=1 to n) constituting the column decoder 15 are each connected to the read circuit 16 and the bit lines BLj (j=1 to n) without ground connections. Because of this, the threshold voltages at the transistors QNCj (j=1 to n) are increased by the substrate bias effect. The influence of the increased threshold voltages resulting from the substrate bias effect becomes large as the power supply voltage is decreased, so that the ON-state current of the transistors QNCj constituting the column decoder 15 is decreased greatly. Therefore, the supply of the electric charge to the bit lines BLj cannot be provided sufficiently by the transistor QPL provided to the read circuit 16 to compensate for the OFF leakage currents developed at the memory cells connected to the bit lines. As a consequence, the potentials at the drains of the transistors QNCj, which constitute the column decoder 15 connected to the read circuit 16, cannot be shifted to the low level, so that the potentials are held at the high level. Therefore, the function of the semiconductor memory device is impaired.
In recent years, as a need for operation effected with low power supply voltage has been increased rapidly with the advance of techniques for manufacturing smaller semiconductor devices, it has been particularly required that apparatus provided with semiconductor memory devices feature low power consumption to pursue their portability and so on. However, because of the suppression of power consumption increased by the OFF leakage current of transistors, it is difficult to lower the threshold voltage at the transistors; hence, this not only exists as a determinant of the range of the power supply voltage with which the semiconductor memory devices operate but brings about a big problem in the implementation of low-power semiconductor memory devices.
As a result, methods for lowering only the threshold voltage at some transistors during their manufacture and for reducing the substrate bias effect through the boost of the gate voltage at some transistors have been proposed. To lower the threshold voltage during their manufacture, however, there is a necessity to provide special manufacturing steps in addition to normal ones. In addition, to boost the gate voltage, there is a necessity to provide a booster circuit having a relatively large area, which brings about increases in not only the size of semiconductor memory devices but their production cost.

Semiconductor memory device having bit line precharge circuit controlled by address decoded signals

Matsushita Electric Industrial Co., Ltd.


A process is described for controlling the size of additive or catalyst particles mixed with heavy hydrocarbon oil feedstock containing asphaltenes and metals and being subjected to hydrotreating. A slurry feed of a mixture of the heavy hydrocarbon oil feedstock and coke-inhibiting additive particles or catalyst particles is passed upwardly through a confined vertical hydrotreating zone in the presence of hydrogen gas, while removing from the top of the hydrotreating zone a mixed effluent containing a gaseous phase comprising hydrogen and vaporous hydrocarbon and a liquid phase comprising heavy hydrocarbon. The mixed effluent is passed through a separation vessel, while withdrawing from the top of the separator a gaseous stream comprising hydrogen and vaporous hydrocarbons and withdrawing from the bottom of the separator a liquid stream comprising heavy hydrocarbons and particles of coke-inhibiting additive or catalyst. At least part of the liquid stream containing heavy hydrocarbons and particles is recycled and an aromatic oil is added to the hydrotreating zone in an amount sufficient to substantially inhibit adsorption of asphaltenes on the surfaces of the particles and subsequent agglomeration of the additive or catalyst particles.

This invention relates to the treatment of hydrocarbon oils and, more particularly, to the hydrotreating of heavy hydrocarbon oils in the presence of particulate additives.
Hydroconversion processes for the conversion of heavy hydrocarbon oils to light and intermediate naphthas of good quality for reforming feedstocks, fuel oil and gas oil are well known. These heavy hydrocarbon oils can be such materials as petroleum crude oil, atmospheric tar bottoms products, vacuum tar bottoms products, heavy cycle oils, shale oils, coal derived liquids, crude oil residuum, topped crude oils and the heavy bituminous oils extracted from oil sands. Of particular interest are the oils extracted from oil sands and which contain wide boiling range materials from naphthas through kerosene, gas oil, pitch, etc., and which contain a large portion of material boiling above 524.degree. C. equivalent atmospheric boiling point.
As the reserves of conventional crude oils decline, these heavy oils must be upgraded to meet the demands. In this upgrading, the heavier materials is converted to lighter fractions and most of the sulphur, nitrogen and metals must be removed.
This can be done either by a coking process, such as delayed of fluidized coking, or by a hydrogen addition process such as thermal or catalytic hydrocracking. The distillate yield from the coking process is typically about 80 wt % and this process also yields substantial amounts of coke as by-product.
Work has also been done on an alternate processing route involving hydrogen addition at high pressures and temperatures and this has been found to be quite promising. In this process, hydrogen and heavy oil are pumped upwardly through an empty tubular reactor in the absence of any catalyst. It has been found that the high molecular weight compounds hydrogenate and/or hydrocrack into lower boiling ranges. Simultaneous desulphurization, demetallization and denitrogenation reactions take place. Reaction pressure up to 24 MPa and the temperature up to 490.degree. C. have been employed.
Research has been conducted on additives which can suppress coking reaction or can remove the coke from the reactor. It has been shown in Ternan et al., Canadian Patent No. 1,073,389, issued Mar. 10, 1980 and Ranganathan et al., U.S. Pat. No. 4,214,977, issued Jul. 29, 1980, that the addition of coal or coal-based additive results in the reduction of coke deposition during hydrocracking. The coal additives act as sites for the deposition of coke precursors and thus provide a mechanism for their removal from the system.
Ternan et al., Canadian Patent No. 1,077,917 describes a process for the hydroconversion of a heavy hydrocarbonaceous oil in the presence of a catalyst prepared in situ from trace amounts of metals added to the oil as oil soluble metal compounds.
In U.S. Pat. No. 3,775,286, a process is described for hydrogenating coal in which the coal was either impregnated with hydrated iron oxide or dry hydrated iron oxide powder was physically mixed with powdered coal. Canadian Patent No. 1,202,588 describes a process for hydrocracking heavy oils in the presence of an additive in the form of a dry mixture of coal and an iron salt, such as iron sulphate.
Particularly useful additive particles are those described in Belinko et al., U.S. Pat. No. 4,963,247, issued Oct. 16, 1990. Thus, the particles are typically ferrous sulfate having particle sizes less than 45 .mu.m and with a major portion, i.e. at least 50% by weight, preferably having particle sizes of less than 10 .mu.m.
Development of such additives has allowed the reduction of reactor operating pressure without coking reaction. However the injection of large amounts of fine additive is costly, and the application is limited by the incipient coking temperature, at which point mesophase (a pre-coke material) is formed in increasing amounts.
Heavy hydrocarbon oils typically contain asphaltenes and metals which can lead to deactivation of catalysts and agglomeration of particulate additives. The asphaltenes are present as a colloidal suspension which during hydrotreating tends to be adsorbed on the surfaces of the particles and also cause the particles to agglomerate. Jacquin et al., in U.S. Pat. No. 4,285,804 try to solve the problem of asphatenes by a rather complex process in which a solution of fresh metal catalyst is injected into fresh feedstock prior to heating.
Further, it is shown in Jain et al., U.S. Pat. No. 4,969,988 that conversion can be further increased through reduction of gas hold-up by injecting an anti-foaming agent, preferably into the top section of the reactor.
Sears et al., U.S. Pat. No. 5,374,348 teaches recycle of heavy vacuum fractionator bottoms to the reactor to reduce overall additive consumption by 40% more.
It is the object of the present invention to provide a process for hydrotreating heavy hydrocarbon oils using additive particles in the feedstock to suppress coke formation in which improved utilization of additive particles can be achieved by retarding the tendency of the asphaltenes to be adsorbed on the surface of the particles and thereby retard the subsequent agglomeration of the particles.

Hydrotreating of heavy hydrocarbon oils with control of particle size of particulate additives


In a heterogeneous network based on LTE, the random access, RA, procedure triggered in a macrocell produces transmissions from a UE (20) on the physical random access channel, PRACH, which a picocell eNB (12) can attempt to make measurements of for interference coordination purposes over the X2 interface between the macro eNB (10) and the pico eNB (12). By reconfiguring the UE's behavior during principally the contention-free RA procedure, its transmissions on PRACH are made different to the default such as to be suitable for heterogeneous network interference measurements. This is done by assigning new meanings to certain of the characteristic parameters provided by the macro eNB (10) to the UE (20), such as the RA preamble it uses and the C-RNTI it is assigned during the procedure. Interpreting these new meanings allows the UE (20) to temporarily re-configure its PRACH transmissions so as to be useful to the pico eNB's (12) interference measurement needs without disrupting the UE's existing configuration within the macrocell, and without the UE needing to know the purpose of its transmissions.

Wireless communication networks are widely known in which base stations (BSs) communicate with user equipments (UEs) (also called terminals, or subscriber or mobile stations) within range of the BSs.
The geographical area covered by one or more base stations is generally referred to as a cell, and typically many BSs are provided in appropriate locations so as to form a network or system covering a wide geographical area more or less seamlessly with adjacent and/or overlapping cells. (In this specification, the terms "system" and "network" are used synonymously except where the context requires otherwise). Each BS divides its available bandwidth into individual resource allocations for the user equipments which it serves. The user equipments are generally mobile and therefore may move among the cells, prompting a need for handovers between the base stations of adjacent and/or overlapping cells. A user equipment may be in range of (i.e. able to detect signals from) several cells at the same time, and it is possible for one cell to be wholly contained within a larger cell, but in the simplest case the UE communicates with one "serving" cell.
The direction of communication from the base station to the UE is referred to as the downlink (DL), and that from the UE to the base station as the uplink (UL). Two well-known transmission modes for a wireless communication system are TDD (Time Division Duplexing), in which downlink and uplink transmissions occur on the same carrier frequency and are separated in time, and FDD (Frequency Division Duplexing) in which transmission occurs simultaneously on DL and UL using different carrier frequencies.
Resources in such a system have both a time dimension and a frequency dimension. In LTE, the resources in the time domain are organised in units of frames, each having a plurality of "subframes". Frames follow successively one immediately after the other. An FDD frame consists of 10 uplink subframes and 10 downlink subframes occurring simultaneously. An FDD frame has duration of 10 ms and each subframe a duration of 1 ms. In TDD, the 10 subframes are shared between UL and DL and various allocations of subframes to downlink and uplink are possible, depending on the load conditions. Subframes may consequently be referred to as uplink subframes or downlink subframes.
The basic system architecture in LTE is illustrated in FIG. 1. As can be seen, each UE 20 connects over a wireless link via a Uu interface to an eNodeB (eNB) 10, which defines one or a number of cells for wireless communication.
Each eNB 10 in turn is connected by a (usually) wired link using an interface called S1 to higher-level or "core network" entities, including a Serving Gateway (S-GW 22), and a Mobility Management Entity (MME 21) for managing the network and sending control signalling to other nodes, particularly eNBs, in the network. These are shown in combined form in the Figure. The links to the core network are referred to as "backhaul". The backhaul is defined as the transport network which allows connecting all network nodes together, namely each eNB to the core network entities and each eNB to its neighbour eNB if needed. Generally, backhaul is based on Internet Protocol (IP), and for femto stations only (HNBs and HeNBs), backhaul may be over existing broadband infrastructure in homes and offices
In FIG. 1, the S1 interface is labelled S1-U, the suffix U denoting the user plane employed by the eNBs 10 for communicating user data to and from the S-GW 22. The S-GW is responsible for packet forwarding of user data on the downlink to the UE 20 and on the uplink. The S-GW 22 provides a "mobility anchor" for the user plane during handovers of a UE 20 from one eNB 10 to another.
In parallel to this, there is an interface S1-MME (sometimes called S1C) via which the eNBs 10 exchange control messages with the MME 21. The main function of the MME 21, as its name suggests, is to manage mobility of the UEs 20, and it is a signalling-only entity. The MME 21 is also responsible for controlling security (including authenticating users). In practice, there may be several MMEs forming a MME "pool". One eNB can have several S1-MME interfaces towards several MMEs.
In addition, as shown in FIG. 1, the eNBs 10 communicate among themselves by a (usually) wireless link, using an interface called X2 for mutual co-ordination, for example when handing over a UE 20 from one eNB to another. There is only one X2 interface between two eNBs. The application layer signalling protocol is referred to as X2AP.
Several "channels" for data and signalling are defined at various levels of abstraction within the network. FIG. 2 shows some of the channels defined in LTE at each of a logical level, transport layer level and physical layer level, and the mappings between them.
At the physical layer level, on the downlink, user data as well as System Information Blocks (SIBs) are contained in a transport channel DL-SCH, carried on the Physical Downlink Shared Channel (PDSCH). As can be seen from FIG. 2, PDSCH also carries a paging channel PCH at the transport layer level. There are various control channels on the downlink, which carry signalling for various purposes; in particular the Physical Downlink Control Channel, PDCCH, is used to carry, for example, scheduling information from a base station (called eNB in LTE) to individual UEs being served by that base station. The PDCCH is located in the first OFDM symbols of a slot.
Each base station broadcasts a number of channels and signals to all UEs within range, whether or not the UE is currently being served by that cell. Of particular interest for present purposes, these include a Physical Broadcast Channel PBCH as shown in FIG. 3, as well as (not shown) a Primary Synchronization Signal PSS and Secondary Synchronization Signal SSS. PBCH carries a so-called Master Information Block (MIB), which gives, to any UEs within range of the signal, basic information including system bandwidth, number of transmit antenna ports, and system frame number. Reading the MIB enables the UE to receive and decode the SIBs referred to earlier.
Meanwhile, on the uplink, user data and also some signalling data is carried on the Physical Uplink Shared Channel (PUSCH), and control channels include a Physical Uplink Control Channel, PUCCH, used to carry signalling from UEs including channel quality indication (CQI) reports and scheduling requests.
The Physical Random Access Channel PRACH is used to carry the Random Access Channel (RACH) for accessing the network if the UE does not have any allocated uplink transmission resource. If a scheduling request (SR) is triggered at the UE, for example by arrival of data for transmission on PUSCH, when no PUSCH resources have been allocated to the UE, the SR is transmitted on a dedicated resource for this purpose. If no such resources have been allocated to the UE, the RA procedure is initiated. The transmission of SR is effectively a request for uplink radio resource on the PUSCH for data transmission.
Thus, RACH is provided to enable UEs to transmit signals in the uplink without having any dedicated resources available, such that more than one terminal can transmit in the same PRACH resources simultaneously. The term "Random Access" (RA) is used because (except in the case of contention-free RACH, described below) the identity of the UE (or UEs) using the resources at any given time is not known in advance by the network. Preambles (which when transmitted, produce a signal with a signatures which can be identified by the eNB) are employed by the UEs to allow the eNB to distinguish between different sources of transmission.
Situations where the RACH process is used include:                Initial access from RRC_IDLE        RRC connection re-establishment        Handover        DL data arrival in RRC_CONNECTED (when non-synchronised)        UL data arrival in RRC_CONNECTED (when non-synchronised, or no SR resources are available)        Positioning (based on Timing Advance)
RACH can be used by the UEs in either of contention-based and contention-free modes. In contention-based RA, UEs select any preamble at random, at the risk of "collision" at the eNB if two or more UEs accidentally select the same preamble. Contention-free RA avoids collision by the eNB informing each UE which preambles may be used.
The RA procedure can be triggered in response to a PDCCH order (e.g. for DL data arrival, or positioning). Contention free RA in Release-8/9/10 is only applicable for handover, DL data arrival and positioning.
Referring to FIG. 3, the RA procedure typically operates as follows (for contention based access):—
(i) As already mentioned the UE 20 receives the downlink broadcast channel PBCH for the cell of interest (serving cell). This is indicated by (0) in the Figure.
(ii) The network, represented in FIG. 3 by eNB 10, indicates cell specific information including the following:                resources available for PRACH        Random Access Preambles (henceforth, "preambles") available (up to 64)        preambles corresponding to small and large message sizes.
(iii) The UE 20 selects a PRACH preamble according to those available for contention based access and the intended message size.
(iv) The UE 20 transmits the PRACH preamble (also called "Message 1", indicated by (1) in the Figure) on the uplink of the serving cell. The network (more particularly the eNB 20 of the serving cell) receives Message 1 and estimates the transmission timing of the UE.
(v) The UE 20 monitors a specified downlink channel for a response from the network (in other words from the eNB 10). The UE monitors this channel for a specified length of time, the RAR window shown in the Figure. In response to the UE's transmission of Message 1, the UE receives a Random Access Response or RAR ("Message 2" indicated by (2) in FIG. 3) from the network. This is described in more detail below.
(vi) In response to receiving Message 2 from the network, the UE 20 makes a scheduled transmission on PUSCH ("Message 3" as indicated by (3) in the Figure) using the UL grant and TA information contained in Message 2.
(vii) A contention resolution message may be sent from the network (in this case from the eNB 10) in the event that the eNB received the same preamble simultaneously from more than one UE, and more than one of these UEs transmitted Message 3.
If the UE 20 does not receive any response from the eNB, the UE selects a new preamble and sends a new transmission in a RACH subframe after a random back-off time.
For contention-free RA, the procedure is simpler:
(i) The eNB configures the UE with a preamble from those available for contention-free access.
(ii) The UE transmits the preamble (Message 1) on the uplink of the serving cell.
(iii) The UE receives the RAR (Message 2) via PDSCH from the network, which contains an UL grant for transmission on PUSCH. The resource to be used for RAR is again signalled on PDCCH using CSS.
In both contention-based and contention-free RA procedures, the RAR contains a Temporary Cell Radio Network Temporary Identifier (C-RNTI) which identifies the UE. The C-RNTI is used to address UL transmission to the cell by identifying the UE in later UL transmissions.
In the contention-based procedure, the UE transmits this C-RNTI back to the eNB in Message 3 and, if more than one UE does so there will be a collision at the eNB which may then initiate the contention resolution procedure.
In both contention-based and contention-free RA procedures, the RAR contains:                A Timing Advance command;        A UL Grant; and        A Temporary Cell Radio Network Temporary Identifier (C-RNTI).
At the physical layer, the 20-bit UL Grant is interpreted as the Random Access Response Grant (RARG), and contains amongst others things an indication of the UL resources and transmit power control (TPC) to be used for the forthcoming transmission on PUSCH.
The various fields of the RAR and RARG may or may not be relevant to a given RA procedure, depending on whether it is contention-based or contention-free, and depending on its purpose.
The Temporary C-RNTI becomes permanent after contention-resolution and further attempts in the contention-based RA procedure.
In order to manage, e.g., scheduling and congestion issues in the downlink, the eNB is given a window of time to send the RAR. This is the RAR window mentioned earlier and shown in FIG. 3, and is configurable from two to ten milliseconds (corresponding to two to ten subframes), depending upon the choice of system parameters. The UE is required to monitor the whole RAR window to detect if the eNB has acknowledged its preamble transmission. If no RAR is received within the RAR window then typically the RA preamble is re-transmitted.
Further details of the RA procedure in LTE are given in the document 3GPP TS 36.321, hereby incorporated by reference.
As already mentioned, cells may be overlapping or even entirely contained within a larger cell. This is particularly the case for so-called Heterogeneous Networks.
FIG. 4 schematically illustrates part of a heterogeneous network in which a macro base station 10 covers a macrocell area (indicated by the large outer ellipse), within which there are other, overlapping cells (the smaller ellipses) formed by a pico base station 12 (picocell) and femto base stations 14. As shown a UE 20 may be in communication with one or more cells simultaneously, in this example with the macro cell and the picocell. The cells may not have the same bandwidth; typically, the macro cell will have a wider bandwidth than each pico/femto cell.
Some definitions are as follows:                Heterogeneous Network: A deployment that supports a mixture of more than one of macro, pico, femto stations and/or relays in the same spectrum.        Macro base station—conventional base stations that use dedicated backhaul and open to public access. Typical transmit power ˜43 dBm; antenna gain ˜12-15 dBi.        Pico base station—low power base station with dedicated backhaul connection and open to public access. Typical transmit power range from ˜23 dBm-30 dBm, 0-5 dBi antenna gain;        Femto base station—consumer-deployable base stations that utilize consumer's broadband connection as backhaul; femto base stations may have restricted association. Typical transmit power <23 dBm.        Relays—base stations using the same radio spectrum for backhaul and access. Similar power to a Pico base station.
In LTE, an example of a femto base station is the so-called Home eNodeB or HeNB.
The installation by network customers of base stations with a localised network coverage cell, such as femto base stations (Home eNodeBs) is expected to become widespread in future LTE deployments. A femto base station or pico base station can be installed in, for example, a building within which network subscriber stations experience high path loss in transmissions with a macro cell. Femto and pico base stations can be installed by a customer in his own premises. The femto and picocells thereby formed can improve network coverage, but for coordination among the various cells, it is preferable that they be able to exchange information with the macro cell (more precisely the MeNB 10 of FIG. 4), in some cases with other cells, and that they are synchronized with one another.
Pico eNBs and femto eNBs differ in that a pico eNB supports the X2 interface with a macro eNB, whilst a femto cell (HeNB), in current LTE specifications, does not always support the X2 interface with a macro eNB. However, since a femto cell has an S1 interface to the core network, it would be possible in principle for it to receive such exchanges over S1. The term "picocell" will henceforth be used to cover both femto and picocells, and "peNB" used to cover both a pico and femto base station.
Consider now a heterogeneous network (HetNet) in which UEs operate within the coverage of at least two cells: a macrocell to which they are presently connected and a picocell to which they may cause uplink (UL) interference. The picocell eNodeB (peNB) and macrocell eNodeB (MeNB) are able to exchange information (normally over the X2 interface), and the macrocell is able to effect handover of any macro-connected UE (MUE) to the picocell, making it a pico-connected UE (pUE).
The peNB may need to estimate the UL interference MUEs are causing so that it can provide load information to the MeNB in order to facilitate, e.g. re-scheduling of UL transmission in the macrocell or handover of certain MUEs to the picocell whence they will no longer cause interference in the picocell. It is preferred that solutions to this should not rely on tight synchronization among the layers of the network. Therefore, on the uplink, using the Random Access (RA) procedure and measuring the transmission on the Physical Random Access Channel (PRACH) are a useful solution.
It has been proposed in the above scenario that the MeNB triggers, via a PDCCH order, a contention-free RA procedure from a UE. The peNB is informed over X2 of the resources and preamble the UE will use, and the peNB can then measure the received signal and use this to estimate the interference the UE will cause when transmitting, e.g., PUSCH and PUCCH.
Following this proposal, the UE will expect the contention-free RA procedure to run to full completion, including, for example, re-transmission of the preamble or the RAR if the procedure does not complete successfully the first time. However, the peNB may be able to obtain satisfactory interference estimates without the procedure being fully complete, and there could thus be wasted transmit power, signalling, and processing effort at both the UE and eNBs, which could additionally disrupt conventional RA procedures in the macrocell by occupying resources. Furthermore, the RA procedure in LTE allows for power ramping if the preamble is not received successfully at the eNB. This is undesirable in the scenario considered here since ideally the transmission on PRACH would have a power approximately the same as typical transmission on PUSCH. Additionally, power-ramping would make it difficult to form a meaningful time-average of the interference at the peNB. Trying to use the X2 interface from the peNB to MeNB to trigger, terminate, configure, etc. a contention-free RA procedure in the macrocell according to the peNB's interference measurement needs will be too slow compared to the several millisecond timescale of the RA procedure at lower layers.
Therefore, schemes that minimise wasted procedures and associated signalling, whilst enabling suitable interference measurements at the peNB to be configured in a timely manner, are of significant interest.

Interference measurement in heterogeneous networks


A damper and seal system for a stage of a turbine that includes inner shrouds disposed circumferentially of a hot gas path through the turbine stage and shroud body(s) for supporting the inner shroud(s). A damper block engages a backside surface of the inner shroud and a damping mechanism is carried by the shroud body and connected to the damper block for applying a load to the damper block and inner shroud through the engagement of the block with the backside surface of the inner shroud, thereby damping vibratory movement of the inner shroud. The seal system includes at least one primary, integral seal and at least one secondary, non-integral seal to limit axial and radial hot gas leakage through the stage.

It will be appreciated that the shrouds are subject to vibration due to the pressure pulses of the hot gases as each blade or bucket passes the shroud. Moreover, because of this proximity to high-speed rotation of the buckets, the vibration may be at or near resonant frequencies and thus requires damping to maintain life expectancy during long-term commercial operation of the turbine.
Ceramic matrix composites offer advantages as a material of choice for shrouds in a turbine for interfacing with the hot gas path. The ceramic composites offer high material temperature capability. Ceramic composites, however, are difficult to attach and have failure mechanisms such as wear, oxidation due to ionic transfer with metal, stress concentration and damage to the ceramic composite when configuring the composite for attachment to the metallic components.
U.S. application Ser. Nos. 10/700,251 and 10/793,051 provide an attachment mechanism between a ceramic composite shroud and a metallic support structure which utilizes the pressure distribution applied to the shroud, coupled with a loading on the shroud to tune the shroud to minimize damaging vibratory response from pressure pulses of the hot gases as the buckets pass the shrouds.


The present invention relates to a wireless communication system, and more specifically, to a method and apparatus for accessing channels in a wireless LAN system. The method for accessing channels in a station (STA) of the wireless communication system according to one embodiment of the present invention comprises the steps of transmitting a first frame of a channel access request to an access point (AP); and receiving, from the AP, a second frame related to whether access to the channel is allowed in response to the first frame, wherein the second frame can include a value for a channel access start offset with respect to the STA.

Recently, with development of information communication technology, various wireless communication technologies have been developed. Among others, a wireless local area network (WLAN) enables wireless access to the Internet using a portable terminal such as a personal digital assistant (PDA), a laptop, a portable multimedia player (PMP) in a home, an enterprise or a specific service provision area based on radio frequency technology.
In order to overcome limitations in communication rate which have been pointed out as weakness of a WLAN, in recent technical standards, a system for increasing network speed and reliability and extending wireless network distance has been introduced. For example, in IEEE 802.11n, multiple input and multiple output (MIMO) technology using multiple antennas in a transmitter and a receiver has been introduced in order to support high throughput (HT) with a maximum data rate of 540 Mbps or more, to minimize transmission errors, and to optimize data rate.

This patent is subject to a terminal disclaimer.

Method and apparatus for accessing channels in wireless LAN system


An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

1. Field of the Invention
The invention relates generally to the field of semiconductor devices and fabrication and, more particularly, to memory elements and methods for making memory elements.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in one or more memory devices that are coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. For instance, volatile memories, such as dynamic random access memories (DRAMs), must be continually powered in order to retain their contents, but they tend to provide greater storage capability and programming options and cycles than non-volatile memories, such as read only memories (ROMs). While non-volatile memories that permit limited reprogramming exist, such as electrically erasable and programmable "ROMs," all true random access memories, i.e., those memories capable of 1014 programming cycles are more, are volatile memories. Although one time programmable read only memories and moderately reprogrammable memories serve many useful applications, a true nonvolatile random access memory (NVRAM) would likely be needed to surpass volatile memories in usefulness.
Efforts have been underway to create a commercially viable memory device that is both random access and nonvolatile using structure changing memory elements, as opposed to the charge storage memory elements used in most commercial memory devices. The use of electrically writable and erasable phase change materials, i.e., materials which can be electrically switched between generally amorphous and generally crystalline states or between different resistive states while in crystalline form, in memory applications is known in the art and is disclosed, for example, in U.S. Pat. No. 5,296,716 to Ovshinsky et al. The Ovshinsky patent contains a discussion of the general theory of operation of chalcogenide materials, which are a particular type of structure changing material.
As disclosed in the Ovshinsky patent, such phase change materials can be electrically switched between a first structural state, in which the material is generally amorphous, and a second structural state, in which the material has a generally crystalline local order. The material may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states. In other words, the switching of such materials is not required to take place in a binary fashion between completely amorphous and completely crystalline states. Rather, the material may be switched in incremental steps reflecting changes of local order to provide a "gray scale" represented by a multiplicity of conditions of local order spanning the spectrum from the completely amorphous state to the completely crystalline state.
These memory elements are monolithic, homogeneous, and formed of chalcogenide material typically selected from the group of Te, Se, Sb, Ni, and Ge. This chalcogenide material exhibits different electrical characteristics depending upon its state. For instance, in its amorphous state the material exhibits a higher resistivity than it does in its crystalline state. Such chalcogenide materials may be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods with the input of picojoules of energy. The resulting memory element is truly non-volatile. It will maintain the integrity of the information stored by the memory cell without the need for periodic refresh signals, and the data integrity of the information stored by these memory cells is not lost when power is removed from the device. The memory material is also directly overwritable so that the memory cells need not be erased, i.e., set to a specified starting point, in order to change information stored within the memory cells. Finally, the large dynamic range offered by the memory material theoretically provides for the gray scale storage of multiple bits of binary information in a single cell by mimicking the binary encoded information in analog form and, thereby, storing multiple bits of binary encoded information as a single resistance value in a single cell.
Traditionally, the operation of chalcogenide memory cells requires that a region of the chalcogenide memory material, called the "active region," be subjected to a current pulse to change the crystalline state of the chalcogenide material within the active region. Typically, a current density of between about 105 and 107 amperes/cm2 is needed. To obtain this current density in a commercially viable device having at least one million memory cells, for instance, one theory suggests that the active region of each memory cell should be made as small as possible to minimize the total current drawn by the memory device.
However, such traditional chalcogenide memory cells have evolved into what is referred to as a programmable metallization cell or a plated chalcogenide memory cell for use in a plated chalcogenide random access memory (PCRAM) device. Such a cell includes a chalcogenide material between opposing electrodes. A fast ion conductor material is incorporated into the chalcogenide material. The resistance of such material can be changed between highly resistive and highly conductive states.
To perform a write operation with the memory cell in its normal high resistive state, a voltage potential is applied to a certain one of the electrodes, with the other of the electrode being held at zero voltage or ground. The electrode having the voltage applied to it functions as an anode, while the electrode held at zero or ground functions as a cathode. The nature of the fast ion conductor material is such that it undergoes a chemical and structural change at a certain applied voltage level. Specifically, at some suitable threshold voltage, the metal ions within the chalcogenide material begin to plate on the cathode and progress through the chalcogenide material toward the anode. The process continues until a conductive dendrite or filament extends between the electrodes, effectively interconnecting the top and bottom electrodes to create an electrical short circuit.
Once this occurs, dendrite growth stops, and the dendrite is retained when the voltage potentials are removed. This results in the resistance of the chalcogenide material between the electrodes dropping by a factor of about 1,000. The material can be returned to its highly resistive state by reversing the voltage potential between the anode and cathode to cause the dendrite to disappear. Again, the highly resistive state is maintained when the reverse voltage potential is removed. Accordingly, such a device can, for example, function as a reprogrammable memory cell of non-volatile random access memory circuit.
As mentioned above, the variable resistance material disposed between the electrodes typically is a chalcogenide material having metal ions diffused therein. A specific example is germanium selenide with silver ions. Typically, to provide the silver ions within the germanium selenide material, germanium selenide is deposited onto the first electrode using chemical vapor deposition. A thin layer of silver is then deposited on the glass, for example by physical vapor deposition or another technique. The layer of silver is then irradiated with ultraviolet radiation. The thin nature of the deposited silver allows the energy to pass through the silver to the silver/glass interface to cause the silver to diffuse into the chalcogenide material. The applied energy and overlying silver result in the silver migrating into the glass layer such that a homegenous distribution of silver throughout the layer is ultimately achieved.
Unfortunately, chalcogenide materials are relatively delicate. The nature of the deposition technique used to deposit the silver can damage the chalcogenide material and, thus, adversely affect the resulting memory cell. Furthermore, it can be challenging to etch and polish chalcogenide materials. Accordingly, it would be desirable to develop memory cell fabrication methods that avoid steps that can damage such materials.


The gaming apparatus of the present invention comprises a variable display unit configured to variably display a plurality of symbols, a front side display unit located in front of the variable display unit and configured to enable viewing of the symbols displayed by the variable display unit, a concealing unit located between the variable display unit and the front side display unit and configured to temporarily conceal the display of the variable display unit, an internally winning prize determiner configured to determine an internally winning prize, a stopping controller configured to stop the varying of display of the variable display unit based on a result of determination by the internally winning prize determiner, and wherein a prize is awarded if a stopped stare displayed on the variable display unit, which is caused by the stopping controller, matches a prescribed stopped state.

1. Field of the Invention
The present invention relates to a gaming apparatus, such as slot machine, pachinko machine or other gaming apparatus, which comprise a variable display means to variably display symbols required for a game and a controller to control the varying of the display.
2. Description of the Related Art
Conventionally, as an aforementioned type of gaming apparatus, a slot machine which comprises a stopping means to stop varying of the display, as so-called "pachi-slo" gaming apparatus is known. FIG. 1 shows a conventional pachi-slo gaming apparatus X.
The pachi-slo gaming apparatus X comprises, three reels 104 to 106, which variably display a plurality of symbols, in display windows 101 to 103 on a face panel 100, and a variable display unit configured with reel stop buttons 107 to 109, to stop the reels 104 to 106. If a prescribed symbol combination lines up on the variable display unit, a return is given to a player of the pachi-slo gaming apparatus X.
Further, winning lines, which relate to nine (9) symbols formed by three (3) rows× three (3) lines are printed on a front side of the face panel 100. These winning lines are a one medal winning line 111 in the middle, which becomes active if one medal is inserted, two medal winning lines 112a, 112b, which become additionally active if two medals arc inserted, and three medal winning lines 113a, 113b, which become additionally active if three medals are inserted. In FIG. 1, the pachi-slo gaming apparatus X also has a game token insertion slot 114 configured to accept a game token (e.g., medal or coin) and a start lever 115 configured to start a game.
Incidentally, regarding the variable display unit, besides the above mechanical type using the reels 104 to 106, there is also a display unit which can variably display symbols using a liquid crystal display (LCD), etc.
As for procedure of playing game, a game is started by insertion of a game token into the game token insertion slot 114. The controller then controls the variable display unit to spin the reels 104 to 106 according to an operation of the start lever 115 by the player, and symbols are then variably displayed.
The variably displayed symbols stop automatically after a certain period of time or stop according to an operation of the reel stop buttons 107 to 109 so as to stop spinning of the reels 104 to 106 one after the other. As a result, if symbols on the reels 104 to 106 appeared within the display windows 101 to 103 reach a certain combination (winning combination), game tokens are paid out so that a return can be given to the player.
The aforementioned pachi-slo gaming apparatus X has a plurality of winning modes. Specifically, in a case where the player wins a prescribed prize, in addition to a single payout of medals, a game state is transferred to an advantageous state for the player for a certain period of time rather than the normal game state. As for such prizes, there are a big bonus (hereinafter referred to as "BB"), which allows a certain number of games serving relatively a bigger return to the player, and a regular bonus (hereinafter referred to as "RB"), which allows a certain number of games serving relatively a smaller return to the player.
Further, in the pachi-slo gaming apparatus X, a combination of symbols that lines up along the active winning lines 111 to 113 (hereinafter referred to as "active line") is internally sampled (hereinafter referred to as "internal sampling"), and winning is determined based on the result of internal sampling and a timing when the player performs a stopping operation by pushing of the reel stop buttons 107 to 109.
In other words, in order to win a prize which medals or coins are paid out, it is necessary that winning as a result of internal sampling (hereinafter referred to as "internally winning") and that the player performs the stopping operation at a timing that allows lining up of the combination corresponding to the prize acquired by internally winning (hereinafter referred to as "internally winning prize") along the active line(s).
It means that even if the internally winning is achieved, the prize is not awarded in a case where the timing of the stopping operation is not appropriate. Therefore, a technique of performing the stopping operation in a timely manner (which is called "see-and-push" and which intervention of player's technique is high) is required, and such a type of pachi-slo gaming apparatus has become major today.
Regarding such a type of pachi-slo gaming apparatus, various techniques have been recently proposed to display the symbols as well as the winning lines 111 to 113 on the face panel 100 in order to improve attractiveness and to ease identification of the winning prizes.
For example, in the gaming apparatus described in the Japanese patent publication No. H4-220276, three pairs of LCD shutters are placed in a row in front of a display window corresponding to the three reels and displaying a winning symbol combination at completion of the game. On the other hand, the gaming apparatus activates the LCD shutter to conceal corresponding to the six rest positions that display non-winning symbols so as to display only the winning symbol combination.
Further, in the gaming apparatus described in the Japanese patent publication No. P2000-350805, an information display panel having some transparency is placed on the rear or close to the rear of the face panel and is configured with a matrix display unit enabling display by a dotted pattern using dots formed by a plurality of lines and columns. Moreover, the information display panel is configured by a transparent electronic luminescent (EL) panel in order to display characters and symbols, etc. on the panel by a dotted pattern.
However, in the gaming apparatus comprising the above described LCD shutters (i.e., Japanese patent publication No. H4-220276), although the winning symbol combination can be clearly displayed by concealment of the non-winning symbols, a lot of winning lines including lines that are not active are continuously displayed. It is therefore difficult to view the symbols on the respective reels. Further, it is required to additionally integrate a variety of indication lamps and indicators, etc., which causes the structure of the gaming apparatus to become complex.
Further, in the gaming apparatus comprising the information display panel (i.e., Japanese patent publication No P2000-350805), although display of only the active lines and various information including images for entertainment can be accomplished, is the symbols of the respective reels are viewed through the dotted pattern because the information display panel is transparent.
Accordingly, it is a problem that both the images for entertainment and the symbols of the respective reels may not be displayed clearly.

Gaming apparatus with a variable display unit and concealing unit to temporarily conceal the variable display unit


To provide an aqueous ink, particularly, an inkjet recording ink, and an inkjet recording method, which can form an image having good color hue and excellent fastness to light and active gases in the environment, particularly, ozone gas, the aqueous ink has a polyazo dye containing at least two azo groups, an ionic hydrophilic group, and a sulfur-containing 5-membered heterocyclic group; and an inkjet recording ink and an inkjet recording method each using the aqueous ink.

1. Field of the Invention
The present invention related to an aqueous ink comprising at least one disazo or polyazo dye, and also relates to an inkjet recording ink and an inkjet recording method.
2. Background Art
The coloring agent used in an inkjet recording ink is required to have high solubility or dispersibility in a solvent, enable high-density recording, provide good color hue, be resistant to light, heat and active gases in the environment (for example, oxidative gases such as NOx and ozone, and SOx), exhibit excellent fastness to water and chemicals, ensure good fixing property to an image-receiving material and less bleeding, give an ink having excellent storability, have high purity and no toxicity, and be available at a low cost. However, it is very difficult to find out a coloring agent satisfying these requirements in a high level. In particular, a black dye providing good color hue for compensating a color corresponding to a longer wavelength side in a black color, exhibiting fastness to light, humidity and heat, and exhibiting fastness to oxidative gases in the environment such as ozone when the image is printed on an image-receiving material having an ink-receiving layer containing a porous inorganic white pigment particle, are strongly demanded.
Azo coloring matters comprising a sulfur-containing heterocyclic coupler as a coupling component of an azo dye have been heretofore disclosed, for example, in JP-A-54-46226 (the term "JP-A" as used herein means an "unexamined published Japanese patent application"), JP-A-54-139638, JP-A-60-235866, JP-A-2001-207092, JP-A-59-152957, JP-A-6-143838 and JP-A-6-143839. However, azo dyes described in these publications all are insufficient in the fastness to light, heat, humidity, active gases in the environmental and the like.

Aqueous ink, inkjet recording ink and inkjet recording method


In accordance with one embodiment, a commodity recognition apparatus detects, from a captured image, an object imaged in the captured image and extracts an appearance feature amount of the object from the image of the object; compares the extracted appearance feature amount with feature amount data of a dictionary file in which feature amount data indicating the surface information of a commodity is stored for each recognition target commodity to calculate a similarity degree indicating how similar the appearance feature amount is to the feature amount data for each recognition target commodity; recognizes whether or not the object is a commodity based on the calculated similarity degree; and specifies and notifies the reason in a case in which the object is not recognized as a commodity.

There is a technology in which an object is recognized according to a similarity degree calculated by extracting an appearance feature amount of the object from the image data of the object photographed by an image capturing section and comparing the extracted appearance feature amount with the feature amount data of a reference image of each object pre-registered in a recognition dictionary file. Such a technology is called as a general object recognition, and various recognition technologies are disclosed in the following document.
Keiji Yanai "Current status and future direction of general object recognition", Journal of Information Processing Society, Vol. 48, No. SIG16 [Search on Heisei 22 August 10], Internet <URL:http://mm.cs.uec.ac.jp/IPSJ-TCVIM-Yanai.pdf>
In addition, the technology carrying out the general object recognition by area division of the image for each object is described in the following document.
Jamie Shotton etc, "Semantic Texton Forests for Image Categorization and Segmentation", [Search on Heisei 22 August 10], Internet <URL:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.145.3036&rep=repl&type=pdf>
In recent years, for example, the general object recognition technology described above is proposed to be applied to a recognition apparatus for recognizing a commodity, especially a commodity on which a barcode is not applied, such as vegetables, fruits and the like purchased by a customer in a checkout system (POS system) of a retail store. In this case, an operator (a shop clerk or a customer) holds the recognition target commodity over the image capturing section. In this way, in the commodity recognition apparatus, the commodity is recognized from a captured image and the information (for example, a commodity name) indicating the recognition result is displayed on a display section.
However, the commodity is not always recognized. For example, there is a case in which the commodity is not recognized because the commodity is shield by the hand of the operator. Alternatively, there is a case in which the commodity is not recognized because the similar feature amount data is not registered in the recognition dictionary file. Further, there is a case in which the commodity is not recognized because the commodity recognition program is frozen.
The commodity recognition apparatus has no reaction in a case in which the commodity is not recognized. As a result, it is difficult to determine the reason why the commodity is not recognized, and most operators feel stress because they tried to change the position and the direction to hold the commodity.