A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally. The novel method further comprises instructing the CPLD to program again, or overprogram, the program data into the memory location if the program data matches the verify data. The novel method further comprises reprogramming the program data into the memory location if the program data does not match the verify data.

1. Field of the Invention
The present invention relates to the field of programming and testing integrated circuits or systems.
2. Art Background
Various techniques have been developed to enable programming and testing of programmable elements (memory locations) of a programmable logic device (PLD) or complex programmable logic device (CPLD). Generally, programmable elements within CPLDs have been programmed by applying program data through a parallel interface of the CPLD. When a CPLD is programmed through a parallel interface, the data used for programming a memory location is provided on several device pins, and the data that is output during the verification of a memory location is also provided on several device pins. These device pins may or may not comprise the same device pins.
A typical flow diagram for programming every memory location with a desired pattern in a CPLD is illustrated in FIG. 1. The programming flow chart illustrated in FIG. 1 may be used, for example, in programming a CY7C371 CPLD manufactured by Cypress Semiconductor Corporation. At step 100, a power supply voltage is applied to the CPLD. Typically, the power supply voltage applied to the CPLD comprises +5.0 volts or +3.3 volts. At step 102, a programming voltage is applied to the CPLD. The programming voltage is typically an elevated voltage which is used to program the memory locations in the CPLD. A typical programming voltage comprises +12.0 volts. At step 104, the silicon identification for the particular CPLD under test is read from a memory location within the CPLD. The silicon identification is verified to match the CPLD device under test (e.g. CY7C371). At step 106, a program cycle counter is read and verified. The program cycle counter indicates the number of times the CPLD has been programmed. For quality and reliability purposes, at step 108, the program cycle counter is checked to determine if it contains a value greater than or equal to a predetermined number of programming attempts (e.g. 100 programming attempts). If the program cycle counter is greater than or equal to the predetermined number of programming attempts, the device is discarded at step 110. If the device has been programmed less than the predetermined number of times, program data is applied to the parallel interface of the CPLD and every memory location is programmed with a background pattern at step 112. Background programming ensures that every programmable memory location contained within the device is programmed, including main array bits, configuration bits, user identification bits, program cycle counter bits and a security bit. Every programmable element is programmed regardless of whether its present state is programmed or unprogrammed. This is done to provide for a consistent erasure of all of the memory locations. At step 114, all of the memory locations are erased. At step 116, the erasure of the memory locations is confirmed. Step 116 is referred to as the blank verify.
At step 118, a desired program pattern is programmed into the CPLD. FIG. 2 illustrates a general program flow chart for programming the desired pattern into the CPLD, and will be described in detail below. At step 120, the configuration bits of the CPLD are programmed again to boost or raise the overall margin. Configuration bits in a CPLD may comprise programmable locations that control the configuration of macrocells, a programmable interconnect matrix (PIM), or a product term matrix (PTM). At step 122, the program cycle counter is updated and verified. At step 124, all of the memory locations are read at power supply rails to verify that no disturb problems exist in the programming of the CPLD. Disturb problems cause unintentional programming of a memory location while programming another related location, such as a location on the same row or column. At step 126, a security bit of the CPLD is optionally programmed and verified. At step 128, the programming voltage is removed from the CPLD, that is, the programming voltage is forced to a non-programming voltage (e.g. ground). At step 130, the power supply voltage is removed from the CPLD and the programming flow stops.
FIG. 2 illustrates one example of parallel programming a desired pattern into a CPLD according to step 118 of FIG. 1. The programming flow starts at step 202. At step 204, a row address is loaded into a row address register. The row address indicates the row address of the memory location to be programmed. At step 206, a column address is loaded into a column address register. The column address indicates the column address of the memory location to be programmed. At step 208, program data is placed onto parallel interface data input pins. At step 210, a counter variable C is set to zero. The counter variable C indicates the number of attempts at programming a particular memory location. At step 212, the program flow checks to see if the counter variable has reached the maximum number of programming attempts allowed. In one example, C may comprise a maximum of four programming attempts. If C has reached the maximum number of programming attempts, the programming of the CPLD fails as indicated by step 214. If C has not reached the maximum number of programming attempts, the program flow programs data into a memory location at step 216. At step 218, C is incremented by one.
At step 220, programming of the memory location is immediately verified to determine if another attempt to program the same memory location is required. If the data read from the programmable memory location (verify data) does not match the program data, the program flow returns to step 212 and attempts to reprogram the memory location if C has not reached the maximum number of programming attempts. If the verify data matches the program data at step 220, the program data is programmed again into the memory location at step 222. The reprogramming of the program data at step 222 is termed "overprogramming." Overprogramming boosts the charge stored at a programmed memory location. At step 224, the program flow determines if the last column address of the programmable memory locations has been programmed. If it has not, the column address is updated and the program flow returns to step 206. If the last column address has been reached, the program flow determines if the last row address has been reached at step 226. If it has not, the row address is updated and the program flow returns to step 204. If the last row address has been reached, the program flow stops at step 228.
Parallel programming and verification of programming are not always possible or efficient. For example, when a CPLD has been affixed to a printed circuit board (PCB), it is expensive, time consuming, and often impractical to test an individual component by a parallel programming technique. Additionally, programming a device using a parallel programming interface requires the control of a significant number of pins. In many cases, as many as 25 to 30 pins must be controlled in a parallel programming interface. As a result, various techniques have been developed to enable testing of a CPLD using test logic having a serial programming interface. Program data to be provided to programmable memory locations of a CPLD are input through a serial input port. Verification data read from the programmable memory locations is read from a serial output port. The serial programming interface provides a more efficient interface for programming a device already soldered onto a PCB.
One type of serial programming interface is incorporated into the 22V10D Flash PLD designed by Cypress Semiconductor Corporation. The 22V10D includes a test circuit coupled to memory locations as generally illustrated in block diagram form in FIG. 3a. FIG. 3a shows a 22V10D Flash PLD 300 which includes programmable memory 304 coupled to parallel input data at node 318 and parallel output data at node 332. The 22V10D 300 incorporates a serial interface test circuit 303 which is not compatible with the IEEE 1149.1 (JTAG) specification described below, but is able to generally implement a serial program flow consistent with FIG. 1 and FIG. 2. Test circuit 303 comprises control logic 306 which controls the programming of memory 304. Control logic 306 receives control signals from the parallel data input, including a programming voltage at node 320, register select signals RSEL0 at node 322 and RSEL1 at node 324 which are used to select one of four shift registers, and a program pulse DO.sub.-- IT at node 326. Additionally, control logic 306 receives a serial input clock SCLK at node 328. Test circuit 303 also includes four shift registers, namely: data shift register 310, column address shift register 312, row address shift register 314 and mode select shift register 316. The four shift registers receive serial input data from SDI at node 330 and the serial input clock SCLK at node 328.
With reference to FIG. 2, a row address for a memory location to be programmed in the 22V10D is serially shifted into row address shift register 314 at step 204, a column address is serially shifted into column address shift register 312 at step 206 and program data is serially shifted into data shift register 310 at step 208. The 22V10D must use the externally supplied register select signals RSEL0 and RSEL1 to determine which register is selected at a given time. In response to a program instruction loaded into mode select shift register 316, program data is programmed into a memory location at step 216 when a program pulse is applied on DO.sub.-- IT at node 326. As a result of the programming step, the programmed data is immediately fast verified. Verify data is not loaded into the data shift register and then shifted out of the 22V10D to be compared against the program data. Instead, an internal comparison of the verify data and the program data is made by compare logic 308. The result of that comparison is output on one of the parallel data output pins at a predetermined amount of time following a program pulse on DO.sub.-- IT at node 326. The result of the comparison is combinatorial in nature, that is, the result is not registered nor output on one of the parallel data outputs in response to a clock signal. As a result, one 22V10D cannot be cascaded with another 22V10D and continue to support the verify method described above.
The comparison of the verify data read from the memory location and the program data stored in the data shift register is accomplished by compare logic 308. Compare logic 308 is further illustrated in FIG. 3b, which shows exclusive OR (XOR) gate 380 comparing the data shift register bit zero (DR0) with the verify data bit zero. In like manner, each of the program data bits stored in the data shift register is compared against each of the corresponding verify bits read from a memory location. As illustrated in FIG. 3b, there are ten (10) program data bits (DR0-DR9) stored in the data shift register which are compared against ten (10) verify data bits by XOR gates 380 through 389. The outputs of XOR gates 380 through 389 are coupled to an inverted OR (NOR) gate 390. NOR gate 390 generates a fast verify output which comprises a high logic level when all of the program data bits match all of the corresponding verify data bits. NOR gate 390 generates a fast verify output which comprises a low logic level when one of the program data bits does not match a corresponding one of the verify data bits.
While program verification is performed by compare logic within the 22V10D, the 22V10D architecture suffers from a number of disadvantages. First, the 22V10D architecture is not compatible with the IEEE 1149.1 JTAG) four-pin specification (described below). Second, the only 22V10D instruction (mode) that has multiple functions is the program (DO.sub.-- IT pulse)/fast verify instruction (mode). That is, the 22V10D does not receive an instruction which indicates that the 22V10D should load row, column or program data and then program the received data; rather, there is only one program instruction which programs data into a memory location and verifies the results in response to a program (DO.sub.-- IT) pulse. The 22V10D shifting of the row address, column address, and data registers is always separate and never combined. The user must use the RSEL0 and RSEL1 external signals to control the loading of the various shift registers. Third, the 22V10D codes used for the instructions (modes) are not defined to allow partial shifting to accomplish the changing of one instruction into another instruction. Fourth, the program/fast verify instruction (mode) of the 22V10D only improves the time required to immediately verify a location after programming and then to overprogram, but the speed of the other operations are not improved. Fifth, as described above, the 22V10D combinatorial nature of the compare logic performing a fast verify function does not allow multiple devices to be cascaded together.
Additionally, the 22V10D architecture must compare each and every program data bit against each and every verify data bit. This is a significant disadvantage when considering two types of verification scenarios. In the first scenario, a memory location to be programmed does not comprise the same number of bits as the number of bits in the data shift register. Some memory locations are naturally better suited to be programmed in groups that are less than the size of the data shift register (e.g. programming the one-bit security bit). For example, the data shift register may comprise eight bits and a programmable location may only comprise six bits. Since each and every bit of the data shift register is compared against each and every bit of the verify data, data bits not used for programming in a given programming step would have to be preloaded with predetermined default values. This requires the user to know the default values ahead of time.
The second scenario involves "single-bit programming." Even though the programming of an entire byte of program data is supported by the 22V10D's programming interface, many times only one bit of a byte can be programmed at a time to achieve satisfactory programming. This may be due to the relatively close proximity of the bits of a byte to be programmed within the layout of a particular programmable device. Bits of a byte which must be programmed under the technique of single-bit programming are usually determined during characterization of the device rather than during design and fabrication. In single-bit programming, if n bits of a byte are to be programmed, the same addressed memory location must be programmed and verified with n different data patterns, each data pattern containing the data to program only one bit. The fast verify architecture of the 22V10D does not support single-bit programming. For example, if an eight bit data pattern to be programmed using single-bit programming comprises 00001010 (where a logic one indicates programming a bit in a memory location), the first single-bit programming data pattern to be loaded into the data shift register would comprise 00000010. In the immediately following verify function, the verify data would also comprise 00000010, and the verify function would generate a correct comparison result. The second single-bit programming data pattern to be loaded into the data shift register and programmed into the appropriate memory location would comprise 00001000. The verify data now read from the programmed memory location would now comprise 00001010. This bit pattern would be compared against 00001000 stored in the data shift register. Given that each and every bit of the program data is compared against each and every corresponding bit of the verify data, regardless of whether the program data comprises a logic one or a logic zero, the result of the fast verify would indicate a failure when there was no failure. Therefore, the fast verify architecture as utilized in the 22V10D does not support single-bit programming. Additionally, the 22V10D architecture does not support multi-bit programming. Multi-bit programming is an extension of single-bit programming in that no adjacent bits may be simultaneously programmed.
Therefore, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a PLD, CPLD or other programmable device. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which supports programming a memory location and immediately verifying the programming. When immediately verifying the programming, the data in the data register remains intact for reprogramming when the memory location does not verify, or for overprogramming when the memory location does verify. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which utilizes a register. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which supports the cascading of serial test circuits and propagating the fast verify result through the serial test circuits. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which supports single-bit programming or multi-bit programming. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which compares only those bits programmed into a memory location with verify data read from the memory location. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which fills in the bits of a data register with appropriate logic states without the user having to know what default states to load into the data register where there is not a corresponding bit in the memory location, thus excluding those bits from the fast verify comparison.
Another approach to providing a serial programming interface in a device under test is defined in IEEE Std 1149.1-1990 and 1149.1a-1993 entitled IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1), ISBN 1-55937-350-4, which is commonly referred to as the JTAG (Joint Test Access Group) specification. The JTAG specification defines a test access port (TAP) which is a general purpose port that can provide access to any test support functions built into a component to be tested. The TAP has a minimum of three dedicated input connections: a Test Input Clock (TCK) for clocking in serial test data or instruction information, a Test Mode Select Input (TMS) which is decoded by logic accessing the TAP to control test operations, and Test Data Input (TDI) which provides serial input test data, address information, or instruction information. In addition, the TAP has, at a minimum, one dedicated output: Test Data Output (TDO) which provides for the serial output of data from the TAP. Through the use of the test logic accessed through the TAP, data, address and instruction information may be serially written to and read from a device under test.
FIG. 4a shows a single device under test 400 in which test logic accessed through a TAP may be implemented. Device under test 400 may be a single integrated circuit device or a system on a PCB. Device under test 400 may comprise, for example, a CPLD. Device under test 400 includes a memory 402 comprising programmable memory locations coupled to test circuit 404 via bus 418. Memory 402 receives parallel input data at node 406 and provides parallel output data at node 408. Test circuit 404 receives serial input test data, address data and instruction information from TDI at node 410. Test circuit 404 also receives test input clock TCK at node 412, and test mode select input TMS at node 414. Additionally, test circuit 404 serially outputs TDO at node 416.
FIG. 4b shows a multiple device under test configuration illustrating how components may be cascaded together in a serial fashion in compliance with the JTAG specification. Specifically, device under test 430 is serially coupled to device under test 446 through their respective test circuits 434 and 450. When test circuits 434 and 450 comprise test logic accessed through a TAP, as illustrated in FIG. 4a, test circuits 434 and 450 receive TCK 438 and TMS 440. Test data, address data and instruction information is serially received by test circuit 434 from TDI at node 436 and may be coupled to test circuit 450 via node 442. Test circuit 450 outputs the test data, address data and instruction information at node 452. Test circuits 434 and 450 may be distributed throughout device under test 430 and device under test 446.
FIG. 5 illustrates prior art test logic 500 which operates in accordance with the JTAG specification. Test logic 500 is coupled to memory 528. Memory 528 comprises memory locations in a programmable logic device under test. Test logic 500 comprises controller 503 which includes control logic 502 coupled to decode logic 504. Control logic 502 receives and interprets the signals on TMS at node 518 and TCK at node 520. Control logic 502 and decode logic 504 generate clock and/or control signals as required by test logic 500. A set of registers, including instruction register 506, data register 508, address register 510, boundary scan register 512 and bypass register 514, is configured to receive input signals from decode control logic 504, TCK and TDI.
Through the interaction of control logic 502 and decode logic 504 an instruction is serially loaded into instruction register 506 from TDI. Instructions loaded into instruction register 506 are decoded by decode logic 504 and are used to select a test to be performed and/or register to be accessed. Data register 508 stores program data to be programmed into memory 528 and verify data read from memory 528. Address register 510 stores the address location of the memory location to be accessed in memory 528.
Test logic 500 additionally includes a selector or multiplexer 516 coupled to select signal 526. Selector 516 receives serial data shifted out from data register 508, address register 510, instruction register 506, boundary scan register 512 and bypass register 514. Control logic 502 and decode logic 504 control select signal 526 which selectively enables one of the serial inputs coupled to selector 516 to be serially output at TDO at node 524.
FIG. 6 shows a TAP controller state diagram 600 that is included in the JTAG specification. All test circuitry compliant with the JTAG specification must implement the TAP controller state diagram including states 602 through 632. The TAP controller state diagram would be implemented by controller 503 illustrated in FIG. 5. The TAP controller state diagram is synchronized to the TCK input and is controlled by the TMS input.
FIGS. 7-10 illustrate conventional methods of serially programming a CPLD according to the program flow charts of FIGS. 1 and 2 and using the JTAG compatible test circuit illustrated in FIG. 5. The programming methods illustrated in FIGS. 7-10 are implemented using the TAP controller state diagram illustrated in FIG. 6. Throughout the discussion of FIGS. 7-10, reference will be made to the number of clock cycles that is required to complete a given operation. It will be appreciated that the following discussion generally excludes the calculation of the clock cycles that are required to move from one state to another state in the TAP controller state diagram. These transition clock cycles are generally excluded from the discussion in order to not obscure the general operation of the program flow charts. Additionally, instruction register 506 comprises Z bits, address register 510 comprises Y bits and data register 508 comprises X bits. Therefore, it requires Z clock cycles to shift an instruction into instruction register 506, Y clock cycles to shift address information into address register 510 and X clock cycles to shift program data into data register 508.
FIG. 7 illustrates a conventional method for reading verify data from a memory location in a CPLD using the serial programming interface test circuitry of FIG. 5. The verify data may be compared against an expected result external to the CPLD. The program flow illustrated in FIG. 7 may be used for a number of read steps illustrated in FIG. 1, including: reading or verifying a single memory location such as step 104; reading and verifying multiple locations; and reading and verifying the entire CPLD such as steps 116 and 124. The program flow starts at step 702. At step 704, an instruction is shifted into instruction register 506 which indicates that address information will be shifted into address register (AR) 510. At step 706, the address information is shifted into address register 510. At step 708, an instruction is shifted into instruction register 506 which indicates that verify data is to be read from the memory location addressed by the address information stored in address register 510. At step 710, verify data is captured or read into data register (BR) 508. At step 712, the verify data is shifted out of data register 508 to serial output TDO. Step 714 determines if another memory location within the device is be read. If another memory location is to be read, the program flow returns to step 704. If another memory location is not to be read, the program flow stops at step 716. The program flow illustrated in FIG. 7, requires at least 2Z+Y+X clock cycles to read verify data from one memory location. Reading verify data from subsequent memory locations also requires 2Z+Y+X clock cycles.
FIG. 8 illustrates a conventional method for programming a memory location in a CPLD using the serial programming interface test circuitry of FIG. 5. The program flow illustrated in FIG. 8 may be used for step 120 illustrated in FIG. 1. The program flow starts at step 802. At step 804, an instruction is shifted into instruction register 506 which indicates that address information will be shifted into address register 510. At step 806, address information is shifted into address register 510. At step 808, an instruction is shifted into instruction register 506 which indicates that program data will be shifted into data register 508. At step 810, program data is shifted into data register 508. At step 812, an instruction is shifted into instruction register 506 which indicates that the program data in data register 508 will be programmed into a memory location having the address stored in address register 506. At step 814, the program data is programmed into the memory location. Step 816 determines if another memory location is be to programmed. If another memory location is to be programmed, the program flow returns to step 804. If another memory location is not to be programmed, the program flow stops at step 818. The program flow illustrated in FIG. 8 requires at least 3Z+Y+X clock cycles to program one memory location. Programming subsequent memory locations also requires 3Z+Y+X clock cycles.
FIG. 9 illustrates a conventional method for programming a background pattern into all of the memory locations in a CPLD using the serial programming interface test circuitry of FIG. 5. The program flow illustrated in FIG. 9 may be used for step 112 illustrated in FIG. 1. The program flow starts at step 902. At step 904, an instruction is shifted into instruction register 506 which indicates that program data will be loaded into data register 508. At step 906, program data is shifted into data register 508. At step 908, an instruction is loaded into instruction register 506 which indicates that address information will be loaded into address register 510. At step 910, address information is shifted into address register 510. At step 912, an instruction is shifted into instruction register 506 which indicates that the program data in data register 508 will be programmed into a memory location having the address stored in address register 506. At step 914, the program data is programmed into the memory location. Step 916 determines if another memory location is be to programmed. If another memory location is to be programmed, the program flow returns to step 908. If another memory location is not to be programmed, the program flow stops at step 918. The program flow illustrated in FIG. 9 requires at least 3Z+Y+X clock cycles to program at least one memory location. Programming of subsequent locations requires at least 2Z+Y clock cycles.
FIG. 10 illustrates a conventional method for programming a desired pattern into a CPLD, immediately verifying the programming, and overprogramming the desired pattern. The program flow illustrated in FIG. 10 corresponds to the program flow illustrated in FIG. 2 using the serial programming interface test circuitry of FIG. 5. The program flow starts at step 1002. At step 1004, an instruction is loaded into instruction register 506 indicating that address information will be loaded into address register (AR) 510. At step 1006, address information is shifted into address register 510. At step 1008, C is initialized to zero. At step 1010, the program flow checks to see if C equals the maximum number of programming attempts allowed. In C has reached the maximum number of programming attempts, the programming of the CPLD fails at step 1012. If C has not reached the maximum number of programming attempts allowed, the program flow shifts an instruction into instruction register 506 at step 1014 which indicates that program data will be loaded into data register 508 (BR). At step 1016, program data is shifted into data register 508. At step 1018, an instruction is shifted into instruction register 506 which indicates that program data in data register 508 will be programmed into a memory location having the address stored in address register 510. At step 1020, the program data is programmed into the memory location.
At steps 1022 through 1028, the programming of the memory location is immediately verified to determine if another attempt to program the same memory location is required. At step 1022, an instruction is loaded into instruction register 506 which indicates that verify data will be read from the programmed memory location. At step 1024, the verify data is read or captured into data register 508. At step 1026, the verify data is shifted out of data register 508 to serial output TDO. At step 1028, the verify data is externally compared against the programmed data. If the verify data does not match the program data, the program flow increments C at step 1029 and returns to step 1010. If the verify data matches the program data, the program flow overprograms the program data into the same memory location at steps 1030 through 1036. At step 1030, an instruction is shifted into instruction register 506 which indicates that the program data will be reloaded into data register 508. At step 1032, the program data is reshifted into data register 508. At step 1034, an instruction is shifted into instruction register 506 which indicates that the reloaded program data will be overprogrammed into the memory location. At step 1036, the program data is overprogrammed into the memory location. At step 1038, the program flow determines if another memory location needs to be programmed in accordance with the desired program pattern. If another memory location is to be programmed, the program flow returns to step 1004. If no other memory locations are to be programmed, the program flow stops at step 1040. The program flow illustrated in FIG. 10 requires at least 6Z+Y+3X clock cycles to program, verify and overprogram one memory location.
An alternative program flow based on FIG. 10 shifts the original program data into data register 508 at the same time the captured verify data is being shifted out of data register 508 at step 1026. This alternative obviates the need for steps 1030 and 1032 reducing the number of clock cycles required to program, verify and overprogram one memory location to at least 5Z+Y+2X clock cycles. Additionally, the number of cycles required to reprogram a memory location after the first memory location did not verify requires at least 2Z+X clck cycles (steps 1014 and 1016 are then not required for reprogramming).
The programming methods illustrated in FIGS. 7-10 require a significant number of clock cycles to program a memory location in a device under test, to verify the programming, and to reprogram or overprogram the memory location. The more clock cycles that are required to test a device, the lower the testing throughput and the greater the likelihood that a false programming error will be introduced due to system noise.
Therefore, a need exists for a method of programming and testing a device which reduces the number of method steps, instructions and clock cycles over the conventional methods illustrated in FIGS. 7-10. Additionally, a need exists for implementing such a method using test circuitry which is compatible with the JTAG specification. Additionally, a need exists for a method of programming and testing a device which uses multi-purpose instructions which define both programming and shifting operations in order to reduce the number of required method steps, instructions and clock cycles. Additionally a need exists for instruction codes which allow partial shifting to accomplish the changing of one instruction into another instruction in a number of clock cycles which is less than the number of clock cycles required to completely load every bit of an instruction register.

CPLD serial programming with extra read register


An artificial intelligence (AI) system is disclosed. The AI system includes a processor that processes a sequence of input frames with a neural network including a dilated self-attention module trained to compute a sequence of outputs by transforming each input frame into a corresponding query frame, a corresponding key frame, and a corresponding value frame leading to a sequence of key frames, a sequence of value frames, and a sequence of query frames of same ordering and by performing attention calculations for each query frame with respect to a combination of a portion of the sequences of key and value frames restricted based on a location of the query frame and a dilation sequence of the key frames and a dilation sequence of value frames extracted by processing different frames of the sequences of key and value frames with a predetermined extraction function. Further, the processor renders the sequence of outputs.

Nowadays, attention mechanism has become a central component in many Neural Network (NN) architectures for different artificial intelligence (AI) applications including machine translation, speech processing, language modeling, automatic speech recognition (ASR), computer vision, and the like. Further, self-attention mechanism is also a widely used neural network component. The self-attention mechanism allows inputs to interact with each other ("self") and find out who they should pay more attention to ("attention") to compute outputs in the best way for a given task. Outputs of the neural network components using such a self-attention mechanism are aggregates of these interactions.
Attention-based architectures (such as, transformer architecture) have been successfully applied for various domains where attention is utilized throughout all model components. A number of model parameters are increased to further improve results using deeper and wider architectures. The attention-based architectures process inputs of different lengths (also called as "input sequence length"). In general, computational complexity of the attention-based architecture depends upon the input sequence length. Also, the computational complexity of the self-attention mechanism grows quadratically with increase in the input sequence length. This can be problematic for applications such as, but not limited to, Automatic Speech Recognition (ASR), where the input sequence length of an utterance may be relatively long. The increase in the computational complexity of the neural networks results in low processing performance, such as increase in processing time, low processing speed, and increase in storage space.
To solve the problem of computational complexity in the neural networks, restricted self-attention mechanism may be used. However, the restricted self-attention mechanism ignores distant information relative to a query associated with the current query frame. Hence, output result of such a mechanism may be deteriorated.
Accordingly, there is a need for a technical solution to overcome the above-mentioned limitation. More specifically, there is need to provide high quality outputs, while minimizing computation cost (time and space requirement).

Artificial intelligence system for capturing context by dilated self-attention

Mitsubishi Electric Research Laboratories, Inc.


A mechanical assembly, for regulating the temperature of an electronic device, includes a gimbal and a heat-exchanger which is attached to the gimbal. The gimbal includes a base member, a carrier member, and a spring which has—1) a first end with a rigid coupling to one of the base and carrier members, and 2) a second end with a slideable coupling to the remaining member. The slideable coupling prevents any gap from occurring between the heat-exchanger and the electronic device when they are pressed together.

This invention relates to a mechanical assembly that regulates the temperature of an integrated circuit chip (IC-chip) by pressing a temperature controlled heat-exchanger against a planar surface of the IC-chip.
One particular use for the above mechanical assembly is in a chip testing system. There, test signals are sent to the IC-chip while the mechanical assembly maintains the temperature of the IC-chip at a set point.
In the prior art, one mechanical assembly which regulates the temperature of an IC-chip is shown in FIGS. 1 and 2 of U.S. Pat. No. 4,791,983. The mechanical assembly in patent '983 includes a coil spring 20 which presses a planar surface of a liquid cooling jacket 15 against a planar surface of the IC-chip 11. Squeezing those two planar surfaces together enables heat to flow by thermal conduction from the IC-chip 11 to the liquid cooling jacket 15.
But due to various manufacturing tolerances, the planar surface of the IC-chip in a chip testing system can be oriented at different angles relative to a nominal position. To accommodate these different angles, the mechanical assembly in patent '983 includes a guidepost 18 which has one end that is rigidly attached to the cooling jacket 15, and has an opposite end that pivots on a frame 14. The coil spring 20 is coiled around the guidepost 18. Thus the guidepost 18, together with the coil spring 20 and the cooling jacket 15, can tilt at different angles.
After initial contact occurs in patent '983 between the planar surface of the cooling jacket 15 and one edge of the IC-chip 11, the guidepost 18 must pivot on the frame 14 to make the cooling jacket 15 lie flat against the IC-chip 11. However, the present inventors have determined that as the guidepost 18 pivots on the frame 14, the spring 20 can exert a lateral force on the cooling jacket 15 which may cause a gap to occur between the IC-chip 10 and the planar surface of the cooling jacket. When this gap occurs, the IC-chip 10 will not be adequately cooled. This lateral force problem is analyzed herein in detail in conjunction with the Detailed Description of FIGS. 4 and 7.
Also in the prior art, another mechanical assembly which regulates the temperature of an IC-chip is shown in FIGS. 10 and 11 of U.S. Pat. No. 6,116,331. This mechanical assembly includes a single leaf spring 80 which presses a planar surface 91 of a heat-exchanger 90 against a planar surface of an IC-chip.
However, the leaf spring 80 in patent '331 lies parallel to the planar surface 91 of the heat-exchanger 90, and that leaf spring must have a certain length in order to have the proper flexibility. If the leaf spring 80 is too short, it will be so stiff that the heat-exchanger 91 will press against the IC-chip with too much force and thereby damage the IC-chip.
But as the length of the leaf spring 80 is increased, the density with which multiple copies of the mechanical assembly can be arranged side-by-side in a chip testing system is decreased. Thus, the total number of IC-chips which can be tested concurrently per unit area in a chip testing system is decreased.
According, a primary object of the present invention is to provide an improved mechanical assembly for regulating the temperature of an IC-chip in which all of the above drawbacks with the prior art are overcome.

Mechanical assembly for regulating the temperature of an electronic device, having a spring with one slideable end


The invention is directed to a method and apparatus for preventing software piracy. A license enforcement server may be integrated with an operating system running on a network-critical machine. As such, other computational devices connected to the network may obtain permission to perform licensed activities. These computational devices may have an instruction set for communicating with the license enforcement server. Further, the license enforcement server may communicate with a licensing organization. The license enforcement server may utilize a namespace tree to organize licenses and uniquely identify licensed activities. In this manner, a universal license enforcement system may be achieved in which disabling of the license enforcement mechanisms would adversely effect a network.

Software developers build revenue streams by licensing software to end users. However, significant losses in revenue may occur when software is pirated. As such, unlicensed use represents a large revenue loss to software companies. However, there is no unified method of preventing piracy.
In one exemplary licensing scenario, software products are licensed to companies. The license may be for a multitude of instances of the software application which may expire on a given expiration date. For example, a company may license ten copies of an application that expire at the end of the year. In this example, the revenue model for the software licensor is circumvented when more than the licensed number of copies are used or the copies are used beyond the expiration date.
In one typical embodiment, a server delivers the applications to a computer connected to the network. As such, the server keeps track of the number of applications delivered or the number of instances of the application in service. However, this method may be circumvented by detaching the computer from the network once the application has been served. Alternately, the server may lose track of the number of applications delivered, especially in the event of network failures or other network events.
A further typical solution is to require a license server to be named upon installation. This method may suffer similar deficiencies as the method above. Further, customers may be reluctant to undergo the expense associated with installing and maintaining a license server.
In another situation, applications are often sold or licensed to individuals for use on a single machine. These machines may be periodically connected to a network. A problem exists when one copy is installed on multiple machines.
Other typical solutions require a software key in order to enable the application to run. However, if the software is copied onto a second computer, the same key may be used; thus circumventing the licensing process. Such piracy accounts for a significant revenue loss to the software developer.
Another typical solution is to require electronic registration. With this solution, a software company may determine if multiple copies of the same licensed application have been installed on various machines. The electronic registration method may also attempt to determine if other pirated software resides on the machine requesting the registration. However, this method is often circumvented by users not registering the software.
On the other hand, companies have seen an increased liability associated with having pirated software on company computers. Periodic software audits that find pirated software may lead to costly fines. As a defensive measure, companies may be tempted to purchase more than the required number of licenses to limit their liability. In some instances, they may purchase licenses for all of the computers owned in the facility. However, the software may or may not be used at all the computers simultaneously.
As such, deficiencies exist in delivering software licenses. Software keys may be copied. Software delivered through servers may be pirated through errors in the network or the server. In addition, many other typical licensing mechanisms may be circumvented through network failure or the sharing of licensing and licensed keys.
As such, many typical licensing mechanisms suffer from deficiencies in providing and preventing piracy of software and providing an economic means for licensing software by companies. Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention described herein.

System and method for preventing software piracy


A transistor using a single crystal silicon nanowire and a method for fabricating the transistor is disclosed. The transistor using a single crystal silicon nanowire comprises a substrate and a single crystal silicon nanowire formed on the substrate. Here, the single crystal silicon nanowire comprises a source region and a drain region formed longitudinally with the single crystal silicon nanowire and separate from each other, and a channel region located between the source region and the drain region, wherein the perpendicular thickness of the channel region to the longitudinal direction is thinner than the thickness of the source region and the drain region.

With respect to prior bottom-up methods for fabricating nanowires, there has been much progress in research in synthesizing nanowires, and its electrical, optical and physical characteristics, but there are still limitations in applying the methods for aligning this in desired locations in integrated systems.
On the contrary, overcoming problems with respect to alignments are possible when fabricating nanowires in a top-down method, but they are fabricated through SOI substrates and e-beam lithography and thus have problems in productivity of nanowire devices.
Recently, various methods regarding fabricating nanowires using single crystal silicon substrates, not SOI substrates, are being introduced, but devices using these are realized on rigid substrates or even when realized on flexible substrates, they mostly have bottom-gate and top-gate structures.
But the nanowires, as its diameter becomes smaller, electrostatic control effects of nanowire devices become excellent, but have problems of parasitic resistance of source/drain becoming greater.
Also, as the size of devices become smaller, channel lengths of transistors formed at device forming regions, especially active regions becoming shorter, and thus influence of source/drain regions to electric fields of channel regions become significant, and problems of short channel effects, from which channel driving performance by gate electrodes deteriorates, occur.

Transistor using single crystal silicon nanowire and method for manufacturing same

KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION


A device for assembling an element, such as a washer, to the end of a fastener, such as a bolt, in a reliable, high-speed fashion wherein the assembling device includes the washers being supplied in a position to be picked up by an end of the shank of the bolt and slides along a ramp causing the washer to be positioned closer to the head of the bolt. The bolts are supplied to the assembling machine in an upright, in-line position. The bolts are conveyed through the assembling machine utilizing a screw having a thread designed to receive a portion of the shank of the bolt within the thread and cause the bolt to catch the hole of the washer and be assembled therewith into the assembled bolt and washer.

1. Field of the Invention
The present invention generally relates to a conveying device and more particularly to a conveying device adapted to move a bolt or similar fastening device along a straight line path over a defined distance and to place a washer, or similar element, onto the shank of the bolt. More particularly, the present invention is related to an apparatus for assembling a washer onto a bolt using a screw type conveyor which moves the bolt in a linear direction while the washer, or similar element, is placed onto the shank of the bolt.
2. Description of the Prior Art
Prior to the present invention, there have been a plethora of devices utilized in the field of assembling bolts and similar fastening devices to washers and similar elements in an expedited fashion and without the need for human intervention. The goals of all of these devices are typically to eliminate the need of human labor when combining two elements, upon a bolt and a washer, in a predictable, fast and efficient manner.
The bolt and washer, for example, are assembled in either one of two states, the first being of the type where the washer freely slides over the fastener or bolt and there is no interference fit between the two. The second is where the washer has an interference fit with the fastener. In each of the above types of fasteners, however, many different apparatus are used to achieve the end result.
One common apparatus uses single or multiple rotating wheels (or discs) to move the bolt (or washer) to a preselected engagement point to meet with the other element with which it is to be combined. In this type of device, the head of the bolt is usually magnetically held by a rotating wheel and the washer is assembled with the head of the bolt in a capture-type arrangement. Some typical examples of the above type of apparatus are Foster, U.S. Pat. No. 4,058,866; Lapohn, U.S. Pat. No. 4,309,787; Stern, U.S. Pat. No. 3,155,993; Pipes, U.S. Pat. No. 3,212,114; Jung et al, U.S. Pat. No. 4,237,605; Jackson, U.S. Pat. No. 4,453,308; Cambiaghi et al, U.S. Pat. No. 4,470,194; and Prutton, U.S. Pat. No. 2,914,781, as well as others. Typically, these types of devices utilize an inclined surface along which the washer and/or bolt are moved in relation to one another in order to achieve the assembly or pick up of the washer on the bolt and the insertion of the washer all the way to the underside of the head of the bolt. These types of devices require moving both the fastener and the washer to the point where they engage each other. This configuration adds unnecessary complexity to the device.
In contrast to the above rotating or disc-like assembly machines, there are several apparatus which utilize an in-line assembly technique. Examples of the above types of apparatus are U.S. Pat. No. 389,648 to Hamilton; U.S. Pat. No. 2,288,620 to Goodhue; U.S. Pat. No. 2,073,096 to Scholz; U.S. Pat. No. 3,103,023 to Zdanis; U.S. Pat. No. 2,333,940 to Kuehlman, and U.S. Pat. No. 3,872,530 to Festerling, as well as other references listed above. In this latter type of device, typically the fastener or bolt is moved in series fashion, one after the other, along a tractor or chain-type device utilized to cause the bolt to move within a defined track. As the bolts move along the track, the shank end of the bolts are caused to come into orientation with washers in a temporary stationary position which are picked up and inserted onto the shank of the bolt. Commonly, a ramp surface of some type is used to move the washer onto and along the shank of the bolt to achieve assembly of the bolts to the washers.
The Hamilton reference, U.S. Pat. No. 389,648, discloses a declining tube with a slot along the underside of the tube. Nails are gravity fed along a slot to a funnel where each nail is deposited through the funnel onto a washer below. U.S. Pat. No. 2,288,620 to Goodhue discloses a link belt carrier for conveying bolts. The bolts are dropped, shank down, onto a carrier. The carrier has clasps adapted to secure the head of the bolt. As the bolts are held by the clasps, the link belt carrier moves around a sprocket, changing the orientation of the bolt stem to an upward position. Washers descend from a trough and are dropped onto the bolt stem. U.S. Pat. No. 3,103,023 to Zdanis discloses an endless conveyor chain similar to the conveyor in Goodhue. However, Zdanis discloses terminal blocks mounted to the conveyor, for carrying the bolts, shank facing upward, along the conveyor path. As the bolt passes under a chute holding washers, a washer is deposited onto the bolt shank. U.S. Pat. No. 3,872,530 to Festerling discloses moving the bolts downward along a conveyor path which passes over a tube containing washers. As the bolt contacts a washer at the tube discharge end, the bolt stem picks up the top washer. As the bolt continues along a downward incline, the washer is pushed up the shank towards the bolt head.
In both the rotating disc type and in-line assembly type apparatus discussed above, typically the bolt or fastener is moved serially along its path by the gravitational force generated through physical contact with adjoining bolts. This force is generally applied to the head of the bolt and thereby is transferred from bolt to bolt. The only exception to the above is when the bolt is picked up by a rotating wheel and is caught within a recess designed to receive the bolt. In this case, the bolt is carried by the wheel in an arcuate or circular path.
Both the rotating disc as well as in-line assembly apparatus have sever limitations when the demand for higher production rates becomes dominant. The centrifugal forces on disc type rotating devices for large bolts cause disturbing forces resulting in misalignments and dislodging the bolt from the discs while the reliance on gravitational forces with associated unknown frictional components results in uneven movements of the components and inability to achieve high production rates resulting in severe derangement of the assembly operation. What is needed, therefore, is a conveying device for assembling a washer to the shank of a bolt wherein higher production rates not previously attainable are achieved by conveying the shank of the bolt in a rapid positive movement mode so that frictional forces or centrifugal forces do not interfere with movement of the fastener such that at these higher production rates, the bolt and washer still arrive at the predefined position for mounting the washer onto the shank of the bolt.
With respect to known prior art devices, nowhere has there been disclosed or taught the idea of using a conveyor for moving the bolt in a straight line wherein the shank of the bolt or other type of fastener is constrained and moved along the thread of a screw conveyor in a straight line manner. Moving one bolt at a time along the thread on a screw to a supply of washers in place ensures adequate separation of components and reliable transfer, resulting in a faster, more reliable assembly process.

Bolt and washer assembly machine and method of assembly


Spherical surface inspection equipment which optically examines the nature of the surface of a sphere to be examined, is made up of light illumination member including a point of light source for emitting a luminous flux, at predetermined angle of spread in a specific direction which is disposed in such a way that the exit point of the luminous flux matches a first focal point, and a curved-face mirror whose mirror surface is defined by a predetermined inner surface area which forms a part of a curved surface obtained by rotating a specific curve around a specific axis including the first focal point and includes and extends through at least 180 degrees around the axis. The spherical surface inspection equipment also includes sphere-to-be-examined drive member which retains the sphere such that its center is brought in alignment with the second focal point, and which rotates the sphere about the axis of rotation along a specific half of the meridian included between the poles on the surface of the sphere opposite to the predetermined inner surface of the curved-surface mirror; and surface nature determination member which limits the light reflected from the sphere to only the light reflected from an area corresponding to a predetermined width between the half of the specific meridian included between the poles and detects the thus-limited reflected light through use of at least one photodiode; and which determines the nature of the surface of the sphere according to the result of such detection.

The present invention relates to spherical surface inspection equipment for optically examining the surface nature of a sphere to be examined such as a steel ball.
1. Description of the Prior Art
As illustrated in FIG. 1, spherical surface inspection equipment having the following structure is already known as the previously described type of spherical surface inspection equipment. Specifically, the spherical surface inspection equipment is comprised of a semi-circumferential array 53 which includes a plurality of pairs of flood-light element 51 and light-receiving element 52 arranged in a semi-circumferential pattern at uniform angular intervals. The semi-circumferential array 53 is positioned in a circumferential direction of a steel ball 54 which is a ball to be examined. The steel ball 54 is rotated around a support axis 55 in the direction designated by arrow Y. The surface nature of the steel ball 54 is determined on the basis of an electrical signal output from the light-receiving element 52 (this spherical surface inspection equipment will be hereinafter referred to as a "first conventional example").
As illustrated in FIG. 2, in the first conventional example, the light emitted from the flood-light element 51 is reflected from the surface of the steel ball 54, and the thus-reflected light is received by the light-receiving element 52 disposed at a given angle alpha in relation to the flood-light element 51. The light-receiving element 52 converts the thus-received light into an electrical signal by a photoelectric converting element (not shown) such as a photo-diode. The thus-converted signal is output, via an amplifier and a gain control circuit (not shown). The level of the signal output from the light-receiving element 52 is compared with a given reference value, and the surface nature of the steel ball 54 is determined on the basis of the result of such comparison. In short, an examination is carried out as to whether or not there are imperfections such as flaws on the surface of the steel ball 54.
As illustrated in FIG. 3, there is another example of known spherical surface inspection equipment. The flood-light 56 (emitted from lighting equipment) incidents on the surface of the steel ball 54 which is rotating in the direction designated by arrow Z, and the light reflected from the surface of the steel ball 54 is collected into a point by use of a convex lens 57. An image of the thus-collected light is formed on a photoelectric converting element 58 such as a CCD (Charge-coupled Device). This example will be hereinafter referred to as a "second conventional example," and please refer to; e.g., Japanese Patent Unexamined Publication Nos. Sho-56-58643 and Sho-56-58644.
In the second conventional example, the photoelectric converting element 58 converts luminous energy into an electrical signal, and the nature of the spherical surface is determined on the basis of the level of the electrical signal. Specifically, a decision as to the presence or absence of imperfections in the steel ball 54 is performed on the basis of the level of the signal output from the photoelectric converting element 58. The second conventional example enables even the photoelectric converting element 58 having a small light-receiving area to examine the nature of the overall surface of the steel ball 54 by obliquely rotating at a given angle in relation to the steel ball 54.
However, in the first conventional example, it is necessary to examine the surface nature of the steel ball 54 with substantially identical sensitivity with regard to the diametrical dimension of the steel ball 54 (hereinafter referred to as the "size of the steel ball"). It is necessary to adjust the sensitivity of the spherical surface inspection equipment with regard to the detection of imperfections in the steel ball 54 every time the size of the steel ball changes. The allowable size of imperfections in a steel ball changes according to the size of the steel ball. In the case of the steel ball 54 having a small size, the allowable size of imperfections such as flaws must be set to a small size. In contrast, in the case of the steel ball 54 having a large size, the allowable size of imperfections may be set to a large size according to the size of the steel ball.
To prevent a decrease in the yield of steel balls, the sensitivity of the spherical surface inspection equipment is conventionally carried out according to the size of the steel ball so as to set the allowable size of imperfections corresponding to the size of the steel ball. For this reason, in the first conventional example, it is necessary to adjust and check the balancing of variations in the sensitivity of the photoelectric converting element to convert luminous energy into an electrical signal for each size of the steel ball.
In order to improve the capacity of the spherical surface inspection equipment to detect and resolve imperfections in view of surface nature, it is necessary to bring the light-receiving elements 52 as close to the vicinity of the steel ball 54 as possible such that the field of view of each light-receiving element 52 becomes narrow. For this reason, in the first conventional example, it is necessary to prepare the plurality of semi-circumferential arrays 53 tallying with the size of the steel ball beforehand. More specifically, in order to examine the nature of the surface of the steel ball 54 with high accuracy while the semi-circumferential array 53 is brought as close to the surface of the steel ball 54 as possible, it is necessary to manufacture a plurality of types of semi-circular arrays 53 having.-different pitch diameters according to the size of the steel ball. The spherical surface inspection equipment must be set by selection of a desired semi-circular array 53 corresponding to the size of the steel ball. It requires a lot of expense in time and effort to prepare for measurement.
In contrast, in the second conventional example, an image pick-up optical system determines a face-to-face distance of a steel ball to be examined (i.e., a first spacing "a" between the steel ball 54 and the lens 57 and a second spacing "b" between the convex lens 57 and the photoelectric converting element 58) and the magnification of an image (b/a). It is relatively easy to control in such a way that a relative distance; namely, the first spacing "a" and the second spacing "b," becomes constantly equal with respect to the steel ball 54 having a different size. However, it is difficult to ensure an image having uniform brightness by evenly illuminating the surface of the steel ball 54. More specifically, even when illumination light incidents on the surface of the steel ball 54, there is a great difference between the center of the illumination light and its periphery with regard to the angle at which the incoming light is reflected from the surface of the steel ball 54. It becomes difficult for the reflected light originated from the periphery of the illumination light to enter the lens 57, which in turn makes it impossible to produce an image having uniform brightness. The following method is conceivable. Specifically, as designated by a two-dot chain line in FIG. 3, a diffusing glass 59 is provided in the optical path of the illumination light, and the surface of the steel ball 54 is illuminated from many directions. The light reflected from the surface is diffused in various directions, and the diffuse reflections are collected into an image on the photoelectric conversion element 58.
However, if the diffusing glass 59 is disposed in the optical path, the illumination light is diffused in a wide range over the surface of the steel ball, thereby deteriorating the light-focusing efficiency of the convex lens 57. It is practically difficult to examine a wide range of the surface of the steel ball.
It is possible to change the capacity of the spherical surface inspection equipment to detect and resolve imperfections in terms of surface nature by changing the magnification of the optical system by use of the convex lens 57 according to the size of the steel ball. To obliquely rotate a steel ball, it is necessary to use a control roller manufactured according to the size of the steel ball and the degree of skew as disclosed in Japanese Patent Examined Publication (kokoku) Sho-42-17608, or it is necessary to provide the spherical surface inspection equipment with a skew mechanism as disclosed in Japanese Patent Unexamined Publication No. Sho-56-58643. Consequently, it is necessary to replace the previously-described component of the equipment each time the size of the steel ball changes. As in the first conventional example, it requires expense in time and effort to set the spherical surface inspection equipment. Further, the component is abraded or damaged as a result of contact between the component and the steel ball 54, thereby resulting in faulty oblique rotation of the steel ball. For this reason, in order to sufficiently ensure the result of inspection of the overall surface area of the steel ball 54, it is necessary for a person to carefully control the component. Furthermore, in practice, it is very difficult to manufacture a control roller and a skew mechanism capable of obliquely rotating the steel ball 54 having a diameter as small as 1 mm or thereabouts in view of production engineering. In short, as has been described above, the second conventional example has various problems with regard to production, as well as to the replacement and maintenance of a rotation control mechanism.

Spherical surface inspection equipment for optically examining the surface of a sphere


A riding toy for children has a chassis, a pair of side walls, lateral roof supports and wheel supports. The chassis includes locating protuberances and securement apertures which cooperate with side wall recesses and darts, respectively, to secure the side walls thereto. The roof supports have apertures formed therein which cooperate with roof darts on the side walls to establish a rigid construction of the chassis, side walls and roof supports. The chassis also has seat portions and axle tie bars interconnecting side rails. A front axle tie bar has vertical axle support guides which provide steerable supports for the front axles.

Riding toys for children are generally formed as a unitary item or are assembled with threaded fasteners such as bolts and nuts. When such toys are so assembled the fasteners employed are inserted through apertures formed in the structural components of the toy, and the fasteners are tightened to secure the components together. These fasteners must remain tight if the riding toy is to be useful. One alternative solution is to use locking type fasteners in order that the conjoined components will remain rigidly assembled. Such fatseners, however, increase the manufacturing costs of the toy.
Another approach to maintain the desired rigidity is for an adult, or an older child, continually to check for, and tighten, loose fasteners. This option may not always be available. For example, when the child is playing with the toy the loosening of one or more fasteners may go unnoticed, or even if noticed, the necessary tools and a person of sufficient age and experience properly to use the necessary tools may not be readily available. As a result, the child becomes unhappy with the toy, the parents become frustrated and the child ceases to play with the toy.


A motor vehicle includes several battery elements placed in modules of a first type and modules of a second type. The battery elements in each module of first type are grouped together in an assembly such that the battery elements can shift when exposed to a force, while the assembly is deformable. In each module of second type, the battery elements can shift, when exposed to the force, without being damaged while retaining their shape. The modules of first type are installed in a first region of the motor vehicle of a low stiffness compared to a second region, in which a body of the motor vehicle is designed for force-dissipating deformation in the event of an accident, and the modules of second type are installed in the second region, in which the body of the motor vehicle is designed to retain its shape in the event of an accident.

The invention relates to a motor vehicle having a plurality of battery elements.
The storage of electrical energy is playing an ever increasing role in motor vehicles. The battery cells, which are used in motor vehicles for storing energy, are then oftentimes arranged in large battery systems. These battery systems usually have a plurality of battery cells and are installed in the motor vehicle in a region that is exposed to little force. As a result, either the battery size is limited or the battery cells must be protected by massive reinforcement measures. This causes considerable increase in weight. There are known solutions which describe so-called crash-compatible battery systems. These battery systems include modules of e.g., trapezoidal shape to thereby allow a shift that deforms the assembly and destroys energy, so that the battery elements are not destructed. By using additional crash profiles, more energy can be dissipated.
For example, FR 2961442 describes a battery arrangement, which absorbs energy in the event of an accident as it deforms. Wedge-shaped battery cells are hereby shifted relative to one another. DE 10 2008 059 973 A1 discloses a battery unit, in which the battery cells are arranged in a two-shell construction. Energy absorption is realized here as the outer shell undergoes deformation while the battery cells, which are arranged in the inner shell, shift at the same time. DE 10 2008 010 822 A1 also discloses a deformable battery housing which is designed to be deformable, when the battery housing is exposed to a force impact, while the shape of individual battery cells is retained.
DE 10 2010 033 806 A1 proposes a battery pack which has a plurality of battery elements, with deformation elements being arranged there between. These deformation elements are located in intermediate spaces between the battery elements, so that the battery elements shift as the deformation elements undergo deformation in the event of an external application of force. This deformation absorbs kinetic energy.
DE 10 2011 106 090 A1 relates to an assembly of battery modules in a vehicle floor of a vehicle. At least two adjacent battery modules have respective sliding faces, along which the two adjacent battery modules can move relative to one another as a result of an application of force. This allows the battery modules to move out of the way in the event of a crash without being destroyed. Also DE 10 2010 034 925 A1 relates to an energy storage arrangement in a floor region of a vehicle. An underfloor mounting plate fixes hereby the energy storage carrier and thus the energy storage device to an underfloor structure of the vehicle. A cover plate in the floor region of the vehicle covers at least the energy storage carrier in a media-tight manner with respect to the vehicle interior.

Motor vehicle having structurally integrated battery elements


In certain implementations, user performance related to a virtual environment may be utilized to provide a targeted presentation of action —figures, action figure accessories, or other items (e.g., services, products, etc.) available for purchase in an online marketplace. As an example, performance indicator information related to performance of a user of the virtual environment may be obtained. One or more of the action figures or action figure accessories may be selected based on the performance indicator information. The selected action figures or action figure accessories may be presented to the user in the online marketplace.

In recent years, a number of video game/toy hybrid systems have emerged where figurines of movie, comic, or story characters can "come to life" in a video game. As an example, typical video game/toy hybrid systems enable a player to "import" a character represented by a figurine into the video game by placing the figurine on a portal device attached to a game console. Each game session may require the player to import the character (via the placement of the figurine) to utilize the character to accomplish various tasks in the game during the session. From the perspective of the player, the figurine and the character may become "synonymous" with one another as the player continues to use the figurine to access the character in the video game. As the character grows in-game (e.g., levels up) and obtains new abilities and special powers, the value of the figurine to the player may also increase—further adding to the collectability value of the figurine.
While these video game/toy hybrid systems are distinct from their traditional non-hybrid counterparts, the marketing, sale, or order fulfillment experience with respect to video games or toys of the hybrid systems are generally similar to the marketing, sale, or order fulfillment experience of traditional video games or toys. For example, recommendation systems providing recommendations of video games or toys of the hybrid system typically utilize the same techniques as the techniques utilized to provide recommendations of traditional video games or toys. As such, typical recommendation systems fail to take advantage of aspects unique to video game/toy hybrid systems to personalize recommendations of sale items for users. These and other drawbacks exist.

System and method for providing an enhanced marketing, sale, or order fulfillment experience related to action figures or action figure accessories having corresponding virtual counterparts


A controller for a hybrid vehicle in which the torque is output from an engine and/or an electric motor and is transmitted to drive wheels through a fluid torque converter and a transmission. The controller includes a motor output torque limiter to restrict the output torque from the electric motor such that the torque increased by the fluid torque converter does not exceed permissible torque which is acceptable for the transmission to receive when the electric motor in addition to the engine is driven.

In vehicles, there is a hybrid vehicle in which an engine driven by combustion of fuel is directly connected to an electric motor driven by electric power and having a power generating function. In this hybrid vehicle, torque is output from the engine and/or the electric motor and is transmitted to vehicle drive wheels through a fluid torque converter and a transmission. That is, in the vehicle drive system the motor in connection with a crankshaft of the engine assists the output of the engine, and a controller controls the assist torque in combination with the automatic transmission equipped with the fluid torque converter.
Conventionally, the hybrid vehicle is provided with not only the engine but the electric motor (herein "motor") to improve fuel efficiency (see JP Application Laid-Open No. H09-84210 and JP Application Laid-Open No. 2000-197209). In this hybrid vehicle, the motor assists the drive torque if the engine load is heavy or the torque ratio of the torque converter is large, whereas the motor does not assist the drive torque if the engine load is light or the torque ratio of the torque converter is small, so that the motor is driven frequently in a range the efficiency of the engine is relatively high.
However, there are some problems if the motor assists the drive torque under a condition where the engine load is heavy or the torque ratio of the torque converter is large.
That is, under a condition where the engine load is heavy, the torque that the automatic transmission receives, i.e., transmission input torque, becomes large. As shown in FIG. 7, if the ratio "e" between input and output speeds of the torque converter (turbine rotational speed/pump rotational speed) is small, the transmission input torque becomes larger due to the fact that the torque is multiplied by the torque converter before the coupling point. In other words, the torque converter has efficiency "n" increased due to movement of a stator, thereby increasing torque ratio "t". If the electric motor assists the engine under this condition, the transmission input torque may exceed a permissible value or capacity, thereby reducing durability of the automatic transmission.
To obviate this problem, the vehicle is typically provided with an automatic transmission having a large permissible value or capacity for receiving the input torque. However, the larger the permissible capacity for input torque, the heavier and larger the automatic transmission becomes, and the greater the torque lost owing to the friction in the automatic transmission, which is disadvantageous in improving fuel efficiency.

Controller with motor output torque limiter for hybrid vehicle


The present invention is aimed to provide a cost-effective optical glass with refractive index of 1.74-1.80 and Abbe number of 47-51 but containing no Gd2O3 and an optical element made hereof. The optical glass contains the following components according to percentage by weight: more than 2.7% but less than 10% of SiO2, 20-31% of B2O3, 38-49% of La2O3, more than 12% but less than 20% of Y2O3, more than 1% but less than 4% of ZnO, more than 0.5% but less than 3% of Nb2O5, wherein the content of ZnO is more than that of Nb2O5, 0-5% of Ta2O5, 0-5% of RO, wherein the RO is one or more of CaO, SrO and MgO, and content of ZrO2 is more than 6.7% but less than 15%. The present invention is a lanthanum borate glass containing no Gd2O3. A stable glass can be obtained by adjusting the content of La2O3, B2O3 and Y2O3.

In recent years, with the increasing integrated level and rapidly increasing functions of the equipment applied in the optical system, the optical system is required to be more accurate, lighter and smaller. In order to meet the refractive index of 1.74 to 1.80 and Abbe number of 47 to 51, the optical glass is often B2O3—La2O series. Japanese patent application laid-open No. 2006-117506 discloses an optical glass with refractive index of 1.74-1.80 and Abbe number of 47-51. However, the optical glass contains 25-35% (by wt %, hereinafter the same) of Gd2O3. Gd2O3 is rare earth oxide and expensive so that the optical glass is featured in high cost.


Systems and methods that provide audio feedback in response to gesture validity can provide a more intuitive interface that can train users to correctly complete gestures. Moreover, systems and methods that provide line-specific audio feedback can provide more specific feedback that can allow a user to better understand what sensing line is being contacted. The systems and methods can further include basing the audio feedback based at least in part on obtained activity data, such that invalid and valid feedbacks can provide different sounds dependent on the determined activity state.

Touch based ambient devices which use gestures as an input mechanism require accurate motions from users to ensure accurate gesture recognition. Gestures performed by users however, have a great degree of variability, which can make it very difficult for the machine learning algorithms to recognize the user's intent. Even with visual or haptic feedback users may still be confused as to what is an acceptable versus what is an unacceptable gesture. This leads to reduced recognition rates during runtime, and higher frustration by users.
Moreover, inputs can be limited for some devices, and devices may fail to leverage activity dependent data for different inputs, which can further restrict the corpus of inputs available.

Activity-dependent audio feedback themes for touch gesture inputs


A system and method for providing RFID dynamic content presentation using wireless devices and RFID technologies. The method comprises providing a wireless capable device which is configured to receive RFID information and store the RFID information in storage for later retrieval. The system is an infrastructure which comprises at least one RFID tag which stores RFID information; and a wireless capable device which is configured to receive the RFID information and store the RFID information in storage for later retrieval.

Wireless and other types of technology have become ubiquitous in today's daily life. These wireless technologies include cellular telephones, the Internet, wireless Internet access (WiFi), GPS and RFID technologies, to name a few. These technologies are used over a broad range of applications, including personal usage to consumer transactions, to entertainment to business to business applications. As such, these technologies have evolved over the years to become increasingly more important to business transactions, including retail transactions, etc.
For example, RFID technology is used to track merchandise throughout the supply chain, including the purchasing of merchandise by the consumer. GPS, on the other hand, is used for personal usage to find retail outlets, residential locations, etc. Likewise, WiFi is used to access the Internet from many different locations, for many different types of usages, including personal and business usage. This technology allows a user to conduct business regardless of their whereabouts, with the caveat that they are near a WiFi hub.
Many technologies have evolved in such a way that the combination of the technologies have provided a synergistic effect. This, as such, has increased the effectiveness and workability of the technology to such an extent that they play a critical role in business. As an illustrative example, the combination of the Internet and WiFi has made the Internet that much more accessible to a user, regardless of their location. This allows the user to conduct business transactions more efficiently, such as track inventory, purchase items and maintain contact with an array of business associates and colleagues.
However, there is a need to increase the synergistic effects of different technologies. By doing so, it would be possible to increase the ability and efficiency to transfer and/or obtain content. Accordingly, there exists a need in the art to overcome the deficiencies described hereinabove.

System and method for RFID dynamic content presentation

International Business Machines Corporation


A writing method for a solid state disk is disclosed. The method comprises following steps: A writing unit is arranged in a buffer memory, wherein plane addresses of the writing unit are in one-to-one correspondence with non-volatile memories of the solid state disk. A writing data is received. A reordered plane address of the writing unit is obtained by using the residue of the logical allocation address of the writing data dividing the plane address number. Whether the reordered plane address is empty is checked. If the reordered plane address is not empty, the next plane address is shifted and the plane address is reordered. If the reordered plane address is empty, the writing data is buffered to the reordered plane address and the logical allocation address of the writing data is arranged in order.

1. Field of the Invention
The invention relates in general to a writing method for a solid state disk, and more particularly to a writing method for a solid state disk in which data is reordered in a buffer memory before being written to a non-volatile memory.
2. Description of the Related Art
Solid state disk (SSD) is formed by integrating a plurality of non-volatile memories (NVMs) into a single storage device. The solid state disk, having a fast data transmission rate which is beneficial to the transmission of a large volume of data, has become an essential data storage device to modern computer systems.
As indicated in FIG. 1, a schematic diagram of a data writing procedure of a solid state disk according to prior art is shown. A host, such as a computer system, uses a processor to output writing data with logical allocation address (LAA) such as writing data LAA(0, 8, 2, 3, 4, 5, 6, 7, 1, 9, 10, 11, 12, 13, 14, 15). The writing data is received by a controller of a solid state disk and buffered in a buffer memory. Based on the order of reception, the writing data which correspond to non-volatile memories 0-7 are divided into a plurality of writing units, such as writing unit 1 and writing unit 2, wherein the writing data 1 is LAA (0, 8, 2, 3, 4, 5, 6, 7), and the writing data 2 is LAA (1, 9, 10, 11, 12, 13, 14, 15). Then, the writing data are distributed to writing units and stored to corresponding non-volatile memories in parallel via respective first in first out (FIFO) channels of non-volatile memories 0-7, such that the write rate can be increased.
When reading data, the solid state disk receives a read request from the host, and distributes the read request and registers it in respective read request queues of the non-volatile memories. Then, based on the order of the read request in the read request queues, the data stored in the non-volatile memories are read in parallel on a FIFO basis, and are outputted via respective FIFO channels. The outputted data are arranged by the controller and stored in a dynamic random access memory (DRAM) of the host. Therefore, through the use of respective FIFO channels of the non-volatile memories, the solid state disk can read data in parallel via multi-channels to increase the read rate.
However, when the host needs to read data LAA(0,1,2,3,4,5,6,7), the non-volatile memory 0 cannot read and output two required data LAA(0,1) because each non-volatile memory of the solid state disk is restricted by its corresponding FIFO channel. In the first schedule, the non-volatile memory 0 can only read data LAA(0) and output LAA(0) together with LAA(2,3,4,5,6,7) read by the non-volatile memories 2,3,4,5,6,7 in parallel. In the second schedule, the non-volatile memory 0 alone reads and outputs data LAA(1). Under such design, the solid state disk takes a longer time to read data, and multi-channel parallel reading efficiency of the solid state disk will be reduced.
The solid state disk distributes the received writing data to each non-volatile memory and further uses parallel multi-channels to increase the writing rate. However, when data is written based on the order of reception alone, different writing data with continuous or similar logical allocation addresses may be written to the same non-volatile memory. When reading data, due to the jamming in the FIFO channel, the overall read/write efficiency of the solid state disk will deteriorate. Therefore, the solid state disk still has many problems to tackle with when it comes to the writing method.


High-temperature oil returning from a cylinder head is to be prevented from being sucked directly into an oil pump through an oil strainer. An oil intake space is defined by partition walls formed near a split plane of both a front casing and a rear casing. The interior of the oil intake space is partitioned into a lower oil chamber and an upper oil chamber by an oil strainer. The lower oil chamber is in communication with the interior of an oil pan through intake ports, while the upper oil chamber communicates with an oil pump. The oil strainer is separately formed as an intake duct and a screen. The oil strainer is fitted and held in a slot formed in the partition wall.

1. Field of the Invention
The present invention relates to an oil intake structure of an engine for suctioning oil located in the lower portion of an engine casing into an oil pump through an oil strainer.
2. Description of the Background Art
Various oil intake structures of an engine are known in the art. For example, Japanese Patent Laid Open No. 166205/89 discloses an oil strainer chamber defined by a partition wall in the bottom of an oil pan, with a self-locking door provided in an opening formed in the partition wall. The arrangement it is intended to keep the oil level in the interior of the oil strainer chamber constant to thereby prevent air inclusion in the oil strainer.
In the above conventional oil intake structure, since the upper portion of the oil strainer chamber is open, high-temperature oil dripping from the cylinder head flows directly into the oil strainer chamber, then through the oil strainer into the oil pump. Consequently, the engine cooling performance is diminished by allowing the high-temperature oil to be immediately returned to the oil pump for delivery to the engine parts.


An impact of configuration changes on controllers is projected, in a computing environment including one or more bridge attached channels. This projection quantifies the impact for each controller affected by the change, such that it is known by a quantifiable value how much the change impacts the controller. In order to project the impact, a projected I/O velocity of the controller is determined. In making the projections, pseudo channels associated with a particular bridge attached channel are modelled as independent channels. Alternatively, a utilization metric of a bridge attached channel is determined and compared to a threshold; pseudo channels associated with the bridge attached channel are modelled as independent channels if the utilization metric is below the threshold.

The management of workload plays an important role in computing environments today. Thus, various aspects of processing within a computing environment are scrutinized to ensure a proper allocation of resources and to determine whether any constraints exist. One type of processing that is scrutinized is I/O processing.
In I/O processing, workload management includes properly allocating different kinds of channels to control units. To determine whether the allocation is sufficient, channel delay is measured. Previously, the metric of channel delay included measuring the response times. In application Ser. No. 09/676,715, "Method, System and Program Products for Projecting the Impact of Configuration Changes on Controllers," Johnson et al., previously incorporated herein by reference, the metric used is channel pending time.
When it is determined that the allocation is insufficient, then various changes need to be made. The cost of making these changes is expensive and thus, a need exists for a technique for projecting the impact of configuration changes on the control units, prior to making the adjustments. In particular, a need exists for a capability that quantifies the impact of a change on one or more control units to be affected by that change.
Furthermore, I/O configurations exist where one or more channels are connected, either directly or indirectly, to a bridge device. Such a channel is referred to as being bridge attached. A bridge device may perform either or both of the following functions. First, a bridge device may perform protocol conversion, allowing a device using one protocol to communicate with a device using a different protocol. Second, a bridge device may perform capacity matching, providing a mechanism for communicating the information from two or more low capacity links over a single high capacity link. In computing environments having one or more bridge attached channels, a further need exists for projecting the impact of configuration changes which takes into account the capabilities of bridge attached channels.

This patent is subject to a terminal disclaimer.

I/O velocity projection for bridge attached channel

International Business Machines Corportion