A highly reliable semiconductor device having an underlying film with a trench and a conducting material film formed in the trench, a method of manufacturing the same and a method of forming a resist pattern used therein are obtained. The underlying film having an upper surface and the trench is formed. The conducting material film is formed on the upper surface and in the trench. A photo resist film is formed on the conducting material film located on the upper surface of the underlying film and in the trench. The photo resist film is left in the trench whereas the photo resist film is developed and removed outside the trench. The conducting material film located on the upper surface of the underlying film is etched and removed with the photo resist film left in the trench used as a mask.

1. Field of the Invention
The present invention relates to a semiconductor device, a manufacturing method thereof and a method of forming a resist pattern used therein. More particularly, the present invention relates to a semiconductor device having a conducting material film formed in a trench, a manufacturing method thereof and a method of forming a resist pattern used therein.
2. Description of the Background Art
In the field of a DRAM (Dynamic Random Access Memory), which is conventionally known as one type of the semiconductor device, efforts have been made to increase capacity and miniaturize the device. Along with these efforts and achievements, to secure a capacity necessary for a capacitor cell, which is an element of a DRAM, within a limited area of a semiconductor substrate, three-dimensional cells such as a trench type cell or a stacked type cell have been developed. Among the stacked capacitor cells, those with vertically long shape such as a cylindrical type cell or a thick film type cell are mainly used.
FIGS. 17-19 show partial sectional views of a cylindrical stacked capacitor cell, on which the present invention is based and which is referenced for describing the manufacturing process of a lower electrode of a capacitor. With reference to FIGS. 17-19, the manufacturing process of the capacitor lower electrode of the cylindrical stacked capacitor cell will be described.
As shown in FIG. 17, a first interlayer insulation film 115 is formed on a semiconductor substrate (not shown). Openings 116a and 116b are formed in first interlayer insulation film 115. Plugs 117a and 117b are formed respectively in openings 116a and 116b for electrically connecting the capacitor lower electrode and a conducting region in a main surface of the semiconductor substrate. A second interlayer insulation film 123 is formed on first interlayer insulation film 115. Trenches 130a and 130b are formed in second interlayer insulation film 123 in regions above plugs 117a and 117b. Polycrystalline silicon film 119 is formed on second interlayer insulation film 123 as well as in trenches 130a and 130b. An HSG (Hemi Spherical Grained) polycrystalline silicon film 120 having a resist 127 formed thereon is formed on polycrystalline silicon film 119. Here, HSG polysilicon film means a polysilicon film having roughened surface, and to roughen (roughening) refers to a process of generating hemispherical grains by growing crystal grains.
With etch back of resist 127 using Reactive Ion Etching (hereinafter referred to as RIE), portions 127a and 127b of resist are left in trenches 130a and 130b as shown in FIG. 18 while resist 127 (see FIG. 17) is removed in other regions. Here, the level difference L1 between an upper surface of HSG polycrystalline silicon film 120 on second interlayer insulation film 123 and an upper surfaces of resists 127a and 127b is called recess length. As will be described hereinafter, as portions 127a and 127b of resist are used as masks for removing polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 on second interlayer insulation film 123, the recess length L1 must be controlled with a high precision. If the recess length L1 is too small and the upper surfaces of resist portions 127a and 127b are higher than the upper surface of second interlayer insulation film 123, problems arise. For example, upon etching for removing polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 on the upper surface of second interlayer insulation film 123, etching residue may be produced.
Then using resist portions 127a and 127b as masks, polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 on the upper surface of second interlayer insulation film 123 are etched and removed. Thus a capacitor lower electrode of polycrystalline silicon film 119a and HSG polycrystalline silicon film 120a is formed in trench 130a and a capacitor lower electrode of polycrystalline silicon film 119b and HSG polycrystalline silicon film 120b is formed in trench 130b as shown in FIG. 19.
Then resist portions 127a and 127b are removed and a dielectric film, a capacitor upper electrode and so on are formed on the capacitor lower electrode. The cylindrical stacked capacitor cell is thus formed.
The process shown in FIGS. 17-19 has a following problem. When the resist is etched back by RIE to leave resist portions 127a and 127b only in trenches 130a and 130b as shown in FIG. 18, an oxide film or the like is sometimes partially formed on the surface of HSG polycrystalline silicon film 120 on the upper surface of second interlayer insulation film 123. The oxide film thus formed through RIE serves as a mask upon etching of polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 for isolating the capacitor lower electrode trench by trench. Therefore polycrystalline silicon film 119 of HSG polycrystalline silicon film 120 is sometimes partially left on the upper surface of second interlayer insulation film 123.
When polycrystalline silicon film 119 or the like is left on the upper surface of second interlayer insulation film 123, the capacitor lower electrode is not sufficiently isolated, and whereby a problem such as short circuit of the capacitor lower electrode is caused. As a result, operation failure and reliability degradation of the DRAM occur.
Alternatively, CMP (Chemical Mechanical Polishing) can be used for removing resist 127 (see FIG. 17) in the region outside trenches 130a and 130b for leaving resist portions 127a and 127b in trenches 130a and 130b. In this case, however, slurry used in CMP is left in the area such as an inner area of trenches 130a and 130b, and adversely affects the subsequent process steps. The slurry thus left in trenches 130a and 130b also causes operation failure and reliability degradation of the semiconductor device such as a DRAM.
An object of the present invention is to provide a highly reliable semiconductor device having a conducting material film formed in a trench.
Another object of the present invention is to provide a method of manufacturing a highly reliable semiconductor device having a conducting material film formed in a trench.
Still another object of the present invention is to provide a method of forming a resist pattern which can be used in the method of manufacturing the highly reliable semiconductor device having the conducting material film formed in the trench.
In the method of manufacturing the semiconductor device according to one aspect of the present invention, an underlying film having an upper surface and a trench is formed. A conducting material film is formed on the upper surface and in the trench. A photo resist film is formed on the conducting material film which is located on the upper surface of the underlying film and in the trench. The photo resist film is left in the trench whereas in other region the photo resist film is developed and removed. With the photo resist film left in the trench used as a mask, the conducting material film on the upper surface of the underlying film is etched and removed.
Thus, an etching technique such as RIE which is used in a conventional manufacturing process is not employed in the step of leaving the photo resist film in the trench and removing the photo resist film in the region outside the trench. Therefore the formation of oxide film on the conducting material film caused by etching can be prevented. As a result, in the step of removing the conducting material film on the upper surface of the underlying film, the conducting material film is prevented from being partially left on the upper surface of the underlying film because of the existence of the oxide film. Thus, failure such as short circuit caused by the residual conducting material film can be avoided, whereby a highly reliable semiconductor device can be obtained.
In addition, as the development is utilized in the step of leaving the photo resist film in the trench, the thickness of the photo resist film to be removed and therefore the level of the upper surface of the photo resist film left in the trench can be controlled with high precision by controlling the time of development.
In the method of manufacturing the semiconductor device in accordance with one aspect of the present invention, the photo resist film in the region outside the trench may be exposed before the development.
Then the thickness of the exposed photo resist film, which is to be removed in the step of removing the photoresist film outside the trench, can be controlled by the control of exposure energy when a positive photo resist film is used. Therefore, the level of the upper surface of the photo resist film left in the trench can be controlled more surely.
In the method of manufacturing the semiconductor device in accordance with one aspect of the present invention, the photo resist film in the region outside the trench may be completely exposed whereas the photo resist film to be left in the trench may not be exposed in the step of exposing the photo resist film.
As the photo resist film in the trench is not exposed when the positive photo resist film is used, the photo resist film can surely be left in the trench after the development.
In the method of manufacturing the semiconductor device in accordance with one aspect of the present invention, light used for the exposure may be directed obliquely for irradiation to the upper surface of the underlying film in the step of exposing the photo resist film.
Thus the light is prevented from reaching the bottom portion of the trench, because the light for exposure is not in a direction perpendicular to the extension of the upper surface of the underlying film. Therefore the exposure of the photo resist film at the bottom portion of the trench can surely be prevented. As a result, the photo resist film can surely be left in the trench.
In the method of manufacturing the semiconductor device in accordance with one aspect of the present invention, an angle of incidence of the light used for exposure with respect to the upper surface of the underlying film may be adjusted so that the light does not reach the photo resist film to be left in the trench in the step of exposing the photo resist film.
Thus the exposure of the photo resist film to be left in the trench can even more surely be prevented and the photo resist film can surely be left in the trench. In addition, the location in the trench where the light reaches can be adjusted by adjusting the angle of incidence of the light used for exposure with respect to the upper surface of the underlying film. As a result, the level of the upper surface of the photo resist film left in the trench can be controlled with high precision.
In the method of manufacturing the semiconductor device in accordance with one aspect of the present invention, the step of forming the underlying film may include the steps of: forming an underlying film with a planar upper surface; forming a resist pattern for forming a trench on the upper surface using a photo resist film for pattern formation; and forming the trench by removing the underlying film using the resist pattern as a mask. The photo resist film may be less sensitive to the light than the photo resist film for pattern formation.
Thus, even when the exposure energy upon photo resist film exposure varies, the fluctuation of the thickness of the exposed portion of the photo resist film can be made smaller than when the photo resist film for pattern formation is used. As a result, the fluctuation of the level of the upper surface of the photo resist film left in the trench can be made smaller than in a conventional art.
In the method of manufacturing the semiconductor device in accordance with one aspect of the present invention, the step of forming the photo resist film may include a step of forming the photo resist film such that the non-exposed portion with the thickness of the photo resist film to be left in the trench is left even when the exposure energy is increased in the step of exposing the photo resist film.
Thus the delicate control of the exposure energy in the step of exposing the photo resist film is not necessary for adjusting the thickness of the exposed portion of the photo resist film and for leaving the non-exposed portion of the photo resist film with the necessary thickness in the trench. Therefore, even when the exposure energy varies, and even if the light with the exposure energy above a predetermined value is directed to the photo resist film, the non-exposed portion with a predetermined thickness can be formed and whereby the photo resist film with the predetermined thickness can surely be left in the trench.
In addition, as the thickness of the exposed portion can be determined by the chemical composition of the photo resist film, the thickness of the non-exposed portion of the photo resist film can be controlled with higher precision than when the thickness of the exposed portion is controlled by adjusting the exposure energy. As a result, more precise control of the level of the upper surface of the photo resist film left in the trench is allowed.
The method of manufacturing the semiconductor device in accordance with one aspect of the present invention may further include the step of forming under the photo resist film, a light absorption film absorbing the light used in the step of exposing the photo resist film.
Thus the light is prevented from reaching inside the underlying film, because of the existence of the light absorption film. Therefore, the exposure of the side surface and so on of the photo resist film in the trench, caused by the entrance and scattering of the light used in the step of exposing the photo resist film, in the underlying film under the photo resist film, can be prevented. As a result, the photo resist film can surely be left in the trench.
In the method of manufacturing the semiconductor device in accordance with another aspect of the present invention, an underlying film having an upper surface and a trench is formed. A conducting material film is formed on the upper surface and in the trench. A photo resist film having an upper surface is formed on the conducting material film in the trench. The level of the upper surface of the photo resist film is made lower than the level of the upper surface of the underlying film through curing of the photo resist film. The conducting material film on the upper surface of the underlying film is etched and removed with the use of cured photo resist film as a mask.
Here, the curing is a treatment for hardening and shrinking the photo resist film by directing an ultra violet ray (Deep UV) or conducting a heat treatment on the photo resist film. At curing time longer than a predetermined period, volumetric shrinkage of the photo resist film shows a certain threshold value.
Because of this certain threshold value of volumetric shrinkage of the photo resist film at the curing time longer than a predetermined amount, with the adjustment of the thickness of the photo resist film prior to the curing, the height of the upper surface of the photo resist film after the curing can be correctly controlled.
In addition, the formation of the oxide film on the conducting material film can be prevented because technique such as RIE is not employed in the step of forming the upper surface of the photo resist film at a level lower than the upper surface of the underlying film. Thus in the step of removing the conducting material film located on the upper surface of the underlying film, a portion of the conducting material film is prevented from being left on the upper surface of the underlying film, which is caused by the existence of the oxide film. As a result, failure such as a short circuit which is attributable to the residual conducting material film can be prevented, and whereby a highly reliable semiconductor device can be obtained.
In a method of forming a resist pattern in accordance with still another aspect of the present invention, the resist pattern is formed on an underlying film having an upper surface and a lower upper surface lower than the upper surface and adjacent to the upper surface with a step side wall therebetween. In this method, a photo resist film is formed on the upper surface, the step side wall, and the lower upper surface. The photo resist film formed in a region other than the bottom portion of the step side wall is exposed by the light incident obliquely on the upper surface. A non-exposed portion of the photo resist film is left at the bottom portion of the step side wall and the exposed portion of the photo resist film is removed by development.
With the use of the light directed obliquely to the upper surface for the exposure of the photo resist film, the exposure of the photo resist film at the bottom portion of the step side wall can surely be prevented. Thus, the non-exposed portion of the photo resist film can surely be left at the bottom portion of the step side wall.
In addition, the amount of the photo resist film left at the bottom portion of the step side wall can be controlled through the adjustment of the angle of incidence of the light used for exposure with respect to the upper surface.
A semiconductor device in accordance with still another aspect of the present invention includes an underlying film having a trench, a conducting material film formed in the trench, and, a light absorption film formed on the conducting material film, for absorbing the light used in photolithography for forming the conducting material film.
Thus, in the step of forming the conducting material film in the trench, as the light used in the exposure/development is absorbed by the light absorption film, even when the photo resist film is formed in the trench and on the underlying film outside the trench, and the photo resist film outside the trench is removed by the exposure/development, the light is prevented from reaching the underlying film and the conducting material film. Therefore, the light is not scattered in the underlying film and the conducting material film, and the exposure of the side surface and the bottom surface of the photo resist film in the trench can be prevented. As a result, the photo resist film can surely be left in the trench. Thus the failure caused by the partial absence of the photo resist film in the trench, such as the removal of the conducting material film which is to be left in the trench can be prevented in the step of forming the conducting material film in the trench.
In the semiconductor device in accordance with the still another aspect of the present invention, the conducting material film may be a capacitor lower electrode, and the device may further include a dielectric film formed on the capacitor lower electrode and a capacitor upper electrode formed on the dielectric film.
In the semiconductor device in accordance with the still another aspect of the present invention, the light absorption film may be a silicon nitrided oxide film.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor device having conducting material film formed in trench, manufacturing method thereof and method of forming resist pattern used therein


A computer keyboard optimized for generating multi-color text documents is described. A standard keyboard includes a plurality of selected function keys that are programmed to change the document text color when activated. The function keys are displayed on a computer display screen and each of the selected keys further includes color indicia to indicate the new text color that results from activation of that key and all color changes can be performed at the same normal typing speed.

The present invention relates to the field of computer keyboards, and more particularly to keyboards for which selected keys are programmed to effect text color changes and which are color encoded to indicate the resulting text color.
Most computer-generated documents have previously been printed with black text on white paper. When color was used in printed documents, it was common to minimize the number of colors used and the number of color changes due to the relative inconvenience of initiating text color changes. Even with the widespread availability of color printers, many documents such as letters, reports, and memos continue to be generated primarily in black and white despite a growing appreciation of the enhanced impact that multi-color documents can provide. One reason why computer users do not more freely utilize changes in text color to increase the visual impact of their correspondence and other documents is that most application software requires an inconvenient and relatively slow process to effect text color changes. A mouse may be used to manipulate icons on a function bar, but this requires removal of the hand from the keyboard. Effecting text color changes from the keyboard often requires a complicated multi-step series of keyboard strokes which are difficult to remember. Alternatively, the number of key strokes required to effect a text color change may be reduced by creating a programmed macro. If more than one or two text colors are so programmed, however, it becomes difficult to memorize the correspondence between the key combination that causes a particular color change and the desired color.


A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit.

The electricity meter is one of the devices that have conventionally been passively controlled but recently been required to perform active control using a data processing device including a central processing unit (CPU).
In the conventional electricity meter, the data processing device has been required to perform the function of measuring and recording the consumed amount of electric power generated by a power company and supplied through a power grid to each house, as well as the function of transmitting to the power company the recorded amount of power consumption through a predetermined communication line.
As for the electricity meter used for next-generation power grids, the data processing device is required not only to perform processing for measuring the amount of electric power distributed from the power company but also to perform processing such as processing for conducting reverse-power-flow control under which electric power from a power generation system such as photovoltaic cell or from a power storage system installed in each house is fed back to the power grid, as well as processing for offsetting the amount of distributed electric power and the amount of electric power fed back to the power grid.
Even a system like the electricity meter is required to reduce as much as possible the electric power consumed by the electricity meter itself. Regarding the data processing device performing the processing as described above, the period during which the data processing device is in the standby state is relatively longer than the period during which the data processing device is performing processing. It is therefore necessary to reduce not only the power consumption of the period during which the data processing device is performing processing but also the power consumption of the period during which the data processing device is in the standby state.
In order to minimize the power consumption of the data processing device in the standby state, the data processing device in the standby state is switched to a low power consumption state. For achieving this low power consumption state, it is necessary not only to stop supply of electric power to functional units including the central processing unit (CPU) and stop an oscillator which generates an operation clock in the data processing device, but also to reduce the power consumption of a power supply circuit itself in the data processing device.

First power-on reset circuit with higher power consumption than a second power-on reset circuit


A device includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors proximate to the first surface. The first semiconductor die is configured to have a flexibility compliance greater than a first pre-determined value in a direction substantially perpendicular to a plane including the plurality of proximity connectors in order to reduce misalignment in the direction between the plurality of proximity connectors and additional proximity connectors on another device.

1. Field of the Invention
The present invention relates to connector alignment for semiconductor dies. More specifically, the present invention relates to structures having flexibility compliance to facilitate communication of signals between semiconductor dies using proximity connectors.
2. Related Art
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, it becomes possible to transmit data signals directly from the first chip to the second chip without having to route the data signals through intervening signal lines within a printed circuit board.
Capacitive coupling depends on a relative position of the transmitter pads and the receiver pads, both in a plane defined by the pads and in a direction perpendicular to the plane. Misalignment in the plane may cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, satisfactory communication requires alignment such that misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. In addition, limiting overall misalignment may improve communication performance between the chips and reduce power consumption.
Unfortunately, it is not a simple matter to align the chips properly using existing mounting structures, such as conventional single-chip modules or conventional multi-chip modules. The chips in these structures are subject to thermal expansion and mechanical vibrations, as well as manufacturing and assembly perturbations that result in misalignment problems. In addition, existing approaches to compensate for or reduce misalignment in the plane of the pads may be less effective when there is significant misalignment in the direction perpendicular to the plane.
What are needed are single-chip modules and multi-chip modules that include one or more structures having flexibility compliance in the direction perpendicular to the plane to reduce misalignment in this direction and thereby facilitate capacitive inter-chip communication without the problems listed above.

Structures for Z-aligned proximity communication


The invention relates to a proton-conducting polymer membrane and to a method for the production thereof. Starting from a catalyst layer, which is homogeneously deposited on the polymer membrane (3), the catalyst layer is subdivided into a number of catalyst segments (1a, 1b) by microstructuring so that adjacent fuel cell units of a planar fuel cell arrangement can be realized in the smallest possible space.

The present invention relates to a proton-conductive polymer membrane as well as to a method for its manufacture.
Fuel cell systems are becoming more and more important with regard to the supply of voltage for mobile electric and electronic apparatus. For achieving commercially common voltages, several fuel cells are connected in series for the addition of individual voltages. With a planar fuel cell arrangement, this is realised by way of connecting several fuel cell units arranged in a plane in series. Each fuel cell unit on the cathode and anode side in each case has a gas distribution structure and a diffusion layer. These two reaction spaces are separated by a membrane electrode assembly (MEA). This is a proton-conductive polymer membrane which is catalytically coated in the region of the reaction spaces. A known arrangement for the series connection of fuel cell units is the so-called strip membrane fuel cell. With this, a transverse conductor structure penetrates through the plane of the membrane and by way of this connects the cathode side of a first fuel cell unit to the anode side of the adjacent fuel cell unit. However the leading of the transverse conductor through the plane of the membrane quickly leads to leakage (unsealedness) of the fuel cell system.
For an improved sealing and for reasons of manufacturing technology, it is therefore advantageous to separate the reaction spaces of the anode side from the cathode side by way of a continuous polymer membrane which however still needs to have a catalyst coating in the region of the reaction spaces.
Polymer membranes are known for this, which are catalytically coated in segmented regions. At the same time, the catalyst layers may be deposited on the polymer membrane in segments by way of roller deposition or hot pressing. With these mechanical deposition methods, minimum distances of several millimeters (about 3 mm) are necessary between the individual adjacent catalyst segments in order to achieve a clear separation of the individual segments from one another. Additional problems arise due to the fact that the membrane is heated or deformed on deposition (e.g. by way of hot pressing), and thus an exact positioning of the catalyst segment and membrane is rendered more difficult.
One basic disadvantage of the known polymer membrane with catalyst segments is thus that due to the large minimum distances between the catalyst segments which must be maintained, surface area remains unused, which thus is no longer available for voltage production, in miniaturised planar fuel cells.

Proton-conducting polymer membrane and method for the production thereof to simultaneously remove the catalyst layers

Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.


Flame retardant crosslinkable polyolefin compositions useful for the production of films, sheets and membranes are provided. The compositions are comprised of ethylene-silane copolymer, plastomer, flame retardant filler and, optionally, silanol condensation catalyst.

1. Field of the Invention
The invention relates to flame retardant, crosslinkable polyolefin-based compositions and articles produced therefrom. More specifically the compositions of the invention are comprised of an ethylene-silane polymer, an ethylene plastomer and a flame retardant filler. The compositions are used for the manufacture of films and sheets and are particularly useful for the production of roofing membranes.
2. Description of the Prior Art
Crosslinkable ethylene polymers having alkoxysilane functionality incorporated into the polymer either by grafting an unsaturated alkoxysilane onto an ethylene polymer backbone or directly copolymerizing ethylene with an unsaturated alkoxysilane are known. In the presence of moisture the alkoxysilane groups undergo hydrolysis and condensation reactions to form crosslinks. Silanol condensation catalysts are typically used to increase the rates of hydrolysis and condensation.
Crosslinkable ethylene polymers prepared by grafting unsaturated alkoxysilanes to ethylene polymers are disclosed in U.S. Pat. No. 3,646,155. Crosslinkable ethylene polymers prepared by copolymerizing ethylene with an unsaturated alkoxysilane are disclosed in U.S. Pat. Nos. 3,225,018 and 3,392,156.
Compositions of the above types are widely used for wire and cable insulation. For example, U.S. Pat. No. 6,197,864 discloses flame retardant insulation compositions comprised of 30 to 90 weight percent olefin-alkoxysilane copolymer derived from an α-olefin having from 2 to 8 carbon atoms and 0.25 to 20 percent by weight, based on the weight of the copolymer, of an unsaturated alkoxysilane of the formulaR*—Si(R**)a(Y)3-awherein R* is an ethylenically unsaturated hydrocarbon radical having from 2 to 6 carbon atoms, R** is a hydrocarbon radical having from 1 to 10 carbon atoms, Y is an alkoxy group having from 1 to 4 carbon atoms and a is an integer from 0 to 2; 5 to 40 weight percent halogenated organic compound; 1 to 20 weight percent antimony trioxide; 0.01 to 2.5 weight percent silanol condensation catalyst; and 1 to 40 weight percent magnesium hydroxide. Optional ingredients such as hindered phenol antioxidants and mineral fillers may also be included in the formulations.
Copending application Ser. No. 10/653,514, now U.S. Pat. No. 6,936,655, discloses wire and cable insulation compositions having improved abrasion resistance comprising 30 to 90 weight percent high density, bimodal silane-containing polyethylene base resin which can be a blend of a bimodal high density polyethylene resin having a density of 0.940 to 0.960 g/cm3, melt flow ratio from 50 to 300 and ratio of weight average molecular weight to number average molecular weight from 15 to 30 with an ethylene-silane copolymer or a bimodal high density polyethylene resin having a density of 0.940 to 0.960 g/cm3, melt flow ratio from 50 to 300 and ratio of weight average molecular weight to number average molecular weight from 15 to 30 grafted with a silane monomer; 5 to 70 weight percent flame retardant; and 0.01 to 1 weight percent silanol condensation catalyst.
Crosslinkable olefin-silane copolymers have also been utilized for roofing membrane materials. U.S. Pat. No. 4,722,961 discloses roofing membrane compositions comprising (a) a hydrolyzable polyolefin having a density less than or equal to 0.92 selected from the group consisting of (i) copolymers of ethylene and silane and (ii) silane modified polyethylenes wherein silane is present in an amount of about 0.5 to about 10 percent by weight based on the weight of the polyolefin, said polyolefin being present in the composition in an amount of about 20 to about 90 percent by weight based on the combined weight of components (a) and (b); (b) an ethylene-propylene-diene terpolymer rubber, said terpolymer rubber containing about 30 to about 85 percent by weight ethylene, about 15 to about 70 percent by weight propylene and about 1 to about 10 percent by weight diene, all percentages based on the weight of the terpolymer rubber, said terpolymer rubber being present in the composition in an amount of about 10 to about 80 percent by weight based on the combined weight of the components (a) and (b); (c) a particulate filler selected from the group consisting of carbon black and non-black reinforcing fillers, and mixtures thereof, said filler being present in the composition in an amount of about 10 to about 200 parts by weight per hundred parts by weight of components (a) and (b) combined; and (d) a compound selected from the group consisting of paraffin oils, naphthenic oils, and liquid polybutene, said compound being present in the composition in an amount of about 10 to about 100 parts by weight per hundred parts by weight of components (a) and (b).
Roofing membrane compositions derived from propylene polymers are disclosed by N. Dharmarajan, et al., in an article entitled "Metallocene Plastomer Based Thermoplastic Olefin Compounds Designed for Roof Membrane Applications," ANTEC 2001, pages 1694-1698 and in an article by T. A. Glogovsky, et al., entitled "Development and Characterization of a New Plastomer Designed for Single-Ply Roofing Membranes," ANTEC 2002 Plastics: Annual Technical Conference, Vol. 3: pg. 189. The compositions of the latter reference utilize ethylene-octene-1 plastomers produced using metallocene catalysts as one of the components with the propylene polymer.
Membranes produced in accordance with the above-referenced disclosures are deficient in flame retardance. Furthermore, the propylene polymer based compositions are not crosslinked which limits their utility to lower temperature membrane applications.
There is a continuing need for compositions which can be used for single-ply roofing membranes or multi-layer membrane constructions and particularly for crosslinkable, flame retardant, tear and puncture resistant compositions capable of withstanding prolonged exposure to the elements, i.e., wind, rain, sun, high and low temperatures, etc. Additionally, it would be even more advantageous if membranes formed from such compositions had good flexibility and heat sealability for ease of application. Heat sealability, i.e., the ability to seal overlapping material without the use of adhesives, is highly desirable since roofing membranes are typically installed as wide (6-12 foot) sheets which are overlapped and preferably heat welded to provide strong, watertight bonds between adjoining sheets. These and other advantages are achieved with the compositions of the invention.

Flame retardant crosslinkable compositions and articles


One or more hints can be presented during the entry of protected information. Traditionally, for security reasons, the protected information is displayed as ambiguous characters, hindering the ability to determine if there was an error inputting the information. A hash can be calculated from some or all of the protected information already input, and the resulting hash value can be used to select a hint. The hints can be selected from a relatively small number of easily distinguishable hints, including visual, auditory and sensory hints, or any combination thereof. The hints are not a globally unique identifier of the protected information and can, instead, be used to detect a deviation from the correct entry of the protected information.

Users of computing devices are increasingly requested for information that should be protected from malicious elements. For example, computing devices often require passwords to enable users to access even basic functionality. Additional passwords can then be required to access specific functions, software applications, data, or other resources through the computing device. Other information, such as social security numbers, credit card numbers, personal identification numbers, and other like information that is also to be protected is often requested by, and utilized by, computing devices.
One mechanism for protecting information from malicious elements, especially during its entry, such as by a user through a keyboard or other user entry device, is to display, not the data that the user is entering, but other non-descript elements, such as asterisks, dots, and the like. While such display tactics can prevent protected information from being captured, such as through visual surveillance means, they can also remove an important avenue of feedback for the user entering the information. In particular, because the same non-descript elements are displayed irrespective of the data entered by the user, the user cannot verify that they are entering the correct data.
One common mistake made by users when entering data is to accidentally activate the "caps lock" key, which causes the entry of different data than the user expected. However, mechanisms now exist whereby the activation of the caps lock key can be detected and the user can be informed of its activation, such as through a symbol representing the activation of the caps lock key, or through an explicit textual notification. Additional mechanisms have been developed that link a user's password to a globally unique indicator that cannot be generated other than by the exact password, but from which the user's password itself cannot be derived. Such a globally unique indicator can inform the user that they typed the password in correctly because that globally unique indicator only appears after the user has typed in their complete password, and only their password, correctly.

Providing hints while entering protected information


Embodiments of the present disclosure relate to a transfer head assembly and an LED transfer apparatus, and more particularly, to a transfer head assembly and an LED transfer apparatus in which a plurality of pickup units picks up LEDs, which are adhered to the upper surfaces of the LEDs, and transfers the LEDs to a display substrate. According to the embodiments of the present disclosure, a large number of LEDs located on a wafer substrate or a carrier substrate can be transferred in bulk to a display substrate. Thus, it is possible to rapidly perform the transfer process of the LEDs.

As the information-oriented society has been developed, demand for a display device for displaying an image is increasing in various forms. Recently, various display devices such as a liquid crystal display device, an organic light-emitting display device, and the like have been utilized.
Such display devices may include a display panel in which a plurality of sub-pixels is arranged, and various drive circuits for driving the sub-pixels, such as a gate drive circuit, a data drive circuit, and the like.
In a conventional display device, a display panel is configured by arranging transistors, various electrodes, various signal lines, and the like on a substrate, and a drive circuit that may be implemented as an integrated circuit is mounted on a printed circuit so as to be electrically connected to the display panel.
Such a display panel is becoming thinner as technology advances, thereby enabling a light-weighted display device to be realized.
Recently, a display device (hereinafter, also referred to as a micro display device) using a micro light-emitting diode (LED) having a structure suitable for a small-sized display device has appeared. The LED means an ultra-small LED having a size of several tens of m or less.
Such a micro display device uses LEDs themselves as pixels, and can be miniaturized and light-weighted, thereby providing various advantages in that it can be variously utilized in a smart watch, a mobile device, a virtual reality device, an augmented reality device, a flexible display device, etc.
In order to manufacture a micro display device, it is necessary to crystallize a plurality of LEDs on a semiconductor wafer substrate such as sapphire or silicon (Si), and to move the plurality of crystallized LEDs to a substrate having drive elements. A precise transfer process of placing the LEDs at positions corresponding to respective pixels is required.
Unlike conventional LEDs, such a transfer process requires precise processing because it is necessary to control diode chips having a size of several tens of μm, which is as small as a pixel size.
Since each pixel corresponds to a LED, it is necessary to transfer a large number of diode chips to a substrate on which drive devices are arranged.
However, a conventional transfer process or equipment have disadvantages in that a long time is taken for a transfer process because diode chips are picked up and transferred to a substrate one by one, and in that yield reduction or the like may be caused due to damage to diode chips because an adsorption or attraction method using air pressure or static electricity is mainly used.
Therefore, there has been a need to improve this.

Transfer head assembly and LED transfer apparatus


The printer 1 includes a controller 32 for feeding at least a sort of recording medium P to a feed mechanism, obtaining a tendency of degradation of feed accuracy with respect to at least one sort of the recording medium, calculating an adjustment value of feed accuracy based on the number of the recording medium in the past, based on the tendency, and adjusting a feed accuracy based on the calculated adjustment value.

1. Field of the Invention
The present invention relates to a recording apparatus including a feed accuracy adjustment apparatus. More particularly, the preset invention relates to a liquid ejecting apparatus such as an ink-jet type recording apparatus by ejecting liquid, for example ink, to ejected medium from the ink-jet type recording head.
Here, the liquid ejecting apparatus includes a printer, a copying machine or a facsimile which performs recording by injecting ink from the recording head onto the recording medium using an ink-jet type recording head, as well as any apparatus which makes the liquid to be adhered onto an exposed media corresponding to the recording medium by injecting any type of liquid suitable for a predetermined purpose instead of the ink from a liquid injection head corresponding to the ink-jet type recording head.
Other than the above-mentioned recording head, the liquid injection head includes a coloring-material injection head used for color filter manufacturing such as a liquid crystal display, an electrode material (conductive paste) injection head used for electrode formation of an organic EL display, a field emission display (FED), etc., and an organic substance injection head used for biochip manufacture, a specimen injection head as a precision pipette, and the like.
2. Description of the Related Art
A feed apparatus for feeding recording medium in a recording medium such as an ink-jet type printer, generally includes a feed paper drive roller (so-called a feed roller), and a feed paper driven roller. The feed apparatus feeds the recording medium to the recording mechanism via these rollers and executes an accurate transporting and an accurate recording. Recently, there are some papers that are required to record more accurately, for example a PM photo paper (a name of commodity of Seiko Epson Corporation), and consequently, it becomes important to control the feed accuracy when feeding the recording medium.
In a conventional method for controlling the feed accuracy, an average feed error with respect to plural recording medium is obtained in every sort of the recording medium, and then, a correction for feeding is respectively executed in a direction so that the average error approaches to zero as disclosed, for example, in Japanese Patent Application Publication (Laid-Open) No. 2002-120421. Here, an actual feed error varies according to the increase of the number of the transported recording medium, when starting to use a new feed apparatus. However, this variation is not taken into consideration in the conventional method. Thus, a correction corresponding to the actual feed error is not executed, and consequently, it is impossible to keep the feed accuracy of the recording medium optimal constantly.
The present inventors found the fact that although the feed error increases according to the number of the recording medium, after feeding of a certain number of the recording medium, the increasing amount of the feed error is approximately zero, and consequently the feed error becomes a constant value, by feeding some sorts of plural the recording medium to the feed mechanism experimentally.

Feeding accuracy adjustment apparatus, recording apparatus, liquid ejecting apparatus, feeding accuracy adjustment method for recording medium


A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels. In the code definition and implantation process, a selected number of the channel regions are diffused with impurities so as to set the associated memory cells with a first threshold voltage representing the storage of a first binary digit; while the threshold voltage of all the other channel regions that are not diffused with impurities are set to a second threshold voltage representing the storage of a second binary digit. In the method of fabricating the ROM device, the bit lines are not formed by diffusing impurities into the silicon substrate. As a result of this, the drawbacks of lateral diffusion, junction leakage, and reduced breakdown voltage are not experienced when the ROM device is further miniaturized.

1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells for data storage and a method of fabricating the same.
2. Description of Related Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the data to be permanently stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
Most ROMs are identical in semiconductor structure except for the different data stored therein. Therefore, the ROM devices can be fabricated up to the stage ready for the programming and then the semi-finished products can be stocked in inventory awaiting customer orders. The customer then furnishes the data to the factory where the data are to be stored into the semi-finished ROMs by using the so-called mask programming process. This procedure is now a standard method in the semiconductor industry for fabricating ROMs.
In most ROMs, metal-oxide semiconductor field-effect transistors (MOSFET) are used as the memory cells for data stored. In the mask programming stage, impurities are selectively diffused into specific channels in the MOSFET memory cells so as to change the threshold voltage thereof, thereby setting the MOSFET memory cells to ON/OFF states representing different binary data. The MOSFET memory cells are connected to the external circuits via a plurality of polysilicon-based word lines and bit lines. The channel regions are located beneath the word lines and between each pair of adjacent bit lines. Whether one MOSFET memory cell is set to store a binary digit of 0 or 1 is dependent on whether the associated channel is diffused with impurities or not. If the associated channel is diffused with impurities, the MOSFET memory cell is set to have a low threshold voltage, effectively setting the MOSFET memory cell to a permanently-ON state representing the storage of a binary digit of 0, for example; otherwise, the MOSFET memory cell is set to have a high threshold voltage, effectively setting the MOSFET memory cell to a permanently-OFF state representing the storage of a binary digit of 1.
Referring to FIG. 1, there is shown the circuit diagram of a conventional mask ROM device 10, which includes a plurality of crosswise-arranged parallel-spaced word lines [ WL0, WL1, WL2, WL3] and a plurality of lengthwise-arranged parallel-spaced bit lines [BL0, BL1, BL2, BL3, BL4]. Each segment of the word lines located between one neighboring pair of the bit lines is the location where one MOSFET memory cell is formed. The binary data stored in each MOSFET memory cell is dependent on the threshold voltage of the same. For instance, if one MOSFET memory cell is custom-made with a low threshold voltage, it means that this MOSFET memory cell is set to a permanently-ON state representing the permanent storage of a binary digit of 0, for example. Conversely, if the MOSFET memory cell is custom-made with a high threshold voltage, it means that this MOSFET memory cell is set to a permanently-OFF state representing the permanent storage of a binary digit of 1, for example. In FIG. 1, for example, those memory cells that are set to store a binary digit of 1 are indicated by the labeling of a black box between the source/drain electrodes, as indicated by the one labeled with the reference numeral 14. Conversely, those memory cells that are not labeled with a black box are set to store a binary digit of 0, as indicated by the one labeled with the reference numeral 12.
To read data from the ROM device, a specific potential is applied to the corresponding bit lines and word lines. For instance, to read data from the memory cell 12 (which has a low threshold voltage indicating the storage of the binary data of 0), a potential is applied to the gate of the memory cell 12 via the word line WL0 and the drain of the same via the bit line BL0. Since the memory cell 12 is custom-made with a low threshold voltage, the applied potential will turn ON the MOSFET memory cell, thus causing a change in the current flowing in the bit line BL0. By contrast, since the memory cell 14 is custom-made with a high threshold voltage, the applied potential will not cause a change in the current flowing in the corresponding bit line BL2. By detecting the current changes in the bit lines, the external circuitry can determine whether the data is 0 or 1.
Referring to FIG. 2, there is shown a top view of the layout of part of the conventional ROM device of FIG. 1. This ROM device is based on a P-type silicon substrate 20. Through ion implantation with an N-type impurity material at selected areas on the silicon substrate 20, a plurality of parallel-spaced buried bit lines 22, 26 and complementary bit lines 24, 28 are formed. The buried bit lines 22, 26 are connected to a voltage source V, while the complementary bit lines 24, 28 are connected to ground. The ROM device is further formed with a plurality of parallel-spaced word lines WL0, WL1 intercrossing the buried bit lines 22, 26 and complementary bit lines 24, 28 substantially at right angles. This forms a plurality of MOSFET memory cells 30 (as indicated by the dashed boxes in FIG. 2) which have a low threshold voltage, and a plurality of MOSFET memory cells 32 which have a high threshold voltage.
Referring to FIG. 3, there is shown a schematic sectional diagram of a part of the ROM device of FIG. 2. This sectional diagram is used in particular to depict the programming of data into the ROM device. First, a silicon substrate 15 is prepared. Then, an N-type impurity material, such as arsenic (As), is diffused by means of ion implantation into selected regions of the silicon substrate 15 to form a plurality of parallel and substantially equally spaced N.sup.+ diffusion regions 11 serving as a plurality of bit lines. One channel region 16 is formed between each neighboring pair of the N.sup.+ diffusion regions (bit lines) 11. Subsequently, a thermal oxidation process is conducted on the wafer. Due to different oxidation rates at different regions, a thick oxidation layer 17a (which serves as an isolation layer) is formed over the N.sup.+ diffusion regions (bit lines) 11, while a thin oxidation layer 17b is formed over each channel region 16. After that, a plurality of parallel-spaced polysilicon layers 13 (which serve as word lines) are formed over the wafer in such as manner as to intercross the underlying N.sup.+ diffusion regions (bit lines) 11 substantially at right angles (only one of the polysilicon layers 13 is visible in the sectional diagram of FIG. 3 ). This completes the semi-finished product of the ROM device.
In the mask programming process, a mask 19 covers the top surface of the semi-finished product of the ROM device. This mask 19 is predefined to form a plurality of openings to expose those channel regions that are associated with the MOSFET memory cells that are to be set to a permanently-ON state. A P-type impurity material, such as boron, is diffused by ion implantation through the openings in the mask 19 into the corresponding channel regions. This completes the so-called code implant process.
In the finished product of the ROM device, the doped channels cause the associated MOSFET memory cells to have a low threshold voltage, thus setting them to a permanently-ON state representing the storage of a binary digit of 0. On the other hand, the undoped channels cause the associated MOSFET memory cells to have a high threshold voltage, thus setting them to a permanently-OFF state representing the storage of a binary digit of 1.
The foregoing ROM device, however, has the following two drawbacks. First, when the ROM device is further miniaturized, the application of a high concentration of impurities to selected channel regions could cause the undesired phenomena of lateral diffusion, junction leakage, and reduced breakdown voltage. This is due to the fact that the buried bit lines in the conventional ROM device are formed by implanting impurities into the silicon substrate. Second, since the process for fabricating the conventional ROM device involves the use of thermal oxidation to form the isolating oxidation layers, the planarization of the wafer surface is not very satisfactory. Poor planarization adversely affects the performance of the ROM device.

Semiconductor read-only memory device and method of fabricating the same


A device for selectably passing a wire through a cap of an insulation displacement connector to a point beyond the connector. A wire is inserted into a passage in the cap and exits the passage through an exit aperture in the cap. A stop wall is positioned in spaced confronting relationship with the exit aperture. The stop wall is dimensioned and shaped so that when the wire exits the exit aperture, the wire contacts the stop wall and is inhibited from passing beyond the stop wall, yet when the wire is selectively guided around the stop, the wire is passed beyond the connector.

Telephone lines, which are carried by electrical conductors known as tip ring wires pairs, originate from a central office (CO) and are aggregated at a particular point in a building prior to being distributed and connected to various types of telephone equipment, such as, for example, telephones, fax machines, modems etc., in the building. The tip ring wire pairs, which generally enter the building as part of a multi-conductor cable, are connected to a junction box known as, for example, a building entrance protector (BEP) or network interface unit (NIU). Within the junction box, the individual telephone line tip ring wire pairs are separated from the cable, individually connected to a connector block, and made available for further electrical connection and distribution.
The connector block, also known as an insulation displacement connector (IDC) block, may be the ubiquitous punch down connector block, also known as a 66-type connector block, or the tool-less insulation displacement connector block utilizing punch cap connectors, such as that described in the U.S. Pat. No. 4,913,659 dated Apr. 3, 1990, the entire disclosure of which is incorporated herein by reference. The IDC connector block is commercially available under the product designation SC99 from Lucent Technologies Inc.
The tool-less insulation displacement connector block includes an IDC type connector on one side of the connector block. The IDC connector includes a connector cap that is moveable from an up position, for facilitating insertion of the wire, to a down position, where the wire is brought into mechanical and electrical contact with a terminal strip disposed in the IDC connector. Opposite the IDC on the other side of the connector block is a matching, electrically connected wire wrap end of the terminal strip, such that a wire connected on the wire wrap side may be connected to another wire coupled to the IDC side of the block.
In operation, the connector cap of the IDC connector is initially in the up position and a tip ring wire is inserted into an entrance aperture in the connector cap. The wire is then urged through a wire passage disposed in the connector cap until it exits the cap through an exit aperture. After the wire is inserted through the connector cap, the connector cap is pushed down which causes the wire to be gripped by the terminal. Typically, the portion of the tip ring wire that extends beyond the exit aperture in the connector cap is trimmed so that the wire is flush with the connector cap surface. In this way, the excess wire does not interfere with other connectors on the connector cap. However, in some instances, it is desirable to pass the tip ring wire from the connector to another connector on the connector block so that a single tip ring wire pair may be branched across multiple terminals.
A significant drawback of the prior art IDC connectors is that when the portion of the tip ring wire that exits the IDC connector is trimmed, the trimmed section can fall on the connector block and cause an electrical short between terminals on the block, or fall into the BEP or NIU or other associated equipment. Furthermore, the step of trimming the excess wire portion is labor intensive, especially when wire density is high, which increases the cost associated with installation of the connector block. Accordingly, there exists a need in the art for a device that eliminates the need to trim the excess portion of the tip ring wire while also selectably providing for the routing of the wire from the connector to other connectors on the connector block, or to other connection points.

Wire pass through device for an insulation displacement connector


A sunshade panel apparatus includes a first sunshade panel, a second sunshade panel and a third sunshade panel a first connecting mechanism connecting the second sunshade panel and the third sunshade panel so that the second sunshade panel and the third sunshade panel are moved integrally or relatively; a guide rail supporting the first, second and third sunshade panels to be slidable within the same plane; and a panel housing portion for storing the first, second and third sunshade panels overlapping one another in parallel and provided with inclined guiding portions to move the first, second and third sunshade panels in parallel in an upward direction of the vehicle, wherein the first connecting mechanism has a supporting portion, an engagement groove, an engagement portion; and a biasing member.

In sunroof apparatuses formed with an opening on the roof of a vehicle, a fixed panel or a movable panel including a transparent glass plate is provided at the opening on the roof. In order to adjust the amount of the sunlight taken through the panel into a vehicle compartment, a known sunshade panel apparatus disclosed in, for example, JP2003-48433A is employed.
With the construction of the sunshade panel apparatus described in JP2003-48433A (i.e., paragraphs [0029], [0031], FIGS. 1 and 4), in a state where the sunshade panel is closed, plural panels, for example two panels, are arranged adjacent to each other within a plane in an extended state, whereas in a state where the sunshade panel is opened, the plurality of panels are arranged to be overlapped parallel to each other.
In order to achieve the arrangement structure as described above, the sunshade panel apparatus described in JP2003-48433A is structured as follows. A connection pin engaging with a tilting start portion of a bent guide trail provided at a first sunshade panel is provided at a second sunshade panel. Movement of the sunshade panel is transmitted to the second sunshade panel via the connection pin and the tilting start portion so that two panels synchronously move along a guide way extending along a straight line. When the second sunshade panel is moved to a predetermined opened position, a guide cam provided at the second sunshade panel is moved into a cross guide way portion utilizing a component of a force applying on the tilting start portion. Then, the second sunshade panel is lifted up and the first sunshade panel is slid under the second sunshade panel so that the sunshade panel overlaps the first sunshade panel, as a result, the first and the second sunshade panels are opened.
According to the construction of the known sunshade panel apparatus described in JP2003-48433A, when the sunshade panel is moved to be in the predetermined position, because of the component of the force applying to the tilting start portion, the guide cam provided at the second sunshade panel can smoothly move into the cross guide way portion. However, the component of the force continuously acts upon the tilting start portion even during when two panels are being slid in an adjacently aligned state within one and the same plane. Accordingly, two panels are respectively pressed strongly against the opposite surfaces of the guide way by the slant component of the force. Thus, the resistance when sliding the sunshade panels becomes large, which brings a drawback that the drive force is required to be increased for sliding the sunshade panels.
A need thus exists for a sunshade panel apparatus, which is capable of stably sliding sunshade panels with a small drive force.


A process is disclosed for the monohydrogenolysis of 2,2-dichlorohexafluoropropane to 2-chloro-2-hydrohexafluoropropane. The process involves reacting the 2,2-dichlorohexafluoropropane with hydrogen at an elevated temperature of about 150.degree. C. or less in the presence of a catalyst containing a catalytically effective amount of palladium supported on trivalent chromium oxide in the presence of an acid of the formula HZ (where Z is Cl and/or F) to produce 2-chloro-2-hydrohexafluoropropane with a selectivity of over 70% based upon the 2,2-dichlorohexafluoropropane converted. Azeotropes of 2-chloro-2-hydrohexafluoropropane with HF are also disclosed; as are processes for producing such azeotropes.

Various processes for the catalytic hydrogenolysis of chlorofluorocarbons and hydrochlorofluorocarbons are known. For example, U.S. Pat. No. 2,942,036 discloses the reaction of 1,2,2-trichloropentafluoropropane with hydrogen in the presence of palladium on activated carbon catalyst to produce 1,2,2-trihydropentafluoropropane. The examples show that under the conditions of the experiments one of the products from this reaction is CF.sub.3 CH.dbd.CF.sub.2. Japanese Patent Application Publication Hei 1(1989)-319441 discloses a process where one chlorine atom is selectively replaced by hydrogen in 1,1,1-trichlorotrifluoroethane using a platinum catalyst. For comparison, a palladium on carbon catalyst is disclosed to produce 1,1,1-trifluoroethane as the major product under the conditions of the experiment.
It is well known that the hydrogenolysis of compounds such as chlorofluorocarbons to replace chlorine by hydrogen produces hydrogen chloride as a co-product. Loss of fluorine when it occurs (e.g., to produce overhydrogenated products) can produce HF as a by-product.

Production of 2-chloro-2-hydrohexafluoropropane and azeotropes thereof with HF


To support a changing volume of a voice-grade traffic in an access network having a local exchange with a limited capacity, provide two or more access networks each having subscribers and associated local exchange with a limited capacity; each capable of dividing traffic, outgoing from its subscribers, into the voice-grade traffic portion and data traffic portion, and capable of directing the data traffic portion to a packet network while directing the voice-grade traffic portion to a PSTN network via associated local exchange. Second, detecting the overload condition on one local exchange (LE1). Third, find a remaining one (LE2) of the local exchanges in normal load condition. Fourth, partially diverting the voice-grade traffic intended for the local exchange LE1 and passing the diverted voice-grade traffic to its destination via the packet network and the local exchange LE2.

The main problem that is nowadays intrinsic to the telecommunication networks is a problem of switching capacity overload due to the growing amount of calls transmitted over the networks. Bulky streams of calls and call attempts flowing to and from subscribers of the networks result in degradation of quality of the basic service which is offered by telephone networks, namely—the voice service. Up to a particular moment, regular telephone networks, such as PSTN, equipped with conventional public switches (which can also be called Local Switches, Local Exchanges or Central Offices) coped with more and more increasing use of telephone lines to handle data traffic (for example, on Internet), though very quickly the required bandwidth and the growing volume of the data traffic posed a serious problem and led to the necessity that the traffic load be divided. The main idea of sharing the traffic load was to transmit the high rate data, in the digital form, via separate networks suitable for transmitting data, such as packet networks like ATM, IP, Frame relay and the like.
One of practical solutions for overcoming the above problem is described in a publication WO97/39563, which proposes a method and apparatus for providing bypass networks in a telephone system. The bypass networks permit all forms of traffic on a telephone system, including various forms of data traffic, to be handled without resulting in significant degradation in service to customers while facilitating the controlled growth of the telephone system to handle rapidly increasing classes and levels of traffic. This is accomplished by providing one or more bypass networks in the system, with at least one class of traffic being diverted through such bypass network so as to utilize shared resources of the system. In the WO 97/39563, the idea of bypassing is described and illustrated with respect to the data traffic constituting the source of congestion in the system, while for the voice traffic of a particular local switch subscribers the basic route via the local loop and the local switch is preserved.
There is, however, another problem in the modem combined networks which has not yet been recognized enough and thus has not yet met its solution. Today, the traditional voice traffic, normally handled by its appropriate local loops and local switches, can be "protected" from invasion of new developing classes of traffic by diverting the data traffic to bypass networks. However, while these new developing classes of traffic have led to developing of new networks for transmission, the voice traffic still remains in the frame of the same capacities of local loops and local exchanges, which were calculated and built for some previously existed conditions. Furthermore, the need of temporary increasing/decreasing of the load may cause service degradation in the switched telephone networks.
Historically, a local switch capacity was usually selected with certain traffic load assumptions based on voice traffic characteristics so as to normally avoid overloading of the network. For example, depending on location, there might be four to eight times as many subscribers as there is switch capacity at a central office. Such systems have worked reasonably well with the number of lines and central office capacity being incrementally increased as the number of subscribers increases and only in rare circumstances does such a network become so overloaded that it is not possible to serve new call attempts properly (i.e., during peak traffic periods or anomalous conditions such as on holidays or where there is a catastrophe in the area).
It should also be noted that expenses for increasing capacity of a central office (local switch) are usually very high and operators would prefer not to upgrade them but to support the existing networks infrastructure.

Method and system for effective utilizing the switching capacity of local exchanges


A system with at least one access control device (1) exhibiting an access authorization reader (4) for data carrier (8) containing access authorization and identification data, a database (9) and a camera (7). Once a valid access authorization is read, the identification data from the data carrier in question (8) and a digitized image of the user taken by the camera (7) are stored in the database. The stored image of the user of the particular data carrier can be transferred from the database (9) to terminals (11 to 13), in order to compare it with a image of the user previously taken and stored in the database (9). If the images of the user do not match, further access is denied for that particular data carrier (8).

Systems for access control are used, for example, for cable cars and ski lifts. In addition to single trip tickets, daily, weekly and seasonal passes are issued, especially for winter sports, and often for a complex of cable cars and ski lifts throughout an entire region. Considerable price reductions are granted for the longer-term passes compared to the price for individual trips, but the former are not transferable to other persons.
The unauthorized transfer of longer-term tickets is, however, a widespread practice. It often happens, for example, that a skier who has bought a ticket early in the morning discontinues skiing around midday and then gives the card to a friend, or in some cases even to a stranger in the parking lot. Lift operators incur considerable financial losses as a result of this practice. In order to prevent such unauthorized transfers, an identification photo of the buyer is therefore taken and affixed to the ticket when it is purchased, so that ticket collectors can compare the photo on the ticket with the person who is using it. However, processing the photos and affixing them to the tickets is costly and time-consuming, with the result that this is only practical for higher-value tickets, such as weekly or seasonal passes.
Another well-known system is the technique of storing a digitized image of the ticket purchaser in a database, along with identification data for the particular ticket, and installing a device with a display screen at the point of access. The image of the ticket holder is transmitted from the database and displayed on the screen once the identification data for the ticket has been entered by the ticket collector. This allows the control personnel to compare the user with the image on the screen. However, this method of checking is also time-consuming and is considered a serious inconvenience by legitimate ticket holders, so that this access control method can only be implemented in exceptional cases.
Automatic face recognition via photo processing is scarcely applicable for access control systems, and not at all practical for winter sports because of the caps, headbands, goggles, sunglasses, scarves and the like, which cover the face of the skier.
The purpose of the invention is to provide a simple, effective system for controlling non-transferable data carriers for access authorization without unduly inconveniencing access users.

This patent is subject to a terminal disclaimer.


A dry powder fire extinguisher recharging system charges and discharges a bottle with dry powder. The system includes a frame unit and various components associated with it, such as a clamp assembly to clamp a bottle assembly. The bottle assembly has a bottle in a pre-discharge or a discharge condition, and a valve. There are also components including locking plungers, a torque idler to torque and untorque the valve, a fill valve to recharge the bottle assembly, a fill gauge to pressurize the bottle assembly to the required pressures, a recharge line to charge the bottle assembly with the pressurizing agent, a discharge line to discharge a fully charged bottle, and a socket and an extension. The system also has a valve service area to re-service the valve, and a sprayer gun to remove dry powder residue from the valve during re-servicing of the valve.

Fire extinguishing typically involves either the temporary creation of an atmosphere that is incapable of sustaining combustion within the volume to be protected, or applying a stream of extinguishing agent to the base of the flame. Fire extinguishing is commonly practiced using portable fire extinguishers.
One fire extinguishing method in widespread use at present includes the introduction of volatile halocarbons (Halons), such as Halon 1301 or Halon 1211, for example, into the volume to be protected. Halons are known to interfere with the chemical reactions taking place in the flame and effectively inhibit the flame. Nevertheless, Halons suffer from a fundamental disadvantage; namely, they are known to interact with ozone, which leads to the destruction of the earth's ozone layer.
Ecologically benign fire extinguishing powders (dry powders) based on mineral salts, such as carbonates, bicarbonates, alkali metal chlorides, ammonium phosphates, and the like have been found to provide alternative volume fire extinguishing. These dry powders could successfully act to replace halocarbons or to enhance the performance of halocarbons or other commonly used extinguishing agents, such as CO2 and the like. Dry powders possess a volume and local fire extinguishing effectiveness at least equal to that of halocarbons, yet are ecologically safe and nontoxic.
Fire extinguisher recharging equipment and methods for Halons and dry powders are known in the art. These conventional methods have been developed for controlled environments. However, fire extinguisher recharging equipment that operates in a variety of uncontrolled environments and that can be used for recharging containers with dry powders and Halons is needed for both civil and military purposes. Conventional systems often cannot satisfy sensitive mission capabilities for military purposes, for example. Further, conventional systems for recharging include multiple pieces of equipment representing a logistic impossibility for deployment with a battle group. Many of these pieces of equipment would not be mission capable, at least in that the commercial dry powder hoppers are cumbersome to use and are open to the atmospheric elements, thereby exposing dry powder to moisture.
Thus, there is an urgent need for a fire extinguishing recharging equipment that is mission capable and can encompass all aspects of the recharging process, including the discharging of full containers, and that can be modified for existing Halon units already in the field.

Dry powder service unit and method of use thereof

United States of America as Represented by the Secretary of the Army


Methods of treating an individual who has a disease or disorder associated with one or more genetic mutations or undesirable alleles in genomic DNA of the individual, or preventing an individual from developing a disease or disorder associated with one or more genetic mutations or undesirable alleles in genomic DNA of the individual, by replacing a segment of genomic DNA that has a mutated sequence or undesirable allele with a corresponding segment of DNA that has a non-mutated sequence or desirable allele, are disclosed. Methods of inducing tolerance and preventing transplant rejection in a recipient, methods of inducing tolerance and or reducing allergies are disclosed and method of increasing fertility in a woman are disclosed. Each of the methods comprises replacing a segment of genomic DNA in an individual with a corresponding segment of DNA from another. An apparatus for doing large scale PCR preparations is disclosed. Pharmaceutical compositions that comprise a plurality of polynucleotide molecules which collectively comprise an essentially complete genome in polynucleotide molecules having about 100–3000 nucleotides are disclosed.

Every cell of an organism contains genomic DNA that keeps encoded information about all proteins of all cells of the organism and eventually about the whole organism and its development. Initially this genomic DNA is identical in all cells of an organism. But as the organism grows genomic DNA of every cell becomes subjected to mutational pressure due to environmental factors and mistakes of cellular replication and repair machinery. The known cellular DNA repair mechanisms replace damaged or incorrect DNA bases and rejoin ends of DNA after single-strand and double-strand breaks immediately after mutational events. They can also employ the second DNA chain as a template. When the damage is rather long and affects both DNA chains its repair becomes problematic and the damage results in mutation. The double-strand break repair mechanism can itself be a source of mutations (Pfeifer, P., The mutagenic potential of DNA double-strand break repair. 1998, 96–97, 119–129). As mutations are accumulated in the cellular genome they can cause malfunction of some cells or cancerous transformation.
Environmental mutagenic factors and errors of cellular replication and repair are sources of somatic cell mutations. It has been suggested that gradual accumulation of mutations in cells can cause multi-step cancer transformation. Somatic mutations are considered to be the main cause of aging. Mutations may also induce development of some hereditary associated diseases such as cardio-vascular diseases, high blood pressure, rheumatoid arthritis, and diabetes.
The genetic, multi-mutational nature of cellular cancer transformation and cancer itself suggests that methods of cancer therapy should be directed to the cause of the disease and particularly targeted to the treatment of mutations. Methods for fixing definite point mutations in cells have been suggested (U.S. Pat. No. 5,795,972 issued to Kmiec on Aug. 18, 1998, which is incorporated herein by reference) but according to the method, mutations must be precisely identified before each treatment. Because not a single mutation has been 100% proven to cause a cancer, the development of these methods requires additional fine and time-consuming research. There is a need for methods which can be applied based upon the current knowledge underlying the causes of cancer.
Applying DNA fragments locally has been suggested for treatment of precancerous conditions in skin of patients and for tanning stimulation (U.S. Pat. No. 5,955,059 issued to Gilchrest, et al., on Sep. 21, 1999; and U.S. Pat. No. 5,470,577 issued to Gilchrest, et al., Nov. 28, 1995, both of which are incorporated herein by reference). No sequences or sources of DNA are specified. Rather, the patent suggests that 'any appropriate sources' DNA natural or synthetic, for example, salmon DNA with the length from 200 to mononucleotides and nucleosides including dimers, the most potent agents in their tests can be used.
Another method to activate DNA repair in cells is offered including delivery of enzymes participating in DNA repair into skin cells (U.S. Pat. No. 5,352,458 issued to Yarosh, Oct. 4, 1994; and U.S. Pat. No. 5,302,389 issued to Kripke, et. al., Apr. 12, 1994, both of which are incorporated herein by reference). However the latter methods do not suggest fixing of already established or inherited mutations.
There remains a need for methods of correcting genetic mutations. There remains a need for treating individuals who have diseases and disorders associated with genetic mutations. There remains a need to replace undesirable alleles with desirable alleles. There is a further need for methods for inducing tolerance to prevent transplant rejection. There is a further need for methods for inducing tolerance to treat and prevent allergies. There is a need for methods for increasing fertility.

Compositions comprising genome segments and methods of using the same


A method and apparatus for enhancing images for facsimile machines, printers, etc., is provided. An independent training phase is used to train a system processor to create a probability table based on the surrounding pixel pattern of a given pixel in a training document. The training data generated is used in an enhancement phase where unknown pixels are determined based on the probability table generated during the training phase.

1. Field of Invention
This invention relates to enhancement of facsimile image quality for standard resolution images.
2. Description of Related Art
Facsimile machines generally image and transmit documents at a resolution of either approximately 200 dots per inch (dpi) horizontally and 100 dpi vertically (so-called standard resolution) or at 200.times.200 dpi (fine or detailed resolution). This practice is defined by the Group 3 standards. The detailed resolution offers higher image quality, but the standard resolution is used more frequently.
However, 200.times.100 dpi images are more difficult to read and are more susceptible to distortion than 200.times.200 dpi images. Nonetheless, the 200.times.200 dpi detailed resolution is slower and consumes more memory than the standard 200.times.100 dpi image. Thus, a need exists for producing high quality 200.times.200 dpi images with the speed and lower required memory capacity of a 200.times.100 dpi image.
There are two common methods for producing a 200.times.200 dpi facsimile image from a 200.times.100 dpi image. The first method uses simple scan line duplication that produces coarse results. This method is commonly used by facsimile machines to normalize a received standard resolution fax image. The duplication method simply applies the same value of the pixels in an adjacent scan line to the value of the unknown pixels.
The second method, one example described in McConnell and Bodson, in the book "Digital Facsimile Technology and Applications Handbook", which is incorporated herein by reference, uses fixed interpolation. The interpolation method uses an algorithm that only considers the pixels contained in the immediately touching scan lines in determining the value of an unknown pixel. Thus, the accuracy of determining missing pixels using the interpolation method is limited.
Consequently, the duplication and interpolation methods fail to produce significantly high quality images.

Method and apparatus for image enhancement


A work vehicle includes an engine controller for driving an engine, a power supply line, a power supply control line, and a display signal line. When a check switch switchable into a safe position corresponding to safe drive of the engine and a non-safe position is switched to the safe position, the power supply control line renders a power supply relay ON. The display signal line transmits a signal indicative of the switched state of the check switch to a display.

A work vehicle disclosed in Japanese Unexamined Patent Application Publication No. 2005-273539 includes a speed changer switch for detecting whether a speed changer device is under a neutral state or not, a brake switch for detecting whether a brake is under a braking state or not, an implement switch for detecting whether an implement clutch is under a transmitting state or not, a seat switch for detecting whether a driver's seat is under a seated state or not, and a relay switch for switching conduction states between a state for allowing startup of an engine and a state for inhibiting engine startup. In case the speed changer switch detects the neutral state of the speed changer device, the brake switch detects the braking state of the brake switch, the implement switch detects non-transmitting state of the implement clutch and the seat switch detects the seated state of the driver' seat, startup of the engine is allowed. With this arrangement, it is possible to prevent startup of the engine when an operator is away from the driver's seat. And, it is also possible to avoid occurrence of inconvenience of inadvertent start of the vehicle body or activation of the implement in association with startup of the engine. However, with such engine drive checking system, the driver cannot know the reason when the engine is not started. So, the driver needs to find a reason why the engine is not started.
A work vehicle disclosed in U.S. Pat. No. 8,888,133 (corresponding to Japanese Unexamined Patent Application Publication No. 2005-273539) allows a driver to visually recognize through illumination of LED, states of e.g. battery charge, parking brake, headlamp, PTO clutch, etc. Further, ON/OFF of the parking brake is a condition for engine start. To this end, a detection signal of a parking sensor for detecting ON/OFF position of the parking brake is inputted to an engine ECU to be used for determination of allowing or not allowing engine start. With this arrangement, in case the LED of the parking brake is lit (parking brake ON) although engine start inhibiting message is being displayed, the driver can determine that although the start condition relating to the parking brake is satisfied, some further engine starting condition than the parking brake is not. However, such system as above in which many sensor signals relating to engine start conditions are inputted to the engine ECU and this engine ECU determines whether the engine can be started or not, employs a microcomputer, thus requiring cost for software, as well as cost for a measure to be taken for protection of the microcomputer and its peripheral devices that are vulnerable to exposure to rainwater, dust, etc.

Work vehicle having engine drive checking circuit


A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on the semiconductor substrate; forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode; selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask; and forming the gate insulating layer and the gate electrode using the gate-formation mask.

In order to improve the degree of integration of a semiconductor integrated circuit, a channel length of a MOS transistor would be shortened. If a channel length of a MOS transistor is shortened, a hot-carrier implantation phenomenon would become remarkable, and therefore, a threshold voltage of the MOS transistor would be fluctuated. For suppressing generation of hot carriers, electrical filed around a drain region is decreased. A LDD structure, which includes a region having a lower density of impurities as compared to a drain region, has been used.
According to a LDD structure, a drain has a double-region structure including a first region with a lower density of impurity and a second region with a higher density of impurity, so that a depletion layer of the drain is extended not only to the channel region but also to the first region having a lower density of impurity. As a result, electric field near the drain region is reduced and weakened.
Japanese patent publication No. 2003-100771A describes a high voltage MOS transistor having a gate-overlap LDD (Lightly Doped Drain) structure, in which a gate electrode and a low density diffusion layer are overlapped.
FIGS. 1-1 to 1-9 illustrate fabrications steps of a high voltage MOS transistor according to a conventional technology. First, as shown in FIG. 1-1, element isolation regions 12 are formed in a p-type silicon substrate 10 by a STI process. Next, as shown in FIG. 1-2, a resist pattern 14 is formed on the silicon substrate 10 by a well-known photo-lithographic process.
Next, as shown in FIG. 1-3, phosphorus is implanted as impurities in the silicon substrate 10 using the resist pattern 14 as a mask to form a pair of low-density impurity-implanted regions 16 of n-type. The low-density impurity-implanted regions 16 are formed by an ion implantation process at 1.0×1013 cm−2. Next, as shown in FIG. 1-4, the resist layer 14 is removed. Next, as shown in FIG. 1-5, a gate oxide layer 18 is formed on the silicon substrate 10 to have a thickness of 500 Å by a thermal oxidation process. After that, a poly-silicon layer 20 is formed on the gate oxide layer 18 to have a thickness of 3000 Å by a CVD process.
Next, as shown in FIG. 1-6, a resist pattern 22 is formed on the poly-silicon layer 20 by a well-know photolithographic process. After that, as shown in FIG. 1-7, the poly-silicon layer 20 and the gate oxide layer 18 are etched using the resist pattern 22 as an etching mask to form a gate electrode.
Next, an oxide layer is formed on the silicon substrate 10 to have a thickness of 5000 Å by a CVD process. After that, as shown in FIG. 1-8, the oxide layer is shaped to form a side wall 24 on a side surface of the gate electrode 20 and on a side surface of the gate oxide layer 18 by an etching back process.
Next, arsenic of 1.0×1013 cm−2 is implanted into the silicon substrate 10 by a photolithographic process and an ion implantation process to form high-density impurity-implanted regions 26, as shown in FIG. 1-9. The high-density impurity-implanted regions 26 function as source and drain electrodes. After that, a thermal treatment is carried out so that impurities in the low-density impurity-implanted regions 16 are diffused to form low-density n-type impurity-diffused regions and impurities in the high-density impurity-implanted regions 26 are diffused to form high-density n-type impurity-diffused regions. According to the above described steps, a high voltage MOS transistor having a gate-overlap structure, is fabricated.
However, according to the above-described conventional technology, it is difficult to align a gate electrode and low-density n-type impurity-diffused regions directly to each other. If the gate electrode and the low-density n-type impurity-diffused regions are not located properly, the gate-overlap length between them would be fluctuated. As a result, characteristics of a MOS transistor would be fluctuated as well. A substrate current of a MOS transistor changes in accordance with the gate-overlap length. The more the gate-overlap length is shortened, the more the substrate current of a MOS transistor would be increased. In more detail, when the overlap length between the gate electrode and the low-density n-type impurity-diffused regions becomes lower than 0.5 μm, the substrate current of a MOS transistor would be rapidly increased. And therefore, a hot-carrier resistance of the MOS transistor would be remarkably decreased.
Japanese Patent Publication H05-243262A describes a method for controlling an overlap area between the gate electrode and the low-density n-type impurity-diffused regions by a self-alignment manner. According to a method described in Japanese Patent Publication H05-243262A, an etching mask having an opening is formed on a first gate electrode layer, then a second gate electrode layer is formed over the etching mask. Subsequently, the second gate electrode layer that is located on a side surface of the opening is selectively removed to form side openings. After that, impurities are implanted from the side openings into a semiconductor substrate to form low-density regions. Next, a coating layer is formed in the opening, and the first and second gate electrode layers are etched using the coating layer as a mask. Subsequently, high-density impurity regions are formed.
According to Japanese Patent Publication H05-243262A, the second gate electrode layer is etched before performing an ion implantation to form the low density impurity regions. When etching the second gate electrode layer, the dimension and shape of the side opening are defined by the difference of etching speed between a flat surface region and a side surface region. Therefore, the dimension of the side opening varies due to the thickness of the second gate electrode layer.
When the thickness of the second gate electrode layer varies, the dimension of the side openings varies as well, and therefore, the area or length of overlapped regions of the gate electrode and the low-density impurity-diffused regions varies. In another case, overlapped lengths vary in a single MOS transistor. Namely, according to the conventional technology, it is difficult to control an overlapped area or length of a gate electrode and low density impurity diffused regions precisely.

Method for fabricating high voltage semiconductor device