A method of fabricating cylinder capacitors is provided comprising forming a first conductive layer and a dielectric layer on the semiconductor substrate. A via is formed in the dielectric layer. Then, a second conductive layer and a top oxide layer are formed on the dielectric layer. Part of the top oxide layer and the second conductive layer is removed by pattering the photoresist layer. A first spacer is formed at a side wall of the top oxide layer and the second conductive layer. The second conductive layer is etched by using the top oxide layer and the first spacer as a mask. Then, the top oxide layer is removed to form a second spacer. The second spacer is used as a mask in etching the second conductive layer to form a cup-shaped lower electrode. Further, a dielectric film layer and an upper electrode are formed to make a cylinder capacitor.

1. Field of the Invention
The invention relates in general to a method for manufacturing dynamic random access memory (DRAM). More particularly, the invention relates to the manufacturing of a DRAM capacitor that has a larger electrode surface area for increasing the memory storage capacity of a DRAM.
2. Description of the Related Art
As microprocessors become more powerful and the amount of software data that needs to be processed becomes very large, the amount of memory necessary for storing data becomes great. FIG. 1 is a circuit diagram showing a DRAM memory unit. A DRAM memory unit comprises a pass transistor 10 and a storage capacitor 11. The source terminal of the pass transistor 10 is connected to a bit line 12, the gate terminal is connected to a word line 13, and the drain terminal is connected to the storage electrode, known also as the lower electrode 14, of a storage capacitor 11. The plate electrode 15, also known as an upper electrode or a cell plate, is connected to a fixed voltage source. Between the storage electrode 14 and the plate electrode is a dielectric thin film 16.
When a small charge storage capacity is needed in a DRAM capacitor, a conventional two-dimensional or a planar type of capacitor can be fabricated in the integrated circuit. However, a planar type capacitor occupies a rather large surface area on the semiconductor substrate surface, hence is not suitable for high levels of integration. Therefore, three-dimensional capacitors, for example, the so-called stacked type or trench type capacitors, are used for increasing the level of integration of DRAMs. Nowadays, even the simple three-dimensional capacitor design is insufficient to provide the necessary capacitance. Consequently, methods of producing DRAM capacitors that can increase the surface area of the lower electrode within a given substrate area are still being developed.
FIG. 2 is a cross-sectional view of a conventional stacked type DRAM capacitor structure. First, a semiconductor substrate 20 having a metallic oxide semiconductor (MOS) transistor 22 already formed thereon is provided. The MOS transistor includes a gate terminal 23, source/drain region 24 and spacers 25. On top of the substrate 20, there is a field oxide layer 26 and a conductive layer 27. Next, insulating material is deposited over the substrate to form an insulating layer 28, and then the insulating layer 28 is etched to form contact windows at designated locations above the source/drain regions 24. Thereafter, a lower electrode 29, a dielectric layer 210 and an upper electrode 211 are sequentially formed above the contact windows to form a stacked capacitor structure 212. The dielectric layer 210 can be a silicon nitride/silicon dioxide (NO) composite layer or a silicon dioxide/silicon nitride/silicon dioxide (ONO) composite layer. The lower electrode 29 and the upper electrode 211 can be polysilicon layers. Furthermore, the lower electrode 29 can have an undulating and non-planar profile. Finally, subsequent processing operations such as the formation of a metallic contact and protective insulating layer are performed to complete the DRAM capacitor structure.
FIG. 3A-3F are cross-sectional views showing the progression of manufacturing steps in the fabrication of a cylinder DRAM capacitor according to a conventional method. First, referring to FIG. 3A, a first oxide layer 304 is formed on a MOS device 300, with a source/drain region 301, a field oxide layer 302 and gate electrode 303 provided on the MOS device 300. A thin silicon nitride layer 305 is formed on a surface of the first oxide layer 304 to be an etching stop layer in follow-up steps.
Referring to FIG. 3B, a photolithography step is promoted to pattern the silicon nitride layer 305 and the first oxide layer 304 to form a first contact opening 306 and expose the source/drain region 301 on the MOS device 300. Further, a first polysilicon layer 307 is deposited on the silicon nitride layer 305 and fills the first contact opening 306. The first polysilicon layer 307 is etched back until a surface of the first polysilicon layer 307 is flush with the surface of the silicon nitride layer 305 showed in FIG. 3C.
Referring to FIG. 3D, a second oxide layer 308 is formed, for example, by chemical vapor deposition (CVD) on the structure showed in FIG. 3C. The second oxide layer 308 is patterned by a photolithography step to formed a second opening 309 and to expose the contact opening 306. Then, a second polysilicon layer 310 is formed on the surface of the MOS device to cover the second oxide layer 308 and fill the second opening 309. The second polysilicon layer 310 is coupled with the first polysilicon layer 307. Further, a third oxide layer 311 is formed on the second polysilicon layer 310.
Referring to FIG. 3E, the third oxide layer 311 is etched back to expose the surface of the second polysilicon layer 310. Then, the second polysilicon layer 310 is etched back until the second oxide layer 308 is exposed.
Finally, referring to FIG. 3F, the third oxide layer 311 and the second oxide layer 308 remaining on the MOS device are removed by wet etching, in which the silicon nitride layer 305 is used as an etching stop layer. A dielectric film layer 312 is formed on the top surface of the MOS device, and a third polysilicon layer 313 is formed on the dielectric thin layer 312 to make the DRAM cylinder capacitor structure.
Cylinder capacitors are conventional capacitor structures used currently in DRAMs. The polysilicon layer is etched back to form a spacer used as a hard mask. A dummy oxide layer is dug, and a silicon nitride layer is used for a etching stop layer during the digging step. The cylinder structure increases the surface area of the capacitor to enhance the capacitance, but a disadvantage of the structure is the high stress of the silicon nitride layer. The high stress makes the cylinder structure crack in the back-ending process. Furthermore, many steps are needed to form the cylinder structure and the process is complex.

Method of fabricating cylinder capacitors


A new liquid dispenser for carrying on a head for the purpose of allowing a user to partake of a liquid without the use of their hands. The inventive device includes a hat with an inner layer and outer layer defining a reservoir for holding a liquid. A tubing is coupled to the hat and in fluid communication with the reservoir. The liquid dispenser for carrying on a head is designed to be worn on a person's head allowing the tubing to be inserted into the wearer's mouth for drawing a liquid from the reservoir.

1. Field of the Invention
The present invention relates to liquid dispensers and more particularly pertains to a new liquid dispenser for carrying on a head for allowing a user to partake of a liquid without the use of their hands.
2. Description of the Prior Art
The use of liquid dispensers is known in the prior art. More specifically, liquid dispensers heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art liquid dispensers include U. S. Pat. No. 4,921,141; U.S. Pat. No. 4,369,782; U.S. Pat. No. 340,344; U.S. Pat. No. 5,148,950; U.S. Pat. No. 4,813,083; and U.S. Pat. No. 4,739,905.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new liquid dispenser for carrying on a head. The inventive device includes a hat with an inner layer and outer layer defining a reservoir for holding a liquid. A tubing is coupled to the hat and in fluid communication with the reservoir. The liquid dispenser for carrying on a head is designed to be worn on a person's head allowing the tubing to be inserted into the wearer's mouth for drawing a liquid from the reservoir.
In these respects, the liquid dispenser for carrying on a head according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of allowing a user to partake of a liquid without the use of their hands.


A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.

Typical memory storage devices require complex circuits and high performance materials in order to provide stable and reliable storage of information. Techniques of non-volatile data storage are based on multiple approaches. Some materials such as amorphous silicon exhibit phase change from amorphous to crystalline state when heated to fusing point and cooled slowly. This process is reversible by heating and rapidly cooling the material. The difference between the two states is detected by the change in resistance. The heating rates can be controlled by controlling the current flow through the devices.
In addition, complementary metal-oxide semiconductor (CMOS) flash memories include a buried gate MOS capacitor. During write operation, charge is placed on the capacitor by the application of high electric fields. This charge is read out with simultaneous resetting of the memory. This gate is then capacitively programmed, and the charge is the MOSFET channel is read to obtain the data.
Furthermore, different techniques can be used to fuse a wire. The data storage is binary, depending in whether the wire is open or not.

Charge mapping memory array formed of materials with mutable electrical characteristics

Abstract: A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.


Monostatic homodyne radar system, in particular for continuous wave operation, in which one input port of a balanced mixer (2) is connected to an oscillator (1) and another input port of the mixer is connected to an antenna (3). The mixer has a directional coupler with a 90.degree. phase difference between the coupling arms. The load impedances of the coupling arms have a reflection factor greater than 0.3, so that coupling of the power supplied from the oscillator to the antenna ensues, which coupling is sufficient for the radiation.

With the increasing use of radar systems in the civil sector, e.g. in industrial measurement technology (e.g. level measurement), in traffic electronics (distance warnings, measurement of ground speed) and in the consumer area (motion sensors, door openers), a minimization of technological outlay and thereby of cost is particularly important. A radar system particularly suited for these applications uses a monostatic construction in which one antenna is used both for transmission and for reception. A radar system of this sort is called monostatic, in contrast to systems with separate transmitting and receiving antennas, called bistatic radar. In the standard design of a continuous-wave radar system in conventional radar technology, a radio-frequency signal produced by an oscillator is both radiated via the antenna as a transmission signal and is also used to convert the reception signal to a considerably lower frequency (the difference frequency of the two signals) in a mixer, according to the homodyne principle. For this purpose, a part of the power given off by the oscillator is branched off from the transmission signal using a directional coupler, and is supplied to the input of the mixer.
A system of this sort is schematically illustrated in FIG. 3. The oscillator 1 supplies the radio-frequency signal, from which a part is branched off in the directional coupler 11 and is supplied to the mixer 13. The separation of the transmission and reception signal at the antenna 3 ensues by means of a circulator 12. According to the application of the system, the frequency of the radio-frequency signal remains constant (e.g. in Doppler radar), or the frequency is altered by an external modulation signal (FMCW radar frequency modulated continuous wave!, pulse FM radar). The terminal 4 provided for the feeding of the external modulation signal and the terminal 5 provided for the tapping of the intermediate frequency are also shown in FIG. 3.
The circulator 12 used in this arrangement is a substantial obstacle to a simple and economical manufacturing of the radar system. A construction that does not use this circulator can be most simply realized by using two separate antennas for transmission and reception (bistatic radar). The main disadvantage here is the increase in the outer dimensions, caused essentially by the antennas. In addition, the directional characteristics do not agree precisely, especially at close range, due to the spatial displacement of the antennas. The circulator can also be omitted in a monostatic radar system if for example the arrangement shown in FIG. 4 is chosen. In this arrangement, the directional coupler 14 is also used to conduct the reception signal coming from the antenna to the radio-frequency input of the mixer 13. Corresponding to the coupling attenuation of the directional coupler 14, the power of the reception signal is not conducted completely to the mixer, in contrast to the arrangement with the circulator. The lower receiver sensitivity that thereby results can mainly be tolerated in the applications mentioned above, due to the short range (200 m maximum).
In the arrangements described, it was presupposed that the mixer is provided with separate inputs for the local oscillator signal and for the radio-frequency reception signal. This is the case in constructions with balanced mixers, preferred in microwave technology. In a non-balanced mixer (e.g. a one-diode mixer), the two radio-frequency signals to be mixed are supplied via a common terminal. With the use of such a mixer, a further simplification of the system according to FIG. 4 is possible by replacing the directional coupler with a T branching. The essential disadvantage of this variant is the negative influence on the sensitivity, due to the amplitude noise of the oscillator, said noise being demodulated in the non-balanced mixer. This solution thus appears to be suited only for sensors with ranges of a few meters.


A handheld electronic device includes one or more networking applications that enables the handheld electronic devices to be used as a networking device. The networking application monitors the types of contact that the user has with individuals, the frequency of contact, and type of contact, to infer the closeness of the relationships between the user and the contact. The networking application may monitor not only network based contact, but also physical contact between the two individuals. Knowledge of the closeness level may enable the handheld electronic device to classify contacts, so that different contacts may be handled differently by the handheld electronic device. The closeness level may also be used to alert the user to the presence of people that are close contacts. An anonymizing service may be provided to enable communications between people without requiring them to exchange sensitive personal information until the closeness level reaches a particular threshold.

1. Field of the Invention
The present invention relates to social networking and, more particularly, to a method and apparatus for managing business and social contacts.
2. Description of the Related Art
People interact with each other in person as well as via communications networks. For example, people can interact by telephone, e-mail, instant message, facsimile, and in other ways. More recently, people have been able to interact with each other in virtual environments. A virtual environment is a computer-generated two or three dimensional environment in which participants are able to interact with each other and with other objects in the virtual environment. One context in which a virtual environment may be used is in connection with gaming, although other uses for virtual environments are also being developed.
As the number of ways to communicate increases, managing contact information becomes more important. There are several contact management systems that enable users to collect contact information such as telephone numbers, instant mail contact numbers, e-mail addresses, mailing address, and other contact information. Other contact management systems are available as well. In a conventional contact management system, when a user meets someone in person or on a network, the user may create a contact for the person to allow the user to store contact information in the contact management system. This contact may be automatically generated, or more typically, may be manually created.
Typically, a contact management system of this nature will run on a desktop or laptop computer. Since people generally don't carry around their desktop/laptop computer, portable handheld electronic devices have been developed which can maintain similar contact information. Example portable handheld devices include cellular telephones and personal data assistants, although other types of portable handheld electronic devices may also be used to manage contact information. The portable handheld electronic devices often are able to synchronize with the user's desktop or laptop computer so that contacts entered in the portable handheld device are populated to the desktop/laptop, and vice versa.
Although contact management systems have become fairly sophisticated, it would be advantageous to provide a system that has additional intelligence to enable contacts to be managed in a more natural manner that relies less on manual input and more on system intelligence.

Method and apparatus for managing business and social contacts


A method includes receiving a multi-phase axial cardiac dataset, receiving a selection of a phase from a user, when the received selection is systole, generating an endocardial volume of a left ventricle at an end systole phase without further user intervention, and when the received selection is diastole, generating an endocardial volume of the left ventricle at an end diastole phase without further user intervention.

This invention relates generally to CT, PET, and MR examinations of the heart, and more specifically to methods and apparatus for automating image generation and review.
Accurate evaluation of the cardiac function, particularly left ventricular (LV) function (e.g., stroke volume, ventricular ejection fraction, regional wall motion) is useful in cardiac diagnosis, guiding patient therapy, determining prognosis, and following the course of a disease. LV function is also a useful component of any comprehensive cardiac diagnostic examination for stable coronary artery disease (e.g., stable angina) and acute cardiac syndromes (e.g., acute myocardial infarction and unstable angina). Measurement of ventricular function complements and supplements other cardiac diagnostic procedures such as cardiac catheterization and coronary artery imaging for vessel patency and myocardial perfusion. In patients with a variety of heart diseases, cardiac function has a better diagnostic and prognostic value than vessel patency. For instance, even if a patient has stenosed coronary arteries as in chronic, stable coronary artery disease, close to normal ventricular function at rest and exercise suggests an excellent prognosis. On the other hand, even with good coronaries and normal perfusion, depressed ventricular function indicates a poor prognosis.
There are several known methods to measure cardiac function including echocardiography (Ultrasound), radionuclide imaging (positron emission tomography (PET)), magnetic resonance (MR) imaging, and computed tomographic (CT) imaging. One disadvantage of the echocardiographic methods is that they are highly operator dependent.
Three-dimensional imaging techniques of the heart are now widely used in several modalities (such as CT, MR, and PET). The review of these 3D datasets by a radiologist usually involves the creation of 2D reformatted slices (also called oblique planes) in specific anatomical orientations. These views are defined according to the long axis of the heart, which is defined as the line that joins the apex of the heart to the center of the mitral valve plane. For example, a Short Axis (SA) plane is the orientation orthogonal to the long axis allowing the visualization of cardiac anatomical structure in a meaningful cardiac plane without any foreshortening or elongation distorting structures and allowing comparison with output created from other cardiac imaging modalities. A SA plane is a cross-sectional view of the left ventricle, which is the standard plane for viewing the functional parameters of the heart. This allows the physician to view the motion of the heart through systole to diastole.
A Horizontal Long Axis (HLA) is the plane defined by the long axis and the four chamber cut plane (approximately the Left to the Right cut plane relative to the patient) allowing the visualization of cardiac anatomical structures in a meaningful cardiac plane without any fore-shortening or elongation distorting structures and allowing comparison with output created from other cardiac imaging modalities. This view allows for a four-chamber view of the heart displaying both the atria and ventricles in one view allowing visualization of the tricuspid and mitral valves.
A Vertical Long Axis (VLA) is the plane orthogonal to the HLA and containing the Long axis, allowing the visualization of cardiac anatomical structures in a meaningful cardiac plane without any fore-shortening or elongation distorting structures and allowing comparison with output created from other cardiac imaging modalities. This view allows for a two-chamber view of the heart displaying both the atria and ventricle of the heart.
An Inflow/Outflow view of the Left Ventricle allows additional views contributing to analysis of cardiac morphology.
The orientation of the heart within the chest may vary from patient to patient, therefore the geometric orientations of these anatomical planes have variability and must be determined specifically for each case.
Moreover, to review efficiently a 3D cardiac dataset, there is a need to display simultaneously several anatomical orientations in different view ports for review, with the images being linked by a common 3D cursor. The configurations of the views on the screen can vary, according to the preference of each physician or according to a specific clinical task.
Known techniques involve manual determination of each of these planes on the screen. This is performed by manually orienting each oblique view, based on other views. Creating several views in different orientations can be very time consuming. Therefore, below are described methods and apparatus which address the above problems, in one embodiment, with a unified automated solution.


A clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock is presented. The circuit and method include a clock enable control circuit generating a clock enable control signal controlled by a power supply voltage and a power-down signal. The circuit and method also include a clock generating circuit receiving an input clock which selectively generates an internal clock synchronized to an external clock using the input clock using the clock enable control signal. Whereupon, a locking failure can be prevented by performing a phase update operation selectively in accordance with whether the power supply voltage is varied or not in the power-down mode. Furthermore, current consumption can be reduced by controlling phase update time in accordance with a variable magnitude of the power supply voltage.

The present invention relates generally to a semiconductor device, and more particularly to a clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock.
In general, a synchronous semiconductor device operating in synchronization with a clock from an external system (hereinafter, "the external clock") includes a clock synchronization circuit in order to generate an internal clock of the semiconductor device (hereinafter, "the internal clocks") having the same phase as the external clock. As the clock synchronization circuit, a phase locked loop (PLL) and a delay locked loop (DLL) have been widely used.
The phase locked loop is to synchronize a phase of the internal phase with a phase of the external phase, and the delay locked loop is to synchronize the internal clock with the external clock by reflecting on the internal clock a negative delay corresponding to a delay component in a clock path of the external clock generated within the semiconductor device.
Meanwhile, the semiconductor device enters into a power-down mode when there is no access to memory cells for the purpose of low power, in which it is allowed to reduce current consumption as possible by disabling the clock synchronization circuit. Further, when the semiconductor device exits into an active mode, the clock synchronization circuit is enabled again.
Hereinafter, although the clock synchronization circuit is shown as a delay locked loop for the purpose of easiness of explanation, it should be understood that other clock synchronization circuit including a phase locked loop can be applied.
Referring to FIG. 1, a delay locked loop circuit 1 according to prior art comprises a input buffer 10 buffering and inputting an external clock ECLK, a clock enable unit 12 selectively inputting an input clock ECLK1 output from the input buffer 10 by power-down signal PWDN, a phase updating unit 14 outputting an internal clock ICLK synchronized to the external clock ECLK by updating a phase of a reference clock ECLK2 output from the clock enable unit 12, and an output buffer 16 outputting data synchronized to the internal clock ICLK output from the phase updating unit 14.
Herein, the phase updating unit 14 comprises a phase delay unit 20 inputting the reference clock ECLK2 and delaying a phase of it to output the internal clock ICLK synchronized to the external clock ECLK, a delay model unit 26 modeling the internal clock ICLK with delay elements of the clock signal within the memory to output a feedback clock FBCLK, a phase comparing unit 24 inputting the reference clock ECLK2 and the feedback clock FBCLK and detecting a phase difference between two clocks input to output a phase detect signal DET, and a delay control unit 22 inputting the phase detect signal DET and outputting a control signal CTL which controls the phase delay of the phase delay unit 20.
Referring to FIG. 2, the operations of the conventional delay locked loop circuit 1 will be described. When the semiconductor device enters into the power-down mode, a power-down signal PWDN is enabled thus transitioning from logic low to logic high. Then, the delay locked loop circuit stops a phase update operation to save current states and store the previous locking information, thereby entering into a frozen state.
Herein, the phase update means keeping track of a phase difference between the feedback clock FBCLK and the reference clock ECLK2 in the delay locked loop circuit, and the frozen state means storing the previous locking information but updating the phase.
Meanwhile, the power supply voltage VDD can have voltage sections V1, V2 of which voltage level is randomly varied due to power noise. Such power noise continues to be generated even while the delay locked loop circuit remains in the power-down mode.
Conventionally, since the delay locked loop circuit has other locking information value in accordance with a level of power supply voltage VDD, the locking information value varies considerably if a level of the power supply voltage VDD of when the delay locked loop circuit enters into power-down mode and a level of the power supply voltage VDD of when the delay locked looped circuit exits the power-down mode are different to each other.
However, since prior delay locked loop circuit does not perform a phase update operation in response to changes of the power supply voltage VDD while remaining in the power-down mode, if it exits the power-down mode at power supply voltage level other than a level of power supply voltage VDD of when entering into the power-down mode, e.g., voltage section V1 or V2, a delay of the reference clock ECLK2 is controlled by the locking information un-updated, thereby generating the internal clock ICLK.
As a result, there is a problem that the semiconductor device cannot receive/transmit available data since a phase difference between the external clock ECLK and the internal clock ICLK is caused.

Clock synchronization circuit and clock synchronization method


A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.

An SRAM compiler is a computer program which can synthesize different memory configurations. Variables which determine a specific memory configuration are word width, number of words, and number of memory blocks. An SRAM compiler program creates a netlist of the memory, simulates the worst case delay path through the memory to generate timing information, builds a symbol of the SRAM for placement in a schematic, builds a simulation model with the timing information, creates a physical layout of the SRAM, builds a routing abstraction of the SRAM, and creates a power grid structure for the SRAM. In general, an SRAM compiler is used to generate memories for application specific integrated circuits (ASICs) such as a gate array or a standard cell circuit. A compiled SRAM may be one of many components which make up an integrated circuit.
An SRAM generated by a compiler contrasts greatly with an SRAM designed for the general marketplace as a stand alone part. Typically, general product SRAMs are full custom designs which focus on memory density, speed, power, yield, and package size. All of these constraints must be met within a short design cycle time to introduce a successful SRAM in a highly competitive market.
Creating an SRAM compiler is a task which involves both design and computer resources. Memory sizes and word widths on an ASIC can vary drastically depending on the customer application. Initial efforts attempted to take existing full custom memory designs and build them into memory compilers. Writing the computer code to create a configurable memory from a full custom design proved to be an extremely difficult task. Most abandoned this approach and created new memory designs which simplified writing the code to synthesize various memory configurations and reduce the complexity of building the physical layout of the SRAM.
Two features are typical of most SRAM compiler designs. First, the compiler builds a single block of memory for the application. Second, decoding stages are designed to minimize layout changes which reduces the complexity of the physical layout compiler. For large memory sizes both of these standard compiler attributes reduce SRAM performance. Larger memory array sizes increase loadings on outputs of decoder circuits and memory cells, increasing SRAM access times. Building the decoding circuits to simplify layout changes often compromises performance for high row/column counts.
In general, large amounts of memory are required in complex integrated circuit designs. The memory required typically takes the form of a large single SRAM or multiple smaller SRAMs.
The main limitation in an SRAM generated by a computer (compiled SRAM) is performance. The memory size typically is dictated by the largest SRAM that can be formed that meets the system speed requirements of an integrated circuit. Presently, compilers have been unable to generate SRAMs approaching the speed/density of the full custom SRAM designs.
In the past, techniques for defining subsets of a memory have included compiling a circuit macro by using a set of predetermined circuit blocks. According to such techniques, as illustrated in FIG. 1, in the physical layout of an SRAM, a central block structure may be formed that includes control circuits, word/bit decoder circuits, and a required number of wordline selector circuits. Storage block macros may be formed that include an array of memory cells grown to the required size in the wordline direction, bit selectors, write drivers, sense amplifier circuits, and output latches. The final SRAM may be formed by placing in the bitline direction, the required number of storage block macros, around the central block structure. Multiple bit selector circuits may permit some performance versus area optimization by varying the aspect ratio of the number of wordlines versus the number of bitlines. This technique provides minimal performance optimization, and does not include a technique for optimizing performance over a range of SRAM sizes.
The above-described technique may be enhanced for compiling SRAMs with multiple read and write ports. According to the enhanced technique, a silicon compiler approach may be utilized to generate the various layouts for the required subcircuits. The compiler calculates load capacitance and increases buffer transistor sizes, based on technology information, to maintain a pro-programmed signal rise/fall time. Once all buffer sizes are known, the compiler then generates the transistor layout and wiring.
While the idea of addressing a subset of a memory array may be known, the techniques do not optimizing performance over an entire range of subset sizes. Additionally, known techniques do not disclose how to control critical timing of the SRAM and, thus, the actual technique for determining performance versus the size of the SRAM.
One technique for timing control employs what are commonly called "dummy wordline" and "dummy bitline" control signals. These control signals attempt to mimic the time required to generate enough signal on the bitline so that the sense amplifier operates correctly, as well as to assure the SRAM cycles at a functional rate.
According to this technique, an extra wordline decoder circuit may be selected every cycle to drive a "dummy wordline" net. The "dummy wordline" is constructed of "dummy cells", such that the signal net delay is proportionally equal to the net delay of a selected wordline. The "dummy wordline" net in turn drives the gate of a "dummy device", which discharges a "dummy bitline" net.
The "dummy bitline" is constructed of "dummy cells" similar to the "dummy wordline", such that it is also proportionally equal to the load of a real bitline. This discharging "dummy bitline" net, which is used as a mimic of the signal generation delay, is then used to control the sense amplifier set clock. In a compilable SRAM, such as that illustrated in FIG. 2, the "dummy wordline" and "dummy bitline" nets grow as the SRAM is grown. Thus, in theory, their net delays increase versus the size of the RAM.
In a design where a "dummy wordline" and a "dummy bitline" are 100% physically matched to the "real wordline" and "real bitline" structures, the slope of their delays, as a function of array size, will be parallel, as illustrated in FIG. 3. This approach has the advantage of the sense amplifier set signal delay tracking the bitline signal delay versus size, temperature, process, and voltage. However, a large performance penalty is taken because a dual sense scheme is required to sense both the dummy bitline, which in turn initiates the sense of real data.
An improved approach, is to scale the dummy structures such that they are faster than the real wordline & bitline delays. In this case, as illustrated in FIG. 4, the "dummy" delays are set so that the maximum size RAM has the minimum required signal margin, which eliminates the delay penalty. However, this structure no longer has a delay slope parallel to the real wordline/bitline delays. Thus, a large performance penalty results with smaller RAMs. Also, since the physical structures are no longer matched, the delay tracking versus process, temperature, and supply voltage is greatly degraded.
This design technique has proven to be somewhat effective in compilable SRAMs up to now. It will track process, voltage, and temperature such that signal margin can be guaranteed, while maintaining functionality across the full operational range. However, each variation of this approach results in some overall loss of RAM performance.

Performance optimizing compiler for building a compiled SRAM

International Business Machines Corporation


A radio communications system (10) having a remote or mobile station (30) and at least two base stations (13, 14). ATM radio channels (31, 32) are provided between the remote station and base stations. The remote station (30) has a logic unit (520) for combining cell streams received from the first and second base stations during a handoff from the first base station to the second base station. A receiver in the remote station (30) is powered up during first time periods corresponding to physical layer synchronization cells arriving from one base station (13) and second time periods corresponding to ATM cells arriving from the other base station. When handoff conditions are met, the receiver is powered up for a third time period longer than the first and second time periods.

In the modern telecommunications world, voice communications continue to be a popular mode of communication, but new services like video telephony, high speed data and short message services continue to expand on existing services. The arrival of new telecommunications services generates new requirements for telecommunications networks. New telecommunications techniques (transfer modes) are required and offer possible advantages compared to existing techniques. Traditional transfer modes for wired communications are circuit switching, familiar in classical telephone services, and packet switching, familiar in telegraphy and modern short message service and data systems.
Asynchronous transfer mode (ATM) is a mode of fast packet switching which allows systems to operate at a much higher rate than traditional packet switching systems. Features which characterize ATM communications are: the ability for asynchronous operations between a sender clock and a receiver dock; transmission "cells" of pre-defined sizes; and addressing carried out in a fixed size header (that is not but time, frame position or other fixed characteristic). ATM communication is sometimes also referred to as asynchronous time division (ATD) communications.
Asynchronous transfer mode (ATM) is a mode of fast packet switching which facilitates switching systems that operate at a much higher rate than traditional packet switching systems. Features which characterize ATM communications are: the ability for asynchronous operations between a sender clock and a receiver clock; the concept of a "virtual connection" which is established for the lifetime of an information flow that comprises part or all of the communication; transmission "cells" of a fixed, standardized size; and connection identification carried in a fixed size header (that is not by time, frame position or other fixed characteristic). ATM communication is sometimes also referred to as asynchronous time division (ATD) communications. Other features of ATM communications are notions of a "service category", "traffic contract" and Quality of Service objectives that apply to the virtual connection. The expression "virtual connection" here is used to refer a virtual path and virtual circuit pair and "virtual connection identifier" means either a virtual path identifier (VPI) or a virtual circuit identifier (VCI) or both.
ATM communication has proven useful in high-value point-to-point land-line communication, for example, satellite links and undersea cables. ATM allows multiple simultaneous circuits, sometimes referred to as virtual circuits (VCs), to be established from end to end along the link.
European Patent No. EP0679042 of Roke Manor Research describes a mobile communications network with ATM as the transfer mode used in the switching infrastructure and describes steps to be taken in the mobile network switching infrastructure when a mobile terminal changes affiliation from one base station to another base station, as in a conventional handoff operation and when a mobile terminal communicates simultaneously through more than one base station. The transfer mode of the radio link is not described. International Patent Application No. WO94/28645 of The Trustees of Columbia University in the City of New York also addresses the use of ATM in a mobile communications system switching network and addresses distributed call set-up and rerouting in a mobile ATM based system with ATM switches.
A mobile communications network consists of a number of mobile end systems, a number of base stations, and a number of base station controllers, where the base stations and base station controllers are interconnected using an Asynchronous Transfer Mode (ATM) network. When a mobile end system moves from radio site (or "cell" or "zone") to another, it is necessary to execute a handoff between the corresponding base stations.
The standardized ATM architecture prohibits any ATM network (including a wireless ATM network) from misordering or duplicating ATM user data cells. In general, ATM networks should lose (i.e. by discarding) few, or preferably no, ATM user data cells at any time, including during handoff. Further, the ATM service architecture distinguishes between `real time` and `non-real time` service categories. In real time service categories, cell delay variation (CDV--the variability in the pattern of cell arrival events at the output of an ATM connection relative to the pattern of corresponding events observed at the input of the connection) is an element of quality of service. CDV is negotiated between the end systems (including mobile end systems) and the network(s). If a cell exceeds the agreed CDV, then it either is lost, or becomes useless to the end system when it is delivered; thus, a late cell is treated as if it were lost. Non-real time services are indifferent to CDV, but may be more sensitive to cell discard.
The arrangements described in the above prior art patent application are not optimal in their use of ATM resources in an access network, nor do those arrangements address communication using ATM as the transfer mode over-the-air.
International Patent Application No. WO94/32594 of NTT Mobile Communication Network, Inc. describes a cellular mobile radio communication system soft-handover scheme using code division multiple access (CDMA) where signals transmitted from different base stations are spread with different spread codes and simultaneously received at a mobile station with reception units in correspondence to different base stations. It is described how communication can take place in packets which include a call number, in case the mobile station deals with a plurality of calls, a sequence number and an identification number (ID) for the mobile station. It is explained how the same packet can be received at the mobile station from more than one base station or received at more than one base station from the same mobile station, to provide a reliable diversity handover scheme. The establishment of simultaneous communication through two base stations is described, without the completion of a handover process being described. It must be assumed that the completion of handover complies with pre-existing CDMA soft handover principals. The patent application also mentions that the packet communication scheme can be an ATM scheme.
Attention is turning to the use of ATM for the radio interface transfer mode of wireless communications. There is, for example, a need for wireless users to have access to wired ATM networks and existing ATM systems such as multi-media applications need a wireless platform providing multi-media support. It is also recognized that systems such as universal mobile telephone systems (UMTS) and existing wireless local area networks (LANs) cannot meet all future data user needs. Efforts to date have been in the use of ATM in the wireless extension of fixed infrastructure systems, such as local area networks (LANs) and integrated service data network (ISDN).
For private land mobile networks and cellular radio networks, circuit-switched frequency-division multiple access (FDMA) with or without time division multiple access (TDMA), as well as code division multiple access (CDMA) continue to be the available multiple access schemes for the radio interface. Each of these multiple access schemes has its advantages and disadvantages in different circumstances and the various schemes are generally incompatible with each other.
A mobile radio system is now envisaged using ATM as the transfer mode and using a novel multiple access scheme which has advantages over existing FDMA, TDMA and CDMA multiple access schemes. There is a need for a method of handover in such a novel system.
______________________________________ Glossary of Terms ______________________________________ ATM Asynchronous Transfer Mode BS Base station BSC Base station controller CDV Cell Delay Variation CLP Cell Loss Priority GFC Generic Flow Control HEC Header Error Control PTI Payload Type Identifier VPI Virtual Path Identifier VCI Virtual Circuit Identifier ______________________________________

Power control of a remote station of a radio communications system


A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate electrode and including an opening, a second gate electrode formed on the intergate insulating film and electrically connected to the first gate electrode through the opening, and a boost electrode formed on the intergate insulating film and electrically isolated from the first gate electrode and the second gate electrode.

1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a structure and a manufacturing method of a transistor used in a peripheral circuit for supplying a predetermined voltage to a memory cell transistor.
2. Description of the Background Art
In general, a memory cell transistor in a non-volatile semiconductor memory includes a gate insulating film referred to as a tunnel insulating film, a floating gate electrode functioning as a charge accumulation layer, an intergate insulating film, a control gate electrode, and the like. The non-volatile semiconductor memory charges electrons in the floating gate electrode by applying a high voltage to the control gate electrode and feeding a tunnel current to the tunnel insulating film. In this way, data are written in the memory cell transistor.
Usually, a high write voltage (Vpp) ranging from 15V to 25V is necessary for the tunnel current flowing to the tunnel insulating film. The write voltage is transferred from a transfer gate transistor to the memory cell transistor and then applied to the control gate electrode.
In general, the transfer gate transistor includes a gate insulating film, a first gate electrode, an intergate insulating film having an opening, a second gate electrode, and the like. The first gate electrode is electrically connected to the second gate electrode through the opening in the intergate insulating film. Usually, the transfer gate transistor is formed simultaneously with the memory cell transistor. Accordingly, the gate insulating film, the first gate electrode, the intergate insulating film, and the second gate electrode of the transfer gate transistor are generally formed of identical layers to those of the gate insulating film, the floating gate electrode, the intergate insulating film, and the control gate electrode of the memory cell transistor, respectively.
The transfer gate transistor has to transfer the write voltage Vpp to the source. Accordingly, it is necessary to apply the write voltage Vpp to the drain and to apply a voltage equivalent to a sum of the write voltage Vpp and a threshold voltage Vth of the transfer gate transistor to the second gate electrode. For this reason, the non-volatile semiconductor memory as described above requires a large charge pump circuit for generating such a high voltage as Vpp+Vth.
Japanese Patent Application Publication No. 2007-27666 describes an example of a non-volatile semiconductor storage device. FIG. 3, FIG. 4, and FIG. 5 in JP 2007-27666 disclose examples of cross-sectional structures of a memory cell transistor, a low voltage transistor, and a high voltage transistor, respectively.

Semiconductor device and method of manufacturing the same


A display device includes: a plurality of pixels; a signal controller generating data accumulations for current image data for the pixels based on an accumulation of input image data, calculating modification coefficients according to the data accumulations, and modifying the current input image data based on the modification coefficients to generate modified image data; and a data driver generating data voltages corresponding to the modified image data and supplying the data voltages to the pixels.

(a) Technical Field
The present disclosure relates to a display device and a driving method thereof, and in particular, to an organic light emitting diode display and a driving method thereof.
(b) Discussion of Related Art
Recent trends toward light-weight and thin personal computers and televisions sets also require light weight and thin display devices, and flat panel displays satisfying such a requirement are being substituted for conventional cathode ray tubes (CRT).
The flat panel displays include a liquid crystal display (LCD), field emission display (FED), organic light emitting diode (OLED) display, plasma display panel (PDP), and so on.
Generally, an active matrix flat panel display includes a plurality of pixels arranged in a matrix and displays images by controlling the luminance of the pixels based on given luminance information. An OLED display is a self-emissive display device that displays image by electrically exciting light emitting organic material, and it has low power consumption, wide viewing angle, and fast response time, thereby being advantageous for displaying motion images.
A pixel of an OLED display includes an OLED and a driving thin film transistor (TFT) including polysilicon or amorphous silicon.
An OLED and an amorphous silicon driving transistor become degraded after a long-time driving, and this deteriorates the image quality of the OLED display and reduces the life time thereof.
Accordingly, several pixel circuits for reducing or compensating for the degradation of the OLED or the driving TFT are suggested. However, each of such pixel circuits includes three or more transistors and signal lines so as to decrease the aperture ratio. In addition, the degree of compensation decreases as time goes by.

Display device and driving method thereof


Communication may be provided from a first communication device over a multiple-input-multiple-output (MIMO) wireless channel to a second communication device. More particularly, feedback may be received at the first communication device from the second communication device, with the feedback including a precoding matrix selection from the second communication device. A representation of a speed of the second communication device relative to the first communication device may be generated. Responsive to the representation of the speed of the second communication device indicating a speed that is greater than a selection threshold, a generalized precoding matrix may be selected that is different than a precoding matrix indicated by the precoding matrix selection from the second communication device. Related devices are also discussed.

In a typical cellular radio system, wireless terminals (also referred to as user equipment unit nodes, UEs, and/or mobile stations) communicate via a radio access network (RAN) with one or more core networks. The RAN covers a geographical area which is divided into cell areas, with each cell area being served by a radio base station (also referred to as a RAN node, a "NodeB", and/or enhanced NodeB "eNodeB"). A cell area is a geographical area where radio coverage is provided by the base station equipment at a base station site. The base stations communicate through radio communication channels with UEs within range of the base stations.
Multi-antenna techniques can significantly increase capacity, data rates, and/or reliability of a wireless communication system as discussed, for example, by Telatar in "Capacity Of Multi-Antenna Gaussian Channels" (European Transactions On Telecommunications, Vol. 10, pp. 585-595, November 1999). Performance may be improved if both the transmitter and the receiver are equipped with multiple antennas to provide a multiple-input multiple-output (MIMO) communication channel. Such systems and/or related techniques are commonly referred to as MIMO. The LTE standard is currently evolving with enhanced MIMO support and MIMO antenna deployments. A spatial multiplexing mode is provided for relatively high data rates in more favorable channel conditions, and a transmit diversity mode is provided for relatively high reliability (at lower data rates) in less favorable channel conditions.
In a downlink from a base station transmitting from an antenna array over a MIMO channel to a wireless terminal, for example, spatial multiplexing (or SM) may allow the simultaneous transmission of multiple symbol streams over the same frequency from different antennas of the base station antenna array. Stated in other words, multiple symbol streams may be transmitted from different antennas of the base station antenna array to the wireless terminal over the same downlink time/frequency resource element (TFRE) to provide an increased data rate. In a downlink from the same base station transmitting from the same antenna array to the same wireless terminal, transmit diversity (e.g., using space-time codes) may allow the simultaneous transmission of the same symbol stream over the same frequency from different antennas of the base station antenna array. Stated in other words, the same symbol stream may be transmitted from different antennas of the base station antenna array to the wireless terminal over the same time/frequency resource element (TFRE) to provide increased reliability of reception at the wireless terminal due to transmit diversity gain.
The performance of a wireless communication system can thus be improved using multiple antennas at the base station and/or wireless terminal to provide spatial multiplexing SM in more favorable channel conditions and to provide transmit diversity gain in less favorable channel conditions. Transmit diversity and/or spatial multiplexing may be implemented without knowledge of the wireless channel at the transmitter. In many wireless communication standards such as the 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE), High-Speed Downlink Packet Access (HSDPA), and/or Worldwide Interoperability for Microwave Access (WiMAX), however, knowledge of the wireless channel (referred to as channel state information or CSI) may be provided at the MIMO transmitter via feedback from the receiver as discussed, for example, in the 3rd Generation Partnership Project document entitled "UTRA-UTRAN Long Term Evolution (LTE) And 3GPP System Architecture Evolution (SAE)"
(http.//www.3gpp.org/Highlights/LTE/LTE.htm). Accordingly, the MIMO transmitter can use the channel state information (or CSI) to provide precoding to further improve system performance as discussed, for example, by Scaglione et al. in "Optimal Designs For Space-Time Linear Precoders And Decoders" (IEEE Transactions On Signal Processing, Vol. 50, No. 5, May 2002, pages 1051 to 1064) and by Sampath et al. in "Generalized Linear Precoder And Decoder Design For MIMO Channels Using The Weighted MMSE Criterion" (IEEE Transactions On Communications, Vol. 49, No. 12, December 2001, pages 2198 to 2206). CSI precoding can thus be used by a MIMO transmitter to provide beam forming gain and/or to condition transmissions to existing characteristics of the wireless channel.
Communications standards such as 3GPP, LTE, HSDPA, and/or WiMAX may use frequency division duplex (FDD) such that uplink and downlink communications between two communications devices (e.g., between a wireless terminal and a base station) are provided over different carrier frequencies. In such FDD MIMO systems (referred to as limited feedback systems), channel state information may be provided at a MIMO transmitter as feedback information from the receiving device with which it is communicating. For example, a MIMO transmitter at a base station may transmit over a downlink (using a first carrier frequency) to a wireless terminal, and the wireless terminal may provide channel state information for the downlink as feedback that is transmitted over the uplink (using a second carrier frequency different than the first carrier frequency) to the base station. In such limited feedback systems, CSI feedback may be provided, for example, using codebook based feedback and/or quantized channel feedback as discussed, for example, by Mukkavilli et al. in "Design Of Multiple Antenna Coding Schemes With Channel Feedback" (Proc. Annual Asilomar Conf. On Signal Systems And Components, 2001, pages 1009-1013) and by Love et al. in "Quantized Antenna Weighting Codebook Design For Multiple-Input Multiple-Output Wireless Systems" (Proc. 40th Allerton Conf. Communications, Control, And Computing, Moticello, Ill., 2002). Communications standards such as 3GPP, LTE, HSDPA, and WiMAX may use codebook based CSI feedback for precoding.
With codebook based precoding, a same codebook of precoding matrices is defined at both the transmitting and receiving devices (e.g., at both the base station and wireless terminal). The precoding matrices (also referred to as precoding codewords, precoding codebook entries, precoding vectors, etc.) may be constructed using methods such as Grasmanian, Lyod algorithm, Discrete Fourier transform DFT matrix, etc. At the receiving device (e.g., at the wireless terminal), Signal-to-Interference-and-Noise-Ratios (SINRs) may be calculated for received downlink signals for each of the precoding matrices of the codebook, and a rank and a precoding matrix providing the best performance (e.g., highest spectral efficiency and/or capacity) may be selected for CSI feedback. Because the matrices of the codebook are known at both the transmitting and receiving devices, the receiving device may include a precoding matrix index (PMI, also referred to as a precoding matrix indicator) in the channel state information that is provided to the transmitting device wherein the precoding matrix index uniquely identifies the selected precoding matrix and rank. By providing an index as opposed to the precoding matrix, communication resources may be used more efficiently.
In general, the wireless terminal may decide whether to receive over a downlink in a MIMO diversity mode or in a MIMO multiplexed mode, and the wireless terminal reports this decision using a Rank Indicator (RI). For example, a Rank Indicator of 1 may specify a MIMO diversity mode providing only one symbol stream (also referred to as a transmission layer), a Rank Indicator of 2 may specify a MIMO multiplexed mode simultaneously providing two symbol streams (or transmission layers), a Rank Indicator of 3 may specify a MIMO diversity mode simultaneously providing three symbol streams (or transmission layers), a Rank Indicator of 4 may specify a MIMO multiplexed mode simultaneously providing four symbol streams (or transmission layers), etc. For example, with a four antenna base station transmitter, Rank Indicators from 1 to 4 may be available, and with an eight antenna base station transmitter, Rank Indicators from 1 to 8 may be available. Moreover, the codebook may include multiple precoding matrices for each of the ranks. With a four antenna base station transmitter, up to four different transmission layers defined by four respective Rank Indicators (e.g., Rank Indicators 1 to 4) may be available, and 16 precoding matrices may be provided for each transmission layer or rank for a codebook of 64 precoding matrices. With an eight antenna base station transmitter, up to eight different transmission layers defined by eight respective Rank Indicators (e.g., Rank Indicators 1 to 8) may be available, and 16 precoding matrices may be provided for each transmission layer or rank for a codebook of 128 precoding matrices.
Cellular operators have begun offering mobile broadband based on WCDMA/HSPA, and fuelled by new devices designed for data applications, end user performance requirements are steadily increasing. The increased use of mobile broadband has resulted in increased traffic volumes being handled by the HSPA networks. Techniques that allow cellular operators to more efficiently manage their spectrum resources may have increasing importance.
One technique to improve downlink performance may be to introduce support for 4-branch MIMO using four transmitter and four receiver antennas. Given a fixed level of transmission power, the supported peak data rate may be doubled so that 84 Mbps can be supported on a single downlink 5 MHz carrier, and/or coverage for rank-1 and rank-2 transmissions may be improved due to the higher order of beamforming gain.
Introduction of 4-branch MIMO may require new pilot symbols to be transmitted. One approach may be to extend the pilots of 2-branch MIMO (e.g., Primary Common Pilot Channel or P-CPICH, and Secondary Common Pilot Channel or S-CPICH) to 3rd and 4th antennas (e.g., providing tertiary and quaternary pilots). Unfortunately, these additional pilot symbols may act as interference for legacy UEs and other sector UEs, reducing their throughputs. Another option is to use common pilots for channel sounding and dedicated (precoded) pilots for data demodulation. Dedicated pilots may not cause any interference to legacy UEs and the other sector users. These technologies are discussed in 3GPP standards documents such as: R1-111763, Ericsson, "4-branch MIMO for HSDPA," 3GPP TSG RAN WG1 Meeting #65, Barcelona Spain, 9th-13th May 2011; and R1-113431, Ericsson, ST-Ericsson, "Initial discussion on pilot design for 4-branch MIMO", 3GPP TSG RAN WG1 Meeting #66b, Zhuhai, China, 10th-14th Oct. 2011.
When dedicated (precoded) pilots are used for data demodulation, the NodeB may choose the precoding matrix. One option is to use the precoding matrix chosen by UE (and communicated through the feedback channel). For UEs with slowly changing channels, this precoding matrix may provide suitable performance, but for UEs with more rapidly changing channels, the precoding matrix chosen by the UE may be outdated before a next data block transmission over the downlink. FIG. 6 shows packet success probabilities with 3 different Link adaptation schemes. The first scheme uses an Minimum Mean Square Error (MMSE) receiver, the second scheme uses a Serial Cancellation (SC) receiver, and the third scheme uses link adaptation with MMSE and detection with serial cancellation. For slow speed UEs (at 3 km/hour), the packet success probability is more than 80% for all the cases. For medium to high speed UEs (at 30 km/hour and 120 km/hour), however, the packet success probability is less than 50%. If common pilots are used for channel sounding and data demodulation, the performance may thus be reduced compared to open loop MIMO.

Method and device for selecting precoding matrices based on representations of speed of related devices


A method for controlling a diesel engine is disclosed in which the diesel engine is controlled to produce less soot when the operating state of an associated emission control device such as a diesel particulate filter or the amount of a contaminant such as fuel or soot in the oil used to lubricate the diesel engine exceed predetermined respective thresholds.

It is well known that, if a sudden demand for increased torque is received by a diesel engine, a large amount of soot will be produced by the engine due to mis-fuelling of the engine. That is to say, to meet the requested torque demand a specific amount of fuel is required but the amount of ingested air is initially lower than that required to efficiently combust this volume of fuel due to the low initial speed of the engine. The result of this mis-fuelling is the production of soot from the engine due to the inefficient and incomplete combustion that takes place.
This mis-fuelling is disadvantageous in several respects. Firstly, fuel is wasted and therefore the fuel economy of the engine is reduced, secondly, unnecessary emissions are produced including the above referred to soot, thirdly, over fuelling produces un-burnt fuel in the engine which is absorbed into the lubricating oil, and fourthly, the soot produced rapidly fills any particulate filter provided to remove the soot from the exhaust gasses of the engine.
One approach to this problem includes restricting the amount of soot that is produced during such a transient event by modifying the target torque to be provided by the engine. However, a relatively high level of soot is still produced because an overall objective is to minimize the loss of potential torque output obtainable from the engine. A large amount of fuel or soot in the oil will reduce the lubricating properties of the oil. Furthermore, if the amount of fuel in the oil becomes very high, this high level of fuel in the oil can lead to engine runaway if the highly combustible fuel/oil mix is ingested back into the engine via an engine breather system.
The soot loading of a diesel particulate filter (DPF) affects the efficient operation of a diesel engine because as the DPF fills with soot the back pressure on the engine increases and so the torque output attainable from the engine will tend to drop. Therefore, a DPF may be regularly regenerated by burning off the soot stored in it. To do this, fuel is injected into the engine late in the combustion cycle so that un-burnt fuel travels towards the DPF where it auto-ignites in an upstream catalyst before entering the DPF and the exhaust gases at an increased temperature enter the DPF and burn off the soot. However, this process has two main disadvantages. Firstly, fuel is wasted regenerating the DPF, and secondly, the late injection of the fuel often result in un-burnt fuel impinging against the cylinder wall of the engine where it is readily absorbed into the oil thereby increasing the amount of fuel in the oil.
The inventors have recognized the issues with the above approaches and offer a method to at least partly address them. In one embodiment, there is provided a method for controlling an engine system having a diesel engine, at least one emission control device and oil to lubricate the engine, the method comprising adaptively varying an operation of the engine to reduce the production of soot by the engine based upon at least one of the current state of the emission control device and the current state of the oil of the engine.
In this way, the soot production of a diesel engine is adaptively reduced so as to increase the time periods between DPF regeneration events, thereby reducing the amount of fuel used during the life of the diesel engine for these events. The present disclosure may offer several advantages. For example, decreased fuel consumption in DPF regeneration may result in enhanced fuel economy and decreased soot production may result in decreased emissions.
The above advantages and other advantages, and features of the present description will be readily apparent from the following Detailed Description when taken alone or in connection with the accompanying drawings.
It should be understood that the summary above is provided to introduce in simplified form a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is defined uniquely by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.

Method for controlling a diesel engine system


An adsorbent for selective removal of nitrile from a hydrocarbon feedstock includes a substantially homogeneous mixture of a cationic nonacidic zeolite and an inorganic oxide matrix, the zeolite having an accessibility index of between about 0.1 to about 0.4, and the adsorbent being capable, when contacted with a hydrocarbon feedstock containing nitrile and containing dienes in an amount of at least about 1.0% by volume, of adsorbing at least about 80% of the nitrile during contact with at least about 200 volumes of the feedstock per volume of adsorbent.

The invention relates to an adsorbent for selectively removing nitrile from a hydrocarbon feedstock, to a method for making the adsorbent, and to a process for removing nitrile from a hydrocarbon feedstock using the adsorbent.
Nitrile compounds are frequently undesirable contaminants in feedstocks which otherwise contain valuable fractions. Particularly, C4 and C5 cuts from FCC units can be useful in the preparation of oxygenates such as MTBE, ETBE, TAME and the like. However, these feedstocks typically contain nitrites and diolefins. The diolefins may typically be hydrogenated before and/or at the etherification reactor. Nitriles, however, must be removed upstream of the reactor and therefore must be removed in the presence of dienes which make the feedstock higly reactive.
Upstream nitrile removal techniques include washing, but propionitrile cannot be removed through washing. In the presence of hydrogenation catalysts, however, propionitrile is believed to undergo conversion to totally or partially hydrogenate products, which behave as basic nitrogen and rapidly poison the acid sites of the catalyst. It is apparent that the need remains for a treatment for removal of nitrile compounds, especially propionitrile, wherein the agent used for removal is selective to nitrile and has longevity toward the selective removal of nitrile especially in the presence of relatively large amounts of dienes.
It is therefore the primary object of the present invention to provide a nitrile selective adsorbent which is not rapidly deactivated during use, even in the presence of dienes.
It is a further object of the present invention to provide a method for preparing an adsorbent according to the present invention.
It is a still further object of the present invention to provide a process for treating a feedstock such as an FCC etherification feedstock with a nitrile selective adsorbent according to the invention so as to effectively and selectively remove nitrile compounds.
Other objects and advantages will appear herein below.

Process for the removal of nitrile using a selective adsorbent


The present invention is a medical training simulation apparatus for training of medical professionals in medical examinations involving body parts with concealed geometry. The apparatus may comprise a physical model of a body part having an opening and structure that simulates the concealed geometry of a body part and may receive an inserted medical tool. A video display may be disposed within the structure of the apparatus to display at least one image of a physical defect or medical condition for the body part. The at least one image may e be alterable such that its appearance simulates the appearance of the defect or medical condition within the concealed geometry when viewed using the medical tool in relation to an applicable human or animal subject patient. The training apparatus is operable for one or more simulations for training a trainee in a medical examination or procedure for a body part in accordance with a training method.

Numerous medical examinations or procedures involve body parts with concealed anatomy, such as the ear, nose, throat or eye. These medical examinations or procedures generally involve the use of a specialized medical tool, for example, such as in an otoscope used to conduct an ear examination.
At most medical schools, training in medical examinations or procedures relating to body parts with concealed anatomy involves visual identification of possible defects or medical conditions. The training is generally conducted through the use of basic tools, such as slide presentations including photos of the physical defects or medical conditions. Some estimate that only around five percent of medical students feel comfortable about their skills to use specialized medical tools, for example, such as with their otology skills, at the end of their residency.
Prior art medical training systems are known. For example, the "NASCOLIFEFORM", and United States Publication No. 2008/0050710 both include a model of a head or portion of a head, which contains an area that can receive one of a plurality of inserts that simulate an ear and also the ear canal. Such inserts are formed so that the inside of the model of the ear canal shows a physical defect or medical condition. The inserts are generally made of a flexible material such that trainees may pull on the ear portion thus also displacing the ear canal as is required in otoscopy examinations.
As another example, U.S. Pat. No. 6,241,526, issued to Auran et al., discloses a device for training physicians in tympanocentesis. The device includes an outer member resembling a side profile of a child's head and shoulder area. The outer member is attached to a surface portion to define a receiving area for receiving a slidable inner member or insert. A replica of at least an eardrum and an ear canal of a child's inner ear are associated with the sliding inner member. A training portion of the inner member supports a simulated inner ear, positions the simulated inner ear to a desired position adjacent the outer ear of the outer member, and acts as a holder for the training cartridges used with the training device. The cartridges or inserts simulate the "look and feel" of popping through the tympanic membrane. The cartridges include one or more training areas. The disclosed prior art invention trains the user in proper location and depth. Once all of the training areas of the cartridge have been used, it is replaced with a new cartridge.
There are several drawbacks to the prior art training systems. For example, the trainer cannot see the image of the physical defect or medical condition at the same time as it is shown to the trainee. Another drawback is that manual changing of the ear inserts is required for the prior art system. Yet another drawback is that, because of cost, the number of inserts is often limited in the prior art system. The limited number of inserts can reduce the number of images of physical defects or medical conditions to which the trainees are exposed through use of the training system.

System, method and computer program for training for medical examinations involving body parts with concealed anatomy


A precharge circuit of a semiconductor memory device may include a precharge controller, a first precharge unit and a second precharge unit. The precharge controller may enable a first control signal in a precharge mode for a first operation, and may enable a second control signal in a precharge mode for a second operation. The first precharge unit may precharge a pair of I/O lines to a first voltage in response to the first control signal in the precharge mode for the first operation. The second precharge unit may precharge the pair of I/O lines to a second voltage lower than the first voltage in response to the second control signal in the precharge mode for the second operation.

1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices, for example, a semiconductor memory device including an input/output (I/O) line precharge circuit and method of precharging an I/O line.
2. Description of the Conventional Art
A conventional I/O line must be precharged in order to write and/or read data to/from a memory cell array of a conventional semiconductor memory device. As semiconductor memory devices become more integrated, the number of the I/O lines may be increased. When the number of the I/O lines is increased, power consumption and/or electrical noise may increase.
FIG. 1 is a circuit diagram illustrating a conventional semiconductor memory device including an I/O line driver 10 and a precharge circuit 20. Referring to FIG. 1, the I/O line driver 10 includes drivers DRV1 and DRV2 for driving I/O lines IO<0>and IOB<0>. The drivers DRV1 and DRV2 may include a pull-up transistor and a pull-down transistor, respectively. Each of the pull-up and pull-down transistors may be implemented using NMOS transistors. The precharge circuit 20 may include PMOS transistors M5, M6 and M7, and may be coupled to the I/O lines IO<0> and IOB<0>. When the precharge circuit 20 is activated, the I/O lines IO<0> and IOB<0> may precharge to a higher voltage VDD.
The conventional semiconductor memory device implemented using a semiconductor integrated circuit (IC) may include a plurality of pairs of I/O lines, a plurality of the I/O line drivers 10 and a plurality of the precharge circuits 20. To write data to the semiconductor memory device, an active command signal and a write command signal may be activated. After the write command signal is activated, an I/O line precharge signal PIOPRB_A may be deactivated and a write pulse signal PDT_A may be activated.
Before the write command signal is activated, the PMOS transistors M5, M6 and M7 of the precharge circuit 20 may turn on, and the I/O lines IO<0> and IOB<0> precharge to the voltage VDD. Because the write pulse signal PDT_A is at a logic 'low' level (e.g., a logic '0'), the NMOS transistors M1 and M2 of the driver DRV1 and the NMOS transistors M3 and M4 of the driver DRV2 turn off. As the write command signal is activated, the PMOS transistors M5, M6 and M7 of the precharge circuit 20 may turn off and the NMOS transistors M1 and M2 of the driver DRV1 and the NMOS transistors M3 and M4 of the driver DRV2 may selectively turn off based on input data DIO<0>. For example, when the input data DIO<0> has a 'high' logic level (e.g., a logic '1'), the NMOS transistors M1 and M4 may turn off, and the NMOS transistor M2 and M3 may turn on. After all of the input data are written to a selected memory bank, the write command signal may deactivate and the I/O line precharge signal PIOPRB_A may be activated. As a result, the I/O lines IO<0> and IOB<0> may precharge to the voltage VDD. During the write operation, a data mask signal PDMB may activate and transition to a logic 'low' level. When the data mask signal PDMB activates, the I/O lines corresponding to each of the memory banks precharge to the voltage VDD, and all of the NMOS transistors M1, M2, M3 and M4 turn off.
Because the precharge circuit 20 of the semiconductor memory device shown in FIG. 1 comprises PMOS transistors M5, M6 and M7, the I/O lines I/O<0> and IOB<0> precharge to the voltage VDD. When the I/O lines I/O<0> and IOB<0> precharge to the voltage VDD, a data write operation may cause unnecessary power consumption and/or an unnecessarily long period required to perform data transition.
Alternatively, the conventional precharge circuit 20 of the semiconductor memory device may comprise NMOS transistors. When the precharge circuit 20 is implemented using the NMOS transistors, the I/O lines IO<0> and IOB<0> precharge to (VDD-Vth) due to a threshold voltage Vth of the NMOS transistor. When the I/O lines I/O<0> and IOB<0> precharge to the lower voltage (VDD-Vth), a voltage level of the I/O lines may swing between (VDD-Vth) and ground or between ground and (VDD-Vth). In this example, the power consumption of the semiconductor memory device may be reduced and/or an operating speed of the semiconductor memory device may improve. However, when the I/O lines I/O<0> and IOB<0> precharge to (VDD-Vth), an I/O sense amplifier may not operate with sufficient stability during the read operation. In addition, or alternatively, the precharge operation of the I/O lines I/O<0> and IOB<0> may not be performed with sufficient stability because of the lower precharge level.

Semiconductor memory devices including precharge circuit and methods for precharging


In a rigid magnetic recording disk, the magnetic properties, such as the coercivity, of a cobalt based, hard, magnetic alloy, such as a cobalt-platinum-chromium (CoPtCr) thin film magnetic recording layer, are controlled by providing a thin, sputtered, underlayer of a nonmagnetic, binary, chromium-tungsten (CrW) alloy whose major constituent is chromium, and preferably of a composition Cr.sub.88 W.sub.12 upon which the thin film magnetic recording layer is subsequently sputter deposited.

This patent application describes a cobalt alloy thin film magnetic disk having a sputter deposited, single element, chromium underlayer, of a thickness 50 to 200 Angstroms (A), which presents the (100) (one,zero,zero) plane of the chromium atoms at a layer's surface. The cobalt alloy is sputter deposited on this chromium underlayer, such that the (110) plane of the cobalt alloy, and thus the C axis of the cobalt alloy, are parallel to the disk's recording surface, thus facilitating operation of the disk in longitudinal, binary data, recording systems.
The magnetic properties of a thin film magnetic recording layer, for example the coercivity thereof, must be tightly controlled in order for the magnetic recording disk to meet the design specifications of a particular DASD device, which DASD device is in turn used to store digital data in conventional data processing installations.
A goal in the fabrication or manufacture of thin film magnetic recording media is to obtain magnetic properties that are compatible with, and indeed are required by, the read/write transducing head of the DASD unit in which the media will be used.
A number of means have been practiced in the art to control the magnetic properties of thin film magnetic media. Examples are, the use of different materials directly under the thin film magnetic layer, variation in the thickness of the magnetic layer, and the use of different magnetic alloys in the magnetic layer. However, the art has generally not succeeded in controlling the bulk magnetic properties of the thin film magnetic layer for a given set of material and thickness requirements for the magnetic layer.
U.S. Pat. No. 4,749,459, incorporated herein by reference, describes a number of ways by which the coercivity of a thin film magnetic recording layer may be controlled, including forming the magnetic film on a chromium underlayer and controlling the magnetic film's coercivity by controlling the thickness of the underlayer, controlling the amount of platinum in the magnetic film, and sputtering the magnetic film in an atmosphere that includes argon and a trace amount of a selected gas such as nitrogen, ammonia, or oxygen and nitrogen.
U.S. Pat. No. 4,654,276, incorporated herein by reference, is directed to improving the coercivity of a magnetic layer by the use of a nonmagnetic underlayer of tungsten (W) between a substrate and a cobalt-platinum (CoPt) or a cobalt-platinum-chromium (CoPtCr) magnetic layer. This patent also point out that the coercivity of a CoPt magnetic film can be improved by the use of a Cr underlayer, that W has been used as an enhancement layer in certain types of thin film disks, that a layer of an intermetallic compound such as cobalt-tungsten (Co.sub.3 W) has been used to form a nucleating layer for a subsequently deposited magnetic film, and that a CoPt magnetic layer has been formed on a nonmagnetic layer of a tungsten-cobalt (WCo) alloy.
U.S. Pat. No. 4,079,169, incorporated herein by reference, describes a magnetic recording disk, and recognizes that a clad layer is normally deposited on the substrate member, before a magnetic layer is deposited thereon. This clad layer provides wear resistance and mechanical rigidity, provides an easily polishable layer, protects the underlying aluminum from corrosion, and that this clad layer, as well as any other underlayers, should enhance the coercivity and other magnetic properties of the overlying magnetic thin film layer. The specific cobalt based alloy clad layer that is described comprises 10-30% chromium, from 8-18% tungsten, from 8-30% nickel, the remainder being cobalt. The function of the cobalt and the chromium in this clad layer is to provide corrosion resistance. The function of the tungsten in this clad layer is to provide hardness and rigidity. The function of the nickel in this clad layer is to provide ductility.
The above mentioned related patent application describes a cobalt alloy thin film magnetic disk having a sputter deposited, single element chromium underlayer.
While the various means practiced in the art for controlling the magnetic properties of thin film magnetic recording media have been generally useful, there remains a need in the art for an underlayer of simple construction whereby these magnetic properties can be controlled independent of controlling the magnetic properties of the magnetic layer itself, and independent of factors such as layer thickness.
The present invention provides such an underlayer in the form of a thin, sputtered, underlayer of a nonmagnetic, binary, chromium-tungsten (CrW) alloy whose major constituent is chromium, and preferably of a Cr88%,W12% composition, upon which the thin film magnetic recording layer is subsequently deposited.

Magnetic recording medium having a cobalt-plantinum-chromium alloy magnetic layer and a chromium-tungsten underlayer a specified underlayer thickness range


A novel two-dimensional optical signal processing circuit which becomes possible only by the introduction of a concave, flat or convex reflecting structure; and a method of producing the same. Disposed on an optical wave-guiding circuit board (50) formed with an output wave-guiding path (13) and an input wave-guiding path (14) are the optical axes of the input coupling end (I) and output coupling end (U) of a coupling circuit (15) such that the optical axes pass through the same point (Q) on a reflection structure (16), the reflection structure (16) being fabricated by using a laser ablation device (30).

1. Field of the Invention
The present invention relates to an optical signal processing circuit and a method for producing the same. In particular, it relates to an optical signal processing circuit and a method for producing the same, which are effective in applications for an optical multiplexer for optical communications and an optical signal processing apparatus that controls a super high-speed optical signal waveform.
2. Description of the Related Art
There is an optical signal processing circuit disclosed in Japanese publication of unexamined patent application No. (hereinafter referred to as JP-A-) 2000-098150 as one of the prior arts pertaining to optical signal processing circuits having a concave, flat or convex reflecting structure formed therein.
In the prior art, it has been proposed that optical coupling between an arrayed waveguide and an input/output waveguide is coupled by means of a reflecting structure.
However, the prior art does not provide any detailed method for producing the reflecting structure, and problems remain in the reflecting structure and in arrangement of the input/output waveguides.
FIG. 42 shows a configuration of a prior art slab waveguide lens function circuit.
The slab waveguide type lens function circuit 200 is structured so that arrayed waveguides 201a and 201b consisting of a single waveguide or a number of waveguides are connected to each other via a slab waveguide 202. Ends 201ae and 201be of respective waveguides are disposed on arcs centering around both ends P and Q of optical axes PQ of the slab waveguide 202. The configuration becomes approximately equivalent to a case where the ends 201ae and 201be of the waveguides are placed at positions of the front focusing plane and the rear focusing plane in a lens because both ends P and Q of the slab waveguide 202 are, respectively, made into the relationship of spatial Fourier transformation.
However, in the configuration, it is impossible that an image-formation of each other is established between two waveguides 201 and 201b as in an optical system using lenses and mirrors, and since it is necessary that the ends 201ae and 201be of the waveguides are disposed on arcs, the degree of freedom in creating circuits is low.
Further, no publicly known technique is provided in regard to a general configurational method of an optical signal processing circuit in which a reflecting structure of a concave, flat or convex plane or a periodic grooved structure is formed in an optical waveguide circuit to constitute a reflective optical system.
There is a one-dimensional optical waveguide as a technique that can be regarded as its particular case, wherein a reflecting structure of a distributed feedback type semiconductor laser and a distributed reflective type semiconductor laser, and an optical fiber diffraction grating are already known.
In actuality, however, these publicly known techniques are arts pertaining to a reflecting structure and diffractive structure, which are constituted in a single optical waveguide, and are not necessarily sufficient for circuit design of a two-dimensional planar waveguide having a concave, flat or convex reflecting structure or a periodic grooved structure.
Also, in an ion etching method (reactive ion etching method) that has generally and conventionally been utilized as a production technique for the above-described structure, since it is not possible to form smooth grooves perpendicularly and sufficiently deep, the method is not suitable for production of the above-described optical signal processing circuit.
The convergence ion beam etching method as has been disclosed in JP-A-H7-7229 can be considered as another groove formation art.
However, although the perpendicularity and smoothness of the grooved structure formed by this method are comparatively satisfactory, the convergence ion beam etching method has a slow etching speed, wherein it takes two or three hours to form a grooved structure of several tens of microns. In addition, the ion beam diameter is usually 5 through 10 microns in the convergence ion beam etching method, wherein further minute processing is difficult to perform. Therefore, concurrent use of a specified mask is taken into consideration. However, since the etching selectivity is slight between substances with respect to the ion beam, it is necessary to provide a thick resist film in view of forming deep grooves, and resultantly it is difficult to process minute patterns of 3 microns or less.
FIG. 43 shows a configuration of an optical nonlinear element having a pseudo phase matching section by a prior art periodic polarization inverting structure 502. In the prior art element, efficiencies of wavelength conversion and secondary higher harmonics generation, etc., are low if applied for practical uses, and the prior art element is driven only by a laser light having high intensity. Since the efficiencies are proportional to the square of an element length, a large-sized substrate may be used. However, it is extremely difficult to produce a large-sized substrate, and production cost thereof is expensive. Also, the application area of a large-sized element is narrowed in view of practical applications.
In the prior art laser processing, there is a limit in minute processing of a high wavelength, and the prior art laser processing is not suitable for a sub-micron process. This is a physical limit resulting from a diffraction limit of light. Utilization of a mask by electron beam tracing is taken into consideration. However, since light exponentially attenuates if the light transmits a window whose dimension is less than the wavelength, deep processing becomes impossible.
Conventionally, no configuration method of TE/TM mode coupler/splitter circuit that can be integrated in a waveguide has publicly been known.
In the prior arts, a specified pattern is formed by an electron beam exposure and tracing method, a structure is produced by dry etching, etc., and a diffraction grating is produced in a waveguide. (For example, DFB laser utilizing a chemical compound semiconductor). However, an expensive and large-sized apparatus is indispensable for highly accurate etching.
Conventionally, ion implantation type and combination of substrates aiming at reflectivity control utilizing an ion implantation technique are not taken into consideration, and no report exists of an optical signal processing element utilizing the same. The ion implantation is used mainly to control the electric transmissivity of a semiconductor, and only a research report exists of a current narrowing structure by H+ ion implantation in production of optical elements.
Conventionally, it takes a long time for patterning of minute processing. For example, it takes approximately 10 hours to trace at an accuracy of 0.01 microns in an area of 1 cm square with an electron beam tracing device. For this reason, an element provided by the electron beam exposure/tracing method generally becomes expensive and special.

Optical signal processing circuit and method of producing same


Embodiments described herein provide enhanced testing of devices. For example, in an embodiment, an interposer for testing devices is provided. The interposer includes a substrate, a first plurality of connection elements located on a surface of the substrate, and a memory device electrically coupled to the first plurality of connection elements through the substrate. The first plurality of connection elements are configured to mate with a second plurality of connection elements located on a device under test. The memory device is configured to store information received from the device under test and to output stored information to the device under test.

1. Field
Embodiments described herein generally relate to systems and methods for testing electrical devices.
2. Background
Package-on-package (POP) devices include two or more packaged devices (e.g., integrated circuit (IC) devices) stacked on top of one another. In one example, a POP device can include a memory stacked on top of a memory controller. In such an example, the memory controller controls access to the memory device stacked on top of it. For example, the POP device including the memory and memory controller can be mounted on to a printed circuit board (PCB), which can electrically couple the POP device to other devices mounted on it. In such an example, the memory controller can regulate how other components store and retrieve information from the memory.
In a POP device, at least one of the stacked devices typically includes connection elements on at least two surfaces. For example, for a memory stacked on a memory controller, the memory controller can include connection elements on its top surface (to communicate with the memory) and on its bottom surface (to communication with a PCB). Thus, when the memory controller is tested, communications with both the top and bottom sets of connections elements must be tested.
One approach for testing a memory controller having connection elements on both its top and bottom surfaces is to use an actuator to physically acquire the memory controller. The actuator physically places the memory controller into a socket of a device interface board (DIB). The socket establishes electrical connections with the memory controller's bottom surface connection elements. The top surface connection elements can be routed to the DIB through the actuator. To test the interaction of the memory controller with a memory, the DIB can emulate the operation of a memory.
The emulation approach to testing the memory controller suffers from a number of drawbacks. First, the emulation provided by the DIB is relatively slow compared to memories with which the memory controller will be used. Thus, emulation often does not accurately mimic real world operation and it requires more testing time than if testing was conducted using an actual memory. Also, the emulation approach requires relative long signal paths from the top surface connection elements to the DIB, Because of signal integrity issues associated with those long paths, the emulation approach often only uses DC testing schemes.
The disclosed subject matter will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.

Method and system for automated device testing