In a method of operating a drive train of a motor vehicle including a drive motor with a multi-unit transmission including an unsynchronized main transmission and a synchronized output drive unit, wherein, for performing a shift in the unsynchronized main transmission, a speed synchronization is carried out by means of the drive motor for the engagement of a target gear and, in an emergency mode of the drive motor, a clutch arranged between the drive motor and the main transmission is disengaged, the output gear unit is placed into neutral, the target gear is engaged, the output drive unit is placed into a drive position and the clutch is at least partially engaged.

The invention relates to a method of operating a drive train of a motor vehicle with a motor whose torque is transmitted to the drive wheels via the drive train which includes an unsynchronized main transmission and a synchronized output drive unit.
EP 0 676 566 A1 discloses a method for operating a motor vehicle having an engine and a transmission with an unsynchronized main transmission and a synchronized output drive unit. Arranged between the drive motor and the transmission is a clutch which is actuated by external force. The necessary adaptation of the rotational speed of a transmission input shaft, the so-called synchronization to a synchronous rotational speed of the target gear, in the event of a shift from an original gear to a target gear in the main transmission is carried out by means of the drive motor. Here, the synchronous rotational speed of the target gear is that rotational speed of the transmission input shaft which is generated at the momentary speed of the motor vehicle with the target gear selected.
The synchronization cannot be carried out reliably if the drive motor is not fully functional, that is to say is in an emergency mode. Since the main transmission is embodied as an unsynchronized transmission, there is the risk that the original gear is disengaged but the target gear cannot be engaged. There is therefore no drive connection between the drive motor and driven vehicle wheels. The drive motor therefore cannot be utilized either to accelerate or decelerate the motor vehicle.
It is the object of the present invention to provide a method of operating a drive train including an unsynchronized main transmission and a synchronized output drive unit in such a way that smooth engagement of a target gear can be ensured.

Method for operating a drive train of a motor vehicle


A switching power supply device includes: a transformer; a first switch connected between a high potential terminal of an input DC voltage source and a primary winding; a second switch connected between a low potential terminal of the input DC voltage source and a primary winding; a control circuit outputting a driving pulse signal for synchronizing the first and second switches; first and second rectifying devices; a synchronous rectifier circuit; and a positive bias circuit that applies a positive bias to a control terminal of one of the first and second switches so as to constantly turn the one of the first and second switches ON. When the first and second switches stop a switching operation while an output voltage exists between the output terminals, the positive bias circuit applies the positive bias to the one of the first and second switches.

The present invention relates to a switching power supply device that has a cascaded forward converter unit and a synchronous rectifier circuit and that can be utilized for various electronic apparatuses. Specifically, the cascaded forward converter unit has a plurality of main switching elements. The synchronous rectifier circuit has a rectifying switch element and a commutation switch element.
In regards to a switching power supply device that has high power, it is important to achieve high efficiency and reduction in heating of components. As a measure for the achievement, because it becomes possible to decrease a switching loss of a main switch when it is turned ON, it is efficient that a switching element such as a MOS-FET (Metal Oxide Semiconductor Field Effect Transistor), which has a large rated current and small ON resistance, is used for the main switch. By the way, in general, it is said that the ON resistance of a MOS-FET increases in proportion to the rise of a withstand voltage to the second to second and half power (2-2.5 power). Therefore, it is necessary to use a MOS-FET that has a withstand voltage as low as possible.
In this regard, because an applied voltage to a main switch becomes half in a steady state and a surge voltage that is generated according to switching is clamped by an input voltage, a cascaded forward converter, in which the MOS-FET having a low withstand voltage can be used, is preferred as a circuit system (refer to Japanese Patent Publication Number 2007-74812 described below).
Further, with respect to a switching power supply device in which an output voltage is low and in which a large current flows, because a synchronous rectifier circuit in which a diode is replaced with a MOS-FET as a rectifying device can decrease conduction loss in a rectifier, it is efficient. Further, because the above configuration has advantages with respect to the heating of components, the above synchronous rectifier circuit is preferred as a circuit system (refer to JP 2007-74812 discussed below). As a synchronous rectification operation of the synchronous rectifier circuit that has a rectifying side MOS-FET corresponding to a rectifying switch element and a commutation side MOS-FET corresponding to a commutation switch element, the rectifying side MOS-FET is turned ON in synchronization with an ON driving signal of a main switch at a primary side. On the other hand, the commutation side MOS-FET is turned ON in synchronization with an OFF driving signal of the main switch at the primary side. As a configuration in which a driving signal of a main switch in an insulated converter is transmitted to a secondary side synchronous rectification part, a separately-excited configuration, in which the signal is directly transmitted via an insulation element such as a pulse transformer and a photocoupler, exists. However, because this configuration (the separately-excited configuration) requires a large number of parts, the circuit is complicated. Further, it is also disadvantageous with respect to a mounting space for components. In contrast, a self-excited configuration, in which the signal is transmitted by using a main winding at a secondary side of a main transformer or a driving winding that is independently provided, exists. Because this configuration (the self-excited configuration) requires a small number of parts, the circuit is relatively simple. Therefore, it is also advantageous with respect to the mounting space (refer to JP 2007-74812 discussed below).
To satisfy the demand for a low voltage and a large current at a load side in a switching power supply device in recent years, in a case in which there is an insufficient output rated current in a single switching power supply device, a plurality of switching power supply devices have been used in parallel.
The present invention is directed to a case in which a plurality of switching power supply devices operate in parallel. The switching power supply device corresponds to a synchronous rectifier circuit in which a DC (direct current)-DC converter unit is a cascaded forward converter unit and in which a rectifier at a secondary side is self-excitedly driven.
FIG. 1 shows a circuit diagram of a conventional switching power supply device that corresponds to a synchronous rectifier circuit in which a DC-DC converter unit is a cascaded forward converter unit and in which a rectifier at a secondary side is self-excitedly driven. An operation according to the conventional switching power supply device is explained below with reference to the circuit diagram of FIG. 1.
In FIG. 1, only the DC-DC converter unit is shown by omitting components of a general switching power supply device in which an input AC (alternating current) voltage is filtered/rectified/smoothed.
In FIG. 1, a main transformer isolates a primary side of the unit from a secondary side of the unit. Further, the main transformer T1 is configured with a primary-side main winding Np, a secondary-side main winding Ns1 and an auxiliary winding Ns2, which drives a commutation side MOS-FET Q4.
The polarities of the primary-side main winding Np, the secondary-side main winding Ns1 and the auxiliary winding Ns2 (in a secondary side) of the main transformer T1 are shown by dots in FIG. 1. Further, phase relations of voltages that are induced at each winding are indicated by arrows in FIG. 1. Main switches Q1 and Q2 correspond to switching elements such as MOS-FETs. The DC-DC converter unit adopts a cascade forward configuration. Therefore, a connection configuration between input DC voltage terminals +Vin and −Vin of an input DC voltage Vin is in the following order: the input DC voltage terminal +Vin on a high potential side, a drain terminal of the main switch Q1, a source terminal of the main switch Q1, a dot mark side of the primary-side main winding Np of the main transformer T1, a non-dot mark side of the primary-side main winding Np, a drain terminal of the main switch Q2, a source terminal of the main switch Q2 and the input DC voltage terminal −Vin on a low potential side. Further, an input capacitor C1 is connected between the input DC voltage terminals +Vin and −Vin.
Further, a cathode of a rectifying device CR2 is connected to the source terminal of the main switch Q1, and on the other hand, an anode is connected to the input DC voltage terminal −Vin on the low potential side of the input DC voltage Vin.
Further, an anode of a rectifying device CR1 is connected to the drain terminal of the main switch Q2, and on the other hand, a cathode is connected to the input DC voltage terminal +Vin on the high potential side of the input DC voltage Vin.
Though descriptions of a detection circuit of an output voltage Vout are omitted in FIG. 1, the detection circuit of the output voltage Vout detects a fluctuation error between a setting voltage and the output voltage Vout and feedbacks the fluctuation error to a control circuit. Further, the control circuit outputs a driving pulse signal that variably controls a time ratio of ON and OFF operations of the main switches Q1 and Q2 so as to correct the fluctuation error. That is, so-called PWM control is performed.
The main switches Q1 and Q2 perform switching operations (ON/OFF operations) in synchronization with each other by inputting the driving pulse signals from the control circuit to each of the control terminals of the main switches Q1 and Q2.
Source potentials of the main switches Q1 and Q2 are different. In this case, the source potential of the main switch Q2 is connected to a GND potential of the control circuit that outputs the driving pulse signal via the input DC voltage terminal −Vin on the low potential side of the input DC voltage Vin. On the other hand, the source potential of the main switch Q1 is connected to the main transformer T1 in which a potential significantly fluctuates by the switching operation. Therefore, the driving pulse signal for the main switch Q1 is isolated in the middle of a transmission path from the control circuit (indicated by dual wavy lines in the diagram) and is floated from the GND potential of the control circuit.
Because the main switches Q1 and Q2 perform the switching operations in synchronization with each other, the input DC voltage Vin is intermittently applied to the primary-side main winding Np of the main transformer T1. On the other hand, in the secondary side of the main transformer T1, a rectification smoothing circuit, which is configured with a rectifying side MOS-FET Q3, the commutation side MOS-FET Q4, a choke coil L1 and a capacitor C3, is connected to the secondary-side main winding Ns1.
A drain terminal of the commutation side MOS-FET Q4 and one end of the choke coil L1 are connected to a terminal on the dot mark side of the secondary-side main winding Ns1. Further, the other end of the choke coil L1 is connected to an output terminal +Vout. On the other hand, a drain terminal of the rectifying side MOS-FET Q3 is connected to a terminal on the non-dot mark side of the secondary-side main winding Ns1. Further, a source terminal of the rectifying side MOS-FET Q3, a source terminal of the commutation side MOS-FET Q4 and an output terminal −Vout are connected to each other. In addition, a capacitor C3 is connected between the output terminals +Vout and −Vout.
When the main switches Q1 and Q2 are turned ON, the input DC voltage Vin is applied to the primary-side main winding Np of the main transformer T1 in the direction of the arrow (the dot side indicates the high potential) shown in FIG. 1. In this case, voltages are respectively generated at the secondary-side main winding Ns1 and the auxiliary winding Ns2 in the direction of the arrow (the dot side indicates the high potential) in the same manner as the above. Specifically, the voltages are in proportion to each turn ratio of a set of the primary-side main winding Np and the secondary-side main winding Ns1 and a set of the primary-side main winding Np and the auxiliary winding Ns2 of the main transformer T1. At the same time, because the voltage that is generated at the secondary-side main winding Ns1 is applied to the gate terminal of the rectifying side MOS-FET Q3 as a positive bias voltage via a capacitor C2 and a resistor R1, the rectifying side MOS-FET Q3 is turned ON. On the other hand, the voltage that is generated at the auxiliary winding Ns2 is a reverse bias voltage for the gate terminal of the commutation side MOS-FET Q4. Therefore, because a gate stored charge of the commutation side MOS-FET Q4 is discharged, the commutation side MOS-FET Q4 is immediately turned OFF.
On the other hand, when the main switches Q1 and Q2 are turned OFF, the input DC voltage Vin that is applied to the primary-side main winding Np of the main transformer T1 is released so that a flowing current Ip is immediately interrupted. Thereafter, as shown in FIG. 2, in the main transformer T1, exciting energy, which is accumulated into an inductance of the main transformer T1 by an excitation current that is obtained by eliminating a transmission electric current to the secondary side from the flowing current of the main transformer T1, is generated at the primary-side main winding Np of the main transformer T1 as a flyback voltage that has an inverted polarity with respect to the polarity of the voltage that is applied when the main switches Q1 and Q2 are turned ON. The flyback voltage described above is clamped by the rectifying device CR1 and a rectifying device CR2, that is by the input DC voltage Vin at most.
In this case, in the same way as the primary-side main winding Np, flyback voltages are respectively generated also at the secondary-side main winding Ns1 and the auxiliary winding Ns2 in a direction (the non-dot side indicates the high potential) opposite to the arrow shown in FIG. 1. A peak value of the flyback voltages are in proportion to the turn ratio of each winding. Because the voltages respectively generated at the secondary-side windings are reversed compared with a case in which the main switches Q1 and Q2 are turned ON, the gate terminal of the rectifying side MOS-FET Q3 becomes in a reverse bias state so that a gate stored charge of the commutation side MOS-FET Q3 is discharged. As a result, the commutation side MOS-FET Q3 is immediately turned OFF. Because the flyback voltage that is generated at the auxiliary winding Ns2 is applied to the gate terminal of the commutation side MOS-FET Q4 as a positive bias voltage via a resistor R2, the commutation side MOS-FET Q4 is turned ON.
As explained above, the rectifying side MOS-FET Q3 and the main switches Q1 and Q2 are turned ON in synchronization with each other. On the other hand, the commutation side MOS-FET Q4 is turned ON in synchronization with the turning OFF state of the main switches Q1 and Q2.
At the primary side, a DC voltage is converted into an AC voltage by chopping the input DC voltage Vin by the main switches Q1 and Q2. Then, the AC voltage is transmitted from the primary-side main winding Np to the secondary-side main winding Ns1 via the main transformer T1. Further, the transmitted AC voltage is rectified by synchronous rectifying MOS-FETs Q3, Q4. Further, the transmitted AC voltage is smoothed by the smoothing circuit that is configured with the choke coil L1 and the capacitor C3. At the time, ON and OFF time ratios (a pulse width) of the main switches Q1 and Q2 are variably controlled so as to obtain a desired DC voltage.
An operation of the smoothing circuit is explained below. The energy transmission via the secondary-side main winding Ns1 is cut off when the main switches Q1 and Q2 and the rectifying side MOS-FET Q3 are synchronously turned OFF. However, energy, which is accumulated into the choke coil L1 (an inductor) during an ON period of the main switches Q1 and Q2 immediately before the cut-off, is continuously supplied to the capacitor C3 and a load via the commutation side MOS-FET Q4 that is shifted to be in an ON state. As a result, the smoothing can be achieved.
The operation of the conventional switching power supply device, in which the DC-DC converter unit adopts the cascade forward configuration and the rectifier at the secondary side corresponds to the synchronous rectifier circuit that is driven by the self-excited configuration, is explained above.
As operating states of the switching power supply device explained above, the following states are typically known: a plurality of switching power supply devices connected in parallel are operated so as to correspond to high power demand; the switching power supply device is operated by connecting a battery as a load; and the switching power supply device is operated in a light-load state including a non-load state by connecting a large capacity capacitor at the load side.
When the switching power supply device, in which the synchronous rectifier circuit that is driven by the self-excited configuration and that is adopted as the rectifier at the secondary side as described in the above background, is under operation in the states explained above and when the main switches stop the switching operations for some reason, the rectifying side MOS-FET and the commutation side MOS-FET alternatively repeat the ON and OFF operations even though the main switches stop. As a result, a self-excited oscillation state can be generated. Specifically, in the self-excited oscillation state, energy is regenerated for an input side of the stopped switching power supply device by the output of the other parallel connected switching power supply devices that are normally operated, by the battery of the load or by the large capacity capacitor at the load side.
As a cause of the stop of the main switches, the following cases are considered: operations of various protection functions such as an overvoltage protection and an heating protection; variation/unevenness of potential differences among the output voltages Vout of the parallel connected power supply devices; a general breakdown; and a stopping operation as a remote control function of the power supply device.
The self-excited oscillation can be generated by a mechanism explained below. There are two modes for the self-excited oscillation. Specifically, a mode 1 is explained with reference to FIG. 2 and a mode 2 is explained with reference to FIG. 3 below.
First of all, both of the main switches Q1 and Q2 or one of them are/is suddenly turned OFF. As a result, flyback voltages are generated at each winding of the main transformer T1 in the direction of the arrows (the non-dot sides indicate the high potentials) shown in FIG. 2. The flyback voltage regenerates energy for the primary side input by the rectifying devices CR1 and CR2 even at this time. Because the gate terminal of the commutation side MOS-FET Q4 becomes in a positive bias state according to the flyback voltage explained above, the commutation side MOS-FET Q4 is turned ON. In this state, when the voltage (an energy source) exists at the output terminal +Vout, an inductor current IL that flows in the choke coil L1 (the inductor) in a direction opposite to the normal operation, i.e., from the side of the current output as shown in FIG. 2. Further, a current Iq4 flows in the commutation side MOS-FET Q4. While a part of the inductor current IL stores energy in the choke coil L1 (the inductor), the inductor current IL increases as time elapses. When the main switches Q1 and Q2 are turned ON, the current flows in the main transformer T1. The flyback voltage is generated by exciting energy that is accumulated into the inductor (the choke coil L1) by an excitation current component. Specifically, the excitation current component is obtained by eliminating the transmission electric current from the current flowing in the main transformer T1. When the exciting energy is consumed and exhausted, the flyback voltage decreases. As a result, the commutation side MOS-FET Q4 is eventually turned OFF (the above explanation is defined as the mode 1).
When the commutation side MOS-FET Q4 is turned OFF, a voltage at a node connected between the drain terminal of the commutation side MOS-FET Q4 and the choke coil L1 (the inductor) increases up to an electrical potential. Specifically, this electrical potential of the increased voltage is obtained by adding the voltage at the output terminal +Vout and an electromotive voltage which is generated by the energy being accumulated into the choke coil L1 (the inductor) during the ON period of the commutation side MOS-FET Q4. Because the increased voltage is the positive bias voltage for the gate terminal of the rectifying side MOS-FET Q3 via a series circuit of the resistor R1 and the capacitor C2, the rectifying side MOS-FET Q3 is turned ON. At the same time, the increased voltage is applied to the secondary-side main winding Ns1 of the main transformer T1 in the direction of the arrow (the dot side indicates the high potential) shown in FIG. 3. Even at this time, the inductor current IL that flows in the choke coil L1 (the inductor) in the direction opposite to the normal operation, i.e., from the side of the current output as shown in FIG. 3. However, because the energy is discharged from the choke coil L1 (the inductor), the inductor current IL decreases as time elapses. Further, a current Iq3 flows in the rectifying side MOS-FET Q3. At this time, a voltage in which a peak value is proportional to the turn ratio between the primary-side main winding Np and the secondary-side main winding Ns1 is generated at the primary-side main winding Np of the main transformer T1 in the direction of the arrow (the dot side indicates the high potential) shown in FIG. 3. Though the main switches Q1 and Q2 are turned OFF, energy regeneration from the secondary-side output to the primary-side input occurs because body diodes inside the main switches Q1 and Q2 are provided in forward directions with respect to the input DC voltage source. Even at this time, the exciting energy is accumulated into the choke coil L1 (the inductor) by an excitation current Ip in the main transformer T1. When the inductor current IL of the choke coil L1 (the inductor) is equal to an excitation current of the secondary-side main winding Ns1 by discharging the energy that is accumulated into the choke coil L1 (the inductor), the electromotive voltage of the choke coil L1 (the inductor) decreases. As a result, the rectifying side MOS-FET Q3 is eventually turned OFF (the above explanation is defined as the mode 2).
Thereafter, the flyback voltage is generated in the main transformer T1 again by the exciting energy that is accumulated so far in a direction (the non-dot side indicates the high potential) opposite to the arrow shown in FIG. 1 so that the mode 1 starts. Thereafter, the switching power supply device becomes in the self-excited oscillation state in which the mode 1 and the mode 2 are alternatively repeated.
Because the self-excited oscillation state is an uncontrolled state, there is a possibility that the voltage unexpectedly increases depending on the impedance between input DC voltage terminals (+Vin and −Vin). In this case, there is a possibility that the main switches Q1 and Q2 are broken because an unexpectedly increased voltage exceeds withstand voltages of drain-source voltages Vds between the drains and the sources of the main switches Q1 and Q2. Further, the voltage that is obtained by adding the electromotive voltage of the choke coil L1 (the inductor) and the output voltage is applied between the drain and the source (Vds) of the commutation side MOS-FET Q4 when the commutation side MOS-FET Q4 is turned OFF. Similarly, the above added voltage is also applied between the gate and the source (Vgs) of the rectifying side MOS-FET Q3. Therefore, there is a possibility that the rectifying side MOS-FET Q3 and the commutation side MOS-FET Q4 are broken because the added voltage exceeds respective withstand voltages thereof.
Further, there are the following other possible problems: generation of an abnormal loss by flowing an unexpected current; abnormal heat due to the abnormal loss; influence to other power sources as energy sources connected in parallel; and influence to a battery.
Output pulse waveforms of a conventional control circuit shown in FIG. 5 are used in a circuit diagram shown in FIG. 4 to conduct an experiment of self-excited oscillation. Specifically, a voltage Vext that is higher than an output voltage Vout of a power source is applied from outside by turning an external power source application switch S1 ON. When the voltage Vext is applied, the main switches Q1 and Q2 stop their operations so that the self-excited oscillation occurs. At this time, corresponding pulse waveforms are generated as shown in FIGS. 6 and 7. In FIGS. 6 and 7, both a peak upper limit value and a peak lower limit value of an inductor current IL flowing in a choke coil L1 (an inductor) are shifted downwardly. Further, a mean value becomes a negative value from a positive value. The above states show that because the electric power (an external power source) is supplied from the outside, the self-excited oscillation state starts.


A new and useful DMA-like arrangement provides fast inter-system transfers of large data volumes. A preferred embodiment of the invention includes a data-transfer-out system and further includes a data-transfer-in system. At least one of the systems has a dual ported memory structure configured in a way so that data can move out of a memory module of the structure from one port while other data can independently move into the memory module through the other port. The systems are detachable with respect to each other, and the memory modules of both systems are correspondingly paired with compatible specifications such as module sizes. Furthermore, these memory modules are physically configured in a way so that inter-system data transfer occurs in a parallel (i.e., module to module) manner without the aid of the CPU of the system that has the dual ported memory structure.

1. Field of the Invention
The present invention pertains generally to computing system memory management and, more particularly, to copying data to memory of a detachable device using a direct memory access (DMA) mechanism.
2. Background of the Invention
DMA is a well-known technique for transferring data between one sub-system within a computer system to another sub-system without the aid of the system's central processing unit (CPU). Examples of sub-systems using DMA include disk-drive controllers, graphics cards, network cards and sound cards. If the CPU were used, as another example, to transfer program instructions stored on a secondary storage (e.g., hard disk, a RAM drive) into the primary storage (e.g., system RAMs) for execution, operations would be severely slowed and overall system performance severely degraded.
Typically as a solution, a dedicated DMA controller is used to load the program, freeing the CPU for other operations. The DMA controller may include a processor and numerous registers that keep track of the start address from which bytes of data are to be moved, the address to where those bytes should be placed, and the number of bytes involved in the move operation.
Given that the DMA and CPU memory access usually share the same information buses for data and/or commands, therefore, while the DMA controller is executing a memory data transfer, the CPU is not able to access the same memory for read/write operations. One solution to this is to make use of multi-ported or dual ported memories. Generally speaking, the CPU and DMA controller can both access the same memory contents through separate ports with minimal interference to the memory cycle performance.
One disadvantage however is that any typical DMA is a method for intra-system data transfers. It fails to adequately address any large volume (e.g., multiple terabytes or multiple-million files) data transfer needs for inter-system data transfers. Today, there are numerous areas in our society where large volume electronic data transfers are time critical activities, for example, data transfers for electronic evidence such as emails, chat messages and other electronic documentation in discovery proceedings during litigation. Other activities include data transfers of daily financial information, Homeland security processing for air flights and other modes of entries into the USA, and clinical trial related pharmaceutical bioinformatics tasks.
Transferring large volume of data from one system to another is an input/output (I/O) intensive activity where the data transfer bottleneck is its single I/O interface (e.g., IDE, SATA, SCSI Fiber Channel). IDE and SATA interfaces provide a throughput ranging from 150-300 MB/s. USB devices operate at approximately 60 MB/s. Operating at the highest rates and assuming only a few large files, a terabyte (TB) takes approximately 1-2 hours to transfer from one drive to another. When files have smaller sizes, the transfer time could be extended as much as 6-8 hours for the transfer.

Detachable direct memory access arrangement


A moisture sensor device for detecting the degree of wetting of a transparent pane by drop-shaped precipitation. The sensor device is provided with a beam guide element, which is affixed to the pane by an optical adhesive. A beam transmitter and a beam receiver are each associated with a lens. Such a sensor device solves the problem of guaranteeing optimum conditions for the generation and output of rays into and out of a beam guide element. Aspherical lenses are associated with and arranged at a short distance from the beam transmitter and the beam receiver. Each lens has a surface facing the beam transmitter or beam receiver which in outline is fashioned according to a polynomial selected to be equal to or greater than the third degree and is developed to form a body of rotation.

DE 33 14 770 C2 discloses a sensor device wherein two lenses are arranged on a beam guide element. One lens is associated with a beam transmitter and the other lens is associated with a beam receiver. The cited publication discloses no details about the construction of the lenses or the way in which they are assigned to the beam transmitter and the beam receiver.