According to this invention, a group III nitride inverted high electron mobility transistor, and a power amplifier using the same are provided. A transistor and power amplifier according to this invention are characterized in that the lattice constant of a bulk of a donor layer is larger than that of an underlayer containing a group III nitride compound semiconductor material, or the donor layer is made of impurity-doped AlyGa(1xe2x88x92y)N, the underlayer is made of undoped AlxGa(1xe2x88x92x)N, and x and y satisfy an inequality 0xe2x89xa6y less than xxe2x89xa61.

This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-184647, filed Jun. 30, 1999; and No. 2000-179544, filed Jun. 15, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a high electron mobility transistor and power amplifier and, more particularly, to a group III nitride inverted high electron mobility transistor and a power amplifier using the same.
Since field effect transistors (FETS) using a group III nitride compound semiconductor material, especially, gallium nitride (GaN) can realize high output power in the high-frequency range, they are expected to be used as power elements. As such transistors, a metal-semiconductor field effect transistor (MESFET), high electron mobility transistor (HEMT), metal-insulator field effect transistor (MISFET), and the like have been proposed.
Among these transistors, according to a GaN-based HEMT which has an AlGaN layer as a donor layer and a GaN layer as a channel layer, higher density of two-dimensional electron gas can be realized in the channel layer compared to a GaAs-based HEMT which has an AlGaAs layer as a donor layer and a GaAs layer as a channel layer. Therefore, the GaN-based HEMT is considered as a very promising high-output element. However, in order to realize high-output characteristics by the GaN-based HEMT, some problems remain unsolved, as will be described below.
FIG. 1 is a schematic sectional view showing a conventional GaN-based normal HEMT. A GaN-based HEMT 110a shown in FIG. 1 has the following structure. That is, a GaN underlayer 114, a GaN channel layer 111, and an Alxcex1Ga(1xe2x88x9260)N (0 less than xcex1 less than 1) donor layer 113 are stacked in turn on a substrate 115, and a gate electrode 116, and source and drain electrodes 117 and 118 are formed on the AlGaN layer 113.
In such structure, a good ohmic contact must be achieved between the source and drain electrodes 117 and 118, and the AlGaN layer 113. However, since the AlGaN layer 113 has a broad band gap, it is hard to achieved a good ohmic contact between the source and drain electrodes 117 and 118, and the AlGaN layer 113. For this reason, in the GaN-based HEMT 110a shown in FIG. 1, the contact resistance between the source and drain electrodes 117 and 118, and the AlGaN layer 113 is large. Hence, the GaN-based normal HEMT structure shown in FIG. 1 cannot realize sufficiently high output.
A structure shown in FIG. 2 is known as the one for combating the problems that have been explained in association with the GaN-based normal HEMT structure shown in FIG. 1. FIG. 2 is a schematic sectional view showing a conventional GaN-based inverted HEMT (IHEMT). In this GaN-based inverted HEMT 110b, an Alxcex1Ga(1xe2x88x92xcex1)N (0 less than xcex1 less than 1) donor layer 113 is formed on a GaN underlayer 114 as in a GaAs-based inverted HEMT. A GaN channel layer 111 is stacked on the AlGaN layer 113, and a gate electrode 116, and source and drain electrodes 117 and 118 are formed on the GaN layer 111 (O. Aktas, et al., IEEE Electron Device letters, Vol. 18, No. 6, pp. 293-295, 1997).
The GaN-based inverted HEMT 110b shown in FIG. 2 is mainly different from the GaN-based normal HEMT 110a shown in FIG. 1 in that the Alxcex1Ga(1xe2x88x92xcex1)N donor layer 113 is located between the GaN channel layer 111 and GaN underlayer 114. In such inverted HEMT, the source and drain electrodes 117 and 118 are formed on the GaN layer 111 unlike the normal HEMT. Also, the band gap of the GaN layer is narrower than that of the AlGaN layer. Therefore, according to the inverted HEMT 110b shown in FIG. 2, the aforementioned problem of the contact resistance can be avoided.
However, the difference between the lattice constants of GaN and Alxcex1Ga(1xe2x88x92xcex1)N is one or more orders of magnitudes larger than that between GaAs and Alxcex1Ga(1xe2x88x92xcex1)As. For this reason, in the GaN-based inverted HEMT 110b shown in FIG. 2, larger piezoelectric charges are produced compared to the GaAs-based inverted HEMT. The piezoelectric charges act to reduce the density of two-dimensional electron gas in the GaN channel layer 111 with respect to the HEMT 110b having the structure shown in FIG. 2. Therefore, even the GaN-based inverted HEMT structure shown in FIG. 2 cannot realize sufficiently high output power.
It is an object of the present invention to provide a group III nitride high electron mobility transistor which can realize high output power.
It is another object of the present invention to provide a power amplifier using a group III nitride high electron mobility transistor which can realize high output power.
According to the first aspect of the present invention, there is provided a group III nitride high electron mobility transistor comprising an underlayer comprising a first group III nitride compound semiconductor material, a donor layer formed on the underlayer and comprising a second group III nitride compound semiconductor material, a lattice constant of a bulk of the donor layer being larger than a lattice constant of the underlayer, a channel layer formed on the donor layer and comprising a third group III nitride compound semiconductor material, and gate, source, and drain electrodes formed on the channel layer.
According to the second aspect of the present invention, there is provided a group III nitride high electron mobility transistor comprising an underlayer comprising AlxGa(1xe2x88x92x)N, a donor layer formed on the underlayer and comprising AlyGa(1xe2x88x92y)N, x and y satisfying an inequality 0xe2x89xa6y less than xxe2x89xa61, a channel layer formed on the donor layer and comprising a nitrogen compound, and gate, source, and drain electrodes formed on the channel layer.
According to the third aspect of the present invention, there is provided a power amplifier comprising a group III nitride high electron mobility transistor. which comprises an underlayer comprising a first group III nitride compound semiconductor material, a donor layer formed on the underlayer and comprising a second group III nitride compound semiconductor material, a lattice constant of a bulk of the donor layer being larger than a lattice constant of the underlayer, a channel layer formed on the donor layer and comprising a third group III nitride compound semiconductor material, and gate, source, and drain electrodes formed on the channel layer, an input terminal receiving an input signal and is connected to the gate electrode, an output terminal outputting an output signal and connected to the drain electrode, and a power source connected to the drain electrode via a choke coil.
According to the fourth aspect of the present invention, there is provided a power amplifier comprising group III nitride high electron mobility transistor comprising an underlayer comprising AlxGa(1xe2x88x92x)N, a donor layer formed on the underlayer and comprising AlyGa(1xe2x88x92y)N, x and y satisfying an inequality 0xe2x89xa6y less than xxe2x89xa61, a channel layer formed on the donor layer and comprising a nitrogen compound, and gate, source, and drain electrodes formed on the channel layer, an input terminal receiving an input signal and connected to the gate electrode, an output terminal outputting an output signal and connected to the drain electrode, and a power source connected to the drain electrode via a choke coil.
As described above, the conventional GaN-based IHEMT has a structure in which an Alxcex1Ga(1xe2x88x92xcex1)N (0 less than xcex1 less than 1) donor layer having a smaller lattice constant than that of GaN is stacked on a GaN underlayer. In such structure, since positive piezoelectric charges are produced near the interface of the donor layer with the underlayer, and negative piezoelectric charges are produced near the interface of the donor layer with the channel layer, the density of two-dimensional electron gas in the channel layer lowers. For this reason, the conventional GaN-based IHEMT cannot realize sufficiently high output power.
By contrast, in a group III nitride IHEMT of the present invention, the lattice constant of the bulk of the donor layer is larger than that of the underlayer. Therefore, when a combination of materials that can produce negative piezoelectric charges near the interface of the donor layer with the underlayer is selected from those that satisfy the aforementioned condition, the density of two-dimensional electron gas in the channel layer can be sufficiently raised. That is, sufficiently high output power can be realized. Note that the term xe2x80x9cbulkxe2x80x9d used herein means a solid which extends three-dimensionally, and has a size large enough to ignore effects of surfaces, interfaces, and edges.
In order to produce the aforementioned piezoelectric charges, for example, AlxGa(1xe2x88x92x)N can be used as the first group III nitride compound semiconductor material that forms the underlayer, and AlyGa(1xe2x88x92y)N can be used as the second group III nitride compound semiconductor material that forms the donor layer (x and y satisfy inequality 0xe2x89xa6y less than xxe2x89xa61). When these materials are used as the first and second group III nitride compound semiconductor materials, very high output power can be realized.
In the group III nitride IHEMT of the present invention, for example, GaN can be used as the third group III nitride compound semiconductor material that forms the channel layer. Alternatively, InzGa(1xe2x88x92z)N may be used as the third group III nitride compound semiconductor material (z satisfies inequality 0 less than z less than 1).
The group III nitride IHEMT of the present invention may have a spacer layer, which comprises the fourth group III nitride compound semiconductor material, between the donor layer and channel layer. For example, when the aforementioned materials are used as the first and second group III nitride compound semiconductor materials, AlyGa(1xe2x88x92y)N can be used as the fourth group III nitride compound semiconductor material.
In the group III nitride IHEMT of the present invention, the underlayer may be a thin film formed on a substrate such as a wafer, or may be a substrate itself such as a wafer. In the former case, the underlayer can be obtained by crystal growth of the first nitrogen compound on the substrate. In this case, it is preferable that a nucleation layer that provides a nucleus for that crystal growth be formed on the substrate, and crystals of first group III nitride compound semiconductor material then be grown.
In the group III nitride IHEMT of the present invention, the density of negative piezoelectric charges produced near the interface of the donor layer with the underlayer is preferably about 1010/cmxe2x88x922 or higher when it is divided by the absolute value of electron charges. On the other hand, the difference between the lattice constants of the bulk of the donor layer and the underlayer is preferably 0.0009% or higher with respect to the lattice constant of the bulk of the donor layer. Alternatively, the difference between the molar ratios of Al in the donor layer and that in the underlayer is preferably 0.00035 or more. In these cases, the effect of increasing the density of two-dimensional electron gas in the channel layer improves.
The lattice constants and compositions of the individual layers that form the group III nitride IHEMT of the present invention can be measured by known methods such as X-ray diffraction, elemental analysis, and the like. That is, when the donor layer consists of mixed crystals like AlyGa(1xe2x88x92y)N, if the molar ratios of the constituent elements are obtained by a known method, the lattice constant of that bulk can be calculated using the vegard""s law.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

High electron mobility transistor and power amplifier


A combination type tape dispenser includes a first member having a cutter and a first tape roll mount, and a second member having a second tape roll mount. The first member and the second member is manipulative to be combined and separated. When the first member and the second member are combined, the first member and the second member form a big tape dispenser to mount a big tape roll on the second tape roll mount and cut a tape of the big tape roll by the cutter. When the first member and the second member are separated, the first member forms a small tape dispenser to mount a small tape roll on the first tape roll mount and cut a tape of the small tape roll by the cutter.

1. Field of the Invention
The present invention relates generally to a tape dispenser, and more particularly to a combination type tape dispenser, which may dispense two sizes of tape rolls.
2. Description of the Related Art
Conventional tape dispensers only dispense single size of tape roll. Some conventional tape dispensers may dispense various tape rolls by replacing the tape reels. This kind of tape dispenser basically has a constant size so that there will be a small dispenser with a huge tape roll or a huge dispenser with a small tape roll.


A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating it.
Although applicable, in principle, to any semiconductor memory devices, the present invention and the problems on which it is based will be explained with regard to ROM memories or read-only memories using silicon technology.
Known ROM semiconductor memory devices of this type use horizontal or vertical MOSFETs as semiconductor memory cells. A customary method for programming such ROM memories consists in modifying threshold voltages of the MOSFETs used in a ROM cell array in accordance with the desired ROM contents by suitably masked vertical channel implantations. In other words, at least two types of MOSFETs are produced, a first type having a first threshold voltage (e.g. without channel implantation) and a second type having a second threshold voltage (e.g. with channel implantation). One type is assigned the logic "1" and the other type the logic "0". Programmed in this way, each transistor can store a single bit.
It is a constant aim in memory development to increase the storage density, that is to say the number of bits that can be stored per unit area or unit volume. One approach in this direction is the continual miniaturization of the structures involved, for example through read only memories (ROM) memories having folded trench structures.
A further approach is in modifying the semiconductor memory elements in such a way that they can each store more than one bit. This can be achieved for example by performing more than one type of channel implantation, with the result that one bit can be stored per memory cell for each channel implantation.
By way of example, four different threshold voltages, that is to say 2 bits per memory cell, can be generated by four different channel implantations. The different threshold voltages can be distinguished by use of a suitable read-out circuit.
2. Summary of the Invention
It is accordingly an object of the invention to provide a semiconductor memory device and a method for fabricating it that overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, whose semiconductor memory elements can store more than one bit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory device formed of a semiconductor substrate having a first conductivity type and a surface. An insulating layer is disposed on the semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in a respective one of the semiconductor memory elements. The bit definition region in a first group of the semiconductor memory elements is a first implantation region disposed at the surface of the semiconductor substrate and has a dopant of the first conductivity type for decreasing the contact resistance. The bit definition region in a second group of the semiconductor memory elements is a second implantation region disposed at the surface of the semiconductor substrate and has a dopant of a second conductivity type for increasing the contact resistance. The bit definition region in a third group of the semiconductor memory elements corresponds to the semiconductor substrate. A further contact region is disposed in the semiconductor substrate outside of the bit definition region. An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.
The idea underlying the invention consists in configuring the respective bit definition region in such a way that it defines the contact resistance between the substrate region and the contact plug region in accordance with the bit to be stored in the respective semiconductor memory element. In other words, the contact hole implantation mask is used for programming, the contact holes being provided with a varying contact resistance. The different resistances can then be assessed during read-out by a suitable evaluation circuit.
The semiconductor memory device according to the invention and the method for fabricating it according to the invention have the following advantages, inter alia, over the known solution approaches. It is possible to realize three-value logic per memory cell using only two implantations. Therefore, for example, three bits can be stored in two cells. This saves a mask plane in comparison with the above-described method that is customary for MOSFETs. The programming does not take place until late in the process after the contact hole etching, which permits a favorable turnaround time. In the case of applications relevant to security, such as e.g. in the smart card field, subsequent read-out by backward preparation is possible only with difficulty.
Finally, no additional steps are necessary in the process sequence because many known overall processes have contact hole implantations in order to reduce the resistance of the contacts to diffusion region, to be precise particularly when titanium silicide or the like is not used. That makes the semiconductor memory device according to the invention and the method for fabricating it according to the invention highly cost-effective.
In accordance with one preferred development, the bit definition region is an implantation region that is located at the surface of the substrate region and serves for setting the contact resistance between the substrate region and the contact plug region. Thus, the contact resistance can be accurately set.
In accordance with a further preferred development, the bit definition region is an implantation region of a dopant of the first conductivity type. This corresponds to a doping on the surface region of the substrate, that is to say, to a decrease in the contact resistance.
In accordance with a further preferred development, the bit definition region is an implantation region of a dopant of a second conductivity type. This corresponds to a counterdoping of the surface region of the substrate, that is to say, to an increase in the contact resistance.
In accordance with a further preferred development, the bit definition region of the semiconductor memory elements corresponds to the substrate region. Thus, it is possible to establish a first state in accordance with a first bit without additional outlay.
In accordance with a further preferred development, the substrate has a further contact region located outside the bit definition region. The further contact region forms a terminal for a simple evaluation circuit, which is additionally connected to the contact plug region in order thus to determine the electrical resistance of the semiconductor memory element.
In accordance with a further preferred development, provision is made of an evaluation circuit device for evaluating the contact resistance of the respective semiconductor memory elements. As indicated above, the evaluation circuit may have a resistance measuring device, but may also operate capacitively or inductively.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a method for fabricating the semiconductor memory device. The method includes the steps of:                a) providing a semiconductor substrate having a first conductivity type;        b) providing an insulating layer on the semiconductor substrate;        c) forming a matrix of contact holes down to the semiconductor substrate in the insulating layer in accordance with respective semiconductor memory elements;        d) providing a surface region of the semiconductor substrate situated underneath each of the contact holes with a contact resistance in accordance with a bit to be stored in a respective semiconductor memory element as a bit definition region of the respective semiconductor memory element, the contact resistance formed by the steps of:                    d1) performing a first implantation with a dopant of the first conductivity type into a first group of the contact holes with remaining ones of the contact holes being masked;            d2) performing a second implantation with a dopant of a second conductivity type into a second group of the contact holes with remaining ones of the contact holes being masked; and            d3) leaving the surface region of the semiconductor substrate situated underneath the respective contact holes in a substrate doping in a third group of contact holes;                        e) providing contact plugs in the contact holes, the contact plugs being in electrical contact with the bit definition region; and        f) providing a further contact region located in the semiconductor substrate outside the bit definition region.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory device and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

Method of making a semiconductor memory device


A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

The currently claimed embodiments of the present invention relate to quantum mechanical circuits, and more specifically, to a quantum mechanical circuit having an electrical conductor that is a poor thermal conductor.
In a typical printed circuit board (PCB), a relatively large continuous ground plane is generally provided. The return current from a signal running across the typical PCB travels uninhibited. While this may be desirable in a normal electrical application, in an electrical application where thermal isolation plays an important role, the electrically conductive continuous ground plane also thermally shorts together everything connected to it. This can create problems in any thermal gradient sensitive application.
Splitting the ground plane where signals need to cross a boundary between two split ground planes is usually avoided entirely in applications where a common electrical ground is needed. A conventional method to mitigate heat transmission is by using capacitors to bridge the gap between the two separated or split ground planes. For thermal gradient sensitive applications, PCBs are typically not used because of the aforementioned thermal shorting issue.
As a result, there remains a need for an electric circuit that reduces heat transmission while allowing electrical conduction. Therefore, it would be desirable to solve this and other problems of the prior art by providing a new kind of circuit for use in a quantum computer, for example a superconducting quantum computer, where heat dissipation or transmission is often not desirable.

Ground discontinuities for thermal isolation

INTERNATIONAL BUSINESS MACHINES CORPORATION


A system, method and computer program product for validating a document classification process, including a document collection; a document classification process performed on the document collection; a random selection module configured to automatically generate a random validation set of documents from the document collection; and a document review process performed on the random validation set of documents to validate results of the document classification process. The system, method and computer program product are configured to dynamically and in real-time measure and display on a computer display device a best case estimate of a quality of the results of the document classification process based on the documents that are validated, and given a size of a total data set of the document collection.

1. Field of the Invention
The present invention generally relates to systems and methods for validating data, and more particularly to systems and methods for real-time, dynamic measurement and display of a best case estimate of results of a review of a randomly selected validation set, and the like.
2. Discussion of the Background
In recent years, systems and methods for validating data have been developed. However, such systems and methods lack robustness with respect to real-time, dynamic measurement and display of a best case estimate of results of a review of a randomly selected validation set, and the like.

System and method for real-time dynamic measurement of best-estimate quality levels while reviewing classified or enriched data


A linear motion guide unit is disclosed, in which a slider fitting over a guide rail for movement is comprised of three components save rolling elements. The three components are joined together in the slider with using no fastener such as threaded fasteners, but just with fit-engagement that makes it possible to shrink the slider down in size. The three components are made up of a carriage made therein with raceway grooves and return passages, an upper component applied to the carriage to fit into recesses on the top surface of the carriage, and a lower component applied to the carriage to fit into recesses on the bottom surface of the carriage. The upper and lower components are joined together with the help of fit-engagement of hooks and hook holes, with holding firmly the carriage between them.

Most linear motion guide units used extensively in diverse fields of machinery such as semiconductor manufacturing equipments, various assembly machines, inspection instruments, medical gadgets, measurement instruments, and so on are needed in years to shrink them down as minuscule or tiny as permitted in construction, even with making sure of highly precise and smooth movement between components allowed to slide relatively to one another. Latest advanced linear motion guide units have been in pursuit of maintenance-free and especially miniaturization in construction, besides improvements in operational performance including high precision, fast travel, and so on. To meet with the micromechanical requirements as stated earlier, a variety of components and parts to build the linear motion guide unit is getting smaller in construction and less in their number to reduce the assembling steps as well as make any difference in dimension between mating parts less, which might occur in assembling steps, thereby making components or parts as integral as possible. Moreover, it has been needed to relieve the carriage of the slider from many chores including tiny hole-making operation, tiny tapping operation, tiny screw-driving operation, and so on. In summary, the linear motion guide units are now one of the elementary machines practically indispensable to every machine and correspondingly they are used in a wide range of sizes and versions. Nevertheless, modern advanced micromachines needs to further shrink the linear motion guide unit down in size, even with making certain of nimble sliding operation of the slider over the guide rail.
One version of the prior linear motion guide units is disclosed in the commonly assigned Japanese Patent Laid-Open No. 2001-12465, in which a guide rail is composed of a pair of lengthwise sides and a lengthwise bottom joining the sides together with one another along their lengthwise lower edges. With the prior linear motion guide unit recited just above, a slider is comprised of a carriage mostly accommodated in a lengthwise recess defined between widthwise opposing sides of the guide rail, end caps arranged on forward and aft ends of the carriage, one to each end, and end seals attached on the end caps, one to each cap, to seal clearances between the guide rail and the end caps. The end caps and end seals are tightened together to the carriage by means of machine screws, which are screwed into matching threaded holes made in the carriage.
With the prior linear motion guide unit constructed as stated earlier, the carriage is necessarily made therein with threaded holes that are used to fasten both the end caps having turnaround passages therein and the end seals on the forward and aft ends of the carriage. Thus, the prior linear motion guide unit recited earlier is remarkably complicated in construction and further has to go through some troublesome processes of tapping into the carriage in advance to hardening of the carriage, and precise fitting, combining and mating the associated parts or components together with one another to assemble the carriage with the end caps and end seals into a unitary slider. Tapping into the carriage is especially unfit for the tiny carriage, which would experience working, assembling, and so on to finish micromechanical linear motion guide units.
Another commonly assigned Japanese Patent Laid-Open No. 2002-227840 discloses a linear motion guide unit suited to be miniaturization, in which component parts to be combined with a carriage are reduced in number while the parts are assembled together in a snap-fit manner. The slider is comprised of a carriage made up of a major upper portion and side portions depending downwards from widthwise opposing edges of the major upper portion, and a composite member including end caps facing forward and aft ends of the carriage and a covering frame integral with the end caps. The composite member is composed of a first member and a second member adapted to fit over the first member from the outside. With the linear motion guide unit constructed as stated earlier, the composite member is brought into engagement with the carriage after first engaging parts or recesses in the forward and aft ends of the carriage have fit over or conform to their mating second engaging parts or projections in the first member of the composite member.
With the linear motion guide unit recited just above, formation of the first engaging parts or recesses in the carriage is needed to fit the composite member over the carriage. Thus, the carriage has to experience working operation to make the first engaging parts prior to hardening process of the carriage to make raceway grooves on steel material. This means that the prior linear motion guide unit recited is also complicated in construction and further unfit for working, assembling operation, and so on to finish micromechanical linear motion guide units.
Another version of the prior linear motion guide units is disclosed, for example in Japanese Patent Laid-Open No. H06-147222, in which a slider striding over a linear guide tack for movement is made up of first to third components. With the linear motion guide unit recited now, the first component includes forward and aft end caps and lengthwise intermediate members joined integrally with the end caps to provide sidewise outside lower portions to define return passages. The second components has a major portion made of metallic material having a lengthwise dimension corresponding to a load-carrying raceway and a return passage of a recirculating circuit where more than one rolling element is allowed to roll through there. The second component further has widthwise opposing ridges raised integrally downwards below the major portion over the lengthwise dimension equal with the overall length of the major portion to provide sidewise inside lower portions to define return passages. The third component is made of forward and aft blocks that are used to fit into forward and aft clearances left between the end caps of the first component and their associated lengthwise end surfaces of the second component, one to each clearance.
With the linear motion guide unit constructed as stated just earlier, tapping operation on the forward and aft ends of the major portion in the second component is needed to join the second component together with both the first and third components with using screws. Thus, the prior linear motion guide unit stated just above, as with other versions recited earlier, is also complicated in construction and further unfit for working, assembling, and so on to finish micromechanical linear motion guide units.
A further another version of the prior linear motion guide arrangement is disclosed in, for example Japanese patent No. 2936166, in which a guide rail having an axis is combined with a guide carriage movable on the guide rail in the direction of the axis, which runs on the guide rail with intermediacy of an endless rolling-element circuit. With the linear motion guide arrangement recited above, the guide carriage includes a guide carriage housing to form a positioning well into which a carriage member fits together with reversing bodies.
The linear motion guide arrangement constructed as stated earlier is needed to make the positioning well, and therefore is complicated in construction and further unfit for working, assembling, and so on to finish micromechanical linear motion guide units.


The present invention relates to a mobile communication device for communicating with a cellular network by means of a serving base node, the mobile communication device further being connected to a subscriber identity module, the mobile communication device being configured to operate in a power optimization mode wherein the power optimization mode comprises extended paging periods, and the mobile communication device is further configured to set up a communication context with the base node using authentication means of the subscriber identity module, wherein the mobile communication device is further configured, in case of detection of a removal of the subscriber identity module and when the power optimization mode is activated: to send an removal alert message to the serving base node by means of said communication context, afterwards to terminate the communication context.

In the field of wireless cellular communication it is known that each mobile communication device is operated with a subscriber identity module, in particular a SIM card or UICC. The subscriber identity module enables to authenticate towards the cellular network the one mobile communication device where it is connected with.
To assure that at one time only one mobile communication device in combination with the same subscriber identity module is authenticated towards the cellular network, it is known, that the mobile communication device needs to ensure that the subscriber identity module has not been removed during a communication session. This is done by sending with each paging a status command to the subscriber identity module. Should this presence detection fail, the mobile communication device has to terminate the communication session immediately. By this means it is assured that a subscriber identity module is not used by two active mobile communication devices on the cellular network.
In the field of wireless cellular communication a new category of devices is introduced in particular covered by new technology specification of long term evolution (LTE), which are the so-called machine-type communication (MTC) devices. Such MTC devices further comprise so-called low cost devices, which are supposed to operate in LTE networks only in a limited way, and hence less equipped with processors and other hardware resources than a full-featured LTE handset.
Those MTC devices are in particular characterized by the fact that they are operated with a battery with an expected lifetime without recharging which is far larger than that of mobile handsets. This is in particular achieved by considering that they are rarely contacted and practically operated stationary, hence a lot of operations used for regular communication measures with the cellular network resp. the base node where the mobile communication device is camping on—hereinafter called the serving base node—can be omitted or at least drastically reduced.
One of these operations is the DRX cycle which indicates the frequency for listening to paging messages from the serving base node. For such machine-type communication devices it is foreseen in particular a low power mode, where at least the DRX cycle is massively enlarged. In standardization document ETSI TS 26.304 Rel. 13.0.0 it is in particular suggested to allow DRX resp. extended DRX (eDRX) cycles with Paging Hyperframes (PH) leading to cycles of 3 to 24 hours. This is fully sufficient for a machine-type communication device, which e.g. once a day sends metering data to a remote server. Further the new Power Saving Mode (PSM) foresees to leave the mobile communication device asleep for a defined time period longer than e.g. a day, introduced in standardization document ETSI TS 24.301 Rel. 12.5.0.
However, with the increase of the DRX cycle it means at the same time that the frequency of detection of the presence of the subscriber identity module is increased to those values as well. This is in particular a problem, as for machine-type communication devices typically the SIMs/UICCs are accessible without removing the battery, unlike it is typically the case for mobile handsets.
In effect there is with recent developments of MTC devices the risk of a security leak in that sense, that more than one mobile communication device could without detection be registered in a cellular network with the same subscriber identity modules at the same time.
It is therefore the goal of present invention to provide a solution where this shortcoming of the recent developments is omitted and that the mobile communication device and the cellular network can react in case of removal of a subscriber identity module from the mobile communication device.
Further alternative and advantageous solutions would, accordingly, be desirable in the art.

Mobile communication device with subscriber identity module


A cleaning unit includes: a cleaning housing which is open toward an image carrier and has a waste toner accommodating part; a cleaning member which scrapes and collects the waste toner on the image carrier; a waste toner storage part storing the waste toner temporarily; and a waste toner conveying member which conveys the waste toner scraped and collected by the cleaning member from the waste toner storage part toward the waste toner accommodating part, wherein: the waste toner conveying member moves in the advancing/retracting direction along the waste toner storage part; and when the waste toner conveying member moves in the retracting direction, the waste toner conveying member moves in contact with the waste toner, and when the waste toner conveying member moves in the advancing direction, the waste toner conveying member moves without contacting the waste toner.

1. Field of the Invention
The present invention relates to a cleaning unit used in an image forming apparatus such as an electrophotographic copying machine and a printer, and in particular, to a cleaning unit which conveys waste toner collected by a cleaning member, a process cartridge using the cleaning unit, and an image forming apparatus using the cleaning unit.
2. Background Art
Conventionally, in an image forming apparatus using, for example, an electrophotographic method, an electrostatic latent image formed on an image carrier such as a photoconductive drum is developed (visualized) with toner by a developing unit, and then the toner images formed by the developing unit are transferred onto a transfer medium such as a paper and an intermediate transfer body by a transfer unit, and toner remaining on the surface of the image carrier is collected by a cleaning unit.
Further, as a cleaning unit, a so-called blade cleaning method, in which a plate shaped cleaning blade is mounted, to a periphery of an opening of a cleaning housing which is open toward the image carrier, and the cleaning blade scrapes off residual toner on the image carrier by bringing the cleaning blade into contact with the image carrier to thereby collect the toner in the cleaning housing, has been widely adopted.
However, except for a case in which waste toner scraped and collected by the cleaning blade immediately falls downward, this kind of blade cleaning methods has drawbacks. That is, in a structure in which the cleaning blade is disposed to face a rotational direction of the image carrier and the rotational direction of the image carrier is downward from above, waste toner scraped and collected by the cleaning blade inevitably is place on an upper portion of the cleaning blade.
A technique for preventing a case, in which waste toner scraped and collected by the cleaning blade is placed on the upper portion of the cleaning blade to damage a waste toner collecting operation due to a cleaning member, and for conveying the waste toner scraped and collected by the cleaning blade to a waste toner accommodating part located at an inner side of the cleaning housing by using a waste toner conveying member, has already been proposed.
As such a technique, for example, a technique in which a rotary driving part is provided above the upper portion (serving as the waste toner storage part) of the cleaning blade and the waste toner conveying member is rotated by the driving part such that the waste toner accumulated in the waste toner storage part is conveyed toward the waste toner accommodating part has been proposed (see JP-A-10-301460).
Further, as another technique in the related art, for example, as shown in FIG. 19A, a technique in which a waste toner conveying member 515 extending between a waste toner accommodating part 512 inside a cleaning housing 511 and the upper portion (waste toner storage part) of the cleaning blade 513 is provided, a rotary driving part 520 (for example, using a crank arm) is provided at a waste toner accommodating part 512 side of the waste toner conveying member 515, the waste toner conveying member 515 is slidably supported by a supporting member 521, and a free end of the waste toner conveying member 515 is rotated to convey the waste toner accumulated in the waste toner storage part toward the waste toner accommodating part 512 has been proposed (see JP-A-2002-123143 and JP-A-2003-162191).
Furthermore, as the waste toner conveying member 515, for example, as shown in FIG. 19B, one in which a frame member 516 has a multi-stage frame structure and openings 517 are provided in the frame member 516 so as to perform waste toner conveying operations at a plurality of places. In FIG. 19A, reference numerals 500, 501, and 502 denote an image carrier, a charged roll, and a cleaning unit, respectively.
However, in each of the cleaning units disclosed in JP-A-10-301460, JP-A-2002-123143 and JP-A-2003-162191, a portion for serving to convey waste toner is rotated by the waste toner conveying member, so that the portion for serving to convey waste toner comes in only line-contact with the waste toner storage part (upper portion of the cleaning blade). Even though a plurality of portions for serving to convey waste toner is provided, the conveying efficiency of the waste toner on the waste toner storage part is apt to be insufficient.
In addition, a large upper space of the waste toner storage part needs to be secured in order to allow the rotary movement of the portion for serving to convey waste toner, which increases the vertical length of the cleaning housing. As a result, a technical problem in which the cleaning unit becomes large occurs.

Cleaning unit, process cartridge using cleaning unit, and image forming apparatus using cleaning unit


A method for production of a welded connection between at least one first electrical conductor and at least one second electrical conductor, in which the conductors are brought into a compression chamber enclosed by delimitation elements and welded therein by an ultrasound welding device, one of the delimitation elements forming a sonotrode which may be subjected to ultrasound vibration. According to the invention, in order to connect a first conductor in the desired circumference with second conductors, where the total cross-section of the second conductors for connection to the first conductor can optionally be greater than the usual cross-section with the ultrasound device used, the first conductor is welded sequentially with two or more second conductors in the compression chamber.

The present invention relates to a method for producing at least one welded joint between at least a first electrical conductor such as a rigid flat support, and at least a second electrical conductor such as litz wires, where the conductors are inserted into a compression space surrounded by limiting elements that can be adjusted relative to one another, and in which they are welded by means of an ultrasound welding device sonotrode which produces ultrasonic vibrations and forms one of the limiting elements.
In order to ultrasonically weld litz wires on a support, according to DE-C-34 37 749 it is provided that the cheeks limiting a compression space laterally can be displaced along the support, whereas the clearance of the cheeks is adjusted to the width of a section of a star sonotrode that dips into the compression space. The support itself is supported on a counter electrode, also called an anvil.
DE-Z.: Die Bibliothek der Technik, Band 108: Ultraschall-Metallschweiβen, Verlag Moderne Industrie, (The Library of Technology, vol. 108: Ultrasonic Metal Welding, Moderne Industrie Publishing), 86895 Landsberg, 1995, page 43, shows a weld between a U-shaped cable lug and electrical conductors. For this purpose, ultrasonic welding devices are used, in which the conductors to be welded are inserted into a compression space that is limited in a known manner by sections of a sonotrode and anvil as well as laterally displaceable cheeks.
From WO-A-95/10866 a method is known for compressing and subsequent ultrasonic welding of electrical conductors, in particular litz wires, in a compression space that can be adjusted to the height and width of the conductor, whereby the conductors to be welded are first compressed and then welded. The compression space can be adjusted to a specified height-width ratio independently of the cross section of the conductor to be welded.
Compression spaces of ultrasonic welding devices that are adjustable in height and width are likewise apparent from EP-B-0 143 936 or DE-A-37 19 083.
The power rating of each of the ultrasonic welding devices that are used is designed for the maximum cross section of the conductors to be welded. If usually control cables, for example, are to be connected to a connector, also called a terminal, the power rating of the ultrasonic welding device to be used is designed for the cross section of the control cables to be welded. If an earth cable is also to be connected, it is connected to the terminal in a conventional manner by means of screws or plugs. The disadvantage of the corresponding connection is that contact resistances may appear, which may disturb the signals of the control cables.
But even if the power of the ultrasonic welding device is sufficient to weld an earth cable or battery cable, for example, to a control cable on a connector, there are still disadvantages in that adequate process monitoring is not possible, because the permissible tolerances when welding conductors with large cross sections are frequently larger than the cross sections of the control cables, so that combination errors could consequently appear that cannot be detected in process monitoring.

Method for producing a welded joint between electrical conductors by means of an ultrasonic welding method


The invention relates to a device for loading substrates into and unloading them from a clean room, comprising a lock device onto which a transport box for receiving the substrates can be placed and which is fitted with a hermetically sealing lock opening, and a process unit adjacent to the lock opening. To allow for a valid adjustment of the lock device in relation to the process unit even when the lock device is exchanged, the invention provides for an adapter device to be positioned between the process unit and the lock device to which the lock device can be removably fixed and which is maintained at the level of the process unit and can be adjustably aligned in relation to same.

With known devices of this type, the processing installation has a manipulating device, by means of which the substrates can be brought from a transport box into the processing installation or vice versa, when the transport box is docked at a lock opening. The exact position of the transport box with respect to the manipulating device, and therefore the processing installation, is important here. This orientation is performed once in a relatively extensive manner during the installation of the device. If now the lock device must be exchanged for whatever reason, another elaborate adjustment of the exchanged lock device with respect to the processing installation is necessary.

Device for loading substrates into and unloading them from a clean room


A method of communication between a transmitter and a receiver over a channel is provided. The transmitter is capable of transmitting packets with multiple data rates, each of which adapts to a respective channel condition with regards to the performance of the communication. The method comprises the steps of at the level of the transmitter: upon detection of a disappearance of deterioration of the channel condition, transmitting packets with a data rate selected from a group of stable data rates that are stably used before the disappearance of the deterioration but larger than the last data rate before disappearance of the deterioration.

A WLAN is such a network system that a part of the wire LAN is constructed by a wireless system, in which wireless stations can be bridged to the backbone network via an access point.
The IEEE 802.11 standard for WLAN data communication provides a multi-rate capability, in which a transmitter can transmit packets using any one of multiple optional data rates according to the quality of the channel condition. That is, the physical layer (PHY) of the IEEE 802.11 standard supports multi-rate transmission of the transmitter by dynamically selecting an appropriate modulation technique, for example, according to the feedback of the receiver on the signal strength of received packets. This in turn will enable a Wireless Network Interface Card (WNIC) to adapt a transmission rate to a radio channel condition.
The following table shows a Modulations and Coding Scheme (MCS) used in the IEEE 802.11 standard. As seen from this table, every transmission rate is adapted by a unique MCS to respective wireless channel condition. If a wireless channel condition can not support one given MCS, another MCS will be adopted to achieve higher throughput.
TABLE 1TransmissionModulationBits perCodingrate802.11 standardSchemeSymbolScheme1bBPSK1 1/112bQPSK2 1/115.5bCCK14/811bCCK24/86a/gBPSK11/29a/gBPSK13/412a/gQPSK21/218a/gQPSK23/424a/gQAM-1641/236a/gQAM-1643/448a/gQAM-6462/354a/gQAM-6463/4
While the IEEE 802.11 standard includes a specification for 802.11 MAC protocol and RF-oriented PHY parameters, it does not define any particular data rate adaption schemes or Rate Control Algorithms (RCAs). This topic is open to device manufacturers to improvise. Several data rate adaption methods have been proposed and used with the IEEE 802.11 standard. Next, some known RCAs will be described.
1. ARF and Onoe Algorithms
ARF (Auto Rate Fallback) was developed for WaveLAN-II 802.11 WNICs. According to the ARF, each transmitter attempts to use a higher transmission rate after a pre-designed fixed number of continuous transmissions at a given rate and switches back to a lower rate relative to its currently used rate after two consecutive failures.
The ARF algorithm has advantages of easy implementation in small devices and good performance in conditions where wireless channel quality is changing frequently. However, in spite of its easy deployment in practical application environment, the ARF algorithm will have a poor performance in a situation where wireless links have no much fluctuation on packet loss caused by environmental changes. For example, in a family environment, people are more inclined to sit down to enjoy wireless applications without frequently moving around. In such case, the ARF may often or in a fixed time interval increase the packets transmission rate over the optimal value to another one, which requires many retries for each packet. It will take much time for this procedure to try many transmission rates which are doomed to fail.
The Onoe algorithm, which basically applies the same idea as the ARF, is a credit based RCA where a credit is used to evaluate the performance under current packet transmission rate (just like a score system). The value of the credit is determined by the numbers of continuous transmission, erroneous transmission and retransmissions accumulated during a fixed period, such as 1000 ms. If less than for example 10% of the packets needs to be retransmitted at a particular rate, the Onoe algorithm will keep increasing its credit point till a threshold value, for example 10, is reached. At this point, the current transmission rate is increased to the next available higher rate and the process will repeat with credit score being zero. Similar logic holds for deducting the credit score and moving to a lower bit-rate for failed packet transmission/retransmission attempts.
Although it can alleviate the fluctuation of channel condition, the Onoe algorithm is relatively conservative. That is, once the Onoe algorithm detects that a transmission rate does not work, it will not attempt to step up again within at least 10 seconds. Also, if wireless channel condition degrades for some reasons, the Onoe algorithm will waste roughly 9 seconds to step down in most of such situations. Assuming that the transmission rate is reduced from 24 Mbps to 5.5 Mbps for an occasional interference, according to a calculation, it will take about 60 s for the Onoe algorithm to recover to the previous rate of 24 Mbps after the interference disappears, which is huge resource consumption in practical applications.
2. AARF and AMRR (Adaptive Multi Rate Retry) Algorithms
As described above, ARF will try to use a higher rate every 10 consecutive packets, which will result in increased retransmission attempts and thus a decreased application throughput if the channel condition is relatively stable. To overcome the above disadvantage, a solution called AARF (Automatic ARF) is proposed to increase the threshold used to decide when to increase the current rate, for example, from 10 to 40 or 80. AARF is an extension of ARF, in which the step up parameter is doubled every time the algorithm tries to increase the packet transmission rate but the subsequent packet fails. This can largely increase throughput in a situation where the channel condition does not dramatically fluctuate.
A weak point of the AARF algorithm is that it will take more time to step up to an optimal transmission rate even channel condition supports this rate. This is because the packet loss exists everywhere and AARF will enlarge the occasional packet loss, which will induce a longer adaption time.
Similarly to the AARF, AMRR algorithm also uses the Binary Exponential technique to adapt the length (threshold) of the sampling period which is used to change the value of transmission rate parameter. AMRR, which was combined to Madwifi 802.11 driver, implements and remains the algorithm principle the same as AARF. Therefore, AMRR has the same weak point as AARF.
3. SampleRate Algorithm
SampleRate algorithm determines the transmission rate based on the history of performance. In this algorithm, the transmitter keeps a record of the number of successive failures, the number of continuous transmissions and the total transmission time along with the destination for that transmission rate. Stale samples are removed based on an evaluation window mechanism.
SampleRate stops using a transmission rate if there are four successive failures. So when starting to send packets over a link, the SampleRate will decrease the transmission rate until it finds a transmission rate that is capable of sending packets. SampleRate selects a random transmission rate every tenth data packet from a set of bit-rates that may be better than the current one and sends the packet using that selected transmission rate. To calculate the average transmission time of each transmission rate, SampleRate uses feedback from the wireless card to calculate how much time each packet transmission required. SampleRate calculates the transmission time for each packet using the packet length, transmission rate and the number of retries.
The SampleRate algorithm can achieve a good performance especially in a channel condition where packet loss often occurs. Compared with some other existing RCAs, SampleRate can adapt itself more quickly to wireless channel condition fluctuation. But according to the principle of this algorithm, we can know that SampleRate actually achieves the optimal transmission rate by a probability fashion. Thus, it will take SampleRate much time to reach the optimal transmission rate, especially in a case of recovering to previous higher rate from a lower rate caused by an occasional interference after the interference disappears.
As a conclusion, conventional data rate adaption methods, including the above described RCAs, have a common disadvantage that the data rate is easy to drop down but difficult to restore.
FIG. 1 is an exemplary diagram showing the adjustment procedure of the existing RCAs. As shown by line 101 in FIG. 1, when an occasional wireless interference occurs, the RCA will quickly respond by degrading the transmission rate step by step to a lower value. However, after the interference disappears, it will take a long time for the RCA to recover transmission rate to the level before the interference occurs, as shown by line 102 in FIG. 1. For example, according to the above-described Onoe algorithm, in most cases when a channel condition deteriorates by interference, it will only take transmission failure time of 5 packets (including retry time) for packet transmission rate to drop from 24 Mbps to 11 Mbps. But in a good channel condition after the interference disappears, it will take 50 seconds to restore to the transmission rate of 24 Mbps.
The main reason of this common disadvantage arises from the fact that all the existing RCAs assume that the wireless network will operate in an environment where channel conditions change frequently due to various interferences. However, if we consider a more dedicated network such as family or home WLAN which operates in a relatively stable environment, a more efficient data transmission rate adaptation method is needed.


An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

This invention relates to providing periodic signals and, more particularly, to mitigating phase/period jitter in periodic signals.
Existing technological applications use periodic signals for various purposes, such as timing or modulation. An ideal periodic signal includes a basic waveform (sometimes called a characteristic waveform) that is repeated cyclically, where each instance of the basic waveform is called a "cycle." It is well known that in an ideal periodic signal the amount of time spanned by each cycle is the same and is called a period. Additionally, the number of cycles per second is called frequency.
Periodic signals used in existing technologies generally must be generated. In reality, these generated periodic signals may be non-ideal at least because some cycles may be longer or shorter than they ideally should be. In other words, the "period" of the periodic signal does not stay the same and may vary from cycle to cycle. This variation is often called "period jitter" or "phase jitter." For convenience, the term phase jitter will be used from this point on to this phenomenon.
Phase jitter may cause undesirable effects in technological applications. For example, when a periodic signal is used to time particular operations, phase jitter may cause the operations to be mis-timed and may cause the operations to fail. Therefore, decreasing phase jitter may be important. Accordingly, there is continued interest in developing systems and methods for decreasing phase jitter in periodic signals.

Systems and methods for mitigating phase jitter in a periodic signal


The present invention discloses a method for the treatment of liver diseases, comprising administering an effective amount of an aminoalcohol of the following formula (1) or a salt thereof: ##STR1## wherein R.sup.1 represents a hydrogen atom or a phosphono group, R.sup.2 represents a hydrogen atom or a group --(CH.sub.2).sub.n --OR.sup.1, and n represents an integer between 2 and 5 inclusive. The present invention also relates to the use of the compound in the manufacture of a remedy for the treatment of liver diseases. This compound exhibits hepatocyte proliferation activity and liver disorder restoring effect, and thus is useful for the treatment of acute hepatitis, chronic hepatitis, hepatic cirrhosis, etc.

1. Technical Field
The present invention relates to remedies for liver diseases such as acute hepatitis, chronic hepatitis, liver cirrhosis, and liver cancer.
2. Background Art
The liver is an organ having a strong regenerative power. In rats, when 70% of the liver parenchyma is removed, the remaining mesenchymal tissue begins to proliferate. Although this phenomenon, liver regeneration, has been considered to be induced by the participation of a certain humoral factor, the mechanism has remained unknown.
In 1984, Nakamura et al. discovered a hepatocyte growth factor (HGF) in blood of a rat having a liver that was in the course of regeneration (Nakamura, T. et al., "Biochem. Biophys. Res. Commun.", 122: 1450-1459, 1984). This discovery was achieved by use, as an index, of the DNA synthesis of hepatocytes of a mature rat in primary culture. Thereafter, cloning of the HGF cDNA satisfactorily led to the determination of the entire primary structure (Nakamura, T. et al., "Nature," 342: 440-443, 1989). As a result, HGF was found to be a new growth factor that has homology with no previously known growth factor whose structure had conventionally been clarified, such as epithelial growth factor (EGF), fibroblast growth factor (FGF), neuronal growth factor (NGF), platelet-derived growth factor (PDGF), or endothelial cell growth factor (ECGF).
In the meantime, Takahashi et al. cultured rat hepatocytes for a long period by use of an extract of epithelial mucosa of the bovine small intestine, and found that hepatocytes proliferate, through orderly aggregation and rearrangement of cells, form liver tissue-like construct and come to newly exhibit some of the liver functions (Takahashi, N. et al.: "In vitro Cellular & Developmental Biology, 25:365-372, 1989). Although there have been attempts to isolate and purify the growth factor contained in this extract and also to determine the structure of the growth factor, no such attempts have been successful so far.
The aforementioned HGF discovered by Nakamura et al. has been found to act as a potent mitogen not only on hepatocytes but also on primary culture of tubular epithelial cells, dermal keratinocytes and melanocytes, type II epithelial cells of pulmonary alveolus, and epithelial cells of gastric mucosa. In addition, it has also been elucidated that HGF has a function as a motogen to stimulate motion of cells as well as action to suppress proliferation of cancer cells.
Research and development of pharmaceuticals making use of diversified biological activities of HGF have currently performed actively. For example, clinical applications of HGF have been explored towards remedy and prevention of hepatitis and renal disorders, promotion of regeneration of the liver after hepatectomy, treatment of wounds, and use as anticancer agents. However, no efforts have been successful in using HGF in practical medicine.


An authentication system includes a terminal and a key authentication unit arranged in a communication peer that communicates with the terminal. The key authentication unit receives key information of the terminal carried by a user through wireless communication and performs key authentication that verifies authenticity of the key information. The authentication system further includes detectors that are arranged at different locations and detect biological information of the user and a biometric authentication unit that uses the biological information to perform biometric authentication. The authentication system further includes a controller that controls actuation of the communication peer based on a location of one of the detectors that detected the biological information, an authentication result of the key authentication, and an authentication result of the biometric authentication.

A known authentication system of a vehicle controls the vehicle through wireless communication between a terminal carried by a user and an onboard device of the vehicle. Patent Document 1 discloses a technique for verifying the authenticity of a terminal through wireless communication between an onboard device and the terminal and identifying a user through biometric authentication based on the biological information of the user. Biometric authentication will improve the security of the authentication system.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2018-62306

Authentication system and authentication method

KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO


A disk drive head suspension headlift formed from a single piece of stainless steel includes a beam region, lift tab and offset region between the beam region and lift tab. The beam region has a major surface and formed side rails. The lift tab is a coined, trough-shaped member at a z-height spaced from the major surface of the beam region. The offset region has a major surface and side rails that transition in height between the side rails of the beam region and the lift tab.

Load beams, headlifts and other components of disk drive head suspensions are well known and commercially available. Methods for manufacturing these components are also well known. By way of example, components and manufacturing methods of these types are shown in the Aoyagi et al. U.S. Pat. No. 6,181,529, Watanabe U.S. Pat. No. 6,483,670, Hayen et al. U.S. Pat. No. 6,617,542, Lee et al. U.S. Patent Application Publication No. 2005/0030671, Japanese Patent No. 2005011511 and Japanese Patent Publication No. 01-107384. There remains, however, a continuing need for improved headlifts and related manufacturing methods. In particular, there is a need for relatively stiff headlifts and efficient manufacturing processes.

Coined headlift with formed rail offset for a disk drive head suspension component


A sensor bearing housing assembly for use with or integrally formed with a bearing housing. The bearing housing having a base portion defining a footprint, a shaft receiving collar, and a bearing race disposed between the shaft receiving collar and the bearing housing. The sensor bearing housing assembly having a pair of lengthwise sidewalls configured to extend upward from the base portion and an endwise sidewall configured to extend upward from the base portion. The pair of lengthwise sidewalls and the endwise sidewall being joined to form a sensor volume for receiving a sensor therein generally defined within a vertical volume bounded by the footprint of the base portion. The sensor bearing housing assembly having a cutout formed in at least one of the pair of lengthwise sidewalls and the pair of endwise sidewall to permit access to a fastener extending through a mounting hole formed in the base portion.

This section provides background information related to the present disclosure which is not necessarily prior art. This section also provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.
It is becoming more critical to monitor the operating parameters of roller bearing systems to ensure proper operation and longevity of the bearing system and associated machinery. In some embodiments, these operating parameters can include, but are not limited to, temperature and/or vibration. Such operating parameters can be helpful indicators of potential bearing failures or other operational concerns. In fact, by way of example, it is generally understood that bearing temperature rise can often indicate that the bearing is not working or performing at optimum conditions. A rise in temperature can often be used as a surrogate for determining the bearing health and likely useful life. In situations where bearing wear—potentially caused by degradation, reduced lubrication, or other contamination—is leading to reduced bearing performance, a commensurate increased in friction and resultant heat is experienced. Therefore, the monitoring of temperature is often important in determining the safe and reliable operation of bearing systems.
Likewise, the monitoring of vibration can be used to further determine bearing health. An increase in vibration or a change in established vibration frequency can often be used as a surrogate for determine excessive wear of the bearing systems, such as wear in the roller bearings and/or race. A change in vibration characteristics can indicate a need for lubrication, maintenance, and/or an impending bearing failure. Therefore, monitoring vibration can also be important in determining the safe and reliable operation of bearing systems.
However, conventional bearing systems can and are used in a wide variety of applications and environments that may lead to space and/or environmental limitations when attempting to employ sensor systems. For example, in some applications, conventional bearing housings (i.e. without sensor systems) may be mounted in space-constrained locations, which limit the size of the bearing housing and prevent use of sensor systems that add to the defined volume of the bearing housing. Unfortunately, the lack of a sensor system prevents monitoring of the bearing operation and associated bearing health.
Accordingly, there is a need to provide a bearing housing system that is configured to receive, contain, and/or protect one or more sensors to monitor the operation of the bearing. Further, there is a need to provide a bearing housing system that is sufficiently compact to fit within a volume defined generally by the footprint and height of the bearing housing to enable its use in space-constrained applications. Moreover, there is a need to provide a bearing housing system that, in some embodiments, form bits and/or is integral with the bearing housing. Furthermore, there is a need to provide a sensor bearing housing that overcome the deficiencies of the prior art.
Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.


Disclosed is a word line driver circuit and a driving method thereof. An input to the circuit has a ground voltage level during a non-selected operating mode and, as the output signal of a word line decoding circuit, is applied at a power source voltage level during a selected operating mode. The output of the circuit has a ground voltage level during the non-selected operating mode and applies a higher voltage than the power source voltage to a word line connected to a memory cell during the selected operating mode. Optionally, a capacitor boosts the output voltage during the selected operating mode.

1. Field of the Invention
The present invention relates to an integrated circuit memory device, and more particularly, to a word line driver circuit for supplying a voltage that is higher than the power source voltage requiring an internal boost voltage, and a driving method thereof.
2. Description of the Related Art
In a typical semiconductor memory device that operates at a low voltage, a bootstrap circuit is used to apply a higher voltage than the operating voltage to the capacitor of a memory cell in order to increase the operating speed in reading or writing data. In other words, to prevent or substantially reduce errors in read or write operations, the voltage corresponding to data applied to a bit line is transferred to the capacitor of a memory cell without dropping the threshold voltage of the access transistor of the memory cell, or data stored in the capacitor is supplied to the bit line without dropping the threshold voltage of the access transistor.
A typical word line driver circuit uses a bootstrap circuit for applying a higher voltage than the power source voltage Vcc to a word line.
FIG. 1 illustrates a word line driver according to the prior art.
Referring to FIG. 1, a word line driver circuit according to the prior art includes four transistors N11, N12, N13 and N14, and control signals SWL_PD, SWL_PDb and SWL_DRV. SWL_PD is typically a column select signal and SWL_PDb is the logical inverse of SWL_PD.
In the word line driver circuit, an output signal MWL of a word line decoding circuit (not shown) is typically a row enable signal. The logical state of MWL is transferred to the gate of transistor N12 via transistor N11 that operates from the power source voltage Vcc at its gate. Transistor N12 is configured to transfer control signal SWL_DRV, having an active state voltage level of an external power source voltage Vpp that is a higher voltage than the power source voltage Vcc, to a word line SWL. The word line SWL is also connected to discharge transistor N14 which is operated by inverse control signal SWL_PDb.
During a stand-by mode before active operation of the word line driver, all control signals shown in FIG. 5, except inverse control signal SWL_PDb, are in an inactive state and are applied with a ground voltage level Vss. When a read or write operation starts, an output signal MWL of a word line decoding circuit is asserted with an active state voltage level of the power source voltage Vcc and is applied to the word line driver corresponding to the selected word line. A node voltage between transistor N11 and transistor N12 rises by the voltage level Vcc−Vth obtained by deducting a threshold voltage Vth of transistor N11 from the power source voltage Vcc. The control signal SWL_DRV is then asserted with the active state voltage level of the external power source voltage Vpp and the node voltage between transistor N11 and transistor N12 is boosted to Vcc−Vth+Vpp due to the capacitance between the drain and the gate of transistor N12. As a result, transistor N12 has a sufficient gate voltage Vcc−Vth+Vpp. Therefore, the voltage level Vpp of control signal SWL_DRV is supplied to the word line SWL without dropping the threshold voltage of transistor N12. An access transistor of the memory cell connected to the word line SWL operates by a word line enable signal as the external power source voltage Vpp, thus errors are prevented.
In the word line driver circuit described above, an additional boost circuit or pumping circuit is supplied to obtain a voltage Vpp that is higher than the power source voltage Vcc and the higher voltage is transferred to the word line through control signal SWL_DRV. The additional boost circuit or pumping circuit to generate a voltage Vpp higher than the power source voltage Vcc must be supplied. Thus the chip size becomes larger and the power consumption increases.
Another example of a word line driver circuit according to the prior art is disclosed in U.S. Pat. No. 5,774,392 to William F. Kraus, et. al., which is referred to in FIG. 2.
Referring to FIG. 2, a word line driver circuit according to the prior art employs a ferroelectric capacitor FC0.
The word line driver circuit is constructed of a self boosting circuit and has an advantage of boosting only a selected word line WL0. This has a disadvantage that the data of memory cells connected to non-selected word lines like WL1 may be interfered with by a floating voltage because the non-selected word lines attain a floating state.
If the gain of transistor N0 and transistor N1 is not precisely determined, the voltage level of word line WL0 boosted by ferroelectric capacitor FC0 may excessively increase the voltage level of node WLEN0′ when control signal BOOSTDRIVE is applied. Thus, there may be the case that the voltage level of word line WL0 becomes the same as the voltage level of control signal WLCLK due to transistor N1. In other words, the voltage level difference of word line WL0 is insufficient for the operation, and in the worst case, there may be the case that a word line cannot be boosted.

Word line driver circuits for use in semiconductor memory and driving method thereof


A ureteral stent includes a first material and a second material. The second material is formulated to have a hardness that is greater than a hardness of the first material. The second material is formulated to be soluble in a bodily fluid. The second material is combined with the first material to form a substantially homogeneous combination of the first material and the second material.

The disclosed invention relates generally to a medical device and more particularly to a ureteral stent having a temporally variable hardness.
Ureteral stents are typically placed within a urinary tract of a patient such that one end portion of the ureteral stent is located in a kidney of the patient and the other end portion of the ureteral stent is located in either a bladder or a ureter of the patient. Some known ureteral stents include retention members configured to retain the ureteral stent in a desired position within the patient. Known ureteral stents are typically positioned within the urinary tract of the patient by placing a guidewire within the patient, sliding the ureteral stent on the guidewire, and then pushing the ureteral stent along the guidewire into a desired position using a push rod. After an appropriate period of time, the ureteral stent is removed from the patient, for example by pulling the ureteral stent from the urinary tract of the patient.
Known ureteral stents are designed to provide optimal functionality while minimizing patient discomfort. Some design features that provide improved comfort, however, may decrease functionality. For example, hard stents are known to be more resistant to deformation and easier to position within the urinary tract than soft stents. As the hardness of the stent increases, however, the patient will generally experience greater discomfort while the stent is within the urinary tract. Conversely, softer stents may alleviate patient discomfort, but they are generally more difficult to insert into the patient.
To accommodate the need for both comfort and functionality, some known ureteral stents are configured such the stent hardness (also characterized as the stent durometer) varies spatially along the longitudinal axis of the stent. For example, the distal end section has a relatively high durometer, facilitating insertion of the stent (for which the durometer of the distal end portion is more important) while the proximal end portion has a relatively low durometer, affording greater comfort to the patient because the proximal end portion is typically in contact with the more sensitive area at the junction of the ureter and bladder. Other known stents are configured such that all or a portion of the stent dissolves or degrades upon being inserted into the patient's urinary tract, thereby increasing patient comfort and eliminating the need to remove the stent. Such dissolvable stents, however, do not retain their original shape or size.
Thus, a need exists for a ureteral stent configured to have a relatively high durometer to ease insertion and that softens after insertion to increase patent comfort, while retaining its original size and/or shape.