This invention relates to polybutadiene modified polymer polyols which comprise one or more base polyols, at least one preformed stabilizer, one or more ethylenically unsaturated monomers, and polybutadiene, in the presence of at least one free radical polymerization catalyst, and optionally, one or more chain transfer agents. The polybutadiene present in these polybutadiene modified polymer polyols may be carried into the polymer polyol through the preformed stabilizer, by a polybutadiene containing component that is added separately from the preformed stabilizer to the polymer polyol, or a combination thereof, with the total amount of polybutadiene ranging from 0.03 to 1.0% by weight of polybutadiene, based on 100% by weight of the polymer polyol. The present invention also relates to processes for preparing these polybutadiene modified polymer polyols, to foams prepared from these polybutadiene modified polymer polyols, and to processes for producing foams from these polybutadiene modified polymer polyols.

This invention relates to polybutadiene modified polymer polyols, foams comprising these polybutadiene modified polymer polyols, and to processes for the production thereof.
Various types of filled polyols are known and described in the art. Filled polyols are typically stable dispersions of solid particles in a liquid base polyol. More specifically, the known filled polyols include, for example, polyisocyanate polyaddition (i.e. PIPA) polyols, polyurea and/or polyhydrazodicarbonamide (i.e. PHD) polyols and polymer (i.e. PMPO) polyols.
The basic patents relating to such polymer polyol compositions are Stamberger, U.S. Patent. Re. 28,715 (reissue of U.S. Pat. No. 3,383,351) and U.S. Patent. Re. 29,118 (reissue of U.S. Pat. No. 3,304,273). As described therein, a stable dispersion of polymer particles in a polyol can be produced by polymerizing one or more ethylenically unsaturated monomer dissolved or dispersed in a polyol in the presence of a free radical catalyst.
Since then, numerous patents have issued which describe various advances such as increasing solids contents, decreasing viscosity, enhancing stability, etc. in polymer polyols. These patents include, for example, U.S. Pat. Nos. 3,652,639, 3,823,201, 3,850,861, 3,931,092, 4,014,846, 4,093,573, 4,148,840, 4,172,825, 4,208,314, 4,242,249, 4,342,840, 4,390,645, 4,394,491, 4,454,255, 4,458,038, 4,460,715, 4,550,194, 4,652,589, 4,745,153, 4,997,857, 5,196,476, 5,814,699, 5,990,185, 6,455,603, 7,160,975, 7,179,882, 7,759,423 and Re 32,733 (reissue of U.S. Pat. No. 4,463,107).
It is known that the filled polyols are suitable isocyanate-reactive components for the preparation of polyurethane materials such as foams, elastomers, etc. The two major types of polyurethane foams are termed slabstock foams and molded foams. Slabstock foams are used in the carpet, furniture and bedding industries. Primary uses of slabstock foam are as carpet underlay and furniture padding. In the molded foam area, high resiliency (HR) molded foam is the most common type foam made commercially. HR molded foams are used in the automotive industry for a breadth of applications ranging from molded seats to energy-absorbing padding and the like. As the demand for polymer polyols has increased, and the need for better and improved properties in the polymer polyols has increased, new advances in polymer polyol technology have been achieved.
In spite of advances in reduction in viscosity and increased solids contents of polymer polyols, a need for further improvement in viscosity reduction and increase in solids content has continued to exist. In particular, there is a need for technology in polymer polyols that maximizes viscosity reduction while also providing a viable mechanism to higher solids content, while enhancing the stability of the polymer polyols.
One way of enhancing stability of polymer polyols is by the presence of a minor amount of a graft or addition copolymer formed in situ from growing polymer chains and polyol molecules. Various approaches are known in the art. These typically incorporate small amounts of unsaturation into the polyol in addition to that inherently present in the polyoxyalkylene polyols typically used in forming polymer polyols. Various patents including U.S. Pat. Nos. 3,652,639, 3,823,201, and 3,850,861, British Patent 1,126,025 and Japanese Patent Nos. 52-005887 and 48-101494 utilize this approach. The use of "stabilizer precursors," also termed a "macromer" that contains a particular level of reactive unsaturation, is based on the expectation that during polymerization, in the preparation of the polymer polyol, adequate amounts of stabilizer will be formed by the addition polymerization of the precursor stabilizer with a growing polymer chain. U.S. Pat. Nos. 4,454,255, 4,458,038 and 4,460,715 describe the general concept of using stabilizer precursors in polymerization.
A pre-formed stabilizer (PFS) is known to be particularly useful for preparing a polymer polyol having a lower viscosity at high solids content. In the pre-formed stabilizer processes, a macromer is reacted with monomers to form a co-polymer composed of macromer and monomers. These co-polymers comprising a macromer and monomers are commonly referred to as pre-formed stabilizers (PFS). Reaction conditions may be controlled such that a portion of the co-polymer precipitates from solution to form a solid. Pre-formed stabilizers may be dispersions having low solids contents (e.g., 3 to 15% by weight). It is preferred that the reaction conditions under which pre-formed stabilizers are prepared are controlled so that the particle size is small, thereby enabling the particles to function as "seeds" in the polymer polyol reaction.
U.S. Pat. Nos. 5,196,476, 5,990,185, 6,013,731, 7,160,975 and 7,776,969 as well as EP 0786480 describe a variety of pre-formed stabilizer composition. In general, these are prepared by polymerizing a macromer and one or more ethylenically unsaturated monomers in the presence of a free-radical polymerization initiator and a liquid diluent in which the pre-formed stabilizer is essentially insoluble.
The novel polybutadiene modified polymer polyols of the present invention offer distinct advantages that are not available from the present commercially available polymer polyols. These include improved flammability in foams prepared from these novel polymer polyols, and lower VOCs (volatile organic compounds) present in the foams compared to the present commercially available polymer polyols. It was surprisingly found that these advantages could be realized in polymer polyols by substituting either a polybutadiene for a portion of the liquid base polyol (typically a polyether polyol) in the composition of the polymer filled polyol, or by using a preformed stabilizer that comprises a polybutadiene. This has not previously been disclosed or suggested.

Polybutadiene modified polymer polyols, foams prepared from polybutadiene modified polymer polyols, and processes for the production thereof


Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.

In computing devices, graphics processing units (GPUs) can supplement the central processing unit (CPU) by providing electronic circuitry that can perform mathematical operations rapidly. To do this, GPUs utilize extensive parallelism and many concurrent threads. The capabilities of GPUs make them useful to accelerate the processing of visual media and parallel computing tasks. For instance, a GPU can be used for video encoding/decoding, graphics rendering in two and three-dimensional games, and other general purpose computing applications. If the complexities involved in virtualizing GPUs can be overcome, virtualization technologies can be applied to graphics processing units on many different types of computing platforms.

Intelligent GPU scheduling in a virtualization environment


The present invention inhibits quenching of a laser following a radiation event by providing a radiation sensing arrangement connected to the discharge current control circuitry controlling the discharge current of the laser, for sensing a radiation event and for controlling the discharge current control circuitry in such a way that quenching of the laser for a predetermined amount of time after a radiation event is inhibited.

The present invention relates to the control of the discharge current along the laser paths of a ring laser gyro and, more particularly, to a system for inhibiting the quenching of the laser beams in a ring laser gyro after a radiation event.
Ring laser gyros are used, for example, in inertial navigation systems and typically comprise a quartz block having a closed loop lasing path formed therein. The lasing path is filled with a suitable gas and then the quartz block is sealed. At least a cathode and two anodes are provided on the block having electrodes in communication with the gas in order to supply a discharge current in the lasing path to excite the electrons of the gas atoms. As a result, the electrons are excited to different energy levels thereby emitting photons to produce the lasing effect. Typically, two counterpropagating laser beams are produced around the close loop path. The two laser beams interfere with one another such that an interferometer senses the interference pattern resulting from the interaction between the two laser beams As the ring laser gyro experiences rotation, the interference pattern shifts Sensors are provided to sense the shift in the interference pattern so that the inertial guidance system can detect movement of the structure supporting the ring laser gyro.
Discharge current controllers are usually provided in order to regulate the discharge current between the cathode and the anodes. When the ring laser gyro is subjected to an extremely large transient nuclear radiation event, the ionization of the gas within the ring laser gyro can increase dramatically. This increase in gas ionization results in a significant decrease in the voltage drop between the cathode and anodes resulting in a substantial increase in discharge current. The discharge current control circuitry usually recovers from the radiation event before the extra discharge path ionization dissipates. The discharge current control circuitry will, therefore, reduce the higher discharge current flow before the extra gas ionization dissipates. When the radiation-induced ionization finally does dissipate, the current control circuitry frequently is unable to track the resulting rapid increase in voltage across the ring laser gyro electrodes. Thus, subsequent to the event, the extra radiation-induced ionization collapses causing a rapid increase in the voltage and a rapid decrease in discharge current. The discharge current control circuitry cannot respond quickly enough in order to keep the discharge current at a level which will support lasing. Consequently, as the extra radiation-induced ionization collapses, there will be insufficient current flow along the laser paths of the ring laser gyro to support lasing and, as a result, the laser beams will be quenched.

System for inhibiting quenching of laser beams in response to radiation events


A digital enhanced cordless telecommunication (DECT) base station, the DECT base station may include a transmitter that is arranged to transmit, at different points of time, downlink transmitted DECT signals to another DECT device that differs from the DECT base station; a receiver that is arranged to receive from the other DECT device downlink reception information indicative of attributes of downlink received DECT signals that were received by the other DECT device as a result of the transmission of the downlink transmitted DECT signals; a processor that is arranged to process the downlink reception information to detect a motion that affects a reception of the downlink received DECT signals by the other device.

Much research was done on motion sensing that is based on blocking and reflection of radio waves. An object that is located somewhere along the propagation path of a radio signal may affect the overall propagation path of the signal, as it may attenuate, block, or reflect certain parts of the signal. In a multipath environment, a receiver that is tuned to receive the said radio signal receives the superposition of all signal paths—resulting in possible decay or intensification of the signal amplitude depending on the phase of each individual component. Those specific signal components that are affected by a given object may change their phases and amplitudes depending on the position of the object. By inspecting the changes in the received signal amplitude the receiver may be able to determine whether or not there is any object in motion in the close environment. Motion sensing that is based on radio signals consist of a radio transmitter that transmits a constant pattern, a radio receiver, and a processing unit.

Method and system for motion detection using digital enhanced cordless telecommunicaiton (DECT) signals


A gas seal for rotary shaft applications in which at least a portion of a contact surface of one member of the seal that has relative motion with and in contact with a second member of the seal is coated with a chromium carbide-age hardenable nickel base alloy. The process for depositing and heating the coating is also claimed.

Rotary contact seals are seals in which the rotating and stationary seal faces are kept in nominal contact. The seals have minimum fluid leakage but are limited in speed capability by frictional heat generation and wear problems at the interface between the faces. Rotary contact seals can be either circumferential seals, with a circumferential contact area between the internal diameter of a sealing ring and the shaft surface, or face seals with contact between the radial seal faces.
Generally, the basic face contact seal consists of two solid rings of material held in nominal contact along a radial face by an axial load. Usually one of its rings is a soft material such as a carbonaceous material, i.e., carbon and the other would be a hard material such as a metal or metal alloy; i.e., steel, tungsten carbide or silicon carbide. Which ring rotates and which is held stationary depends on the individual seal design and application, although it is more common for the hard ring to rotate. The rotating ring is usually mounted in a fixed position on a shaft, with the stator ring loaded so as to press axially against it. The axial load can be provided by springs, bellows, magnetic means or the like. Although contact seals have negligible leakage characteristics, they are subject to wear problems due to the frictional contact of the surfaces.
Copending U.S. patent application Ser. No. 07/599,482 filed Oct. 10, 1990 now U.S. Pat. No. 5,137,422, discloses an erosion resistant coating for turbo machine gas path components which comprises the thermal spray depositing of a chromium carbide and an age hardenable nickel base alloy onto the surface of the gas path components and then preferably heat treating the gas path component. This reference is incorporated herein as if it were recited in its entirety.
The chromium carbide base thermal spray coating family has been in use for many years to provide sliding and impact wear resistance at elevated temperatures. The most frequently used system by far is the chromium carbide plus nickel chromium composite. The nickel chromium (usually Ni -20 Cr) constituent of the coating has ranged from about 10 to about 35 weight percent. These coatings have been produced using all types of thermal spray processes including plasma spray deposition as well as detonation gun deposition. The powder used for thermal spray deposition is usually a simple mechanical blend of the two components. While the chromium carbide component of the powder is usually Cr.sub.3 C.sub.2, the as-deposited coatings typically contain a preponderance of Cr.sub.7 C.sub.3 along with lesser amounts of Cr.sub.3 C.sub.2 and Cr.sub.23 C.sub.6. The difference between the powder composition and the as-deposited coating is due to the oxidation of the Cr.sub.3 C.sub.2 with consequent loss of carbon. Oxidation may occur in detonation gun deposition as a result of oxygen or carbon dioxide in the detonation gases, while oxidation in plasma spraying occurs as a result of inspiration of air into the plasma stream. Those coatings with a relatively high volume fraction of the metallic component have been used for self-mating wear resistance in gas turbine components at elevated temperatures. These coatings, because of the high metallic content, have good impact as well as fretting wear and oxidation resistance. At lower temperatures, coatings with nominally 20 weight percent nickel-chromium have been used for wear against carbon and carbon graphite in mechanical seals, and for wear in general in adhesive and abrasive applications. These coatings are most frequently produced by thermal spraying. In this family of coating processes, the coating material, usually in the form of powder, is heated to near its melting point, accelerated to a high velocity, and impinged upon the surface to be coated. The particles strike the surface and flow laterally to form thin lenticular particles, frequently called splats, which randomly interleaf and overlap to form the coating. The family of thermal spray coatings includes detonation gun deposition, oxy-fuel flame spraying, high velocity oxy-fuel deposition, and plasma spray.
It is an object of the present invention to provide a coating having excellent contact wear resistance for a contact surface of a face contact fluid seal.
It is another object of the present invention to provide a face contact fluid seal in which one of the contacting surfaces is coated with a chromium carbide-age hardenable nickel base alloy coating that has excellent contact wear characteristics.
It is another object of the present invention to provide a method for coating a contact surface of a face contact fluid seal with a chromium carbide-age hardenable nickel base alloy coating.
The foregoing and additional objects will become more apparent from the description and disclosure hereinafter set forth.

Rotary seal member coated with a chromium carbide-age hardenable nickel base alloy


A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.

1. Field of the Invention
This invention is related to the field of distributed simulation systems.
2. Description of the Related Art
Generally, the development of components for an electronic system such as a computer system includes simulation of models of the components. In the simulation, the specified functions of each component may be tested and, when incorrect operation (a bug) is detected, the model of the component may be changed to generate correct operation. Once simulation testing is complete, the model may be fabricated to produce the corresponding component. Since many of the bugs may have been detected in simulation, the component may be more likely to operate as specified and the number of revisions to hardware may be reduced. The models are frequently described in a hardware description language (HDL) such as Verilog, VHDL, etc. The HDL model may be simulated in a simulator designed for the HDL, and may also be synthesized, in some cases, to produce a netlist and ultimately a mask set for fabricating an integrated circuit.
Originally, simulations of electronic systems were performed on a single computing system. However, as the electronic systems (and the components forming systems) have grown larger and more complex, single-system simulation has become less desirable. The speed of the simulation (in cycles of the electronic system per second) may be reduced due to the larger number of gates in the model which require evaluation. Additionally, the speed may be reduced as the size of the electronic system model and the computer code to perform the simulation may exceed the memory capacity of the single system. As the speed of the simulation decreases, simulation throughput is reduced.
To address some of these issues, distributed simulation has become more common. Generally, a distributed simulation system includes two or more computer systems simulating portions of the electronic system in parallel. Each computer system must communicate with other computer systems simulating portions of the electronic system to which the portion being simulated on that computer system communicates, to pass signal values of the signals which communicate between the portions. Generally, distributed simulation systems sample output signals from the model in each node and communicate the corresponding signal states to other nodes. The received signal states are then driven as inputs to the models in those other nodes.
In such a simulation, skew may be experienced for some signals (as compared to the signals produced by the corresponding hardware). For example, signals which are asynchronous may change state at any time. A first node in the distributed simulation system may simulate a first model which drives a first output signal. The first output signal may be an input signal to a second model in a second node. The input signal to the second model may asynchronously cause a second output signal of the second model to change state during the same simulation timestep as the input signal is received. However, the second output signal is actually sampled in the next simulation time step (and thus the second output signal may affect receiving nodes in the next simulation time step). In contrast, in a single simulation image, the second output signal may affect receiving models in the same simulation timestep.
A glitch may be experienced for bi-directional signals (signals which may act as both inputs and outputs at different times). The bi-directional signal drivers may be located in different nodes, and thus the simulator in a given node may not have the states for all the drivers on a given bi-directional signal. Accordingly, resolving the value on the bi-directional signal line at a given time step may involve multiple nodes. Typically, the value on the bi-directional line from each node is transmitted to a central point, which resolves the value for the bi-directional line and transmits the resolved value to each of the nodes. However, simulator time progresses in each node while the central point is resolving the state, and the value on the bi-directional signal line in each node may be the value driven by the local model in that node until the central point returns the resolved value.
Test monitor code or test stimulation code is often used in distributed simulation systems. Frequently, such code may sample or change the values of various signals (or internal facilities such as registers) to determine if a simulation is operating properly or to cause a desired test event to occur. Such sampling and changing of values may also cause skew in the simulation. For example, reading a register may involve placing a value on the inputs of the model including the register. The input values are values which cause the model to output the register's contents. Simulator time may then advance by one or more timesteps to receive the register result.

Distributed simulation system having phases of a timestep


Provided is a process for preparing a bismuth compound at a heat treatment temperature lower than conventional. A bismuth compound is prepared by the steps of heating under vacuum to form a reduced phase and heating under oxidizing environment of normal or lower pressure.

1. Field of the Invention
The present invention relates to a process for preparing bismuth compounds useful for use in electronic devices such as ferroelectric memories.
2. Description of the Related Art
Bismuth compounds, in particular bismuth layer compounds, are a class of compounds which are industrially very important in bismuth superconductive oxides having a critical temperature of 110K, materials for ferroelectric memories or the like. In order to apply these compounds to electronic devices, a process for forming thin films must be developed.
For these bismuth layer compounds, for example, Bi.sub.2 (Sr,Ba,Ca)(Ta,Nb).sub.2 O.sub.9, a temperature for heat treatment in a process for preparing a bulk is 1,000.degree. C. or higher (see G. A. SMOLENSKII et al., SOVIET PHYSICS-SOLID STATE, p.651-655 (1961)) while a temperature for post annealing in a process for preparing a thin film is about 800.degree. C. (see C. A. Paz de Araujo et al., International Patent Publication #W093/12542 (Jun. 24, 1993)).
The above mentioned high heat treatment temperature may cause various problems with respect to semiconductor processes.
In capacitors using a bismuth layer compound, for instance, hillock (i.e., growth of coarse particles) may be caused in a platinum lower electrode which becomes one of electrodes of a capacitor, or a buffer layer which is formed between the platinum lower electrode and an electrode-forming surface thereof may deteriorate in the heat treatment due to a problem of its heat resistance.
When titanium nitride TiN is used as a buffer layer, for instance, the annealing temperature should be decreased to 700.degree. C. at the highest, preferably to about 650.degree. C. or lower.
Illustrative methods for decreasing the annealing temperature include development of a new starting material or film-formation as deposited, i.e., in the state of a film as simply formed by a ultra-high vacuum process such as MOMBE (metal organic molecular beam epitaxy; CBE). At present, however, these methods could not have crystallized oxides such as bismuth layer compounds.


The present invention discloses systems and methods for a smart card including: a first card having a device; and a second card having an aperture that is configured to allow a device to be inserted into an aperture when the second card is properly aligned with the first card, thereby allowing a device to protrude into an aperture. Optionally, the first card includes an aperture, and the second card includes a device, so that an aperture of the first card accommodates a device of the second card when the first card is properly aligned with the second card. Optionally, the apertures and the devices are configured to allow a stack of a plurality of the first and second cards to be densely packed Optionally, a card includes a magnetic stripe, an electronic circuit, and/or an embedded electrically-conductive wire for operationally connecting a device to a connector.

The present invention relates to systems and methods for a smart card with embedded electronic circuitry, and for reducing the thickness of a stack of smart cards that contain discrete devices
Smart cards are well-known in the art of information security as inexpensive, portable devices for storing and transporting secure information. The electronic circuitry, which is embedded in such a card and functions as a data-storage device, has a finite thickness. This thickness of the circuitry is determined by the technology used. The circuitry is typically a few hundred microns thick Clearly, the thickness of the card must be slightly more than the thickness of the embedded circuitry.
When a user has to carry only a small number of cards, the thickness of each card is not particularly important in terms of the volume that the cards occupy in his/her wallet. However, as the cost of the electronics decreases and the storage capacity increases, the ability and need to stack a larger number of cards in one pile becomes more of a problem because the cards occupy more wallet space
A U.S. patent application Ser. No. 11/444,385 of Raz Dan, filed on Jun. 1, 2006, and assigned to the assignee of the present invention, entitled "A Business Card Comprising a Digital Memory" teaches a standard-size business card that contains a USB Flash Drive (UFD). Such a card enables a user to carry tens of cards; for example, for handing out in a conference or in a meeting. In such a scenario, the thickness of the card increases the volume of the stack, and limits the number of cards that can be carried comfortably.
It would be desirable if the total thickness of a stack of cards, having embedded electronic circuitry, could be significantly less than the sum of the thicknesses of the individual cards.


Computerized methods and systems for generating a suggested query list with suggested search terms displayed as highlighted text utilizing a user-defined query are provided. Query search terms are received by a user-interface display. Upon inputting query search terms, the user-interface automatically generates a suggested query list. The suggested query list is associated with the query search term and the suggested query list is comprised of at least one suggested search term. A query suggestion architecture determines if the query search term and the suggested search term are a match, and if so, highlights the suggested search term that is not a match. The user interface displays the highlighted terms to assist in refining a search. The present invention further provides a stemming algorithm that extracts the root form of the query search term.

In hypermedia systems preceding the Web, and on the Web since its inception, users have employed a variety of tools to aid in navigating available information. For example, users often utilize search engines specifically designed for information retrieval. Additionally, more advanced search engines assist Web searching by providing features related to distinguishing terms returned on the search results page. One class of features is hit-highlighting. The hit-highlighting feature will "highlight" terms within the documents returned by the search engine that match the initial search query terms. Highlighting typically sets apart the search query terms in bolded text such that the user may easily determine where the search query was matched.
The hit-highlighting feature can facilitate a search procedure by allowing users, who desire to identify terms in titles of documents, to quickly locate the matched search query terms. However, the present method of hit-highlighting does not produce or display related search terms that may be suggested by the search engine server. In addition, providing highlighting to displayed terms similar to initial search query terms precludes the rapid navigation of the related search terms when refining the initial search query criteria. Accordingly, standard hit-highlighting has been limiting to Web users.
Therefore, there is a need in the art for computerized methods and systems for attaining related search terms, as suggested by a search engine, which incorporate the hit-highlighting feature. Further, there is a need to provide a method for easily navigating related search terms, thus, allowing a user to focus on a broad initial search query.

Support for reverse and stemmed hit-highlighting


An apparatus and method for modifying RFID tag data in a portable terminal are provided. The method includes determining whether a UID of the RFID reader is received; when the UID of the RFID reader is received, determining whether RFID tag data corresponding to the received UID exists in an RFID data management database; and when the RFID tag data corresponding to the received UID data exists in the RFID data management database, recording the corresponding data in the RFID tag and transmitting the recorded data. The data recorded in the RFID tag can be dynamically modified according to the RFID readers that are located near the portable terminal and collect the RFID tag data.

1. Field of the Invention
The present invention relates generally to an apparatus and method for modifying a Radio Frequency Identification (RFID) tag data in a portable terminal, and in particular, to an apparatus and method for dynamically modifying RFID tag data using an RFID reader in a portable terminal.
2. Description of the Related Art
RFID tags, called smart tags, are one of automatic identification technologies using an ultraminiature chip that is built in a card and can store up to 6000 times more data than barcodes. Functions of RFID tags are similar to those of barcodes.
However, RFID tags can be identified simultaneously at a long distance. Because of these advantages, RFID tags are widely used in various fields such as product information management systems and Global Positioning Systems (GPSs).
Specifically, RFID tags are widely used in identification systems, such as entry authorization systems and locking systems, which operate specific devices. For example, in the case of an RFID-based electronic locking system, an electronic key and an electronic lock have an RFID tag and an RFID reader, respectively. When the electronic key and the electronic lock are matched with each other, the electronic lock is operated through the authentication of an electronic key data contained in the RFID tag.
As described above, the identification system with the RFID reader is operated using the data recorded in the RFID tag (also referred to as RFID tag data). However, because the RFID tag records data for one RFID reader, the user has to modify the RFID tag data so as to allow another RFID reader to operate with that RFID tag.

Apparatus and method for modifying RFID tag data in portable terminal


An optical tape including an optical recording layer for permitting information to be optically recorded thereon and a light-reflective magnetic layer. The light-reflective magnetic layer which reflects light projected onto the recording layer, also permits magnetic recording or magneto-optical recording to be performed thereon, thereby increasing a storage capacity of the optical tape remarkably. Further, the optical tape is provided with a layer to form guiding grooves for tracking control. The layer to form guiding grooves is made up of ultraviolet-hardening resin, photo-resist, or a photochromic material. For example, in the case of using ultraviolet-hardening resin, after a guiding groove pattern has been exposed by projecting an ultraviolet ray on a layer made up of ultraviolet-hardening resin, the exposed areas harden to form areas corresponding to guiding grooves between those exposed areas. The guiding grooves are formed by removing the areas corresponding to guiding grooves from the layer made up of the ultraviolet-hardening resin. Additionally, along with a guiding groove pattern, an index pattern can also be exposed. The guiding grooves thus formed do not reduce the recording density for information of the optical tape.

Conventionally, various optical disks for providing optical recording and/or reproduction such as those of read-only type, that is, so-called compact disks and the like, of DRAW type capable of writing desired information only once and of rewritable type have been known. Among those optical disks, in those of the type such as read-only type, which record information by the use of pits physically provided thereon, so-called tracking control is performed by directing a light beam onto the center of a pit row. On the other hand, in magneto-optical disks and the like which record information without using such pits physically recorded, tracking control is provided, in general, by installing guiding grooves with a rectangular shape in their cross-section, indicating a recording path of information, preliminary formed on a substrate.
In those optical disks described above, detection of information is performed based on a reproduced light transmitted through a recording layer or on a reflected light obtained by allowing a reproduced light transmitted through a recording layer to reflect from a reflective layer properly disposed. For example, a metal film made of Al or the like is employed as the reflective layer in a magneto-optical disk where reflection-type detection is performed.
In the mean time, recently studies on optical cards and so-called optical tapes have been carried out to provide an optical memory medium other than optical disks. In those optical cards and optical tapes, recording and/or reproduction is performed by utilizing the same principle as the optical disks. For example, an optical tape is basically composed of an elongated film substrate, an optical recording layer provided on the film substrate, on which recording of information is performed by utilizing the magneto-optical effect, photochromism, etc. and a protective layer for protecting the optical recording layer.
For those optical tapes, the following arrangement is suggested as in the case of magnetic tapes for VTR (Video Tape Recorder): an optical tape is stored in a cassette case; a portion thereof is taken out from the cassette case to be brought into an operative position for recording or reproduction; tracks as paths for information recording are predeterminately set in a direction slanting to the longitudinal direction of the optical tape so as to permit recording and/or reproduction.
Meanwhile, in those optical tapes, since a substrate thereof is generally thin as well as flexible, it is extremely difficult to form on the substrate guiding grooves for providing tracking control. Hence, a method for providing tracking control for optical tapes is disclosed, for example, in Japanese Patent Laid-Open Publication No. 63-117326 (117326/1988).
The system described therein provides straight guiding patterns which are optically recorded on a recording layer prior to recording operation, being predeterminately disposed in positions parallel to and adjacent to actual tracks, and performs recording and reproduction in parallel with the guiding patterns while reproducing the guiding patterns.
In the mean time, the above-mentioned optical recording medium generally enables high recording density for information, and therefore has a comparatively large storage capacity, yet it is desired to further increase the storage capacity with the thought of using the medium for long-time recording of music information and video information or enabling, for example, double recording etc. of information in order to prevent losing of information due to external causes.
However, for the above-mentioned method, it is necessary to additionally install a light source for recording the guiding patterns, another light source for reproducing the guiding patterns, a photodetector and so on in addition to a light source, a photodetector, etc for recording or reproducing information on or from the optical tape. Therefore, the arrangement presents problems that the number of parts of optical head for optical tapes is increased, the cost becomes high, and the recording density of information is lowered due to the fact that the guiding patterns are recorded on the recording layer in addition to information.

Optical recording medium and manufacturing method thereof


An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.

1. Technical Field
The present invention generally relates to semiconductor devices and fabrication of semiconductor devices. More particularly, the present invention relates to the reducing or eliminating delamination of a metal gate of a FinFET device.
2. Background Information
The two principal approaches for forming semiconductor device gate structures have been gate-first and gate-last process approaches.
In a gate-first fabrication approach, a metal gate is provided over a gate dielectric, and then patterned and etched to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided. In the gate-last approach, a sacrificial (or dummy) gate material is provided, patterned and etched to define one or more sacrificial gates. The one or more sacrificial gates are subsequently replaced with corresponding replacement metal gates, after source and drain features of the devices have been formed. The sacrificial gate material, such as, for example, amorphous silicon (a-Si) or polycrystalline silicon, holds the position for the subsequent metal gate to be formed. For instance, an amorphous silicon (a-Si) or polysilicon sacrificial gate material may be patterned and used during initial processing until high-temperature annealing to activate the source and drain features has been completed. Subsequently, the a-Si or polysilicon may be removed and replaced with the final metal gate.
Low resistance metal gate materials, such as tungsten, are currently employed due to advantages associated such as reduced gate contact resistance, which provide faster device performance. However, the poor adhesion between the layers during fabrication of the metal gate can have negative consequences, such as bubbling, blistering, peeling and/or delamination at the interface between the layers. Bubbling, blistering or peeling degrades the electrical contact between the layers resulting in low yield and low reliability in devices. The susceptibility of a device to the negative effects of poor adhesion between layers increases as the area of contact between poorly adhering layers increases.
Hence, there is a need to reduce or eliminate delamination of a metal gate of a FinFET device.

FinFET gate with insulated vias and method of making same


One embodiment of the invention provides for receiving a call from a caller, the call being associated with a first merchant; placing the call in a queue; determining a second merchant; and establishing a connection, the connection enabling communication between the caller and the second merchant while the call is in the queue.

Telephone-based customer service plays an increasingly important role for organizations involved in activities requiring direct communication with customers. In order to serve a maximum number of callers, call centers are typically designed to optimize call handling efficiency and telephone attendant productivity. Many conventional systems allow telephone attendants to service a greater number of callers by ascertaining the nature of a caller's request through collection, by a live attendant, of initial information from the caller, and transferring the call to a voice response unit to address the specific request of the caller. Other systems reverse the answer and collection process by connecting the caller initially to a voice response unit that collects information on the nature of a caller's request. The information is ultimately used to route the call to an appropriate attendant.
An Automatic Call Distributor (ACD) is commonly utilized by call centers to enhance attendant productivity. An ACD allows a call center to handle a large number of calls cost-effectively by placing some of the calls in a queue when no attendants are available. When a call is placed in the queue, a greeting message is typically played to the caller, identifying the called party and indicating that the next available attendant will service the call.
Call queuing plays an important role in call center operations and provides many advantages to the call center, including: increased attendant productivity, by minimizing idle time for the attendant; simultaneous handling of a greater number of calls during an increase in calls; and encouragement of callers to wait for an available attendant, as opposed to requiring the caller to attempt another call in response to a busy signal. Call queuing, however, is perceived by customers to be a waste of their time, and may result in frustration, abandoned calls, a loss of business, and poor customer satisfaction when the holding time is deemed excessive.
Thus, in order to entertain callers waiting in a call queue, many call centers play music, news, weather or advertising messages to the caller during the holding period. In this manner, the caller may be entertained or informed of sales promotions for particular products or services. For example, U.S. Pat. No. 5,444,774 to Friedes discloses an Interactive Queuing System For Call Centers and suggests that music or advertising messages may be played to a caller on hold.
Unfortunately, such conventional call queuing entertainment systems have experienced only marginal success in satisfying callers placed in a queue. Since most callers can already access such conventional and freely available programming sources directly from their home, such programming is generally not a sufficient novelty or value to the caller, nor does it allow the caller to make effective use of the holding time, nor does it generally minimize the frustration experienced by the caller as a result of an excessive hold time. Conventional systems for entertaining callers placed on hold by a call center also do not permit a caller to select a desired entertainment option.

Method and apparatus for entertaining callers in a queue


A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p−-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

1. Field of Invention
The invention relates to a semiconductor device. More particularly, the invention relates to an insulated gate semiconductor device with low on-resistance, used for a high breakdown voltage IC to control a large current, such as an IC for a switching power source. The invention also relates to an IC for driving an automotive power system and to an IC for a plasma display panel driver.
2. Prior Art
In recent years, with the rapid spread of portable information appliances and the development of information technology, power ICs containing power MOSFETs are becoming more important. As for a power IC with a lateral power MOSFET and a control circuit thereof being integrated together, expectations are placed on downsizing, lowered power consumption, increased reliability and reduced cost. This is in contrast to a previous arrangement of a combination of a discrete power MOSFET with control and driving circuits. Thus, on the basis of CMOS processes, efforts are being actively carried out to develop high performance lateral power MOSFETs.
Recently, development activity has occurred regarding a trench lateral power MOSFET (hereinafter referred to as "TLPM"), because of its possibilities of further lowering on-resistance and of further increasing a packing density when being integrated into a power IC. Such improvements would be in comparison to on-resistance and packing densities in previous planar type lateral power MOSFETs. The TLPM may be classified into a type that provides a drain contact at a bottom of a trench (hereinafter referred to as "TLPM/D") and a type that provides a source contact at the bottom of the trench (hereinafter referred to as "TLPM/S") (see the Japanese patent publication JP-A-2002-353447, A. Sugi et al., "A 30V Class Extremely Low On-resistance Meshed Trench Lateral Power MOSFET," IEEE IEDM, (US), 2002, Technical Digest, pp. 297–300, and N. Fujishima and 5 others, "A Low On-resistance Trench Lateral Power MOSFET in a 0.6 μm Smart Power Technology for 20–30V Applications," IEEE IEDM, (US), 2002, Technical Digest, pp. 455–458).
Explanations will be made of a previous TLPM/D and a previous TLPM/S. FIG. 36 is a cross-sectional view showing an arrangement of the previous TLPM/D. As shown in FIG. 36, in a p−-semiconductor substrate 1, a trench 2 is formed. The trench 2 is filled with a gate insulator film 3, a gate electrode 4, an interlayer insulator film 5 and a buried electrode 6, which are provided from the sidewall of the trench 2 toward the center thereof in the order stated. In the lower half section of the trench 2, an insulator film 7 that is thicker than the gate insulator film 3 is provided for ensuring a withstand voltage.
The lower half section of the trench 2 is surrounded by an n−-extended drain region 8. Under the bottom of the trench 2 in the n−-extended drain region 8, an n+-drain region 9 is provided. The buried electrode 6 is electrically connected to the n+-drain region 9 at the bottom of the trench 2. Outside of the upper half section of the trench 2 is a p-base region 10.
Close outside the trench 2, in the upper section of the p-base region 10, an n+-source region 11 is provided. In the upper section of the p-base region 10, a p+-plug region 12 is provided. To the top end of the buried electrode 6, a drain electrode 13 is electrically connected. A source electrode 14 penetrates through an interlayer insulator film 15 so as to electrically connect to both the n+-source region 11 and the p+-plug region 12 on the surface of the substrate 1.
FIG. 37 is a cross-sectional view showing an arrangement of the previous TLPM/S. As shown in FIG. 37, a trench 2, formed in a p−semiconductor substrate 1, is filled with a gate insulator film 3, a gate electrode 4, an interlayer insulator film 5 and a buried electrode 6, which are provided from the sidewall of the trench 2 toward the center thereof in the order stated. Close outside the upper half section of the trench 2, an insulator film 7 that is thicker than the gate insulator film 3 is provided for ensuring a withstand voltage.
The lower half section of the trench 2 is surrounded by a p-base region 10. Under the bottom of the trench 2 in the p-base region 10, an n+-source region 11 is provided. The buried electrode 6 is electrically connected to the n+-source region 11 at the bottom of the trench 2. Outside the upper half section of the trench 2 is an n−-extended drain region 8.
In the n−-extended drain region 8, an n+-drain region 9 is provided. A drain electrode 13, penetrating through an interlayer insulator film 15 and an interlayer insulator film 16 on the film 15, is electrically connected to the n+-drain region 9 on the surface of the substrate 1. A source electrode 14, penetrating through the interlayer insulator film 16, is electrically connected to the top end of the buried electrode 6.
In a MOSFET, lower on-resistance per unit area generally is desirable. A channel width per unit area (hereinafter referred to as a channel density) is an important parameter for determining the on-resistance per unit area and is inversely proportional to the device pitch of the MOSFET. In either of the TLPM's shown in FIGS. 36 and 37, a transistor is formed on the sidewall of the trench 2, which brings the device pitch to on the order of half that of a previous planar power MOSFET. Therefore, in the TLPM, the channel density becomes about twice as great as that of the previous planar power MOSFET, thereby to reduce the on-resistance by half.
A MOSFET, however, is a monopolar device that is operated by majority carriers. A current flows only on the surface of the device. Therefore, reduction in the on-resistance per unit area still has possibilities for improvement. Moreover, when the MOSFETs are mounted in a power IC, the elements are to be isolated from one another by the junction isolation technique. Therefore, integration of the TLPM and a CMOS device for controlling the TLPM has a possibility of causing latchup due to interaction between transistors.
Therefore, an arrangement is proposed in which an insulated gate bipolar transistor (hereinafter referred to as an IGBT) is used instead of the MOSFET to isolate the elements from one another by a dielectric isolation technique. An IGBT, being a bipolar device, has an advantage of allowing on-resistance to be lowered by applying conduction modulation. The applicant has previously filed an application for a patent concerning a planar lateral IGBT to which SOI (Silicon-on-insulator) technology is applied (see Japanese patent publication JP-A-6-151576, for example).
FIG. 38 is a cross-sectional view showing an arrangement of a previous planar lateral IGBT. As shown in FIG. 38, an n-single-crystal silicon semiconductor layer 21 is layered on an oxide film 23 provided on the surface of a supporting substrate 22. In the silicon semiconductor layer 21, an element-forming region 24 is formed like an island while being isolated by a trench isolation region 25. The trench isolation region 25 is formed by an isolation trench 26 penetrating through the silicon semiconductor layer 21 to reach the oxide film 23, a dielectric film 27 provided on the inside face of the isolation trench 26 and polysilicon 28 filling the inside of the dielectric film 27.
In the element-forming region 24, on the surface layer of the silicon semiconductor 21, an n−-drift region 29 is provided. In the n−-drift region 29, a p+-collector region 30 is provided. Moreover, in the element-forming region 24, on the surface layer of the silicon semiconductor 21, a p-base region 31 is provided apart from the n+-drift region 29. In the p-base region 31, an n+-emitter region 32 and a p+-base region 33 are provided.
On the surface of the silicon semiconductor layer 21 between the n+-emitter region 32 and the n−-drift region 29, a gate electrode 35 is provided, with a gate insulator film 34 thereunder. To the p+-collector region 30, a collector electrode 36 is electrically connected. To both of the n+-emitter region 32 and the p+-base region 33, an emitter electrode 37 is electrically connected.
The on-resistance of the planar lateral IGBT shown in FIG. 38, being brought to one fourth that of a planar lateral MOSFET of the same device size, is to be reduced to a half the on-resistance of the TLPM shown in FIG. 36 or FIG. 37. Moreover, an SOI (silicon on insulator) structure, by which the supporting substrate 22 and elements are isolated, can prevent a substrate current. This makes it possible to reduce switching losses and to enhance an operation speed. Furthermore, the introduction of the dielectric isolation technique can eliminate interaction between the IGBT and transistors when IGBTs, or an IGBT and a CMOS, are integrated with each other. This makes it possible to eliminate latchup due to a parasitic thyristor.
In the previous planar lateral IGBT, however, the drift region, being formed laterally, namely, in the direction perpendicular to that of the device thickness, must be extended laterally for enhancing the breakdown voltage. This prevents the IGBT from being highly integrated. Moreover, there also arises a problem that the laterally extended drift region causes an increase in the device pitch, which in turn results in an increase in on-resistance.
Objects and Summary of the Invention
The invention was made in view of the above problems with an object of providing a semiconductor device provided with a trench lateral IGBT (hereinafter referred to as a TL-IGBT) having a small device pitch by which the IGBT can be highly integrated. Moreover, it is also an object of the invention to eliminate the substrate current of the TL-IGBT in a semiconductor device provided with the TL-IGBT, to enable realization of a reduction in switching losses and a high operation speed.
A further object of the invention to reduce on-resistance in the semiconductor device provided with the TL-IGBT to be less than those in a TLPM and a planar lateral IGBT. In addition, it is an object of the invention to prevent latchup in a semiconductor device in which the TL-IGBTs are integrated together, or to prevent malfunctions due to interaction between transistors in a semiconductor device in which the TL-IGBT and elements such as CMOS devices are integrated together.
In order to achieve the above objectives, a semiconductor device according to a first embodiment of the invention includes a collector region of a first conductivity type provided on the underside of a bottom of a trench formed in a semiconductor layer. An emitter region of a second conductivity type is provided on the outside of the trench in a surface layer of the semiconductor layer. A base region of the first conductivity type is provided between the emitter region and the collector region. Adrift region of the second conductivity type is provided between the base region and the collector region. A gate insulator film is provided on the inside of the trench. A gate electrode is provided on the inside of the gate insulator film. An interlayer insulator film is provided on the inside of the gate electrode. A buried electrode is provided on the inside of the interlayer insulator film and electrically connected to the collector region at the bottom of the trench. A collector electrode is electrically connected to the buried electrode. An emitter electrode is electrically connected to both of the emitter region and the base region.
In the this embodiment, the semiconductor device may have an arrangement further including an insulator film thicker than the gate insulator film in a lower half section of the trench. Alternatively, it may have an arrangement that including a buffer region of the second conductivity type surrounding the collector region. The semiconductor device may be formed in an element-forming region isolated from surroundings by a trench isolation region in which a conductive material fills an isolation trench with an insulator film provided at the trench boundary, the isolation trench penetrating through the semiconductor layer. The semiconductor layer may be made of a silicon semiconductor layered on an insulation layer.
The semiconductor device according to the first embodiment is provided with a TL-IGBT having a gate electrode in the trench formed in the semiconductor substrate, and having a current path near the sidewall or the bottom of the trench. Further, in the semiconductor device according to this embodiment, the TL-IGBT is formed on an SOI substrate.
Also to achieve the above objectives, a semiconductor device according to a second embodiment includes an emitter region of a second conductivity type provided on the underside of a bottom of a trench formed in a semiconductor layer. A collector region of a first conductivity type is provided on the outside of the trench in a surface layer of the semiconductor layer. Abase region of the first conductivity type is provided between the emitter region and the collector region. A drift region of the second conductivity type is provided between the base region and the collector region. A gate insulator film is provided on the inside of the trench. A gate electrode is provided on the inside of the gate insulator film. An interlayer insulator film is provided on the inside of the gate electrode. A buried electrode, provided on the inside of the interlayer insulator film, is electrically connected to the emitter region at the bottom of the trench. An emitter electrode is electrically connected to the buried electrode. A collector electrode is electrically connected to the collector region.
In the second embodiment, the semiconductor device may have an arrangement that also includes an insulator film thicker than the gate insulator film in an upper half section of the trench, and/or it may have an arrangement that includes a buffer region of the second conductivity type surrounding the collector region. Moreover, the semiconductor device may be formed in an element-forming region isolated from its surroundings by a trench isolation region in which a conductive material fills an isolation trench with an insulator film provided between the conductive material and the surroundings. The isolation trench penetrates through the semiconductor layer. The semiconductor layer may be made of a silicon semiconductor layered on an insulation layer.
More specifically according to the second embodiment, a semiconductor device is obtained which is provided with the TL-IGBT having the gate electrode in the trench formed in the semiconductor substrate, and having a current path near the sidewall or the bottom of the trench. Further, a semiconductor device is obtained in which the TL-IGBT is formed on an SOI substrate.
Moreover, in order to achieve the above objectives, the semiconductor device according to a third embodiment has a silicon semiconductor layer layered on an insulation layer, with the silicon layer being divided into a plurality of element-forming regions. The element-forming regions are isolated from each other by dielectric isolation with a trench isolation region in which a conductive material fills an isolation trench with an insulator film. The isolation trench penetrates through the semiconductor layer. In a first of the element-forming regions, the semiconductor device according to the first embodiment is formed. In a second of the element-forming regions, the semiconductor device according to the first embodiment with a conductivity type different from that of the semiconductor device formed in the first element-forming region is formed. Alternatively, a semiconductor device according to the first embodiment and a semiconductor device according to the second embodiment may be formed, respectively, in the first element-forming region and the second element-forming region, which are isolated from each other by dielectric isolation. As another alternative, the respective semiconductor devices formed in the first element-forming region and the second element-forming region may be the semiconductor devices according to the second embodiment, with conductivity types being different from each other.
More specifically according to the third embodiment, a semiconductor device is obtained with an arrangement in which the TL-IGBTs are integrated together, with each being isolated from others by a dielectric isolation technique.
Furthermore, in order to achieve the above objectives, according to the semiconductor device of a fourth embodiment, a silicon semiconductor layer layered on an insulation layer is divided into a plurality of element-forming regions isolated from each other by dielectric isolation with a trench isolation region in which a conductive material fills an isolation trench, with an insulator film provided at the trench boundary, the isolation trench penetrating through the semiconductor layer. In a first of a plurality of the element-forming regions, the semiconductor device according to the first or the second embodiment is formed, and in a second of the element-forming regions, one or both of a planar p-channel MOSFET and a planar n-channel MOSFET are formed for controlling the semiconductor device formed in the first element-forming region. In the fourth embodiment, the p-channel MOSFET and the n-channel MOSFET may be formed in their respective different element-forming regions, isolated from each other by dielectric isolation. Also, according to the fourth embodiment, a semiconductor device is obtained with an arrangement in which the TL-IGBT and CMOS devices are integrated together with each being isolated from others by dielectric isolation.


Provided herein is a thermoelectric element that includes a cold end, a hot end, and a p-type or n-type material having a length between the hot end and the cold end. The p-type or n-type material has an intrinsic Seebeck coefficient (S), an electrical resistivity (ρ), and a thermal conductivity (λ). Each of two or more of S, ρ, and λ generally increases along the length from the cold end to the hot end. The thermoelectric element may be provided in single-stage thermoelectric devices providing enhanced maximum temperature differences. The single-stage thermoelectric devices maybe combined with one another to provide multi-stage thermoelectric devices with even further enhanced maximum temperature differences.

A material with distributed transport properties (DTP) has varying properties (Seebeck coefficient, electrical resistivity, and thermal conductivity) at different spatial locations within the material at the same temperature. This concept has also been described as functionally graded material. First described as a material utilizing the distributed Peltier effect by Reich et al.'s patent application, filed in 1966 and issued as U.S. Pat. No. 3,564,860 in 1971, claimed a material "having differing thermoelectric properties along the spatial extent thereof between said hot junction and said cold junction" and further states that the absolute value of the Seebeck coefficient at the cold junction is "significantly less than the absolute value of the Seebeck coefficient of material at said hot junction."
Buist described an approach as the extrinsic Thomson effect in "The Extrinsic Thomson Effect (ETE)," International Conference on Thermoelectrics (Cardiff, Wales, 1991). In this paper, he describes test results for a three stage device with up to 20% gain in maximum temperature difference. The group of Walczak, Seifert, and Muller conducted modelling studies achieving a maximum temperature difference of 10-20% using what they called the functionally graded material (FGM) effect as described in "Modeling of segmented Peltier cooling with discrete and continuous concentration function," Materials Science Forum 492-493: 507-516 (2005) and "Optimization strategies for segmented Peltier coolers," Physica Status Solidi (a) 203(8): 2128-2141 (2006). They claimed that no substantial improvement can be achieved with greater than five stages. Korzhuev and Nikhesina also described the effect that creates improvement by " . . . 20% and more" in "Efficiency of low-grade heat recovery using various thermoelectric converters," Journal of Thermoelectricity No. 1, 4: 63-70 (2011). Kaliazin et al. studied FGM stating that "real coefficient of performance can indeed be significantly different from that given by Ioffe formula, particularly in the regime of maximum temperature" in "Rigorous calculations related to functionally graded and segmented thermoelectrics," International Conference on Thermoelectrics (2001). Semeniouk et al. described fabrication of a device with distributed properties in two segments by the Czochralski method, achieving a maximum temperature difference of 83K for a single stage device in "Single stage thermoelectric coolers with temperature difference of 80K," International Conference on Thermoelectrics (St. Petersburg, Russia, 1995). Bian and Shakouri described that "cooling enhancement is attributed to the redistribution of the Joule heating and Peltier cooling profiles" in "Beating the maximum cooling limit with graded thermoelectric materials," Applied Physics Letters 89: 212101-1 to -3 (2006). They concluded that "more than twice maximum cooling temperature of the uniform material with the same ZT can be achieved".
Anatychuk and Vikhor described different methods to produce functionally graded materials, including by pressing, extrusion, zone melting, and the Czochralski method in "Functionally graded materials and new prospects for thermoelectricity use," International Conference on Thermoelectrics (1997). Kuznetsov further described making functionally graded materials using the Bridgeman method, Czochralski technique, plasma spray method, diffusion of a dopant from a gaseous phase, zone leveling technique, and hot pressing of powder layers containing different amounts of a dopant in "Functionally graded materials for thermoelectric applications," Thermoelectrics Handbook—Macro to Nano (D. M. Rowe, editor, CRC Tatlor & Francis, 2006). He further concluded that the efficiency of a functionally graded material is insensitive to variations in the doping profile "which means that the carrier concentration along the length of the material does not have to match exactly the optimum profile to achieve thermoelectric efficiency very close to its maximum possible value".

Thermoelectric elements and devices with enhanced maximum temperature differences based on spatially varying distributed transport properties


Various methods and apparatuses are described for a multiple wavelength light source. The multiple wavelength light source may be located in a central office to supply a first broad band of wavelengths for a one or more passive optical networks. The multiple wavelength light source generates a series of four or more pulses of light in the first broad band of wavelengths. Each pulse of light in that series has a different center wavelength. The series of pulses of light in the first broad band of wavelengths may be repeated at a channel data rate of an optical receiver at a subscriber's location.

In a typical wavelength division multiplexed passive optical network system, the system may require multiple optical transmitters to exist in the central office. For example, the system may have thirty two optical transmitters per passive optical network having thirty two subscribers. This results in a high cost, a large physical space occupied in the central office, and a high power consumption per optical passive optical network. Eliminating the multiple optical transmitters per passive optical network and replacing the multiple transmitters per optical network with a single high-speed modulator could improve the cost, size, and power consumption associated with the multiple optical transmitters. As discussed, typically, a dedicated wavelength or channel exists for each end user/subscriber in a passive optical network. This typically requires a dedicated optical transmitter and a dedicated optical receiver for each subscriber in the central office. The multiple optical transmitters in the central office may be replaced with a one or a few high-speed modulated wavelength light sources.

Multiple-wavelength pulsed light source for a wavelength division multiplexed passive optical network


An active RC filter (20) includes a first resistive element (23) and a first capacitor array (10/50) which co-acts with the first resistive element (23) to determine a bandwidth characteristic of the programmable active RC filter circuit (20). The total filter capacitance is programmed by switching various first capacitors (4-0, 1, 2 . . . 7) of a first capacitor array (10) in parallel between first and second terminals of the first capacitor array in response to a control word (B0, 1, 2 . . . 7) to determine a first portion of the bandwidth characteristic, and by switching various second capacitors (7-0, 1, 2 . . . 6) of the first capacitor array between the first and second terminals of the first capacitor array in parallel with various ones of the first capacitors (4-0, 1, 2 . . . 7) of the first capacitor array (10) in response to less significant bits (B0, 1, 2 . . . 6) of the control word (B0, 1, 2 . . . 7) to determine a second portion of the bandwidth characteristic.

The present invention relates generally to programmable active filter stage circuits, and more particularly to a technique which increases the resolution of the bandwidth of a digitally programmable filter stage with respect to a bandwidth control word.
FIG. 1 shows a wide-bandwidth digitally programmable capacitor array 1 suitable for use in a RC active filter stage. Programmable capacitor array 1 has its terminals connected to conductors 2 and 3, respectively. The bits B7,B6,B5,B4,B3,B2,B1,B0 of a 8-bit control word are applied to the gates of N-channel switching transistors M7, M6, M5, M4, M3, M2, M1, and M0, respectively. The sources of transistors M7, M6, M5, M4, M3, M2, M1, and M0 are connected to conductor 3. The drains of transistors M7, M6, M5, M4, M3, M2, M1, and M0 are connected to first terminals of filter capacitors 4-7, 4-6, 4-5, 4-4, 4-3, 4-2, 4-1, and 4-0, respectively. Second terminals of those filter capacitors are connected to conductor 2. One terminal of a capacitor 6 of capacitance CFIX is connected to conductor 2 and the other terminal is connected to conductor 3. The capacitances of filter capacitors 4-0, 1, 2 . . . 7 are equal to C0, 2C0, 4C0, 8C0, 16C0, 32C0, 64C0 and 128C0, respectively. The binary exponential weighting of the foregoing filter capacitors as indicated by the numbers 1, 2, 4, 8 . . . 128 as shown along conductor 2 in FIG. 1. The capacitance CFIX is selected to establish a maximum bandwidth of a digital filter stage including capacitor array 1.
In digitally programmable wide-bandwidth RC active filter design, the filter bandwidth BW (or corner frequency Fc, usually specified at the 1 dB or 3 dB point) is usually adjusted by controlling the amount of capacitance C through the use of a bank or array of capacitors. Each capacitor is connected in series with a corresponding switch (usually a MOS transistor). Turning the switch on/off, the capacitor is added/removed to/from the equivalent RC network, varying the filter corner frequency Fc˜1/RC. In a conventional implementation, the capacitor array is usually composed of a defined number N of capacitors, in series with corresponding switches, the capacitors being binarily weighted by the factors 1, 2, 4, 8, 16, . . . 2N-1, respectively. The combination of those binary weighted capacitors provides a total capacitance that is a linear function of the control word or state programmed into the RC active filter, usually through a serial interface or calibration logic circuit.
Referring to curve A in the graph of subsequently described FIG. 3A, it shows that bandwidth points corresponding to successive binary steps are close together for low bandwidths and far apart for high bandwidths, due to the parabolic nature of the relationship between bandwidth and the capacitance of an RC filter. For example, on curve A a one-bit change in the binary control word B7,B6,B5,B4,B3,B2,B1,B0 changes the filter bandwidth from about 22 MHz to about 18 MHz. This very large change in bandwidth BW means that the bandwidth resolution with respect to the control word B7,B6,B5,B4,B3,B2,B1,B0 is very low for a programmable filter stage which includes programmable capacitor array 1.
However, in many applications it is highly desirable to keep the bandwidth resolution of a digital filter within a certain percentage, specific to the particular application, of the maximum bandwidth resolution value so that the filter bandwidth can be controlled with a desired level of accuracy. Consequently, it is also highly desirable that the bandwidth of a digital filter be as linear as possible with respect to the value of the digital bandwidth control word. Unfortunately, the relationship of the bandwidth of a RC circuit to the capacitance thereof is parabolic, i.e., the bandwidth is proportional to 1/C. Therefore, the desired linear relationship of the bandwidth of the digital filter to the value of the digital bandwidth control word is relatively difficult and impractical to achieve.
Because of the 1/C dependence of the filter bandwidth on the filter capacitance value, the filter bandwidth shows a parabolic behavior, with very small steps in bandwidth at large filter capacitance values (and consequently low bandwidth values) and very wide steps in bandwidth at low filter capacitance values (and consequently high bandwidth values). That is, the filter bandwidth has fine resolution with respect to the binary control word at low bandwidths and gross resolution with respect to the binary control word at high bandwidths.
This problem is more severe in filter design if a wide range of frequencies is required for the filter bandwidth. The problem could be minimized by increasing the number of control bits and consequently the number of capacitor "bit units" in the capacitor array, but this would reduce the frequency step sizes at high bandwidths at the expense of an even smaller frequency step sizes at low bandwidth and also at the expense of additional circuit complexity.
It is believed that increasing the number of binary control bits is the main known technique for increasing the bandwidth resolution of programmable active RC filters in the prior art. It would be highly desirable to provide a way of improving the bandwidth resolution of a programmable active RC filter without increasing the number of control bits to achieve a more uniform control of the bandwidth.
Thus, there is an unmet need for a way to provide a substantially lower percentage change in bandwidth of a programmable active RC filter for each binary step of the filter bandwidth control word than has been achievable in the prior art.

Circuit and method for improved frequency resolution of wide-bandwidth digitally programmable RC active filters


A central processing unit includes a programmable logic array, a timing control unit, a predecoder, a data input/output part, and a processing part. The processing part carries out a predetermined operation on m-bit low-order data from among data which is composed of n bits and which is read out from a memory and m-bit high-order data from among the data composed of n bits, and outputs a carry signal when the predetermined operation on the m-bit low-order data results in a carry. When the operation code is a read modify write instruction and when the processing part outputs the carry signal, the programmable logic array controls the input/output part so that only the result of the predetermined operation on the m-bit low-order data is written into the memory.

The present invention generally relates to a central processing unit, and more particularly to a central processing unit which processes a predetermined number of bits which is different from the number of bits stored, during one machine cycle, in a memory coupled to the central processing unit via a bus. Further, the present invention is concerned with a system using the above-mentioned central processing unit.
A central processing unit is used together with memories, such as a read only memory and a random access memory, which are coupled to the central processing unit via a bus. In some systems, the number of bits processed by the central processing unit is different from that processed by the memories during one machine cycle. For example, the central processing unit processes 8 bits of data, and each memory stores data for every 16 bits. In this case, data is read out from or written into each memory for every 8 bits.
Referring to FIG. 1, there is illustrated a procedure for executing an addition operation in a system where a central processing unit (hereinafter simply referred to as a CPU) processes data for every 8 bits and a memory stores data for every 16 bits. During cycle 1, an operation code is fetched. A data bus which mutually connects the CPU and the memory carries data for every 8 bits. Thus, during cycle 2, 8-bit low-order data (hereinafter simply referred to as an L data) of 16-bit data to be subjected to the addition operation is read out from the memory and transferred to the CPU via the bus. During cycle 3, 8-bit high-order data (hereinafter simply referred to as an H data) of the 16-bit data is read out from the memory and transferred to the CPU via the bus. Cycle 3 also has a procedure for adding a binary value of 1 to the L data. During cycle 4, the addition result obtained during cycle 3 is written into the memory, and a carry signal indicative of a carry generated in the addition result is added to the H data. During cycle 5 the H data is written into the memory.
However, the above-mentioned prior art has the following disadvantage. Even if the carry is equal to 0 during cycle 4, that is, even if no carry is generated by the operation on the L data, zero is added to the H data, which is then written into the memory during cycle 5. That is, the same data as data read out from the memory during cycle 3 is written into the memory during cycle 5. As a result, cycle 5 is wasteful and thus it takes a long time to complete the operation and obtain the operation result.
In an increment operation (instruction), a carry is generated once for every 256 cycles. Thus, the remaining 255 cycles are wasteful.

System including central processing unit


In a seat back frame formed by attaching a spring unit to a frame body, the spring unit is easily attached to the frame without performing caulking. A projecting hooked portion is formed in one side of the spring unit, and an insertion hole that receives the hooked portion therein is provided in the frame. Thus, the hooked portion is inserted into the insertion hole and hooked at a position on the rear surface thereof.

The disclosure of Japanese Patent Application No. 11-370634, filed on Dec. 27, 1999, including the specification, drawings and abstract, is incorporated herein by reference in its entirety.
1. Field of Invention
The invention relates to an attachment structure of a spring unit in a structural component formed by attaching the spring unit to a frame body.
2. Description of Related Art
A structural component formed by attaching a spring unit to a frame body has been applied to various fields, for example, seat frames such as a frame constituting a seat cushion serving as a seating portion of a vehicle seat and an ordinary chair, and a frame forming a seat back serving as a backrest. The spring unit constituting such a structural component has a rectangular shape that is formed by a plurality of wire springs connected with each other at each intersection. The spring unit is attached to the frame body by hooking the upper and lower right and left ends of the spring unit to the corresponding frame portions of the frame body, and hooking the intermediate portion of at least one of four sides of the spring unit to a corresponding frame portion of the frame body.
Generally, the spring unit forming the structural component is attached to the frame body by caulking each hooked portion of the spring unit to the corresponding frame portion of the frame body. However, caulking is a rather troublesome operation in the case where the spring unit has many hooked portions. Moreover, in the case where the frame body is molded from an alloy as a molding material, the caulking cannot be used due to the property of the molding material.
For example, in recent years, the vehicle seats have been reduced in weight, in part by integrally molding a seat frame serving as a frame body from an alloy as the molding material, for example, a magnesium alloy and an aluminum alloy. In the case where the seat frame is used as a frame body, the caulking cannot be used due to the property of the molding material.
It is an object of the invention to enable a spring unit to be easily attached to a frame body upon forming a structural component without using the caulking to attach the spring unit to the frame body.
In order to achieve the above-stated object, an structural component of one exemplary embodiment of the invention includes a frame body having a plurality of frame portions and a spring unit composed of a plurality of wire springs connected to each other at each intersection. Each end of the spring unit is hooked to a corresponding frame portion and an intermediate portion of at least one side of the spring unit is hooked to at least one frame portion. The structural component also includes a projecting hooked portion unit provided on the side frame where the intermediate portion of at least one of four sides of the spring unit is hooked. The hooked portion is inserted into a intersection hole of the side frame and hooked at a portion on a rear surface of the side frame.
According to the structural component described above, the intermediate portion of the spring unit can be attached to the frame body by attaching a hooked portion in the intermediate portion of the spring unit to a corresponding frame portion of the frame body. This eliminates the need to use the caulking to attach the spring unit to the frame body. Accordingly, even if the caulking cannot be used due to the molding material of the frame body, the spring unit can be easily attached to the frame body. Even if the caulking can be used, the troublesome attachment operation can be eliminated, thus improving operation efficiency.


A mounting aid for the alignment of a first graduation support in relation to a second graduation support of a position measuring system, the mounting aid including a spacer, which specifies a preset scanning distance between a first measuring graduation of the first graduation support and a second measuring graduation of the second graduation support. The mounting aid further including a connector having a structure to positively engage the first graduation support, wherein the connector is released from engagement with the first graduation support by displacing the connector with respect to the first graduation support and a protective cover that covers the measuring graduation.

1. Field of the Invention
The present invention relates to a mounting aid for the alignment of a first graduation support of a position measuring system. The present invention further relates to a scale with a mounting aid for the alignment of the scale relative to a scanning unit of a position measuring system. The present invention also relates to position measuring system with a scale and a scanning unit.
2. Discussion of Related Art
A position measuring system contains two graduation supports, which are movable with respect to each other for a position-dependent modulation of a physical value. One of these graduation supports is the scale with a graduation, which can be designed to be incrementally or absolutely coded. In the course of the position measurement, this graduation of the scale is scanned by a graduation of a further graduation support. This graduation is a scanning graduation of a scanning plate or the arrangement of detector elements.
When being installed on parts of machinery, these two graduation supports must be aligned with respect to each other. An essential parameter in this case is the so-called scanning distance, i.e. the distance between the graduation of the scale and the graduation of the scanning unit.
Mounting aids for setting the scanning distance are already known. In accordance with EP 0 177 711 B1, the scanning unit has a slit, through which a foil of defined thickness can be introduced between the measuring graduation and the scanning graduation from the outside. The thickness of the foil corresponds to the required scanning distance. Adjusting the scanning distance is performed by moving the scanning unit until it clamps the foil. The scanning unit is screwed onto a part of a machine in the clamped state and thereafter the foil is removed by pulling it out of the slit. It is stated that the foil is included with the measuring device and possibly performs a further function as the warranty document.
A self-adhesive foil, whose thickness corresponds to the desired scanning distance, is provided for setting the scanning distance in DE 102 29 888 A1. The scale is protected against damage by the self-adhesive foil during the alignment and attachment. The disadvantage of a self-adhesive foil is the possible effect of remaining residue from the adhesive layer on the measuring graduation. Moreover, handling of the self-adhesive foil is impractical, since it can only be removed by pulling it off, for which a sufficient free space must be available after the installation of the scanning unit and the scale.

Mounting aid for a position measuring system, as well as a scale and position measuring system with this mounting aid


The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.

Bonded wafers prepared by bonding a bond wafer to a base wafer and then reducing the thickness of the wafer used for fabricating device (bond wafer), have been used as a wafer for a high-performance device.
An SOI wafer has been known as one of the bonded wafers. This wafer can be manufactured as follows, for instance. That is, two mirror-polished silicon wafers (bond wafer and base wafer) are prepared, and an oxide film is formed on at least one wafer. Then, these wafers are bonded and then subjected to heat treatment at 200 to 1200° C. to increase bonding strength. After that, the wafer used for fabricating device (bond wafer) is ground and polished down to a desired thickness to thereby complete an SOI wafer having an SOI (silicon on insulator) layer formed thereon.
Besides, a bonded wafer is manufactured by directly bonding silicon wafers together not through an oxide film in some cases. Further, an insulator wafer made of quartz, silicon carbide, alumina, or the like may be used as a base wafer.
Referring now to FIGS. 4 and 5, conditions of an outer peripheral portion of a mirror-surface wafer before bonding and after bonding an outer peripheral portion of bonded bond wafer and base wafer are explained.
As shown in FIG. 4, the outer peripheral portion of a mirror-surface wafer 40 before bonding generally includes a chamfered portion 41 and a slightly thin portion called a polishing sag 42. If a bonded wafer is manufactured as above with the mirror-surface wafer 40, the chamfered portion 41 and the polishing sag 42 portion are not bonded and remain unbonded.
FIG. 5 shows this state. In FIG. 5, an oxide film 53 is formed on a bond wafer 51, and then a base wafer 52 is bonded thereto. As shown in FIG. 5, the chamfered portion or polishing sag portion of the mirror-surface wafer is left as an unbonded portion 54 after bonding. This unbonded portion 54 extends about 3 mm or less from the outer edge.
If the thickness of the bond wafer including such unbonded portions is reduced by grinding or the like, the unbonded portions are partially delaminated during the step of reducing the thickness. Thus, the thinned bond wafer might be smaller in diameter than a wafer as a base (base wafer) or an array of small irregularities might be formed in its peripheral portion.
If this bonded wafer is applied to a device manufacturing process, the remaining unbonded portion is delaminated during the process, with the result that particles are generated and the device yield is lowered.
To avoid such a situation, it is necessary to previously remove the unbonded portion left in the outer peripheral portion of the bond wafer before reducing the thickness of the bond wafer through grinding or the like. A portion obtained by removing the unbonded portion to expose the base wafer is referred to as a terrace portion. FIG. 6 shows a terrace portion 55 formed before the step of reducing the thickness of the bond wafer. In FIG. 6, reference numerals other than the terrace portion 55 are identical to those of FIG. 5.
In general, two methods are conceivable for forming such a terrace portion.
To explain the first method, the entire surface of the bond wafer is ground through surface grinding, and a tape is put on the ground surface of the bond wafer except the outer peripheral portion of several mm from the outer edge. As a result, the outer peripheral portion of the bond wafer is exposed and then, the exposed portion of the bond wafer is melted and removed by etching to thereby form a terrace portion.
The second method is explained with reference to FIG. 3. Here, the case of bonding a bond wafer 31 having an oxide film 33 formed thereon to a base wafer 32 is explained by way of example (see FIG. 3(a)). First, the outer peripheral portion of several mm from the outer edge of the bond wafer 31 is ground by several mm into a thickness of 10 to 100 μm (see FIG. 3(b)). Then, the remaining is etched off to form a terrace portion 35 (see FIG. 3(c)).
The latter method has been employed in most cases to keep up with recent trend to automation and mass-production (see Japanese Unexamined Patent Application Publication No. 2000-223452, for example).
Moreover, a demand to increase a quality of the terrace portion recently grows, and it is required to produce smoother terrace portions with uniform quality.
If grinding and etching for forming a terrace portion are compared, etching is more likely to involve unevenness than grinding as a machining process due to temperature, composition, or other such conditions. Hence, in order to produce smooth terrace portions with uniform quality, an etching amount has to be reduced as much as possible. Thus, the etching amount is reduced and grinding removal is increased to meet the demand to increase the quality.
However, the following problem occurs as a result of reducing an etching amount and increasing grinding removal.
That is, if the grinding removal is increased, an outer peripheral portion of the bond wafer becomes too thin (see an encircled portion of FIG. 3(b)). The too-thin outer peripheral portion of the bond wafer is caught in a grind stone and then chips or delaminates in some cases. Moreover, if the chipped or delaminated portion damages an insulator film underlying the bond wafer, corrosion proceeds up to the base wafer in a subsequent etching step, resulting in small recesses (dimples) in the terrace portion. As a result, a product is unusable for practical applications, which causes reduction in production yield. Further, the terrace dimples cause a problem such as dusting during a device manufacturing process. The wafer cannot function as an SOI wafer in some cases.
Due to the unbonded portions corresponding to the shape of the chamfered portion of the outer peripheral portion of the bond wafer and the polishing sag, the outer peripheral portion of the bond wafer becomes too thin when the polishing removal is increased. That is, the outer peripheral portion of several hundreds μm from the outer edge is delaminated from the base wafer as described above. As a result, the outer peripheral portion of the wafer is broken, chips, or delaminates due to vibrations or shock applied upon grinding with the grind stone.
As described above, in the case of removing the outer peripheral portion of the bonded bond wafer to form a terrace portion, dimples formed in the terrace portions cannot be entirely prevented and there is still room for improvement.

Method for manufacturing bonded wafer and outer-peripheral grinding machine of bonded wafer


A brake device for a pushcart includes a main movable member disposed movably within a main seat, an auxiliary movable member disposed movably within an auxiliary seat, and a connecting member interconnecting the main and auxiliary movable members. The main movable member is biased to an upper limit position, and is movable to a lower limit position so as to engage a main brake pin with a groove in a main pin-engaging member that is connected fixedly to one wheel. Hence, the connecting member moves the auxiliary movable member from a first position to a second position so as to engage an auxiliary brake pin with a groove in an auxiliary pin-engaging member that is connected fixedly to another wheel. As a result, the wheels are locked.

This invention relates to a brake device for a pushcart, and more particularly to a brake device that includes an operating portion, which can be operated to lock two wheels.
A conventional brake device includes two operating members that can be actuated to lock two aligned wheels. The use of two separate operating members results in a troublesome braking process. Such a brake device is disclosed in U.S. Pat. Nos. 4,479,566 and 5,368,133.

This patent is subject to a terminal disclaimer.


A locking pliers preferably includes a fixed jaw, a movable jaw, a fixed handle, an adjusting screw, a biasing spring, a toggle link, a power triangle link, at least one tie link and a movable handle. The fixed jaw, the movable jaw, the fixed handle, the adjusting screw and the biasing spring are preferably taken from an Irwin item no. 502L3 vise grips, but other parts may also be used. A second embodiment of the locking pliers preferably includes a fixed jaw, a movable jaw, a fixed handle, an adjusting screw, a biasing spring, a toggle link, two power links, at least one tie link, a release link and a movable handle. The fixed jaw, the movable jaw, the fixed handle, the adjusting screw and the biasing spring are preferably taken from an Irwin item no. 502L3 vise grips.

1. Field of the Invention
The present invention relates generally to hand tools and more specifically to a locking pliers, which includes a reduced distance between the fixed handle and the movable when the locking pliers is an open position.
2. Discussion of the Prior Art
U.S. Pat. No. 5,056,385 to Petersen discloses a compound toggle link. U.S. Pat. No. 6,095,019 to Warheit et al. discloses a locking plier tool. U.S. Pat. No. 7,762,162 to Phillips, Sr. et al. discloses a locking pliers with cam.
Accordingly, there is a clearly felt need in the art for a locking pliers, which includes a reduced distance between the fixed handle and the movable when the locking pliers is an open position, relative to the prior art.