A replaceable panel structure and a socket, switch and humidity sensor with the replaceable panel. The replaceable panel structure includes a base, and a panel main body which is replaceably mounted on the base by a snap structure having first snap structures and second snap structures, wherein each of the first snap structures includes a first elastic snap disposed on the panel main body and a stop block disposed on the base, a first slot fitted with the first elastic snap being formed on one side of the stop block away from the panel main body, the first elastic snap being deformed due to the stop of the stop block and then snapped into or released from the first slot; each of the second snap structures includes a second snap disposed on the panel main body and a second slot disposed on the base and fitted with the second snap, the second snap being able to be inserted into or released from the second slot in a horizontal direction.

When using electrical apparatus elements such as sockets, switches and humidity sensors, the matching degree of the color of a panel thereon with surroundings will be usually taken into consideration in order to achieve the aesthetically pleasing effect in relation to the surrounding environment. For a conventional electrical apparatus element, the panel is usually integrated with the electrical apparatus element main body and non-replaceable, so it is required to replace the whole electrical apparatus element when the color of the panel is not matched with the surroundings. In addition, if the panel of an electrical apparatus element such as a socket, a switch and a humidity sensor is damaged, the whole electrical apparatus element will be replaced, thereby resulting in waste in cost.
An existing wall type switch socket with a replaceable panel consists of a switch assembly, a fixed bottom plate, slots, a snap, a switch socket, positioning snapping tongues, a decorative panel and a hollow cylindrical body, wherein the hollow cylindrical body is provided between the switch assembly and the switch socket, one or more outwardly convex positioning snapping tongues being provided on one end of the hollow cylindrical body close to the fixed bottom plate, the inwardly concave slots being provided on an inner wall of the decorative panel, the decorative panel being transversely fixed through the fitting of the slots with the positioning snapping tongues on the hollow cylindrical body; two or more inwardly concave slots are provided at the other end of the hollow cylindrical body, and a small opening, provided therein with a snap fitted with the slots, is formed in the middle of the decorative panel, so that the switch assembly is integrated with the decorative panel and the switch socket by snapping and fixing two ends of the snap into the slots. Although the above wall type switch socket may also realize the replaceability of the panel, the withdrawing of the snap is realized by inwardly pressing the two hook-like ends of the snap snapped into the slots and then puffing the snap outward, so that it is likely to damage the snap due to too large force during disassembly and replacement. If the force is too small, the two hook-like ends of the snap are not likely to be released from the slots. If the two ends of the snap are forcibly taken out, it is likely to damage the hook-like portions. Moreover, the replaceable structure is complicated and difficult to disassemble.
Accordingly, it would be desirable to provide a replaceable panel structure and a socket that addresses at least some of the problems identified above.

Replaceable panel structure and socket, switch and humidity sensor with replaceable panel


A system and method for an approach of detecting faults in a redundant bus system based upon four timers.

Numerous regulatory agencies dealing with building safety have established different safety classifications for different electrical circuits and communication transmission pathways. The highest level of safety class is "class X" (see 12.3.6 NFPA 72 2010 safety regulation). In order to obtain a "class X" classification, the following requirements must be meet:                All circuits have a redundant path.        Circuit paths between the Fire Alarm Central Unit (FACU) and remote peripherals shall continue to operate flawlessly under the condition of a single open or a single short circuit condition.        Circuit paths shall be monitored and supervised to detect and annunciate a short or open circuit condition.Thus, FACU and remote peripherals must be monitored and any short or open circuit conditions must be annunciated in order to fulfill the requirements of the "class X" performance criteria.
As redundant circuits are typically routed via different physical transmission pathway locations for the obvious safety reasons; the propagation delays experienced on one pathway versus another will vary. Real world cable propagation delays of five nanoseconds per meter or more preclude a simple solution of combinatorial logic being implemented on the redundant received data lines of the two pathways to arrive at a desired logic level for the desired bit time.
Currently, simplistic approaches have been used to detect open or short conditions in a circuit. Such approaches detected the fault and provided little or no additional information. In a fire or disaster, additional information enables first responders to better understand where problems or dangers may exist. Maintainers of a redundant bus system may also benefit from additional information when an error is detected in a system and more quickly correct detected faults. Therefore, there is a need for an approach that not only detects a short or open circuit, but provides additional information that may aid in correcting the fault or identifying at risk areas during an emergency.


The invention relates to a method of and apparatus for displaying a holographically generated video image having plural video frames. For each frame there is provided and computed (20) a respective sequential plurality of holograms. Each said sequential plurality of holograms of the plural video frames are sequentially displayed on a diffractive element (12) for viewing the replay field thereof, and the noise variance of each frame is perceived as attenuated by averaging across said plurality of holograms.

For the sake of clarity, the term "video data" is not limited to data representing any particular type of image content and is intended to include data that is representative of one or more still images, wherein the data are periodically or regularly refreshed.
Holographically generated 2D video images are known to possess significant advantages over their conventionally projected counterparts, especially in terms of definition and efficiency. However, the computational complexity of the current hologram generation algorithms preclude their use in real-time applications. Furthermore, even if the existing algorithms were fast enough, the images generated by them are not of sufficient quality for use in a display application.
Traditionally, hologram generation algorithms may proceed by finding holograms that minimise the mean-squared error (MSE) between the desired image and the image produced (the replay field, or RPF) when the hologram is illuminated with coherent light. The inventors have shown that human subjects consider lower signal and noise variance in the RPF to be far more important in display applications. Using this result, a new algorithm optimised to the psychometrically-determined perceptual measure of image quality has been developed.
Holographically generated images may be formed by light leaving a device exhibiting a phase-modulating effect upon light incident upon the device. Typically the device is a spatial light modulator (SLM) and has a field of addressable phase-modulating elements. In some SLMs the phase-modulating elements are a linear or one-dimensional array of elements; in others a two dimensional array may be provided. For simplicity many SLMs have a regular 2-D array of like, generally square, phase-modulating elements; it is however not necessary for the phase-modulating elements to be alike in size or shape.
In general the phase-modulating elements of SLMs are often referred to as "pixels", and the elements themselves as "pixellated". The terms are used interchangeably herein. It is not intended herein, when the term "pixel" is used, that any directly viewable picture content is to be seen on the elements concerned.
An object of some embodiments of the invention is to achieve high quality real-time holographic video projection.
An object of some embodiments of the invention is to provide an algorithm for forming a CGH, which algorithm involves a low number of computationally intensive steps.
An object of some embodiments of the invention is to provide a fast algorithm for forming a CGH, which algorithm can be implemented on relatively unsophisticated hardware, such as is currently commercially available.

Cambridge University Technical Services Limited


A graphics system that is configured to utilize a sample buffer and a plurality of parallel sample-to-pixel calculation units, wherein the sample-pixel calculation units are configured to access different portions of the sample buffer in parallel. The graphics system may include a graphics processor, a sample buffer, and a plurality of sample-to-pixel calculation units. The graphics processor is configured to receive a set of three-dimensional graphics data and render a plurality of samples based on the graphics data. The sample buffer is configured to store the plurality of samples for the sample-to-pixel calculation units, which are configured to receive and filter samples from the sample buffer to create output pixels. Each of the sample-to-pixel calculation units are configured to generate pixels corresponding to a different region of the image. The region may be a vertical or horizontal stripe of the image, or a rectangular portion of the image. Each region may overlap the other regions of the image to prevent visual aberrations.

1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to high performance graphics systems.
2. Description of the Related Art
A computer system typically relies upon its graphics system for producing visual output on the computer screen or display device. Early graphics systems were only responsible for taking what the processor produced as output and displaying it on the screen. In essence, they acted as simple translators or interfaces. Modem graphics systems, however, incorporate graphics processors with a great deal of processing power. They now act more like coprocessors rather than simple translators. This change is due to the recent increase in both the complexity and amount of data being sent to the display device. For example, modem computer displays have many more pixels, greater color depth, and are able to display more complex images with higher refresh rates than earlier models. Similarly, the images displayed are now more complex and may involve advanced techniques such as anti-aliasing and texture mapping.
As a result, without considerable processing power in the graphics system, the CPU would spend a great deal of time performing graphics calculations. This could rob the computer system of the processing power needed for performing other tasks associated with program execution and thereby dramatically reduce overall system performance. With a powerful graphics system, however, when the CPU is instructed to draw a box on the screen, the CPU is freed from having to compute the position and color of each pixel. Instead, the CPU may send a request to the video card stating xe2x80x9cdraw a box at these coordinates.xe2x80x9d The graphics system then draws the box, freeing the processor to perform other tasks.
Generally, a graphics system in a computer (also referred to as a graphics system) is a type of video adapter that contains its own processor to boost performance levels. These processors are specialized for computing graphical transformations, so they tend to achieve better results than the general-purpose CPU used by the computer system. In addition, they free up the computer""s CPU to execute other commands while the graphics system is handling graphics computations. The popularity of graphical applications, and especially multimedia applications, has made high performance graphics systems a common feature of computer systems. Most computer manufacturers now bundle a high performance graphics system with their systems.
Since graphics systems typically perform only a limited set of functions, they may be customized and therefore far more efficient at graphics operations than the computer""s general-purpose central processor. While early graphics systems were limited to performing two-dimensional (2D) graphics, their functionality has increased to support three-dimensional (3D) wire-frame graphics, 3D solids, and now includes support for three-dimensional (3D) graphics with textures and special effects such as advanced shading, fogging, alpha-blending, and specular highlighting.
The processing power of 3D graphics systems has been improving at a breakneck pace. A few years ago, shaded images of simple objects could only be rendered at a few frames per second, while today""s systems support rendering of complex objects at 60 Hz or higher. At this rate of increase, in the not too distant future, graphics systems will literally be able to render more pixels than a single human""s visual system can perceive. While this extra performance may be useable in multiple-viewer environments, it may be wasted in more common primarily single-viewer environments. Thus, a graphics system is desired which is capable of matching the variable nature of the human resolution system (i.e., capable of putting the quality where it is needed or most perceivable).
While the number of pixels is an important factor in determining graphics system performance, another factor of equal import is the quality of the image. For example, an image with a high pixel density may still appear unrealistic if edges within the image are too sharp or jagged (also referred to as xe2x80x9caliasedxe2x80x9d). One well-known technique to overcome these problems is anti-aliasing. Anti-aliasing involves smoothing the edges of objects by shading pixels along the borders of graphical elements. More specifically, anti-aliasing entails removing higher frequency components from an image before they cause disturbing visual artifacts. For example, anti-aliasing may soften or smooth high contrast edges in an image by forcing certain pixels to intermediate values (e.g., around the silhouette of a bright object superimposed against a dark background).
Another visual effect used to increase the realism of computer images is alpha blending. Alpha blending is a technique that controls the transparency of an object, allowing realistic rendering of translucent surfaces such as water or glass. Another effect used to improve realism is fogging. Fogging obscures an object as it moves away from the viewer. Simple fogging is a special case of alpha blending in which the degree of alpha changes with distance so that the object appears to vanish into a haze as the object moves away from the viewer. This simple fogging may also be referred to as xe2x80x9cdepth cueingxe2x80x9d or atmospheric attenuation, i.e., lowering the contrast of an object so that it appears less prominent as it recedes. More complex types of fogging go beyond a simple linear function to provide more complex relationships between the level of translucence and an object""s distance from the viewer. Current state of the art software systems go even further by utilizing atmospheric models to provide low-lying fog with improved realism.
While the techniques listed above may dramatically improve the appearance of computer graphics images, they also have certain limitations. In particular, they may introduce their own aberrations and are typically limited by the density of pixels displayed on the display device.
As a result, a graphics system is desired which is capable of utilizing increased performance levels to increase not only the number of pixels rendered but also the quality of the image rendered. In addition, a graphics system is desired which is capable of utilizing increases in processing power to improve the results of graphics effects such as anti-aliasing.
Prior art graphics systems have generally fallen short of these goals. Prior art graphics systems use a conventional frame buffer for refreshing pixel/video data on the display. The frame buffer stores rows and columns of pixels that exactly correspond to respective row and column locations on the display. Prior art graphics system render 2D and/or 3D images or objects into the frame buffer in pixel form, and then read the pixels from the frame buffer during a screen refresh to refresh the display. Thus, the frame buffer stores the output pixels that are provided to the display. To reduce visual artifacts that may be created by refreshing the screen at the same time the frame buffer is being updated, most graphics systems"" frame buffers are double-buffered.
To obtain more realistic images, some prior art graphics systems have gone further by generating more than one sample per pixel. As used herein, the term xe2x80x9csamplexe2x80x9d refers to calculated color information that indicates the color, depth (z), transparency, and potentially other information, of a particular point on an object or image. For example a sample may comprise the following component values: a red value, a green value, a blue value, a z value, and an alpha value (e.g., representing the transparency of the sample). A sample may also comprise other information, e.g., a z-depth value, a blur value, an intensity value, brighter-than-bright information, and an indicator that the sample consists partially or completely of control information rather than color information (i.e., xe2x80x9csample control informationxe2x80x9d). By calculating more samples than pixels (i.e., super-sampling), a more detailed image is calculated than can be displayed on the display device. For example, a graphics system may calculate four samples for each pixel to be output to the display device. After the samples are calculated, they are then combined or filtered to form the pixels that are stored in the frame buffer and then conveyed to the display device. Using pixels formed in this manner may create a more realistic final image because overly abrupt changes in the image may be smoothed by the filtering process.
These prior art super-sampling systems typically generate a number of samples that are far greater than the number of pixel locations on the display. These prior art systems typically have rendering processors that calculate the samples and store them into a render buffer. Filtering hardware then reads the samples from the render buffer, filters the samples to create pixels, and then stores the pixels in a traditional frame buffer. The traditional frame buffer is typically double-buffered, with one side being used for refreshing the display device while the other side is updated by the filtering hardware. Once the samples have been filtered, the resulting pixels are stored in a traditional frame buffer that is used to refresh to display device. These systems, however, have generally suffered from limitations imposed by the conventional frame buffer and by the added latency caused by the render buffer and filtering. Therefore, an improved graphics system is desired which includes the benefits of pixel super-sampling while avoiding the drawbacks of the conventional frame buffer.
U.S. patent application Ser. No. 09/251,844 titled xe2x80x9cGraphics System with a Variable Resolution Sample Bufferxe2x80x9d discloses a computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics processor generates a plurality of samples and stores them into a sample buffer. The graphics processor preferably generates and stores more than one sample for at least a subset of the pixel locations on the display. Thus, the sample buffer is a super-sampled sample buffer which stores a number of samples that may be far greater than the number of pixel locations on the display. The sample-to-pixel calculation unit is configured to read the samples from the super-sampled sample buffer and filter or convolve the samples into respective output pixels, wherein the output pixels are then provided to refresh the display. The sample-to-pixel calculation unit selects one or more samples and filters them to generate an output pixel. The sample-to-pixel calculation unit may operate to obtain samples and generate pixels which are provided directly to the display with no frame buffer there between.
The problems set forth above may at least in part be solved by a graphics system that is configured to utilize a sample buffer and a plurality of parallel sample-to-pixel calculation units, wherein the sample-pixel calculation units are configured to access different portions of the sample buffer in parallel. Advantageously, this configuration (depending upon the embodiment) may also allow the graphics system to use a sample buffer in lieu of a traditional frame buffer that stores pixels. Since the sample-to-pixel calculation units may be configured to operate in parallel, the latency of the graphics system may be reduced in some embodiments.
In one embodiment, the graphics system may include one or more graphics processors, a sample buffer, and a plurality of sample-to-pixel calculation units. The graphics processors may be configured to receive a set of three-dimensional graphics data and render a plurality of samples based on the graphics data. The sample buffer may be configured to store the plurality of samples (e.g., in a double-buffered configuration) for the sample-to-pixel calculation units, which are configured to receive and filter samples from the sample buffer to create output pixels. The output pixels are usable to form an image on a display device. Each of the sample-to-pixel calculation units are configured to generate pixels corresponding to a different region of the image. The region may be a vertical stripe (i.e., a column) of the image, a horizontal stripe (i.e., a row) of the image, or a rectangular portion of the image. Note, as used herein the terms xe2x80x9chorizontal rowxe2x80x9d and xe2x80x9chorizontal stripexe2x80x9d are used interchangeably, as are xe2x80x9cvertical columnxe2x80x9d and xe2x80x9cvertical stripexe2x80x9d. Each region may overlap the other regions of the image to prevent visual aberrations (e.g., seams, lines, or tears in the image). As previously noted, each of the sample-to-pixel calculation units may advantageously be configured to operate in parallel on its own region or regions. The sample-to-pixel calculation units are configured to process the samples by (i) determining which samples are within a predetermined filter envelope, (ii) multiplying those samples by a weighting, (iii) summing the resulting values, and (iv) normalizing the results to form output pixels. The weighting value may vary with respect the sample""s position within the filter envelope (e.g., the weighting factor may decrease as the samples move farther from the center of the filter envelope). In some embodiments, the weighting factor may be normalized or pre-normalized, in which case the resulting output pixel will not proceed through normalization because the output will already be normalized. Normalized weighting factors are adjusted to ensure that pixels generated with fewer contributing samples will not overpower pixels generated with more contributing samples. In contrast, if un-normalized weighting factors are used, the resulting pixel will typically proceed through normalization. Normalization will typically be performed in embodiments of the graphics system that allow for a variable number of samples to contribute to each output pixel. Normalization may also be performed in systems that allow variable sample patterns, and in systems in which the pitch of the centers of filters vary widely with respect to the sample pattern.
In some embodiments, the graphics system may be configured to dynamically change the size or type of regions being used (e.g., changing the width of the vertical columns used on a frame-by-frame basis). Some embodiments of the graphics system may support a variable resolution or variable density frame buffer. In these configurations, the graphics system is configured to render samples more densely in certain areas of the image (e.g., the center of the image or the portion of the image where the viewer""s attention is most likely focused). Advantageously, the ability to dynamically vary the size and/or shape of the regions used may allow the graphics system to equalize (or come closer to equalizing) the number of samples that each sample-to-pixel calculation unit processes for a particular frame.
The samples may include color components and alpha (e.g., transparency) components, and may be stored in xe2x80x9cbinsxe2x80x9d to simplify the process of storing and retrieving samples from the sample buffer. As described in greater detail below, bins are a means for organizing and dividing the sample buffer into smaller sets of storage locations. In addition, in some embodiments the three-dimensional graphics data may be received in a compressed form (e.g., using geometry compression). In these embodiments the graphics processors may be configured to decompress the three-dimensional graphics data before rendering the samples. As used herein, the term xe2x80x9ccolor componentsxe2x80x9d includes information on a per-sample or per-pixel basis that is usable to determine the color the pixel or sample. For example, RGB information and transparency information may be color components.
A method for rendering a set of three-dimensional graphics data is also contemplated. In one embodiment the method comprises: (i) receiving the three-dimensional graphics data, (ii) generating one or more samples based on the graphics data, (iii) storing the samples, (iv) selecting stored samples; and (iv) filtering the selected samples in parallel to form output pixels. The stored samples may be selected according to a plurality of regions, as described above.

Graphics system configured to perform parallel sample to pixel calculation


A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and particularly to a layout of CMOS type SRAM cells.
2. Description of Related Art
SRAM that configures a memory cell with six transistors can be formed in a standard semiconductor CMOS process and is widely used for system LSI and the like. A conventional SRAM memory cell is comprised of six transistors, which are two NMOS driver transistors, two NMOS transfer transistors and two PMOS load transistors.
Japanese Unexamined Patent Publication No. 2003-115551 (Satomi et al.) discloses a technique to form one each of NMOS driver transistor and NMOS transfer transistor in a first and a second P-well region. It also discloses that two PMOS load transistors are formed in one N-well region.
Meanwhile in recent years as elements become finer, soft error phenomena are reported to occur that causes an inversion of logical data stored in a memory cell due to an influence of radiation such as neutrons from cosmic radiation that reach on the ground. Moreover the influence of radiation further causes a multi-bit error in which a plurality of cells generate an error simultaneously. For this reason, a technique to address such multi-bit error is reported in for example, "Circuit Techniques for Low-Power SRAM", Osada et al., The Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, 2004-4.
Moreover in a SRAM cell, retention stability of data is quantitatively provided by a characteristic curve which is created by reversing input and output transfer characteristic curves of inverters and then superimposing the reversed curves on original curves. The larger an area bounded by the two characteristic curves, the more stable data can be retained. A size of this area is referred to as Static Noise Margin (SNM). SNM depends on input logic threshold of an inverter that constitutes SRAM. Accordingly SNM depends on current drive capability (for instance threshold voltage and size of MOSFET) of MOS transistors that constitute the SRAM cell. For example, when an ability of a transfer transistor becomes higher as compared to that of a driver transistor, a level of a bit line can be easily transmitted to a memory node. Since noise on the bit line can be also easily transmitted, it could result in a decrease of SNM, generating a bias in a stability point, and cell data being easily destroyed. For this reason, a transfer transistor is usually designed to have an inferior capability than a driver transistor.
To maintain data retention characteristic of a SRAM memory cell, drive capability of a NMOS driver transistor must be better than that of a NMOS transfer transistor. A technique described by Satomi et al. differentiates between the drive capability of a transfer transistor and that of a driver transistor by having a different implanted ion dose or gate length. Additionally in this technique, diffusion layers and electrodes are shaped in rectangle from an aspect of securing SMN and yield.
Techniques disclosed in Japanese Unexamined Patent Publication No. 10-162581 (Tei et al.) and Japanese Unexamined Patent Publication No. 11-232878 (Michael et al.) use PMOS transistors as transfer transistors. However a layout for the techniques is neither clearly identified nor does the technique include a resolution against the above soft error.
For a SRAM memory cell that induces a difference in drive capability by differentiating a gate length of a driver transistor from that of a transfer transistor as described by Satomi et al., there could be a difficulty in reducing cell area due to nonuniformity in its pattern. It could also reduce accuracy in microfabrication. As a countermeasure for the soft error in a conventional SRAM memory cell, there is a known method to have an error correction circuit from an aspect of circuit technology. There are other known methods from an aspect of process device to add extra capacity to cell node, adjust substrate impurity concentration and use a SOI substrate. However it has now been discovered that no technique has considered over both of a layout in view of processing accuracy and a reduction in charge collection of cell node diffusion layer on a radiation incidence.


A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

1. Field of the Invention
The invention relates to time-shared bus computer architecture having bus Users with private cache storage, particularly with respect to bus access by Users during cache consistency procedures.
2. Description of the Prior Art
Present day digital computers often utilize a time-shared bus architecture including plural bus Users with one or more Users having a private cache. This architecture typically includes an I/O module User, one or more processor Users and a main memory User. An arbiter on the bus traditionally arbitrates the bus requests from the Users and the bus grants thereto. In operation, a User with a cache copies words from main memory into its cache and performs processes using the words in cache. For example, a processor User may copy program instructions and data from main memory to its cache and, thereafter, execute the program task from cache. As is appreciated, cache is used in this manner to enhance performance. The processor User with the cache avoids going back and forth on the bus to main memory for each instruction.
While a first User is performing processes with its cache, a second User may write to main memory in the locations copied by the first User into its private cache, rendering the cached words from the overwritten locations invalid. In order to maintain cache consistency, the first User monitors the bus and when a write to memory is detected from the second User, the first User executes a cache cycle to determine if it has data from the write-addressed main memory location. If so, the first User invalidates its cache so that the invalid data is not subsequently used. Typically, the execution time of a cache cycle occupies a significant number of bus cycles. Thus, while a cache cycle is executing, the second User, or a third User, can put another request on the bus to do another memory write while the first User is occupied with the original memory write.
In a particular design initially tried by the present inventors in the development of a computer system utilizing the above described architecture, the first User put a RETRY signal on the bus advising the second/third User to retry its memory write request at a later time and the second/third User included a Retry mechanism that retried the bus request at a fixed time interval after receiving the RETRY signal. Additionally, the User Retry mechanism included logic to establish a limit on the number of sequential retries that could be attempted before a decision was made that a malfunction had occurred. When such a malfunction was detected, the process was aborted and an error message generated.
The present inventors discovered that, although a User may indicate a Retry-Limit-Exceeded error condition, the condition was not caused by a malfunction. Instead, a rarely occurring synchronism between repetitive WRITES TO MEMORY by a first bus User, the concomitant cache cycles of a second bus User and the Retry mechanism in a third bus User, resulted in the apparent "failure" of the third bus User. The third bus User was forced to retry its bus operation beyond its Retry Limit. This failure mechanism, herein denoted as bus lockout, will be described later in greater detail.
The occurrence of bus lockout may be exacerbated since the sending of the RETRY signal is repeated when numerous bus Users attempt WRITES TO MEMORY via the bus during a cache cycle. Furthermore, each of numerous bus Users can have a cache, thus causing numerous RETRY signals to be sent.
In the non-analogous technology of Local Area Networks (LAN), communication users on the LAN retry transmissions using a randomly selected Retry wait interval. Such a system is described in U.S. Pat. No. 4,410,889, issued Oct. 18, 1983. It is appreciated that the random Retry wait interval is unsuitable for use in the computer architecture described above. A randomly selected Retry wait interval can be unacceptably long, seriously degrading the performance of the User.

Varying wait interval retry apparatus and method for preventing bus lockout


A hollow composite interior door assembly includes a pair of sheet molding compound skins mounted on a rectangular frame. No spacer is used to provide the necessary rigidity to the structure. Rather, the skins are adhered to each other along opposed recesses crating a lattice structure framework that supports the assembly.

Traditionally, door assemblies have been made entirely of wood. The wood provides the necessary strength and rigidity to enable the assembly to maintain its shape, and it gives the assembly a pleasing appearance and feel. However, wooden doors chip, crack, and become weathered. In addition, they are expensive and heavy. To overcome the problems associated with wooden doors, metal exterior doors and composite skin interior doors have been used.
Exterior metal doors with filler materials solve the problems of weathering, cracking, and chipping associated with wooden doors. The metal skin provides the necessary strength and is easily maintained. The interior of the door can be filled with an insulating material such as polyurethane or polystyrene foam to give the door the desired thermal characteristics. Although these doors are a suitable alternative to wooden doors for exterior use, they are not desirable for interior use because of cost and weight. Moldable composite skin doors are often used as an alternative to wooden doors for interior use. Moldable composite skin doors have many advantages over wooden doors. They are generally lighter than wood doors, they do not weather, chip, or crack, and they are easier to clean and maintain.
Interior door assemblies constructed of moldable composite skins are well known in the art. Since the skins lack necessary strength, a spacer, or other filler material is used to provide the door assembly with the necessary rigidity. Generally, the spacer is made of strips of wood or corrugated cardboard that are bonded to the skins. Without the spacer that is bonded to the outer skins, the door assembly would easily deflect. Although the spacer provides rigidity to the door assembly, it also increases the cost and weight of the door assembly and requires a complex manufacturing process.


This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing radio frequency sensing control and dynamic frequency selection control. A method called Cognitive Dynamic Frequency Hopping that is based on the selective Simultaneous Sensing and Data Transmissions is described. The Cognitive Dynamic Frequency Hopping method is further facilitated by a collision avoidance technique. The described method satisfies both reliable and timely RF sensing for guaranteeing licensed user protection, and QoS satisfaction for services of the dynamic spectrum access systems.

The present invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing radio frequency sensing control and dynamic frequency selection control.
RF Spectrum scarcity, caused by costly spectrum access, becomes a major issue for deploying future wireless communication systems, according to the current spectrum allocation of regulatory organizations world wide. On the other hand, spectrum utilization measurements indicate that frequencies allocated in the licensed bands are largely under-utilized. For example, measurement shows that only 5.2% of spectrum is in use in the US for the frequency bands below 3 GHz. Scarcity of spectrum licensing and under-utilization of licensed bands motivate dynamic spectrum access that allows un-licensed wireless applications to operate in the licensed bands while insuring no harmful interference to the incumbent users in the licensed bands.
As an enabling technology for open spectrum access, cognitive radio is able to perform spectrum sensing, learning, and adapting to the RF environment so as to facilitate unlicensed radio operations and enhancement of spectrum reuse efficiency in intelligent ways. The key issues are RF spectrum sensing, learning, and adaptation, with objectives of guaranteeing incumbent service protection, and maintaining fair spectrum sharing and appropriate Quality-of-Service of cognitive radio systems.
The charter of IEEE 802.22, the Working Group on Wireless Regional Area Networks ("WRANs"), under the PAR approved by the IEEE-SA Standards Board is to develop a standard for a cognitive radio-based PHY/MAC/air-interface for use by license-exempt devices on a non-interfering basis in spectrum that is allocated to the TV Broadcast Service.
This invention provides Medium Access Control (MAC) methods for Cognitive Radio based dynamic access network systems, especially for IEEE 802.22 WRAN systems, addressing the key technical issues listed above.

Methods of RF sensing control and dynamic frequency selection control for cognitive radio based dynamic spectrum access network systems-cognitive dynamic frequency hopping


A stator core has 3N salient poles arranged circularly where N is a natural number of four or more but except a multiple of three. Coils are formed around the salient poles where winding directions of the coils is the same for the salient poles. A first, a second and a third crossover are formed between a first and an (N+1)-th salient pole, between the (N+1)-th and a (2N+1)-th salient pole and between the (2N+1)-th and the first salient pole, respectively, to forming a triangle before cutting within the salient poles arranged circularly. An end portion of each crossover is connected to a substrate.

The present invention relates to a stator core. Particularly, this invention relates a stator core of a motor which is smaller in size and thinner used for storage devices of apparatuses for office automation, video tape recorders, and so on, and a wire winding method for the stator core.
Motors used for hard disc drives, floppy disc drives as memory devices of apparatuses for office automation, and for video tape recorders, etc., have recently an accelerative trend for smaller and thinner with smaller apparatus. Further, higher performance, lower cost, and higher productivity have been demanded for such motors. Among them, particularly, connection of coil terminals requires increased number of processes, leading to higher cost.
FIG. 1 shows a stator core applied with a conventional wire winding method as related art; and FIG. 2 shows the state where a stator core is mounted on a printed substrate.
A lead wire 20 for a core coil is tied up and soldered to a metal pin 22 provided on a holder 21 formed of resin, and wound around each stator core to form a coil 15. A protrusion 25 provided on the lower part of the holder 21 is inserted into a hole 26 provided in a corresponding printed substrate 12 and caulked. Further, the metal pin 22 is soldered at its printed substrate side, and a crossover 20 of the coil 15 is connected to the printed substrate 12.
However, the conventional configuration has a problem in that since the number of processes of tying up the lead wire to the metal pin is increased, the assembly time is required, and a resin holder, a metal pin and equipment or fitting for assembling them are necessary, thus increasing the cost.
Japanese Patent Laid-Open No. 1994(6)-225488 discloses a wire winding method in which a coil is formed continuously without disconnection halfway. A crossover between coils passing through upper or lower portion of an opening provided in a stator core is cut, whose cut portion is soldered to a printed substrate.
However, a winding direction to a salient pole is not constant, and hence extra time for winding is required; and since crossovers run vertically and horizontally, places where crossovers are cut are difficult to be specified, and hence a long assembling time is required.

Stator core and wire winding method for the same


A liquid ejecting head which is formed by joining a liquid introducing member for introducing liquid and a base body by welding includes an introduction hole which is formed in a front end of the liquid introducing member and an extending section which is tilted to extend from the exterior edge of an introduction hole to the inside of the introduction hole.

1. Technical Field
The present invention relates to a liquid ejecting apparatus such as an inkjet-type recording device, a display device manufacturing apparatus, an electrode forming apparatus, or a bio chip manufacturing apparatus and a liquid ejecting head installed in the liquid ejecting apparatus.
2. Related Art
Ink jet printers serving as liquid ejecting apparatuses appropriate for printing on paper are well known. Generally, ink jet printers have a configuration in which a liquid ejecting head having fine nozzles for ejecting liquid (liquid droplets) is loaded onto a carriage reciprocating with respect to printing paper. For example, in a liquid ejecting head disclosed in JP-A-10-193646, an ink supply needle (liquid introducing member) combined with a supply section of an external ink cartridge for introducing ink is provided.
The ink supply needle is a member having the shape of a hollow needle in which a plurality of introduction holes are formed on peripheral surface of a cone-shaped apex portion. The peripheral surface of the apex portion serves as a guide when the ink supply needle is inserted into a supply hole of the ink cartridge, and ink can be introduced from the ink cartridge through an introduction hole.
The introduction hole of the ink supply needle is a spot that causes pressure loss (flow resistance) at a time when the ink is introduced, and accordingly, it is preferable that the inside diameter of the introduction hole increases to some degree from the viewpoint of the reduction of pressure loss. However, as the diameter of the introduction hole increases, a partition wall between the introduction hole and an adjacent introduction hole becomes thinner, and thus, there may be a case where the partition wall between adjacent introduction holes is broken at a time when the ink supply needle is welded to the base body (case) of the liquid ejecting head using an ultrasonic welding method.

Ink supply needle for a liquid ejecting head and liquid ejecting apparatus


On the top surface of a substrate, an atmosphere blocker plate, of which plan size is equal or larger than the substrate size, is disposed opposing to the top surface of the substrate. In the rim portion of the atmosphere blocker plate, a vertical through hole is formed so that a nozzle can be inserted into the hole. Nozzle move mechanism moves the nozzle to insert the nozzle to the through hole and position it to the opposing position that is opposed to the top rim portion of the substrate and to the retract position that is away from the atmosphere blocker plate. Processing liquid is supplied from the nozzle, which is positioned to the opposing position, to the top rim portion of the substrate.

1. Field of the Invention
The invention relates to a substrate processing apparatus for performing processing such as cleaning of various types of substrates such as semiconductor wafers, glass substrates for photo mask, glass substrates for liquid crystal display, glass substrates for plasma display and optical disk substrates by supplying a processing liquid to these substrates.
2. Description of the Relates Art
In the manufacturing process for semi conductor devices, coating of a thin metallic film such as a thin copper film is often performed on the entire top surface and edge surface (and bottom surface in some cases) of a substrate. Then, the metallic thin film is removed by etching from the portions where coating is not required. For example, when the copper thin film is used for the purpose of facilitating for wiring, the coating of copper thin film is needed only in device seating areas. Therefore, the copper thin film portions that are adhered to the rim of the top surface, bottom surface and outer edge will not be needed. Moreover, when the substrate is transported by a substrate-transporting robot that is installed in a substrate processing apparatus, the copper may adhere to contaminate the hands of the robot. When the contaminated hands come in contact with other substrates, the copper and other unwanted substances will consequently be transferred to these substrates.
For the same reasons, the processing is performed for the purpose of removing the metallic contaminant, by thinly etching a non-metallic film such as an oxidized film, a nitride film or the like that is formed on the rim of the substrate. An apparatus, which is described in the Japanese Publication of Unexamined Application 2004-6672, performs processing of the rim portion and edge surface of the substrate through selective etching. This apparatus comprises: a spin chuck that rotates the substrate while keeping it horizontal; a blocker plate that is located above the spin chuck to control the space on the top surface of the substrate; and a nozzle that supplies the processing liquid such as an etching liquid to the bottom surface of the substrate. With this apparatus, the processing liquid that is supplied to the bottom surface of the substrate flows outward from the center to the rim portion of the bottom surface of the substrate, due to the presence of centrifugal force. Then, the processing liquid flows over edge surface to reach the top rim portion. The blocker plate is disposed in adjacent to the top surface of the substrate and the inert gas such as nitrogen gas or the like is supplied to the space between the blocker plate and the substrate. By controlling the flow rate of the inert gas, the rotating speed of substrate and the supplying quantity of processing liquid at the optimum levels, the etching of the top rim portion of the substrate is selectively performed at a pre-determined width. After the unwanted substance on the top rim portion of the substrate is removed by etching, the top and bottom surfaces of the substrate are rinsed with pure water or DIW (de-ionized water). Subsequent to the rinsing process, the spin chuck is activated to spin at high speed to spin-dry the top and bottom surfaces of the substrate.

This patent is subject to a terminal disclaimer.

Apparatus for and method of processing a substrate with processing liquid


An apparatus in an electronic device such as a buck converter circuit receives as a first input a voltage signal VSNS from the electronic device that represents a current through the electronic device, and receives as a second input a direct current reference voltage signal from a reference voltage source VREF. The apparatus regulates a direct current output IOUT of the electronic device with respect to the reference voltage source VREF by applying a pulse level transformation to the voltage signal VSNS using an operational transconductance amplifier.

To better understand the advance in the art that the present invention provides a prior art floating buck converter circuit 100 will first be described. As shown in FIG. 1, prior art floating buck converter circuit 100 comprises the following elements: diode 110, capacitor 120, load 130, inductor 140, transistor 150 (here shown as a field effect transistor (FET) designated "MAIN FET M0"), resistor RSNS, pulse width modulation (PWM) control unit 160 and gate driver 170. The diode 110, capacitor 120 and the load 130 are coupled in parallel with a first end of each element coupled to the input voltage VIN. The load 130 shown in FIG. 1 comprises a plurality of serially connected light emitting diodes (LEDs). The output current through the load 130 is designated IOUT.
A first end of inductor 140 is coupled to the second end of diode 110 and to the drain of transistor 150. A second end of inductor 140 is coupled to the second end of load 130 and the second end of capacitor 120. The current through inductor 140 is referred to as the inductor current and is designated with the letters IL.
The source of transistor 150 is coupled to a first end of resistor RSNS. The second end of resistor RSNS is coupled to ground. The current through the transistor 150 is referred to as the transistor current and is designated by the letters IFET. A first end of a voltage signal line 180 is coupled to node between transistor 150 and resistor RSNS. The value of voltage at the node is designated with the letters VSNS. The second end of the voltage-signal line 180 is provided to an input of the pulse width modulation (PWM) control unit 160. An output of the pulse width modulation (PWM) control unit 160 is provided to gate driver 170. The output of gate driver 170 is connected to the gate of transistor 150. Control signals from the pulse width modulation (PWM) control unit 160 are provided through gate driver 170 to the gate of transistor 150 to control the transistor current and the output current IOUT. The pulse width modulation (PWM) control unit 160 monitors the value of the voltage signal VSNS on voltage signal line 180 and adjusts the value of the control signals to gate driver 170 based on the average value of the VSNS voltage.
FIG. 2 illustrates a schematic circuit diagram 200 of the prior art floating buck converter circuit 100 shown in FIG. 1 showing the pulse width modulation (PWM) control unit 160 in more detail. The second end of the voltage signal line 180 is provided to an input of a leading edge blanking unit 210. The operation of the leading edge blanking unit 210 removes any voltage "spike" that may be present at the leading edge of the VSNS voltage signal.
The output of the leading edge blanking unit 210 is provided to a non-inverting input of a comparator unit 220. A reference voltage VREF is provided to the inverting input of comparator unit 220. The output of comparator unit 220 is provided to the pulse width modulation (PWM) control logic circuit 230. As shown in FIG. 2, the PWM control logic circuit 230 comprises a first edge pulse generator unit 240, a second edge pulse generator unit 250, a first NOR gate 260, a second NOR gate 270, and a third NOR gate 280.
As shown in FIG. 2, an input line 290 provides a pulse signal to the first edge pulse generator unit 240 and to the second edge pulse generator 250. The first edge pulse generator unit 240 generates a first control signal pulse and provides the first control signal pulse to an A1 input of the third NOR gate 280. The second edge pulse generator unit 250 generates a second control signal pulse and provides the second control signal pulse to an A1 input of the first NOR gate 260.
The comparator 220 generates a third control signal by comparing the reference voltage VREF to the VSNS voltage signal on voltage signal line 180. The comparator 220 provides the third control signal to an A2 input of the second NOR gate 270. The output of first NOR gate 260 and the output of second NOR gate 270 are cross-coupled. That is, the output of the first NOR gate 260 is provided to the A1 input of the second NOR gate 270. The output of the second NOR gate 270 is provided to the A2 input of the first NOR gate 260. The output of the first NOR gate 260 is also provided to the A2 input of the third NOR gate 280. The output of the third NOR gate 280 is provided to the gate driver 170.
The general principles of operation of the prior art floating buck converter circuit 100 shown in FIG. 1 (and the circuit 200 shown in FIG. 2) are well known in the art. Prior art floating buck converter circuits operate by sensing the sloped rise portion of the inductor ripple current. However, the choice of a particular value for inductor 140 will alter the average output current.
Consider, for example, the two waveforms of inductor current 300 shown in FIG. 3. The first waveform 310 for a first inductor illustrates a first inductor ripple current in a prior art floating buck converter circuit. The second waveform 320 for a second inductor illustrates a second inductor ripple current in the same prior art floating buck converter circuit.
The value of peak current is the same for both the first waveform 310 and the second waveform 320. However, the average current for the first waveform 310 ("Average Current 1") is greater than the average current for the second waveform 320 ("Average Current 2"). The prior art method of sensing the peak value of current to regulate the peak inductor current does not determine a true average output current value. This leads to less precision in the average output current regulation. Therefore it would be desirable to have an apparatus and method that could determine a true value of the average output current and utilize the true value to provide a true average output current regulation.
FIG. 4 illustrates generic waveforms of a prior art floating buck converter circuit. FIG. 4(a) shows the inductor current IL as a function of time. The inductor current ripple is designated with the letters Irip. The average value of the inductor current IL is equal to the direct current (DC) output current IOUT. FIG. 4(b) shows the field effect transistor current IFET as a function of time. The mid-level value of the IFET current during the sloped rise of the IFET current is equal to the direct current (DC) output current IOUT. As shown in FIG. 4(b), the increase in the IFET current during its sloped rise is equal to the inductor current ripple Irip. When the IFET current has increased by a value of one half Irip ("Irip/2") from the beginning of the sloped increase in current then the IFET current has reached a value of the direct current (DC) output current IOUT.
FIG. 4(c) shows the value of the VSNS voltage signal as a function of time. The mid-level value of the VSNS voltage signal during the sloped rise of the VSNS voltage is equal to the product of the direct current (DC) output current IOUT and the resistance RSNS. Comparing FIG. 4(b) and FIG. 4(c) leads to the relationship shown in FIG. 4(d). The mid-level of the sloped rise of the VSNS voltage (that originated from the inductor current ripple Irip) is equal to the product of the direct current (DC) output current IOUT and the resistance RSNS.
As shown in FIG. 4(d), the increase in the VSNS voltage during its sloped rise is equal to the product of the inductor current ripple Irip and the resistance RSNS. When the VSNS voltage has increased by a value of one half Irip ("Irip/2") times the resistance RSNS from the beginning of the sloped increase in voltage then the VSNS voltage has reached a value of the direct current (DC) output current IOUT times the resistance RSNS.
There is a need in the art for a system and method that is capable of precisely regulating the direct current (DC) output current of a floating buck converter circuit. There is also a need in the art for a system and method that is capable of determining a true value of the average output current and utilizing the true value to provide a true average output current regulation in a floating buck converter circuit.
One prior art approach to controlling a floating buck converter circuit is set forth in a paper entitled Dynamic Effects of Inductor Current Ripple in Average Current Mode Control by T. Suntio, J. Lempinen et al. published in the 32nd Annual IEEE Power Electronics Specialists Conference, 17-21 Jun. 2001, Volume 3, pp. 1259-1264. Another prior art approach to controlling a floating buck converter circuit is set forth in a paper entitled DC-to-DC Buck Converters with Novel Current Mode Control by Z. Yang and P. C. Sen published in the 30th Annual IEEE Power Electronics Specialists Conference, 27 Jun.-1 Jul. 1999, Volume 2, pp. 1158-1164.
The assignee of the present patent application also has a related patent application entitled Versatile System for High-Power Switching Controller in Low-Power Semiconductor Technology filed on Nov. 2, 2005 with patent application Ser. No. 11/265,783.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation; the term "or," is inclusive, meaning and/or; the phrases "associated with" and "associated therewith," as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
The term "controller" means any device, system, or part thereof that controls at least one operation. A controller may be implemented in hardware, software, firmware, or combination thereof. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.

Constant current output using transconductance amplifier


A technology for illuminating almost an entire console with a simple structure, even when a display is located at the right or left of the center of the console is disclosed. According to this technology, when a display 1 is located at the center of a console 2, a detection signal of a sensor S1 is turned ON, a light L1 in the center of the display is lit, and the light illuminates the entire console. In addition, when the display is located at the right of the console, the detection signal of the sensor S2 is turned ON, the light L2 on the left-side of the display is lit, and the light can illuminate the entire console. In addition, when the display is located at the left of the console, the detection signal of the sensor S3 is turned ON, the light L3 on the right-side of the display is lit, and the light can illuminate the entire console.

Because, for example, an ultrasonic diagnostic apparatus, among various equipments, is used in a dimly lit environment, a method of illuminating a pictogram on a console from within the console or providing a task light on the display that illuminates the console, to facilitate visibility of the console, and in particular, the pictogram that expresses the functions of the operation keys on the console in a dimly lit environment, is known. In addition, as a conventional example of the task light, for example, there is the invention disclosed in Patent Document 1, below. Patent Document 1: Japanese Patent Application Publication (PCT) No. 2002-510134 (Abstract of the Disclosure)
However, generally, when an operator such as a doctor uses equipment such as an ultrasonic diagnostic apparatus, the operator images a tomographic image by pressing a probe onto a subject site, displays the image on a display, and at this time, shows the examinee the displayed image. Therefore, the display is rotatable to the console. This is problematic in that, the task light cannot illuminate the entire console by merely providing a task light on the display to illuminate the console, when the display is located at the right or left of the center of the console. In addition, in the method in which a pictogram on the surface of the console is illuminated from within the console, this is problematic in that the internal structure of the console becomes complicated.


A vibration damping device includes: a cylindrical first attachment member and a second attachment member; and an annular first elastic body and an annular second elastic body, wherein, a liquid chamber is formed between the elastic bodies, elastic division walls that divide the liquid chamber into a plurality of pressure receiving liquid chambers are arranged, wherein the elastic division wall is joined to the first elastic body, and is also in abutment with the second elastic body, wherein the second attachment member is divided in the axial direction into: a first divided body to which an inner peripheral edge portion of the first elastic body is joined; and a second divided body to which an inner peripheral edge portion of the second elastic body is joined, and wherein the inner peripheral edge portions of the elastic bodies are located side by side in the axial O direction.

Conventionally, a vibration damping device is known that includes: a cylindrical first attachment member that is joined to either one of a vibration generating unit and a vibration receiving unit; a second attachment member that is joined to the other; and elastic bodies that join the attachment members, as is shown in, for example, Patent Document 1 below.
The elastic body includes a first elastic body and a second elastic body, both having an annular shape and being spaced from each other in an axial direction. Between the first and second elastic bodies, a liquid chamber is formed, and also a plurality of elastic division walls, which divide the liquid chamber into a plurality of pressure receiving liquid chambers, are arranged in a circumferentially spaced manner, the pressure receiving liquid chambers being in communication with each other though a restriction passage. The elastic division walls are joined to the first elastic body and are also in abutment with the second elastic body. The second attachment member is axially divided into: a first division body to which an inner peripheral edge portion of the first elastic body is joined; and a second division body to which an inner peripheral edge portion of the second elastic body is joined.


An image display apparatus includes a memory for holding in advance, of the one or more information terminal apparatuses connected via a network, information of information terminal apparatuses whose connection to the network is desired, a controller for reading out the information of the information terminal apparatuses stored in the memory, and display section for displaying a list of the information of the information terminal apparatuses. In this case, the image display apparatus further includes selector for selecting one information terminal apparatus from the list displayed on the display section, it is able to change the connection of the information terminal apparatus to desired information terminal apparatus by manipulation of the selector on a display screen.

1. Field of the Invention
The present invention relates to an image display apparatus that receives images transferred from a plurality of information terminal apparatuses connected to a wireless or wire network, and displays them on a display section, and further relates to an image display system and an image display method that include a plurality of information terminal apparatuses connected to a wireless or wire network and an image display apparatus.
2. Description of Related Art
In general, as apparatuses for displaying an image (hereinafter referred to as image display apparatuses), image display apparatuses such as projection display systems comprised of a predetermined plane of projection (projection screen) and an image projection apparatus (projector: PJ) that projects and displays an image on the screen, cathode ray tube (CRT) display apparatuses that display an image using cathode rays, image display apparatuses that display an image on a liquid crystal display (LCD) section and the like are known. Such image display apparatuses generally are capable of receiving image information that is sent from an information terminal apparatus, such as a personal computer, through wire communications or wireless communications, and of displaying an image corresponding to the received image information.
In Patent Document 1 mentioned below, a configuration is disclosed wherein, between an information terminal apparatus and an image display apparatus that are wire connected, a projector receives image information transmitted from the information terminal apparatus, and projects it onto a screen.
Patent Document 1: Japanese Laid-Open Patent Application No. 2002-123238

Image display apparatus, image display system, and image display method


Disclosed is a system which employs a cooling or heating pad which is preferably a thin, flexible pad for placement at an intended area of the body. The pad includes a layer of highly conductive material which can be cooled or heated using a portable source of heat or cold material delivered to the conductive material by a delivery conduit. Valves can be included to regulate flow of the cooling or heating material from the source to the pad. The system can also include a dual-chambered canister for containing two different media for heating, cooling or for alternating heating and cooling the pad.

Cooling or heating pads are well known in the art and have been used for therapeutic procedures for many years. Currently available cooling or heating pads typically require prior refrigeration/freezing or heating/warming of the pad, as the case may be, and can require more than one pad so that a "reserve" pad can be refrigerated/frozen ("cooled") or heated while another is in use. In addition, such pads typically use bulky materials which prohibit free mobility of the injured area and can be uncomfortable to wear during normal activities.
Cooling or heating pads in the prior art generally employ a gel or similar material to retain externally-generated cold or heat, whereby the cooled or heated pad is placed within the source of cold or heat (e.g., refrigerator/freezer or oven, such as a microwave oven) and is removed from the cold or heat source so that it can be applied to an intended area of the body in need of treatment using cold or hot temperatures.
The prior art, and the disadvantages thereof, is discussed here in the context of cool or cold packs and therapy but, as would be understood by persons of ordinary skill in the art, apply equally to heat or hot-packs and therapy. For example, a common method of alleviating pain or swelling after a surgical procedure or accidental injuries is to use a cold compress, using an ice bag, a bag of frozen peas, or snow-type freezer packs to be wrapped around or applied to the affected area. Currently available cooling pads require pre-cooling or pre-freezing of the pad whereby the pad is physically placed within the cold source prior to use.
Other cooling devices utilize cold liquid to circulate around the affected area and require tubes carrying the liquid to be continuously connected to the device whereby use of the device is inconvenient and bulky.
Moreover, bulky cooling pads or cold packs are limited as to their applicability to certain parts of the body. For example, specific areas of the face, such as the brow or nose, generally require the pad or pack to cover the whole, general area and cannot provide a truly moldable device which substantially conforms to areas of the body which are not easily enwrapped.
A pad which is pre-cooled or frozen generally adapts its shape to the environment of the cold source. For example, even a flexible ice pack, when frozen, is generally defined by the shape of its outer container. When placed in a freezer, ice packs are typically formed in a generally rectangular shape with generally flat faces for contacting the body. Although they can be frozen in a particular or pre-formed "curved" shape, it is well recognized that the curvature only generally mimics the shape of the body at the site of application and does not mold to the specific contours as would be desired.
The previously available processes, though effective, are inconvenient and can limit mobility of the person due to the weight or bulkiness of the ice or cooling pack. None of the previous devices known to the inventors can provide cold therapy "on demand" without requiring removal of the pad to replace cold or hot temperatures, and without the use of bulky materials or requiring continuous circulation of liquid through the device during use.
Thus, what is needed is a flexible or moldable cooling or heating pad device and system that can efficiently provide cold or heat to a specific area of the body. Preferably, this desired action is achieved by a system comprising a pad that can be "charged" with cold or heat at the time of use and at the site of use so that the pack does not require extended periods of time to cool down or become frozen, or to warm up to a desirable temperature before use. Neither would such system require removal of the pad for re-cooling, re-freezing, or re-heating following dissipation of the therapeutically effective cold or hot temperature after a period of time.
Moreover, what is needed is a system which can provide a "re-chargeable" pad which can be re-cooled or re-heated during use without requiring connection to an external source or generator of cold or hot temperatures. Thus, a pad and system providing an external source of cold or heat which is connected to the pad temporarily, only to provide cold or heat to the pad, and then is disconnected from the pad during use, advantageously provides greater mobility and ease of use to and for the user of such pad and system.
These advantages, as described herein, as well as other advantages that would be recognized and appreciated from this disclosure, are achieved by the subject invention which overcomes the disadvantages and inconvenience of cold and heat packs known or currently available in the art.

Portable therapeutic system using hot or cold temperature


Provided is an apparatus and method for controlling a charge capacity balancing operation of a secondary battery cell. According to the present disclosure, the charge capacity balancing operation starts under the consideration of an environment condition suitable to perform the charge capacity balancing operation, so that sufficient time for the charge capacity balancing operation of the secondary battery cells may be ensured. Accordingly, this may reduce the possibility of the balancing operation being interrupted.

Recently, due to the exhaustion of fossil energy and environmental pollution, the interest in electric products, which may operate with electrical energy instead of fossil energy, is growing more and more. Accordingly, with the increasing development and demand of mobile devices, electric vehicles, hybrid vehicles, energy storage devices, uninterrupted power supplies, or the like, the demand of secondary batteries as energy sources are rapidly increasing as well as its various forms thereof. Therefore, secondary batteries are being studied very actively to cope with such diverse demands.
Generally, a secondary battery includes a nickel cadmium battery, a nickel metal hydride battery, a lithium ion battery, a lithium ion polymer battery, and the like. This secondary battery is largely classified into a lithium-based battery and a nickel metal hydride-based battery. The lithium-based battery is primarily used in a wide range of application including small-scale products, for example, a digital camera, a P-DVD, an MP3P, a mobile phone, a PDA, a Portable Game Device, a Power Tool, an E-bike, and the like, and the nickel metal hydride-based battery is used in a variety of application including large-scale products requiring high output such as an electric vehicle or a hybrid electric vehicle.
Meanwhile, to drive an electric vehicle or a hybrid electric vehicle, an electric motor requiring high output should be operated. Also, in a case of an energy storage device used to supply power to a building or a predetermined area, a sufficient amount of energy to meet the energy demand must be supplied. Accordingly, energy of a desired output or amount is provided using a battery pack in which a plurality of unit secondary battery cells, hereinafter referred to as unit cells, are connected in series or in parallel, to provide high output or high capacity energy.
However, in a case of a battery pack including a plurality of unit cells connected to one another, a charge capacity difference occurs between the respective unit cells as charging and discharging is performed repeatedly. Under the condition of charge capacity imbalance, a particular unit cell having a low charge capacity is over-discharged if the battery pack is continuously discharged, which hinders a stable operation of the battery pack. In contrast, under the condition of charge capacity imbalance, a particular unit cell having a high charge capacity is over-charged if the battery pack is continuously charged, which reduces safety of the battery pack. The charge capacity imbalance puts a certain unit cell into an over-charge state or over-discharge state and thereby hinders stable power supply to a load, for example, an electric motor or an electrical grid. To solve this problem, a charge capacity balancing operation is needed to continuously monitor and balance the charge capacity of unit cells to a predetermined level.
This charge capacity balancing operation is performed in the way of discharging a unit cell having a higher charge capacity than a reference charge capacity through a buck circuit until it reaches the reference charge capacity, or charging a unit cell having a lower charge capacity than the reference charge capacity through a boost circuit until it reaches the reference charge capacity.
However, it takes some time to charge or discharge a secondary battery due to the characteristics of the secondary battery, and as a charge or discharge amount increases and the number of unit cells requiring a balancing operation increases, a period of time taken to complete the balancing operation increases. Further, since use of a battery pack is restricted while a balancing operation of unit cells is in progress, there is a need to control a time to start the balancing operation.

Apparatus and method for controlling charge capacity balancing operation of secondary battery cell


A plethysmograph is constructed with a base including parallel, horizontal guide rails; an open-ended, moveable enclosure section having a horizontal central axis slidable on the guide rails between open and closed positions; a fixed enclosure section mounted on the base transverse to the horizontal pathway, the fixed enclosure section including an inner face toward the open end of the enclosure section adapted for sealing engagement with the open end of the moveable enclosure section when the moveable enclosure section is in its closed position; and a support table attached to the fixed section, the table projecting into the moveable enclosure section when the moveable enclosure section is in the closed position, the table being vertically adjustable and having an angularly adjustable longitudinal axis.

(1) Field of the Invention
The present invention relates to plethysmographs used to measure changes in air volume, such as in pulmonary testing of small animals, and in particular to plethysmographs facilitating accurate positioning of anesthetized animals for tracheal cannula insertion during laboratory testing.
(2) Description of the Prior Art
Various laboratory procedures require an analysis of the respiratory patterns of small test animals. Respiratory data is collected by enclosing the animal in the chamber of a device known as a plethysmograph, and measuring changes in air pressure within the chamber during the test procedure.
A plethysmograph is generally comprised of an enclosure with a closeable access opening to permit placement and removal of the test animal, and a cover to releasibly fit over the enclosure access opening. The enclosure is provided with a means for controlled air access and egress, a means to measure variations in air pressure within the enclosure, such as a differential pressure transducer, and commonly a means for administering test materials to the animal during the test procedure.
Test animals may be anesthetized and tracheotomized during many test procedures. Therefore, plethysmographs often include a table to support the animal. Usually, the table will include a horizontal upper surface upon which the animal is placed, normally on its back, with the animal's head toward the end or side of the chamber through which the tracheal cannula is inserted during the test procedure.
To facilitate opening and closing, one section of the enclosure, either the open-ended chamber or the cover, may be held in a stationary position, while the other section is moveable between an open position and a closed position. In the closed position, the open end of the chamber releasibly engages the cover in a sealing fashion to prevent air from entering the chamber between the two sections. For example, as taught in U.S. Pat. No. 5,379,778, an air-tight seal may be achieved by positioning an O-ring between the chamber opening and the cover.
Prior art plethysmographs are less than optimal. First, due to variations in animal sizes, accurate placement of the tracheal cannula is not always possible. Second, fitting of the chamber cover onto the chamber may be difficult due to the need to align the chamber opening with the corresponding connection area of the cover. Therefore, there is a need for further improvements in prior art plethysmographs.


In accordance with embodiments of the present disclosure, an apparatus may include an input for indicating a characteristic of an output load current of a switched output stage comprising at least one driver device and a predriver circuit coupled to the input and a gate terminal of the at least one driver device, the predriver circuit for driving an input voltage signal to the gate terminal and configured to select an effective impedance of the gate terminal based on the input for indicating the output load current. In accordance with these and other embodiments of the disclosure, a method may include receiving an input for indicating a characteristic of an output load current of a switched output stage comprising at least one driver device and selecting an effective impedance of a gate terminal of the at least one driver device based on the input for indicating the output load current.

Many electronic devices on the market today often use power converters to convert electric energy from one form to another (e.g., converting between alternating current and direct current), amplifying a voltage or current of an electrical signal, modifying a frequency of an electrical signal, or some combination of the above. Examples of power converters may include boost converters, buck converters, and audio amplifiers (including, but not limited to Class D, and Class H amplifiers). Such power converters often employ a switched output stage, an example of which is shown in FIG. 1. In FIG. 1, switched output stage 100 comprises a pull-up device 102 (e.g., a switch, a p-type metal-oxide-semiconductor field effect transistor, etc.) coupled at its non-gate terminals between a supply voltage and an output node and a pull-down device 104 (e.g., a switch, an n-type metal-oxide-semiconductor field effect transistor, etc.) coupled at its non-gate terminals between a ground voltage and the output node. The gate terminals of each of the pull-up device and the pull-down device are typically driven by a pulse-width-modulated input voltage signal νIN (or a derivative thereof), and the switched output stage produces an output voltage signal νOUT on the output node which is a function of the input voltage signal.
One drawback in using switched output stages in a power converter is the presence of spikes (or overshoot) and ringing in the output voltage signal, as shown in FIG. 2. Such overshoot and subsequent ringing often occurs as a result of parasitic capacitances and inductances in the circuit resonating at their characteristic frequency, which decays over time due to resistances present in the circuit. For example, as output voltage signal νOUT transitions from a ground voltage to a supply voltage VSUPPLY, νOUT may first overshoot νSUPPLY by an amount νOVER, and then oscillates about VSUPPLY as the ringing decays. Overshoot and ringing may be undesirable as they may cause unneeded current to flow (e.g., thereby wasting energy and potentially causing undesirable heat), may delay arrival at a desired final state, and/or may cause communication of incorrect signals.

Systems and methods for reducing spike voltages in a switched output stage


A gradient amplifier system, includes: a power stage comprising a plurality of bridge amplifiers, each operates at a first switching frequency; a gradient coil coupled to the power stage and configured to produce a magnetic field proportional to a coil current signal supplied by the power stage; a controller stage coupled to an input terminal of the power stage and configured to: generate a pulse width modulated gate signal based on the coil current signal and a reference current signal, wherein the pulse width modulated gate signal is generated at a second switching frequency when a slew rate associated with the reference current signal is below a threshold rate for at least a first time period; and apply the pulse width modulated gate signal to the power stage for changing an operating frequency of each of the plurality of bridge amplifiers from the first to the second switching frequency.

The disclosure relates generally to magnetic resonance imaging (MRI) systems and more specifically to reducing power losses in a gradient amplifier system adapted for use in MRI systems.
In just a few decades, the use of magnetic resonance imaging (MRI) scanners has grown tremendously. MRI scans are being increasingly used to aid in the diagnosis of multiple sclerosis, brain tumors, torn ligaments, tendonitis, cancer, strokes, and the like. As will be appreciated, MRI is a noninvasive medical test that aids physicians in the diagnoses and treatment of various medical conditions. The enhanced contrast that an MRI scan provides between the different soft tissues of the body allows physicians to better evaluate the various parts of the body and determine the presence of certain diseases that may not be assessed adequately with other individual imaging methods such as X-ray, ultrasound, or computed tomography (CT).
A conventional MRI system typically establishes a homogenous magnetic field generally along a central axis of a subject undergoing an MRI procedure. This homogeneous magnetic field affects the gyro magnetic material of the subject for imaging by aligning the nuclear spins in atoms and molecules forming the body tissue. For example, in medical applications, the nuclear spins are aligned along the direction of the magnetic field. If the orientation of the nuclear spins is perturbed out of alignment with the magnetic field, the nuclei attempt to realign their spins with the field. Perturbation of the orientation of nuclear spins is typically caused by application of radio frequency (RF) pulses tuned to the Larmor frequency of the material of interest. During the realignment process, the nuclei precess about their axes and emit electromagnetic signals that may be detected by one or more RF detector coils placed on or about the subject.
The frequency of the magnetic resonance (MR) signal emitted by a given precessing nucleus depends on the strength of the magnetic field at the location of the nucleus. It is possible to distinguish signals originating from different locations within the subject using encoding, typically phase and frequency encoding, created by gradient coils that apply gradient fields over the main magnetic field. A typical MRI system includes three gradient coils for providing respective fields along the X, Y, and Z axes. Control of the gradient coils allows for orientation of the axes for encoding of locations within the subject, and for selection of a desired "slice" for imaging.
Furthermore, these gradient coils typically produce additional magnetic fields that are superimposed on the primary magnetic field to permit localization of the image slices and also provide phase encoding and frequency encoding. This encoding permits identification of the origin of resonance signals during image reconstruction. The image quality and resolution depends significantly on how the applied fields can be controlled. To achieve faster imaging rates, the gradient fields are typically modified at frequencies of several kHz. Control of the gradient coils is generally performed in accordance with pre-established protocols or sequences, called pulse sequence descriptions, permitting many types of tissues to be imaged and distinguished from other tissues in a medical context, or for imaging various features of interest in other applications.
Typically, a gradient coil operates at high current levels and high voltage ranges. Therefore, it is desirable to provide a gradient amplifier that is configured to supply the gradient coils with the desired current and voltage levels. In certain embodiments, the gradient amplifier is a power amplifier.
Earlier implementations of gradient amplifiers used linear amplifiers that provided high fidelity. However, given present power level requirements, the use of these amplifiers becomes impractical due to need for the higher voltages and currents. Present day techniques use hybrid systems that combine linear amplifiers with switching power stages. Such systems use bridges in parallel or bridges stacked to meet the system requirements, and typically employ power semiconductor devices. However, in the conventional gradient amplifier system, each of the bridges has different direct current (DC) link voltages and different voltage commands, which unfortunately results in different switching frequencies for each of the bridges. Since each of the bridges operates at different switching frequencies with different DC link voltages, there is significant power loss in the gradient amplifier system. Moreover, the power loss increases when a low voltage is desired across the gradient coil. In addition, the power losses are unevenly distributed across the bridges, and the loading on each bridge is also different, causing intense thermal stress on the gradient amplifiers.
It is therefore desirable to develop a design of a gradient amplifier system that reduces power loss. Particularly, it is desirable to develop the design of a controller stage and a power stage architecture in the gradient amplifier system that provides high power and delivers high fidelity with reduced power loss and cost through circuit topologies and control mechanisms.

System and method to reduce power loss in a gradient amplifier


Oxide-free metallic, alloy or intermetallic compound formed by coating a powder of at least one member selected from the group consisting of elemental metallic, alloy and intermetallic compound with an oxide-replacing metal. The oxide-free compound may be compacted without the addition of a liquid sintering agent and at temperatures below the melting point of the compound, under sufficient pressure to form a uniform, consolidated intermetallic body.

Amalgams and related alloys have been incorporated into a variety of commercial applications and thus a number of processes for producing such amalgams are known. For example, U.S. Pat. No. 4,664,855 discloses a universally employed process which triturates elemental metallics or an intermetallic alloy, in the form of comminuted filings or atomized spherical powders, with the sintering agent mercury and compacts the resulting amalgam into a uniform, consolidated intermetallic alloy. The process may be considered a combination of liquid phase and reactive metal sintering. The finely comminuted metallic or intermetallic powders react with the Hg and when pressure is applied to the reaction product, form a compact, high density mass. U.S. Pat. No. 3,933,961 discloses a process for preparing a pre-weighed alloy tablet of uniform weight which is then triturated with a weighed quantity of Hg to form a traditional amalgam alloy.
Metallic powders have two basic forms: 1) minute lathe-cut filings and 2) atomized, spherical particles. Lathe-cut filings are subsequently milled and sifted to produce the desired particle size. The length of particles in a commercial lathe-cut alloy might range from 60-120 .mu.m long, 10-70.mu.m wide and from 10-35.mu.m thick. On the other hand, spherical particles, produced by means of an atomizing process whereby a spray of tiny drops is allowed to solidify in an inert gaseous (e.g., argon) or liquid (e.g., water) environment, have a maximum size between 40 and 50 .mu.m (Dental Amalgams, William J. O'Brien, Ph.D., Quintessence Publishing Co., 1989, at p. 264, 266).
For more than 150 years, dental practitioners have applied a Ag-Sn system and related intermetallic alloys as dental amalgam preparations for use in dental restorations such as fillings and prostheses. The amalgamation reaction which forms Ag-Sn dental preparations is best represented below (Dental Materials, supra, at p. 269); EQU Ag.sub.3 Sn+Hg.fwdarw.Ag.sub.2 Hg.sub.3 +Sn.sub.7 Hg+Ag.sub.3 Sn; EQU or
gamma+Hg.fwdarw.gamma 1+gamma 2+gamma (residual).
After completion of the amalgamation reaction, the high-melting Ag.sub.3 Sn (gamma) products are embedded in a matrix of mercury reaction products. Both the Ag.sub.2 Hg.sub.3 (gamma 1) and Sn.sub.7 Hg (gamma 2) phases form a continuous network. In the amalgam structure above, however, the Sn.sub.7 Hg is susceptible to corrosion by the following reaction: EQU Sn.sub.7 Hg+101/220.sub.2 +21H.sub.2 O +14Cl.sup.- .fwdarw.7Sn.sub.4 (OH).sub.6 Cl.sub.2 +4Hg.
Dental amalgam corrosion results in a weakened structure and further formation of unsupported, "margin" amalgam which easily fractures under tension.
The introduction of contemporary amalgams in the 1960s (amalgams known as "high-copper" amalgams) eliminated the corrosive phenomenon of Sn.sub.7 Hg by preventing the formation of Sn.sub.7 Hg (gamma 2). However, even though the addition of Cu into amalgam alloys markedly improved the integrity of the dental amalgam, the Cu.sub.6 Sn.sub.5 (the eta prime phase of the copper amalgam system) is prone to corrosion according to the following reaction (Dental Materials, supra, at 293). EQU 2Cu.sub.6 Sn.sub.5 +41/2O.sub.2 +9H.sub.2 O+6Cl.sup.31 .fwdarw.CuCl.sub.2 .multidot.3Cu(OH).sub.2 +.sup.10 SnO.
Furthermore, the copper which is known to leach out during corrosion of the high-copper amalgam systems has raised concern regarding the biocompatibility of these contemporary copper amalgams.
A more recent attempt to eliminate the well-known corrosive tendencies of the Ag-Sn and Ag-Sn-Cu amalgam systems is addressed in U.S. Pat. No. 4,181,757 which discloses a process for surface coating parent metals with a slurry (composed of a low-melting-temperature gold alloy powder, an inorganic oxide-dissolving flux, and organic liquid) and firing the slurry to produce a bonded, corrosion-resistant layer on the parent metal surface. The disclosed process is intended for use with dental prostheses and is not readily adaptable for in situ dental restorations such as fillings.
Additionally, recent evidence has raised new issues concerning the biocompatibility of currently used dental amalgams. Evidence has now been put forward that air expired by dental patients having dental restorations made from these amalgams, particularly after gum chewing, has a significantly higher mercury vapor content than that of amalgam free patients.
In an attempt to replace traditional dental amalgams with a more biocompatible intermetallic, experiments have been conducted on gallium alloys formed by triturating liquid gallium with a metal powder (Journal of Fukuoka Dental College, "Gallium Alloys for Dental Restorations,"Takashi Horibe et al., 12(4): 198-204, 1986). However, the Journal of Dental Health has reported that gallium alloys supplied orally to rats and mice induce toxic responses in the test subjects (J. of Dental Health, "Study on Toxicity of a New Gallium Alloy for Dental Restorations," 37. 361-371, 1987). This raises questions about their safety as an alternative to traditional amalgams used in dental restorations.

Process for forming alloys in situ in absence of liquid-phase sintering

The United States of America as represented by the Secretary of Commerce