The invention provides synthetic heparin-binding growth factor analogs of formulas I or II as given in the specification, having two peptide chains branched from a dipeptide branch moiety composed of at least one and preferably two trifunctional amino acid residues, which peptide chain or chains bind a heparin-binding growth factor receptor. The synthetic heparin-binding growth factor analogs are useful as pharmaceutical agents, soluble biologics or as surface coatings for medical devices.

1. Field of the Invention (Technical Field)
The invention relates to the field of synthetic peptides and analogs of heparin-binding growth factors. The invention further relates to the clinical uses of such analogs as soluble drugs and as coatings for medical devices.
2. Description of Related Art
Note that the following discussion refers to a number of publications by author(s) and year of publication, and that due to recent publication dates certain publications are not to be considered as prior art vis-a-vis the present invention. Discussion of such publications herein is given for more complete background and is not to be construed as an admission that such publications are prior art for patentability determination purposes.
The heparin-binding growth factors (HBGFs) constitute a large class of growth factors that includes the 23 fibroblast growth factors identified to date (FGFs 1-23), HBBM (heparin-binding brain mitogen), HB-GAF (heparin-binding growth associated factor), HB-EGF (heparin-binding EGF-like factor) HB-GAM (heparin-binding growth associated molecule), TGF-α (transforming growth factor-α), TGF-βs (transforming growth factor-βs), PDGF (platelet-derived growth factor), EGF (epidermal growth factor), VEGF (vascular endothelial growth factor), IGF-1 (insulin-like growth factor-1), IGF-2 (insulin-like growth factor-2), HGF (hepatocyte growth factor), IL-1 (interleukin-1), IL-2 (interleukin-2), IFN-α (interferon-α), IFN-γ (interferon-γ), TNF-α (tumor necrosis factor-α), SDGF (Schwannoma-derived growth factor) and the many other growth factors, cytokines, lymphokines and chemokines that have an affinity for heparin.
Peptides from natural HBGFs that bind heparin-binding growth factor receptors have been identified. See for example Ray et al., Proc. Natl. Acad. Sci. USA 94:7047-7052 (1997). These authors demonstrated that two amino acid sequences from FGF-2 are sufficient to block the mitogenic activity of FGF-2 on neural progenitor cells. The first peptide is a ten amino acid sequence, from amino acids 65-74, the second peptide extends from amino acids 115-129.
In an alternative approach, an artificial peptide that binds a heparin-binding growth factor receptor was identified by a phage display method. Ballinger et al., Nature BioTechnology 17:1199-1204 (1999) used this technique to isolate a 28 amino acid peptide called C19, which binds FGF-2 receptors, but by itself fails to stimulate biological activity. The peptide has no amino acid sequence identity with any known FGF.
HBGFs useful in prevention or therapy of a wide range of diseases and disorders may be purified from natural sources or produced by recombinant DNA methods, however, such preparations are expensive and generally difficult to prepare.
Some efforts have been made to generate heparin-binding growth factor analogs. For example, natural PDGF occurs as an A chain and a B chain arranged in head-to-head (AA or BB) homodimers, or (AB or BA) heterodimers. Thus, U.S. Pat. No. 6,350,731 to Jehanli et al. discloses PDGF analogs in which two synthetic PDGF receptor-binding domains are covalently linked through a polyglycine or an N-(4-carboxy-cyclohexylmethyl)-maleimide (SMCC) chain to mimic the natural active polypeptide dimer.
U.S. Pat. No. 6,235,716 to Ben-Sasson discloses analogs of angiogenic factors. The analogs are branched multivalent ligands that include two or more angiogenic homology regions connected by a multilinker backbone.
Other workers have described compositions that include homologs and analogs of fibroblast growth factors (FGFs). See for example U.S. Pat. No. 5,679,673 to Lappi and Baird; U.S. Pat. No. 5,989,866 to Deisher et al. and U.S. Pat. No. 6,294,359 to Fiddes et al. These disclosures relate to FGF homologs or analogs that are either conjugated to a toxic moiety and are targeted to the FGF receptor-bearing cells; or are homologs or analogs that modulate the biological pathways through the signal transduced by the FGF receptor upon binding by the FGF homolog or analog.
A series of patent applications to Kochendoerfer et al. disclose polymer-modified proteins, including synthetic chemokines and erythropoiesis stimulating proteins. See, for example, International Publications WO 02/04105, WO 02/19963 and WO 02/20033. These include chemically ligated peptide segments of a polypeptide chain of a synthetic erythropoiesis protein, such that a polypeptide chain results, with a water soluble polymer attached at one or more glycosylation sites on the protein. These applications also disclose synthetic chemokines, which are also polymer modified, and are asserted to be antagonists. Other erythropoietin mimetics are known, such as those disclosed in U.S. Pat. Nos. 5,773,569 and 5,830,851 to Wrighton et al.
International Publication WO 00/18921 to Ballinger and Kavanaugh discloses a composition consisting of fusion proteins having FGF receptor affinity linked to an "oligomerization domain", either directly or through a linking group. The oligomerization domain ranges in length from about 20 to 300 residues, and includes constructs such as transcription factors, Fc portions of IgG, leucine zippers and the like. The oligomerization domains disclosed are homodimeric domains, wherein a single FGF receptor affinity fusion protein is linked to a single domain, such as a leucine zipper, which in turn is linked to a similar molecule by means of cysteine residues at both the amino and carboxy termini of the leucine zippers, such that two parallel leucine zippers, each with a single FGF receptor affinity fusion protein, are cross-linked by means of disulfide bonds. It is also disclosed that fusion proteins may include a heparin binding domain, such as the use of jun as a multimerization domain, which is asserted to be a heparin binding domain. Thus the compositions disclosed by Ballinger and Kavanaugh are all composed of a single receptor-binding sequence covalently attached to an oligomerization domain, whereby two or more similar oligomerization domains, each with a single receptor-binding sequence, are conjoined by means of either an association provided by the oligomerization domain, or alternatively, are chemically cross-linked to provide for the covalent bonding of the individual components.
The above described homologs, analogs, conjugates or ligands each include a receptor-binding domain. However, none of these or other known heparin-binding growth factor analogs provide the advantages described herein below. There is still a need for new peptide analogs of HBGFs, particularly for those that function as agonists. In particular, there is still a need for cost-effective synthetic peptide agonists of heparin-binding growth factor receptors, particularly synthetic heparin-binding growth factor agonists.
This application is related to U.S. patent application Ser. No. 10/644,703, entitled Synthetic Heparin-Binding Growth Factor Analogs, filed on Aug. 19, 2003, and to U.S. patent application Ser. No. 10/224,268, entitled Synthetic Heparin-Binding Growth Factor Analogs, filed on Aug. 20, 2002, and the specification thereof of each is incorporated herein by reference.

This patent is subject to a terminal disclaimer.

BioSurFace Engineering Technologies, Inc.


A system for detecting proximity to a target object. The novel system includes a detector adapted to receive a reflected electromagnetic beam from the target and a processor adapted to determine a distance to the target by measuring an angle of the reflected beam. The system may also include an emitter adapted to transmit an electromagnetic beam toward the target to produce the reflected beam such that the angle of the reflected beam corresponds with a distance to the target. In an illustrative embodiment, the emitter is a focused infrared emitter or laser diode positioned to transmit the beam at a known angle such that the transmitted beam crosses an optical axis of the detector. The processor may also be adapted to use the rate of change of the amplitude of the reflected beam in determining the distance to the target.

1. Field of the Invention
The present invention relates to optical and electrical systems. More specifically, the present invention relates to systems and methods for sensing proximity to a target object.
2. Description of the Related Art
Missiles often require detonation of a warhead to occur a short distance before impacting the target for maximum warhead effectiveness. Particularly when a shaped charge warhead must penetrate an armored target, the ability to control standoff distance for warhead jet formation greatly impacts the probability of kill.
Fuzes for low cost weapons have traditionally detonated warheads upon target impact using crush switches. Other fuzes have also been deployed that sense altitude or target proximity for detonation. Proximity sensing fuzes typically operate by transmitting an RF (radio frequency) or optical signal toward the target and measuring the time until a reflected return signal is received to determine the distance to the target. The warhead is then detonated when the missile is at a predetermined distance away from the target.
Conventional proximity sensing fuzes typically require additional electronics for transmitting, receiving, and processing the RF or optical signal. These electronics usually serve no purpose other than proximity sensing and add a higher cost to the missile. In addition, conventional proximity sensing fuzes typically have lower precision at sensing the distance to a target located directly in front of the weapon.
Hence, a need exists in the art for an improved system or method for sensing proximity that is less expensive and more accurate than prior approaches.


A piezoelectric ceramic laminate device constituted by a plurality of piezoelectric ceramic sheets, wherein the concentration of at least one metal component constituting the piezoelectric ceramic sheets changes substantially along a sinusoidal curve in the laminating direction thereof.

1. Field of the Invention
The present invention relates to a piezoelectric ceramic laminate device, more specifically, to a piezoelectric ceramic laminate device suitable for actuators usable in precise positioning devices of machine tools, flow-controlling valves, automobile brakes, etc.
2. Description of the Background Art
Materials which mechanically strain when an electric field (voltage) is applied thereto are generally called piezoelectric materials or electrostrictive materials, and these kinds of materials are used as electromechanical transducers in many applications such as bimorphs, piezoelectric ignition elements, ultrasonic vibrators, piezoelectric buzzers, ceramic filters, etc.
Generally, when voltage is applied to a piezoelectric material, the crystal structure of the piezoelectric material is transformed and a maximum strain (maximum electromechanical coupling constant) is obtained at its crystal transformation point. Since the crystal transformation point varies depending on the composition of the piezoelectric material used, a proper piezoelectric material should be selected depending on a temperature at which it is used.
BaTiO.sub.3, Pb(Zr,Ti)O.sub.3 (which is generally called PZT), LiNbO.sub.3, LiTaO.sub.3, etc. are known as piezoelectric materials. Also usable are those obtained by adding other metal oxides to the above piezoelectric materials to improve various properties. Further, since a PNZST-type piezoelectric material which is obtained by partially substituting Zn in the above PZT piezoelectric material with Nb and Sn strains greatly without cracking or breakage, attempts have been made to use the PNZST piezoelectric material for actuators.
However, as schematically shown by a solid line in FIG. 15, the strain of the PNZST piezoelectric material suddenly increases almost to the maximum when a certain voltage (E.sub.q) is applied thereto. This means that, in practice, the strain of the PNZST piezoelectric material is controlled only at the maximum strain (.DELTA.Lo) and the minimum strain (0); in other words, the strain of the PNZST piezoelectric material is only controlled digitally. There also is a problem that a hysteresis loop of voltage vs. strain is relatively large in the PNZST piezoelectric material.
Although the above-mentioned digital control is effective in some cases, a piezoelectric material would be able to find much more applications in the field of actuators, if the analog control of the strain of the piezoelectric material can be performed, namely if the strain can be controlled at a certain point between the maximum and the minimum. To achieve the analog control of the strain, it is necessary to develop a piezoelectric material whose strain changes more gradually in proportion to the voltage applied and which has a strain/voltage hysteresis loop which is much slimmer. For instance, in the case of the PZT as shown in FIG. 16, .DELTA.X/X.sub.max should be small. Also, in the case of the PNZST as shown in FIG. 17, it is needed to have a strain changeable by a small .DELTA.L relative to the change of voltage .DELTA.E.


A method and system for connecting a vehicle to a charging source comprising: at least one retractable protrusion operatively connected to a battery terminal; the at least one retractable protrusion being mounted on the vehicle; at least one receptacle operatively connected to the charging source adapted to receive the retractable protrusion for electrical connection of a vehicle to a charging source; whereby by driving the vehicle in the proximity of the at least one receptacle, the charging source is connected to the electrical system of the vehicle as the retractable protrusion engages the at least one receptacle. Another embodiment comprises at least one solar element for converting solar power to electric power; at least one battery for storing electricity generated by the solar element; the solar element being operatively connected to the at least one battery for storing electric power therein; first and second vehicle based connectors for connecting the vehicle power supply to the charging system, the first and second vehicle based connectors being located on the periphery of the vehicle such that the vehicle may be connected to the vehicle charging system by alignment of the vehicle with first and second external connectors operatively associated with the external charging system; whereby by maneuvering the vehicle, the first and second vehicle based connectors are bought into contact with the first and second external connectors to enable charging of the vehicle battery.

The 2011 Chevy Volt, primarily an electric (or hybrid) vehicle is advertised as requiring 10 to 12 hours of charging at 110 volts. If the charging current is between 15-30 amperes of current @ 110 volts, the power is on the order of 1650 to 3300 watts per hour. If the charge is 10-12 hours, one can multiply by the number of hours to produce the kilowatt hours. While charging is available to some people in their homes/garages, it presents a problem to apartment dwellers and to people who do not have access to a charging system. Accordingly, making charging systems available through parking meters or charging stations is highly desirable.
Remote power stations may be useful to supplement or as an alternative to the home recharging concept. Solar power does not require the installation of power lines for supply of power to remote charging stations.
Background solar powered devices include U.S. patent application Ser. No. 12/025,737 entitled "SOLAR-POWERED LIGHT POLE AND LED LIGHT FIXTURE," hereby incorporated by reference, which discloses a solar-powered lighting system that includes a flexible, wrap-around, preferably self-stick panel of photovoltaic laminate applied to the outside surface of a light pole. An LED light fixture is connected preferably at or near the top of the pole and has the same or similar diameter as the pole. The LED light fixture has multiple columns and rows of LEDs and an interior axial space for air flow to cool the LEDs. The pole preferably also has vents and axial passage(s) for creating a natural updraft through at least a portion of the pole and the light fixture, for cooling of the photovoltaic panel interior surface, the LEDs, and/or other equipment inside the fixture or pole, and batteries that may be provided inside the pole or pole base.
U.S. Patent Application No. 2006/0149607, hereby incorporated by reference, discloses means for programming and controlling an LED assembly using a programmable controller and feedback means.
Interconnection of the charging source, whether it be a solar powered charging source or convention power lines, can be hazardous when requiring a individual to get out of the driver's seat to plug a cord from the power supply into the car receptacle or vice versa. This is particularly disadvantageous in bad weather.


4-tert.-Butylcyclohexanol having a larger content of its cis-isomer is prepared by hydrogenating 4-tert.-butylphenol in a solvent in the presence of a rhodium catalyst and a compound selected from the group consisting of hydrogen chloride and (anhydrous) sulfuric acid. Furthermore, 4-tert.-butylcyclohexanol obtained by the above hydrogenation is acetylated to give 4-tert.-butylcyclohexyl acetate.

1. Field of the Invention
The present invention relates to a process for preparing 4-tert.-butylcyclohexanol containing the larger amount of the cis-isomer by hydrogenating 4-tert.-butylphenol under specific conditions. The present invention also relates to a process for preparing 4-tert.-butylcyclohexyl acetate by acetylating 4-tert.-butylcyclohexanol which is obtained by the process described above.
2. Description of the Prior Art
4-tert.-Butylcyclohexyl acetate is widely used as a perfume for cosmetics including soaps, and fragrance of its cis-isomer is more favorable than that of its trans-isomer. To prepare 4-tert.-butylcyclohexyl acetate having a high cis-isomer content, it is desired to provide a process for preparing 4-tert.-butylcyclohexyl containing the larger amount of the cis-isomer because 4-tert.-butylcyclohexanol is used as a raw material of 4-tert.-butylcyclohexyl acetate.
In general, 4-tert.-butylcyclohexanol is prepared by hydrogenating 4-tert.-butylphenol.
JP-B-42-13938 discloses a process for preparing 4-tert.-butylcyclohexanol comprising catalytically reducing 4-tert.-butylphenol in the presence of a rhodium base catalyst.
MARUZEN OIL TECHNICAL REVIEW (MARUZEN SEKIYU GIHO) (1971) page 77 discloses a process for preparing 4-tert.-butylcyclohexanol comprising hydrogenating 4-tert.-butylphenol in the presence of various transition metals of the 8 to 10 Groups of the Periodic Table.
JP-A-54-122253 discloses a process for preparing a cis alkylcyclohexanol comprising hydrogenating an alkylphenol in the presence of a ruthenium-alumina catalyst.
U.S. Pat. No. 2,927,127 discloses a process for preparing 4-tert.-butylcyclohexanol comprising hydrogenating 4-tert.-butylphenol in ethanol in the presence of the rhodium catalyst.
JP-A-3-173842 discloses a process for preparing 4-tert.-butylcyclohexanol comprising hydrogenating 4-tert.-butylphenol in the presence of a combined catalyst of Rh supported on a carrier and a boron fluoride type acid such as HBF.sub.4.
However, the cis-isomer content in 4-tert.-butylcyclohexanol which is prepared by the processes disclosed in JP-B-4213938, MARUZEN OIL TECHNICAL REVIEW and JP-A-54-122253, is still insufficient. The process of U.S. Pat. No. 2,927,127 achieves a high cis-isomer content, but the reaction must be performed under a high hydrogen pressure. Further, in the process of JP-A-3-173842, since the process uses the boron fluoride type acid, a workload is required to recover fluorine and boron, and generated acids such as HF corrode a production equipment.

Processes for preparing 4-tert.-butylcyclohexanol and 4-tert.-butylcyclohexyl acetate


In a method and apparatus for producing an ink jet printer head composed of a number of stacked modules, a piezoactuator plate is formed by metallizing opposite major faces of a plate of piezoelectric material, while leaving an unmetallized stripe on one of said major faces, thereby separating the metallization on that major face into two regions. A side face of the piezoelectric plate is also metallized, the side face extending substantially parallel to the unmetallized stripe, thereby electrically connecting one of the metallized regions on one major face to the metallized layer on the opposite major face. The metallized piezoelectric plate is then structured so as to produce a number of side-by-side piezoactuators therein, each piezoactuator having first and second electrodes formed by the respective metallization on the opposite sides of the plate. Respective electrical leads for the two electrodes of each piezoactuator can be electrically contacted to the same side of the plate, i.e. the side having the non-metallized stripe thereon.

1. Field of the Invention
The invention is directed to a plate-shaped piezoactuator assembly and to a method for manufacturing such an assembly, particularly for ink printer heads that are assembled of ink printer modules in stacked fashion.
2. Description of the Prior Art
Ink printer heads assembled of stacked ink printer modules are employed in small, fast printers that are in turn a component of moderate machines for franking postal matter or for printing addresses. Differing from standard office printers having line-by-line imprinting, printing in these machines ensues as a one-time franking impression in one pass of the postal matter. Corresponding to this significantly greater print width --approximately one inch--, the number of ink nozzles to be arranged under one another, and thus the number of piezoactuators in an ink printer head, is substantially larger than in the case of ink printer heads for office printers. In order to satisfy the current customer desire to print blocks with words as well as image characters in a postage meter machine with good print quality, printer resolutions of approximately 200 dpi are required, which means ink printer heads having the same number of nozzles and piezoactuators given a printing width of one inch. Of necessity, such ink printer heads are implemented in a planar or stacked structure; first, for reasons of allowable dimensions, and thus the packing density to be achieved and, second, for reasons of an economical manufacture (see German OS 42 25 799).
Plate resonators are usually utilized as piezoactuators, a piezoelectric material, for example lead-zirconate-titinate (PZT), being provided between two metal electrodes. The carrier plate, which simultaneously serves as the diaphragm plate over the ink pressure chambers, for the piezoactuators can be composed of glass, ceramic, plastic or metal. In the latter instance, one electrode can be omitted; however, a conductive glue in then required.
The nature of the arrangement, application and contacting of the piezoactuators is thereby a critical problem.
German OS 37 10 654 discloses a planar ink printer head assembled of metal plates. One of the plates is a diaphragm plate of nickel having a plate thickness of 0.03 mm on which piezolaminae having a diameter of approximately 1 mm are arranged as drive elements for the pressure chambers in a number corresponding to the number of nozzles. The diaphragm plate is followed by a pressure chamber plate of nickel having a plate thickness of 0.2 mm; this corresponds to the desired height of the pressure chambers.
The piezolaminae are individually glued or soldered onto the diaphragm plate in the regions above the pressure chambers. The assembly and adjustment expenditures required therefor are substantial.
The conditions are also analogous in another known ink printer head, disclosed in U.S. Pat. No. 4,703,333. Here, the coatings of the piezoactuators facing away from the diaphragm plate are contacted to the terminals of a ribbon conductor.
German OS 38 05 279 further discloses a piezoelectric ink printer head having a solid-state piezoceramic body, this ink printer head having transducers arranged parallel side-by-side. Each transducer includes a planar, piezoelectric drive element, a pressure chamber, an ink channel and a nozzle. The pressure chambers, the ink channels and the nozzles are fashioned as cavities in a piezoceramic body. Each drive element has an outer electrode, an inner electrode and an active piezoceramic layer arranged between the electrodes. The drive elements are acoustically separated from one another by incisions in the active piezoceramic layer. The incisions are intended to prevent cross-talk between the individual drive elements. For manufacturing the solid-state piezoceramic member, piezoceramic green films are stacked on top of one another, pressed in a vacuum and sintered. A piezoceramic green foil is structured by etching; the cavities that have arisen correspond to the shape of the pressure chambers, the pressure chamber outlet as well as the ink channels. The etching ensues with spray etching or laser etching. An intermediate green foil of piezoceramic that is metallized on one side is placed onto the structured piezoceramic green foil. After the sintering, the piezoceramic of the intermediate green foil forms the pressure chamber walls, whereby the metallization lies at that side facing away from the pressure chambers. The metallization is produced by printing the intermediate green foil with a metal paste. After the sintering, it forms the inner electrodes connected to one another. An upper piezoceramic green foil is arranged on the intermediate green foil and the active piezoceramic layers arise therefrom after sintering.
After the sintering of the stacked and pressed piezoceramic green foils, the openings of the ink channels are uncovered by removing material on the basis of mechanical processing. The outer electrodes are applied onto the outer side of the active piezoceramic layers by sputtering using a mask or by silkscreening. This is followed by the polarization of the transducers and the separation of the drive elements. The piezoceramic member that has arisen in this way is contacted with terminals of a terminal ribbon and is introduced into a housing or a retainer frame.
In another known method for manufacturing a piezoceramic element for ink jet printers, see German OS 37 33 109, and that is likewise based on the sintering of piezoceramic green foils, sintering temperatures from 1100-1300.degree. C. in an oxygen atmosphere are required. Platinum or metals of the platinum group are utilized as electrode material that is suitable for the sintering process. These two latter solutions have the disadvantage that time-consuming and energy-consuming high-temperature processes and expensive electrode material are required. Moreover, only the finished, solid-state piezoceramic body can be polarized. The electrode material must be resistant to corrosion with respect to the ink since one electrode is accommodated in the ink chamber.
German OS 38 04 165 also discloses a method for equipping an ink jet print head with piezoactuators, whereby a piezoceramic plate is first firmly joined to a diaphragm plate and only then does a separation of the piezoactuators from the piezoceramic plate ensue. The diaphragm plate is composed of glass and the side thereof facing toward the piezoceramic plate provided with a zinc or nickel oxide layer. The two plates are joined with a glue. The piezoactuators are detached with a separating means such as a laser beam or a saw. In this way, the piezoceramic plate serves as an aid to assembly and prevent an incorrect polarization. The metal oxide layer on the glass plate constitutes the common electrode for the piezoactuators. A conductive glue is required so that a reliable contact is present between one side of the piezoactuator and the metal oxide layer. As is known, metal layers on a glass substrate have poor adhesion. Since the joint between the metallized glass diaphragm and the piezoactuators is subject to high mechanical loads due to the periodic oscillations, delamination of the metal layer from the glass can occur, and thus a failure of the printer module can result.

Arrangement for plate-shaped piezoactuators and method for the manufacture thereof


A control method in a printing apparatus includes printing, by a printing unit, an adjustment image for adjusting a printing position on a sheet, conveying, by a conveying unit, the sheet on which the adjustment image is printed, reading, by a reading unit, an image to generate image data, the reading unit being executable to perform reading by a first reading method for reading an image of a sheet without conveying the sheet or a second reading method for reading the image of the sheet while conveying the sheet, and determining, based on that a type of the sheet on which the adjustment image is to be printed is a specific type, to read the adjustment image by the first reading method.

Field of the Invention
The present invention relates to a printing apparatus for printing an image on a sheet, a control method for the printing apparatus, and a storage medium.
Description of the Related Art
There is an image forming apparatus that reads a chart with a black image having a predetermined width being printed thereon in advance by using an auto document feeder (ADF) to diagnose misregistration at a leading edge (see Japanese Patent Application Laid-Open No. 2005-176045).
To read a document by using an ADF, for example, a document placed on a document tray of the ADF is conveyed while an image of the document is read at a fixed position of an optical system. To read a document by using a document positioning plate, for example, a document placed on the platen glass (document positioning plate) is fixed while an optical system is moved to read an image of the document.
For example, when images of a plurality of documents are read, it is more desirable to use the ADF for reading them than to use the document positioning plate for reading them. The reason is that the plurality of documents can be placed on the document tray of the ADF and the documents can be separated and conveyed one by one. This can reduce time taken for a user repeatedly placing the documents.
An amount of shift of a printing position depends on physical properties of the sheet to print. Thus, for example, when a shift in the printing position with respect to a sheet of high grammage is checked, a black image having a predetermined width needs to be printed on the sheet of high grammage to output a chart. The chart of high grammage is more desirably read by using the document positioning plate than by using the ADF. The reason is that the chart of high grammage is difficult to bend, and when the chart is conveyed from the document tray of the ADF, the chart may fail to form a loop and can cause a jam on the way.
However, the image forming apparatus discussed in Japanese Patent Application Laid-Open No. 2005-176045 scans a chart by using the ADF to diagnose misregistration at the leading edge. As a result, with a technique discussed in Japanese Patent Application Laid-Open No. 2005-176045, a jam can occur when a specific chart is scanned (for example, chart of high grammage) by the ADF, and the amount of shift of the registration at the leading edge may fail to be obtained.

Printing apparatus, control method for printing apparatus, and storage medium


A differential amplifier includes: a constant current source; first and second field effect transistors whose respective gates are imparted with positive-phase and negative-phase input signals and whose sources commonly connected to each other, the constant current source being connected to a common node of the sources; first and second loads serving as current paths for respective drain currents of the first and second field effect transistors; an amplifying unit which outputs positive-phase and negative-phase output signals which are amplified in response to the respective drain voltages of the first and second field effect transistors; and a current path generator which generates first and second current paths parallel to the respective first and second field effect transistors for a predetermined period of time at the time of start-up of the differential amplifier.

The present invention relates to a differential amplifier that performs differential amplification of two-phase input signals of differential-type having two a positive phase and a negative phase.
FIG. 4 is a circuit diagram showing an example configuration of an analogue circuit using a differential amplifier 1 that is an example related-art differential amplifier. In the illustrated example, a high potential power line of the differential amplifier 1 is connected to a power source of a source voltage AVDD, and a low potential power line of the same is connected to a ground. The differential amplifier 1 is broadly made up of a differential amplifying section 10 and source-grounded amplifying sections 20 and 30. The differential amplifying section 10 is made up of P channel field effect transistors 11 and 12 whose respective sources are commonly connected, to thus constitute a differential transistor pair; N channel field effect transistors 13 and 14 that act as loads of the transistors 11 and 12 and that constitute a current-mirror circuit; and a constant current source 15 that supplies the differential transistor pair with a constant current. Two-phase input signals Vip and Vin having positive and negative phases, subjected to differential amplification, are imparted to respective gates of the P channel field effect transistors 11 and 12.
The source-grounded amplifying section 20 is made up of an N channel field effect transistor 21 whose gate receives a drain voltage of the P channel field effect transistor 11 and whose source is connected to a ground; and a constant current source 22 that is interposed between the drain of the N channel field effect transistor 21 and the high potential power line. A voltage appearing at a node between the constant current source 22 and the drain of the N channel field effect transistor 21 acts as a positive phase output signal OP of the differential amplifier 1.
The source-grounded amplifying section 30 is made up of an N channel field effect transistor 31 whose gate receives a drain voltage of the P channel field effect transistor 12 and whose source is connected to a ground; and a constant current source 32 that is interposed between the drain of the N channel field effect transistor 31 and the high potential power line. A voltage appearing at a node between the constant current source 32 and the drain of the N channel field effect transistor 31 acts as a negative phase output signal ON of the differential amplifier 1.
In the illustrated example, an input terminal of the differential amplifier 1 for the positive phase input signal IP is connected to one end of an input resistor 41, and an input terminal of the differential amplifier 1 for the negative phase input signal IN is connected to one end of an input resistor 42, in which the input resistors 41 and 42 have the same resistance value. A feedback resistor 51 is interposed between an output terminal of the differential amplifier 1 for the negative phase output signal ON and the input terminal for the positive phase input signal IP. A feedback resistor 52 having the same resistance value as that of the feedback resistor 51 is interposed between an output terminal of the differential amplifier 1 for the positive phase output signal OP and the input terminal for the negative phase input signal IN.
In the foregoing configuration, the other terminal of the input resistor 41 is applied with the positive phase input signal Vip, and the other terminal of the input resistor 42 is applied with the negative phase input signal Vin. For instance, provided that a value of AVDD/2 is taken as an in-phase level, the input signals Vip and Vin are balanced differential signals that are symmetrical about the in-phase level. Since negative feedback acts on an illustrated analogue circuit by way of the resistors 51 and 52, the differential amplifier 1 differentially amplifies the input signals Vip and Vin in a state of virtually grounding the respective input terminals for the positive phase input signal IP and the negative phase input signal IN at the in-phase level; and outputs the positive phase output signal OP and the negative phase output signal ON that are results of amplification.
Incidentally, in the analogue circuit, such as that exemplified in FIG. 4, when operation of the entire circuit, including the differential amplifier 1 and a previous stage circuit (omitted from the drawings), is stable, the input signals Vip and Vin, which are symmetrical about the in-phase level, are imparted from the previous stage circuit to the differential amplifier 1. However, for instance, upon start-up of the overall analogue circuit, there is a case where the input signals Vip and Vin applied from the previous stage circuit to the differential amplifier 1 rise to a voltage close to, for instance, the source voltage AVDD, in excess of an in-phase input range that is a voltage range of an input signal where differential amplification is possible. In such a case, both the P channel field effect transistors 11 and 12 are turned off, and supply of current to the N channel field effect transistors 13 and 14 is interrupted. Therefore, N channel field effect transistors 13 and 14 are not turned on and remain in an OFF state. The respective drains of the P channel field effect transistors 11 and 12 enter a floating state, and voltages of the respective drains come close to 0V. For this reason, both the N channel field effect transistors 21 and 31 are turned off, and both the positive phase output signal OP and the negative phase output signal ON come close to the source voltage AVDD, thereby the positive phase output signal OP and the negative phase output signal ON are positively fed back to the respective input terminals for the negative phase input signal IN and the positive phase input signal IP. Due to this positive feedback, the negative phase input signal IN and the positive phase input signal IP are maintained in the vicinity of the source voltage AVDD. Once the analogue circuitry has entered such a state, there arises a problem of a time being consumed before the differential amplifier 1 gets out of an anomalous operating state and initiates normal differential amplification even when the input signals Vip and Vin applied from the previous stage circuit to the differential amplifier 1 subsequently assume normal waveforms that are symmetrical about the in-phase level.


A method and device for sending an aggregated CQI are provided by the disclosure. The method includes a terminal side receiving CSI-RS configuration information and/or interference measurement information sent from a base station side, the terminal side determining a sending sequence of aggregated CQI of each aggregated CSI-RS configuration resource and/or interference measurement resource according to a receiving sequence of the CSI-RS configuration information and/or interference measurement information, wherein each aggregated CSI-RS configuration resource and/or interference measurement resource is aggregated of at least one configuration CSI-RS configuration resource and/or interference measurement resource corresponding to the CSI-RS configuration information and/or interference measurement information, the terminal side sending the aggregated CQI to the base station according to the sending sequence. The disclosure resolves the problem in related art that the base station side cannot acquire the channel state of the terminal side accurately due to the fact that the base station side cannot acquire the CSI-RS configuration resource and/or interference measurement resource fed back by the terminal side corresponding to the aggregated CQI, thereby the interference between cells is reduced, and the throughput of system is improved.

After the long term evolution (LTE) system has gone through several releases of R8/9/10, R11 technology will be researched in the future. Currently, some R8 products are gradually commercially available, and R9 and R10 products need to be further planned.
After having gone through R8 and R9 stages, R10 adds many new properties on the basis of the former, for example, pilot frequency properties such as DMRS (Demodulation Reference Signal), CSI-RS (Channel State Information Reference Signal), transmission and feedback properties such as 8 antenna support and so on, especially eICIC (enhanced Inter-Cell Interference Cancellation) technology takes into account the interference avoidance technology among cells on the basis of taking into account R8/9 ICIC. For the technology which solves the interference problem among cells, at the initial stage of R10, cell interference avoidance in a homogeneous network is mainly taken into account, wherein what are mainly taken into account are eICIC technology and CoMP (Coordinated Multi-point) technology. Just as its name implies, CoMP is that a plurality of CSI-RS configuration resources and/or interference measurement resources coordinate to send data to one or more UE in the same time frequency resources or different time frequency resources. CoMP technology can reduce inter-cell interference, improve cell edge throughput and enlarge cell coverage. However, since the situation where the homogenous network introduces more scenarios is taken into account at the later of discussion, in view of the complexity of CoMP technology and the temporal limitation of R10 discussion, finally it is decided not to introduce additional CoMP standardization contents at R10 stage, however, design can be made by taking into account the demand of the CoMP part when designing CSI-RS, and therefore, CoMP technology is not discussed further after 60 bis conference.
At the initial R11 discussion SI (study item) stage, a unified evaluation architecture is determined by planning scenarios and various transmission technologies of CoMP, and it is proved that CoMP technology can obtain significant performance gain after two stages of CoMP evaluation. Recently completed CoMP SI conclusions are that it needs to further research JT (Joint Transmission), DPS (Dynamic Point Selection) with/without muting, CS (Coordinated Scheduling) with/without muting, CB (Coordinated Beamforming) in CoMP technology.
Before researching various technologies of CoMP, it needs to first take into account CoMP technology has what differences for R8/9/10 technologies, which includes how the control signalling of CoMP supports the notification of a CoMP measurement set, how to support the demands of different transmission technologies of CoMP and how a UE measures and reports the CSI (Channel State Information) and so on of a plurality of CSI-RS configuration resources and/or interference measurement resources. How a UE measures and reports the CSIs of a plurality of CSI-RS configuration resources and/or interference measurement resources is one of the primary problems to be solved. In the current discussion, the feedback of CoMP can be mainly divided into periodical feedback and non-periodical feedback, and aggregated channel information feedback and non-aggregated channel information feedback. The so-called aggregated channel information feedback refers to that the channel information about a plurality of CSI-RS configuration resources and/or interference measurement resources are aggregated into one piece of channel information of CSI-RS configuration resource and/or interference measurement resource for global feedback. For example, a measurement set contains two CSI-RS configuration resources and/or interference measurement resources, wherein the channel information about CSI-RS configuration resource and/or interference measurement resource 1 is H1, the channel information about CSI-RS configuration resource and/or interference measurement resource 2 is H2, and at this moment, the UE first aggregates the channel information about two CSI-RS configuration resources and/or interference measurement resources into a large piece of channel information, expressed with H=[H1; H2], and then measurement relevant calculation and feedback are performed. Non-aggregated channel information feedback can also be divided into independent single cell feedback and independent single cell feedback plus inter-cell correction information. The so-called independent single cell feedback refers to independently performing measurement relevant calculation and feedback according to the channel information about each CSI-RS configuration resource and/or interference measurement resource. The so-called independent single cell feedback plus inter-cell correction information refers to independently performing measurement relevant calculation according to the channel information about each CSI-RS configuration resource and/or interference measurement resource, and calculating the phase and/or amplitude information about each CSI-RS configuration resource and/or interference measurement resource and performing feedback. For feedback whereby aggregated channel information includes an aggregated CQI, aggregated CQI refers to that the CQI fed back by the UE side corresponds to the aggregated CQI for measuring one or more pieces of CSI-RS configuration information and/or interference measurement resource information, and the UE finds the time frequency location of a corresponding CSI-RS using a plurality of pieces of CSI-RS configuration information and/or interference measurement resource information, so as to perform measurement and obtain precoding weight information and obtain interference information using other pilot frequencies and then perform calculation, and at this moment, the UE assumes that there are CSI-RS configuration resources and/or interference measurement resources corresponding to one or more pieces of CSI-RS configuration information and/or interference measurement resource information sending data thereto, thus obtaining a CQI value corresponding to the joint transmission of the plurality of CSI-RS configuration resources and/or interference measurement resources. Since one aggregated CQI may correspond to an aggregation for measuring one or more pieces of CSI-RS configuration information and/or interference measurement resource information, for example, a measurement set may contain 3 pieces of CSI-RS configuration information and/or interference measurement resource information, and at this moment, there are 3 possibilities for aggregating one piece of CSI-RS configuration information and/or interference measurement resource information, there are 3 possibilities for aggregating two pieces of CSI-RS configuration information and/or interference measurement resource information, and there is one possibility for aggregating one piece of CSI-RS configuration information and/or interference measurement resource information, totally 7 possibilities, and therefore, there are many possibilities for an aggregated CQI, each possibility can be referred to as an aggregation possibility, that is, an aggregated CSI-RS configuration resource and/or interference measurement resource is aggregated of at least one configuration CSI-RS configuration resource and/or interference measurement resource, and the current constituent manner is referred to as aggregation possibility.
For traditional R8/R9/R10, a user merely needs to feed back the CSI of the serving cell, and therefore, over the same carriers, it merely needs to take into account single cell capacity for periodical feedback and non-periodical feedback, especially for a PUCCH, it merely needs to optimize the feedback of a single cell. Currently, taking into account coding and HARQ (Hybrid Adaptive Request Repeat) bit number and so on, for one UE, at most 11 bit CSI feedback is supported in one PUCCH (Physical Uplink Control Channel) uplink subframe. The constituent of 11 bits at most may take into account 4-bit PMI (Precoding Matrix Indicator) and two code word 7-bit CQI (Channel Quality Indicator) (taking into account the differential feedback of the CQIs among different code words). Since CoMP needs to take into account the CSI for a plurality of cells, it needs to have N*11-bit PUCCH capacity capability, however, the current PUCCH capacity cannot meet this requirement, a rational feedback solution is needed to solve the problem of insufficient PUCCH capacity. It is easily conceivable of compressing the feedback signalling, however, CoMP has relatively high requirements on the accuracy of CSI, especially, JT even JT-MU proposes relatively high requirements on the accuracy of CSI, and therefore, the performance loss caused by compression may lead to the decreasing of CoMP performance gain. Another consideration is to improve the capacity of the PUCCH, and this requires to redesign the feedback format of the PUCCH, which will inevitably bring significant standardization efforts. If it is taken into account the feedback requirements for CSI among different modes of CoMP and ensure adaptive switching among different modes, this feedback design may be more complicated. Thus, in discussion, it is taken into account information among CSI-RS configuration resources and/or interference measurement resources which can ensure the flexible switching of coordinated sending modes and/or introduce the concept of aggregated CQI. In a recent conference, it is discussed that the aggregated CQI can obtain and introduce performance similar to information among CSI-RS configuration resources and/or interference measurement resources+aggregated CQI, at this moment, no additional feedback of information among CSI-RS configuration resources and/or interference measurement resources is introduced, and currently, the conference still discusses whether to take into account the feedback of information among additional CSI-RS configuration resources and/or interference measurement resources. However, the two solutions mentioned above take into account the concept of aggregated CQI, and for the concept of aggregated CQI, it needs to feed back a CQI value generated by the aggregation of a plurality of CSI-RS configuration resources and/or interference measurement resources, the number of aggregated CSI-RS configuration resources and/or interference measurement resources can be a combination of any number of CSI-RS configuration resources and/or interference measurement resources in all the CSI-RS configuration resources and/or interference measurement resources in the measurement set, for example, the measurement set includes 6 CSI-RS configuration resources and/or interference measurement resources, at this moment, possible combinations include 63 situations, and if it is taken into account to limit the maximum number of CSI-RS configuration resources and/or interference measurement resources, the combinations include 41 possibilities. If the UE feeds back a plurality of CQIs in one feedback or feeds back a plurality of aggregated CQIs of various situations in a plurality of feedbacks, how the base station side learns the aggregated CQI fed back by the UE correspond to the combination of which CSI-RS configuration resources and/or interference measurement resources, this point needs to be specified uniformly at the base station side and the UE side, otherwise, the base station side cannot learn the received aggregated CQI correspond to the combination of which CSI-RS configuration resources and/or interference measurement resources.
Aiming at the problem mentioned above, no effective solution has been presented.

Method and device for sending aggregated CQI


A biochip and apparatus is disclosed for performing biological assays in a self-contained microfluidic platform. The disposable biochip for multi-step reactions comprises a body structure with a plurality of reagent cavities and reaction wells connected via microfluidic channels; the reagent cavities with reagent sealing means for storing a plurality of reagents; the reagent sealing means being breakable and allowing a sequence of reagents to be released into microfluidic channel and reaction well; and the reaction well allowing multi-step reactions to occur by sequentially removing away the residual reagents. The analysis apparatus can rapidly, automatically, sensitively, and simultaneously detect and identify multiple analytes or multiple samples in a very small quantity.

Current hospital and clinical laboratories are facilitated with highly sophisticate and automated systems with the capability to run up to several thousand samples per day. These high throughput systems have automatic robotic arms, pumps, tubes, reservoirs, and conveying belts to sequentially move tubes to proper position, deliver the reagents from storage reservoirs to test tubes, perform mixing, pump out the solutions to waste bottles, and transport the tubes on a conveyer to various modules. Typically three to five bottles of about 1 gallon per bottle of reagent solutions are required. While the systems are well proved and accepted in a laboratory, they are either located far from the patients or only operated once large samples have been collected. Thus, it often takes hours or even days for a patient to know their test results. These systems are very expensive to acquire and operate and too large to be used in point-of-care testing setting.
The biochips offer the possibility to rapidly and easily perform multiple biological and chemical tests using very small volume of reagents in a very small platform. In the biochip platform, there are a couple of ways to deliver reagent solutions to reaction sites. The first approach is to use external pumps and tubes to transfer reagents from external reservoirs. The method provides high throughput capability, but connecting external macroscopic tubes to microscopic microchannel of a biochip is challenging and troublesome. The other approach is to use on-chip or off-chip electromechanical mechanisms to transfer self-contained or preloaded reagents on the chips to sensing sites. While on-chip electromechanical device is very attractive, fabricating micro components on a chip is still very costly, especially for disposable chips. On the other hand, the off-chip electromechanical components, facilitated in an analysis apparatus, that are able to operate continuously for a long period of time is most suited for disposable biochip applications.
The microfluidics-based biochips have broad application in fields of biotechnology, molecular biology, and clinical diagnostics. The self-contained biochip, configured and adapted for insertion into an analysis apparatus, provides the advantages of compact integration, ready for use, simple operation, and rapid testing. For microfluidic biochip inanufactirers, however, there are two daunting challenges. One of the challenges is to store reagents without losing their volumes over product shelf life. The storage cavity should have a highly reliable sealing means to ensure no leak of reagent liquid and vapor. Although many microscale gates and valves are commercially available to control the flow and prohibit liquid leakage before use, they are usually not hermetic seal for the vaporized gas molecules. Vapor can diffuse from cavity into microchannel network, and lead to reagent loss and cross contamination. The second challenge is to deliver a very small amount of reagents to a reaction site for quantitative assay. The common problems associated are air bubbles and dead volume in the inicrochannel system. An air bubble forms when a small channel is merged with a large channel or large reaction area, or vice versa. Pressure drops cause bubble formation. The air bubble or dead volume in the microfluidic channel can easily result in unacceptable error for biological assay or clinical diagnosis.
Several prior art devices have been described for the performance of a number of microfluidics-based biochip and analytical systems. U.S. Pat. No. 5,096,669 discloses a disposable sensing device with special sample collection means for real time fluid analysis. The cartridge is designed for one-step electrical conductivity measurement with a pair of electrodes, and is not designed for multi-step reaction applications. U.S. Pat. No. 6,238,538 to Caliper Technologies Corp. discloses a method of using electro-osmotic force to control fluid movement. The microfabricated substrates are not used for reagent storage. U.S. Pat. No. 6,429,025 discloses a biochip body structure comprising at least two intersecting microchannels, which source is coupled to the least one of the two microchannels via a capillary or microchannel. Although many prior art patents are related to microfluidic platform, none of them discloses liquid sealed mechanism for self-contained biochips. They are generally not designed for multi-step reactions application.

Self-contained microfluidic biochip and apparatus


An electrochromic display is disclosed which comprises an array side substrate (10) on which a pixel electrode (15) and an electrochromic layer (30) are formed, a color filter side substrate (50) on which a counter electrode (53) and an electrochromic layer (54) are formed, and an electrolytic layer (80) injected between the array side substrate (10) and the color filter side substrate (50). By forming the pixel electrode (15) of a reflective electrode material, it becomes unnecessary to add a coloring agent in the electrolytic layer (80) for enhancing contrast and therefore the electrolytic layer (80) can be made thin.

1. Field
The present invention relates to an electrochromic display that displays images by utilizing an electrochromic phenomenon.
2. Description of the Related Art
Electronic paper is getting more and more attention as a new display medium that combines the characteristics as paper, which is no need of information holding energy, can be securely saved, easily read, quickly readable and so on, and the characteristics as an electronic display capable of rewriting information and so on.
Various types are known as a display principle in the electronic paper. For example, it is a microcapsule type electrophoretic display method where capsules enclosing positively and negatively charged black and white particles are moved between electrodes. Further, it is a twist ball method where the direction of spherical particles colored in black and white are controlled. These methods perform display by utilizing a physical phenomenon.
On the other hand, there is known a method that performs display by utilizing a chemical phenomenon. Among others, one utilizing an electrochromic phenomenon is known where voltage is applied between electrodes to cause coloring or deletion by oxidation-reduction reaction. This is described in Japanese Patent Laid-Open No. 10-232413 publication, for example.
In the case of an electrochromic display utilizing the electrochromic phenomenon, it is constituted that electrodes are formed on each of substrates that make a pair, an electrochromic film is formed on the electrodes, and an electrolytic layer is sandwiched between the both substrates. Coloring agent such as white particles is usually contained in the electrolytic layer for improving contrast. However, the coloring agent is contained in the electrolytic layer at a fixed ratio and target contrast cannot be secured when the electrolytic layer is made too thin, and manufacturing of a thin electrochromic display is thus limited to a certain level.


A method and system (50) reduce the apparent time between turning on a computer (10) and making available the computer (10) processing capability. The method and system (154) include the necessary steps for and instructions and circuitry for generating a startup command for the computer. The method and system include displaying within a shortened predetermined time period an interface screen (14) that includes a plurality of interface checkpoints (24) and address data relating to application programs associated with the user interface checkpoints. The shortened predetermined time period has a duration substantially shorter than the period associated with booting (60) the associated application programs. In turning off computer (10), the method and system (50) include generating a shut down command (70) to computer (10) and storing interface screen (14) and any data files (78) that are open at the time of turning off computer (10). The interface screen (14) and data files are stored so that upon subsequently turning on computer (10), computer (10) displays interface screen (14) in the shortened predetermined time.

As desktop and notebook computing systems have become increasingly complex, capable of performing multimedia applications, communicating on networks, and displaying varied and multi-dimensional images, the type and number of software programs that the computer must boot or initialize to become operable have dramatically increased. In addition, the software for many different types of peripherals, including hard drives, CD-ROM devices, printers, facsimile, and other peripheral software that a computer must initialize adds yet another level of complexity to computer operation. Known methods for starting a computer that include all of these many software programs consume as much as two, three, and four minutes from the time that a user first activates the computer's power button or switch.
Computer users, however, desire to have computers operate like a calculator. That is, they desire the computer to operate immediately after being turned on. With today's computers, however, this is not possible, because a computer must, prior to being operational, operate BIOS software and initialize hardware devices drivers to associate hardware peripherals the central processor unit.
User's also desire to have a computer that can be immediately shut down. This cannot happen with today's computers, because of the need to close the many files that may have been open during the computer's operation. In fact, computer users desire to simply press a key on the computer keyboard and have the computer immediately go to a shutdown condition.
There have been some attempts to achieve this level of operation by establishing a hibernate mode of operation for the central processing unit. This hibernate mode of operation, while operating the computer in a reduced mode of operation, still requires that the central processing unit have some applied power. Whereas this may not be a problem for desktop computers, this mode of operation is not practical for notebook computers.
A first limitation of a hibernate mode of operation derives from the fact that the central processing unit still must draw power. Because notebooks operate from battery power, the hibernate mode of operation depletes the battery power source.
Another limitation of a hibernate mode of operation comes from the fact that the central processing unit still operates during this mode, albeit at a minimal level of operation. Federal Aviation Administration (FAA) regulations prohibit the passenger use of electronic devices during aircraft takeoff and landing due to the electromagnetic frequency (EMF) emissions from these electronic devices. Even though the central processing unit of a notebook or laptop computer may be operating at a lower rate during the hibernate mode, EMF emissions still occur in violation of the FAA regulations. Accordingly, the hibernate mode of operation is not practical for notebook computer operation during air travel.
Still another limitation of the hibernate and similar modes of operation is that these modes of operation assume that all applications and data files are to be saved to the computer's hard drive. This assumes a sufficient amount of storage on the hard drive. In addition, the hibernate mode of operation assumes that the user only desires to restore to operation those files that were saved upon entering the hibernate mode.
There is, therefore, no known way to effectively eliminate the wait period of making computers, whether they are desktop or notebook computers, available to users.

Method and system for maximizing the apparent initial processing capability of a computer


In some embodiments, an apparatus includes an electronic device that has a ground to receive an electrostatic discharge. A radiation detector, mounted on the electronic device, generates a differential signal in response to the electrostatic discharge.

1. Field of the Invention
The present invention relates to electronic devices, and in particular, to the testing of electronic devices.
2. Description of Related Art
Control of static charge in test and assembly of semiconductor components is an activity with increasing importance as the components become more sensitive to electrostatic discharge (ESD). Common in test and assembly is the practice of monitoring certain equipment that might produce damaging ESD events, such as socketing of a charged component. One known method for monitoring electrostatic discharge is to use a near-field ball antenna. The antenna is positioned approximately 15–30 cm from the equipment and components to be monitored. An oscilloscope is used to pick up electromagnetic interference (EMI) signal caused by an ESD event. Components tested under a charged device model (CDM) are typically subjected to simulated ESD pulses using an automated CDM testing process.
The EMI signals picked up by the prior art antenna have an oscillatory waveform. This is because the component under test is coupled to a metal ground. The electrostatic discharge from the ESD event is discharged into the metal ground and the oscillations generated occur in the metal ground. These oscillations occur despite the fact that the ESD event is a largely unipolar event (i.e., a brief current spike) from the point of view of the charged component generating the electrostatic discharge. This is because the component is a small electronic component relative to the much larger metal ground. The sudden injection of current into the large metal ground causes ringing in that metal ground, with the resulting radiation (EMI signals) being picked up by the near-field ball antenna. Having spread into the large expanse of the metal ground, the charge does not find its way back into the small component in a significant way, so the unipolar pulse at the component is consistent with continuing electrical oscillations in the metal ground as the energy dissipates.

Radiation detector for electrostatic discharge


A combination including a cabinet and a shredder. The cabinet including a cabinet housing having a top, a front, a back and two sides, a drawer supportable by the cabinet housing and operable to selectively support materials therein, the drawer being movable between an open position and a closed position and the shredder being supported by the cabinet housing and at least partially positioned within the cabinet housing, the shredder having an inlet for materials to be fed into the shredder to be shredded to form shredded material and an outlet through which shredded material is dispensed.

Paper shredders are commonly placed on an office floor or stacked on desks, book shelves or other office furniture or cabinets along with printers, fax machines or other office equipment. Such stacking or other placement of office equipment is commonly unsightly and inefficient.
In other arrangements, paper shredders have been placed on cabinets having pivotal doors. The pivotal doors provide access to the interior of the device where a collection bag is supported for collection of shredded material from the shredder. The sole function of the cabinet is to support the collection bag therein. In such an instance, efficient use of the office space is not achieved because the device is occupying the same or more office space than the shredder and is not providing any additional capabilities.


Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a circuit adapted to reduce standby leakage current in a semiconductor memory device comprising memory cells. The circuit comprises a bias signal generator adapted to generate a bias signal, wherein a voltage level of the bias signal is set in accordance with a result of a standby leakage current test. The circuit further comprises a ground voltage controller adapted to receive the bias signal from the bias signal generator and to control a level of a voltage apparent on a virtual ground terminal in response to the bias signal while the semiconductor memory device is in a standby mode.

1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. In particular, embodiments of the invention relate to a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit.
This application claims priority to Korean Patent Application 10-2005-0131194, filed on Dec. 28, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Generally, standby current in a semiconductor memory device may be current that leaks from a semiconductor memory device while the semiconductor memory device is in a standby mode. Standby current may also be referred to herein as standby leakage current.
An active mode of a semiconductor memory device may be a mode in which peripheral circuits of the semiconductor memory device operate to store data in memory cells of the semiconductor memory device or output data stored in the memory cells to an element(s) outside of the semiconductor memory device. A standby mode of a semiconductor memory device may be a mode in which read and write operations are not performed on the memory cells. In addition, peripheral circuits may be disabled and the amount of power consumed by the peripheral circuits may be reduced while the semiconductor memory device is in the standby mode.
When a semiconductor memory device is in a standby mode for a relatively long amount of time, the semiconductor memory device enters a deep power down mode in order to stop the operation of peripheral circuits to thereby reduce the amount of power consumed by the semiconductor memory device in the standby mode.
FIG. 1A is a timing diagram illustrating timings for an exemplary entry of a conventional semiconductor memory device into a deep power down mode, and FIG. 1B is a timing diagram illustrating timings for an exemplary exit of a conventional semiconductor memory device from the deep power down mode. The deep power down mode will now be described briefly.
The deep power down mode is controlled by an external command. In the semiconductor memory device, after a precharge time tRT elapses (precharge time tRT is initiated in accordance with a precharge command), the semiconductor memory device enters a deep power down mode DPD and then exits deep power down mode DPD in response to a clock signal CLOCK and in accordance with the respective states of signals input through an external signal pin of the semiconductor memory device. The signals may be a chip selection signal CS, a row address strobe /RAS, a column address strobe /CAS, a write enable signal WE, and a clock enable signal CKE.
An exemplary process in which a semiconductor memory device enters and exits deep power down mode DPD will now be described. When chip selection signal CS, clock enable signal CKE, and write enable signal WE each have a logic low level; and row address strobe /RAS and column address strobe /CAS each have a logic high level, the semiconductor memory device enters deep power down mode DPD in response to clock signal CLOCK. Then, regardless of the respective logic levels of chip selection signal CS, row address strobe /RAS, column address strobe /CAS, and write enable signal WE, deep power down mode DPD is completed (i.e., the semiconductor memory device exits deep power down mode DPD) when clock enable signal CKE transitions to a logic high level (see FIG. 1B).
Standby leakage current will now be described using a Static Random Access Memory (SRAM) device as an exemplary semiconductor memory device in which standby leakage occurs.
A unit-memory cell of SRAM is generally configured to store data using a latch comprising two inverters connected with one another. Data may be stored in a memory cell using a bit line pair and may also be output from the memory cell. In addition, bit line pairs are precharged with a voltage having a given level before data is input or output.
FIG. 2 is a circuit diagram illustrating standby leakage current in a portion of a conventional SRAM device. FIG. 2 illustrates a unit-memory cell of an SRAM device, and standby leakage current in the unit-memory cell is represented by arrows.
Standby leakage current in the SRAM device may be divided into gate leakage current (represented by gate leakage current arrows A1) and sub-threshold leakage current (represented by sub-threshold leakage current arrows A2). Referring to transistors PM11, PM12, NM11, NM12, NM13, and NM14 of FIG. 2, a gate leakage current arrow A1 may indicate standby leakage current passing between a drain terminal and a gate terminal, or between a source terminal and a gate terminal, of one of the transistors mentioned previously. A sub-threshold leakage current arrow A2 may indicate standby leakage current flowing between one or more pairs of drain and source terminals.
When the semiconductor memory device partially illustrated in FIG. 2 is in the standby mode, the voltage level apparent on word line WL within the semiconductor memory device has a logic low level, so access transistors NM13 and NM14 are turned OFF. Thus, first and second output terminals N1 and N2 of the first and second inverters illustrated in FIG. 2, which may be storing data, are electrically insulated from bit line pair BL, BLB. The first inverter of FIG. 2 comprises PMOS transistor PM11 and NMOS transistor NM11, and the second inverter of FIG. 2 comprises PMOS transistor PM12 and NMOS transistor NM12.
Then, bit line pair BL, BLB is precharged to a power source voltage VCC by a bit line precharge circuit (not shown). When bit line pair BL, BLB is precharged to a power source voltage VCC, standby leakage current (which is indicated by arrows A1 and A2) flows. The magnitude of the standby leakage current indicated by arrows A1 and A2 is proportional to the magnitude of power source voltage VCC.
In general, power source voltages VCC having various voltage levels are applied to a semiconductor memory device according to strictly defined specifications so as to properly control the device's operating characteristics. The magnitude of standby leakage current (comprising gate leakage current and sub-threshold leakage current) is proportional to the magnitude of power source voltage VCC. When a high level power source voltage HVCC (i.e., a power source voltage VCC having a relatively high voltage level) is applied in the semiconductor memory device, the amount of standby leakage current may increase. Many attempts to reduce the amount of standby leakage current suffered by memory cells based on varying the voltage level of power source voltage VCC have been proposed, as in, for example, U.S. Pat. Nos. 6,970,374; 6,611,451; and 5,764,566. The subject matter of each of the preceding patents is hereby incorporated by reference in its entirety.
Two of the various methods used to reduce standby leakage current will be described herein. The first method is an exemplary method for increasing the threshold voltage Vth of MOS (Metal Oxide Semiconductor) transistors within a memory cell, and the second is a method for differentially controlling the levels of the voltages apparent on respective ground connection terminals Vgnd of memory cells during an active mode and a standby mode, etc. Each ground connection terminal Vgnd may be referred to herein as a virtual ground terminal Vgnd in order to clearly distinguish it from ground voltage VSS.
One shortcoming of this method of increasing the threshold voltage Vth of a MOS transistor in a memory cell is that certain operating characteristics of the memory cell may become impaired when a relatively low external power source voltage LVCC is applied in the semiconductor memory device.
In the method for differentially controlling the level of the voltage apparent on a virtual ground terminal Vgnd of memory cells in an active mode and in a standby mode, virtual ground terminal Vgnd may be set to a voltage level substantially equal to a ground voltage VSS when the semiconductor memory device is in the active mode, and a voltage apparent on virtual ground terminal Vgnd may be set to a voltage level greater than ground voltage VSS when the semiconductor memory device is in the standby mode. Thus, the method may reduce standby leakage current by reducing a power source voltage VCC and reducing a margin between the level of the power source voltage VCC and the level of the voltage apparent on virtual ground terminal Vgnd.
FIG. 3 is a circuit diagram illustrating a portion of an exemplary conventional SRAM device.
Referring to FIG. 3, the SRAM device of FIG. 3 may comprise a memory cell sector 30, a bias sector 32, and a sleep sector 34. Memory cell sector 30 may comprise memory cells adapted to store data. In addition, bias sector 32 controls the voltage level of virtual ground terminal Vgnd when the SRAM device of FIG. 3 is in the standby mode. Bias sector 32 comprises NMOS transistors NM31 to NM34. NMOS transistors NM31 to NM34 receive bias signals bias0 to bias3, respectively, and control an operational resistance apparent in bias sector 32. The operational resistance is calculated in accordance with the level of the voltage apparent on virtual ground terminal Vgnd and the amount of current flowing between drain and source terminals of NMOS transistors NM31 to NM34. The voltage apparent on virtual ground terminal Vgnd is represented herein as the product of a current Ioff, which is the current flowing between source and drain terminals of NMOS transistors NM31 to NM34 when the SRAM device is in a standby mode, and the operational resistance of NMOS transistors NM31 to NM34.
That is, the voltage apparent on virtual ground terminal Vgnd may be expressed as Vgnd=Ioff*Rbias_on, wherein Rbias_on represents the operational resistance of NMOS transistors NM31 to NM34.
Sleep sector 34 is controlled in accordance with a sleep signal Sleep, and comprises a sleep transistor NM35 that is turned ON when the memory cell sector is in an active mode and is turned OFF when the memory cell sector is in a standby mode.
As described above, the SRAM device partially illustrated in FIG. 3 may reduce standby leakage current by controlling the voltage level apparent on virtual ground voltage Vgnd through bias sector 32.
In addition, various mobile applications require very low standby leakage current. In these applications, the amount of standby leakage current is very sensitive to variations in the fabrication processes used to manufacture the constituent semiconductor device, variations in the applied external power source voltage (i.e., the level of a voltage received form an external power source), and temperature.
However, a limitation in conventional semiconductor memory devices is that conventional semiconductor memory devices do not account for process variation or temperature variation when reducing standby leakage current.
Conventional semiconductor memory devices suffer from problems such as data loss and the consumption of excess power as a result of standby leakage current caused by variations in temperature, external power source voltage, and fabrication process (hereafter "process scatter").

Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit


An automatic heat transfer press for imprinting sublimation transfers onto mugs and the like by utilizing heat and contact pressure. The press has three vertically stacked, general sections: a heating chamber, a base, and a cooling chamber interconnecting the heater chamber and base. The heating and cooling chambers are enclosed by a casing. The heating chamber contains the press's two heating units, one for heating the external surface of the mug and the other for heating the interior the mug. The press utilizes a stainless steel sheathed, mineral insulated band heater with a multizone, uniplanar heater element.

This invention relates to heat transfer presses, and more particularly to an automatic heat transfer press for tubular structures and containers.
Printed cups, mugs, glasses and other tubular structures (hereinafter collectively "mugs") have become increasingly popular over the past few years, especially as a marketing and advertising tool. There are three basic approaches to printing onto mugs: decal printing, screen printing, and heat transfer.
Decal printing, especially glass decal printing, involves a glass frit arranged onto a decal to form the desired print. The decal is then pressed against the glass or ceramic surface to be imprinted and both the decal and glass placed in an oven. The temperature is gradually increased until the temperature reaches 900 to 1900 degrees F. The process to prepare the decal takes approximately one day for each color and several hours to "fire" the decal onto the mug. Built up color printing is possible, but full color printing is not possible. Whereas in full color printing primary colors can be mixed to attain the desired color, built color printing requires the initial use of the desired end color, the mixing of colors cannot be used.
With screen and pad printing, special glass/ceramic inks can be applied to the surface of the ceramic/glass surface to be imprinted, normally in one color, although two or three colors are possible where close registration is not critical. The printed item is then placed in an oven and the temperature is gradually increased to 900 degrees F. The heating process takes several hours. Generally "firing" takes place after each color on multi-colored designs.
Heat transfer printing is the printing of sublimation transfers onto mugs by heating. The heat transfer process involves transferring sublimation transfers by heat and contact pressure. There are many types of sublimation transfers that can be imprinted. Copy machines can produce a sublimation transfer; video printers can generate a sublimation transfer; laser printers, printing presses, etc. The key to all these images is that they all use a form of "sublimation" ink. The "sublimation" transfer is made up of two basic parts: the transfer release paper and the sublimation dyes. The sublimation dyes are printed onto the transfer release paper. The heat transfer process heats the transfer paper and sublimation dye to a certain temperature. As the temperature of the mug rises during the cycle time, the sublimation dyes start to release from the transfer paper and are transmitted to the coating on the mug. This transitiveness of sublimation dyes from the transfer paper to the coated mug is the key to any heat transfer process. The different types of sublimation transfers work best at different operating temperatures. For example, video processes and films require lower temperatures during the transfer process.
Decal printing is impractical and inflexible for point of sale applications in that the decal printing must be done when the mug itself is fired. Although screen printing has been the historic method of printing onto coffee mugs, the process and equipment required makes it very difficult to print a mug at a point of sale. Heat transfer printing overcomes the limitations of screen and decal printing in that printing may be done at a point of sale, quickly and flexible. Heat transfer printing with sublimations can produce inexpensive "one-of-a-kind" items. The market for cylindrical shaped glass and ceramic products, such as coffee mugs and glasses, lends itself to the one of a kind market. It is also possible to produce full color reproductions of full color designs. The time required to impart a design using heat transfer sublimation can be a matter of seconds and minutes versus hours or days with other technologies.
With heat transfer printing there are several major factors that determine the quality of printing. Among the major variables are: the mug structure, the heat transfer process, mug coating, and transfer placement.
All mugs are different. Each mug has a different wall thickness, ceramic composition, coating, thickness of coating, physical dimensions (inside and outside diameter), slopes, angles, curves, post-curing time of coating, chemical make-up, etc. The differences in mug structures, even two that are nominally alike, must be taken into account by any printing process.
Mug coating plays a major part in the ability to apply a sublimation transfer to a ceramic mug. Ceramic mugs have a hardened layer of material that resists allowing sublimation dyes to impregnate the surface. Mugs to be sublimation printed are coated with a layer of special polymer. These polymers are receptive to sublimation dye, aesthetically acceptable, adhere permanently, and in the case of containers for holding food and beverages, the coating is inert and safe to come in contact with food, skin and may be ingested without causing harm.
Adhering the sublimation transfer to a mug is a critical part of mug printing. Care must be taken to ensure that the transfer paper is tight.
In order to print using sublimation, a properly prepared transfer must be held in tight contact with the receptive surface while heat is applied. The heat and pressure must continue for a sufficient time to allow the sublimation process to complete itself.
The first historic attempts at producing sublimation transfer devices involved the use of cylindrical block heaters. These are heaters which have elements forming two approximate 100 degree arcs about the exterior of the mug. The elements apply heat and pressure to the sublimation transfer to effectuate the imprint transfer. Block heaters have several limitations. The radius of the object to be printed is generally limited to the radius of the heater block. A smaller or larger circumference item does not fit accurately enough into the heat block to produce a uniformly printed surface. Natural irregularities in the surface of the cylindrical container, especially on glass and ceramic objects, create hot spots (places where the pressure is very high) or cold spots (places where the pressure contact is too low). To resolve the latter problem, it is common to place a flexible silicon rubber pad with silicon on the heater block. The rubber pad improves the contact pressure between the heater block and the cylindrical glass or ceramic surface. However, the rubber pad also acts as a heat insulator thereby making it more difficult to attain the needed temperature.
To overcome the limitations of heater blocks heat transfer printing devices for sublimation transfers have been produced using a flexible heater coated with silicon rubber. Such devices allow the mug to be printed up to 300 degrees of the cylinder's circumference. The use of a flexible heater also helps to solve the problem of producing acceptable prints in spite of the natural irregularities in the surface of the glass or ceramic cylindrical surface. The flexible heater also increases the range of cylinder diameters that can be printed.
There are, however, limitations when printing with silicone flexible heaters. The flexible heater has to perform two functions, one of heating and the other of creating uniform contact pressure. The physical properties needed to address the two printing conditions are opposite enough to cause problems. The first problem is that the heater portion of the flexible heater is a fine mesh of conductive resistors which is needed to produce uniform heating over the entire surface. This material is woven and therefore its surface, while flexible on one axis as much as a sheet of typing paper is flexible in one axis, is made of a material hard enough that it imparts its natural weave print onto the printed surface. To eliminate this problem, flexible heaters have been produced that bury the heating unit inside of a silicone rubber material. This eliminates the problem of printing the impression of the woven surface onto the end product's surface, but create new problems. Even though the heater and rubber are flexible by nature, they are produced in a flat state, again much like a sheet of paper, but because of their thickness, which is required to resolve the problem of printing on the naturally irregular surface of glass or ceramic, they do not bend uniformly. The outside of this material sandwich, (which generally measures about 3/8 inch thick), must travel further than the inside surface when being wrapped around an object. The pressure required to wrap and hold the flexible heater against the cylindrical surface to be printed must be applied from the outside, and as a result the inside surface has a tendency to buckle in order to use up the additional material resulting from wrapping this material around a cylinder. This results eventually in wrinkling which is impossible to repair or remove. The wrinkles cause uneven contact pressure to be applied to the cylindrical surface to be printed, thereby resulting in a finished design that reflects the exact shape of the wrinkle. As a result, the flexible heater that develops a wrinkle must be replaced. The wrinkling problem can occur after as few as twenty uses, although it normally lasts for a few hundred uses.
Another problem associated with the flexible heating unit is that the rubber layer and the heating web layer have a tendency to separate after repeated use (as few as fifty, but normally a few hundred uses). This separation creates an electrical shock hazard and further aggravates the problem of surface wrinkles. The heater must be replaced if separation occurs.
A still further problem associated with the prior art flexible heating unit has to do with the natural physical difficulty associated with trying to apply an even pressure between all points of a cylindrical surface and the flexible heating unit. The flexible heating unit wraps around the cylindrical object and applies pressure by pulling from the ends. This tends to create a contact pressure differential at different points about the surface of the cylindrical object. The result is that the print will be darker in areas of high pressure and lighter in the area of low pressure.
Flexible silicon heaters are basically lower temperature devices with external heating devices operating at less than 500 degrees F (Fahrenheit). The temperature limitation is required because silicon breaks down and disintegrates at temperatures approaching 500 degrees F. The lower temperature usually means a longer "dwell" time, i.e., time to transfer the image to the mug. A serious danger with longer dwell times or with high temperatures is that the image being imprinted may burn or yellow.
Prior art heat transfer devices also include devices which heat the inside of a mug with hot air. This is basically a high temperature process. Although effective, these types of devices take from 3 to 4 minutes to accomplish the transfer.
As may be seen in FIG. 9, a conventional ceramic mug 10 has a handle 11, bottom 12, exterior surface 14 and inside opening 13. The mug areas about the handle 11 and bottom 12 are necessarily structurally thicker for support. This results in two "colder" areas on the mug 10 during heat transfer printing. Because of this, prior art heat transfer printing devices have left larger areas around the handle and bottom unprinted or poorly printed. The present invention has a two pronged approach to overcoming the prior art limitations on heat transfer printing.
The press of the present invention allows transfer printing for all transfer types, from processed sublimation and litho transfers to thermal video prints, onto the entire cup--from the very top lip of the cup right to the very bottom and within 1/2 inch of the handle--in less time than of current transfer machines.

Automatic heat transfer press for tubular structures and containers


A steering lock device including a steering shaft having an engagement recess, a steering column pipe having an insertion hole, a housing mounted to the steering column pipe with a guide projection being inserted into the insertion hole, a cylinder body mounted in the housing, a key-operated rotor disposed in the cylinder body, a lock pin inserted slidably in the slide hole of the housing and engageable with the engagement recess, and a lock mechanism actuated in accordance with the rotation of the rotor for conducting engagement and disengagement of the lock pin in which the lock pin has a square cross sectional shape, wherein the following relations are satisfied: EQU H.gtoreq.16 and 6.gtoreq.B.gtoreq.[13050/(D.multidot.H)].sup.1/2. where H is the length for the first side, B is the length for the second side of the lock pin and D is the diameter for the steering shaft, or the relations: EQU f(D.sub.C)=0.0031D.sub.c.sup.2 -0.1375D.sub.c +7.2 EQU f(D.sub.C)-0.5.ltoreq.b.ltoreq.f(D.sub.C)+0.5. where b is a distance from the center of the lock pin within a plane orthogonal to the axial line of the steering shaft to the outer surface of the guide projection and D.sub.C is a diameter of the steering column pipe.

1 Field of the Invention
The present invention relates to a steering lock device in which a rotor is made rotatable by insertion of a key and inserted into a fixed cylinder, a housing having a guide projection inserting into an insertion hole of a steering column pipe is mounted to the steering column pipe, and a lock mechanism having a lock pin in a square cross-sectional shape engageable with an engagement recess of a steering shaft is constituted to enable engagement and disengagement of the lock pin with and from the engagement recess to be switched in accordance with the rotation of the rotor.
2 Description of the Prior Art
The above steering lock device has already been known, for example, by Japanese Utility Model Publication Nos. 15080/1988 and 27891/1991.
A lock pin of a lock mechanism undergoes a bending load by a rotational torque of a steering shaft in a state in which the lock pin is engaged in an engagement recess. In the lock pin of the steering lock mechanism, the modulus of section Z is represented as: (Z=(1/6).multidot.H.multidot.B.sup.2) where H is a length of a first side along the axial line of the steering shaft and B is a length of a second side orthogonal to the first side. In order to increase the flexural strength of the lock pin by making the modulus of section larger, the length B was set relatively largely, for example, the lengths B, H were set as: 1.gtoreq.B/H.gtoreq.0.5.
However, if the flexural strength of the lock pin is excessively large, the strength of the contact portion between a guide projection and an insertion hole provided in the steering column pipe into which the guide projection is inserted becomes relatively lower than the above mentioned flexural strength and, as a result of which, the insertion contact portion of the guide projection and the insertion hole is deformed before the lock pin is deformed. Therefore, the flexural strength of the lock pin and the strength of the insertion contact portion between the guide projection and the insertion hole have to be balanced with each other for improving the strength limit of the lock mechanism.
Further, in a structure in which the guide projection provided in the housing is inserted into the insertion hole provided in the steering column pipe, and the lock pin protruded from the guide projection is engaged with the engagement recess in the steering shaft, bending load is exerted from the lock pin to the guide projection of the housing in the engagement state of the lock pin into the engagement recess, and a reaction is exerted on the guide projection from the contact portion of the insertion hole and the guide projection. According to the result of the studies of the present inventor, it has been proved that the strength of the guide projection is lowered depending on the offset amount between the operation point of the bending load and the operation point of the reaction. Then, it is necessary to appropriately determine the offset amount on every steering lock device in order to maintain the strength of the guide projection. In this case, if an appropriate offset amount can be determined in accordance with the dimensions of the parts constituting the steering lock devices, it can contribute to the rationalization of the productivity.
In addition, if the lock mechanism having a relatively great number of parts can be simplified and the number of parts can be reduced, the assembling operation for the lock mechanism can also be facilitated.