An underwater sampler has a tubular body having closures biased to move from open to closed positions. The closures releasably may be latched in their open position by a latch mechanism having retainers separably coupled to anchor cables attached to the respective closures. The latch mechanism may be actuated by a weighted messenger or by a sharp tug on a hoist line by which the tubular body is suspended at a predetermined level in a body of water from which a sample is to be taken.

For some liminological and oceanographic studies it is important that underwater samples be taken at selected depths and that such samples be protected against dilution or modification due to leakage of the sampler during retrieval of the latter. One type of sampler used for this purpose comprises a hollow tube, usually open at both ends, and having end closures or stoppers which are adapted to be moved from open positions to closed, sealing positions in response to the dropping of a weighted messenger along the tether line or cable which supports the sampler. The stoppers are latched in their open positions by a releasable latch mechanism which has a release assembly that is tripped by compressive force generated by the weighted messenger to enable the stoppers to move to their closed positions. Such a latch mechanism is disclosed in U.S. Pat. No. 3,949,497, granted Apr. 13, 1976.
Some of the water samplers comprise hollow tubes which are adapted to be suspended substantially horizontally in the water, whereas others comprise hollow tubes that are adapted to be suspended vertically. In either case the closures at the ends of the tube are adapted to be moved from open to closed position when desired and at whatever level the samplers are located.
Effecting closing movement of the closures at opposite ends of a vertically suspended tube presents a special problem. This primarily is due to the fact that the latch mechanism associated with the uppermost closure must be capable of overcoming an upward force exerted by the cable which retains the uppermost closure in its open position. To accomplish this objective vertical water samplers have been fitted with extremely complex latch release mechanisms.
A principal object of the invention is to provide a simple, inexpensive, easily operable, releasable latch mechanism for latching closures at opposite ends of a vertically oriented water sampler in their open position, but which assures release of the latch mechanism when desired so as to enable the closures to move from their open position to their closed position.


An image forming system includes a plurality of image forming apparatuses and a group management server. The plurality of image forming apparatuses each include a document-box management unit. The document-box movement processing unit transmits a command to at least one of a first image forming apparatus assigned to a group before the movement and a second image forming apparatus assigned to a group after the movement, the command causing movement of a document box of the moved user from the first image forming apparatus to the second image forming apparatus. The document-box management unit in at least one of the first image forming apparatus and the second image forming apparatus accepts the command. The document-box management unit forwards the document box of the moved user from the first image forming apparatus to the second image forming apparatus.

Unless otherwise indicated herein, the description in this section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section.
When a user uses an image forming apparatus in an organization such as an office with a plurality of image forming apparatuses, the user uses the image forming apparatus nearest to the user's desk or the image forming apparatus of the department to which the user belongs. Accordingly, when the position of the desk is changed or the user is moved because of change of the belonging department, the image forming apparatus that the user uses is also changed.
In some image forming apparatus, a document box can be generated for each user. The user can save a document file or similar file obtained by image reading in the document box of the user.
Accordingly, when the image forming apparatus that the user uses is changed due to movement of the user, there is the need to simply move the document box of the user.
Regarding the movement of the document file, there is a technique that moves the file in a first folder to a second folder, which is preliminarily set, using administrative rights when a file is, for example, added or updated in the first folder on a file sharing service.

Image forming system and image forming apparatus that forward document box of moved user


Aspects relate to digital imaging. An example method includes receiving a first image frame of a scene captured by a first image sensor. The method also includes receiving a second image frame of the scene captured by a second image sensor. The second image frame is captured concurrently with capture of the first image frame. The method also includes receiving a third image frame of the scene captured by a third image sensor. The third image frame is captured concurrently with capture of the first image frame. The method also includes generating a combined image from the first image frame, the second image frame, and the third image frame. The combined image includes a first field of view that is wider than a field of view of the first image frame.

Many devices include one or more cameras. For example, a smartphone or tablet includes a front facing camera to capture selfie images and a rear facing camera to capture a scene (such as a landscape or other scenes of interest to a device user). A user may wish to capture a scene that does not fit within a field of view of a camera. For example, a user may wish to capture a panorama image of a landscape. Some devices include multiple cameras with different fields of view based on a curvature of a camera lens directing light to the image sensor. Some devices include a software implemented panorama function using a single image sensor. When the user selects the function, the camera captures an image of the camera's current field of view. The user rotates the device (such as moving his or her arms from left to right) to rotate the camera's field of view, and the camera continues to capture images during the rotation. After capture, the device stitches together the sequence of frames to generate a panorama image.

Multiple camera system for wide angle imaging


A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

In semiconductor fabrication processes, the resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch. To continue to use fabrication equipment purchased for larger technology nodes, double exposure methods have been developed.
Double exposure involves forming patterns on a single layer of a substrate using two different masks in succession on the same layer of the substrate. A set of first patterns are formed using the first mask. The patterns in the second mask are positioned so as to form second patterns that are interleaved between the first patterns formed by the first mask. As a result, a minimum line spacing in the combined pattern can be reduced while maintaining good resolution. In a method referred to as double dipole lithography (DDL), the patterns to be formed on the layer are decomposed and formed on a first mask having only horizontal lines, and on a second mask having only vertical lines. The first and second masks are said to have 1-dimensional (1-D) patterns, which can be printed with existing lithographic tools.
Another form of double exposure using two masks is referred to as double patterning technology (DPT). Unlike the 1-D approach of DDL, DPT in some cases allows a vertex (angle) to be formed of a vertical segment and a horizontal segment on the same mask. Thus, DPT generally allows for greater reduction in overall IC layout than DDL does. DPT is a layout splitting method analogous to a two coloring problem for layout splitting in graph theory. The layout polygon and critical space are similar to the vertex and edge of the graph respectively. Two adjacent vertices connected with an edge should be assigned different colors. Only two "color types" can be assigned. Each pattern on the layer is assigned a first or second "color"; the patterns of the first color are formed by a first mask, and the patterns of the second color are formed by a second mask. A graph is 2-colorable only if it contains no odd-cycle and loop. Although DPT has advantages, it is computationally intensive.
When two different photomasks are used to pattern the same layer, misalignment of patterns can occur.

This patent is subject to a terminal disclaimer.

RC extraction for single patterning spacer technique

Taiwan Semiconductor Manufacturing Co., Ltd.


A piston support housing for a transmission assembly includes a plurality of axially-extending finger portions engaging a plurality of spline portions formed in a corresponding transmission case, and a plurality of friction plates are assembled adjacent the piston support housing such that the finger portions extend circumjacent peripheral edges of the friction plates. The friction plates include a plurality of torque-transmitting spline portions disposed circumferentially intermediate the finger portions. The friction plates also include a plurality of recesses disposed with one adjacent each of the finger portions to preclude contact between the finger portions and the friction plates thereby preventing torque-transmission through the finger portions to the transmission case.

Automatic transmission assemblies sometimes include a piston housing member which houses a piston and its associated clutch plates. The clutch plates are engaged with internal splines of the piston housing member, and the piston housing member has external splines which are splined to a transmission case. The piston housing member may be axially secured with respect to the transmission case by one or more snap rings to axially ground forces of the piston.
With the clutch plates splined into the piston housing member, the piston housing member becomes a large component which adds mass and cost to the transmission assembly.

Support housing for torque-transmitting mechanisms in a power transmission


A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected.

1. Field of the Invention
The present invention relates to a level shifter and a flat panel display using the same.
2. Description of the Related Art
Recently, various flat panel display devices that have reduced weight and volume in comparison to a cathode ray tube have been developed. Different types of flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel and an organic light emitting display, etc.
The liquid crystal display displays images by controlling the amount of light generated from the external backlight that is transmitted through the liquid crystal panel. The liquid crystal display can display a large area image at a high resolution as technology has developed. Therefore, it has been used in various fields. Also, the organic light emitting display displays images by using organic light emitting diodes (OLEDs) that generate light through the recombination of electrons and holes. The organic light emitting display has been spotlighted as the next generation display since the organic light emitting display has advantages of rapid response speed and low power consumption.
The liquid crystal display and the organic light emitting display include pixels positioned at crossing portions ("crossings") of scan lines and data lines, a data driver for driving the data lines, and a scan driver for driving the scan lines.
The scan driver sequentially selects the pixels in a horizontal line unit (i.e., a horizontal row of pixels) by sequentially supplying scan signals to the scan lines. The data driver supplies data signals to the data lines in synchronization with the scan signals supplied from the scan lines. As a result, the data signals are supplied to the pixels selected by the scan signals and an image having brightness corresponding to the supplied data signals is then displayed.
The scan driver and/or the data driver include a level shifter unit having a plurality of level shifters that generally shift the magnitude of input signal voltages.

Level shifter and flat panel display using the same


An expandable assembly for insertion into an intervertebral space is presented. The assembly, in particular aspects, includes an elongate body comprising an upper portion and a lower portion, wherein the elongate body defines an internal longitudinal channel extending from a proximal opening to a distal cavity. The assembly may include an expander that is sized and shaped for insertion into the distal cavity, thereby selectively expanding the upper portion away from the lower portion. The elongate body may also include one or more bone graft windows a cap that is sized and shaped for insertion into the proximal opening.

The following disclosure relates generally to medical devices, systems and methods, including, for example, systems and methods for lumbar interbody fusion.
Surgical implantation of disc replacement material is typically used to provide support along the spinal column in cases where a portion of the patient's intervertebral anatomy has become weakened, diseased, or destroyed. Such support systems are also commonly used following a discectomy, where an intervertebral disc is surgically removed.
Most commonly, existing support systems typically operate by inhibiting normal movement between the adjacent vertebrae, thereby holding these vertebrae at fixed positions relative to one another, with the mechanical body of the supporting structure providing the needed support along the patient's spinal column. Such supporting systems are typically made of stainless steel, titanium, polymer (e.g., an organic polymer thermoplastic such as polyether ether ketone (PEEK)), carbon fiber, or ceramic and they are designed to permanently remain within the patient's body.
It is beneficial, in addition to fixation, to try to stimulate bone growth between the adjacent vertebrae. To do so, spine surgeons use bone graft material in addition to fixation devices. Bone graft doesn't heal or fuse the spine immediately; instead, bone graft provides a foundation or scaffold for the patient's body to grow new bone. Bone graft can stimulate new bone production. When new bone grows and solidifies, fusion occurs. Although instrumentation (e.g., screws, rods) is often used for initial stabilization (post-operative), it is the healing of bone that welds vertebrae together to create long-term stability. There are two general types of bone grafts: real bone and bone graft substitutes. Real bone can come from the patient (autograft) or from a donor bone (allograft). Also used in these types of surgery are bone substitute, osteoinductive agent, and bone cement.
There is a need for improved systems and methods for lumbar interbody fusion.

Expandable intervertebral cage assemblies and methods


A coating system may include a coating chamber; a substrate holder to move a substrate along a motion path; and a sensor device in the coating chamber, wherein the sensor device is configured to move along the motion path, and wherein the sensor device is to perform a spectral measurement on the substrate.

A coating system may be used to coat a substrate with a particular material. For example, a sputtering system may be used for deposition of film layers, such as thin film layers or thick film layers. Based on depositing a set of layers, an optical element may be formed. For example, a thin film may be used to form a filter, such as an optical interference filter.


The present invention provides an electrophotographic photoreceptor which has high light resistance, has high durability in exposure to oxidizing gases such as ozone and NOx, is excellent in mechanical properties such as printing durability, wearing resistance, marring resistance, and slip properties in repetitions of use, and further has excellent electrical properties. Specifically, the present invention provides an electrophotographic photoreceptor having an electroconductive substrate and provided thereon at least a photosensitive layer having a charge generation material, a charge transport material, and a binder resin.

1. Field of the Invention
The present invention provides an electrophotographic photoreceptor. More particularly, the present invention provides a high-performance electrophotographic photoreceptor having excellent light and ozone resistance.
2. Discussion of the Background
Owing to its instantaneous nature and ability to provide high-quality images, electrophotography is used extensively not only in copiers, which are a conventional application, but also in various printers, facsimile telegraphs, and the like.
Inorganic photoconductive materials, such as amorphous silicon and arsenic-selenium systems, are presently employed as part of the photoreceptors, which are the nucleus of electrophotography. However, use of organic photoreceptors remains in the majority.
Multi-layer arrangements have been developed for organic photoreceptors. However, an arrangement in which the multi-layered photosensitive layer consists of a charge generation layer and a charge transport layer, so that the function of charge generation and that of charge transport are separately allotted, is currently being enthusiastically investigated/developed. This is because this type of photosensitive layer has a high degree of freedom of design and, hence, would enable a higher-performance photoreceptor to be produced, as well as having a high productivity, etc. At present, the range of uses thereof has spread even to medium- to high-speed copiers and printers.
The properties required of photoreceptors include the following basic properties: to have high photosensitivity; to have sufficient charge acceptance capacity; to be reduced in dark decay after mechanical light irradiation; to show a low residual potential; to show satisfactory response characteristics; and to be highly stable in these properties in repetitions of use. In addition to the foregoing, various properties are required from the standpoint of practical use.
One of these is ambient light resistance. Usually, the photoreceptor mounted in a copier or laser printer is used in the state of being shielded from ambient light. However, during machine assembly or when the photoreceptor is taken out of the machine due to, e.g., paper sticking, the photoreceptor is inevitably exposed to the ambient light. This ambient light has a far higher intensity than the exposure/mechanical light to be used for image formation in the machine and, hence, causes considerable damage to the photoreceptor. This is because a large amount of charge traps generate within the photoreceptor when the photoreceptor is exposed to light, and in many cases this leads to a considerable increase in residual potential.
Although the mechanism by which charge traps generate has not been fully elucidated, the following hypothesis exists. For example, the charge transport material itself absorbs the exposure/mechanical light and is thus excited. When this charge transport material relaxes from the excited state, it does not return to the original ground state but changes into another structure having an intermediate energy state, and this is causative of the charge traps. In another case, an ingredient in the charge transport layer (e.g., the charge transport material alone or, in the case where substance having an electron affinity is contained, a weak charge-transfer complex formed from the substance having an electron affinity and the charge transport material) is directly excited to generate charge carrier pairs, which result in the charge traps.
On the other hand, various charging techniques are employed in copiers and laser printers. It is known that around the high-voltage charging units, oxygen molecules contained in the air are ionized to generate ozone. It is also known that the ozone thus generated causes damage to the photoreceptor. Although the mechanism of this phenomenon also has not been fully elucidated, it is thought that the deterioration of the photosensitive material by ozone, which is an oxidizing substance, and the resultant charge traps are causative.
Heretofore, techniques used to prevent damage to the photoreceptor include the following. For diminishing the influence of ambient light, use has been made, for example, of a method in which a yellow lamp, which is less influential, is employed as an illuminator in machine assembly and a method in which when the machine is opened, a light-shielding plate is disposed in order to minimize the influence of exposure to ambient light on the photoreceptor. For diminishing the influence of ozone, a method in which a contact type charging device, which is less apt to generate ozone, has been employed, as well as a method in which a fan is employed to discharge the ozone generated outside the apparatus.
On the other hand, materials thought to be unsusceptible to oxidation are being investigated for use, such as the incorporation of an electron-attracting substance or an antioxidant into a charge transport layer as described in, e.g., JP-A-7-191476 and JP-A-5-323631. However, these techniques have been insufficient for preventing an increase in residual potential and the effect of inhibiting a decrease in electrification characteristics.
In particular, there have been problems, for example, that use of an antioxidant alone is ineffective in inhibiting the influence of exposure to ambient light and produces higher side effects on other electrophotographic properties. As such, there remains a critical need for high-performance electrophotographic photoreceptors that have excellent light and ozone resistance.

Electrophotographic photoreceptor, drum cartridge employing the electrophotographic photoreceptor, and image-forming apparatus


An object is to provide a chamber lamp socket in which a chamber lamp can be prevented from being loosened even if there is strong impact or vibration and from which the chamber lamp can be easily detached, and a combustible refrigerant applied refrigerator in which the chamber lamp socket is adopted. In the refrigerator provided with the chamber lamp socket attached to the inside of a chamber and the chamber lamp attached to and supported by this chamber lamp socket, the chamber lamp socket includes a socket main body provided with a lamp holder to be engaged with a mouthpiece of the chamber lamp, and a support member whose tip portion is brought into contact with an outer periphery of a light emitting portion glass tube of the chamber lamp to hold the lamp and which is formed of a flexible material, and the tip portion of the support member has a sawtoothed shape constituted by alternately forming gentle slopes and steep slopes in such a manner that a resistance in detaching the chamber lamp is larger than that in attaching the chamber lamp.

The present invention relates to a chamber lamp socket attached to the inside of a chamber of a refrigerator, and a refrigerator provided with this chamber lamp socket.
In a thermostatic chamber or a household refrigerator, a chamber lamp socket is disposed in an appropriate position in a chamber. Moreover, a mouthpiece of the chamber lamp which lights at a time when an insulating door opens is engaged with a lamp holder of the chamber lamp socket to constitute a chamber lamp device (see U.S. Pat. No. 5,408,392).
Additionally, in the above-described chamber lamp device, the engagement of the mouthpiece with the lamp holder loosens owing to vibrations at the time when the refrigerator door opens or closes, vibrations due to an operation of a compressor constituting a refrigeration cycle, or the like, and the chamber lamp does not light at the time when the door opens in some case.
Moreover, refrigerators increase in which combustible hydrocarbon-based refrigerant (butane, isobutene, propane or the like) is used in a refrigeration cycle constituted by connecting a compressor, a condenser, and an evaporator via pipes to form a refrigerant circulating path. Furthermore, in a case where the refrigerant leaks from the refrigeration cycle in the refrigerator in which the combustible refrigerant is used, when the chamber lamp loosens and sparks are generated between the mouthpiece and the lamp holder, there is a fear that the sparks cause ignition on the leaked refrigerant.
To solve the problem, a refrigerator is known in which an insulating portion of a socket main body is provided with a collar portion to be closely attached to a glass tube of the chamber lamp to reduce the looseness of the chamber lamp, and the mouthpiece is physically separated from a contact portion of the lamp holder to prevent invasion of the combustible refrigerant (see Japanese Patent Application Laid-Open No. 2002-164138).
However, even in this type of refrigerator, the chamber lamp loosens in rare cases. To solve the problem, it is proposed that the collar portion be formed to be large, and a closely attached area with respect to the glass tube be enlarged. However, in this case, a large force is required for the engagement of the chamber lamp, and operations to attach and detach the chamber lamp become laborious.
Furthermore, in this type of refrigerator, when the collar portion is closely attached to the glass tube of the chamber lamp for many years, both of the collar portion and the glass tube stick to each other. When they are removed from each other once, this state returns to an original state.
The chamber lamp is usually positioned in an inner portion of the chamber of the refrigerator. Therefore, in the refrigerator at a time when several years have passed after the refrigerant was purchased, the chamber lamp expires. To change the lamp, a user stretches out his arm into the chamber to manually hold, turn, and detach the chamber lamp. In this case, the collar portion sticks to the glass tube of the chamber lamp. Therefore, the user has to stretch out his arm, manually hold the glass chamber lamp, and apply such a sufficient force as to prevent this glass chamber lamp from being broken in detaching the chamber lamp. This is very difficult.


A wearable drug delivery device includes an injector having a housing, a reservoir, a needle or cannula, a drive mechanism for urging drug product out of the reservoir, through the needle or cannula, and to a patient, and an activator mechanism disposed on a surface of the housing for activating the drive mechanism. An activation prevention mechanism is coupled to the injector housing and/or activation prevention mechanism to prevent inadvertent actuation of the activator mechanism.

Parenteral delivery of various drugs, i.e., delivery by means other than through the digestive tract, has become a desired method of drug delivery for a number of reasons. This form of drug delivery by injection may enhance the effect of the substance being delivered and ensure that the unaltered medicine reaches its intended site at a significant concentration. Similarly, it is also possible with parenteral delivery to avoid undesirable side effects such as systemic toxicity associated with other routes of delivery. By bypassing the digestive system of a mammalian patient, one can avoid degradation of the active ingredients caused by the catalytic enzymes in the digestive tract and liver and ensure that a necessary amount of drug, at a desired concentration, reaches the targeted site.
Traditionally, manual syringes and injection pens have been employed for delivering parenteral drugs to a patient. More recently, parenteral delivery of liquid medicines into the body has been accomplished by administering bolus injections using a needle and reservoir, continuously by gravity driven dispensers, or via transdermal patch technologies. Bolus injections can require large individual doses. Continuous delivery of medicine through gravity-feed systems can compromise the patient's mobility and lifestyle, and limit therapy to simplistic flow rates and profiles. Transdermal patches often require specific molecular drug structures for efficacy, and the control of the drug administration through a transdermal patch can be severely limited.
In recent years, wearable drug delivery devices, which are sometimes referred to as on-body injectors, have grown in applicability and preference. Like syringes, these wearable devices deliver drug by inserting a needle or cannula into the patient. But, unlike conventional syringes and pens, the patient or caregiver is not required to interact with the device after it is placed onto the patient's skin and activated. For some patients, this removes the fear associated with manually inserting a needle or depressing a syringe plunger. Regardless, for those devices that include externally located and manually operable activator mechanisms, the process of placing the device on the patient's skin must be performed with a certain level of care to avoid inadvertent activation.

Drug delivery device with activation prevention feature


Embodiments of the present invention provide a media drive capable of improving command processing performance by, when a plurality of commands is queued, shortening seek time and rotational latency, and also effectively making use of the shortened period of time. In one embodiment, a HDD includes a queue capable of storing a plurality of commands, and a queue manager for optimizing the execution order of the plurality of commands on the basis of whether or not the execution of each command requires access to a medium. The queue manager determines the execution order so that medium access processing of accessing a disk for execution, and data transfer processing of transferring data between the HDD and a host, are executed in parallel with each other. For example, read processing and transfer processing are executed in parallel with each other. The read processing is adaptive to read out a read command, data of which does not exist in the cache, from the disk into the cache. The transfer processing is adaptive to transfer a read command, data of which exists in the cache, to the host.

The present invention relates to a media drive that transfers write data or read data between the media drive and a host according to a command, and to a command processing method thereof. In particular, the present invention relates to a media drive that stores a plurality of commands in a queue to efficiently perform transfer between the media drive and a host, and to a command processing method thereof.
Devices using various types of media such as optical disks and magnetic tapes are known as information recording and reproducing devices. Among them, hard disk drives (hereinafter referred to as "HDD") have become popular as storage devices for computers to such an extent that they are one of the storage devices indispensable for today's computer systems. Further, not limited to computers, their application is widening more and more due to the superior characteristics with the advent of moving picture recording/reproducing devices, car navigation systems, removable memories for digital cameras and so on.
Almost all of HDDs, which are built into personal computers (PC) excluding servers and some workstations, adopt ATA (AT Attachment) or IDE (Integrated Drive Electronics) interface. In addition, as a result of the improvement in performance, and the increase in capacity, of the ATA interface, because costs of both a drive and a controller are low as compared with costs when SCSI (small computer system interface) is adopted, even entry servers adopt ATA as a hard disk interface in recent years. It is to be desired that a further improvement in performance be achieved without losing advantages of ATA, one of which is very low cost in contrast to the expensive SCSI interface.
As one method for achieving the improvement in performance, it is conceivable that the exchange of data between a HDD and a host is speeded up, that is, an interface is speeded up. There are two methods for speeding up the interface: one is that the number of signal lines is increased so as to increase the amount of data that can be transferred in one cycle; and the other is that a cycle of transferring data is shortened so that the larger amount of data can be transferred during unit time.
Between the two methods, the parallel ATA intended to achieve the speedup by shortening a transfer cycle. However, in order to achieve further speedup, it is necessary to extend the data width, or to increase a frequency of a strobe signal. However, if further speedup is tried, it becomes difficult to maintain synchronization of data between signal lines. Additionally, when a frequency of a signal increases, a problem arises in that the interference between signal lines and noises cannot be ignored. A device is adopted in which a ground line is located between the signal lines so as to make it possible to prevent the interference between the signal lines from occurring, which results in stable transfer. However, with the object of solving the problems, cables and connectors need to be changed to a large extent, and specifications of circuits for transmitting and receiving a signal also need to be changed. For example, a differential signal, the voltage of which is decreased, must be adopted. As a result, the low cost advantage of the ATA interface is lost.
For this reason, in order to achieve the speedup with the manufacturing cost being kept substantially the same as that of the ATA, a serial transmission method is proposed. Serial transmission has a feature that is advantageous to speedup. More specifically, as compared with parallel transmission, the number of signal lines dramatically decreases, and accordingly less interference occurs between signal lines as compared with the parallel transmission. The standards of this serial ATA are being defined by Serial ATA Working Group, constituted of, for example, main hard disk vendors, for the purpose of changing the physical interface of ATA from the conventional parallel interface (parallel ATA) to a high-speed serial interface.
Incidentally, when data is read/written from/to a HDD, the operation requiring the longest period of time is mechanical operation inside the HDD, including the moving time of a head, and rotational latency of a disk. What is required is, therefore, not only an improvement in transfer rate, but also a reduction in the period of time required for read and write.
While electric processing, such as transmitting/receiving a command, decoding, and accessing a memory, is completed in microsecond (μs) order, the mechanical operation inside the HDD requires a long period of time of millisecond (ms) order. The mechanical operation inside the HDD is constituted of the head moving time and the rotational latency. The head moving time denotes a period of time (the seek time) taken from the issuance of a read/write instruction by the HDD until a head is positioned at a target track on a disk. Because this seek time is largely influenced by the moving distance between tracks, the average seek time obtained by dividing the seek time moving from the innermost track to the outermost track by 2 is usually used as a performance indicator.
The rotational latency denotes the waiting time from when the head is moved to a track until the head arrives at a target sector in the track as a result of the rotation of the disk. It is to be noted that although the amount of rotation of the disk differs to a large extent depending on a position of the last sector, a maximum value of the rotational latency is uniquely determined by the rotational speed of the disk. For example, when the rotational speed is 5400 rpm, the maximum value is 11.1 ms; when the rotational speed is 7200 rpm, the maximum value is 8.3 ms; when the rotational speed is 10000 rpm, the maximum value is 6 ms; and when the rotational speed is 15000 rpm, the maximum value is 4 ms.
"Command Queuing" is provided to avoid overhead caused by such mechanical operation to the utmost. The Command Queuing successively issues a plurality of commands without waiting for the completion of command execution, and stores the commands in a queue just as they are. This makes it possible to successively transmit the commands to the HDD without waiting for, on a command basis, the completion of the mechanical operation of the HDD, which requires a long period of time.
In the Command Queuing, instead of executing the commands, which are stored in the queue, according to the order in which the commands have been received (in order), the plurality of commands stored in the queue are rearranged in the efficient order before the commands are executed. The commands are executed by, what is called, out of order. The efficient order is the order that can shorten the distance between tracks so that the move of the head can be shortened as much as possible, and that can shorten the distance between sectors so that the rotational latency becomes short. To be more specific, it is the order that can shorten the mechanical operation of the HDD by shortening the sum of the seek time and the rotational latency. This technique is, what is called, Rotational Positioning Ordering (hereinafter referred to as "RPO").
In recent years, the seek time is shortened as much as possible not only by paying attention to the positional relationship between tracks, but also paying attention to the positional relationship between sectors and the closest head position. It is because the rotational latency may increase depending on the positional relationship between sectors in some cases. Accordingly, with the object of avoiding such an increase in rotational latency, what is being adopted is a method in which commands are rearranged so that the sum of the seek time and the rotational latency can be shortened as a whole to realize the command execution order in efficient combination with other commands.
In addition, with the object of quickly executing write and read commands to process data, for example, if the top and the end of logical block addresses (Logical Block Address: LBA) of read data read out from a hard disk by a read command agree with or overlap the corresponding ones of another read command, these read commands are integrated so that the commands are executed at a time. This is how to efficiently handle the commands (see, e.g., patent document 1 (Japanese Patent Laid-Open No. 2001-209500)).
Incidentally, also in the "Serial ATA II: Extensions to Serial ATA 1.0a" (hereinafter referred to as "Serial ATAII"), which is already released, a command queuing technology called NCQ (Native Command Queuing) is adopted. The NCQ permits a HDD itself to internally determine the execution order of commands that are queued. This makes it possible to effectively reduce the sum of the seek time and the rotational latency, which are caused by the mechanical internal operation of the HDD.
The NCQ is a function designed taking over the way of thinking of the "Tagged Command Queuing" which the SCSI has. The NCQ has the following three functions:
1. Race-free Status Return Mechanism
2. Interrupt Aggregation
3. First Party DMA (FPDMA).
The "Race-free Status Return Mechanism" is a mechanism by which even when any kind of command is being executed, or at any timing, a status can be freely returned from a drive (usually, a HDD) to, for example, a host controller such as a PC. Additionally, for a response to the status, a handshake with the host does not occur at all. Accordingly, the drive can successively transmit, to the host controller, execution completion statuses of a plurality of commands.
The "Interrupt Aggregation" is a function of suppressing the occurrence of an interruption by integrating, into one, interruptions occurring in a plurality of commands. Next, the "First Party DMA" is a function that allows the drive to set up the DMA (Direct Memory Access) operation for data transfer without the intervention of driver software on the host controller side. The Serial ATA is provided with FIS called DMA Setup FIS, by which the drive selects DMA context on the host controller side. The FIS (Frame Information Structure) is a structure of a frame that is a basic transfer unit of the Serial ATA.
The DMA Setup FIS stores information including tag numbers (0-31) corresponding to commands for which the DMA setup is performed, and the amount of data (DMA Transfer Count) transferred to the host controller. The host controller carries out the DMA transfer processing on the basis of the DMA Setup FIS received from the drive.

Media drive and command execution method thereof

Hitachi Global Storage Technologies Netherlands B.V.


A conveying system for food processing such as cooling pouches of food discharged in a single line from a pouch filler including apparatus for rearranging the pouches in order to shorten the line. One apparatus is a right angle transfer device in which the pouches are discharged in a single line onto a belt array which is then dropped to allow an array of rollers to support the pouch and transfer its direction of motion. Another apparatus includes an array of rollers which move the pouch into a position forming a row of pouches which is then picked up by rollers and moved in a direction as a line of rows of pouches. Another apparatus is a belt system for supporting the row of pouches as it is being transferred from a downstream end of an upper conveyor to an upstream end of a lower conveyor thereby reversing the direction of motion of the pouches and allowing them to pass back through the treatment chamber. Mechanistic principles of the invention can be applied to various other operations in addition to hydrochilling such as heating, spraying, etc.

1. Field of the Invention
This invention relates to systems for chilling pouches of food and particularly to a chilling system having a conveying apparatus that automatically conveys pouches of food through a chilling step. In the context of this specification, a conveying apparatus will be understood to mean an apparatus such as a continuous belt or length of parallel rotating rollers that transports a plurality of items from an upstream (entrance) end to a downstream (exit) end in a continuous line (one after the other).
2. Prior Art and Information Disclosure Statement
In many instances, the food industry has adopted the use of plastic pouches or bags as a replacement for rigid containers such as barrels or metal drums formerly used to pack and ship a wide variety of foods. Foods that are presently packed and shipped in pouches include tomato products, various toppings such as chocolate and strawberry, soups, ets. The primary reason for the popularity of pouches for this purpose is cost, not only in terms of the cost of the container, but also in terms of the versatility provided in building equipment to handle these containers.
Typically, the temperature of the pouches of food discharged from a filler is 190.degree.-200.degree. F. The temperature of the pouches must be reduced to 105.degree.-110.degree. F. in order that the pouch can be handled and stored to ambient temperature without deterioration of the product. This reduction in temperature should take place in about 20 to 45 minutes.
The pouches are generally discharged from the filler one pouch at a time. If the pouches must pass through the chiller in a single line, then the length of the line would be excessively long. Therefore, the industry has adapted conveying apparatus that forms rows of pouches that progress through the chiller.
FIG. 1 is a top view showing the indexer 10 of a conveying apparatus of the prior are having a single line of product 12 on a continous belt 14 coming from the filler and moving in the direction from left to right as shown by the arrow. The index station comprises a line of retractable gates 18, each gate 18 coupled to a pneumatic cylinder (not shown), such that, as each pouch 12 carried by the belt 14 reaches its position in the indexer, the respective gate 18 comes down to prevent further movement of the pouch. When all the gates 18 are down, as detected by an electric eye, a set of pushers 20 move the pouches 12 onto a transfer belt in rows 16, with five pouches to a row, that carry the rows of pouches through the chiller.
The rows of pouches pass through the chiller three times by moving on a top level, an intermediate level, and a lower level in succession. This three pass construction requires a shorter chilling machine and also conserves the amount of cooling water needed. The pouches are transferred from one level to the next lower level by an array of rollers which guide the pouches but more or less allow the pouches to "free fall" from one level to the next lower level.
Damage to the pouches during their trip through the chiller system of the prior art occurred because of a number of reasons discussed below. The problem has been exacerbated by the introduction of thinner flexible plastic pouches.
One source of damage to the pouch was that the belt continued to run after the pouch had been stopped by the gate in the indexer thereby subjecting the pouch to rubbing from the belt as well as pushing a portion of the pouch under the nearest gate.
Another source of damage to the pouches is the rough treatment from the guide rollers as the pouch free falls to the next lower level in the chiller.
Another problem is that the retracting gate is sometimes jammed by an incoming pouch. Pouches of plastic can be jammed under the gate of the prior art indexer because the plastic is comparatively thin and flexible.
Another problem is that the conveying system is designed to receive only a fixed number of pouches in a row determined by the number of gates across the conveyor belt. This characteristic places a limit on the rate of throughput of pouches regardless of the size of the pouches.


A magnetic tunnel junction (MTJ)-based magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure and methods for manufacturing and using same. The TAS MTJ-based MRAM cell includes a magnetic tunnel junction that is formed with an anisotropic shape and that comprises a ferromagnetic storage layer, a reference layer, and an intermediate insulating layer. The ferromagnetic storage layer has a magnetization that is adjustable above a high temperature threshold; whereas, the reference layer has a fixed magnetization. The ferromagnetic storage layer is provided with a magnetocrystalline anisotropy that is oriented essentially perpendicular to a long axis of the anisotropic shape of the magnetic tunnel junction. The TAS MTJ-based MRAM cell advantageously limits the effects of dispersion in the magnetic tunnel junction shape anisotropy coming from the fabrication process and features a lower power consumption when compared with conventional MTJ-based MRAM and TAS MTJ-based MRAM cells.

Magnetic random access memories (MRAMs) have been the object of a renewed interest with the discovery of magnetic tunnel junctions (MTJ) having a strong magnetoresistance at ambient temperature. These MRAMs present many advantages such as speed (a few nanoseconds of duration of writing and reading), nonvolatility, and insensitivity to ionizing radiation. Consequently, they are increasingly replacing memory that uses more conventional technology based on the charge state of a capacitor (DRAM, SRAM, FLASH).
In conventional MTJ based MRAM, the memory cell includes a magnetic tunnel junction that comprises a stack of several alternatively magnetic and non-magnetic metallic layers. Examples of conventional MTJ-based MRAM devices are described in U.S. Pat. No. 5,640,343. In their simplest forms, the magnetic tunnel junctions of MTJ-based MRAM are formed from two magnetic layers of different coercivity that are separated by an insulating thin layer. The first layer (or reference layer) of the magnetic tunnel junction is characterized by a fixed magnetization; whereas, the second layer (or storage layer) is characterized by a magnetization direction that can be changed. When the respective magnetizations of the reference layers and the storage layer are antiparallel, the resistance of the magnetic tunnel junction is high. On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction becomes low.
Preferentially, the reference layer and the storage layer are made of 3d metals such as Fe, Co or Ni or their alloys. Eventually, boron can be added in the layer composition in order obtain an amorphous morphology and a flat interface. The insulating layer typically comprises alumina (Al2O3) or magnesium oxide (MgO). Preferentially, the reference layer itself can be formed from several layers as described, for instance, in U.S. Pat. No. 5,583,725, in order to form a synthetic antiferromagnetic layer. A double tunnel junction as described in the paper by Y. Saito et al., Journal of Magnetism and Magnetic Materials Vol. 223 (2001), p. 293, can also be used. In this case, the storage layer is sandwiched between two thin insulating layers with respective reference layers located on the opposite sides of the thin insulating layers.
FIG. 1 shows a memory cell 1 of a conventional MTJ-based MRAM. The memory cell 1 includes a magnetic tunnel junction 2 that comprises a storage layer 21, an insulating layer 22 and a reference layer 23. The magnetic tunnel junction 2 is illustrated as being disposed between a selection CMOS transistor 3 and a word current line 4. A bit current line 5 is placed orthogonal with the word current line 4. When electrical currents flow in the word and bit current lines 4, 5, word and bit magnetic fields 41 and 51 are respectively produced. Electrical currents are typically short current pulses from 2 to 5 nanoseconds having a magnitude on the order of 10 mA. An additional control current line 6 is applied to control the opening and/or the closing of the transistor 3 to address each memory cell 1 individually.
During a writing process, the transistor 3 is in the blocked mode (OFF), and no current flows through the magnetic tunnel junction 2. The intensity of the current pulses and their synchronization are adjusted so that only the magnetization of the storage layer 21 located at the crossing of the word and bit current lines 4, 5 can switch under the combined effect of the word and bit magnetic fields 41 and 51.
During a reading process, the transistor 3 is in the saturated mode (ON) and a junction current will flows through the magnetic tunnel junction 2 allowing the measurement of the junction resistance of the memory cell 1. The state of the memory cell 1 is determined by comparing the measured resistance with the resistance of a reference memory cell. For example, a low junction resistance will be measured when the magnetization of the storage layer 21 is parallel to the magnetization of the reference layer 23 corresponding to a value of "0." Conversely, a magnetization of the storage layer 21, antiparallel to the magnetization of the reference layer 23, will yield a high junction resistance corresponding to a value of "1."
Basic structural details for this type of conventional MTJ-based MRAM are described in U.S. Pat. Nos. 4,949,039 and 5,159,513; while, U.S. Pat. No. 5,343,422 discloses an implementation of a random-access memory (RAM) based on a MTJ based MRAM structure.
To help ensure that this architecture is working properly during the writing process, it is necessary to use memory cells 1 with an anisotropic form having high aspect ratios, typically 1.5 or more. Such geometry is required to obtain bi-stable functioning of the memory cell 1, a good writing selectivity between the selected memory cell and the half-selected cells located on the same line/column, and good thermal/temporal stability of the information.
According to U.S. Pat. No. 5,959,880, the aspect ratio of a memory cell can be reduced by increasing the magnetocrystalline anisotropy of the material that forms the storage layer. By doing this, the system is stable in time and temperature, and both states of the memory cell are well defined. On the other hand, the writing field required to reverse the magnetization of the memory cell from one stable state to another is significant and therefore the power consumed during the writing process is large. Conversely, if the magnetocrystalline anisotropy is low, the power consumed at writing is also low, but thermal and temporal stability of the storage layer are no more ensured. In other words, U.S. Pat. No. 5,959,880 teaches that it is not possible to simultaneously ensure low power consumption and thermal and temporal stability.
A thermally assisted writing switching (TAS) process for the above-referenced MTJ-based MRAM structure is described in United States Patent Application Publication No. US 2005/0002228 A1. The particularity of the magnetic tunnel junction of the TAS MTJ based MRAM is that both the reference layer and the storage layer are exchange biased. More precisely, the reference and storage layers are pinned by interaction with an adjacent antiferromagnetic reference layer and antiferromagnetic storage layer respectively. During a thermally assisted writing process, for example, a junction current pulse is sent through the magnetic tunnel junction rising the temperature of the magnetic tunnel junction and the magnetic coupling between the ferromagnetic storage layer and antiferromagnetic storage layer disappears. The magnetic tunnel junction is then cooled while a moderate magnetic field is applied by making a current to flow in the word current line, allowing for the reversal of the magnetization of the storage layer.
In contrast with the conventional MTJ-based MRAM, the TAS MTJ based MRAM structure is characterized by a considerably improved thermal stability of the storage layer due to the pinning of the antiferromagnetic storage layer. An improved writing selectivity is also achieved due to the selective heating of the memory cell to be written in comparison with the neighboring memory cells remaining at ambient temperature. The TAS MTJ-based MRAM structure also allows for a higher integration density without affecting its stability limit, and reduced power consumption during the writing process since the power required to heat the memory cell is less than the one needed to generate magnetization in the conventional MTJ-based MRAM structure.
A further improvement of the TAS MTJ-based MRAMs in terms of power consumption has been described in United States Patent Application Publication No. US 2006/0291276 A1. Here, the writing field is further reduced by selecting a circular geometry of the memory cell junction. In this case, the writing field is only given by the magnetocrystalline anisotropy of the storage layer and there is no contribution from the shape anisotropy. However, the use of a circular geometry does not allow for simultaneously low power consumption and thermal and temporal stability of the storage layer.
The benefit of using a circular magnetic tunnel junction can be better understood by expressing the energy of the magnetic barrier height that has to be overcome to write the cell from a state "0," of low electrical resistance, to a state "1," of high electrical resistance. The barrier energy per volume unit, Eb, can be expressed as set forth in Equation 1.
                              E          b                =                  K          +                                                                      A                                                                                R                                -                1                            L                                                  tM              s              2                                                          (                  Equation                                                              1                )
In Equation 1, the first term, K, is the magnetocrystalline anisotropy and the second term corresponds to the shape anisotropy. In the second term, AR is the aspect ratio of the magnetic tunnel junction, defined as the ratio of the length to the width L of the magnetic tunnel junction; t is the thickness of the storage layer; and Ms its saturation magnetization. The ellipticity can be defined as (AR−1), expressed in percentage terms.
The limitations of the prior art can be understood by considering that the barrier energy Eb increases with decreasing the size of the magnetic tunnel junction (L decreases and AR is constant), resulting in a significant increase in power consumption. In the other hand, the barrier energy Eb decreases with decreasing AR (L being constant), resulting in a loss of thermal and temporal stability.
In the case of a TAS MTJ-based MRAM with an exchange-biased storage layer, the storage layer stability at working temperatures is ensured by the pinning of the ferromagnetic storage layer with the antiferromagnetic layer, while, at writing temperatures, the pinning disappears and the memory cell can be written with a low writing field. In the case of a circular cell junction, a low writing field is obtained only by the low magnetocrystalline anisotropy. A low writing field and good thermal stability can then be obtained simultaneously by combining the junction geometry with the TAS MTJ-based MRAMs.
However, usual MRAM fabrication processes cannot guarantee perfectly circular magnetic tunnel junctions over a large array of memory cells, due to, for example, accuracy limitations in the pattering of the different junction layers. In addition, the magnitude of writing fields is strongly dependant on variations in the junction ellipticity. FIG. 2 shows the dependence of the writing field HR of the storage layer, on the aspect ratio of the magnetic tunnel junction for a conventional TAS MTJ-based MRAM cell. For example, the magnitude of the writing field more than doubles when the junction aspect ratio is increased from AR=1.0 to 1.1, representing a 10% variation typical from a usual fabrication process. The inset of FIG. 2 shows a top view of magnetic tunnel junctions with aspect ratio comprised between 1.0 and 1.1.
Such a variation of the aspect ratio results in a large dispersion of the writing field and a significant increase of the power consumption in a magnetic memory device containing an array of memory cells with circular junctions. In addition, electromigration effects in the current lines that occur for large electrical currents at high writing field may not be avoided.

Magnetic random access memory with an elliptical magnetic tunnel junction


The storage capacity of a failure analysis memory that performs an interleaved operation is reduced. There are provided a lower order address selecting part for selecting and extracting at least the least significant bit of an address signal, a bank control part for generating a bank switching signal by a logical signal outputted from the lower order address selecting part, a plurality of flip-flops for selecting either one of a plurality of banks operating in the interleaved operation by the bank switching signal outputted from the bank control part, and an access means for accessing an address of a memory constituting the selected bank by an address signal composed of the remaining higher order bit or bits of the address signal.

1. Field of the Invention
The present invention relates to a memory testing apparatus that is suitable for testing a semiconductor memory such as a memory constructed by a semiconductor integrated circuit (semiconductor integrated circuit memory; hereinafter referred to as IC memory), and more particularly, to a failure analysis memory for storing therein the test result of a semiconductor memory.
2. Description of the Related Art
FIG. 6 shows a basic configuration of the conventional semiconductor memory testing apparatus of such type. The illustrated semiconductor memory testing apparatus comprises a timing generator 11, a pattern generator 12, a waveform formatter 13, a logical comparator 14, and a failure analysis memory (FAM) 15.
The timing generator 11 generates, in order to control the test timing of the entire testing apparatus, a reference clock CLK and various kinds of timing signals (pulses) TS. Although a timing signal TS is applied only to the waveform formatter 13 in FIG. 6, it is needless to say that the timing signals are also applied to other units (apparatus, devices and circuits) of the testing apparatus including the logical comparator 14.
The pattern generator 12 generates, in synchronism with the reference clock CLK supplied from the timing generator 11, address data ADRD, test pattern data PTND, and control data CNTLD all of which are to be supplied to a semiconductor memory under test (hereinafter referred to as MUT) 16. These data signals are supplied to the waveform formatter 13. The waveform formatter 13 converts the inputted data signals, by the timing signals TS supplied from the timing generator 11, into an address signal ADR, a test pattern signal PTN and a control signal CNTL, respectively, each having a real waveform required for testing. These signals are applied to the MUT 16.
The write operation and the read-out operation of the MUT 16 are controlled by the control signal CNTL supplied thereto through the waveform formatter 13, so that a write operation of the test pattern signal PTN applied to the MUT 16 from the waveform formatter 13 and a read-out operation of the written test pattern signal from the MUT 16 can be carried out. The test pattern signal PTN having been written in the MUT 16 is read out therefrom later on, and the read-out response signal RPD is supplied to the logical comparator 14 where the response signal RPD is compared with an expected value signal EXP supplied from the pattern generator 12 to detect whether there is any anticoincidence between both two signals or not, and a decision is rendered that the MUT 16 is defective (failure) or not defective (pass).
The logical comparator 14 determines, when there is any anticoincidence between the two signals, that the memory cell of the MUT 16 at an address thereof from which the response signal RPD has been read out is defective, and generates a failure signal (data) FAIL indicating that fact. Usually, this failure signal FAIL is expressed by a logical xe2x80x9c1xe2x80x9d signal, and is stored in a memory cell of the failure analysis memory 15 specified by the address signal ADR supplied from the pattern generator 12. In general, the failure signal (data) is stored in the same address of the failure analysis memory 15 as that of the failure memory cell of the MUT 16.
On the contrary, when the response signal RPD coincides with the expected value signal EXP, the logical comparator 14 determines that the memory cell of the MUT 16 at an address thereof from which the response signal has been read out is defectless or normal, and generates a pass signal indicating that fact. This pass signal is expressed by a logical xe2x80x9c0xe2x80x9d signal, and is usually not stored in the failure analysis memory 15.
After the testing has been completed, a failure analysis for the MUT 16 is carried out with reference to the failure signals FAIL stored in the failure analysis memory 15. For example, in the case that the failure signals are utilized in carrying out a failure relief of the MUT, a failure map is created based on the read-out failure signals, and a decision is rendered as to whether the relief of the failure memory cells of the MUT 16 can be done or not.
FIG. 7 shows in outline a configuration of the failure analysis memory 15. The failure analysis memory 15 comprises a memory part 15A for storing therein a failure signal FAIL, and a control part 15B for controlling the memory part 15A such that the memory part 15A has the same data bit width (the number of bits) and the same word depth as those of the MUT 16. The control part 15B comprises an address formatting part 15B-1 to which an address signal ADR is inputted from the pattern generator 12, and a memory control part 15B-2 to which a failure signal FAIL is inputted from the logical comparator 14. Further, although not shown, to a data input terminal of the memory part 15A is supplied a failure signal FAIL from the logical comparator 14.
The address formatting part 15B-1 formats an address signal ADR supplied from the pattern generator 12, in accordance with the word structure of the MUT 16, into a higher order address signal (the most significant bit or several higher order bits including the most significant bit of the address signal ADR) MADR and a lower order address signal (the least significant bit or several lower order bits including the least significant bit od the address signal ADR) LADR separated from each other. The higher order address signal MADR is supplied to the memory control part 15B-2 as a signal for controlling an enable signal for a RAM (Random Access Memory) constituting the memory part 15A, thereby to control the connection of the memory part 15A in the direction of the word depth. The memory control part 15B-2 generates, based on the failure signal FAIL supplied frorn the logical comparator 14 and the higher order address signal MADR supplied from the address formatting part 15B-1, a write control signal WRSG, and supplies it to the memory part 15A.
The lower order address signal LADR is supplied to the memory part 15A as an address signal for accessing the memory part 15A. Accordingly, the addresses of the memory part 15A are accessed by lower order address signals LADR each supplied from the address formatting part 15B-1.
When both of the lower order address signal LADR supplied from the address formatting part 15B-1 and the failure signal FAIL supplied from the logical comparator 14 are logical xe2x80x9c1sxe2x80x9d, the write control signal WRSG outputted from the memory control part 15B-2 becomes effective or valid (logical xe2x80x9c1xe2x80x9d). As a result, the failure analysis memory 15 writes a logical xe2x80x9c1xe2x80x9d (corresponding to the generated failure signal FAIL) being applied to the data input terminal of the memory part 15A in the same address of the memory part 15A as that of the MUT 16. After the testing has been completed, the stored contents of the memory part 15A are read out therefrom, and the analysis of the failure memory cells (addresses) of the MUT 16 is performed. An address of the failure analysis memory 15 from which a logical xe2x80x9c1xe2x80x9d is read out corresponds to an address of the memory cell of the MUT 16 at which a failure has occurred.
Incidentally, in recent years, a demand for semiconductor memories that can operate at high rate or speed have been increased more and more, and some high-rate operating memories are already in practical use. One of the high-rate operating semiconductor memories includes a memory that operates in burst mode. Burst mode means, in this specification and claims, a mode in which, on the basis of an address signal supplied to a memory, the lower order address bit or bits of this address signal are changed to an address bit or bits (burst address) automatically generated within the memory which is, in turn, accessed by this address bit or bits. By high-rate generation of the burst address in the memory (by generating the burst address at high rate or speed), the write operation in and the read-out operation of the memory at high rate can be realized.
In order to test such a high-speed memory, it is required that failure signals generated at high rate must be stored in the failure analysis memory 15 of the memory testing apparatus. For this reason, the failure analysis memory 15 is constructed such that the memory part 15A thereof stores failure signals generated at high rate by its interleaved operation so as to store these high-rate failure signals therein. The interleaved operation means, in this specification and claims, an operating system in which there are provided a plurality of memory blocks each of which is constituted by a plurality of memories corresponding to the bit width of a memory under test, each memory usually having the same storage capacity as that of the memory under test, and the plurality of memory blocks are sequentially operated at timings of their operations shifted from one another to write signals therein. The number of memory blocks to be prepared is referred to as the number of ways of interleave. If the number of memory blocks is two, it is called a two-way interleaved operation. If the number of memory blocks is four, it is called a four-way interleaved operation. Since each memory block is also called a bank, the word xe2x80x9cbankxe2x80x9d will be used hereinafter.
FIG. 8 shows an example of configuration of the failure analysis memory 15 for performing a two-way interleaved operation. Since the failure analysis memory 15 operates in the two-way interleaved operation, the memory part 15A is constituted by a first and a second two banks BANK1 and BANK2.
There are provided a first flip-flop FF1 and a second flip-flop FF2 each having a data input terminal D to which a lower order address signal LADR from the address formatting part 15B-1 is inputted, and a third flip-flop FF3 and a fourth flip-flop FF4 each having a data input terminal D to which a write control signal WRSG from the memory control part 15B-2 is inputted. Moreover, there is provided a flip-flop FF0 for alternately outputting a first bank switching signal LD1 and a second bank switching signal LD2.
The first bank switching signal LD1 is a control signal for selecting the first bank BANK1, and is supplied to respective load terminals of the first and the third flip-flops FF1 and FF3. In addition, the second bank switching signal LD2 is a control signal for selecting the second bank BANK2, and is supplied to respective load terminals of the second and the fourth flip-flops FF2 and FF4. Each of these first to fourth flip-flops FF1-FF4 is a flip-flop having a load/hold function. Further, a clock CLK shown in FIG. 9A is supplied to each of clock terminals T of the flip-flops FF0-FF4 so that these flip-flops are controlled in synchronism with one another. One period T of this clock CLK corresponds to one operating period of the MUT 16 (one test period of the memory testing apparatus).
The flip-flop FF0 alternately generates, every time the clock CLK shown in FIG. 9A is applied thereto, the first bank switching signal LD1 (FIG. 9D) and the second bank switching signal LD2 (FIG. 9G) each having logical H (logical xe2x80x9c1xe2x80x9d). That is, the flip-flop FF0 outputs the second bank switching signal LD2 having logical L (logical xe2x80x9c0xe2x80x9d) when the first bank switching signal LD1 is in logical H, and outputs the first bank switching signal LD1 having logical L when the second bank switching signal LD2 is in logical H. When the bank switching signal LD1 or LD2 having logical H is supplied to each of the load terminals LD of the respective flip-flops FF1 and FF3 or each of the load terminals LD of the respective flip-flops FF2 and FF4 and the clock CLK is supplied to each of clock input terminals T of those flip-flops, the lower order address signal LADR and the write control signal WRSG being applied to the data input terminals D at that time are loaded into the corresponding flip-flops at the rising edge of the clock CLK.
The lower order address signal LADR outputted from the address formatting part 15B-1 is, as shown in FIG. 9B, a signal having the same period as the operating period T of the MUT 16, and the lower order addresses are generated, in this example, in the sequence of #1xe2x86x92#0xe2x86x92#1xe2x86x92#0xe2x86x92#0xe2x86x92 . . . The memory control part 15B-2 outputs, when the failure signal FAIL shown in FIG. 9C is inputted thereto, a write control signal WRSG having, in this example, its pulse duration (or width) of two times the operating period T when the lower order address signal is logical xe2x80x9c1xe2x80x9d as mentioned above. In the example shown in FIG. 9, the write control signal WRSG is in synchronous state with the failure signal FAIL shown in FIG. 9C. Since the first and the second bank switching signals LD1 and LD2 are alternately generated, each of these signals has a period of two times the operating period T, as shown in FIGS. 9D and 9G.
As can be easily understood from FIG. 9, when the first bank switching signal LD1 shown in FIG. 9D is logical H, the lower order address signal LADR shown in FIG. 9B supplied to the first flip-flop FF1 becomes #0, #0 and #1, and the write control signal WRSG supplied to the third flip-flop FF3 becomes logical L, logical H, and logical L. As a result, an address signal ADRI outputted from the first flip-flop FF1 becomes, as shown in FIG. 9E as BK1, #0, #0 and #1 each having a period of two times the operating period T, and is supplied to an address terminal Ad of the first bank BANK1. In addition, there is outputted from the third flip-flop FF3, as shown in FIG. 9F, a write command signal CS1 having its pulse duration of two times the operating period T and rising at the rising edge of the fourth clock CLK4 shown in FIG. 9A and falling at the rising edge of the sixth clock CLK6 shown in FIG. 9A. This write command signal CS1 is supplied to a write command input terminal CS of the first bank BANK1. Only during the time duration that the write command signal CS1 of logical H is applied to the write command input terminal CS of the first bank BANK1, the first bank BANK1 can write therein the logical xe2x80x9c1xe2x80x9d (corresponding to the generated failure signal FAIL) being applied to its data input terminal Di.
Similarly, when the second bank switching signal LD2 shown in FIG. 9G is logical H, the lower order address signal LADR shown in FIG. 9B supplied to the second flip-flop FF2 becomes #1, #1, #0 and #2, and the write control signal WRSG supplied to the fourth flip-flop FF4 becomes logical L, logical H, logical L and logical H. As a result, an address signal ADR2 outputted from the second flip-flop FF2 becomes, as shown in FIG. 9H as BK2, #1, #1 and #0 each having its period of two times the operating period T, and is supplied to an address terminal Ad of the second bank BANK2. In addition, there is outputted from the fourth flip-flop FF4, as shown in FIG. 9I, a write command signal CS2 having its pulse duration of two times the operating period T and rising at the rising edge of the third clock CLK3 shown in FIG. 9A and falling at the rising edge of the fifth clock CLK5 shown in FIG. 9A. The write command signal CS2 is supplied to a write command input terminal CS of the second bank BANK2. Only during the time duration that the write command signal CS2 of logical H is applied to the write command input terminal CS of the second bank BANK2, the second bank BANK2 can write therein the logical xe2x80x9c1xe2x80x9d (corresponding to the generated failure signal FAIL) being applied to its data input terminal Di.
As discussed above, since each of the first and the second flip-flops FF1 and FF2 holds the lower order address signal LADR which has been acquired therein at the rising edge of the clock CLK applied thereto when the load terminal LD thereof has been in logical H until the rising edge of the clock CLK applied to the flip-flop when the load terminal LD thereof is in logical H at the next time, the address signals ADR1 and ADR2 outputted respectively from these flip-flops FF1 and FF2 have, as shown in FIGS. 9E and 9H, their periods of two times the period of the lower order address signal LADR shown in FIG. 9B, respectively, and have their phases shifted by one operating period T of the MUT 16 from one another. Similarly, the write command signals CS1 and CS2 supplied to the write command nput terminals CS of the respective first and second banks BANK1 and BANK2 also have their pulse durations of two times the operating period T of the MUT 16, and have their phases shifted by one operating period T from one another. On the other hand, the first and the second banks BANK1 and BANK2 are alternately operated by the bank switching signals LD1 and LD2 with their phases shifted by one operating period T of the MUT 16 from each other. Accordingly, the memory part 15A operates with its period 2T (period shown in FIG. 9 as PFAM) which is twice the operating period T of the MUT 16. In other words, the memory part 15A operates at low rate or speed (at a rate of xc2xd of that of the MUT 16).
The first and the second banks BANK1 and BANK2 store, only during the time interval that the write command signals CS1 and CS2 are being applied to their write command input terminals CS, logical xe2x80x9c1xe2x80x9d being supplied to their data input terminals Di in the addresses specified by the address signals ADR1 and ADR2 supplied to their address terminals Ad at that time as a substitution for the generated failure signal FAIL, respectively. In the example shown in FIG. 9, since the second bank switching signal LD2 is in logical H when a failure signal FAIL is generated, a write command signal CS2 is generated at the rising edge of the third clock CLK3. As a result, a logical xe2x80x9c1xe2x80x9d is stored in the address #1 of the second bank BANK2.
In this manner, according to the aforementioned interleaved operation, even if failure signals are generated at high rate from a memory under test operating at high rate, these failure signals can be written in the failure analysis memory 15.
Incidentally, in order to store the failure signals in the failure analysis memory 15 by the aforementioned two-way interleaved operation, a memory having the same storage capacity as that of the MUT 16 must be prepared as each of the first and the second banks BANK1 and BANK2. Next, the reason thereof will be described.
The address sequence automatically generated within the MUT 16 includes an interleave sequence and a linear sequence. FIG. 10 shows a relationship between burst addresses generated in the both sequences in the case that the burst length is four. In FIG. 10, each of #0, #1, #2 and #3 represents a burst address, and each of A1, A2, A3 and A4 represents an address group in the interleave sequence.
For example, if it is assumed, in the linear sequence, that the first and the second banks BANK1 and BANK2 of the memory part 15A are accessed in the sequence of BANK1xe2x86x92BANK2xe2x86x92BANK1xe2x86x92BANK2, the internally generated address of the memory under test changes in the sequence of #0xe2x86x92#1xe2x86x92#2xe2x86x92#3 when the burst starting address is #0. The status of accessing to the memory part 15A of the failure analysis memory 15 in this case becomes the sequence of, as shown in FIG. 11A, BANK1 (#0)xe2x86x92BANK2 (#1)xe2x86x92BANK1 (#2)xe2x86x92BANK2 (#3).
Similarly, the internally generated address of the memory under test changes in the sequence of #1xe2x86x92#2xe2x86x92#3xe2x86x92#0 when the burst starting address is #1. The status of accessing to the memory part 15A in this case becomes the sequence of, as shown in FIG. 11B, BANK1 (#1)xe2x86x92BANK2 (#2)xe2x86x92BANK1 (#3)xe2x86x92BANK2 (#0).
It could be understood that in the both sequences, the same address is not accessed in succession. The pattern generator 12 has a function for generating this burst address in the similar manner to the case of generating the burst address within the memory under test. The pattern generator 12 outputs, separately from the address signal to be applied to the memory under test, an address signal containing this burst address to the failure analysis memory 15 so that failure signals generated in the case that the memory under test operates in the burst mode can also be stored in the failure analysis memory 15.
As is apparent from FIG. 10, assuming that at the starting point of the burst mode, the write operation is started without fail from, for example, the first bank BANK1, and the memory part 15A is accessed in the sequence of BANK1xe2x86x92BANK2xe2x86x92BANK1xe2x86x92BANK2, if the starting address of the burst mode changes in the sequence of #0xe2x86x92#1xe2x86x92#2xe2x86x92#3, all of these addresses #0-#3 must be provided in the first bank BANK1. Similarly, it is also necessary that all of the addresses #0-#3 are provided in the second bank BANK2.
Specifically, the address group A1 in the interleave sequence shown in FIG. 10 accesses the bank BANK1, the address group A2 accesses the bank BANK2, the address group A3 accesses the bank BANK1, and the address group A4 accesses the bank BANK2. In this manner, since all of the address groups A1, A2, A3 and A4 shown in FIG. 10 have the addresses #0-#3 provided therein respectively, it could be understood that the same number of addresses (storage capacity) as that of the memory under test must be provided in each of the banks.
As described above with reference to FIGS. 11A and 11B, the access status to the first and the second banks BANK1 and BANK2 of the memory part 15A in the interleaved operation becomes the sequence of, when the burst starting address is #0, BANK1 (#0)xe2x86x92BANK2 (#1)xe2x86x92BANK1 (#2)xe2x86x92BANK2 (#3), which results in that the addresses #1 and #3 in the first bank BANK1 are not accessed, and that the addresses #2 and #4 in the second bank BANK2 are not accessed. On the other hand, the access status to the first and the second banks BANK1 and BANK2 of the memory part 15A becomes the sequence of, when the burst starting address is #1, BANK1 (#1)xe2x86x92BANK2 (#2)xe2x86x92BANK1 (#3)xe2x86x92BANK2 (#0), which results in that the addresses #0 and #2 in the first bank BANK1 are not accessed, and the addresses #1 and #3 in the second bank BANK2 are not accessed.
What can be understood from FIG. 11 is that the amount of data to be actually written in each of the first and the second banks BANK1 and BANK2 is only xc2xd of the storage capacity of each bank. However, as mentioned above, since the burst starting address is not specified to each bank on entering into the burst mode, the addresses corresponding to all of the addresses of the memory under test must be provided in each of both the banks BANK1 and BANK2. Consequently, the storage capacity of each of the two banks BANK1 and BANK2 constituting the memory part 15A must be equal to the storage capacity of the memory under test, and hence there is a serious drawback in the conventional memory testing apparatus that the storage capacity of each bank of the memory part 15A cannot be reduced.
In the above discussion, the two-way interleaved operation has been explained. However, when the operating frequency of the memory under test MUT becomes high and the number of interleave ways is increased, the number of banks used in the memory part 15A of the failure analysis memory 15 is naturally increased as shown in FIG. 12. Therefore, when the storage capacity and the operating rate of the memory under test MUT are increased more and more, the number of memories used in the memory part 15A of the failure analysis memory 15 is further increased, resulting in a drawback that the storage capacity of the memory part 15A is massive, and the cost of the memory testing apparatus is increased as well as the physical size thereof becomes enormous.
It is an object of the present invention to provide a failure analysis memory in which the number of memories to be used therein is not increased even if the number of interleave ways is increased.
It is another object of the present invention to provide a semiconductor memory testing apparatus provided with a failure analysis memory that performs a multi-way interleaved operation and in which the storage capacity of the memory is decreased.
In order to achieve the above objects, in one aspect of the present invention, there is provided a failure analysis memory which is constructed such that a plurality of banks are operated in an interleaved operation and failure signals generated at high rate from a semiconductor memory under test are acquired into these banks, and comprises: bank control means for generating a bank switching signal by a lower order bit or bits of an address signal; bank selecting means for selecting either one of the plurality of banks to be operated in the interleaved operation by the bank switching signal outputted from the bank control means; and access means for accessing an address of a memory constituting the selected bank by an address signal composed of the remaining higher order bit or bits of the address signal.
In a preferred embodiment, the aforesaid failure analysis memory further includes: means for supplying a write command signal to the bank selected by the bank switching signal in the case that a failure signal is generated from the semiconductor memory under test.
In addition, the failure analysis memory further includes: lower order address selecting means for selecting and extracting at least the least significant bit of the address signal, and the bank control means outputs the bank switching signal in correspondence to a logical signal outputted from the lower order address selecting means.
Moreover, the aforesaid bank selecting means is a plurality of flip-flops each having a load/hold function, and the lower order bit or bits of the address signal are loaded onto one of the flip-flops selected by the bank switching signal outputted from the bank control means, thereby to select one bank.
Furthermore, the access means is a plurality of flip-flops each having a load/hold function, and an address signal composed of a higher order bit or bits of the address signal is loaded onto one of the flip-flops selected by the lower order bit or bits of the address signal, thereby to access a memory constituting one bank.
In another aspect of the present invention, there is provided a semiconductor memory testing apparatus provided with a failure analysis memory which is constructed such that a plurality of banks are operated in an interleaved operation and failure signals generated at high rate from a semiconductor memory under test are acquired into these banks, and the failure analysis memory comprises: bank control means for generating a bank switching signal by a lower order bit or bits of an address signal; bank selecting means for selecting either one of the plurality of banks to be operated in the interleaved operation by the bank switching signal outputted from the bank control means; and access means for accessing an address of a memory constituting the selected bank by an address signal composed of the remaining higher order bit or bits of the address signal.
With the construction of the present invention, it is sufficient that the memory part of the failure analysis memory may have its total storage capacity equal to the storage capacity of the memory under test without respect to the number of interleave ways. Therefore, there is obtained an advantage that the number of memories to be used in the failure analysis memory can be remarkably reduced.


A portable wireless LAN terminal device attachable to an external connecting terminal installed in a portable external connection device, such as a portable data terminal device, includes a device body (2); means for transmitting and receiving (6-9) a signal through a wireless LAN circuit, the means for transmitting and receiving being installed the device body (2); means for supplying power (11) to each portion from means for accumulating power installed in the device body (2) or means for accumulating power attachable to the device body (2); a connecting terminal (13) installed in the device body (2) and attachable to the external connecting terminal; and first sound producing means (12, 15), which is installed in the device body, for producing sound based on the signal received by the means for transmitting and receiving (6-9).

1. Field of the Invention
The present invention relates to a portable wireless LAN terminal device that is attachable to an external connecting terminal installed in a portable external connection device, such as a portable data terminal device, a portable data terminal system having a portable wireless LAN terminal device and an external connection device, and a mobile phone that is attachable to a portable wireless LAN terminal device.
In addition, the present invention relates to a wireless communication method that uses a portable wireless LAN terminal device, a method for providing service using a portable data terminal system, and a method for transferring an incoming call using a portable wireless LAN terminal device.
2. Background Information
A wireless LAN communication system can be easily constructed by buying a market available personal computer, radio base station, or the like. The aforementioned can provide users with a communication system at a relatively low price. In addition, the data transmission speed of a wireless LAN communication system is high, and is suitable for transmission and reception of a large amount of data. Examples of such a conventional wireless LAN communication system are shown in Japanese Laid-open Patent Publications 2003-110751, 2003-23674, HEI 10-51274, HEI 10-271120, 2002-261773, and 2000-224645, for example, which are hereby incorporated by reference. The especially relevant portions can be respectively found on page 3-4, FIG. 1, page 3-8, FIG. 1, page 2-4, FIG. 1, page 3-5, FIGS. 1-2, page 2-3, FIG. 1, and page 3-9, FIG. 1.
JP2003-110751 discloses a system for communicating using a wireless LAN circuit and a mobile phone circuit of a mobile phone with a wireless LAN terminal function installed therein, or with a PC card, which has a wireless LAN terminal function, attached thereto.
JP2003-23674 discloses a system for IP phone communications through a wireless LAN circuit by a slave unit connected to a PHS master unit as a mobile terminal unit, which has a wireless LAN terminal function installed therein through a PHS circuit or the PHS master unit itself.
JP-HEI 10-151274 discloses a system for a fighting game that can be played in competition with others by communicating between portable game terminal devices, which include a wireless LAN terminal function installed therein through a wireless LAN circuit.
JP-HEI 10-271120 discloses a system with a desktop or notebook personal computer (PC) connected to a wireless LAN terminal device by a cable for communication by selecting an available channel from a plurality of channels, which is divided from the specified frequency band of wireless LAN communication electric waves when the PC and a wireless communicate to a base station through the wireless LAN circuit.
JP2002-261773 discloses a system in which a wireless base station detects whether a wireless LAN terminal device, which is connected to a personal computer (PC) via a cable, has been stolen. The wireless LAN terminal device has a function that measures signal intensity from the wireless base station. When the intensity is lower than a predetermined value, the wireless LAN terminal device transmits a particular packet containing a MAC address to the wireless base station.
JP2000-224645 discloses a system for managing the historical travel of a wireless LAN terminal device by a management device connected to a wireless base station. The wireless LAN terminal device detects self-historical travel, and transmits it to the wireless base station.
In the first three patent references, the devices that perform the function of the wireless LAN terminal are installed in the mobile phone or the mobile terminal device (PHS master unit). However, in such a construction, the power consumption of the mobile phone or mobile terminal device is large. Accordingly, the available time allowed by a battery is relatively short. On the other hand, in order to increase the available time allowed by the battery, a battery with large capacity is required. Thus, the mobile phone and other components may be larger than desired. In addition, a shield for preventing interference between the electric wave of mobile phone circuit, and so on, and the electric wave of wireless LAN circuit is required. This may cause the construction of the mobile phone or the mobile terminal device to be larger than desired.
Additionally, when the PC card type wireless LAN terminal device is connected to the mobile phone or the mobile terminal device and is used, electric power is supplied to the PC card from the mobile phone or the like. Accordingly, power consumption of the mobile phone or the mobile terminal device is large. Similarly, this may exacerbate the above problem. Further, a slot exclusively used for attaching the PC card is required. This may cause the construction of the mobile phone or the mobile terminal device to be even larger.
Since the wireless LAN terminal device disclosed in the fourth or fifth reference does not have a user interface in the wireless LAN terminal device itself, the wireless LAN terminal device is required to be used while connected to a personal computer, or the like. Thus, the wireless LAN terminal device cannot be used in a stand-alone mode. Moreover, JP2000-224645 does not concretely disclose the construction of the mobile unit and how the function of the wireless LAN terminal is achieved.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved wireless LAN terminal Device, portable data terminal system, mobile phone, wireless LAN communication method, method for providing service, and method for transferring incoming calls. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Wireless LAN terminal device, portable data terminal system, mobile phone, wireless LAN communication method, method for providing service, and method for transferring incoming call