Devices and methods for detecting islanding operation of a static power source involve injection of a non-harmonic error on the phase angle of the static power source in regular steps to introduce a very small intentional phase shift for the output voltage of the static power source in every voltage cycle which is corrected in each cycle in synchronization with the grid voltage in normal operation of the grid. In abnormal operation of a grid loss, this intentional small phase shift or error causes an intentional small frequency drift in each voltage cycle that continues in one cycle after another cycle. When the intentional frequency drift is over a preset level, a detection circuit starts to isolate the static power source from the grid to prevent islanding operation.

1. Field of the Invention
The present invention relates generally to the field of electric power, and more particularly to devices and methods for detecting the islanding operation of a static power source connected to a utility grid.
2. Description of the Related Art
FIG. 1 is a block diagram that shows an example of a static power source (SPC) 10 connected to and in parallel operation with a grid 12 when a breaker Brk 1 is closed. The electrical loads LD1 and LD2, shown hanging at local power lines 14, can obtain power from both the SPC and/or the grid when the breaker Brk 1 is closed. However, when the grid voltage Va-g, Vb-g, Vc-g is lost, for example, by opening the breaker Brk 1, the loads LD1 and LD2 can still obtain electrical power Va-spc, Vb-spc, Vc-spc from the SPC 10 through the local power lines 14. That situation, in which the operation of a local power source, such as the SPC 10 in FIG. 1, continues to power the local power lines and load after the grid voltage Va-g, Vb-g, Vc-g is disconnected is called islanding operation.
Islanding operation is not desirable due to safety concerns. Detecting the islanding operation of a local power source, such as SPC 10, and isolating the local power source from the local power lines 14 after the grid 12 is lost is typically made mandatory by regulation. It is mandatory to have an anti-islanding feature on inverters, or utilities will not allow such inverters to be connected to the utility grid. In addition to safety issues, islanding also has performance implications. Current active methods of addressing the islanding problem include injecting harmonics which compromise performance. There are also passive methods which have non-detection zones, so anti-islanding is not guaranteed for all conditions. There is a separate issue of multi-unit operations, which also poses a problem for harmonic injection because harmonics can cancel each other.
Existing methods use harmonics or frequency pulse injection, or an explicit positive voltage or frequency feedback technique to detect the grid loss. These methods have serious drawbacks. Such injected signals can interfere with the grid or the load. The injected signals can sometimes cause resonance. The injected signals can also cancel each other, rendering the technique useless when two or more SPCs are connected together. The harmonics introduced to the grid affects the grid quality. The explicit frequency or voltage drifting technique is based on grid frequency/voltage change, and a positive feedback is used to drift the frequency/voltage away. This method cannot guarantee that islanding can be detected if there are no voltage or frequency changes when islanding occurs. At a special operation point (i.e., ideal islanding condition), the SPC's output power and power factor match the load's power and power factor on the local grid, thus there will be no frequency and voltage changes when islanding occurs, causing the above described explicit frequency or voltage drifting technique to fail.
Not only may there be a non-detection point (NDP) as it is described in the above ideal islanding condition, there may also be a non-detection zone (NDZ) associated with the above described method. When the SPC's power and power factor are very close to the load's power and power factor, the frequency and voltage change will be very small when islanding occurs. In order to detect these small changes and build up the drift, a larger gain will have to be used for the positive feedback of the explicit frequency or voltage drifting technique. However, a larger gain for positive feedback can cause the system to become unstable, while a smaller gain can potentially make the system have a larger NDZ in detecting islanding.


Processing components to manufacture information handling systems have build-to-order integrated circuits with plural selectively-enabled features set at the information handling system manufacture location. For instance, fuses integrated in the integrated circuits are selectively blown at the information handling system manufacture location to permanently disable features so that the processing components have a desired configuration. As another example, feature enable or disable states are programmed in flash incorporated in the integrated circuit, with the flash programmability subsequently disabled to permanently set the features so that the processing components have a desired configuration. Features are set with keys provided by the processing component manufacturer to track the information handling system manufacturer's use of the features.

1. Field of the Invention
The present invention relates in general to the field of information handling system integrated circuits, and more particularly to a system and method for configuring information handling system integrated circuits.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems are typically built from a plurality of processing components assembled in a housing and interfaced through a main printed circuit board, known as the motherboard, and a number of secondary printed circuit boards, known as daughterboards. A number of the processing components are independent integrated circuits, such as the CPU, while other processing components include integrated circuits to provide intelligence to perform functions, such as microprocessors and microcontrollers in hard disk drives, optical drives, chipsets, network interface cards, bus controllers, graphics cards, memory and displays. Generally, integrated circuits are also known as semiconductor devices because logic functions are performed with circuits fabricated from semiconductor material, such as silicon transistors interfaced with copper wirelines. Typically, the majority of the cost of an integrated circuit arises from the design and fabrication process and not the materials used to make the physical circuits. In other words, the engineering behind the circuit designs and the capital equipment used to build the circuit designs represent the greater portion of the expense of an integrated circuit. For this reason, manufacturers often combine a number of features in a given integrated circuit, even if all of the features are not used or even desired by all end users. Manufacturing costs are reduced for such multi-function integrated circuits since fewer circuit designs and manufacture process designs are needed for producing fewer types of integrated circuits.
One difficulty with the manufacture and sale of multi-function integrated circuits is that purchasers will balk at paying for functions that are not wanted for a particular information handling system. For instance, RAID functionality in a chipset is generally not needed for basic desktop systems but sometimes included as a function so that the same chipset is used in basic and advanced systems. However, integrated circuit manufacturers generally have to charge for all included functions, otherwise a purchaser may order and pay for limited numbers of functions while using additional functions without the knowledge of the integrated circuit manufacturer. To solve this difficulty, single integrated circuit device types are selectively differentiated by disabling or restricting features of speeds based on pricing or the market segment purchasing the device. Differentiation of a single device type is typically accomplished by activating fusing options during the manufacture process. For instance, blowing a fuse built into an integrated circuit has the effect of making the portion of the circuit associated with the fuse inaccessible. Reducing functions by blowing fuses during manufacture also has the advantage of reducing test costs since disabled functions need not be tested. However, differentiating integrated circuits with fusing results in system integrators having to define multiple types of printed circuit boards to accommodate various fusing options, resulting in platform fragmentation and increased end user costs.

System and method for configuring information handling system integrated circuits


The invention relates to the administration of guanylate cyclase inhibitors, such as methylene blue, for the treatment of septic shock, cardiogenic shock, hypovolemic shock, obstructive shock, neuropathic shock and hypotension caused by excessive doses of nitrovasodilators. The invention also relates to the use of other redox dyes, such as toluidine blue, neutral red, tetrazolium salts, chloranil and dichlorophenolindophenol for the treatment of shock.

1. Field of the Invention
The invention relates to a new method for the treatment of shock states, such as septic shock, cardiogenic shock, hypovolemic shock, shock caused by blood flow obstruction, neuropathic shock, and hypotensive disorders, comprising administering a pharmaceutical composition containing a guanylate cyclase inhibitor to a patient.
2. Brief Description of the Background Art
Shock is a clinical emergency, characterized by widespread, serious reduction in tissue perfusion which, if prolonged, leads to generalized impairment of cellular function. Shock is usually associated with systemic hypotension resulting from a significant decrease in either cardiac output or systemic vascular resistance, without a compensatory increase in the other.
Shock states are classified according to the precipitating factors. Examples include septic (bacteremia), cardiogenic (heart pump failure), hypovolemic (fluid loss), obstructive (circulatory obstruction), and neuropathic (drugs or spinal cord injury).
Septic shock, a life-threatening complication of bacteremia affects 150,000 to 300,000 patients annually in the United States, and has a mortality rate of 50% to 75% (Kilbourn et al., Biochem. and Biophys. Res. Comm. 172(3):1132-1138 (1990); Petros et al., The Lancet 338:1557-1558 (1991)). The shock state is characterized by circulatory insufficiency due to diffuse cell and tissue injury and the pooling of blood in the microcirculation.
The pathogenesis of the cardiovascular collapse that occurs during septic shock is poorly understood, but is believed to occur as a result of the reaction between bacterial products and components of the coagulation and complement systems. For example, bacterial endotoxin activates the synthesis and release of inflammatory mediators such as leukotrienes, prostaglandins, cytokines, such as tumor necrosis factor (TNF), and platelet activating factor. These inflammatory mediators significantly affect vasomotor tone, microvascular permeability and leukocyte and platelet aggregation.
In addition, endotoxin activates the alternative complement pathway, resulting in generation of C3a and C5a, which in turn affect platelet aggregation and vascular tone. Activation of the coagulation system by bacterial products further alters the microcirculation in tissues by contributing to thrombi formation. Finally, endotoxin stimulates release of vasoactive substance such as catecholamines, glucocorticosteroids, histamine and serotonin which, in combination, contribute to the eventual circulatory collapse.
Cardiogenic shock is the most important fatal complication of acute myocardial infarction, occurring in approximately 10% of such patients, and accounting for approximately two-thirds of in-hospital deaths. Other causes of cardiogenic shock include arrhythmias, severe congestive heart failure, mitral valve or aortic valve regurgitation, and perforation of the ventricular septum. The shock state occurs as a consequence of the decrease in arterial pressure and consequent reduction in coronary blood flow, resulting from the significant reduction in the quantity of contracting myocardium. This reduction in blood flow may further impair myocardial function, thereby increasing the size of the infarction.
Both septic and cardiogenic shock have been associated with an increase in the production of nitric oxide or endothelium-derived relaxing factor, (EDRF), a potent labile vasodilator which plays a major role in the regulation of local blood flow, vasomotor tone and systemic blood pressure through activation of soluble guanylate cyclase. In animal models of systemic shock, endotoxin and cytokines, such as interleukin-1 (IL-1) and TNF, have been shown to cause vascular relaxation and hypotension by increasing nitric oxide (NO) synthesis. In septic shock in particular, evidence suggests that TNF stimulates the production of nitric oxide by vascular endothelial cells (Lamas et al., Am. J. Physiol. 261(4 Part 1):C634-C641 (1991).
The synthesis of NO from L-arginine, occurs through the action of a constitutive enzyme in the vascular endothelium, which has a role in the physiological control of blood pressure, and an inducible NO synthase expressed throughout vessel walls in response to endotoxin or cytokines (Petros et al., Lancet 338:1557-1558 (1991)). Expression of inducible NO synthase leads to production of large quantities of NO and profound vasodilation, which is often refractory to vasoconstrictive agents. The mechanism by which NO causes vasodilation and hypotension is through activation of guanylate cyclase. This results in increased levels of cyclic GMP, which cause relaxation of smooth muscle. Thus, activation of guanylate cyclase is an important intermediary step in the NO-induced shock state.
Successful treatment of shock requires rapid restoration of cardiac output and tissue perfusion. Two groups of drugs which have been used to treat shock are beta-receptor stimulants (notably dopamine) and alpha-receptor blocking agonists (epinephrine and norepinephrine). However, all of these drugs have important disadvantages associated with their use, and in certain patients, may be ineffective in reversing established shock. Vasoconstrictive agents are often ineffective, and in patients with severe peripheral constriction, these agents may further reduce the already impaired tissue perfusion.
Effective therapy of septic shock requires immediate reversal of the cardiovascular collapse initiated by endotoxin. Because this collapse occurs as a result of complex interactions between a number of factors, treatment methods are often partially effective at best.
Recently, endotoxin-binding agents, including polymyxin B and antibodies which neutralize TNF, have been used in an attempt to modify the sequelae of septic shock. While these approaches may have prophylactic value there is no evidence that septic shock can be easily or quickly reversed by endotoxin or TNF removal (Kilbourn et al., supra 1132-1138). Some investigators indicate that NO synthase inhibitors, such as N.sup.6 -monomethyl-L-arginine (L-NMMA), may be helpful in the treatment of hypotension associated with sepsis or therapeutic use of cytokines, but caution that complete inhibition of endogenous NO synthesis may be counterproductive (Nava et al., Lancet 338:1555-1557 (1991)).
Methylene blue, a phenothiazine derivative, is a biological stain of low toxicity, as well as a guanylate cyclase inhibitor (Huang et al., Eur. J. Pharmacol. 205:289-294 (1991)). It is a member of a group of compounds, termed "redox dyes", which also includes toluidine blue and neutral red. In mice, methylene blue has been shown to decrease TNF production, when given prior to bacterial lipopolysaccharide challenge (Culo et al., Agents and Actions 34(3/4):424-428 (1991)). In addition, methylene blue has been used for the treatment of methemoglobinemia, nitrite intoxication and cyanide poisoning (Kiese et al., Eur. J. Clin. Pharmacol. 4:115-118 (1972); Burrows et al., Proc. Ann. Meet. U.S. Ani. Health Assoc. 79:266-270 (1975); and Sloand et al., Thrombi. Res. 54:677-686 (1989)).

Use of guanylate cyclase inhibitors in the treatment of shock


An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.

One type of non-volatile memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic "1" data bit value, and a memory element programmed to have a low resistance value may represent a logic "0" data bit value. The resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element. One type of resistive memory is phase change memory. Phase change memory uses a phase change material for the resistive memory element.
Phase change memories are based on phase change materials that exhibit at least two different states. Phase change material may be used in memory cells to store bits of data. The states of phase change material may be referred to as amorphous and crystalline states. The states may be distinguished because the amorphous state generally exhibits higher resistivity than does the crystalline state. Generally, the amorphous state involves a more disordered atomic structure, while the crystalline state involves a more ordered lattice. Some phase change materials exhibit more than one crystalline state, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state. These two crystalline states have different resistivities and may be used to store bits of data. In the following description, the amorphous state generally refers to the state having the higher resistivity, and the crystalline state generally refers to the state having the lower resistivity.
Phase changes in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state in response to temperature changes. The temperature changes to the phase change material may be achieved by driving current through the phase change material itself, or by driving current through a resistive heater adjacent the phase change material. With both of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material.
A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The level of current and/or voltage generally corresponds to the temperature induced within the phase change material in each memory cell.
To achieve higher density phase change memories, a phase change memory cell can store multiple bits of data. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on. For simplicity, the description in this disclosure is substantially focused on three different resistance levels or states and 1.5 bits of data per cell. This is for illustrative purposes only, however, and not intended to limit the scope of the invention. In principle it is possible to store three or more states.
One way to store multiple bits of data is to include multiple layers of phase change material in a phase change memory cell. To program such a phase change memory cell, one should be able to write to different layers.
For these and other reasons, there is a need for the present invention.

Multi-level resistive memory cell using different crystallization speeds


A laryngeal stimulation system including a sensor for detecting an occurrence of a respiratory signal in a subject and a laryngeal stimulator adapted for coupling to a laryngeal muscle and operable to stimulate the laryngeal muscle in response to the sensor detecting the occurrence of the respiratory signal is provided. A method for laryngeal stimulation including detecting an occurrence of a respiratory signal in a subject and then stimulating a laryngeal muscle in response to detecting the occurrence of the respiratory signal is also provided.

Bilateral laryngeal paralysis is a serious and often life-threatening clinical condition. The recurrent laryngeal nerve (RLN) carries motor fibers that innervate both the abductor (posterior cricoarytenoid, PCA) muscle and adductor muscles of the vocal folds. Damage to the nerve compromises both of these functions and arrests the vocal folds in a near-closed position. In cases of bilateral vocal fold paralysis (BVFP), voice tends to be functional but airway embarrassment is often severe enough to warrant emergency tracheotomy to relieve inspiratory stridor and dyspnea.[1,2] If spontaneous recovery from nerve injury does not occur within one year, it is likely the patient will be chronically paralyzed. In such instances, long-term tracheostomy could be considered. Unfortunately, permanent tracheostomy is known to have the complications of tracheal stenosis, chronic infection, and psycho-social impairment.[3-5]
For this reason, laryngeal surgery is usually recommended to enlarge the airway and restore breathing through the mouth. Procedures such as arytenoidectomy and cordotomy, regarded as the standard of care for enlarging the airway, also have inherent complications [6-9]. Specifically, they destroy voice and compromise airway protection during swallowing.
As such, there is presently an unmet need for improved therapies for the treatment of laryngeal paralysis to facilitate return of normal ventilation.

Respiratory triggered, bilateral laryngeal stimulator to restore normal ventilation in vocal fold paralysis


The invention is a method and apparatus for compensating for sculling in a strapdown inertial navigation system. The method operates on a sequence of inputs .DELTA.V.sub.B (n) derived at times n.DELTA.t from the outputs of one or more accelerometers. Separately compensated quantities .DELTA.V.sub.Bc (m,p) calculated at times (pJ+1/2).DELTA.t for M values of m are obtained by summing A(m,k).DELTA.V.sub.B (pJ-j-k) over k from 0 to K-1 and over j from 0 to J-1 where the constants A(m,k) are chosen to minimize sculling error in the individual .DELTA.V.sub.Nc (m,p) quantities where .DELTA.V.sub.Nc (m,p) is the representation of .DELTA.V.sub.Bc (m,p) in the navigation frame of reference. The final compensated quantity .DELTA.V.sub.Bc (p) is obtained by summing B(m).DELTA.V.sub.Bc (m,p) over m where the constants B(m) are chosen to minimize sculling error in .DELTA.V.sub.Nc (p) where .DELTA.V.sub.Nc (p) is the representation of .DELTA.V.sub.Bc (p) in the navigation frame of reference.

Strapdown inertial navigation systems are frequently used in missiles and aircraft. Physically isolated and stabilized apparatus, such as a gimballed platform that is physically angularly-stabilized relative to the local vertical direction, require precise and mechanically complex angle positioning apparatus, and are being systematically replaced by systems of the strapdown type.
A state-of-the-art strapdown inertial navigation system has three rotation sensors or gyros and three accelerometers rigidly attached to a supporting vehicle. The rotation sensors are each positioned and oriented to sense angular displacement about one of three defined orthogonal axes attached to the vehicle body and known as the body coordinate system. The accelerometers are each positioned and oriented in a fixed direction relative to the vehicle, to sense velocity changes (incremental velocities) along different ones of the three defined orthogonal axes. In a strapdown system, the accelerometer axes are not angularly stabilized.
Because the accelerometers are constantly changing direction relative to gravity, navigation velocities cannot be computed by directly integrating the accelerometer signals. Instead, a stable computational frame or analytic navigation coordinate system is continually generated. The output signals from the rotation sensors are used by an attitude integration apparatus to calculate the directions of local vertical, together with two other axes orthogonal to the local vertical direction.
Sensed angle changes and accelerations (incremental velocities) are continually rotated through the calculated angles from the vehicle body axes to the calculated navigation axes. Angle signals from the rotation sensors are used to update the computer-stored angular position and incremental velocity data for both the angle sensors and accelerometers relative to the navigation coordinate system.
The rotation sensors and accelerometers have fixed relative directions in the body coordinate system. An angular transformation matrix of direction cosines is computed in an attitude integration apparatus. The accelerometer signals, which are incremental changes in velocity, in the strapdown body coordinate system are converted in a coordinate transformation computer from that system into corresponding signals in the stabilized navigation coordinate system.
After transformation into the navigation coordinate system, the incremental velocity signals are integrated or summed to form updated velocity signals. The rotation sensor and accelerometer signals are sampled, and the sampled signals are delivered to a computer which is programmed to accept the signals and to calculate both velocities along the three axes in the stabilized navigation coordinate system and attitude angles relative to this system.
A rotation matrix is created in the attitude integration apparatus to transform vector body-coordinate signals (for example, incremental velocity component signals) from the body coordinate system of the instruments to the navigation coordinate system. The transformed signals are used to calculate and create signals that are measures of the local geographical position of the aircraft and the direction of the local gravity. The transformation matrix also yields signals that are measures of the angular orientation of the supporting vehicle relative to the navigation coordinate system.
The data used to compute the transformation matrix is sampled at finite periodic intervals, causing the bandwidth of the signals to be limited. When the instruments sense vibrations that occur at frequencies above or near the upper limit of the bandwidth of the transformation, where the response is poor, rectification errors occur in the calculated incremental velocity signals, and the navigation coordinate system signals are degraded. The rectification errors producing such degrading are called sculling errors.
A sculling error for a first strapped down axis is caused by a periodic angular displacement about a second axis perpendicular to that axis, multiplied by the periodic acceleration along a third axis perpendicular to the first and second axes.
To reduce the sculling error in strapdown systems, the sampling rate of the instrument signals can be increased. The upper limit of the sampling rate is set by the capabilities of the computer. An increase in sampling rate in a fast computer would likely increase the number of its calculations. The faster the computer, the greater its initial cost. The larger number of calculations might also require a prohibitively sophisticated computer with large power demand.
Instead of increasing the iteration rate for the transformation of incremental velocity from one coordinate system to the other, one might use a sculling compensation algorithm which has the effect of reducing sculling errors while only moderately increasing the computational requirements.
One could use both a faster sampling and sculling compensation to improve further the transformation of incremental velocity from body coordinates to navigation coordinates.

Sculling compensation in strapdown inertial navigation systems


A titanium alloy billet having improved response to ultrasonic inspection is described. The billet is given a thermomechanical treatment above the beta transus of the alloy immediately prior to ultrasonic inspection. The treatment may include beta annealing or mechanical deformation above the beta transus. The invention is particularly effective for beta-stabilized alpha-beta and beta titanium alloys.

Titanium alloys are widely used in the aerospace industry because they provide a useful combination of low density, high strength, good toughness, good resistance to corrosion and oxidation, and the ability to retain these properties at temperatures up to about 950.degree. F. However, the nature of aerospace vehicles and propulsion systems, where unnecessary weight exacts a penalty in reduced payload or fuel economy, indicates that designers of such vehicles and systems often seek to load the materials used therein as near to their performance limits as is reasonably prudent. Doing so requires that aerospace materials be made with special care, including careful inspection, to ensure that sound material be used in such a vehicle or system.
Ultrasonic inspection is widely used to inspect nonferrous alloys for aerospace applications. The inspection may be done on semifinished mill products, such as billets, and again on forgings made from those mill products. The double inspection has generally been justified on the basis that the inspection of billets does not detect all of the material imperfections, even those which originate in the manufacture of ingots. However, if ultrasonic inspection of billets could be made more sensitive, it might be possible to omit the second inspection. Besides eliminating the cost of the second inspection operation, imperfections would be identified and removed from the manufacturing process before the cost of forging is incurred; thus, the concept of relying on ultrasonic inspection solely at the billet stage is economically attractive. All metals contain imperfections, which are inherent in their formation. Some imperfections are larger than others with small imperfections not being capable of detection. The smallest size capable of being detected is referred to as the minimum resolvable size.
Ultrasonic inspection is affected by two intrinsic characteristics of the material being inspected, namely, attenuation of the sound waves and reflection of the sound waves within the material itself. Attenuation is manifested as weakness of any signals generated in response to internal structure and imperfections in the material due to scattering of the signal. Reflections from internal structural features as grain boundaries are manifested as noise, which are sometimes referred to as "grass" in the electronic image of the ultrasonic inspection, while reflections from imperfections are frequently referred to as indications. Unfortunately, most titanium alloys suffer from both high attenuation and high noise levels. Consequently, it is difficult to distinguish valid ultrasonic reflections indicating the presence of a subsurface indication from noise, particularly in large diameter billets where the indication may be as much as seven or eight inches below the surface. In comparison, other alloy families, such as aluminum-, iron- and nickel-base alloys, permit much more sensitive ultrasonic inspection than do titanium alloys.
Several investigators have attempted to determine the cause for the high attenuation and high noise in ultrasonic inspection of titanium alloys, specifically Ti-6Al-4V (Ti-64), which is a widely used alpha-beta alloy. Billman and Rudolph ("Effects of Ti-6Al-4V Metallurgical Structure on Ultrasonic Response Characteristics," Titanium Science and Technology, edited by Jaffe and Burte, Vol. 1, (1973), pp. 693-70.5, Plenum Press, New York) evaluated ultrasonic inspection behavior of Ti-64, as such behavior is affected by macrostructure and microstructure, and by deformation below the beta transus. They pointed out the importance of refining the alpha platelets in the microstructure, which they were able to accomplish by beta recrystallization at 2000.degree. F. and by extensive deformation below the beta transus. The beta transus of a titanium alloy is that temperature above which the alpha phase does not exist at equilibrium conditions.
Allison, Russo, Seagle and Williams ("The Effect of Microstructure on the Ultrasonic Attenuation Characteristics of Ti-6Al-4V, "Titanium Science and Technology, edited by Lutjering, Zwicker and Bunk, Vol. 2, (1985), pp. 909-916, Deutsche Gesellschaft fur Metallkunde) showed the value of quenching from a temperature above the beta transus to reduce ultrasonic attenuation in Ti-64.
Granville and Taylor ("High Noise Levels during the Ultrasonic Testing of Titanium Alloys," British Journal of NDT, May, 1985, pp. 156-158) point out the importance of the shape and distribution of alpha particles in determining alloy behavior during ultrasonic inspection.
U.S. Pat. No. 3,470,034, the disclosure of which is incorporated herein by reference, teaches refinement of the microstructure by deformation starting above and ending below the beta transus as a means for reducing noise in ultrasonic inspection.
U.S. Pat. No. 3,489,617, the disclosure of which is incorporated herein by reference, teaches the deformation and beta recrystallization for breaking up alpha networks at prior beta grain boundaries to achieve a better combination of ductility and strength. Both of these patents are directed to Ti-64
As indicated hereinabove, prior work has been directed toward Ti-64 and related alloys; titanium alloys containing greater amounts of the beta stabilizing alloying elements have not received nearly as much attention. Titanium alloys . containing large amounts of beta stabilizing alloying elements are often identified as beta-stabilized alpha-beta alloys, or beta alloys.
The present invention is directed toward a need for improving the ultrasonic response of beta-stabilized alpha-beta and beta titanium alloys. Such alloys respond differently to thermal and deformation processing, and to ultrasonic inspection, than do the alpha alloys and alpha-beta alloys such as Ti-64. Therefore, the methods used to improve the response of alpha and alpha-beta alloys are not capable of providing similar improved response for the beta and beta-stabilized titanium alloys.

Titanium article having improved response to ultrasonic inspection, and method therefor


A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.

1. Field of the Invention
The present invention relates to a solid-state image sensing device and a camera system using the same.
2. Description of the Related Art
In recent years, the demand for solid-state image sensing devices has been rapidly increasing for use in image capturing apparatuses, such as, mainly, digital still cameras and video camcorders. As such solid-state image sensing devices, CCDs (Charge Coupled Devices) or MOS solid-state image sensing devices have been used. The former, as compared to the latter, are widely used as high-definition image sensing devices, due to their high sensitivity and low noise, but, on the other hand, have some disadvantages. Specifically, the power consumption and the drive voltage are high and the cost is high since a general semiconductor manufacturing process cannot be used. Additionally, it is difficult to integrate peripheral circuits, such as a drive circuit.
For these reasons, much effort has been devoted to the development of an amplifying-type MOS solid-state image sensing devices. In an amplifying-type solid-state image sensing devices, signal charge that is stored in a photodiode is introduced into the control electrode of an amplifying transistor, provided in each pixel, is amplified by the amplifying transistor, and the resulting output is output from the main electrode thereof in accordance with the amount of signal charge. In particular, for amplifying-type solid-state image sensing devices, efforts have been directed to the development of CMOS sensors using MOS transistors as amplifying transistors. The demand for portable telephones is projected to increase, and it is expected that MOS solid-state image sensing devices, which can overcome the above-described disadvantages of CCDs, will be applied to portable apparatuses.
FIG. 13 is a circuit diagram of a typical example of a CMOS sensor pixel for use in a solid-state image sensing device.
In FIG. 13, reference numeral 30 represents a unit pixel, 1 is a photodiode for storing signal charge generated from incident light, 6 is a amplifying MOS transistor for outputting an amplified signal in accordance with the amount of signal charge, and 3 is a floating diffusion (hereinafter may be referred to as "FD") region which receives a signal charge and connects the signal charge to the gate electrode of the amplifying MOS transistor 6. Reference numeral 2 represents a transfer MOS transistor for transferring signal charge stored in the photodiode 1 to the FD region 3, 4 is a reset MOS transistor for resetting the FD region 3, and 5 is a selection MOS transistor for selecting an output pixel. Reference numeral 9a is a control line for applying a pulse to the gate of the transfer MOS transistor 2 to control the charge-transfer operation, 9b is a control line for applying a pulse to the gate of the reset MOS transistor 4 to control the reset operation, and 9c is a control line for applying a pulse to the gate of the selection MOS transistor 5 to control the selection operation. Reference numeral 10a is a power-supply wire which is connected to the drain of the amplifying MOS transistor 6 and the drain of the reset MOS transistor 4 to provide a power-supply potential thereto. Reference numeral 10b is an output line for outputting an amplified signal of a selected pixel, 8 is a constant-current MOS transistor that operates as a constant current source and that forms a source follower in conduction with the amplifying MOS transistor 6, and 10c is a wire for supplying a potential to the gate electrode of the MOS transistor 8 so as to operate thereof at constant current.
An arrangement of a plurality of the above-described pixels 30 in a two-dimensional matrix provides a pixel area for a two-dimensional solid-state image sensing device. In the matrix configuration, the output line 10b is used as a common line for pixels in the same column and the control lines 9a, 9b, and 9c are each used as a common line for pixels in the corresponding row. Only pixels in a row that is selected by the control line 9c output signals to the corresponding output line 10b.
FIG. 14 is a circuit diagram of another pixel for a conventional solid-state image sensing device. In FIG. 14, reference numeral 1 represents a photodiode, 2 is a transfer MOS transistor for transferring charge of the photodiode 1, and 3 is a floating diffusion region for temporarily storing the transferred charge. Reference numeral 4 is a reset MOS transistor for resetting the floating diffusion region 3 and the photodiode 1, 5 is a selection MOS transistor for selecting one row in the array, and 6 is a source-follower MOS transistor. This source-follower MOS transistor 6 converts charge in the floating diffusion region 3 into a voltage and amplifies the voltage using a source-follower amplifier. Reference numeral 7 represents a read line, which is used as a common line in the same column, for reading a pixel voltage signal, and reference numeral 8 represents a constant current source for providing constant current to the read line 7.
The operation of this conventional solid-state image sensing device will be briefly described below. The photodiode 1 converts incident light into charge, and the transfer MOS transistor 2 causes the charge to be stored in the floating diffusion region 3. The potential of the floating diffusion region 3 and the photodiode 1 is reset to a constant potential in advance by opening the reset MOS transistor 4 and the transfer MOS transistor 2. Thus, the potential of the floating diffusion region 3 varies in accordance with charge generated from incident light.
The potential of the floating diffusion region 3 is amplified by the source-follower MOS transistor 6 and is output to the read line 7. When the selection MOS transistor 5 is open, that pixel is selected. An output circuit (not shown) detects optical signal components by determining the difference between the potential of the floating diffusion region 3 after optical signals are stored and the reset potential of the floating diffusion region 3.
FIG. 15 is a schematic sectional view of the solid-state image sensing device shown in FIG. 13. This schematic sectional view includes portions corresponding to the photodiode, the transfer MOS transistor, and the FD region. In this figure, reference numeral 11 represents an n-type semiconductor substrate, 12 is a p well, and 15 is an n-type semiconductor region formed in the p well 12. The p well 12 and the n-type semiconductor region 15 constitute a photodiode. Signal charge generated from incident light is stored in the n-type semiconductor region 15. Reference numeral 14 is a gate electrode of the transfer MOS transistor 2 shown in FIG. 13. Reference numeral 18 represents an FD region, which is an n-type semiconductor region formed in the p well 12 and also serves as the drain region of the transfer MOS transistor 2. The source region of the transfer MOS transistor corresponds to the n-type semiconductor region 15. Reference numeral 20 represents a wire that is connected to the FD region 18 and also to the gate electrode of an amplifying MOS transistor (not shown). Reference numeral 17 is an element-isolating insulating film, which is called a "LOCOS" oxide film. Reference numeral 29 is a p+ channel stopper, which is formed under the element-isolating insulating film 17 and has a doping concentration higher than the p well 12.
FIG. 16 is a schematic sectional view of the solid-state image sensing device shown in FIG. 14. This sectional view shows a combination of portions corresponding to the photodiode 1 and the transfer MOS transfer 2 shown in FIG. 14. Reference numeral 11 represents an n-type silicon substrate, 12 is a p well, 13a is a gate oxide film of the transfer MOS transistor 2, 13b is a thin oxide film provided on a light-receiving portion, 14 is the gate electrode of the transfer MOS transistor 2, and 15 is an n-type cathode of the photodiode 1. Reference numeral 16 represents a p-type surface region for providing a photodiode-buried structure, and 17 is a LOCOS oxide film for element isolation. Reference numeral 18 is a heavily-doped n-type region that forms a floating diffusion region and also acts as the drain region of the transfer MOS transistor 2. Reference numeral 19 is a silicon oxide film for providing insulation between the gate electrode and a first metal layer 21. Reference numeral 20 is a contact plug, 22 is an interlayer insulting film for providing insulation between the first metal layer 21 and a second metal layer 23, 24 is an interlayer insulating film for providing insulation between the second metal layer 23 and a third metal layer 25, and 26 is a passivation film. For a color photoelectrical conversion device, a color filter layer (not shown) is formed at the upper layer of the passivation film 26 and a micro-lens (not shown) is further formed thereon to improve the sensitivity. Incident light through the surface enters the photodiode through an aperture where the third metal layer 25 is not provided. The light is absorbed by the n-type cathode 15 of the photodiode or the p well layer 12, so that electron-hole pairs are produced. Of these pairs, electrons are stored in an n-type cathode region.
U.S. Pat. No. 6,403,998 discloses a solid-state image sensor in which a p-type buried layer is formed at a predetermined distance from an n-type substrate and a photoelectric conversion section is formed thereabove. In addition, U.S. Pat. No. 6,504,193 discloses a solid-state image device in which one end of a photodiode is formed to extend to a position under a readout gate and a punch-through stopper region is formed under a signal detection portion, which corresponds to the drain region, to be in self-alignment with the gate electrode.
With the conventional structures shown in FIGS. 15 and 16, however, part of signal charge generated below the photodiode is not absorbed by the photodiode, and is, in turn, absorbed by the FD region 18 and the source and drain regions of the transistor within the pixel. As a result, the sensitivity decreases.
Additionally, although various improvements have been made to CMOS solid-state image sensing devices, there is still a problem in that the sensitivity is low, particularly, in a device having a small pixel size. The present invention provides a CMOS solid-state image sensing device that has a novel structure and that can provide high sensitivity even for micro pixels.
A description is now given to a reason why the sensitivity in the conventional structure shown in FIG. 16 is low. Referring to FIG. 16, electrons that are generated from a light ray 27 entering the aperture are successfully stored in the n-type cathode region and serve as an effective signal charge. However, for example, as in the case of a light ray 28, electrons that are generated at a position somewhat away from the photodiode may be captured, not by the n-type cathode region, but by the n+ type floating diffusion region 18 where the potential is lower. In addition, even immediately under the photodiode, as a result of repeated diffusion and drift of electrons, the electrons are absorbed by a low potential region other than the photodiode with a certain probability and thus do not contribute as photoelectric conversion signals. When the n-type cathode 15 is formed at a position deeper relative to the silicon surface, such an arrangement facilitates the photodiode to collect the electrons. However, since the n-type cathode region is formed in the p well region 12 by ion implantation, the doping concentration cannot be reduced so significantly. This conventional structure also has a problem in that the n-type cathode 15 cannot be formed with a high doping concentration at a considerably deep position, due to the limitation of depletion behavior of the n-type cathode 15.
Thus, the volume of the n-type cathode, which provides the photodiode, is limited. Consequently, a sufficient ability of collecting electrons generated from incident light cannot be achieved, resulting in low sensitivity.
Meanwhile, the conventional structure disclosed in U.S. Pat. No. 6,403,998 also cannot prevent electrons that are generated at a deep position in response to incident light from being absorbed by the floating diffusion region 18 or the like, since no potential barrier is provided under the signal readout gate. Thus, this structure also has a problem in that the sensitivity decreases. Also, the conventional structure disclosed in U.S. Pat. No. 6,504,193 cannot prevent some of electrons that are generated from incident light from being absorbed by the source and drain of another transistor in the pixel or from being absorbed by adjacent pixels, since the punch-through stopper region is formed only under a signal detection portion. Thus, this structure also has a problem in that the sensitivity decreases as well.

This patent is subject to a terminal disclaimer.

Solid-state image sensing device and camera system using the same


A storage and display container for the storage and display of small articles such as jewelry includes a base or display unit and a cover removably received on the base or display unit. The base or display unit includes first and second display areas, one for the article and one for the indicia bearing material relating to the article. The cover for removably closing off the display unit is provided with a tapered top wall so that it can be removed from the display unit, inverted and have the display unit replaced in its open end. The cover has a tapered top wall so that, when inverted, it will support the display unit at an angle to one viewing it. A modified form of the invention includes a slot in the wall of the display unit for receipt of a transport, storage and display package which carries the indicia bearing material. The package has a pocket for receipt of the article for transport and storage when the article is not being displayed.

This invention relates, in general, to combined storage and display containers which are convertible from one mode to another and relates, in particular, to such a convertible container for small articles wherein the cover serves as a support for the base for display purposes when not in the storage mode.
It is known in the prior art that articles such as, for example, items of jewelry and the like are typically stored in a variety of boxes generally having covers which are either fully removable or hinged to as to be movable between open and closed positions.
These containers generally have a soft non-abrasive lining and a slot, hook, strap or some other means of mounting the article to be stored within the box as well as for display of the article. The boxes themselves are also often used for display purposes in display cases or on display counters by simply opening the box so that one can view the article.
Examples in the patent prior art are of general interest in this regard. For example, Weller U.S. Pat. No. 2,000,681 shows a jewelry display case having a cover which fits over the jewelry tray and with the cover capable of being inverted to receive and support the tray. A collapsible easel is also provided within the cover so that the tray and the article may be displayed at an angle with regard to the cover supporting surface to be more attractive and more eye catching to prospective purchasers.
Burnham U.S. Pat. No. 1,265,046 also shows the concept of inverting a cover to support a tray which forms the bottom portion of the box. Rielly U.S. Pat. No. 4,043,450 is generally similar in that a hinged cover/base combination is provided with an insert which can be placed on top of the box for display purposes. Feiler U.S. Pat. No. 4,917,235 is also generally relevant as is Witkoff U.S. Pat. No. 3,942,632. Tessler U.S. Pat. No. 5,967,326 also shows a display unit for rings or articles of jewelry.
However, as previously noted, it is desirable to be able to display the article at an angle and, except for the discrete easel structure previously mentioned, none of the prior art known to the applicant provides a convertible cover/base structure which makes this possible.
Thus, the known prior art fails to show a compact, convertible container for storage and display which utilizes the cover, per se, to provide the tilted display function and also provides internally, on the base, means for displaying informational material such as certificates of authenticity, etc. as well as the article itself. Furthermore, it is believed desirable to provide a base which is suitable for use without the cover in a larger support or tray in which a number of such container bases can be employed concurrently to display a range of articles in a compact single display unit.
It is therefore an object of this invention to provide a combined storage and display container in which the display portion or base is suitable for use with or without the cover for display purposes and which provides an area for displaying informational material as well as a display pedestal for receipt of the article itself.
It is a further object to provide a combined storage and display container of this general nature in which the cover is provided with a slanted or tapered top wall so as to make it possible for the cover to fully enclose the base including a display pedestal projecting upwardly from the base which is employed to display the actual article, when the combination is in its storage or transportation mode.
It is a further object of the invention to provide such a cover with a slanted or tapered top surface so that upon removal and inversion of the cover, the base may be positioned within the opening of the cover, thereby displaying the base and the article carried thereon at an angle with respect to a supporting surface such as a counter top or shelf for enhanced customer attraction.
A modified form of the invention provides for a slot in at least one edge of the base for the receipt of a transport, storage and display package. It has been found that this package can comprise an elongate transparent member with opposed pockets, one of which receives the indicia bearing information relating to the article to be displayed and the other of which is capable of receiving the article of jewelry itself for transport and storage. The package is fabricated of clear flexible material so that it can be folded for insertion into the slot so as to make the indicia bearing material visible to the user.
It is a still further object of the invention to provide an opaque pocket disposed on the back of the display pedestal for displaying the actual article to facilitate insertion of pricing and other information visible, not to the perspective purchaser, but to the salesperson.
Accordingly then production of an improved combined storage and display container and transport, storage and display package of the character above-described become the principal object of this invention with further objects thereof becoming more apparent upon reading of the following brief specification considered and interpreted in view of the accompanying drawings.


An apparatus and method for providing social network content in an online game is disclosed herein. Content is obtained from a social network site and is displayed within the game. The game also provides a mechanism for the user of the game to generate content to the posted within the social network from within the game. Such generated content is automatically posted in the social network for a recipient specified by the user.

Many games provide a virtual world or some other imagined playing space where a player of the game controls one or more player characters, engages in in-game actions, and/or acquires in-game assets. Player characters (also referred to as characters or PCs) can be considered in-game representations of the controlling player. A game engine accepts inputs from the player, determines player character actions, decides outcomes of events and presents the player with a game display illuminating what happened. In some games with multiple players, each player may control one or more player characters.
A player of a game can directly engage in in-game actions or indirectly via a player character in a role-playing game. For example, in-game actions may include building a virtual town, growing virtual crops, going on a quest, buying/selling virtual items from a virtual store, and the like. Many games also support acquisition of in-game assets (also referred to as rewards or loot) by a player in order to facilitate control of player characters or to perform in-game actions. Examples of in-game assets include, but are not limited to, acquiring game points, gold coins, experience points, character levels, character attributes, virtual cash, game keys, and other in-game items of value within the game.
In some games, a game engine may manage and display non-player characters (NPCs). Unlike player characters actively managed by players. NPCs get their movements, actions, decisions, etc. from the game engine. The game engine many provide NPCs within a game, for example, to make the game space more realistic or because the game does not have player characters. Because NPCs are not controlled by player inputs, they can sometimes appear lifeless or indistinguishable from each other.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Providing social network content in games


A vehicle control device using brake hydraulic pressure includes a hydraulic unit having a housing and an electronic control unit having a casing. The housing of the hydraulic unit is mounted on a mounting surface of the casing of the electronic control unit so that the casing of the electronic control unit protrudes from the housing of the hydraulic unit to one side. On the protruding area of the casing, a bulge is formed in which a vehicle behavioral sensor is mounted. A control connector is also provided on the protruding area of the casing. The bulge does not protrude from the substantially square contour of the vehicle control device. Thus, the bulge will scarcely increase the installation space of the vehicle control device. A vehicle behavioral sensor is mounted on a small substrate. By adjusting the angle and position of the small substrate relative to a control substrate in the casing, the position of the sensor can be adjusted relative to the travel direction, lateral direction and vertical direction of the vehicle. With the position of the sensor adjusted, the small substrate is fixed to the bulge of the casing.

The present invention relates to a vehicle control device mounted in a vehicle brake hydraulic pressure control system such as an anti-lock brake system (ABS), a traction control system (TRC) or an electronic stability control system (ESC).
This type of vehicle control device is shown in FIG. 6. As shown, it includes a hydraulic unit (HU) 1, a motor M mounted on one side of the hydraulic unit, and an electronic control unit (ECU) mounted on the other side of the hydraulic unit. The hydraulic unit 1 includes a reservoir 3, a pump 4, control valves 5 for pressure increase, and control valves 6 for pressure reduction, which are all mounted in an aluminum housing 10. The housing 10 is formed with master cylinder ports 7 which communicate with wheel cylinder ports 8 through passages 9a in which the control valves 5 for pressure increase are provided. The wheel cylinder ports 8 also communicate with the reservoir 3 through passages 9b in which the control valves 6 for pressure reduction are provided. The reservoir 3 also communicates with the wheel cylinder ports 8 through passages 9c in which the pump 4 and the control valves 5 for pressure increase are provided.
The electronic control unit 2 includes a control substrate 21 mounted in a resin casing 20 for controlling the hydraulic pressure control valves 5 and 6. The hydraulic pressure control valves 5 and 6, motor M and other units are electrically connected to the control substrate 21. The control substrate 21 controls these units based on signals from various sensors such as wheel speed sensors (as disclosed in JP patent publications 8-11691 and 2001-260846 (both unexamined)). Various electronic control parts 23 are mounted on the control substrate 21. A power source/control connector 24 is mounted on the outer surface of the casing 20.
Normally, the control valves 5 for pressure increase are kept open while the control valves 6 for pressure reduction are kept closed. Thus, when the brake pedal is depressed in this state, hydraulic pressure is supplied from the master cylinder into the passages 9a through the master cylinder ports 7, and then into respective wheel cylinders through the control valves 5 for pressure increase and the wheel cylinder ports 8. The brakes are thus applied to the respective wheels.
If such a vehicle control device is mounted in a vehicle brake hydraulic pressure control system such as ABS, TRC or ESC, the control substrate 21 controls the hydraulic control valves 5 and 6 based on signals from various vehicle behavioral sensors, which are mounted on the control substrate 21, thereby controlling the respective wheel cylinder pressures during e.g. electronic stability control.
With increasing demands for more luxurious and safer motor vehicles, an increasing number of today's automobiles are equipped with driving dynamics sensors, which are a type of vehicle behavioral sensors, to detect the movement of the vehicle in every direction, thereby optimally controlling the brake hydraulic pressure based on the signals from these sensors so that the vehicle can travel more smoothly and safely.
Such driving dynamics sensors are ordinarily mounted at the center of gravity of the vehicle. However, the center of gravity of the vehicle is typically not located in the engine room, in which the vehicle control device is mounted. Thus, it is usually necessary to connect them together through a wire harness.
The use of a wire harness and connectors pushes up the cost of the device, and necessitates measures for fixing it to the vehicle body, which further pushes up the cost of the device. Also, a dedicated sensor bracket is necessary for fixing to the vehicle body. To solve this problem, JP patent publication 2004-506572 proposes to mount the driving dynamics sensors in the electronic control unit 2 of the vehicle control device.
In particular, this publication proposes to mount vehicle behavioral sensors such as driving dynamics sensors S in a bulge 20a (shown by chain line in FIG. 6) formed on the rear surface of the casing 20 of the electronic control unit 2.
The bulge 20a increases the dimension of the vehicle control device in the horizontal direction of FIG. 6. This is not desirable especially in view of the fact that it is acutely desired today that vehicle parts, including the vehicle control device, be as small as possible.
An object of the present invention is to provide a compact vehicle control device carrying vehicle behavioral sensors such as driving dynamics sensors in the electronic control unit.

Vehicle control device utilizing brake hydraulic pressure


The present application discloses a method for resolving harmonic ambiguity and inter-array harmonic tracking. The method allows derivation of a complete set of possible harmonic families given the selection (by an operator) or automatic detection (by an automated algorithm) of a single tone (fselected) from a frequency spectrum using a novel “ambiguity matrix” approach in which a matrix of all N possible harmonic members and M hypothetical fundamentals is constructed. The ambiguity matrix provides an image of all possible harmonic families associated with a selected tone. The selection of the correct fundamental is then made based on simple comparisons between this image and the set of all possible fundamentals. The ambiguity matrix effectively provides a reduced finite solution space (discrete set of possibilities) in which to unambiguously estimate the correct fundamental.

(1) Field of Invention
The invention relates to signal processing approaches for tracking systems and, more particularly, to a method for resolving harmonic ambiguity and inter array harmonic tracking that calculates a complete set of possible harmonic families given the automatic or manual selection of a target frequency from a frequency spectrum.
(2) Background of the Invention
Tracking systems utilize radiating beam-forming sources to probe an area to be searched so as to detect objects. For example, in conventional sonar devices a highly directional beam of sonic energy periodically radiates from a scanning transducer, and a receiver detects echoes reflected from object(s) within range. Modern active sonar systems commonly provide multibeam capabilities as well.
A detectable target typically return-radiates signals over a wide bandwidth. However, only energy from a single frequency is used for target detection in conventional passive sonar systems. Since only a fractional part of the total energy is present at any given frequency, this places a significant constraint on detection ability of conventional circuitry. When uncorrelated noise and clutter is added to the radiated signals, it becomes more and more difficult to identify target signals amidst the noisy signals. Thus, in a high noise environment, the resulting low signal to noise ratio of the target signature results in a generally unacceptable trade-off between no detection or unacceptable false alarms. The target signature will comprise a "fundamental" frequency together with an infinite number of harmonics, the amplitude of the Nth harmonic being 1/N of the amplitude of the fundamental component. The target signature is embedded in a noisy signal. The trick then is to resolve the target signature from amidst the noise despite ambiguity. Prior efforts have been undertaken to pursue this goal.
For example, U.S. Pat. No. 5,034,931 to Wells discloses a method for enhancing target detection through the processing of the fundamental frequency and a plurality of harmonics that are embedded in background noise. Signals comprising a fundamental frequency signal (fo) and a plurality of harmonic frequency signals (2fo, 3fo . . . nfo) embedded in the background noise are received for processing. The plurality of harmonic frequencies are processed to determine the background noise level and to determine which of the harmonic frequency signals contain harmonics of the fundamental frequency signal. The fundamental frequency signal and those harmonic signals that are harmonics thereof are integrated to provide a summed signal. The summed signal is then processed by comparing it to a threshold level that is a function of the background noise level to provide an enhanced target detection signal. The enhanced target detection signal is then displayed on a monitor.
In addition to the Wells '931 threshold approach, other types of signal processing include broad-band amplification, narrow band filtering, variable gain, automatic gain control (AGC), use of an adaptive filter for noise cancellation, neural net identification, FFT or wavelet-based analysis or decomposition, joint time frequency analysis, transfer functioning correlation techniques, template matching, beam-forming algorithms, timing measurements, harmonic analysis, use of decision trees, comparison with a data base and auto-calibration.
Unfortunately, the Wells '931 and other known automatic harmonic detection algorithms suffer from the ambiguity associated with the existence of multiple probable solutions. For example, a given harmonic set H=fo*[1 2 3 4 5 6 7 8 9 . . . ] will result in other possible sub-harmonic sets being selected such as J=fo*[2 4 6 8 . . . ] or K=fo*[3 6 9 12 15 . . . ], etc. These solutions are difficult to resolve in cases where the individual components vary in intensity from member to member. In the case where there is an intensity (power) distribution that coincides with even (or odd) harmonics the associated sub-harmonic set (i.e., J or K) can produce a more likely solution (i.e. total energy) than the set produced from the actual fundamental (i.e., H).
Another drawback to the traditional approaches is the existence of an infinite solution space, over which the search must be performed, thus requiring significant effort and/or computational overhead to resolve.
It would be greatly advantageous to provide a more practical and efficient method for resolving harmonic ambiguity and inter array harmonic tracking capable of calculating a complete set of possible harmonic families given the selection (by an operator) or automatic detection (by an automated algorithm) of a single tone (fselected) from a frequency spectrum using a novel "ambiguity matrix" approach in which a matrix of all N possible harmonic members and M hypothetical fundamentals is constructed. An ambiguity matrix would provide the operator with an image of all possible harmonic families associated with the selected tone. The selection of the correct fundamental could then be based on simple comparisons between this image of the set of all possible fundamentals. This ambiguity matrix would effectively provide a greatly-reduced and finite solution space (a discrete set of possibilities) in which to unambiguously estimate the correct fundamental.

Harmonic ambiguity resolver and inter array harmonic tracker

The United States of America as represented by the Secretary of the Navy


A method, computer program, and computer system is provided for aligning across layers in a coded video stream. A video bitstream having multiple layers is decoded. One or more subpicture regions are identified from among the multiple layers of the decoded video bitstream, the subpicture regions including a background region and one or more foreground subpicture regions. An enhanced subpicture is decoded and displayed based on a determination that a foreground subpicture region is selected. The background region is decoded and displayed based on a determination that a foreground subpicture region was not selected.

Video coding and decoding using inter-picture prediction with motion compensation has been known for decades. Uncompressed digital video can consist of a series of pictures, each picture having a spatial dimension of, for example, 1920×1080 luminance samples and associated chrominance samples. The series of pictures can have a fixed or variable picture rate (informally also known as frame rate), of, for example 60 pictures per second or 60 Hz. Uncompressed video has significant bitrate requirements. For example, 1080p60 4:2:0 video at 8 bit per sample (1920×1080 luminance sample resolution at 60 Hz frame rate) requires close to 1.5 Gbit/s bandwidth. An hour of such video requires more than 600 GByte of storage space.
One purpose of video coding and decoding can be the reduction of redundancy in the input video signal, through compression. Compression can help reducing aforementioned bandwidth or storage space requirements, in some cases by two orders of magnitude or more. Both lossless and lossy compression, as well as a combination thereof can be employed. Lossless compression refers to techniques where an exact copy of the original signal can be reconstructed from the compressed original signal. When using lossy compression, the reconstructed signal may not be identical to the original signal, but the distortion between original and reconstructed signal is small enough to make the reconstructed signal useful for the intended application. In the case of video, lossy compression is widely employed. The amount of distortion tolerated depends on the application; for example, users of certain consumer streaming applications may tolerate higher distortion than users of television contribution applications. The compression ratio achievable can reflect that: higher allowable/tolerable distortion can yield higher compression ratios.
A video encoder and decoder can utilize techniques from several broad categories, including, for example, motion compensation, transform, quantization, and entropy coding, some of which will be introduced below.
Historically, video encoders and decoders tended to operate on a given picture size that was, in most cases, defined and stayed constant for a coded video sequence (CVS), Group of Pictures (GOP), or a similar multi-picture timeframe. For example, in MPEG-2, system designs are known to change the horizontal resolution (and, thereby, the picture size) dependent on factors such as activity of the scene, but only at I pictures, hence typically for a GOP. The resampling of reference pictures for use of different resolutions within a CVS is known, for example, from ITU-T Rec. H.263 Annex P. However, here the picture size does not change, only the reference pictures are being resampled, resulting potentially in only parts of the picture canvas being used (in case of downsampling), or only parts of the scene being captured (in case of upsampling). Further, H.263 Annex Q allows the resampling of an individual macroblock by a factor of two (in each dimension), upward or downward. Again, the picture size remains the same. The size of a macroblock is fixed in H.263, and therefore does not need to be signaled.
Changes of picture size in predicted pictures became more mainstream in modern video coding. For example, VP9 allows reference picture resampling and change of resolution for a whole picture. Similarly, certain proposals made towards VVC (including, for example, Hendry, et. al, "On adaptive resolution change (ARC) for VVC", Joint Video Team document JVET-M0135-v1, Jan. 9-19, 2019, incorporated herein in its entirety) allow for resampling of whole reference pictures to different—higher or lower—resolutions. In that document, different candidate resolutions are suggested to be coded in the sequence parameter set and referred to by per-picture syntax elements in the picture parameter set.

Method for alignment across layers in coded video stream


A power supply system for a car in which a first group of loads is selected by a key switch and fed power via a fuse, while a second parallel connected group of loads is fed power without a fuse via respective ones of control units coupled to transmission lines for controlling each of the second group of loads.

The present invention relates to an apparatus for driving a plurality of electrical loads of a vehicle by feeding electricity to the loads from a single power source.
An apparatus for driving electrical loads of a car, for example, is disclosed in JP-A-77680/1993.
The disclosed apparatus estimates a permissible supply power of a battery and a total consumption power of electrical loads, and regulates the power fed to loads of a lower functional priority, such as a rear defogger, a sheet heater, and so forth.
Even if the above-mentioned apparatus is used, a large current, referred to as a rush current, is needed on starting an electrical load. Therefore, nevertheless the fed power for loads of a lower functional priority is stopped, engine speed decreases in response to the generator's increasing its generated power output, and the load on the engine rapidly increases, on starting of the electrical loads. That is, the existing apparatus causes the engine speed to rapidly change when the electrical loads are started.
The present invention has been achieved in consideration of the above-described problem, and is aimed at providing an apparatus for driving electrical loads of a car, in which the engine speed does not rapidly change, even if operational states of an electrical load change.
To attain the above-mentioned objective, the present invention provides an apparatus for driving electrical loads of a car, comprising:
a plurality of direction devices comprising load switches, each of the direction devices being provided at one of a plurality of electrical loads arranged at the car, for directing an ON/OFF state of the one of the plurality of electrical loads; PA1 storage apparatus or a memory for storing an increase rate per unit time of power feeding (hereafter referred to a power feeding increase rate) preset for each of the plurality of electrical loads when a corresponding one of the direction devices indicates a state transition from an OFF state to an ON state; PA1 a plurality of drive devices comprising an output front stage transistor and an output driving stage transistor, each of the drive devices being provided at each of the plurality of electrical loads, for feeding power to the one of the plurality of electrical loads and for changing the amount of a power fed to the one from a power source; and PA1 control apparatus comprising a CPU for checking an operational state of each of the plurality of electrical loads, and, if the control apparatus has judged that at least one of the direction devices has indicated the state transition, sending such a control signal to a corresponding one of the drive devices that power is fed to a corresponding one of the electrical loads from the power source, with a power feeding increase rate preset and stored in the storage-apparatus, corresponding to the electrical load.
In the above-mentioned apparatus for driving the electrical loads, further, the storage apparatus stores a minimum ratio of power feeding (hereafter referred to a minimum power feeding ration) preset for each of the plurality of the electrical loads, which is kept even at a OFF state of a corresponding one of the direction devices, and the control apparatus sends such a control signal to a corresponding one of the drive devices that power is fed to a corresponding one of the electrical loads from the power source, which is at a stopping state, with a minimum power feeding ratio preset and stored in the storage apparatus, corresponding to the electrical load at the stopping state.
In the above-mentioned apparatus for driving the electrical load, further, an engine state detector comprising a key switch, an accelerator opening sensor and an engine revolution speed sensor for detecting an operational state of an engine of the car is included. The storage apparatus stores a power feeding increase rate preset for each of the plurality of electrical loads, according to each of the predetermined operational states of the engine, and the control apparatus or CPU checks a switching state of each of the plurality of direction devices. If the control apparatus judges that at least one of the direction devices has indicated the state transition, it sends such a control signal to a corresponding one of the drive devices that power is fed to a corresponding one of the electrical loads from the power source, with a power feeding increase rate preset and stored in the memory, corresponding to the electrical load and according to an operational state of the engine detected by the engine state detector.
In the above-mentioned apparatus for driving the electrical loads, the engine state detector includes an engine starting state detector for detecting whether the engine is at a starting state, the storage apparatus stores data indicating whether power is to be fed to each of the plurality of electrical loads, depending on functional importance of a corresponding one of the electrical loads, when a corresponding one of the direction devices directs driving of the corresponding one of the electrical loads at the starting state of the engine, and the control apparatus determines whether power is to fed to one of the plurality of electrical loads, of which driving is directed by one of the direction devices, and sends such a control signal to a corresponding one of the drive devices that power feeding to the corresponding one of the electrical loads is stopped if the control apparatus determines it is not necessary to feed power to the electrical load. Power feeding to the corresponding one of the electrical loads is continued if the control apparatus determines it is necessary to feed power to the electrical load, by referring to the data stored in the memory.
In the above-mentioned apparatus for driving the electrical loads, further, the engine state detector includes an accelerator operating amount detector for detecting an operation amount of an accelerator pedal operated by an operator, the storage apparatus stores a decrease rate per unit time of power feeding (hereafter referred to a power feeding decrease rate) preset for each of the plurality of electrical loads if an acceleration required by an operator exceeds the predetermined value, and the control apparatus estimates the acceleration required by an operator based on the operation amount of the accelerator pedal detected by the accelerator operating amount detector, and sends such a control signal to a corresponding one of the drive devices that power is fed to one of the plurality of electrical loads, of which driving is directed by one of the direction devices, with a power feeding decrease rate preset and stored in the storage apparatus, corresponding to the electrical load.
In the above-mentioned apparatus for driving the electrical loads, a fuel amount detector is provided for detecting a residual fuel amount left in a fuel tank of the car, the storage apparatus stores a decrease rate per unit time of power feeding (hereafter referred to a power feeding decrease rate) preset for each of the plurality of electrical loads, the power feeding decrease rate for each of the plurality of electrical loads being used when the residual fuel amount is less than the predetermined value, and the control apparatus sends such a control signal to a corresponding one of the drive devices that power is fed to one of the plurality of electrical loads, of which driving is directed by one of the direction devices, with a power feeding decrease rate preset and stored in the memory, corresponding to the electrical load, if the residual fuel amount detected by the fuel amount detector is less than the predetermined value.
As mentioned above, if at least one of the direction devices indicates the state transition from a stopping state to an operation state, the control apparatus sends such a control signal to a corresponding one of the drive devices that power is fed to a corresponding one of the electrical loads with a power feeding increasing rate preset and stored in the memory, corresponding to the electrical load. Thus, power is fed to the electrical load with the preset power feeding increase rate from the power source. That is, when starting of an electrical load is directed by one of the direction devices manipulated by an operator, power feeding to the electrical load starts and the ratio of the power feeding gradually increases. Therefore, at the stating state of an electrical load, because it hardly happens that the generator rapidly increases the generated power, and puts a rapid load on the engine, the engine speed can be kept stable.

Apparatus for driving electrical loads provided at a car


A handgun includes a locking mechanism disposed within a thickness of a grip, the locking mechanism being configured to engage with a lever associated with a slider and a magazine carried within a cavity formed by the grip; and a spring-loaded lock pivotally attached to the frame and configured to engage with a lip on a side surface of the slider, the spring-loaded lock being configured to secure the slide in a fixed position when engaged with the lip. A method includes disengaging the magazine after all bullets therein are used via the locking mechanism; and releasing the slide as the new loaded magazine is placed in the cavity of the grip via the spring-loaded lock.

1. Field of the Invention
The present invention relates generally to self-loading firearms, and more commonly, to a handgun with an automatic slide and magazine catch system.
2. Description of Related Art
Self-loading firearms are well known in the art and are an effective means to provide protection and/or enjoyment to the shooter. In one commonly known embodiment, as depicted in FIG. 1, the handgun 101 includes a frame 103, a slide 105 and a grip 107. The slide 105 moves fore and aft relative to the frame 103, as indicated by arrow D11, during use.
A magazine 109 includes a frame 113 that forms a hollow cavity and a spring loaded follower 115 configured to slidingly engage with the hollow cavity. After all cartridges are fired, the follower reaches the lip 117 and engages with the slide 105, holding the slide 105 in the rearmost position, and at this point the magazine is subsequently removed from the cavity formed by grip 107 by pressing button 102, as depicted with arrow D13. After another loaded-magazine is placed into the cavity formed by the grip 107, a lever 111 is manipulated to release the slide 105 and return the slide 105 back to the firing position, as depicted in FIG. 1.
A problem commonly associated with self-loading firearms such as a handgun 101 is the time required to manipulate button 102, which removes the empty magazine, and then return the slide back to the closed position after the magazine 109 is reinserted in the cavity created by grip 107 by manipulating lever 111. This limitation can create significant issues, e.g., during a fast-paced gun fight.
Although great strides have been made in the area of self-loading firearms, many shortcomings remain.
While the system and method of use of the present application is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular embodiment disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present application as defined by the appended claims.

Self-loading firearm with automatic slide and magazine catch and release


Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.

A non-volatile memory is a type of memory device that retains stored data when power is removed. There are various types of non-volatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is the flash EEPROM device (also referred to as "flash memory")
Each non-volatile memory device has its own unique characteristics. For example, the memory cells of an EPROM device are erased using an ultraviolet light, while the memory cells of an EEPROM device are erased using an electrical signal. In a conventional flash memory device blocks of memory cells are simultaneously erased. The memory cells in a ROM device, on the other hand, cannot be erased at all. EPROMs, EEPROMs and flash memory are commonly used in computer systems that require reprogrammable non-volatile memory.
A conventional flash memory device includes a plurality of memory cells, each cell is provided with a floating gate covered with an insulating layer. There is also a control gate which overlays the insulating layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the cell substrate. This insulating layer is an oxide layer and is often referred to as the tunnel oxide. The substrate contains doped source and drain regions, with a channel region disposed between the source and drain regions.
In a flash memory device, a charged floating gate represents one logic state, e.g., a logic value "0," while a non-charged floating gate represents the opposite logic state e.g., a logic value "1." The flash memory cell is programmed by placing the floating gate into one of these charged states. A flash memory cell is un-programmed, or erased, when the charge is removed from the floating gate.
One method of programming a flash memory cell is accomplished by applying a known potential to the cell's drain and a programming potential to its control gate. This causes electrons to be transferred from the source to the floating gate of the memory cell. The programming action of transferring electrons to the floating gate results in a memory cell that conducts less current when read than it would otherwise in the un-programmed state.
Large negative voltages up to e.g., −9.5V are often used when erasing a flash memory cell. Once the erase operation is finished, the large negative voltage (VN) must be discharged to a ground potential (e.g., 0V) in a fixed period of time. Typically, an n-channel pull-down transistor is used to discharge the voltage VN. Because this n-channel "discharge" transistor will have the large negative voltage VN (e.g., −9.5V) across its source/drain terminals, the discharge transistor is prone to the phenomenon known as "snapback." MOSFET snapback is typically defined as a phenomenon in which a MOSFET switches from a high voltage/low current state to a low voltage/high current state by activating the parasitic bipolar device between the MOSFET source, body and drain. A trigger voltage, Vt, is the voltage at which the regenerative effects associated with MOSFET snapback begin.
As is known in the art, a transistor is susceptible to snapback when it has a high field across it drain region (i.e., a large voltage across its source/drain). If the transistor is activated too quickly, snapback may occur. That is, snapback occurs when the parasitic bipolar transistor that exists between the source and drain (for ESD purposes) amplifies the current that results from activating the transistor. This snapback phenomenon results in a very high current between the source and drain regions of the transistor, which is undesirable and may alter the performance of the memory device.
U.S. Pat. No. 6,438,032, assigned to Micron Technology, Inc., and hereby incorporated by reference herein, discloses one technique for controlling a discharge transistor to avoid problems, such as snapback. FIG. 1 is an illustration of charge pump and discharge circuitry 50 incorporating the technique disclosed in the '032 patent. The circuitry 50 includes a charge pump 316, discharge control circuit 324, NMOS discharge transistor 288, discharge control capacitor 292, an NMOS transistor 286 and a PMOS transistor 218.
The charge pump 316 is responsible for generating an elevated erase voltage VN required for the erasure of non-volatile memory cells of the memory device containing the circuitry 50. The charge pump 316 is enabled by an active (i.e., high) erase signal ERASEP when the memory device containing circuitry 50 performs an erase operation. The erase voltage VN generated by the charge pump 316 is placed on signal output line 258, which is connected to an array of non-volatile memory cells (not shown in FIG. 1). After an erase operation takes place, the ERASEP signal transitions to inactive (i.e., low), deactivating the charge pump 316 and enabling the discharge control circuit 324.
The discharge control circuit 324 controls the discharge of the remaining voltage from the charge pump output 258 to ground through NMOS discharge transistor 288. Discharge transistor 288 is normally turned off by capacitor 292. During discharge, the gate of the discharge transistor 288 is raised by a discharge control signal DISCHARGE so that the transistor 288 operates in a linear region for a specified time period to discharge a portion of the pump voltage in a controlled, ramped manner before being driven into saturation to quickly discharge any remaining portion of the pump voltage.
The operation of the circuitry 50 is now described in slightly more detail. When the memory device performs an erase operation, the charge pump 316 is active and provides the erase voltage VN at signal output line 258. The charge pump 316, when active, turns on NMOS transistor 286, which couples circuit node 290 to the erase voltage VN on output line 258. The presence of the negative erase voltage VN on circuit node 290 ensures that the NMOS discharge transistor 288 is inactive and not conducting to ground while the charge pump 316 is active. Additionally, the coupling of the negative erase voltage VN to node 290 charges the discharge control capacitor 292 to the voltage VN. The charge pump 316, while active, also turns off PMOS transistor 218, which isolates the discharge control circuit 324 from circuit node 290 and the negative erase voltage VN.
After an erase operation, the ERASEP signal becomes inactive (low) and the charge pump 316 is deactivated. NMOS transistor 286 is turned off, isolating circuit node 290 from the voltage on the signal output line 258. At the same time, the PMOS transistor 218 is turned on, which couples the discharge control circuit 324 to circuit node 290, which is maintained at the negative erase voltage VN by the charged discharge control capacitor 292. The inactive (low) ERASEP signal also enables the discharge control circuit 324, which provides a control signal DISCHARGE (or current flow) to circuit node 290 through the PMOS transistor 218. This control signal DISCHARGE gradually charges the discharge control capacitor 292. As the discharge control capacitor 292 charges, the voltage signal on circuit node 290 gradually rises from the negative erase voltage VN to a supply voltage VCC. Circuit node 290 is coupled to the gate of the NMOS discharge transistor 288 and the rising voltage on circuit node 290 activates the discharge transistor 288 to slowly discharge the residual voltage from signal output line 258 and the disabled charge pump 316.
After discharge of the residual voltage from signal output line 258, the discharge control circuit 324 maintains a bias on the gate of the discharge transistor 288. This keeps the discharge transistor 288 enabled until the next erase operation.
Thus, as shown in FIG. 2, the '032 patent discloses activating the discharge transistor 288 (i.e., using the slowly ramping DISCHARGE control signal) over a period time Z (i.e., discharge time) to discharge the large negative erase voltage VN (e.g., −9.5V) to the ground potential (e.g., 0V). The inventors of the present invention have discovered that the snapback phenomenon depends on other factors, in addition to discharge time, such as the source/drain voltage across the discharge transistor 288. Thus, it is desirable to control the source/drain voltage across the discharge transistor 288 of a non-volatile memory device to substantially mitigate the effects of snapback and to improve the overall efficiency and operation of the memory device.

Negative voltage discharge scheme to improve snapback in a non-volatile memory