A liquid crystal display device of the present invention includes: first and second electrodes crossing each other; switching elements in a vicinity of each first and second electrode intersection; pixel electrodes respectively arranged in a matrix and partitioned from one another by the first and second electrodes; the first electrodes supplied with a gate voltage for turning ON/OFF the switching elements and the second electrodes supplied with a source voltage; third electrodes supplied with a common voltage; and a liquid crystal layer interposed between the third electrodes and the pixel electrodes. The source voltage includes an image signal voltage and an assist signal voltage. The common voltage has different values between an image signal writing scanning period defined as a period during which the image signal voltage is applied, and at least one assist signal writing scanning period defined as a period during which the assist signal voltage is applied.

1. Field of the Invention
The present invention relates to a liquid crystal display device for use in a television set, a computer, a word processor, an OA (Office Automation) apparatus, or the like, and a method for driving such a liquid crystal display device.
2. Description of the Related Art
FIG. 20 illustrates an equivalent circuit diagram of a typical active matrix type licquid crystal display device.
The liquid crystal display device includes a plurality of gate electrodes 61 and a plurality of source electrodes 62 crossing the gate electrodes 61. A switching element 63, e.g., a thin film transistor, is provided in the vicinity of each intersection of the gate electrode 61 and the source electrode 62. The display area is divided into a plurality of pixel regions arranged in a matrix, which are partitioned from one another by the gate electrodes 61 and the source electrodes 62. A pixel electrode 64 is provided in each of the pixel regions. The pixel electrode 64 is connected to the source electrode 62 via the switching element 63. A liquid crystal layer (not shown) is interposed between the pixel electrode 64 and a common electrode 65. A liquid crystal capacitor 66 is provided between the pixel electrode 64 and the common electrode 65. An image is displayed by holding an intended voltage in each liquid crystal capacitor 66.
FIG. 21 illustrates typical voltage waveforms used for driving such an active matrix type liquid crystal display device.
A pulse waveform of ON voltage Vgh for turning ON the switching element 63 is applied as a gate voltage Vg to the gate electrodes 61 for each field period. A plurality of such pulses are sequentially applied to scan the entire frame. A voltage corresponding to an image signal for the row for which the ON voltage Vgh is being input to the gate electrode 61 is applied as a source voltage Vs to the source electrode 62. A plurality of such image signals are applied sequentially. As a common voltage Vc, xc2x1Vcac is applied to the common electrode 65. Each time the ON voltage Vgh is applied to the gate electrode 61, a new source voltage Vs is applied to the pixel electrode 64 as a pixel voltage Vp. As a result, a liquid crystal voltage Vlc, which is equal to the difference between the pixel voltage Vp and the common voltage Vc, is applied through the liquid crystal layer.
FIG. 22 illustrates the relationship between the liquid crystal voltage Vlc and the transmission. FIG. 22 shows an example for a TN (twisted nematic) type normally white mode which has been used in the art as a typical liquid crystal display mode.
The output range xc2x1Vsmax of the source voltage Vs is normally set to the voltage difference between a voltage Vlca at which the 100% transmission is obtained and a voltage Vlcc at which about 1% transmission is obtained. Thus, the output range of the source voltage Vs is set to a minimum range required to obtain a practically sufficient contrast. When the output range of the source voltage Vs is set to be higher than this, a source driver having a high voltage resistance is required, thereby increasing the cost of the device. Therefore, the source voltage Vs and the common voltage Vc with respect to the liquid crystal voltage Vlc are set as shown in the following Expression 1.
Vlca=┌+Vsmaxxc2x1Vcac|
Vlcb=└+Vcac|
Vlcc=└+Vsmaxxc2x1Vcac|xe2x80x83xe2x80x83Expression 1
FIG. 23 illustrates transmission response characteristics of the liquid crystal panel. In FIG. 23, a solid line shows the change in the transmission obtained when the image signal is changed from white displayxe2x86x92black displayxe2x86x92white display, and a broken line shows the change in the transmission obtained when the image signal is changed from white displayxe2x86x92gray-level displayxe2x86x92white display.
FIG. 23 shows that when the image signal is changed from white displayxe2x86x92black displayxe2x86x92white display, each transmission response is substantially completed within one field period. However, when the image signal is changed from white displayxe2x86x92gray-level displayxe2x86x92white display, the transmission does not change to a transmission corresponding to the image signal within one field period. Thus, between two image signals where the voltage difference is small, the transmission response may be slow.
Liquid crystal display devices have been wide spread as thin display devices as the image qualities thereof, e.g., the contrast, the brightness, and the color reproducibility, have been improved and are now comparable to those of other types of display devices such as CRTs. However, liquid crystal display devices have a relatively slow response as described above. Therefore, when displaying a motion picture on a liquid crystal display device, the displayed picture may be blurred or the after-image phenomenon may occur. This drawback has prevented liquid crystal display devices from replacing CRTs in some applications.
Japanese Laid-Open Publication No. 56-27198 discloses a display device which produces a color display by using a black and white liquid crystal panel in combination with a light source whose output color is switched among red, blue and green. This is called a xe2x80x9cfield sequential color methodxe2x80x9d.
In this method, the output color of the light source is switched among red, blue and green while an image corresponding to each output color is synchronously displayed. Therefore, when displaying a color image, the image signal changes for each display operation even if the image is stationary. Thus, when the response of the liquid crystal panel is slow, the color information for one display operation and the color information for the next display operation may be mixed together, thereby reducing the color reproducibility. In such a case, it is difficult to realize a sufficient display performance.
As described above, the slow response of the liquid crystal panel has been a drawback which deteriorates the display performance. In order to address such a drawback, various methods have been proposed in the art as follows.
For example, Japanese Laid-Open Publication No. 4-42211 proposes a method in which a voltage corresponding to an assist signal, which is different from an image signal, is applied before applying a voltage corresponding to the image signal. This method is based on the fact that the effective liquid crystal response speed (i.e., the speed of the response of the liquid crystal molecules to an applied voltage) can be increased by applying a voltage which is larger or lower than the voltage corresponding to the image signal through the liquid crystal layer before applying the voltage corresponding to the image signal therethrough. This method improves the motion picture display quality.
xe2x80x9cSID 98 DIGEST P. 143 A Novel Wide-Viewing Angle Motion-Picture LCDxe2x80x9d proposes another method in which a voltage corresponding to an assist signal is applied before applying a voltage corresponding to an image signal. This method improves the motion picture display quality by erasing the displayed image before displaying the next image.
Japanese Laid-Open Publication No. 9-138421 proposes a driving method in which a voltage corresponding to an assist signal is applied by activating all scanning lines and then providing the assist signal by varying the common voltage at each common electrode before applying the voltage corresponding to the image signal.
It is possible to prevent the color reproducibility from being reduced by applying the above-described improvements to the field sequential color method.
As described above, it is possible to increase the liquid crystal response by providing a period for the application through the liquid crystal panel of a voltage corresponding to an assist signal, which is not an image signal, before the period for the application of a voltage corresponding to the image signal. In order to effectively improve the liquid crystal response, it is important to appropriately set the voltage value of the assist signal and the length of the period for the application of the voltage corresponding to the assist signal.
Generally, as the amount of change in the voltage to be applied through the liquid crystal layer is larger, it is possible to impart a larger energy to the liquid crystal molecules thereby increasing the response of the display device. Therefore, the voltage value corresponding to the assist signal is preferably set to a voltage value which exceeds the voltage range for the image signals. It is further preferred that the voltage corresponding to the assist signal is variable according to the voltage corresponding to the image signal.
The above-described driving method increase the response speed of the liquid crystal panel by utilizing the transitional response in the period for the application of the voltage corresponding to the assist signal. Therefore, it is preferred that the period for the application of the voltage corresponding to the assist signal can be set to an optimal period for the response characteristics of the liquid crystal panel to be used.
However, the above-described driving method suffers from the following operational limitations, and it has been difficult to effectively improve the liquid crystal response speed.
In the method of Japanese Laid-Open Publication No. 4-42211, a voltage corresponding to an assist signal, which is different from an image signal, is applied from a source electrode through a pixel electrode via a switching element before applying a voltage corresponding to the image signal from the source electrode through the pixel electrode via the switching element. Then, in order to apply a voltage which exceeds the voltage range for the image signals through the liquid crystal layer, it is necessary to increase the voltage resistance of the source driver for inputting the signal voltage to the source electrode, thereby increasing the production cost. Moreover, since the voltage corresponding to the assist signal is applied via the switching element, it is necessary to apply the voltage corresponding to the assist signal within a short period which is provided in addition to the period for the application of the voltage corresponding to the image signal. To do so, it is necessary to dramatically improve the performance of the switching element. Therefore, it is difficult to employ the method in practical use.
In the method of xe2x80x9cSID 98 DIGEST P. 143 A Novel Wide-Viewing Angle Motion-Picture LCDxe2x80x9d, the scanning operation for applying a voltage corresponding to an image signal from a source electrode to a pixel electrode via a switching element and the scanning operation for applying a voltage corresponding to an assist signal from the source electrode to the pixel electrode via the switching element are repeated. Again, in order to apply a voltage which exceeds the voltage range for the image signals through the liquid crystal layer, it is necessary to increase the voltage resistance of the source driver for inputting the signal voltage to the source electrode, thereby increasing the production cost. Moreover, during the period in which the voltage corresponding to the assist signal is applied to the liquid crystal panel, an image signal cannot be displayed, thereby lowering the brightness of the display screen. In order to prevent such reduction of the brightness, the assist signal period is preferably set to be short. It is further preferred that the period in which the voltage corresponding to the assist signal is applied to the liquid crystal panel is set to a minimum period required for ensuring a sufficient liquid crystal response. However, in order to shorten the period in which the voltage corresponding to the assist signal is applied to the liquid crystal panel in this driving method, it is necessary to shorten the assist signal writing scanning period (i.e., the period for a scanning operation for writing the assist signal). To do so, it is necessary to increase the size of the switching element so as to improve the performance of the switching element. Thus, there may occur problems such as an increased defect rate for the switching element, thereby increasing the production cost.
In the method of Japanese Laid-Open Publication No. 9-138421, a voltage corresponding to an assist signal is applied after activating all scanning lines, whereby a constant voltage is applied through all pixels as the voltage corresponding to the assist signal. In an actual image display operation, however, the voltage corresponding to the image signal varies for various pixels, whereby it is necessary to set assist signals respectively corresponding to different image signals for the various pixels in order to reduce the response speed for each pixel, i.e., in order to reduce the amount of time required for the transmission of each pixel to reach the transmission corresponding to the image signal for that pixel. Therefore, the response speed cannot be improved effectively by using such an assist signal that is constant and does not correspond to the image signal for each pixel. Moreover, when writing the assist signal, all of the gate electrodes are activated, and the capacity load per source electrode increases, whereby it is necessary to provide a high-performance source driver capable of driving such an increased capacity load.
Moreover, in each of the above-described driving methods, the voltage corresponding to the assist signal is applied via the switching element, thereby increasing the amount of power consumed by the source driver when writing the assist signal, and thus deteriorating a feature of liquid crystal display devices, i.e., a small power consumption.
According to one aspect of this invention, a liquid crystal display device includes: a plurality of first electrodes; a plurality of second electrodes crossing the first electrodes; a plurality of switching elements each provided in a vicinity of an intersection of the first electrode and the second electrode; a plurality of pixel electrodes respectively provided in a plurality of regions which are arranged in a matrix and partitioned from one another by the first electrodes and the second electrodes; a plurality of first electrodes to each of which a gate voltage is applied for turning ON/OFF each of the switching elements; a plurality of second electrodes to each of which a source voltage is applied; and a plurality of third electrodes to each of which a common voltage is applied, the third electrodes being arranged so that a liquid crystal layer is interposed between the third electrodes and the pixel electrodes. The source voltage includes a voltage corresponding to an image signal and another voltage corresponding to an assist signal. The common voltage has different values between an image signal writing scanning period and at least one assist signal writing scanning period, the image signal writing scanning period being defined as a period during which the voltage corresponding to the image signal is applied, and the assist signal writing scanning period being defined as a period during which the voltage corresponding to the assist signal is applied.
In one embodiment of the invention, a liquid crystal capacitor is provided between one of the pixel electrodes and one of the third electrodes.
In one embodiment of the invention, a liquid crystal capacitor is provided between one of the pixel electrodes and one of the second electrodes.
According to another aspect of this invention, a liquid crystal display device includes: a plurality of first electrodes; a plurality of second electrodes crossing the first electrodes; a plurality of switching elements each provided in a vicinity of an intersection of the first electrode and the second electrode; a plurality of pixel electrodes respectively provided in a plurality of regions which are arranged in a matrix and partitioned from one another by the first electrodes and the second electrodes; a plurality of first electrodes to each of which a gate voltage is applied for turning ON/OFF each of the switching elements; a plurality of second electrodes to each of which a source voltage is applied; and a plurality of third electrodes to each of which a common voltage is applied, the third electrodes being arranged so that a liquid crystal layer is interposed between the third electrodes and the pixel electrodes. The liquid crystal display device further includes a plurality of assist electrodes to each of which an assist voltage is applied, the assist electrode having an assist capacitor being provided between each of the pixel electrodes and the assist electrode. An image signal application period is defined as a period during which a voltage corresponding to an image signal is applied between the pixel electrode and the third electrode. An assist signal application period is defined as a period during which a voltage corresponding to an assist signal is applied between the pixel electrode and the third electrode. At least one of the common voltage and the assist voltage has different values between the image signal application period and the assist signal application period.
According to still another aspect of this invention, a liquid crystal display device includes: a plurality of first electrodes; a plurality of second electrodes crossing the first electrodes; a plurality of switching elements each provided in a vicinity of an intersection of the first electrode and the second electrode; a plurality of pixel electrodes respectively provided in a plurality of regions which are arranged in a matrix and partitioned from one another by the first electrodes and the second electrodes; a plurality of first electrodes to each of which a gate voltage is applied for turning ON/OFF each of the switching elements; a plurality of second electrodes to each of which a source voltage is applied; and a plurality of third electrodes to each of which a common voltage is applied, the third electrodes being arranged so that a liquid crystal layer is interposed between the third electrodes and the pixel electrodes. The liquid crystal display device further includes a plurality of assist electrodes to each of which an assist voltage is applied, the assist electrode having an assist capacitor being provided between each of the pixel electrodes and each of the first electrodes. An image signal application period is defined as a period during which a voltage corresponding to an image signal is applied between the pixel electrode and the third electrode. An assist signal application period is defined as a period during which a voltage corresponding to an assist signal is applied between the pixel electrode and the third electrode. At least one of the common voltage and the assist voltage has different values between the image signal application period and the assist signal application period.
According to still another aspect of this invention, there is provided a method for driving a liquid crystal display device. The liquid crystal display device includes: a plurality of first electrodes; a plurality of second electrodes crossing the first electrodes; a plurality of switching elements each provided in a vicinity of an intersection of the first electrode and the second electrode; a plurality of pixel electrodes respectively provided in a plurality of regions which are arranged in a matrix and partitioned from one another by the first electrodes and the second electrodes; a plurality of first electrodes to each of which a gate voltage is applied for turning ON/OFF each of the switching elements; a plurality of second electrodes to each of which a source voltage is applied; and a plurality of third electrodes to each of which a common voltage is applied, the third electrodes being arranged so that a liquid crystal layer is interposed between the third electrodes and the pixel electrodes. The source voltage includes a voltage corresponding to an image signal and another voltage corresponding to an assist signal. The method includes the steps of: applying the common voltage during an image signal writing scanning period which is defined as a period during which the voltage corresponding to the image signal is applied; and applying the common voltage during at least one assist signal writing scanning period which is defined as a period during which the voltage corresponding to the assist signal is applied. The common voltage has different values between the image signal writing scanning period and the at least one assist signal writing scanning period.
In one embodiment of the invention, a liquid crystal capacitor is provided between one of the pixel electrodes and one of the third electrodes.
In one embodiment of the invention, a liquid crystal capacitor is provided between one of the pixel electrodes and one of the second electrodes.
In one embodiment of the invention, a range of a voltage applied to the liquid crystal capacitor during each assist signal writing scanning period is greater than a range of a voltage applied to the liquid crystal capacitor during the image signal writing scanning period.
In one embodiment of the invention, a range of a voltage applied to the liquid crystal capacitor during each assist signal writing scanning period is greater than a range of a voltage applied to the liquid crystal capacitor during the image signal writing scanning period.
In one embodiment of the invention, the source voltage applied during the assist signal writing scanning period includes a voltage for producing a black display or a white display.
In one embodiment of the invention, the source voltage applied during the assist signal writing scanning period includes a maximum voltage or a minimum voltage which can be output by a source voltage generation circuit for generating the source voltage.
In one embodiment of the invention, one field period includes at least two subfield periods including the image signal writing scanning period and the assist signal writing scanning period. A voltage corresponding to an image signal for a predetermined color component for each of the subfield periods is applied as the source voltage during the image signal writing scanning period.
In one embodiment of the invention, the one field period includes: a subfield period for displaying a red component; a subfield period for displaying a green component; and a subfield period for displaying a blue component.
According to still another aspect of this invention, there is provided a method for driving a liquid crystal display device. The liquid crystal display device includes: a plurality of first electrodes; a plurality of second electrodes crossing the first electrodes; a plurality of switching elements each provided in a vicinity of an intersection of the first electrode and the second electrode; a plurality of pixel electrodes respectively provided in a plurality of regions which are arranged in a matrix and partitioned from one another by the first electrodes and the second electrodes; a plurality of first electrodes to each of which a gate voltage is applied for turning ON/OFF each of the switching elements; a plurality of second electrodes to each of which a source voltage is applied; and a plurality of third electrodes to each of which a common voltage is applied, the third electrodes being arranged so that a liquid crystal layer is interposed between the third electrodes and the pixel electrodes. The liquid crystal display device further includes a plurality of assist electrodes to each of which an assist voltage is applied, the assist electrode having an assist capacitor being provided between each of the pixel electrodes and the assist electrode. The method includes the steps of: applying a voltage corresponding to an image signal is applied between the pixel electrode and the third electrode during an image signal application period; and applying a voltage corresponding to an assist signal is applied between the pixel electrode and the third electrode during an assist signal application period. At least one of the common voltage and the assist voltage has different values between the image signal application period and the assist signal application period.
In one embodiment of the invention, a plurality of rows of assist electrodes receive alternately different signals.
In one embodiment of the invention, a voltage which takes two or more levels is applied during the assist signal application period to one of at least one of the third electrodes and at least one of the assist electrodes.
In one embodiment of the invention, a write period is provided during which a voltage corresponding to an image signal is applied to the pixel electrodes via the switching elements. A first assist signal application period including the write period and a second assist signal application period not including the write period are provided. A polarity of a voltage between the pixel electrodes and the third electrodes is reversed with respect to a polarity of a voltage applied during the image signal application period between the write period and the second assist signal application period.
In one embodiment of the invention, the voltage for the assist signal application period is simultaneously applied to a plurality of pixels.
In one embodiment of the invention, the assist signal application period is coordinated with a timing at which the voltage corresponding to the image signal is applied to each of the pixel electrodes.
In one embodiment of the invention, a voltage exceeding a voltage range to be applied during the image signal application period is applied between the pixel electrodes and the third electrodes during the assist signal application period.
In one embodiment of the invention, one field period includes at least two subfield periods including the image signal application period and the assist signal application period. A voltage corresponding to an image signal for a predetermined color component for each of the subfield periods is applied between the pixel electrodes and the third electrodes during the image signal application period.
In one embodiment of the invention, the one field period includes: a subfield period for displaying a red component; a subfield period for displaying a green component; and a subfield period for displaying a blue component.
According to still another aspect of this invention, there is provided a method for driving a liquid crystal display device. The liquid crystal display device includes: a plurality of first electrodes; a plurality of second electrodes crossing the first electrodes; a plurality of switching elements each provided in a vicinity of an intersection of the first electrode and the second electrode; a plurality of pixel electrodes respectively provided in a plurality of regions which are arranged in a matrix and partitioned from one another by the first electrodes and the second electrodes; a plurality of first electrodes to each of which a gate voltage is applied for turning ON/OFF each of the switching elements; a plurality of second electrodes to each of which a source voltage is applied; and a plurality of third electrodes to each of which a common voltage is applied, the third electrodes being arranged so that a liquid crystal layer is interposed between the third electrodes and the pixel electrodes. The liquid crystal display device further includes a plurality of assist electrodes to each of which an assist voltage is applied, the assist electrode having an assist capacitor being provided between each of the pixel electrodes and each of the first electrodes. The method includes the steps of: applying a voltage corresponding to an image signal is applied between the pixel electrode and the third electrode during an image signal application period; and applying a voltage corresponding to an assist signal is applied between the pixel electrode and the third electrode during an assist signal application period. At least one of the common voltage and the assist voltage has different values between the image signal application period and the assist signal application period.
In one embodiment of the invention, a voltage which takes two or more levels is applied during the assist signal application period to one of at least one of the third electrodes and at least one of the first electrodes.
In one embodiment of the invention, a write period is provided during which a voltage corresponding to an image signal is applied to the pixel electrodes via the switching elements. A first assist signal application period including the write period and a second assist signal application period not including the write period are provided. A polarity of a voltage between the pixel electrodes and the third electrodes is reversed with respect to a polarity of a voltage applied during the image signal application period between the write period and the second assist signal application period.
In one embodiment of the invention, the voltage for the assist signal application period is simultaneously applied to a plurality of pixels.
In one embodiment of the invention, the assist signal application period is coordinated with a timing at which the voltage corresponding to the image signal is applied to each of the pixel electrodes.
In one embodiment of the invention, a voltage exceeding a voltage range to be applied during the image signal application period is applied between the pixel electrodes and the third electrodes during the assist signal application period.
In one embodiment of the invention, one field period includes at least two subfield periods including the image signal application period and the assist signal application period. A voltage corresponding to an image signal for a predetermined color component for each of the subfield periods is applied between the pixel electrodes and the third electrodes during the image signal application period.
In one embodiment of the invention, the one field period includes: a subfield period for displaying a red component; a subfield period for displaying a green component; and a subfield period for displaying a blue component.
Thus, the invention described herein makes possible the advantages of: (1) providing a liquid crystal display device in which it is possible to increase the liquid crystal response speed, prevent a motion picture from being blurred or having an after-image, improve the color reproducibility in the field sequential color method, and reduce the production cost and the power consumption; and (2) providing a method for driving such a liquid crystal display device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.

Liquid crystal display device, and method for driving the same


Systems and methods for verifying user identity in a virtual environment are provided that may include periodic transmitting/monitoring of biometric data and geographic location data. Integrated systems may include anti-tamper devices that automatically delete biometric data in the event if tampering and/or power loss. Thus, the present invention helps to prevent tampering with player identity information, as well as helping to prevent access by a player to the software, graphics or other content associated with selected online activities. Such systems and methods may find particular applicability in fields related to online gambling by verifying the identity and location of an on-line player.

The ability of criminals and cyber-terrorists to infiltrate supposedly well-defended computer networks is well known. In order to successfully breach cyber defenses, criminals or terrorists must execute actions against computer hardware and software that is typically under the complete control of third parties which may include innocent individuals, businesses, or government agencies. As a result, billions of dollars are spent on necessary countermeasures.
The present invention seeks to solve a less widely recognized problem inherent in online activities such as those that involve wagering, and other transfers of funds between individuals, such as may occur in online versions of poker, etc.
By way of example, in internet poker, 2 to 10 people typically play each other across a 'virtual' poker table. The game is managed from servers operated by an internet poker service provider (or 'poker website'). The poker website manages communications to and from remote computers that are under the near complete control of the players. It is on the graphical displays of these remote computers that the virtual poker table, avatars for other players, and card graphics are made visible to the player. For innocent players the fact that they control their own computers is of no consequence. But if the 'player' as known to the poker website and its regulators is a 'money mule' paid by a terror or crime organization (TCO), a significant vulnerability is apparent. A 'money mule' is a person hired by a TCO for his or her unblemished identity and separation from the TCO.
Contrast the problem faced by hackers trying to break into computers under the control of someone else, to that faced by a TCO hacking computers entirely under its control. Manipulation of, for example, internet poker games for the purpose of laundering money becomes astonishingly easy.
Consider a criminal enterprise (CE) seeking to offer untraceable electronic banking services to terror and crime organizations (TCOs). The CE uses technology and carefully-designed business processes to exploit the natural properties of internet poker in order to move vast sums of money among thousands of poker accounts in many different countries. The most basic operation performed by the CE is the corruption of internet poker games using 4-way collusion for the purpose of moving money from two poker accounts to two other poker accounts playing at the same virtual poker table.
Regulators in jurisdictions where internet poker is legal such as the Isle of Man, the Alderney Islands, and Gibraltar claim that by recording hand histories and the identities of the players at any virtual poker table, counter-terrorism investigators can determine connections between donors and recipients. They also claim that it is possible to determine the physical location (geo-location) of an online poker player. They further claim that automated anti-collusion detection systems can reliably find instances where two or more players are sharing card values. The fact is, the CE can breach any anti-collusion or global positioning system (GPS) or internet protocol (IP) address geo-location system currently used by internet poker websites.
The following scenario illustrates just one example of how the CE might use weaknesses in the current internet poker business model to implement a large scale money laundering operation. However, it should be appreciated that the concepts described herein are applicable to a wide variety of online activities in which the actual identity and/or location of a user is needed for verification, tracking and/or monitoring purposes.
The CE business process assigns any number of 'money mule' accounts to poker games in groups of four. This means that 4 of the 9 to 10 seats at a compromised virtual poker table are CE mule accounts. The mules never actually play the games and may not even be privy to the CE's activities. Experts at CE remotely login to the mules' computers and play games under the identities of those mules. They can also transfer money to and from the mule bank accounts and read emails sent to the mules by the poker website.
For typical money transfers, two of the mule accounts are designated as donors and two are recipients. The CE 'players' use technology that allows them to see each others hole cards in an undetectable manner that does not distract from the game in any way. The players can remain focused on the game ensuring, over time, that money moves in the right direction.
Further, specially-designed software used by the CE to generate the four-player games can easily and reliably defeat any automated anti-collusion technique employed by the poker websites or their regulators. This is done by providing each mule with two low-end computers. One computer is 'clean' and the other is 'corrupt'. The clean computer runs the internet poker client software. It contains neither the hack software nor the support software for remote access systems. If regulators require GPS verification of the computer's location, then this technology is included with the clean computer. Since the clean computer does not run any illicit software and possesses the required GPS technology (if it were required), the poker client software will never detect anything suspicious thereby enabling the CE to easily overcome geo-location requirements imposed by the poker websites and their regulators.
The corrupt computer runs all hack software, remote access support software, and the software for a frame grabber that in one implementation grabs the output signal from the clean computer's SVGA port. Keyboard and mouse commands—processed using standard drivers—are sent from the corrupt computer to a clean computer's USB port.
A minimum of three critical software processes are run on the corrupt computer. The first is an encrypted, private, CE-operated communications tool. The second is the 'card clipping' software that captures an image of the player's hole cards, transmits it to the CE's server, and retrieves the images of the other three players' hole cards. A private, CE-controlled instant messaging system is built into the card clip application. The third process allows CE 'players' (AKA 'soldiers') to control the corrupt and clean computers from anywhere in the world—again in an undetectable manner.
The CE uses state-of-the-art technology to manage communication among CE soldiers and the CE leadership. Soldiers can play poker on any computer located anywhere on the internet using a device called a 'remote access appliance' (e.g. Bomgar). Appliances such as the Bomgar device allow the CE to control thousands of remote computers without risking discovery by counter-terrorism investigators. By using a hardware appliance, the CE avoids using commercial remote access services such as GoToMyPC.com that could cooperate with law enforcement or counter-terrorism authorities. And, while all communications between CE leaders, soldiers, and cell leaders are undetectable, they are nonetheless encrypted and always sent via means under the complete control of the CE.
Custom server-side software is used to manage all administrative tasks such as maintaining login credentials for mule accounts, internal communications, game-in-progress data distribution, and generating and managing the games. An electronic database is used to persist data.
In one example, the CE business process starts with customer operative A hiring a money mule B. Mule B is instructed to open a conventional bank account and deposit money provided by operative A. Mule B is then instructed to open one or more internet poker accounts, using the mule's legitimate identity and bank account. The same process occurs between mule C and customer operative D in the country where the operative's money is to be transferred. Once the accounts are opened and the mules' identities are verified to the satisfaction of the poker website, mules B and C give the online logins for their bank account, the poker account(s), and email account associated with the poker websites to customer operatives A and D, respectively. Operatives A and D then send the logins to CE personnel using a privately operated, encrypted communication system. Finally, customer operatives A and D provide mules B and C with specially prepared computer hardware and software systems. Once these procedures are complete, the mules just need to keep the computers running and maintain connectivity to the internet. Mules are usually used indefinitely by the customer operatives and will likely be kept "in the dark", so they may or may not have knowledge of the CE's operations, and may or may not be paid for their services. And if A and B or C and D are compromised, law enforcement or counter-terrorism authorities will have no way of linking operatives A and D because the CE has procedures in place to alter personnel distribution and immediately relocate servers and other traceable technology.
The possibility of money laundering with internet poker presents law enforcement and counter-terrorism authorities with a dilemma. If a money mule is discovered, he or she is unlikely to know anything useful beyond possibly identifying their TCO contact. Furthermore, since the mule doesn't actually play poker, he or she will have no knowledge of the other players at the virtual poker tables. This ensures that authorities will likely bear the expense of an international investigation involving several different foreign jurisdictions.
As this scenario illustrates, current technology and regulatory schemes are not sufficient to keep TCOs from exploiting internet poker. Two innovations are required: (1) a way to remove substantial control of computer hardware and software from an internet poker player while allowing the computer equipment to remain in the possession of the player, and (2) a way to reliably confirm the player's true identity and/or physical location.
The present invention provides the required solution for internet poker and any other business process that requires similar controls.

System and method for verifying user identity in a virtual environment


This invention provides an illumination apparatus and an illumination method. The illumination apparatus comprises: a first light source for illuminating a first area; a second light source for illuminating a second area; a first measuring unit for measuring the illuminance of the first area; a second measuring unit for measuring the illuminance of the second area; and an adjusting unit for adjusting at least one of the first light source and the second light source to make the contrast ratio of the measured illuminance of the first area to the measured illuminance of the second area change gradually from a first predefined value to a second predefined value lower than the first predefined value during a first predefined duration. In this way, the relative higher contrast ratio (i.e. the first predefined value) enables the users to improve their work efficiency and the relative lower contrast ratio (i.e. the second predefined value) allows the users' eyes to be comfortable. In addition, because the contrast ratio changes gradually, the users' attention will not be distracted and the users' eyes will remain comfortable when the contrast ratio changes.

It is known that the illumination requirement is dependent on the visual qualities of the subject being illuminated and appropriate lighting can enhance human experience and make the task at hand easier to perform. For example, bright light is better for reading, soft warm light is better for resting, etc.
In the area of desk lighting, some of the relevant literature recommends a task-area-to-background contrast ratio of 10:3 for providing eye protection and eye comfort. However, this recommended "comfortable" contrast ratio does not consider the need to improve the working efficiency of desk lamp users.
US2007/0258243A1 provides a lighting system for delivering dynamic, fully customized and automatic illumination to a subject. The provided lighting system can adjust the pattern and spectra of light generated by a light source, on the basis of detection information on a target area detected by a sensor pad. However, US2007/0258243A1 fails to point out the relation between work efficiency and comfort of a user's eyes, and therefore fails to give the solution of adjusting the illumination with a view to working efficiency and eye comfort.
There is a need to provide a luminaire, taking into consideration both the requirements of improving working efficiency and maintaining eye comfort.


A liquid crystal display device according to the present invention has a lighting unit (UT) comprising a light guiding plate (3), a light source (2), a reflector (4), a reflecting sheet (5) and a housing (10), and a liquid crystal display panel (1). In the liquid crystal display device, increase in temperature of the light source (2) is prevented by providing an opening portion (S1) on the housing (10) such that the opening portion (S1) reaches the reflector (4). In the liquid crystal display device, light emission intensity of the lighting unit (UT) is not lowered during operation of the device, and further, a lifetime of the light source (2) is not shortened.

A liquid crystal display device characterized by extremely small power consumption has been widely used as an image display device mounted on an image device of an information device such as a notebook-type personal computer, a word processor and the like, or as an image device of a video device such as a portable television, a video movie, a car navigation system and the like, for securing sufficient operating time of the image device, because these image devices are often driven by built-in primary or secondary battery. As used herein, the liquid crystal display device refers to a device comprising, for example, a liquid crystal display panel structured such that two transparent glass substrates on which driving signal supplying electrodes formed by electrically conductive transparent thin films, alignment layers and the like are stacked, are superposed on each other with a predetermined spacing so that the surfaces of the stack are opposed to each other, and sealed after liquid crystal is filled therebetween, and polarizers are provided on outside of both the glass substrates, and configured to display an image by variation of transmissivity of light according to a driving signal inputted to the driving signal supplying electrode, a lighting unit disposed behind the liquid crystal display panel for supplying light to the liquid crystal display panel, and a circuit board and the like for driving the liquid crystal display panel.
FIG. 8 is a cross-sectional view showing an example of the liquid crystal display device comprising a conventional edge light type lighting unit. As a matter of convenience, a direction of the liquid crystal display device is shown as in the drawing. A liquid crystal display device L comprises a liquid crystal display panel 1 disposed such that a display surface 1a on which characters and images are displayed faces forward, front side frames FC formed by molding metal plates having a constant thickness into L-shape and disposed to cover a non-display display region of the display surface 1a of the liquid crystal display panel 1 with a predetermined spacing between the same and the liquid crystal display panel 1 and to form upper and lower surfaces of the end face of the liquid crystal display device L, a lighting unit UT disposed behind the liquid crystal display panel 1 for supplying light to the liquid crystal display panel, and a rear cover RC disposed to cover an entire rear surface of the lighting unit UT.
Herein, the lighting unit UT comprises a light guiding plate 3 formed by a transparent plate made of synthetic resin such as acrylic for guiding light entering from an end face thereof in a direction parallel to a principal surface thereof and emanating the light from the principal surface thereof, light sources 2 such as fluorescent discharge tubes disposed in the vicinity of end faces 3a of the light guiding plate 3 in a direction substantially parallel to the end faces 3a along the end faces 3a, reflectors 4 covering the light sources 2 in U-shape over a substantially entire length thereof, a reflecting sheet 5 formed by a white synthetic resinous sheet or the like having a high reflectivity for reflecting the light emanated from a rear principal surface of the light guiding plate 3 toward the light guiding plate 3 again, and housings 10 made of policarbonate resin or the like for supporting the reflectors 4 and the light guiding plate 3 at upper, lower, and front surfaces of the reflectors 4 and an outer peripheral portion of a front principal surface of the light guiding plate 3, fixing the liquid crystal display panel 1 and the light guiding plate 3 with a predetermined spacing, and fixing front side frames FC to predetermined positions so as to form gaps 7a.
In the liquid crystal display device L structured as described above, light emitted from the light source 2 is efficiently introduced into the end face 3a of the light guiding plate 3 by means of the reflector 4, and the light introduced into the end face 3a of the light guiding plate 3 is guided in the direction away from the light source 2 by means of the light guiding plate 3, and uniformly emanated from a front side of the light guiding plate 3 by being reflected by means of the reflecting sheet 5, and the emanated light enters the liquid crystal display panel 1. And, images are displayed on the liquid crystal display panel 1 by variation of transmissivity of light according to the driving signal inputted to the driving signal supplying electrodes.
In a meanwhile, recently, the liquid crystal display device mounted on the image device so as to obtain a light and thin image device has been required to be light and thin. And, the liquid crystal display device used in the image device such as a monitor is required to obtain high luminance in addition to lightness and thinness. Furthermore, a screen thereof becomes larger. In response to such a trend, a liquid crystal display device using the edge light type lighting unit in which a tubular light source such as a fluorescent discharge tube is disposed on an end face thereof, which is suitable for obtaining lightness and thinness, high luminance, and a large screen, is widely used.
On the other hand, the liquid crystal display device is characterized in that light emission intensity of the light source lowers with elapse of time and a lifetime of the light source becomes short when a temperature in the vicinity of the light source becomes high by heat generated from the light source located within the lighting unit. Therefore, it is required to cool down the vicinity of the light source, or to secure a path for discharging the heat in the vicinity of the light source so as to hold a luminance of the liquid crystal display device constant during operation of the device, and to prevent occurrence of negative effects on the lifetime of the light source.
However, in the liquid crystal display device using the lighting unit of the conventional edge light type, since the light source is covered with the reflector, the housing, the rear cover and the like, there is a problem that the temperature in the vicinity of the light source becomes high by heat generated from the light source during operation of the device. And, if a cooling device is provided in the vicinity of the light source for cooling down the vicinity of the light source, a size of the liquid crystal display device becomes large with an additional volume of the cooling device, so that it becomes difficult to obtain the light and thin image device. Furthermore, since power consumption of the entire image device increases by providing the cooling device, a load on built-in primary or secondary battery increases, thereby causing a problem that securement of sufficient operating time of image device, which is an original object, is inhibited.

Illumination unit and liquid crystal display comprising it

Toshiba Matsushita Display Technology Co., Ltd.


An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a P− type active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the P− type active region has: an N+ type source region; a P type body region; a P+ type back gate contact region; an N type drain offset region; an N+ type drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source side end of the LOCOS film and is shallower than the N type drain offset region.

(1) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing thereof, and more particularly to a MOS transistor that has satisfactory high breakdown voltage characteristics and an on-resistance, and a method for manufacturing thereof.
(2) Description of the Related Art
In recent years, semiconductor devices, in which N channel MOS transistors and P channel MOS transistors are formed in SOI substrates, have been used for various applications. Particularly for semiconductor devices used in drive circuits in a plasma display which are required to achieve compatibility between improvement of breakdown voltage characteristics and reduction of an on-resistance, MOS transistors having an offset structure have been used.
The following describes a conventional MOS transistor having an offset structure with reference to the drawings.
FIG. 1 is a cross-sectional view showing a structure of an N channel MOS transistor described in Japanese Patent Laid-Open Application No. 2001-102586 publication.
The MOS transistor is composed of: a SOI substrate 100; a local-oxidation-of-silicon (LOCOS) film (hereafter referred to as LOCOS film) 105 that is formed on the SOI substrate 100 by a LOCOS method; a source electrode 115 and a drain electrode 121 that are made of metal; a gate electrode 116 that is made of polysilicon; and a gate oxide film 117 that is made of a thin silicon dioxide film. Note that a part of a surface of the SOI substrate 100 between the source electrode 115 and the drain electrode 121, on which the gate oxide film 117 is not formed, is covered with an insulating film (not shown in FIG. 1).
The SOI substrate 100 is made up of: a supporting substrate (silicon substrate) 101; a buried oxide film 102 that is formed on the supporting substrate 101; and an N− type semiconductor layer 103 that is formed on the buried oxide film 102.
In the semiconductor layer 103, there are formed: a P type body region 112 that is implanted with P type impurities of a low concentration; an N type drain buffer region 118 that is implanted with N type impurities of a low concentration; an N type drain well region 122 (L in FIG. 1) that is implanted with N type impurities of a low concentration; and an N+ type drain contact region 120 that is implanted with N type impurities of a high concentration.
In the P type body region 112, an N+ type source region 111 implanted with N type impurities of a high concentration and a P+ type back gate contact region 114 implanted with P type impurities of a high concentration are formed to be exposed to a surface of the semiconductor layer 103, and a P type threshold value (Vt) control diffusion layer (hereafter referred to as P type Vt control diffusion layer) 113 implanted with P type impurities of a low concentration is formed to surround the N+ type source region 111 and the P+ type back gate contact region 114. Here, the P type body region 112 is electrically connected to the N+ type source region 111 by the source electrode 115, and the P+ type back gate contact region 114 improves an electric connection status in the N+ type source region 111 and the P type body region 112.
The N type drain buffer region 118, whose end at a source side reaches below the gate electrode 116, has a diffusion region that is overlapped on the P type body region 112. On the other hand, the N type drain well region 122 does not have such a diffusion region overlapped on the P type body region 112. Furthermore, the N type drain buffer region 118 is shallower than the P type body region 112 and the N type drain well region 122, and has a diffusion region that is in contact with the semiconductor layer 103 between the P type body region 112 and the N type drain well region 122.
The LOCOS film 105 is formed on a region on the surface of the semiconductor layer 103 between the N+ type source region 111 and the N+ type drain contact region 120, and the region is near the N+ type drain contact region 120. On the other hand, the gate oxide film 117 is formed on a region on the above surface, but the region is near the N+ type source region 111. The gate electrode 116 is formed on the gate oxide film 117 and a part of the LOCOS film 105. Here, in order to reduce electric field concentration in a neighborhood of the N+ type source region 111, the gate electrode 116 is formed over the LOCOS film 105 and the gate oxide film 117, which serves as a kind of field plate.
In the MOS transistor having the above structure, the diffusion region where the P type body region 112 is overlapped with the N type drain buffer region 118 has a concentration gradient such that an N type impurity concentration is varied in a transverse direction from a source side to a drain side. Therefore, when a positive high voltage is applied to the drain electrode, an electric field concentration in the transverse direction between a drain and a source is reduced, so that a high drain-to-source breakdown voltage can be realized.
Meanwhile, in the conventional MOS transistor, when a high drain-to-source breakdown voltage is to be realized, it is necessary to lower the impurity concentration in the N type drain buffer region 118 in order not to restrain an extension of a depletion layer growing from a surface of a PN junction between the P type body region 112 and the N type drain buffer region 118. However, when the impurity concentration in the N type drain buffer region 118 is lowered, resistance in the N type drain buffer region 118 is increased especially in a part ranging from the PN junction surface between the P type body region 112 and the N type drain buffer region 118 to the N type drain well region 122 (L in FIG. 1), resulting in a significant increase of an on-resistance. Therefore, the conventional MOS transistor fails to achieve compatibility between increase of the drain-to-source breakdown voltage and reduction of the on-resistance.
In order to address the above problem, as methods to reduce the on-resistance in the MOS transistor, there is a method by which a deep drain well region is formed in the drain side region adjoining the body region. FIG. 2 is a cross-sectional view showing a structure of a MOS transistor applied with the above method. Note that dashed lines in FIG. 2 show a potential distribution in the MOS transistor when the gate electrode and the source electrode are set to 0 V, and a positive high voltage is applied to the drain electrode.
The MOS transistor shown in FIG. 2 differs from the MOS transistor shown in FIG. 1 in that there is not an N type impurity region of a shallow diffusion depth between the N+ type source region 111 and the N+ type drain contact region 120 (L in FIG. 2). In the MOS transistor shown in FIG. 2, during so-called turning-on when the source electrode is set to 0 V and positive voltages are applied to the gate electrode and the drain electrode, electrons having flowed through a channel from the source pass through a deep N type drain well region 119, so that an on-resistance is significantly reduced.
However, in the MOS transistor shown in FIG. 2, since a P type impurity concentration in the P type body region 112 is relatively low, when the source electrode and the source electrode are set to 0 V and a positive voltage is applied to the drain electrode, a depletion layer significantly extends from a boundary between the P type body region 112 and the N type drain well region 119 towards a side of the P type body region 112. Furthermore, since the gate electrode is set to 0 V, potentials are skewed towards a side of the gate electrode 116. Therefore, in the N type drain well region 119 immediately under the gate oxide film 117, the potentials are distributed in a direction perpendicular to a surface of a PN junction between the P type body region 112 and the N type drain well region 119, and the potentials are concentrated in a region including the source side end of the LOCOS film 105 (A in FIG. 2), resulting in an extreme increase of an electric field. Thus, the MOS transistor shown in FIG. 2 fails to ensure a high breakdown voltage. That is, compatibility between increase of the drain-to-source breakdown voltage and reduction of the on-resistance is not able to be achieved.
Furthermore, as other methods to increase the drain-to-source breakdown voltage in the MOS transistor, there is a method by which a distance in the transverse direction between the N+ type source region and the N+ type drain contact region is lengthened. However, this results in just enlargement of device dimensions, which causes a new problem of enlargement of chip dimensions.

Semiconductor device and method for manufacturing the same

Matsushita Electric Industrial Co., Ltd.


Separating a source in a stereo signal having a left channel and a right channel includes transforming the signal into a short-time transform domain; computing a short-time similarity measure between the left channel and the right channel; classifying portions of the signals having similar panning coefficients according to the short-time similarity measure; segregating a selected one of the classified portions of the signals corresponding to the source; and reconstructing the source from the selected portions of the signals.

Networked lighting control has become increasingly popular due to the variety of illumination conditions that can be created. Color Kinetics Incorporated offers a full line of networked lighting systems as well as controllers and light-show authoring tools. Control signals for lighting systems are generally generated and communicated through a network to a plurality of lighting systems. Several lighting systems may be arranged in a lighting network and information pertaining to each lighting device may be communicated to through the network. Each lighting device or system may have a unique identifier or address such that it only reads and react to information directed at its particular address.
There are several methods used for generating networked lighting control signals. A control-signal generating tool can offer a graphical user interface where lighting shows and sequences can be authored. The user can set up series of addressed lighting systems and then create a lighting control signal that is directed to the individually addressed lighting systems. Such an authoring system can be used to generate coordinated effects between lighting systems or within groups of lighting systems. One particularly popular lighting effect that would be difficult to program without an authoring system is chasing a rainbow of colors down a corridor.
To produce a coordinated lighting effect a user must conventionally have knowledge of where the lighting systems reside as well as knowing the particular addresses each of the lighting systems. It remains difficult to program lighting effects that are designed to move through an area other than in a line or within a group of lighting systems. It would be useful to provide a system that allowed a user to generate and communicate lighting control signals based on the desired effect in an area.

Systems and methods of generating control signals


The lower surface of a valve spring retainer is engaged on a valve spring in a valve operating mechanism of an internal combustion engine. The valve spring retainer is subjected to T6 treatment under JIS (Japanese Industrial Standard), and machined as finishing. The lower surface of the valve spring retainer is not machined, and remains as subjected to T6 treatment, thereby improving fatigue strength and wear resistance.

The present invention relates to an Al alloy valve spring retainer which is used in a valve operating mechanism of an internal combustion engine.
FIG. 2 illustrates one example of a valve operating mechanism of an internal combustion engine, in which to the upper end of a poppet valve 1 a valve spring retainer 3 is attached via a pair of semi-cylindrical cotters 2. Between a cylinder head (not shown) and the lower surface of a spring contacting flange 3a of the valve spring retainer 3, a valve spring 4 is provided, and the poppet valve 1 is usually energized upwards via the valve spring retainer 3. The numeral 5 denotes a rocker arm which contacts the upper end of the poppet valve 1 and which is shaken vertically by a rotary cam (not shown), thereby driving the valve in a vertical direction.
The valve spring retainer 3 used in such a valve operating mechanism is made of Al alloy to decrease inertia mass of the valve operating mechanism instead of steel which is usually used.
The Al alloy valve spring retainer is usually made by cold forging such as T6 treatment under JIS (Japanese Industrial Standard) and machining. T6 treatment under JIS means the steps of heating at about 500.degree. C. for several hours, cooling rapidly by water quenching and heating for several hours between 100 and 200.degree. C.
The valve spring retainer 3 is subjected to large repeating loads by the valve spring 4. Therefore, the flange 3a which is engaged with the valve spring 4 requires high fatigue strength and wear resistance. Such Al alloy spring retainer is softer than steel one, and mechanical strength is improved by T6 treatment to increase fatigue strength and wear resistance. However, machining such as lathes is made as finish on the whole inner and outer circumferential surface, so that fatigue strength and wear resistance are decreased.
This is because machining made after T6 treatment increases surface roughness and involving notch effect is likely to cause stress concentration to decrease fatigue strength. It is found that decrease in wear resistance is because a hardened surface layer formed by T6 treatment such as oxidizing coating layer is cut off and lost by machining.

Aluminum alloy valve spring retainer and method of making same


A dual mode autostereoscopic lens sheet. The lens sheet has at least one refractive region and at least one non-refractive region. When the lens sheet is held in intimate juxtaposition with a display, stereoscopic content may be viewed in the refractive region while planar content may be simultaneously viewed in the non-refractive region. In a preferred embodiment, the non-refractive region forms a vertical column on one end of the lens sheet and the refractive region forms a vertical column on the other end of the lens sheet. Advantageously, the refractive region defines a picture area having an aspect ratio of approximately 1.3:1.

The technology of electronic autostereoscopic displays, usually involving flat panels, has advanced to the point where it is now viable for many applications. Dedicated autostereoscopic displays are available, but there are computer users who want the ability to move between planar applications, such as word processing, and stereoscopic visualization applications, and still obtain a clear image for both types of applications. There are some technologies which allow for dual mode monitors that function in either an autostereoscopic mode or planar mode, but not in both modes simultaneously.
For displays using a lenticular (or raster barrier) selection device, a significant problem is that the refractive properties of the lens sheet fragments distorts small point type and fine-resolution image elements such as desktop icons, task bars, and drop-down menus. Thus, with the lens sheet in place, the autostereoscopic monitor can typically not be used to simultaneously view both stereoscopic information and fine type or icons. Many approaches have been previously considered to address this problem. For example, a display utilizing an overlay such as a lenticular screen has been described in co-pending U.S. patent application Ser. No. 09/943,890, entitled AUTOSTEREOSCOPIC LENTICULAR SCREEN. With the lenticular ridges facing inward towards the flat panel surface, a chamber is created between the flat panel surface and the lenticular ridges to hold a liquid that is emptied to provide 3-D viewing and filled to defeat the refraction properties of the screen.
U.S. Pat. No. 5,500,765, entitled CONVERTIBLE 2D/3D AUTOSTERESCOPIC DISPLAY discloses a display having a lenticular overlay in close contact with the flat panel front surface, but with the ridges facing outward. To defeat the lenticular "refractive" characteristics, a mating inverse lenticular screen is placed atop the lenticular screen in proper alignment so that the overlaid screen will negate the refraction of the original.
Another approach is to fabricate a removable lenticular screen that is held firmly in precision alignment when placed in intimate juxtaposition with the flat panel display.
Another approach, described in press releases by Sharp and DTI technologies, involves the use of a liquid crystal modulator in proper proximity to the imaging display surface. The modulator is made up of rulings that can be turned on and off to transition between a raster barrier and a clear cover sheet. When in the raster barrier mode, a stereoscopic image can be observed. This is well-known art and therefore not described herein. However, it is of interest to note that from an optical standpoint, lens sheets and raster barriers are more or less interchangeable, and information prepared for one can be displayed using the other. Therefore, although the inventive technique disclosed herein is described with reference to lenticular sheets, it also applies in principal to the raster barrier selection device technique.
Whatever the merits of these two-state approaches (stereo and planar), they do not solve the essential problem of enabling the user to clearly see some areas of the display screen autostereoscopically and some areas in the planar mode. In this disclosure, a means for simulataneously displaying both stereoscopic and planar information in selected areas of the display is revealed.

Autostereoscopic lens sheet with planar areas


Apparatus and method for clamping a flanged joint, comprising a clamp having first and second clamp devices applied to circumferentially separate portions of the flanges, each device having a foot to engage an outer face of a flange, and a force driver adapted to press the flanges together from opposite sides of the flanged connection. The clamping devices are circumferentially spaced apart on the flange, and a foot portion is adapted to engage the outer face of each flange circumferentially between the bolts, to allow transmission of forces to the flanges without applying forces to the bolts, or the nuts or other fixings attached thereto. The clamping force is applied not through the existing bolts passing through the flanges, but through the clamping device of the invention.

Flanged connections are well known. Flanged connections are used to connect lengths of pipe. Typically a flange extends radially (i.e. perpendicularly away from axis of the pipe) at each end of each pipe section to be connected, so that the flanges on each end are parallel to one another. Normally each flange has apertures extending axially (i.e. parallel to the axis of the pipe) through the flanges to permit fixings such as bolts or threaded studs to be inserted through the flanges so that the flanges can be compressed together to seal the two ends of the pipe to one another. Typically, a resilient gasket seal is compressed between the opposing faces of the flanges, and can often be held in an annular groove in one or both of the faces of the flange.
This is a satisfactory method of connecting pipe ends, and many miles of pipelines and flow lines from many industries are connected in this manner. Pipelines and their connections are of course subject to degradation over time and flanged pipeline connections such as are described above typically suffer from bolt failure before the flanges and the gaskets reach the end of their usable lives. Therefore, remedial work on flanged pipeline connections frequently involves changing out existing bolts that have corroded. Often, removal of a bolt from a flanged pipe connection requires interruption of the flow through the pipe, which can have significant adverse economic consequences in the case of oil pipelines and other high value fluid transfer pipelines. Therefore, the industry has adopted various "hot bolting" methods where individual bolts or threaded studs are removed and replaced one at a time, while the pipeline remains an active fluid conduit with fluids passing through the connection being repaired. However, this can sometimes have significant challenges, as some bolts can easily be extracted from the flanged connection and replaced relatively quickly, whereas other bolts have corroded too much to be unscrewed, and need to be split or cut from the flanged connection. Removing excessively corroded bolts increases the time involved, and also risks disturbing the connection through the high forces applied to the bolts in order to try to free them.

Equalizer Flange Integrity Systems Limited


An image scanning apparatus that forms an optical image of a document with an image-forming lens onto an image sensor. In order to prevent deterioration in image-forming performance, the image scanning apparatus includes a restricting member for restricting displacement of the image-forming lens in the direction of the optical axis. The restricting member is provided on a supporting member for supporting the image-forming lens and the image sensor.

1. Field of the Invention
The present invention relates to an image scanning apparatus used for copying machines, facsimiles, and image scanners.
2. Description of the Related Art
In general, image scanning apparatuses used for copying machines, facsimiles, and image scanners include a scanning optical system, a lens unit, and an image sensor. The scanning optical system includes an exposing lamp and a plurality of mirrors. The lens unit includes a lens barrel containing a plurality of lenses. The scanning optical system scans the surface of a document to obtain reflected light. The reflected light is made to form an optical image on the image sensor by the lens unit. The optical image is converted into an electric signal.
Recent improvements in the quality of the scanned image and in the scanning speed necessitate an increase in the amount of light of the exposing lamp and in the driving speed of the image sensor. Due to the heat emitted from the exposing lamp and the image sensor, the temperature inside the image scanning apparatus rises significantly.
The relative position of the document and the lens unit and the relative position of the lens unit and the image sensor are adjusted so as to satisfy a predetermined optical performance when the image scanning apparatus is constructed. However, when the temperature inside the apparatus rises, the relative positions change due to thermal expansion of the lens barrel and a supporting member for supporting the lens unit and the image sensor, and consequently the optical performance deteriorates.
To solve such a problem, Japanese Patent Laid-Open No. 9-049957 discloses an image scanning apparatus in which the focal length of the lens unit at room temperature is longer (or shorter) than that when the temperature is higher than room temperature; and the thermal expansion coefficient of the lens barrel is larger (or smaller) than that of the supporting member for supporting the lens unit and the image sensor.
That is to say, in the above image scanning apparatus, the thermal expansion coefficients of the lens barrel and the supporting member are determined in accordance with the change in the focal length due to the temperature rise. However, if the amount of change in the focal length cannot be compensated by thermal expansion of the members, optical performance deteriorates. Factors such as strength and cost can limit the materials used for the members. In some cases, deterioration in optical performance due to temperature rise cannot be compensated.


A transmission circuit operates with high efficiency and low distortion. An amplitude and phase extraction section extracts amplitude data and phase data from input data. A phase modulation section phase-modulates the phase data to output a resultant signal as a phase-modulated signal. An amplifier section amplifies the phase-modulated signal to output a resultant signal as a transmission signal. An amplitude control section supplies, to the amplifier section, a voltage controlled in accordance with an AC component represented by a fluctuation component of the amplitude data and a DC component represented by an average value level of the fluctuation component of the amplitude data.

1. Field of the Invention
The present invention relates to a transmission circuit used for communication devices such as mobile phones and wireless LAN devices, and particularly to a transmission circuit, which operates with high efficiency and low distortion, and a communication device using the transmission circuit.
2. Description of the Background Art
Communication devices such as mobile phones and wireless
LAN devices are required to secure linearity of a transmission signal over a wide output level range and also to operate with low power consumption. For such a communication device, a transmission circuit which operates with high efficiency and low distortion is used. Hereinafter, conventional transmission circuits will be described.
One of the conventional transmission circuits is, for example, a transmission circuit which uses a modulation method such as a quadrature modulation method to generate a transmission signal (hereinafter, referred to as a quadrature modulation circuit). Since the quadrature modulation circuit is well known, the description thereof will be omitted. A conventional transmission circuit capable of outputting, more efficiently than the quadrature modulation circuit, a transmission signal having high linearity is, for example, a transmission circuit disclosed in FIG. 9 of Japanese Laid-Open Patent Publication No. 2004-266351 (hereinafter, referred to as Patent Document 1). FIG. 7 is a block diagram showing an exemplary configuration of a conventional transmission circuit 90 disclosed in Patent Document 1. In FIG. 7, the conventional transmission circuit 90 comprises an amplitude and phase extraction section 91, phase modulation section 92, amplifier section 93, output terminal 94 and an amplitude control section 95.
The amplitude and phase extraction section 91 extracts amplitude data and phase data from input data. The amplitude data is inputted to the amplitude control section 95. The amplitude control section 95 supplies a voltage to the amplifier section 93 in accordance with the amplitude data. The phase data is inputted to the phase modulation section 92. The phase modulation section 92 performs phase modulation on the inputted phase data to output a resultant signal as a phase-modulated signal. The phase-modulated signal is inputted to the amplifier section 93. The amplifier section 93 amplifies the phase-modulated signal in accordance with the voltage supplied from the amplitude control section 95. The signal amplified by the amplifier section 93 is outputted from the output terminal 94 as a transmission signal. The transmission circuit 90 which operates in the above manner is called a polar modulation circuit.
The conventional transmission circuit 90 has a problem that in the case where an output level of the transmission signal is varied over a wide range, the linearity of the transmission signal is not always secured. For example, in the case where the conventional transmission circuit 90 is applied to the UMTS specifications, the transmission circuit 90 is required to vary the output level over a range of 75 dB which is wider than the case where the transmission circuit is applied to GSM/EDGE specifications. In such a case, the amplitude control section 95 of the transmission circuit 90 is required to greatly vary the voltage to be supplied to the amplifier section 93. However, since a DC bias voltage, which causes internal elements of the amplitude control section 95 to operate, cannot be freely set in the transmission circuit 90, it is difficult to secure the linearity of the amplitude control section 95 when the DC bias voltage is near VCC or GND potential. For this reason, the conventional transmission circuit 90 cannot always secure the linearity of the transmission signal in the case where the output level of the transmission signal is varied over a wide range.

Transmission circuit and communication device


An aerobic treatment process is operated to reduce overall oxygen requirements, to maintain general pH balance and to produce a low-coliform solids effluent. From the system's clarifier a slurry of concentrated solids is moved to a premix basin, where the slurry is vigorously aerated for a sufficient time to raise microbial activity and dissolved oxygen content. The aerated, microbially active sludge is then moved to a gravity thickener basin, in which solids are allowed to settle to the bottom without aeration, to establish a quiescent state in the settled sludge and also an anoxic stage. This causes the sludge to be denitrified by microbial action, raising and stabilizing the pH of the sludge. Separated supernatant liquid is decanted and removed from the gravity thickener. The sludge is moved into an aerobic digester, where the sludge is aerated and nitrification occurs but using less aeration than normally required in a digester, due to the effect of anoxic/aerobic phases. A portion of the slurry in the aerobic digester basin is recycled back to the premix basin. Another important aspect is the use of two digesters, only one in loop with the premix and thickener at any one time, with each digester being taken out of the loop and isolated when a solids content of about 25,000 to 35,000 mg/L (21/2% to 3.5%) is achieved in that digester. The isolation results in a significantly lowered coliform content in the effluent sludge.

This invention is concerned with sewage treatment involving aerobic digesters, and specifically the invention relates to a method of operating an activated sludge process in such a way as to minimize capital requirements, minimize aeration requirements and minimize coliform count in solids effluent.
In sewage treatment plants, aerobic digestion as a means of stabilizing sludge has been common practice for decades. During the process of digestion, nitrification of the sludge tends to occur when sufficient air is provided, normally via submerged aeration bubblers. However, if nitrification is allowed to continue unchecked, this will lead to a pH drop in the system. A low pH (e.g. about 5) will retard microbial activity, and efficiency of the process will be lost. To recover this lost alkalinity, plant operators have in the past added alkaline agents, specifically lime, to the digester. Also, it is known that on the liquid side of the system, e.g. in aeration basins upstream of clarifiers, aeration air may be shut off for a period of time to enable denitrification of the sludge to occur. This can be used to recover up to about 50% of the lost alkalinity. The abrupt shutoff of air to the microbes, which have become very active during aeration, causes the microbes to break down nitrates in the sludge, utilizing the oxygen from the nitrates and releasing nitrogen gas. Acidity in the solution is reduced in this way, and on the liquid side it has been common to cycle the air on and off to maintain pH in a desired range.
It has also been suggested to incorporate an anoxic operating period into the aerobic digestion cycle. See, for example:
Matzuda, A., T. Ide, and S. Fujii (1988), "Behavior of nitrogen and phosphorus during batch aerobic digestion of waste activated sludge--continuous aeration and intermittent aeration by control of DO," Water Res., vol. 22, 1495-1501;
Peddie, C. C., D. S. Mavinic, and C. J. Jenkins (1990), "Use of ORP for Monitoring and Control of Aerobic Sludge Digestion," Journal of Environmental Engineering, vol. 116, 461-471;
Hao, O. J. and M. H. Kim (1990), "Continuous Pre-Anoxic and Aerobic Digestion of Waste Activated Sludge," Journal of Environmental Engineering, vol. 116, 863-879; and
Hao, O. J., M. H. Kim, and I. A. Al-Ghusain (1991), "Alternating aerobic and anoxic digestion of waste activated sludge," Journal of Chemical Technology and Biotechnology, vol. 52, 457-472. As pointed out in that literature, aerobic/anoxic operation has the advantages of recovering lost alkalinity and it can reduce overall oxygen requirements in the aerobic digestion process.
A recent paper by Glen T. Daigger presented at the 70.sup.th Annual Conference & Exposition of the Water Environment Federation in Chicago, Ill. in October 1997 reviews aerobic/anoxic operation as an improvement to conventional aerobic digestion processes. As reviewed in that paper, one problem in operating conventional aerobic digestion systems is the depletion of alkalinity during aeration, caused by nitrification of released ammonia-nitrogen, which results in a decrease in pH, reducing biological reaction rates. Daigger points out that in the absence of nitrification, the overall digester reaction is as follows: EQU C.sub.5 H.sub.7 O.sub.2 N+5 O.sub.2 .fwdarw.4 CO.sub.2 +NH.sub.4 HCO.sub.3( 1)
where C.sub.5 H.sub.7 O.sub.2 N represents the typical composition of biomass. Alkalinity is produced in the form of ammonium bicarbonate, which at neutral pH will ionize to produce ammonium ions and bicarbonate ions.
With nitrification which tends to occur in the aerobic digester, the ammonia-nitrogen is converted to nitrate-nitrogen: EQU NH.sub.4.sup.+ +2 O.sub.2 .fwdarw.NO.sub.3.sup.- +2 H.sup.+ +H.sub.2 O(2)
Thus, two moles of acidity are produced, because one mole of ammonia is consumed and one mole of nitric acid is produced. Thus, the overall reaction (combining the two above equations) becomes: EQU C.sub.5 H.sub.7 O.sub.2 N+7 O.sub.2 .fwdarw.5 CO.sub.2 +3 H.sub.2 O+HNO.sub.3 (3)
This shows that process oxygen requirements are increased with the occurrence of nitrification, as indicated by an increase from five moles of oxygen per mole of biomass to seven moles of oxygen per mole of biomass, comparing the first and third equations above. The acidity produced by the nitric acid will consume some of the alkalinity produced in the first equation.
As further explained by Daigger, if an anoxic phase is included in the aerobic digestion cycle, the reaction is as follows: EQU C.sub.5 H.sub.7 O.sub.2 N+4 NO.sub.3.sup.31 +H.sub.2 O.fwdarw.NH.sub.4.sup.+ +5 HCO.sub.3.sup.- +2 N.sub.2 (4)
No free oxygen is consumed during this reaction, and alkalinity is produced, which can then be used in nitrifying the ammonia-nitrogen released from the biomass destruction. If the aerobic and anoxic periods can be controlled such that all of the nitrate-nitrogen formed during the aerobic phase is reduced in the anoxic phase, then the overall reaction becomes: EQU C.sub.5 H.sub.7 O.sub.2 N+5.75 O.sub.2 .fwdarw.5 CO.sub.2 +2 N.sub.2 +4 H.sub.2 O (5)
Equations (3) and (5) above demonstrate that the aerobic/anoxic stages introduced in aerobic digestion systems can reduce process oxygen requirements. As pointed out in the Daigger paper (the source of the above equations), equations (3) and (5) show reduction from seven moles of O.sub.2 per mole of biomass to 5.75 moles of O.sub.2 per mole of biomass, a 17% reduction. Moreover, alkalinity is not consumed in the overall reaction. Alkalinity from the destruction of biomass (equation (1)) and resulting from denitrification is that required to provide the alkalinity needed for nitrification (equation (2)). Thus, the pH of the digester, if a controlled aerobic/anoxic process is maintained, should remain near neutral.
The Daigger paper, and tests supporting the paper, suggested establishing the anoxic stage in the digester itself, by cycling aeration on and off (e.g. off for 6 to 8 hours each day).
Prior conventional practice in activated sludge digestion was to draw settled sludge from a main activated sludge process or from clarifier basin(s) and deliver this sludge directly to the digester(s), although it has been common to recycle some of the solids from the clarifier to the aeration basin to maintain a desired solids content in the aeration basin. In more recent years aerobic digester systems have been modified to bring a thicker sludge to the digester, in order to meet requirements for longer retention times without increasing tank volumes. Gravity thickeners, belt thickeners, drum thickeners, centrifuges and even recycle loops have been used, with the purpose of reducing tankage capital costs to achieve target retention times. Enviroquip's prior art Pre-thickened Aerobic Digestion (PAD) system is an example of such a system which pre-thickens sludge prior to aerobic digestion, reducing capital costs in tankage requirements. That system incorporates a premix/thickener/digester recycle loop to progressively thicken wasted sludge.
Thicker sludges delivered to the digester have created several problems, including problems of oxygen transfer, mixing and mechanical equipment. Moreover, pre-thickened systems have not been operated in a manner to achieve the benefits of the invention described herein; nor have aerobic/anoxic cycling been applied in the efficient way which forms a part of the process of the invention.
The recent enactment of stricter EPA sludge quality laws, and regulations defining compliance with sludge standards such as Class A sludge or Class B sludge, have driven efforts to improve the aerobic digestion process.
It is among the objects of this invention to improve the aerobic digestion process with a system which reduces tankage capital costs, maintains pH balance without addition of alkaline agents, reduces overall aeration requirements by as much as 17%, and enables consistent compliance with Class B sludge regulations.


An interlayer insulating layer is formed to cover a fuse layer. A concave portion is provided on the surface of interlayer insulating layer located directly above fuse layer. A nitride layer as a passivation layer extends on the sidewalls of concave portion. In this way, a semiconductor device is obtained, the device having an improved moisture resistance, and in which a fuse can be easily blown by laser and a design rule of the region adjacent to the fuse can be improved.

1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device with a fuse connected to a redundant circuit and manufacturing method thereof.
2. Description of the Background Art
Redundant circuit provided for repairing a semiconductor device with some defect has been known conventionally. Fuse is generally formed with the redundant circuit, then a defective circuit is replaced with a redundant circuit by appropriately blowing the fuse.
A general structure of one example of a DRAM (Dynamic Random Access Memory) provided with a redundant circuit is shown in FIG. 13. Referring to FIG. 13, in a memory cell array 20, a plurality of word lines WL are extended from respective row decoders 21 through word drivers 22 in a row direction. A plurality of bit lines BL are also extended from respective column decoders 23 in a column direction. These word lines WL and bit lines BL are disposed such that they cross each other. Memory cells MC are provided at the crossings.
At the outside of word lines WL mentioned above, a spare word line SWL is extended from a spare decoder 24 through a spare word driver 25 in the row direction. At the crossings of the spare word line SWL and each of the bit lines BL, spare memory cells SMC are provided.
These spare word line SWL, spare decoder 24, and spare word driver 25 form a so called redundant circuit. A defective address comparison circuit 26 is connected to spare decoder 24, and fuses are formed in defective address comparison circuit 26. As shown in FIG. 13, row address is input to defective address comparison circuit 26.
FIG. 14 shows a fuse portion and its adjacent region as well as a bonding pad portion and its adjacent region in DRAM having above described structure. With reference to FIG. 14, a fuse layer 1 is formed in an interlayer insulating layer 2 provided on a substrate (not shown). Metal interconnection layers 3, 3 and a bonding pad layer 3a are formed on the surface of interlayer insulating layer 2. Bonding pad layer 3a functions as an external connection electrode in order to electrically connect some external device with circuit elements formed on the substrate. A nitride layer functioning as a passivation layer is provided to cover metal interconnection layers 3 and bonding pad layer 3a. Nitride layer 4 has an opening 4a placed directly above fuse layer 1, and has an opening 4b placed directly on boding pad layer 3a.
Next, the way of blowing fuse layer 1 and the timing of performing the step will be described. Conventionally, a test for repairing a semiconductor device (chip) was conducted in the line before completing a wafer process. The chip was repaired by blowing the fuse layer 1 corresponding to a defective part by laser (Laser Trimming: LT). After that, a passivation layer was formed and a wafer process was completed. Next, a rough test (Water Test: WT) of the wafer was performed, roughly screening the number of chips to be tested. Then a formal test (Final Test: FT) was performed to prepare for delivery.
However, nowadays the LT step and WT step are performed simultaneously to shorten the test period. In this case, the passivation layer on fuse layer 1 is selectively removed, and a test is executed for repairing the chip out of the line. That is, the test for repair is carried out on such a device as shown in FIG. 14. Next, fuse layer 1 corresponding to a defective portion is blown off by laser.
In FIG. 14, laser is directed following the arrow 5, blowing off prescribed fuse layer 1. When fuse is blown by laser, the dimension of the thickness d of interlayer insulating layer 2 located on fuse layer 1 becomes an important factor. That is, blowing fuse by laser will be difficult if the thickness d is large. To ease the difficulty, width W of the fuse and its peripheral area should be increased, which is disadvantageous for higher integration of the device.
To avoid the above problem, a method as shown in FIG. 15 has been proposed. That is, the thickness d of interlayer insulating layer 2 located on fuse layer 1 is reduced by providing a concave portion 2a on the surface of interlayer insulating layer 2 positioned directly on fuse layer 1. Fuse is then easily blown off by laser. After thus blowing the fuse, a further rough test is given for carrying out a rough screening before the FT step described above.
A following problem still exist in the improved embodiment shown in FIG. 15. An interface 6 between nitride layer 4 and interlayer insulating layer 2 is exposed due to the selective removal of nitride layer 4 located directly above fuse layer 1 as illustrated in FIG. 15. Further, metal interconnection layer 3 formed of material including Al, for example, is provided on the region extending from interface 6. Therefore, water could enter interface 6, possibly causing corrosion of metal interconnection layer 3. As a result, device reliability may be degraded. This is also true in the device shown in FIG. 14.
Above problem associated with the moisture resistance is also experienced at the area adjacent to boding pad layer 3a when passivation layer is provided as a stacked structure of oxide layer and nitride layer. More specifically, if passivation layer is formed as a double layer structure of nitride layer on oxide layer, an interface between oxide layer and nitride layer could be exposed on boding pad layer 3a. In this case, the possibility of water entering the interface between oxide layer and nitride layer becomes higher, lowering the device reliability.

Method of manufacturing semiconductor device having a fuse