A semiconductor memory apparatus able to operate at a low voltage and thus preventing an increase of the operating current during charging and discharging. NMOS transistors are connected to the power supply line and bit lines, and the gates thereof are connected to a precharge signal supply line. PMOS transistors are connected to the connection points of the bit lines and sense amplifiers and the supply line of the power supply voltage. The gates thereof are connected to the precharge signal supply line through inverters. Transfer gates are connected to the connection points of the bit lines and the NMOS transistors. The gates thereof are connected to the column switch signal supply line. Only one bit line of the selected column is precharged to the power supply voltage level. The other bit lines are held at the predetermined low potential.

1. Field of the Invention
The present invention relates to a semiconductor memory apparatus for precharging bit lines at a predetermined electric potential to read data therefrom.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an example of the configuration of a static random access memory (SRAM). The drawing shows an example of a dual port SRAM having a single bit line to which precharging is performed. No writing circuit is shown in this drawing.
In FIG. 1, CELL(1,1) to CELL(m,n) represent SRAM cells arranged in a matrix of m lines and n rows, R.sub.-- B1 and R.sub.-- B2 to R.sub.--B.sub.n represent read bit lines, R.sub.-- W1 and R.sub.-- WB2 to R.sub.-- W.sub.m represent read word lines, W.sub.-- W1 and W.sub.-- W2 to W.sub.-- W.sub.m represent write word lines, NT.sub.PR1 and NT.sub.PR2 to NT.sub.PRn represent n-channel (N) metal oxide film semiconductor (NMOS) transistors for precharging the bit lines, NTSA.sub.PR1 represents a NMOS transistor for precharging an input node of a sense amplifier, NT.sub.SW1 and NT.sub.SW2 to NT.sub.SWn represent NMOS transistors serving as column switches, PU represents a precharge signal supply line, R.sub.-- C1 and R.sub.-- C2 to R.sub.-- Cn represent column switch supply lines, and SA represents a sense amplifier.
In FIG. 1, the SRAM cells CELL (1,1) to CELL (m,n) are TFT load type memory cells. Each, for example, the SRAM CELL (1,1), comprises a flip-flop including a pair of complementary (C) MOS inverters INV.sub.CL1 and INV.sub.CL2, inputs and outputs thereof being connected a cross-wise.
The memory nodes, which are outputs of the inverters INV.sub.CL1 in the SRAM cells CELL (1,1) to CELL (m,n), are connected to the read bit lines R.sub.-- B1, R.sub.-- B2 to R.sub.-- Bn through the word transistors R.sub.-- WT. The gates of the respective word transistors R.sub.-- WT are connected to the read word lines R.sub.-- W1 and R.sub.-- W2 to R.sub.-- Wm respectively.
The outputs of the respective inverters INV.sub.CL1, and the outputs of the inverters INV.sub.CL2 are connected to write bit lines, not shown, through the word transistors W.sub.-- WT1 and W WT2, respectively. The gates of the word transistors W.sub.-- WT1 and W.sub.-- WT2 are connected to the write word lines W.sub.-- W1 and W.sub.-- W2 to W.sub.-- Wm, respectively.
Specifically, the SRAM cells CELL(1,1) and CELL(2,1) to CELL(m,1) are connected to the bit line R.sub.-- B1 through the respective word transistors R.sub.-- WT, the SRAM cells CELL(1,2) and CELL(2,2) to CELL(m,2) are connected to the bit line R.sub.-- B2 through the respective word transistors R WT, and the SRAM cells CELL(1,n) and CELL(2,n) to CELL(m,n) are connected to the bit line R.sub.-- Bn through the respective word transistors R.sub.-- WT.
Also, the SRAM cells CELL(1,1) and CELL(1,2) to CELL(1,n) are connected to the read word line R.sub.-- W1 and the write word line W.sub.-- W2, the SRAM cells CELL(2,1) and CELL(2,2) to CELL(2,n) are connected the read word line R.sub.-- W2 and the write word line EW2, and the SRAM cells CELL(m,1) and CELL(m,2) to CELL(m,n) are connected to the read word line R.sub.-- Wm and the write word line W.sub.-- Wm.
The drains of the precharging NMOS transistors NT.sub.PR1 and NT.sub.PR2 to NT.sub.PRn are connected to the power supply lines of the power supply voltage vdd, and gates of the NMOS transistors NT.sub.PR1 and NT.sub.PR2 to NT.sub.prn are connected to the common precharge signal supply line PU.
The source of the NMOS transistor NT.sub.PR1 is connected to the bit line R.sub.-- B1, the source of the NMOS transistor NT.sub.PR2 is connected to the bit line R.sub.-- B2, and the source of the NMOS transistor NT.sub.PRn is connected to the bit line R.sub.-- Bn.
The NMOS transistor NT.sub.SW1 used as a column switch is provided between a connection point of the bit line R.sub.-- B1 and the source of the NMOS transistor NT.sub.PR1 and a connection point of the bit line R.sub.-- B1 and the sense amplifier SA. The gate of the NMOS transistor NT.sub.SW1 is connected to the column switch signal supply line R.sub.-- C1.
The NOS transistor NT.sub.SW2 used as a column switch is provided between a connection point of the bit line R.sub.-- B2 and the source of the NOMS transistor NT.sub.PR2 and a connection point of the bit line R.sub.-- B2 and the same amplifier SA. The gate of the NMOS transistor NT.sub.SW2 is connected to the column switch signal supply line R.sub.-- C2.
The NMOS transistor NT.sub.SWn used as a column switch is provided between a connection point of the bit line R.sub.-- Bn and the source of the NMOS transistor NT.sub.PRn, and a connection point of the bit line R.sub.-- Bn and the sense amplifier SA. The gate of the NMOS transistor NT.sub.SWn is connected to the column switch signal supply line R.sub.-- Cn.
The drain of the NMOS transistor NTSA.sub.PR1 for precharging the input node of the sense amplifier SA is connected to the supply line of the power supply voltage Vdd, the source of the NMOS transistor NTSA.sub.PR1 is connected to the node ND.sub.SA, which is a connection point between the bit lines R.sub.-- B1 and R.sub.-- B2 to R.sub.-- Bn and the sense amplifier SA, and the gate of the NMOS transistor NTSA.sub.PR1 is connected to the precharge signal supply line PU.
The sense amplifier SA is comprised of inverters IN.sub.SA1 INV.sub.SA2 and an NMOS transistor NT.sub.ST1.
The inverter INV.sub.SA1 and the inverter INV.sub.SA2 are connected in series, the input of the inverter INV.sub.SA1 is connected to the node ND.sub.SA, which is a connection point between the bit lines R.sub.-- B1 and R.sub.-- B2 to R.sub.-- Bn and the NMOS transistor NTSA.sub.PR1, and to the source of the NMOS transistor NT.sub.SA1. The output of the inverter INV.sub.SA2 functions as the output of the sense amplifier SA, and the output of the inverter INV.sub.SA2 is connected to the gate of the NMOS transistor ST.sub.SA1. The drain of the NMOS transistor NT.sub.SA1 is connected to the supply line of the power supply voltage Vdd.
Next, an explanation will be made of the data read operation of the circuit shown in FIG. 1 with reference to the timing chart in FIG. 2.
First, the read word lines R.sub.-- W1 to R.sub.-- Wn are set to the low level, and the precharge signal supply line PU is set to the high level.
As a result, the precharging NMOS transistors NT.sub.PR1 to NT.sub.PRn are turned on. The respective bit lines R.sub.-- B1 to R.sub.-- Bn are precharged at high level. Note that, an actual precharge level is defined as (Vdd-Vth-.DELTA.Vth). Here, Vth is the threshold voltage of the transistors, and .DELTA.Vth is the change of the threshold due to the substrate bias effect.
Also, since the precharge signal supply line PU is set to high level, the NMOS transistor NTSA.sub.PR1 is turned on, and the connection point between each of the read bit lines R.sub.-- B1 to R.sub.-- Bn and the sense amplifier SA, namely, the input node ND.sub.SA of the sense amplifier SA, is precharged at a high level.
Next, the level of the precharge signal supply line PU is changed from the high level to the low level, and the read word line R.sub.-- Wi selected by the address signal is set to the high level. As a result, the NMOS transistors NT.sub.PR1 to NT.sub.PRn and NTSA.sub.PR1 are turned OFF.
In response to the data stored in the SRAM cells CELL(i,l) to CELL(i,n) which are connected to the read word line R.sub.-- Wi set at a high level, the respective read bit lines R.sub.-- B1 to R.sub.-- Bn are discharged to a low level or are held at a high level.
One of n rows of the column switch signal supply bias R.sub.-- C1 to R.sub.-- Cn is set to the high level in accordance with the column address signal. As a result, one column switch NMOS transistor, whose gate is connected to the column switch signal supply line set to the high level, is turned ON, and the signal passing through the column switch NMOS transistor is input to the inverter INV.sub.SA1 in the sense amplifier SA.
In the above-mentioned apparatus, however, when the power supply voltage Vdd becomes low, the resultant precharge level is lowered, and, as a result, the sense amplifier SA may not amplify the input signal as in normal times.
When the sense amplifier SA is of a type of a sense amplifier in which a gate of an NMOS transistor receives the input signal, for example, a CMOS inverter, the high level input signal applied to the gate must be higher than the threshold voltage Vth of the transistor. That is, to ensure the normal operation of the sense amplifier SA, the following relationship must be satisfied:
(Vdd-Vth-.DELTA.Vth.gtoreq.Vth)
.thrfore.(Vdd.gtoreq.2Vth+.DELTA.Vth)
This, however, means that the sense amplifier SA cannot operate normally at the low power supply voltage.
As shown in FIG. 3, there has been proposed a circuit in which the precharging of the bit lines is carried out by p-channel MOS (PMOS) transistors PT.sub.PR1 to PT.sub.PRn and PTSA.sub.PR1, instead of the NMOS transistors. In the circuit, the column switches are comprised of transfer gates TFG.sub.SW1 to TFG.sub.SWn, which are comprised of NMOS transistors and PMOS transistors, with their source and their drains mutually connected, instead of the NMOS transistors. The respective gates of the NMOS transistors N.sub.1 to N.sub.n in the transfer gates TFG.sub.SW1 to TFG.sub.SWn are directly connected to the column switch signal supply lines R.sub.-- C1 to R.sub.-- Cn. The gates of the PMOS transistors P.sub.1 to P.sub.n in the transfer gates TFG.sub.SW1 to TFG.sub.SWn are connected to the column switch supply lines R.sub.-- C1 to R.sub.-- Cn through the inverters INV.sub.SW1 to INV.sub.SWn.
In this circuit, the power supply voltage by which the high level signal to the sense amplifier exceeds the threshold voltage Vth is Vdd.gtoreq.Vth. Thus, in this circuit, as compared with NMOS transistors, the sense amplifier can operate at a low level power supply voltage.
But in this case, since the bit line amplitude is increased from (Vdd-Vth-.DELTA.Vth) to Vdd, it suffers from the disadvantages of the increase of the operating current of the bit lines by charging and discharging.

Dual port memory apparatus operating a low voltage to maintain low operating current during charging and discharging


A position detecting circuit provided in an imaging apparatus having an optical system that images a subject image, an imaging element that performs photoelectric conversion of the subject image, and a release switch capable of setting states of two stages includes: a plurality of magnetic field change detecting elements that detect the intensity of a magnetic field formed by a magnetic field generating body attached to either the optical system or the imaging element and that are provided so as to be separated from each other; a position detecting portion that detects the position of the magnetic field generating body on the basis of outputs from the plurality of magnetic field change detecting elements; and a standby portion that stops a function of at least one of the position detecting portion and the plurality of magnetic field change detecting elements until a first stage of the release switch is set.

1. Field of the Invention
The present invention relates to a position detecting circuit that detects the position of a magnetic field generating body, which is mounted in the same member together with an optical system or an imaging element, and an imaging apparatus.
Priority is claimed on Japanese Patent Application No. 2007-110310, filed Apr. 19, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
There is known a shake correction mechanism that suppresses image blur on an imaged surface of an imaging element, which is caused by hand shake or the like, by shifting an optical system or the imaging element in the direction perpendicular to an optical axis of the optical system according to the amount of hand shake occurring during photographing using an imaging apparatus. In addition, a position detector is used for the shake correction mechanism in order to detect the position to which the optical system or the imaging element is shifted.
In Japanese Unexamined Patent Application, First Publication No. 2005-331399, a position detector having a magnetic field generating body, a magnetic field change detecting element, and a position detecting portion is disclosed. In the position detector, a current supplied to each of a plurality of magnetic field change detecting elements is controlled such that the sum of the output voltages from the plurality of magnetic field change detecting elements is constant. As a result, a temperature characteristic and an individual difference of the magnetic field generating body are corrected and a difference in output voltages from each of the magnetic field change detecting elements is taken out as a signal indicating the relative position of the magnetic field generating body and the magnetic field change detecting elements.

Position detecting circuit and imaging apparatus


Analog-to-digital converting circuitry includes first and second analog-to-digital converting units. A converting start controlling circuit sends out converting start timing signals START1 and START2 which are out of phase with each other. When the first or second analog-to-digital converting unit receives the corresponding converting start timing signal START1 or START2 from the converting start controlling circuit, it samples and holds an analog value of an input signal, and then successively converts the analog value into an n-bit digital signal bit-by-bit and sends out the digital signal. An output selecting circuit outputs the digital signals from the first and second analog-to-digital converting units alternatingly.

1. Field of the Invention
The present invention relates to analog-to-digital converting circuitry which can accept an analog signal and produce an n-bit (n is an integer which is greater than or equal to 2) digital signal which represents the analog signal and, more particularly, to successive approximation analog-to-digital converting circuitry for successively analog-to-digital converting the value of an analog input signal being held therein into a digital signal bit-by-bit in synchronization with a clock signal applied thereto.
2. Description of the Prior Art
Improvements have been made in order to speed up the analog-to-digital converting operation of a prior art analog-to-digital converter which can accept an analog signal and produce an n-bit (n is an integer which is greater than or equal to 2) digital signal which represents the analog signal. For example, in Japanese Patent Application Laying Open (KOKAI) No. 60-211533, there is disclosed an Analog-to-digital converter comprising a plurality of sample-and-hold circuits each for sampling and holding an analog input signal, a plurality of Analog-to-digital converting circuits each analog-to-digital converting an output signal from each of the plurality of sample-and-hold circuits, a selecting unit for selecting one from among outputs from the plurality of Analog-to-digital converting circuits to output the selected one, and a control circuit for controlling the operation timing of each of the circuits included in the Analog-to-digital converter. The Analog-to-digital converter starts a sequence of analog-to-digital converting operations in response to a hold instruction at predetermined intervals of T1 which is longer than the length of time T required for a set of a sampling and holding operation, an analog-to-digital converting operation, and an operation of furnishing the binary word which are repeated as a unit. A plurality of sample-and-hold instructions are sequentially delivered to the plurality of sample-and-hold circuits at predetermined intervals of T1/n, respectively. That is, the plurality of sample-and-hold instructions are shifted from each other in time by the length of time T1/n. As a result, the maximum sampling rate becomes (n/T). Thus the analog-to-digital conversion processing can be speeded up.
Japanese Patent Application Laying Open (KOKAI) No. 2-105629 discloses an Analog-to-digital converting apparatus comprising an analog multiplexer for furnishing an analog input signal applied thereto to a plurality of destinations by turns, a plurality of sample-and-hold circuits connected to the analog multiplexer, each for sampling and holding the analog input signal from the analog multiplexer, a plurality of Analog-to-digital converters each for analog-to-digital converting the analog input signal into a digital signal, a digital multiplexer for selecting one from among outputs from the plurality of Analog-to-digital converters and for furnishing the selected one, and a controller for controlling the analog multiplexer, the plurality of sample-and-hold circuits, the plurality of Analog-to-digital converters, and the digital multiplexer. By causing the analog multiplexer to deliver the analog input signal to the plurality of sample-and-hold circuits by turns, the Analog-to-digital converting apparatus disclosed in the reference can sample and hold the analog input signal at predetermined intervals of (1/n) of the minimum Ts of a conversion time period during which each of the plurality of Analog-to-digital converters can perform an Analog-to-digital converting operation, by means of the plurality of sample-and-hold circuits, and then analog-to-digital converts the analog input signal by means of the plurality of Analog-to-digital converters. Thus the Analog-to-digital converting apparatus offers a several-hold or tens-hold improvement in the Analog-to-digital conversion rate in accordance with the number of the plurality of Analog-to-digital converters included in the Analog-to-digital converting apparatus.
Japanese Patent Application Laying Open (KOKAI) No. 4-72919 discloses an analog-to-digital converting apparatus comprising a plurality of Analog-to-digital converters each for converting an analog signal into a digital signal, a sample clock generating unit for generating a plurality of sample clocks which are 180.degree. out of phase with each other and for furnishing the plurality of sample clocks to the plurality of Analog-to-digital converters, respectively, and a switching unit for selecting one from among outputs from the plurality of Analog-to-digital converters by turns and then sequentially furnishing the selected one in synchronization with each of the plurality of sample clocks from the sample clock generating unit. Thus the Analog-to-digital converting apparatus disclosed in the reference can speed up the Analog-to-digital conversion processing by respectively applying the plurality of sample clocks which are out of phase with each other by the same length of time to the plurality of Analog-to-digital converters by means of the sample clock generating unit, and then selecting outputs from the plurality of Analog-to-digital converters by turns and sequentially furnishing the outputs.
Japanese Patent Application Laying Open (KOKAI) No. 6-46010 discloses an analog-to-digital converting apparatus which can analog-to-digital converts an input signal in response to each of eight clock signals which are out of phase with each other. Each of eight Analog-to-digital converters included in the Analog-to-digital converting apparatus can quantize the input signal to an 8-bit digital word in response to each clock generate, so that the eight Analog-to-digital converters sequentially convert values of the input signal applied to the Analog-to-digital converting apparatus via one channel into eight 8-bit digital signals and send out them on eight sets of eight signal lines, respectively. Accordingly, the Analog-to-digital converting apparatus disclosed in the abovementioned reference can speed up the Analog-to-digital conversion processing.
Japanese Patent Application Laying Open (KOKAI) No. 7-162310 (U.S. Pat. No. 5,450,085) discloses a flash-type (i.e., full parallel-type) analog-to-digital converting apparatus comprising a voltage dividing network comprised of a plurality of resistors, for generating a plurality of reference voltages, first and second comparator banks each including a plurality of comparators each having its first input for receiving an analog signal, and its second input for receiving a reference voltage from the voltage dividing network, a comparator activating circuit for activating the comparators of the first comparator bank in response to an even-numbered pulse of a clock signal having two times as long as the periodicity of a system clock, and for activating the comparators of the second comparator bank in response to an odd-numbered pulse of the clock signal, and a digital output selector/encoder for coding outputs from the first and second comparator banks into two digital data, respectively, and then furnishing the two digital data selectively and sequentially. Thus the flash-type analog-to-digital converting apparatus disclosed in the reference can offer a two-fold improvement in the Analog-to-digital conversion rate by alternately activating the first and second comparator banks in response to even-numbered and odd-numbered pulses of the clock signal having two times as long as the periodicity of a system clock. The above-mentioned reference also discloses the use of n comparator banks.
In above-mentioned references such as Japanese Patent Application Laying Open No. 60-211533, No. 2-105629, No. 4-72919, and No. 6-46010, there is no description about the concrete structure of one Analog-to-digital converter included in the Analog-to-digital converting apparatus. However, it is assumed from information described in those references that each Analog-to-digital converter is in the form of a flash-type (i.e., full parallel-type) analog-to-digital converter including a plurality of comparison circuits each for comparing a reference voltage to the value of an analog signal at the same time that the other comparison circuits do, and an encoder for converting the comparison result into a digital signal and then furnishing the digital signal.
While such a prior art analog-to-digital converting apparatus using a plurality of flash-type (or full parallel-type) analog-to-digital converters as disclosed in the above-mentioned references can reduce the time required to convert the value of an analog input signal at a time into a digital signal, it has a disadvantage in that in order to generate an n-bit (n is an integer which is greater than or equal to 2) digital signal, (2.sup.n -1) comparison circuits are needed and therefore the size of the analog-to-digital converting circuitry increases with an increase in the number of bits of the n-bit digital signal to be generated.


A handle assembly for a valve system is provided. The handle assembly includes a first gear coupled to an input shaft, a handle coupled to the input shaft, a second gear coupled to an output shaft and positioned to engage the first gear, and a saddle interconnecting the input shaft and the output shaft.

The present application relates generally to the field of valve actuation. The present application relates more specifically to the field of valve actuators having a geartrain.
Traditionally, lavatory faucet handles feature a direct drive between the handle and the valve. That is, the handle rotates about the axis of the valve stem. Usually this results in rotation of the handle occurring in a plane that is substantially parallel to that of mounting surface. However, one may desire the handle to rotate in a plane that is not parallel (e.g., perpendicular) to the mounting surface. One solution is to mount the valve at an angle relative to the mounting surface, but this requires a larger body and increases the costs of the handle assembly.
Other solutions, for example, US 2007/0145319 and DE 29504966.9, have used gearsets change the axis of rotation between the handle and the valve. However, these designs have shortcomings with regards to size, durability, and user experience (i.e., "feel"). Thus, there is a need for an improved handle assembly for controlling a fluid control valve, the handle assembly including a geartrain for changing the axis of rotation between the handle and the valve.


A method of modifying the porosity of a thickness of a layer of porous dielectric material having a surface and formed on a semiconductor substrate is provided by exposing the porous dielectric material to a sufficient temperature in the presence of a first gas to drive moisture particles out of the pores. Modifying also includes, exposing the porous dielectric material to a radio frequency stimulus of sufficient power in the presence of a second gas to densify a thickness of the porous dielectric material to reduce or prohibit subsequent absorption of moisture or reactant gas particles by the thickness or porous dielectric material.

Modern integrated circuits (ICs) use dielectric layers to isolate the individual devices on a chip from conductive interconnections connected to the individual devices to integrate devices and send and receive signals external to the chip. Popular types of representative dielectric materials include silicon dioxide (SiO2), silicon nitride (Si3N4), phosphosilicate glass (PSG), silicon carbide (SiC), fluorinated silicate glass (FSG), carbon doped oxide (CDO), and cubic boron nitride (CBN). For instance, a dielectric layer of the representative dielectric materials above may be formed at one or more layers of an integrated circuit during integrated circuit fabrication.
The dielectric constant of a dielectric material generally describes the parasitic capacitance of the material. As the parasitic capacitance is reduced, the cross-talk (e.g., a characterization of the electric field between adjacent interconnections, such as aluminum alloy or copper interconnections formed in trenches along the dielectric) is reduced, as is the resistance-capacitance (RC) time delay and power consumption (e.g., with respect to signals conducted along such interconnections).
The dielectric constant of a dielectric material can be substantially effected by water or liquid absorbed in the pores of the dielectric material. Thus, the porosity of the dielectric material, and amount of moisture in those pores can cause a significant increase in the dielectric constant. The porosity of dielectric material is defined as the percent of the volume of dielectric material that is pore space or, in other words, as the ratio of the volume of all the pores in the dielectric material to the volume of the whole dielectric material.

Ambient gas treatment of porous dielectric


A flame ionization detector having a pair of spaced electrodes to which a DC voltage is applied and a flame produced between the electrodes by burning a gas whose composition is to be determined, thereby ions are produced which form an ion current between the electrodes which is representative of the gas composition to be measured. The flame detector is formed by a base plate having a first channel for inlet of the gas whose composition to be measured, a second channel for inlet of a combustion gas, a third channel connected to the first and second channels for conveying a mixture of the gases to an outlet communicating with a nozzle outlet in a ceramic plate on the base plate which faces an opening in a metal plate spaced at a predetermined distance from the ceramic plate such that the flame burns in the opening in the metal plate. An electrically conductive metal layer is disposed on the ceramic plate around the nozzle outlet therein. A negative pole of the DC voltage supply is connected to the metal plate as one of the electrodes and the positive pole of the DC voltage supply is connected to the electrically conductive metal layer as the other of the pair of electrodes. An output line is connected to the electrically conductive metal layer to provide an output signal.

Flame ionization detectors have been used for a long time for measuring hydrocarbon concentration in automobile exhaust gases, as described, for example, in publication "Emission and Imission Measurement Technology in Traffic Systems", published by TUV Rheinland, 1993 printing, page 214.
The measurement principle of the flame ionization detector is based on the fact that ions are formed in a hydrogen flame from hydrocarbon molecules. The flame burns between two electrodes, to which a d.c. voltage is applied. The combustion air and the combustion gas (H.sub.2 or an H.sub.2 /He mixture) are introduced separately into the burner. The exhaust gas sample is mixed with the combustion gas in front of the burner nozzle. The ions formed by the flame produce a charge, which can be measured as an ion current.
The arrangement of the electrodes with their necessary insulation, screw connections and the like results in a complex mechanical construction which is relatively expensive and leads to high production costs. In addition, this arrangement of the electrodes is not suitable for a design having several channels, for example, for measuring overall hydrocarbon content and specific methane content in the automobile exhaust gas simultaneously.


A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.

1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a seal ring and a manufacturing method thereof.
2. Description of the Related Art
With recent improvements in the integration and performance of elements in semiconductor devices, demand has grown for further reductions in wiring thickness and wiring intervals. As miniaturization of the manufacturing process advances, wiring delays limit the operation speed. To deal with this problem, copper wire technology, in which low-resistance copper (Cu) or a copper alloy is used as wiring material, was proposed. It is difficult to process copper or a copper alloy by etching technology when the copper or alloy is used as wiring material. Therefore, a manufacturing method known as a Damascene method is typically employed.
In the Damascene method, a wiring trench is formed in an insulating film, a copper alloy thin film is deposited in the wiring trench, and then the copper alloy thin film is ground from the upper side thereof to leave only the part embedded in the wiring trench remaining. Thus, an embedded wire is formed. In the process for grinding the copper alloy thin film, a CMP (Chemical Mechanical Polishing) method is used.
To reduce the capacitance of the wiring when employing this type of copper wiring technology, a so-called low dielectric constant film is used as an insulating film instead of a conventional silicon oxide film. The low dielectric constant film has a dielectric constant (k) between approximately 4.2 and approximately 1.5.
This type of low dielectric constant film, particularly a porous film, has a low interface adhesion property as a mechanical characteristic (Modulus, Hardness). Therefore, during processes of the Damascene method in which stress is applied to the low dielectric constant film, such as the CMP process and a segmentation process, damage such as peeling may occur on the interface between the low dielectric constant film and an insulating film or another structure such as a seal ring that contacts the low dielectric constant film. As a result, the electric characteristic of the semiconductor device may be damaged.
Among semiconductor devices employing the Damascene method and a low dielectric constant film, a semiconductor device provided with a so-called seal ring that continuously surrounds an element region with the aim of preventing damage inflicted during dicing from reaching the element region is known, and a manufacturing method of such semiconductor device is also known (for example, Japanese Patent Application Kokai No. 2005-167198).
This conventional seal ring is capable of preventing cracks (peeling) that occur outside the element region during the segmentation process from spreading to the element region.

Semiconductor device with seal ring having protruding portions


A method of manufacturing a semiconductor device includes attaching a curable film to a first connection member including a first circuit terminal, attaching a conductive film to a second connection member including a second circuit terminal, and thermally compressing the first connection member to the second connection member, with the first connection member and the second connection member placed such that the curable film and the conductive film face each other.

1. Field
The present example embodiment relates to a method of manufacturing a semiconductor device using a separable anisotropic conductive film including a curable film and a conductive film.
2. Description of the Related Art
An anisotropic conductive film is a film on which an adhesive, where conductive particles such as metal-plated plastic or metallic particles are dispersed, is coated, and is widely used for connection of circuits in the flat panel display field and for mounting components in the semiconductor field.

Method of manufacturing semiconductor device including thermal compression


A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer are broader than a forbidden bandwidth of the channel layer.

1. Field of the Invention
The present invention relates to a field-effect transistor formed of a group-III nitride semiconductor for a power switching transistor which is used, for example, in a general-purpose inverter.
2. Description of the Prior Art
A GaN based nitride semiconductor has a wider band gap, a larger dielectric breakdown electric field, and a higher saturation drift velocity than those of, for example, a Si semiconductor or a compound semiconductor such as GaAs. Therefore, the GaN based nitride semiconductor is a subject of interest for application in a high voltage power device and an electronic device such as a high-speed, high-power transistor. Especially, a heterojunction field-effect transistor (HFET) of AlGaN/GaN having a large drain current has been reported (see Y. F. Wu et al., Appl. Phys. Lett., 69 (1996) 1438), wherein a major characteristic of the heterojunction field-effect transistor of AlGaN/GaN is that in an AlGaN/GaN heterojunction generally formed on a (0001) plane, due to effects of polarization, a high sheet carrier concentration of 1013 cm−2 or higher can be obtained even in an undoped state. As an application field for advantageously using the feature of a large current operation capability of a GaN based electronic device, a power switching transistor is thought to be promising. However, for practical use, it is highly required to realize a high breakdown voltage and to realize a normally OFF state in which a current does not flow when a voltage is not applied to a gate electrode.
Conventionally, an AlGaN/GaN HFET structure has been disclosed in Japanese Laid-Open Patent Publication No. 2003-109973 and in Y. F. Wu et al., Appl. Phys. Lett., 69 (1996) 1438. Moreover, an AlGaN/InGN/GaN HFET structure has been disclosed in Japanese Laid-Open Patent Publication No. 2006-32524.
A conventional AlGaN/GaN HFET structure on a sapphire substrate will be described below.
FIG. 10 is a cross section illustrating the conventional AlGaN/GaN HFET structure on the sapphire substrate. In FIG. 10 illustrated are a sapphire substrate 901, an undoped GaN layer 902, an AlGaN electron supply layer 903, a Ti/Al source electrode 904, a PdSi gate electrode 905, a Ti/Al drain electrode 906, and a device isolation layer 907.
In this case, on a (0001) plane of the sapphire substrate 901, a low temperature GaN buffer layer, the undoped GaN layer 902 having a thickness of 2 μm, and the Al0.15Ga0.85N electron supply layer 903 having a thickness of 25 nm are formed in this order by Metal Organic Chemical Vapor Deposition (MOCVD). On a surface of the AlGaN electron supply layer 903, the PdSi gate electrode 905, the Ti/Al source electrode 904, and the Ti/Al drain electrode 906 are respectively provided, and further, the device isolation layer 907 is provided by a selective oxidation.
FIG. 11 shows Ids-Vgs characteristics of the field-effect transistor of FIG. 10. It can be understood that in FIG. 11, the threshold voltage is −2 V, and a normally ON characteristic is illustrated.
FIG. 12 shows Ids-Vds characteristics in the OFF state. It can be understood from FIG. 12 that an OFF state breakdown voltage is 70 V, where the gate length Lg is 1 μm, and the distance between the gate and the drain is 3 μm. In this case, "OFF state breakdown voltage" is defined as a voltage value at a time when the drain current Ids attains 100 μA/mm by varying a voltage applied between the source and the drain, where the gate voltage Vg is −5 V. This definition is valid for hereinafter described field-effect transistors of the present invention.
However, the conventional AlGaN/GaN HFET structure has a low breakdown voltage of 70 V. In order to realize a high breakdown voltage, it is necessary to expand the distance between the gate and the drain, which results in an increased chip area and a high cost. Meanwhile, in case of a high breakdown voltage, there is a problem that an ON resistance, which is a series resistance between the source and the drain in the ON state, increases, causing greater deterioration in a power switching element. Moreover, as described above, since a high sheet carrier concentration due to the polarization electric field results in a threshold voltage of −2 V indicating a normally ON characteristic, it is difficult to realize a normally OFF characteristic, which is highly required for a power switching element.


A process for intelligent importation of information from a foreign application user interface includes extraction of raster data from a pre-designated region of a screen displayed in the foreign application, segmentation of the raster data into prospective sets of character raster data; application of the character raster data and a feature data set and a vector data set derived from the character raster data as inputs to respective raster, feature, and vector artificial neural networks to generate candidate characters; using a voting process to identify a character represented by the character raster data from the candidate characters; assembly of the remaining characters as recognized by the neural networks into a key; and association of the key with an external data file which may be stored and thereafter retrieved in association with the screen displayed in the foreign application.

The present invention relates to a process for integrating document management and imaging system functionality with a user interface of a "foreign" or unrelated application in a separate process through the use of artificial neural networks.
All forms of business require record keeping related to employees, customers, suppliers, service providers, inventory, transactions, billing, payments, and the like. For such record keeping, most companies employ business application software which typically includes database management functions along with calendar and financial functions. In addition to traditional types of database records, it is also necessary to keep records of supporting documents, such as orders, invoices, statements, checks, photographs, diagrams, bids, contracts, disclaimers, and so forth. Many existing business applications have no built-in capability for accessing or managing digitized copies of such supporting documents, with the necessity that paper copies be stored. It is generally not desirable to modify an existing business application to add image management capabilities and may also be contrary to the terms of the license for the software. Alternatively, the costs and disruptions involved in installing new software with built-in image management capabilities and training employees to use it can be prohibitive. For these reasons, techniques to "image enable" existing business applications have been developed.
Current desktop computers and operating systems have the capability of multitasking, that is, executing multiple programs simultaneously or, at least, having multiple programs open simultaneously and quickly accessible. Thus, it is possible to run a business application and an image management program simultaneously on commonly available computers. The business application is used to process business records while the image management program provides access to stored digital images of documents which support the business records. The goal of image enablement is to provide a convenient link between business records and the particular image files related to those records.
The linking of elements of business records to images often involves keying the contents of a particular data field of a business record to the file name of the digital image. For example, a customer account number, an invoice number, an address or phone number, a social security number, or the like which appears in an appropriate data field of a record could be used as a key to an associated image. The contents of the data field is selected automatically, by the image management software placing a cursor at the beginning of the character string or by highlighting the string. The image management software is activated by either a particular keystroke combination or a mouse click on an icon on a toolbar or task bar, and a scanned image of a supporting document is saved along with the contents of the data field, and possibly other information, such as the position of the data field on the screen. The linking software obtains the data field contents by reading it from the display buffer or by intercepting the data as it is output to the computer display. The image of the supporting document can be recalled when the associated record is displayed by selecting the variable of the appropriate data field and activating the image management software which then retrieves the image file with which the data field variable is associated and displays the image. A process for such an image enablement technique is detailed in U.S. Pat. No. 5,586,240, which is incorporated herein by reference.
The image enablement processes described above are suitable for business applications which are text based since text characters are typically encoded in a standard manner, such as in ASCII codes. However, some applications do not output display data in a text format with some graphics, but in an entirely graphics format. This is sometimes referred to as "painting the screen" with rasterized or pixel format data which depicts text in any of a number of fonts of selected point sizes and colors along with various kinds of graphics. Business applications with such displays are not suited to conventional processes for image enablement.

Intelligent importation of information from foreign applications user interface


A universal point of contact identifier system calling device facilitates a connection between a caller and a call recipient over a telephone network by communicating with a universal point of contact identifier system server. The calling device includes a keyboard, a display, a circuit to make a telephone call and transmit and receive digital data over the network, a memory unit and a micro-controller to control the functions of the device. The keyboard facilitates the entry of an identifier, e.g., an email address, into the memory unit of the device. After entry of the identifier, the circuit connects the device with the server and transmits the identifier to the server. The server utilizes the identifier to establish a connection over the network between the caller and call recipient.

1. Field of the Invention
The invention relates to devices and methods used to enter alphanumeric information for use with a telephone system.
2. Description of the Related Art
Communication has become a part of everyday life. For some people, being disconnected is a concept that is inexcusable. As a result, it is not unusual for someone to have numerous communication points of contact including home telephone numbers, office telephone numbers, cellular telephone numbers, fax machine numbers, pager numbers and email addresses. The need to consolidate a person's points of contact has been addressed in U.S. patent application Ser. No. 09/873,433, which discloses a universal point of contact (UPOC) identifier system, the disclosure of which is incorporated in its entirety by reference herein. While the universal point of contact identifier system solves the problem of consolidating a person's points of contact to a single identifier, such as an email address, the problem of reliably and conveniently facilitating entering such an identifier remains. For example, entry of an email address consisting of letters, numbers and other symbols such as the "@" symbol, is difficult and confusing, if not impossible using a conventional touch-tone telephone keypad.

Universal point of contact identifier system calling device and method


A transmitter generates a burst signal obtained by multiplexing signals of a first polarization and a second polarization orthogonal to each other, and including, at the beginning thereof, a pilot sequence in which the first and the second polarizations each have single frequency components of a first frequency and a second frequency different from each other. A coherent light reception unit performs conversion into an electrical signal by allowing received light and local light to interfere with each other. A pilot sequence detection unit detects a pilot sequence from the converted electrical signal. The polarization estimation unit estimates polarization states of the first polarization and the second polarization at a receiver from frequency components corresponding to the first frequency, and the second frequency. An equalizer demultiplexes the first polarization and the second polarization on the basis of the estimated polarization states.

In an access optical communication system, a single optical line terminal (OLT) accommodates multiple optical network units (ONUs), so that signals are subjected to time-division multiplexing and transmitted for each customer in a passive optical network (PON). Therefore, the OLT receives a burst signal of about 10 μs transmitted from each ONU.
Introduction of digital coherent technology is expected as a method for expanding transmission capacity of an access optical communication system. In the digital coherent technology, signals can be multiplexed using two orthogonal polarizations, but it is necessary to demultiplex the multiplexed two polarizations in a receiver. A polarization state may change each time of burst reception due to changes in the shape of a transmission fiber and the like, and when receiving a burst signal of about 10 μs, it is necessary to estimate the polarization state and to perform demultiplexing at a high speed in about 1 μs.
A sequential update algorithm such as a constant modulus algorithm (CMA) is used to update a coefficient of an adaptive equalization filter that performs polarization demultiplexing, but there is a problem that it takes time to converge. There is also a problem that the adaptive equalization filter outputs the same polarization. In order to solve the above problems, a method has been conventionally disclosed in which the convergence of an adaptive equalization filter is sped up by adding a header signal composed only of each of the multiplexed polarizations to the beginning of a frame in a time-division manner, and estimating a polarization state of a burst signal from a polarization state of a received header (for example, see Non-Patent Literature 1).


The present invention provides a projection apparatus, comprising: a light source; a spatial light modulator for modulating the incident light emitted from the light source; a spatial light modulator control unit for generating, from an inputted image signal, a control signal for driving the spatial light modulator; and a light source control unit for receiving data corresponding to the control signal for controlling the light source to operate in one of three states consisted of a driven state, a stopped state and a standby state on the basis of the data.

1. Field of the Invention
The present invention relates generally to the system configuration and methods for controlling and operating a projection apparatus. More particularly, this invention related to an image projection apparatus implemented with a spatial light modulator and light source with a controller to control the image projection changeover process for operating the light source and the spatial modulator in different operation states.
2. Description of the Related Art
Even though there have been significant advances made in recent years in the technologies of implementing electromechanical micromirror devices as spatial light modulators (SLM), there are still limitations and difficulties when they are employed to display high quality images. Specifically, when the display images are digitally controlled, the quality of the images is adversely affected because the images are not displayed with a sufficient number of gray scale gradations.
An electromechanical mirror device is drawing a considerable interest as a spatial light modulator (SLM). The electromechanical mirror device consists of a mirror array arranging a large number of mirror elements. In general, the number of mirror elements range from 60,000 to several millions and are arranged on the surface of a substrate in an electromechanical mirror device.
Referring to FIG. 1A, an image display system 1 including a screen 2 is disclosed in a relevant U.S. Pat. No. 5,214,420. A light source 10 is used to generate light beams to project illumination for the display images on the display screen 2. The light 9 projected from the light source is further concentrated and directed toward lens 12 by way of mirror 11. Lenses 12, 13 and 14 form a beam columnator operative to columnate the light 9 into a column of light 8. A spatial light modulator 15 is controlled by a computer through data transmitted over data cable 18 to selectively redirect a portion of the light from path 7 toward lens 5 to display on screen 2. FIG. 1B shows a SLM 15 that has a surface 16 that includes an array of switchable reflective elements 17, 27, 37, and 47, each of these reflective elements is attached to a hinge 30. When the element 17 is in an ON position, a portion of the light from path 7 is reflected and redirected along path 6 to lens 5 where it is enlarged or spread along path 4 to impinge on the display screen 2 to form an illuminated pixel 3. When the element 17 is in an OFF position, the light is reflected away from the display screen 2 and, hence, pixel 3 is dark.
Each of the mirror elements constituting a mirror device functions as a spatial light modulator (SLM), and each mirror element comprises a mirror and electrodes. A voltage applied to the electrode(s) generates a coulomb force between the mirror and the electrode(s), making it possible to control and incline the mirror. The inclined mirror is "deflected" according to a common term used in this patent application for describing the operational condition of a mirror element.
When a mirror is deflected with a voltage applied to the electrode(s), the deflected mirror also changes the direction of the reflected light in reflecting an incident light. The direction of the reflected light is changed in accordance with the deflection angle of the mirror. The present patent application refers to the light reflected to a projection path designated for image display as "ON light", and refers to a light reflected in a direction other than the designated projection path for image display as "OFF light". When the light reflected by the mirror to the projection path is of lesser intensity than the "ON light", because only a portion of the reflected light is directed in the ON light direction, it is referred to as "intermediate light". The present patent application defines an angle of rotation along a clockwise (CW) direction as a positive (+) angle and that of a counterclockwise (CCW) direction as a negative (−) angle. A deflection angle is defined as zero degrees (0°) when the mirror is in the initial state.
The on-and-off states of the micromirror control scheme, as that implemented in the U.S. Pat. No. 5,214,420 and in most conventional display systems, impose a limitation on the quality of the display. Specifically, applying the conventional configuration of a control circuit limits the gray scale gradations produced in a conventional system (PWM between ON and OFF states), limited by the LSB (least significant bit, or the least pulse width). Due to the ON-OFF states implemented in the conventional systems, there is no way of providing a shorter pulse width than the duration represented by the LSB. The least quantity of light, which determines the gray scale, is the light reflected during the least pulse width. The limited levels of the gray scale lead to a degradation of the display image Specifically, FIG. 1C exemplifies, as related disclosures, a circuit diagram for controlling a micromirror according to U.S. Pat. No. 5,285,407. The control circuit includes memory cell 32. Various transistors are referred to as "M*" where "*" designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5, and M7 are p-channel transistors; transistors, M6, M8, and M9 are n-channel transistors. The capacitances, C1 and C2, represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a based on a Static Random Access switch Memory (SRAM) design. All access transistors M9 on a Row line receive a DATA signal from a different Bit-line 31a. The particular memory cell 32 is accessed for writing a bit to the cell by turning on the appropriate row select transistor M9, using the ROW signal functioning as a Word-line. Latch 32a consists of two cross-coupled inverters, M5/M6 and M7/M8, which permit two stable states that include a state 1 when is Node A high and Node B low, and a state 2 when Node A is low and Node B is high.
The mirror is driven by a voltage applied to the landing electrode and is held at a predetermined deflection angle on the landing electrode. An elastic "landing chip" is formed on a portion on the landing electrode that makes contact with the mirror, and assists in deflecting the mirror towards the opposite direction when the deflection of the mirror is switched. The landing chip is designed to have the same potential as the landing electrode, so that a shorting is prevented when the landing electrode is in contact with the mirror.
Each mirror formed on a device substrate has a square or rectangular shape, and each side has a length of 4 to 15 um. In this configuration, a portion of the reflected light is reflected not from the mirror surface but from the gaps between the mirrors or other surfaces of the structures of the mirror device. These "unintentional" reflections are not applied to project an image, however, are inadvertently generated and may interfere with the reflected light for image display. The contrast of the displayed image is degraded due to the interference generated from these unintentional reflections generated by the gaps between the mirrors. In order to overcome such problems, the mirrors are arranged on a semiconductor wafer substrate with a layout to minimize the gaps between the mirrors. One mirror device is generally designed to include an appropriate number of mirror elements, wherein each mirror element is manufactured as a deflectable mirror on the substrate for displaying a pixel of an image. The appropriate number of elements for displaying an image is configured in compliance with the display resolution standard according to the VESA Standard defined by Video Electronics Standards Association or by television broadcast standards. When a mirror device is configured with the number of mirror elements in compliance with WXGA (resolution: 1280 by 768) defined by VESA, the pitch between the mirrors of the mirror device is 10 μm, and the diagonal length of the mirror array is about 0.6 inches.
The control circuit, as illustrated in FIG. 1C, controls the mirrors to switch between two states, and the control circuit drives the mirror to oscillate to either an ON or OFF deflected angle (or position) as shown in FIG. 1A.
The minimum intensity of light reflected from each mirror element for image display, i.e., the resolution of gray scale of image display for a digitally controlled image display apparatus, is determined by the least length of time that the mirror may be controlled to stay in the ON position. The length of time a micromirror is in an ON position is controlled by a multiple bit word. FIG. 1D shows the "binary time intervals" when controlling micromirrors with a four-bit word. As shown in FIG. 1D, the time durations have relative values of 1, 2, 4, 8, which in turn define the relative brightness for each of the four bits where "1" is the least significant bit and "8" is the most significant bit. According to the control mechanism as shown, the minimum controllable differences between gray scales for showing different levels of brightness is a represented by the "least significant bit" that maintains the micromirror at an ON position.
For example, assuming n bits of gray scales, one time frame is divided into 2n−1 equal time periods. For a 16.7-millisecond frame period and n-bit intensity values, the time period is 16.7/(2n−1) milliseconds.
Having established these times for each pixel of each frame, pixel intensities are quantified such that black is a 0 time period, the intensity level represented by the LSB is 1 time period, and the maximum brightness is 2n−1 time periods. Each pixel's quantified intensity determines its ON-time during a time frame. Thus, during a time frame, each pixel with a quantified value of more than 0 is ON for the number of time periods that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For controlling deflectable mirror devices, the PWM applies data to be formatted into "bit-planes", with each bit-plane corresponding to a bit weight of the intensity of light. Thus, if the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit-planes. Then, each bit-plane has a 0 or 1 value for each mirror element. According to the PWM control scheme described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled according to bit-plane values corresponding to the value of each bit during one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed for 1 time period.
When adjacent image pixels are displayed with a very coarse gray scale caused by great differences in the intensity of light, thus, artifacts are shown between these adjacent image pixels. That leads to the degradations of image quality. The image degradations are especially pronounced in the bright areas of image where there are "bigger gaps" between of the gray scales of adjacent image pixels. The artifacts are generated by technical limitations in that the digitally controlled image does not provide a sufficient number of the gray scale.
As the mirrors are controlled to be either ON or OFF, the intensity of light of a displayed image is determined by the length of time each mirror is in the ON position. In order to increase the number of gray scales of a display, the switching speed of the ON and OFF positions for the mirror must be increased. Therefore the digital control signals need be increased to a higher number of bits. However, when the switching speed of the mirror deflection is increased, a stronger hinge for supporting the mirror is necessary to sustain the required number of switches between the ON and OFF positions for the mirror deflection. In order to drive the mirrors with a strengthened hinge, a higher voltage is required. The higher voltage may exceed twenty volts and may even be as high as thirty volts. The mirrors produced by applying the CMOS technologies are probably not appropriate for operating the mirror at such a high range of voltages, and therefore DMOS mirror devices may be required. In order to achieve a higher degree of gray scale control, more complicated production processes and larger device areas are required to produce the DMOS mirror. Conventional mirror controls are therefore faced with a technical problem in that accuracy of gray scales and range of the operable voltage have to be sacrificed for the benefits of a smaller image display apparatus.
There are many patents related to light intensity control. These patents include U.S. Pat. Nos. 5,589,852, 6,232,963, 6,592,227, 6,648,476, and 6,819,064. There are further patents and patent applications related to different light sources. These patents include U.S. Pat. Nos. 5,442,414, 6,036,318 and Application 20030147052. Also, U.S. Pat. No. 6,746,123 has disclosed particular polarized light sources for preventing the loss of light. However, these patents or patent applications do not provide an effective solution to attain a sufficient number of the gray scale in the digitally controlled image display system.
Furthermore, there are many patents related to a spatial light modulation including U.S. Pat. Nos. 2,025,143, 2,682,010, 2,681,423, 4,087,810, 4,292,732, 4,405,209, 4,454,541, 4,592,628, 4,767,192, 4,842,396, 4,907,862, 5,214,420, 5,287,096, 5,506,597, and 5,489,952. However, these inventions do not provide a direct solution for a person skilled in the art to overcome the above-discussed limitations and difficulties.
In view of the above problems, US Patent Application 20050190429 has disclosed a method for controlling the deflection angle of the mirror to express higher gray scales of an image. In this disclosure, the intensity of light obtained during the oscillation period of the mirror is about 25% to 37% of the intensity of light obtained while the mirror is held in the ON position continuously.
According to this control process, it is not necessary to drive the mirror at a high speed. Also, it is possible to provide a higher number of the gray scale using a hinge with a low elastic constant. Hence, such a control makes it possible to reduce the voltage applied to the landing electrode.
An image display apparatus using the mirror device described above is broadly categorized into two types: a single-plate image display apparatus implemented with only one spatial light modulator and a multi-plate image display apparatus implemented with a plurality of spatial light modulators. In the single-plate image display apparatus, a color image is displayed by changing, in turn, the color (i.e. frequency or wavelength) of projected light over time. In a multi-plate the image display apparatus, a color image is displayed controlling the multiple spatial light modulators, corresponding to beams of light having different colors (i.e. frequencies or wavelengths), to modulate and combine the beams of light continuously.
A projection apparatus comprising a spatial light modulator, such as the above-described mirror device has conventionally used an arc lamp light source such as a mercury lamp. Such a projection apparatus using an arc lamp light source is configured to switch between irradiating and not irradiating light onto a spatial light modulator by turning ON and OFF the arc lamp light source, thereby switching between projecting and not projecting an image.
Recently, semiconductor light sources, such as a laser light source, have attracts attention as a light source. Laser light possesses high directivity, providing advantages such as having a single wavelength and allowing pulse emission. The application of laser light sources have driven research in many fields (refer to: http://www.ite.or.jp/news/keyword/laser.html) with the development of projection apparatuses being no exception, and the U.S. Pat. No. 7,193,765 has disclosed a projection apparatus comprising a laser light source and a spatial light modulator.
Similar to a changeover control in a projection apparatus using an arc lamp light source, a projection apparatus using a laser light source can also switch between irradiating and not irradiating light onto a spatial light modulator by turning ON and OFF the laser light source, thereby switching between projecting and not projecting an image.
The control for turning ON and OFF the light source in order to switch between projecting and not projecting an image, however, requires a period of time to send an electric current through a circuit to turn on the light source and an emission preparation time period for the light source to emit light (when the light source is turned off and then turned on). Therefore, there is the problem of a slow rise of the light source and a slow response time in switching between projecting and not projecting an image. Furthermore, the fact that the response time in switching between projecting and not projecting an image is slow presents another limitation in projecting an image.

Projection apparatus and image projection changeover method


A heat generator is disclosed that has its driving state constantly monitored and can be disconnected from a power source after an abnormality of its drive mechanism is detected. A plurality of holes are formed at equal angular intervals along the periphery of a disk-shaped rotor, which is capable of rotating in unison with a drive shaft. A magnetic sensor is mounted in a rear housing in a manner opposed to the holes. The drive shaft is selectively connected to the outer drive source via an electromagnetic clutch. A closed magnetic circuit, which is formed in the heat generator by magnetic flux leakage from the electromagnetic clutch, extends through the rotor and the magnetic sensor. When the rotor is rotating normally, the magnetic flux is periodically disturbed by the holes, and the magnetic sensor outputs a pulse signal indicative of the sensed periodic disturbance of the magnetic flux. On the other hand, when the rotor stops rotating due to an abnormality occurring in the rotor drive system, the disturbance of magnetic flux by the holes disappears, and the pulse signal from the sensor ceases. In this case, the drive shaft is disengaged from the power source.

1. Field of the Invention
The present invention relates to a viscous fluid heat generator, and more particularly, to a viscous fluid heat generator that includes a rotary assembly, which can be selectively connected to an external drive source via an electromagnetic clutch.
2. Description of the Related Art
Heat generators that are driven by a vehicle engine have attracted attention as an auxiliary heat source. This kind of heat generator includes a housing, a drive shaft extending through the housing and driven by the engine, and a rotor received in the housing and operatively connected to the drive shaft. Further, the heat generator has a heat-generating chamber defined within the housing, which accommodates the rotor and is filled with a required amount of a viscous fluid. The rotor shears the viscous fluid held between an inner wall surface of the heat-generating chamber and an outer surface of the rotor itself to generate frictional heat by fluid friction.
The drive shaft of the heat generator is connected to a pulley directly or by way of an electromagnetic clutch mechanism. Further, auxiliary machines for the vehicle, other than the heat generator, are also provided with respective pulleys on which power transmission belts extend. Engine output torque is distributed to the heat generator and other auxiliary machines via the power transmission belts.
However, if the drive shaft and the rotor are locked due to some malfunction of the drive mechanism of the heat generator, it will be impossible for the pulley of the heat generator to be driven. In such a case, the power transmission belt slips on the heat generator pulley, and vibrations caused by the slipping of the power transmission belt are transmitted to other auxiliary machines, resulting in noise.
It is an object of the present invention to provide a heat generator that has its driving state constantly monitored and that can be disconnected from a power transmission system of an external power immediately after an abnormality of its drive mechanism is detected.

Kabushiki Kaisha Toyoda Jidoshokki Seisakusho


Wet wipes having improved wet strength, wet thickness and wet toughness are provided by incorporating a wet strength agent in the fibrous web containing pulp fibers and at least five percent by weight man-made fibers and hydraulically entangling the web. No post-formation bonding treatment is employed and the fiber dispersion includes only about 1% by weight of the wet strength additive. The hydroentanglement coupled with the low amount of additive provides unexpected synergistic strength and absorbency characteristics. The wet wipe retains its strength characteristics despite packaging and prolonged storage in a wet condition.

The present invention relates generally to disposable wet wiping cloths and the like. More particularly, it is concerned with a new and improved nonwoven fibrous web material having sufficient wet strength to be used as a wet wipe, yet is capable of disintegration within a septic system after a brief period of time.
Wiping material of this type typically is prepackaged in a moist environment and is commonly used by consumers for cleansing or wiping parts of the body, particularly when wash water is not readily available or cannot be conveniently used. Travelers find such wipes especially convenient. These wipes have been used for applying or removing makeup or in cleansing other parts of the body, for example, as a substitute for conventional dry toilet paper.
As will be appreciated, these premoistened wipes often are disposed of through a sewer or septic system. Thus, while they must have sufficient wet strength to resist tearing and puncturing during use, they also must easily and readily disintegrate within the disposal systems and preferably, when disintegrated, be totally biodegradable. Disposable wipes of this type for personal hygienic use have been known for some time. Typically, they consist of nonwoven webs of fibrous material saturated with a cleansing solution and packaging in their wet condition for easy dispensing. The sheet material is stacked and wrapped in a liquid type package together with a wetting liquid that often includes bacteriacides and other biological control agents as well as perfumes, organism growth inhibitors, and the like.
Some wet wipes described heretofore have utilized a pH sensitive water soluble binder adhesive to achieve the requisite wet strength during packaging and use. The binders of such systems exhibit a resistance to weakening during storage, but are much more loosely bonded when the wipe has been immersed in a relatively large amount of substantially neutral water, allowing the wipe to readily break up in the turbulent water movement of the septic or sewer system. One such wet wipe is described in Adams et al U.S. Pat. No. 4,117,187 issued Sep. 26, 1978. Others have suggested the complete elimination of any binder system and rely instead on the hydroentanglement of the fibers within the wet wipe to achieve the requisite strength to process the web into a premoistened towelette for one time use. Such wet wipes readily disentangle when exposed to mild agitation so that they can be readily disposed of in the sewer and septic systems. A wipe of this type is described in U.S. Pat. No. 4,755,421, the disclosure of which is incorporated herein by reference. That patent describes a binder free hydroentangled web material consisting essentially of a blend of rayon fibers and papermaking pulp. While such materials exhibit acceptable absorption characteristics, the strength of such materials, particularly the wet strength thereof, is relatively poor as will be appreciated from the very rapid disintegration or breakup times exhibited by such materials.
Unfortunately, the addition of wet strength agents to nonwoven fibrous web materials to improve the wet properties of those materials significantly and deleteriously reduces the absorption characteristics of the fibrous web materials.


The inventive concepts disclosed and claimed herein are generally directed to an improved assisted walking device, such as a cane, walker or wheelchair, that includes an integrated oxygen concentrator housed within the assisted walking device. In some embodiments, for example, the improved assisted walking device includes a handle, a control pad, an elongated housing having an interior chamber, an oxygen concentrator, a leg member and a foot member. The oxygen concentrator detachably positioned within the interior chamber of the elongated housing and including an adsorption system configured to generate a flow of oxygen enriched gas, a compressor that includes a motor, a battery, a plurality of sieve beds configured to extract oxygen-enriched gas from ambient air, and a controller in communication with the control pad.

People with breathing conditions, including but not limited to, asthma, chronic obstructive pulmonary disease (COPD), chronic bronchitis, emphysema, lung cancer, cystic fibrosis, or pneumonia, for example, often require additional oxygen for breathing. In addition, many people who have breathing conditions also have limited mobility and require use of an assisted walking device, such as a cane, wheelchair, or walker, for example.
To treat a breathing condition, a physician may prescribe use of an oxygen concentrator. An oxygen concentrator is a medical device configured for delivering doses or a continuous stream of oxygen to a patient in need of additional oxygen. Traditional oxygen concentrators work by filtering the surrounding air, compressing it to the required density and then delivering the concentrated oxygen into a dose delivery system or continuous stream to the person. An oxygen concentrator has a compressing element but operates in a different manner from a traditional oxygen tank that supplies compressed oxygen. The compressed oxygen inside an oxygen tank, for example, is a set amount of oxygen that is dispensed to the user, eventually requiring a refill or replacement when the oxygen inside the tank runs out. People using compressed oxygen tanks must keep several tanks on hand to ensure that they do not run out of oxygen before receiving a refill. An oxygen concentrator, on the other hand, is an oxygen machine that pulls in air from the atmosphere, purifies it, compresses it and then delivers the oxygen-rich air continuously to the user. Traditional oxygen concentrators may be configured to be fixed in a stationary position, such as in a home or alternatively, may be configured to be portable such that a person may carry the traditional oxygen concentrator with them, for example.
Unfortunately, however, traditional oxygen concentrators, even so-called portable oxygen concentrators, are not configured for use by persons who also require assistive walking devices. Most traditional oxygen concentrators are bulky, require access to a back-up power source for additional safety (in addition to a battery) and may include a variety of oxygen hoses and electrical cords configured to ensure continuous and uninterrupted delivery of oxygen. For example, carrying a traditional oxygen concentrator or attaching it to a traditional assisted walking device alters the weight distribution of the traditional walking device making walking more difficult and increasing the likelihood that a person may fall and become injured. Thus, making use of traditional oxygen concentrators, even portable oxygen concentrators, in combination with traditional assisted walking devices cumbersome and dangerous.
Additional disadvantages associated with use of traditional assistive walking devices and traditional oxygen concentrators include, but are not limited to, unnecessary oxygen tanks and hoses, difficulty using both device simultaneously, and a tendency for people to lean forward while using traditional assisted walking devices, causing the added weight associated with a traditional oxygen concentrator to pull the person forward, which further increases the effects of gravity on posture, particularly in elderly persons. Such improper posture, over time, can cause wedging of degenerative discs. Wedging of the discs posteriorly towards the spinal cord can cause harm, including osteoporosis and spinal compression fractures, for example. Persons carrying traditional oxygen concentrators also tend to self-correct the extra weight being carried, causing distortions in balance and increasing the likelihood of falls, when not using the assisted walking device, which may cause injury or death. These issues can be further complicated by a variety of other medical conditions and medications.
To improve the usefulness and safety of traditional assisted walking devices used by people who are also in need of oxygen, it would be advantageous to provide an improved assisted walking device that includes an integrated oxygen concentrator housed within the assisted walking device, as disclosed and claimed herein.

Assisted walking device and method of use


In its various embodiments, the present invention provides a method and apparatus for creating a target executable program from the source code of a target computer program for execution on a target processor. The target processor provided by the method and apparatus has a first set of registers and a second set of registers. Generally, the target processor is capable of executing a first set of instructions which only address the first set of registers. The method and apparatus provides a second set of instruction for the target processor which include a subset of frequently executed instructions within the first set of instructions. These second set of instructions are novel because they able to address both the first set of registers and the second set of registers. A compiler is provided and used for compiling the source code into a number of target executable instructions and allocating the registers on the target processor. The registers within the second set of registers are only allocated to those target executable instructions in the second set of instructions. According to principles of the present invention, the more frequently executed instructions are able to address a register in the second set of registers located on the target processor.

1. Field of the Invention
This invention relates to the field of computer architecture and compiler design. More specifically, the invention is a method and apparatus for generating instructions capable of addressing an additional set of registers on a central processing unit (CPU).
2. Background
There is an ongoing effort to make computer programs as efficient as possible in their execution time. This has driven the development of multiple issue computer processors. The multiple issue computer architecture improves execution efficiency by processing multiple instructions in parallel each clock cycle rather than only a single instruction each clock cycle. Currently, multiple issue processors issue from 2-4 instructions during each clock cycle on the processor. Some examples of multiple issue processor designs are Sun's UltraSPARC.TM. (4 issue), IBM's PowerPC.TM. series (2-4) issue, MIPS' R10000.TM. and Intel's Pentium-Pro.TM. (3 issue). (These processor names are the trademarks respectively of Sun Microsystems, Inc., International Business Machines (IBM) Corp., MIPS Technologies, Inc. and Intel Inc.). Typically, these processors contain multiple I/O memory ports, integer adders, floating point adders, multipliers and other functional units which enable them to execute multiple instructions simultaneously each machine cycle.
A compiler takes the source code of a computer program and generates an executable module containing machine specific instructions designed to execute on a particular processor. Most modern compilers also have an optimizer designed to schedule instructions and make use of available hardware resources in the most efficient manner possible. A multiple issue processor typically requires an optimizing compiler to maximize the issuance of multiple instructions each machine cycle. FIG. 1 illustrates a conventional optimizing compiler 100 used for a multiple issue processor. The compiler 100 typically contains a front end 102, a code generation section 104, an optimizer section 106 and a backend section 108. First, the source code for a computer program is generated by a user and provided to the front end 102 of the compiler where various pre-processing functions are performed. Next, the code is provided to the code generation section 104 which generates a set of instructions expressed in an intermediate code which is semantically equivalent to the source code. Typically, the intermediate code is expressed in a machine-independent format. The code optimizer 106 accepts the intermediate instruction set and performs various transformations to schedule the instruction set in a faster and more efficient manner. Finally, the backend 108 accepts the optimized intermediate code and generates a target executable program 110 which includes a set of machine instructions in binary format which can be executed on a specific target machine (i.e. SPARC, Intel, PowerPC, MIPS etc.). Each machine instruction includes an operation code (opcode) portion and an operand portion containing one or more operands. The opcode portion of the machine instruction instructs the target machine to execute specific functions. The operand portion of the instruction is used to access data stored in the registers during execution.
Efficient execution of the optimized target computer program is limited, in part, by the availability of registers. These registers are located on board the processor and can store and retrieve data faster than memory or any other storage subsystem. During compilation the backend 108 allocates the registers to instructions which store data and operands in registers. Accordingly, an executable computer program would run most efficiently if the backend could allocate registers to all instructions.
Register pressure is a condition which occurs when the mixture of instructions provided to the processor demands more registers than immediately available. When registers are unavailable the instructions must store data in storage mediums having slower read and write access times such as memory or disk thus creating register "spill over". Significant register "spill over" can cause even a highly optimized target executable program to run less efficiently as the latency in retrieving data from these slower storage mediums becomes the processing bottleneck.
For example, assume a multiple issue processor 200 in FIG. 2A has 32 registers in a register set 208 and processor elements 210 are capable of issuing eight instructions each machine cycle. Accordingly, an instruction group 214 in FIG. 2B contains eight instructions (N=8) which can be executed simultaneously on multiple issue processor 200. Further assume, each instruction retains only two registers for a period of four instruction cycles to complete execution. Consequently, an eight issue multiple issue processor 200 must allocate sixteen registers each machine cycle. This translates to 64 registers each four machine cycles. Unfortunately, all 32 of the available registers on the processor are allocated after only the first two machine cycles. Any instruction issued after the first two machine cycles must "spill over" any operands or data into slower storage such as memory or disk until registers become available once again. Performance on this processor becomes limited by the access times of the numerous storage devices on the system.
Register pressure may be reduced in several steps. First, a second or extended set of registers is added to multiple issue processor 200. For example, in the previous example a second set of 32registers can be added to the first set of registers and make 64 registers available on the processor. Unfortunately, this procedure is not the most difficult aspect of reducing register pressure on a processor. In fact, those skilled in the art of chip fabrication can add a second register set on a processor relatively easily using numerous techniques well known in the art.
Addressing the second set of registers is the more difficult problem. Unfortunately, conventional instruction layout formats 216 are unable to address the second set of registers. For example, in FIG. 2B only five bits are reserved in the DR register address field 216B and five bits are reserved in the SR register address field 216C. A five bit register address field can only address the 32 registers in the first set of registers. More than five bits are required to address the second or extended set of registers on a processor. Accordingly, there is a need to devise a method of addressing a second set of registers on multiple issue processor 200.
In the past, a second set of registers on a processor were addressed by adding additional bits to the length of each instruction in the instruction set. These wider instructions used the additional bits to address the registers in the second set of registers. The normal progression is to increase the bit length of instruction from 32 to 64 bits. For example, assume 3 additional bits are required to address additional registers located on a processor which executes 32 bit instructions. Traditionally, these 3 additional bits would be accommodated by increasing the instruction length to 64 bits.
Unfortunately, increasing the bit width of an instruction has several disadvantages. First, processors with wider instruction words are typically incompatible with legacy software compiled for older processors with shorter instruction words. Generally, processors with wider (e.g. 64 bit) instruction words are unable to execute software compiled for narrower instruction words (e.g. 32 bit) and vice-versa. As a result, software developers must recompile each software program for each type of computer. Users and software developers can not enjoy the luxury of using a single executable program across a family of computers. Furthermore, it is more difficult for hardware manufacturers to sell new computers if they can not execute a user's existing software applications.
Second, the increased instruction width is also undesirable because computer programs with wider instruction words require twice the amount of storage in memory and disk. For example, a binary 64-bit instruction word takes up approximately twice as much storage as the corresponding 32-bit instruction word. It would be desirable to address an extended number of registers on a processor without having twice the storage and memory requirements.
Third, increasing the width of the instruction is undesirable because it may increase the cost of the computer system. Increasing the width of an instruction also requires that various bus widths within the computer increase. A computer system with wider bus widths runs more efficiently because wider instruction words can be fetched and processed in less cycles than on a narrower bus architecture. However, this will cost the computer manufacturer a great deal of money redesigning the processor, busses and all the related computer cards and peripherals to accept the wider instruction words. Ultimately, these higher costs will be passed along to the consumer. It would be advantageous to have an instruction set address an additional set of registers without having to redesign various components within the computer system.
The present invention provides techniques to address additional registers without the previously mentioned disadvantages. The present invention uses an elegant method and apparatus to address an extended set of registers on a processor without increasing the width of the instruction.

Method and apparatus for addressing extended registers on a processor in a computer system


Described are techniques for detecting incompatibilities. A first contents of a data item is determined in accordance with a first set of conventions associated with a first processor architecture. A second contents of said data item is determined in accordance with a second set of conventions associated with a second processor architecture and including at least one convention that is not included in said first set. An actual difference between the first contents and the second contents is determined. It is determined whether the actual difference is expected. If the actual difference is not expected, the data item is flagged as an incompatibility candidate. Code referencing the data item is examined to determine any coding incompatibilities due to coding dependencies.

1. Technical Field
This application generally relates to code and processor architectures, and more particularly to techniques used in connection with detecting incompatibilities and coding dependencies.
2. Description of Related Art
A computer system may include one or more central processing units (CPUs) coupled to a memory and other components, such as I/O devices. A computer system may be used to perform a variety of processing tasks and operations. Binary images or machine executable programs may include instructions and data used in connection with performing a particular task. The instructions may be executed by the CPU and may cause the CPU to access the data at one or more locations. The instructions and/or data associated with an executable program may be produced specifically for use with a particular CPU architecture or family of processors. The CPU architecture may also follow certain conventions, for example, when handling memory storage such as accessing the data.
The executable program may be produced from source code written in a programming language. The source code may be produced by a programmer or other automated coding technique and used in connection with generating a first machine executable program for execution on a first CPU architecture. The first CPU architecture may operate in accordance with a first set of conventions. The source code may be written in such a way that there are dependencies on one or more of the first set of conventions. Problems may arise when the same source code is used to produce a second machine executable program for execution on a second CPU architecture having a different second set of conventions. The coding dependencies upon the first set of conventions may result in the first machine executable program operating as expected for the first CPU architecture and associated conventions, but may result in the second machine executable program, associated with the second CPU architecture and conventions, operating in an incompatible manner and producing unexpected results.
Thus, it may be desirable to detect such occurrences of incompatibilities with different architectures and/or conventions as may be associated with different computing environments.

Techniques for detecting coding incompatibilities


An improved method and apparatus for setting a trip-point temperature value for detection of an over-temperature condition in a chip when a reading from a main temperature sensor exceeds the trip-point temperature value. In one embodiment, the trip-point temperature value is set to a known temperature limit value offset by a temperature difference, ΔT. ΔT is calculated by taking the difference between a reading of the main temperature sensor and a reading of another temperature sensor, remote from the main temperature sensor, while a heat-generating circuit is enabled. The main temperature sensor is distal from heat-generating circuit on the chip and the remote temperature sensor is proximate the heat-generating circuit. For multiple heat-generating circuits on the chip, a ΔT is determined for each of the heat-generating circuits, and the largest ΔT is used to calculate the trip-point temperature value. Advantageously, the largest ΔT determination may be done only once.

The operational lifetime of an integrated circuit (a "chip") is directly related to the operating temperature of the chip. Should any portion of the chip reach an over-temperature condition (where the portion of the chip exceeds a known temperature limit which may be as high as a temperature above which the chip will be irreversibly damaged), that portion the chip might fail for a variety of reasons, such as electromigration-induced failure of metal conductors on the chip. To protect the chip from overheating, a thermal protection circuit may be provided that disables or shuts down various circuits on the chip to reduce power consumption thereof. The thermal protection circuit is triggered when the temperature of the chip exceeds a trip-point temperature. Generally, the trip-point temperature is less than the known temperature limit which is less than the irreversible damage temperature.
A typical thermal protection circuit comprises an on-chip temperature sensor. But because the on-chip temperature sensor is typically much smaller than the chip as a whole, the temperature sensor might be located in an area of the chip that is colder than other areas of the chip. This could lead to premature chip failure notwithstanding the use of a thermal protection circuit. For example, even though a thermal protection circuit that has a trip-point temperature equal to the known temperature limit but does not detect an over-temperature condition, because the temperature sensor could be in a "cold" part of the chip, there might be portions of the chip significantly hotter than the known temperature limit and the life of the chip is thereby shortened.
Because of the uncertainty of where and what the highest temperature is on the chip at any given time, the trip-point temperature value is set significantly lower than the known temperature limit. To guarantee that no portion of the chip, regardless of where and how it is used, exceeds the known temperature limit, the trip-point temperature is typically set so low that the chip will shut down well before any part of the chip reaches the known temperature limit, effectively reducing the operating temperature range of the chip.


Systems and methods for using peripheral vision in virtual, augmented, and mixed reality (collectively referred to as “xR”) applications are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: render an object in a peripheral field-of-view of a user; detect at least one of: the user's eye movement, or the user's head rotation; and determine whether to re-render the object based upon the detection.

The goal of virtual reality (VR) is to immerse users in virtual environments. A conventional VR device obscures a user's real-world surroundings, such that only digitally-generated images remain visible.
In contrast, augmented reality (AR) and mixed reality (MR) operate by overlaying digitally-generated content or entities (e.g., characters, text, hyperlinks, images, graphics, etc.) upon the user's real-world, physical surroundings. A typical AR/MR device includes a projection-based optical system that displays content on a translucent or transparent surface of an HMD, heads-up display (HUD), eyeglasses, or the like (collectively "headsets").
In modern implementations, headsets may be tethered to an external or host computer. Most headsets do not have as much processing capability than the host computer, so the host computer is used to generate the digital images to be displayed by the headset. The headset transmits information to the host computer regarding the state of the user (e.g., position, proximity to other users, etc.), which in turn enables the host computer to determine which image or frame to show to the user next, and from which perspective, as the user moves in space.
Current headset solutions have a horizontal field-of-view (FOV) ranging from about 45 degrees to 130 degrees, and therefore are limited to stereo vision applications. The inventors hereof have recognized, however, that there is a need for headsets that can extend the usable display area to include the user's peripheral vision, where Graphical User Interface (GUI) objects such as alerts, menus, etc. may be rendered and/or manipulated.

Systems and methods for using peripheral vision in virtual, augmented, and mixed reality (xR) applications