A method and apparatus for controlling a memory system 100 comprising a plurality of controllers 105 connected by a fibre channel arbitrated loop 145 to provide transparent failover and failback mechanisms for failed controllers. The controllers 105 are adapted to transfer data between a data storage system 120 and at least one host computer 110 in response to instructions therefrom. In the method, a unique identifier is provided to each controller 105. The operation of the controllers 105 is then monitored and, when a failed controller is detected, a failover procedure is performed on a surviving controller. The failover procedure includes disabling the failed controller and instructing the surviving controller to assume the identity of the failed controller. Thus, the surviving controller is capable of responding to instructions addressed to it and instructions addressed to the failed controller, and the failure of the failed controller is transparent to the host computer 110. A computer program and a computer program product for implementing the method are also provided.

This invention pertains generally to the field of computer memory systems, and more particularly to a method and apparatus for controlling redundant arrays of independent disks.
Modern computers frequently require large, fault-tolerant memory systems. One approach to meeting this need is to provide a Redundant Array of Independent Disk drives (RAID) usually including a plurality of hard disk drives operated by a disk array controller that is coupled to a host computer. The controller provides the brains of the memory system, servicing all host requests, storing data to or retrieving it from the RAID, caching data to provide faster access, and handling drive failures without interrupting host requests. Given the importance of the controller, numerous solutions have been suggested minimize the potential for interrupted service due to controller malfunction. One such solution calls for providing dual-active controllers having failover and failback capabilities. Dual-active controllers are a pair of controllers that are connected to each other and to all the disk drives in a RAID. In normal operation, input/output (I/O) requests from the host computer are divided between the dual-active controllers to increase the rate at which information can be transferred to or from the RAID, commonly referred to as the bandwidth of the memory system. However, in the event that one of the controllers fails, the surviving controller takes over the functions of the failed controller and begins servicing host requests addressed to the failed controller in addition to those addressed to it. The mechanism that allows this is commonly known as a failover mechanism. If the surviving controller is able to assume the functions of the failed controller without any actions on the part of the host computer, for example redirecting I/O requests to the surviving controller, the failover mechanism is said to be transparent. If the failed controller can be subsequently replaced and normal operation resumed without de-energizing or reinitializing the controllers the memory system is said to have a failback mechanism.
One example of the use of such dual-active controllers is described, for example, in U.S. Pat. No. 5,790,775, to Marks et al. uses dual-active controllers connected to the host computer by a Small Computer System Interface (SCSI) bus. Typically, the controllers are also connected to a RAID comprising multiple disk drives through a number of additional SCSI buses. Each SCSI device on a bus, such as a controller or a disk drive, is assigned one bit as an identifier (SCSI ID) to permit the host computer to select a particular controller, and the controller to select a particular disk drive. Thus, the method permits a maximum of eight devices to be identified on a standard 8-bit SCSI bus. In addition, the controllers are connected to one another by a separate communications link, and each has access to a cache memory in the other. Although both controllers are connected to every disk drive in the RAID, to permit dual-active operation each disk drive is typically under primary control of one of the controllers. This is accomplished by dividing the RAID into groups of disk drives that appear to the host computer as a logical drive or unit identified by a logical unit number (LUN) and, during initialization, associating each LUN with the SCSI ID of a particular controller. In normal operation, a controller responds only to I/O requests which are addressed to it and which refer to LUNs over which it has primary control. However, if a controller fails the remaining controller of the pair obtains configuration information, including the SCSI ID and the LUNs of the failed controller, over the communications link and begins servicing requests addressed by the host to the failed controller as well as those addressed to itself
While the above approach has been effective in reducing interruptions in service for memory systems having dual-active controllers, it is limited by the architecture of the SCSI bus. Traditionally, SCSI buses have from eight to sixteen signal lines which allows a maximum of from eight to sixteen SCSI devices to be interconnected by the SCSI bus at any one time. Thus, systems which use a 16-bit wide SCSI bus on the host side and 8-bit wide SCSI buses on the device side, typically provide for at most six device side SCSI buses having six disk drives each. Moreover, the above approach, which relies on SCSI IDs, has not been implemented using fibre interface type controllers.
Fibre interface type controllers are coupled to a host computer through one or more fibre channels. Fibre channel is the general name of a technology using an integrated set of standards developed by the American National Standards Institute (ANSI) for high speed, serial communication between computer devices. (See for example the ANSI standard X3T11, xe2x80x9cFibre Channel Physical and Signaling Interface (FC-PH),xe2x80x9d Rev 4.3 (1994), hereby incorporated by reference.) Manufacturers of RAID systems have been moving to fibre channel technology because it allows transmitting of data between computer devices at rates of over 1 Gbps (one billion bits per second), and at distances exceeding several hundred meters and more. Also, fibre channel arbitrated loop (FC-AL) allows for 127 unique loop identifiers, one of which unique identities is reserved for a fabric loop port.
The widely accepted approach to providing failover/failback capability in RAID systems comprising fibre interface controllers has been to use dual-active controllers coupled by a redirecting driver. In the event of a controller failure the redirecting driver shifts host requests from the failed controller to a surviving controller. The failed controller can then be replaced and the memory system reinitialized to return to normal, dual-active controller operation. The redirecting driver can be implemented using a software or hardware protocol. One exemplary redirecting driver is disclosed in U.S. Pat. No. 5,237,658, to Walker et al., hereby incorporated by reference. However, one problem associated with this type of solution is that it is achieved at the expense of added memory system complexity that increases cost and decreases bandwidth. In addition, when, as is common, the redirecting driver is implemented using software in the host computer, this approach is not independent of the host computer, and typically requires a special driver for each host computer system on which it is to be utilized. This further adds to the cost and complexity, and increases the difficulty of installing and maintaining the memory system.
Accordingly, there is a need for a memory system comprising a number of fibre interface controllers and having a failover mechanism that is transparent to a host computer. There is a further need for such a memory system having a failback mechanism that is also transparent to the host computer. The present invention provides a solution to these and other problems, and offers additional advantages over the prior art.
The present invention provides a memory system and method of operating a memory system. In one embodiment, the memory system includes a number of controllers connected by a fibre channel arbitrated loop to provide transparent failover and failback for failed controllers. The controllers are adapted to transfer data between a data storage system and at least one host computer in response to instructions therefrom. In the inventive method, a unique identifier is provided to each controller to permit the host compute r to address instructions to a specific controller. Then, operation of the controllers is monitored and when a failed controller is detected, a failover procedure is performed on a surviving controller. In one embodiment, the failover procedure disables the failed controller and assumes the identity of the failed controller. Thus, the surviving controller becomes capable of responding to instructions addressed to it and instructions addressed to the failed controller, and the failure of the failed controller is transparent to the host computer. In one particular embodiment, the step of providing a unique identifier to each controller preferably includes the step of providing a world wide name to each controller, and more preferably the step further includes providing a loop identifier to each controller.
In another aspect the invention provides a memory system for transferring data between a data storage system and at least one host computer in response to instructions therefrom. The memory system includes a pair of dual-active controllers connected by a fibre channel arbitrated loop. Each controller has a unique identifier and is adapted to assume the identity of a failed controller and to respond to instructions addressed to it, thereby rendering failure of the failed controller transparent to the host computer. In one embodiment, the memory system further includes a communication path coupling the controllers, the communication path being adapted to enable each controller to detect failure of the other controller. The present invention is particularly useful for data storage systems comprising multiple disk drives coupled to the controllers by disk channels, in which at least one disk channel also serves as the communication path.
In yet another aspect the invention provides a computer program and a computer program product for operating a memory system comprising a plurality of controllers, each controller having a unique identifier, and the controllers adapted to transfer data between a data storage system and at least one host computer in response to instructions therefrom. The computer program product includes a computer readable medium with a computer program stored therein. The computer program has a failure detection unit adapted to detect a failed controller . A failover unit is adapted to enable a surviving controller to respond to instructions addressed to it and to instructions addressed to the failed controller. The failover unit includes a disabling unit adapted to disable the failed controller. The failover unit also includes a loop initialization unit, which is adapted to instruct a surviving controller to assume the identity of the failed controller and to instruct the surviving controller to respond to instructions addressed to it and to the failed controller as well as instructions addressed to the surviving controller. Thus, failure of the failed controller is transparent to the host computer. In one embodiment, each controller has an active port and a failover port, and the failover unit is adapted to activate the failover port of the surviving controller. In another embodiment, the computer program product further includes a replacement detection unit adapted to instruct a replacement controller to assume the identity of the failed controller and respond to instructions to the failed controller, thereby rendering replacement of the failed controller transparent to the host computer.
In still another aspect the invention provides a memory system for transferring data between a data storage system and at least one host computer in response to instructions therefrom. The memory system comprising a pair of dual-active controllers connected by a fibre channel arbitrated loop, each controller having a unique identifier, and a means for providing a failover mode from a failed controller to a surviving controller that is substantially transparent to the host computer. In one embodiment, the means for providing a failover mode is a computer program product having a computer program including a loop initialization unit adapted to instruct the surviving controller to assume the identity of the failed controller and to instruct the surviving controller to respond instructions addressed to it and to the failed controller.

Method and apparatus for providing a raid controller having transparent failover and failback

International Business Machines Corporation


A well in a semiconductor wafer is partially filled by a tungsten plug having an irregular surface. There is an aluminum line exterior of the well for electrically connecting the tungsten plug into an electrical circuit. A doped polysilicon fillet having an irregular surface meshing with the irregular surface of the tungsten plug fills the portion of the well between the plug and line, making a reproducible good electrical connection between the tungsten plug and the aluminum line. The poly fillet is formed by a poly deposit and planarization performed between a tungsten plug overetch and aluminum line deposition.

1. Field of the Invention
The invention in general relates to the fabrication of integrated circuits and more particularly to an apparatus and method for improving metal coverage at a step in the integrated circuit structure.
2. Statement of the Problem
As is well-known, integrated circuits, sometimes called semiconductor devices, are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dice or chips. While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials which are either electrically conductive, electrically non-conductive, or electrically semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. In the integrated circuit fabrication art, polycrystalline silicon is usually called "polysilicon" or simply "poly", and shall be referred to as such herein. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant charge carriers and the doped silicon is referred to as N-type silicon. Silicon dioxide is also commonly used in integrated circuits as an insulator or dielectric. Its use is so common that in the art is generally referred to as "oxide" without ambiguity.
Integrated circuit fabrication may begin with a lightly-doped P-type silicon substrate, a lightly-doped N-type silicon substrate, or lightly-doped epitaxial silicon (deposited crystalline silicon) on a heavily doped substrate. For the sake of simplicity, the invention will be described using lightly-doped P-type silicon as the starting material, although it may be implemented with other materials as the starting point. If other materials are used as the starting point, there may be differences in materials and structure as is well-known in the art, e.g. with N-type silicon as the starting point dopant types may be reversed, or P-type wells may be introduced.
The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, the smaller the size, the more difficult it is to fabricate and locate individual parts, such as contacts, within the specifications and tolerances required.
Integrated circuit memories are generally the most densely-packed integrated circuits commonly manufactured today. In memories and other structures requiring densely packed contacts, contacts are conventionally fabricated by creating a photolithographic mask containing the pattern of the contacts to be fabricated, coating the wafer with a light-sensitive material called photoresist or resist, exposing the resist-coated wafer to ultraviolet light through the mask to soften or harden parts of the resist depending on whether positive or negative resist is used, removing the softened parts of the resist, etching the wafer to remove the part unprotected by the resist, and stripping the remaining resist. Generally the etching process is designed to form wells which penetrate the semiconductor structure down to the areas to which electrical connection is to be made. An area in a integrated circuit to which electrical connection is to be made is generally called an active area (AA). Current integrated circuit technology often includes a thin layer of diffusion barrier material, such as titanium nitride (TIN) or titanium tungsten (TiW), interposed between the AA and the metal contact which connects the active area to an electrical source. This diffusion barrier layer prevents interdiffusion of the material in the active area, generally silicon, and the contact metal. After the diffusion barrier is laid down, a layer of metal is then deposited on the semiconductor wafer to fill the wells. After the metal layer is laid down, it is then etched back to remove all the metal from the various surfaces of the semiconductor wafer, except the metal in the wells. The metal which fills the well is generally called a "plug". A metal interconnect which may be a bit line or a word line for example, is then deposited which connects the plugs to an appropriate circuit.
In prior generations of integrated circuits, aluminum or doped polysilicon have been used as the plug "metal". As the contacts have become smaller, especially in sub-micron sizes, tungsten has become the metal of choice, the plugs made of tungsten have become known "tungsten plugs" and a specialized field of engineering has developed generally called "tungsten plug technology". Generally, aluminum is used for the metal interconnect line.
In semiconductor devices, such as memories, where the contacts are so densely packed as to require sub-micron contact sizes, the wells have high aspect ratios, that is the wells are relatively deep compared to their width. In such high aspect ratio wells, as the plug metal is laid down, it tends to cover over the hole before the metal layers covering the opposite sides of the wells meets. This forms an open area in the well called a "keyhole". When the plug metal layer etch back is performed, the keyhole is opened, which forms an irregular upper surface on the metal plug in the well. Further, the TiN diffusion barrier material generally etches faster than the tungsten. This creates structures called "barrier fangs" around the outer periphery of the well where the TiN lining the sidewall has been eroded more deeply than the metal plug, further increasing the irregularity of the upper surface of the metal plug. It is very difficult to form a good contact between this irregular upper surface of the tungsten plug and the aluminum interconnect line. Metal applied to such irregular surfaces tends to crack or break over time, which can cause a defective integrated circuit and can create major reliability problems. There is a need for apparatus and methods that will permit good electrical contact between the aluminum interconnect line and the tungsten plugs to be routinely made and prevent defective integrated circuits.
In addition to the above problems, in order to make sure that all plug metal is removed from critical surfaces, it is usually necessary to "overetch" in the tungsten etch process, that is, etch so much that the metal plugs recede in the wells. This overetch makes it even more difficult to make good contact between the metal plugs and metal lines. Thus there is a need for apparatus and methods that can create reliable electrical contact between the metal lines and plugs even when the plugs are recessed and have an irregular upper surface.
One solution to the problems discussed above has been to use a plug of doped polysilicon rather than a plug of metal. However doped polysilicon is not as good a conductor as metals such as tungsten and aluminum, and the use of a doped silicon material adjacent silicon material of dissimilar material can create P-N junction diodes that can alter the electrical properties of the semiconductor device. Thus this "solution" can create larger problems than the problems it solves. There is a need therefore for a plug design that consistently produces good electrical contact between the active areas and metal lines in semiconductor devices and which does not create high resistivity, P-N junction diodes, and other electrical problems.
The wells discussed above appear in cross-section as a double step, i.e. a step down and a step up. The problems discussed above with respect to filling the wells and making electrical contact with the plug in the well are special cases of the problems generally associated with step coverage of aluminum metal over recessed tungsten plugs in semiconductor fabrication. Step coverage has consistently been a problem in semiconductor device fabrication when the covering material is aluminum. Thus there is a need for apparatus and methods which improves step coverage by aluminum over recessed tungsten plugs.
3. Solution to the Problem
The present invention solves the above problems by providing a process in which, prior to formation of the metal line, a thin layer of doped polysilicon is deposited which fills in the recessed well and smooths out the irregular surface of the tungsten plug. Preferably, the deposition of the poly layer is followed by planarizing by either a dry etch or a chemical mechanical polish. This creates a poly fillet which makes good contact with the irregularities, fills the recess, and makes a smooth surface to which it is easy to make electrical contact with long-term reliability.

Method for making a fillet for integrated circuit metal plug


In various embodiments, the system includes a tubular female end portion of the first pole section and a male end portion of the second pole section that is insertable into the female end portion. Additionally, the system includes a locking nut including a body portion and a neck portion and is threadingly engaged with the male end portion. Furthermore, the system includes a biased locking sleeve assembly that includes a locking sleeve having an internal cavity such that the locking sleeve fits over the locking nut neck portion, and a biasing device located within the interior cavity of the locking sleeve for applying opposing forces to the locking nut and the locking sleeve.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Various industries incorporate the use of long poles to perform various operational, manufacturing, organizational, inspection and maintenance tasks. For convenience and flexibility, such poles are often constructed, or assembled, by connecting various length pole sections together to provide a pole of a specific length. Additionally, a tool or some other instrument or device is often connected to an end of the assembled pole to perform a desired task. In many instances the interconnection of the pole sections, and the interconnection of the tool and respective pole section, can incur substantial stress, vibration, shaking and/or rotational torque during use. Accordingly, it can be important that the interconnections be very secure to prevent loosening and/or separating of the sections and/or tool during use.
For example, high torque, sectional handling poles are often used by nuclear reactor service technicians to manipulate tools utilized for performing various service, inspection and repair tasks inside the reactor vessel. Frequently, during manipulation of the pole and tool within the reactor vessel, particularly when the technician applies a rotational torque to the pole, one or more coupling assemblies used to connect the pole sections and tool together loosen and often separate. When such separation of the pole sections and/or tool occur, the activities must be interrupted until the section or tool is retrieved.


A pessary senses the dilation and effacement of the cervix of patients at risk for premature labor by sensing changes in the energy levels transmitted through the cervical tissue. In one embodiment, light is utilized to periodically illuminate tissues adjacent the cervix, the light being detected serving as an indicator of the onset of labor. The detection of a condition of premature labor is transmitted to a patient monitor through either conductors extending out of the body and into the monitor, or via electromagnetic transmissions (radio) sent from the pessary to a receiver associated with the patient monitor. Interpretation of the energy detected may occur either within the pessary or within the patient monitor.

There are certain individuals which are subject to premature labor which can result in either a premature birth or miscarriage. The state of premature labor can be corrected via the use of drugs known as tocolytics and the provision of immediate medical care. However, the premature labor state by and large cannot normally be identified by the patient so as to enable medical help to be sought at the time of such premature labor. The ability of a patient to identify the onset of premature labor and immediately seek medical attention will significantly reduce the instances of premature birth and miscarriage.
Premature birth requires 24-hour per day monitoring of the prematurely born child, at a cost on the order of thousands of dollars per day. Such monitoring usually continues until the child is of sufficient birth weight and sufficiently healthy that he can be discharged, which can require months.
In as many as 45% of the instances of premature birth, silent labor occurs where the onset of dilation, effacement and change in orientation of the cervix occurs without the accompaniment of perceived uterine contractions until perhaps minutes before delivery. Conversely, false labor may occur, including the onset of uterine contractions without dilation or effacement of the cervix.
Further, the ability to determine the extent to which premature labor is occurring can be of immeasurable help to the medical practitioner. The dosage of medication and type of treatment will depend upon the extent to which the premature labor process has progressed. The medication will typically be a tocolytic agent, such as terbutaline, ritodrine, and magnesium sulfate.
Once the cervix has dilated to a dimension in excess of four centimeters, the labor process will have begun in earnest and is not subject to reversal. Therefore the onset of labor must be detected, usually within an hour of its beginning, to have a significant chance of preventing such premature labor.
The use of a pessary has been known for some time. The dictionary definition of pessary is "a device worn in the vagina to support a displaced uterus." A modern day pessary type device is the diaphragm. Diaphragms are typically disks each having a curved continuous edge, typically supported with an internal wire spring.
The current use of a pessary for supporting a displaced uterus has been replaced by surgical procedures.
In other specialized circumstances, a pessary may be prescribed by an obstetrician, such as for the promotion of healing of trophic cervical lacerations, the relief of acute urinary retention due to a retroposition of the uterus in mid-pregnancy, preventing or relieving postpartum subinvolution or retroversion, or to protect against spontaneous abortion in the case of cervical incompetence.
Since the use and utility of the pessary has been proven, and since it lies in a position proximate to the cervical opening, what is needed is a method to use the pessary to indicate the onset of premature labor.
What is needed is a pessary which can be pre-selected to fit different sizes of vaginal canals and cervical sizes, but which does not touch or irritate the cervix or vagina. The pessary should not block the area of the os, and should be made of a material which will not cause a reaction in the vaginal/uterine environment. The device should be smooth, and should be constructed to facilitate insertion and removal.
The methods employed in detecting the onset of premature labor should not register false positive labor indications despite patient movement and normal non-vigorous activities. The needed structure must be available in sterile form and be sterilizable. It should also be amenable to an operating mode which will conserve battery power.

Monitoring device and method for detection of premature labor


The preparation and use of diamond as an electron emission material is disclosed. Satisfactory measurements were conducted on diamond coatings deposited on WC-Co alloy by a multiple pulsed laser process. The electron emission was measured in a diode configuration with a diamond surface-anode spacing of 20 and 50 .mu.m in vacuum at P=10.sup.-7 Torr. Current densities of 6 mA/cm were calculated at an applied of voltage of 3000 V (for 20 .mu.m). Analysis proved that electron field emission provided by a diamond grown by a multiple pulsed laser process proved to satisfactorily meet the specified demands.

There has been great interest in fabricating cold cathodes using wide-band-gap semiconductors. Such material has been used as coatings on metallic tips, as tip materials, and as thin-film cold cathodes. Materials of current interest include among others diamond, nitrides, disordered carbon forms, and others.
Electron emission is achievable in many ways from a variety of materials and several mechanisms have been proposed to explain the phenomenon. For example, a disordered tetrahedral carbon thin-film device using a diode configuration has been successfully demonstrated in applications for such purposes. (To this purpose see the article by B. L. Weiss, A. Badzian, L. Pilione, T. Badzian, and W. Drawl, Appl. Phys. Lett. 71, 794 (1997).) This material seems to satisfy the provide the following qualities:
(i) electronic structure characteristics of wide-band-gap semiconductors; PA1 (ii) high dielectric breakdown; PA1 (iii) n-type electrical conductivity; PA1 (iv) favorable emission surface properties, including negative electron affinity and/or emission enhancement by adsorbed specific atoms; and PA1 (v) durability under a high electrical field, including longevity in thousands of hours.
In general, diamond material fulfills these conditions as is demonstrated in the extensive electron emission art. Examples include: U.S. Pat. No. 3,947,716, issued on Mar. 30, 1976, to Fraser, Jr. et al.; U.S. Pat. No. 3,970,887, issued on Jul. 20, 1976, to Smith et al.; U.S. Pat. No. 4,307,507, issued on Dec. 29, 1981, to Gray et al.; U.S. Pat. No. 4,685,996, issued on Aug. 11, 1987, to Busta et al.; U.S. Pat. No. 4,955,636, issued on Aug. 8, 1989, to Busta et al.; U.S. Pat. No. 4,964,946, issued on Oct. 23, 1990, to Gray et al.; and U.S. Pat. No. 5,703,435, issued Dec. 30, 1997.
According to some of the teachings of the art, chemical vapor deposition (CVD) methods were used in the fabrication of emission devices because of their versatility.
Of these requirements, the most difficult to achieve is the n-type diamond, preferably as a shallow donor material. However, n-type diamond was reported as a result of P (phosphorous) doping of (111) homoepitaxial thin films. In this investigation, Hall measurements were taken and an activation energy of 0.46 eV was calculated. (See S. Koizumi, M. Kamo, Y. Sato, H. Ozaki, and T. Inuzuka, Appl. Phys. Lett. 71 (1997) at 1065.)
While providing arguable improvements in the art, the prior art fails to provide a practical method of providing a diamond suitable for providing electron field emission. Such a method remains wanting.

Application of electron field emission from diamond grown by a multiple pulsed laser process


Systems, apparatuses and methods for technology to perform gait detection and identification. The system includes a pre-processing pipeline to process audio input data from one or more microphones to combine and strengthen an audio gait signal. The pre-processing pipeline is coupled to a gait detector to detect the sound of one or more footsteps from the audio gait signal. The system also includes a person evaluator (e.g., identifier/verifier) to identify the person associated with the one or more footsteps using a set of trained footstep identification (ID) classifiers. Each trained footstep ID classifier is mapped to the gait of a specific person in the home based on a particular combination of person, footwear, and floor surface within the home.

Smart home systems may use cameras and video analysis, such as person recognition based on their facial features, to determine the identity and location of a person in the home. Having surveillance cameras throughout the home, however, may be regarded by many users as an invasion of privacy that also incurs additional costs associated with purchasing and installing cameras in every room. Alternatively, each person could wear a device, such as, for example, a radio frequency (RF) identification (ID) tag that communicates with associated sensors located in every room to determine where each person is located. This approach, however, may call for each person to always wear an identification tag, which may not be user friendly.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.


Segmented guide tubes for the signal-bearing wires for journal and thrust bearing instrumentation are received in the lower bearing housing section without removal of the rotor or major tear-down of the turbine. Guide tube segments for the thrust bearings are specifically shaped and configured to enable remote or blind threaded connection within the lower housing section with fittings facilitating the "feel" for the alignment necessary to thread a first straight tube segment from above the lower housing section into the fitting of a second guide segment introduced into the drain hole of the lower housing section. Once threaded together, signal-bearing wires may be snaked through the resultant guide tube assembly. Guide tubes for the journal bearing include side guide tube segments secured at their upper ends to the lower housing section and to a Y-tube connection at their lower ends. A pair of guide tubes are assembled with one guide tube end being coupled to the Y-tube fitting and carrying a self-locking leaf spring support for securing the aft end of one guide tube end in a reduced cavity in the lower housing section by remote means. The latter pair of guide tube segments are clamped to a drain pipe in the drain opening with the second segment passing through a penetration opening in the bearing housing.

As well known, turbine bearing housing instrumentation typically includes thermocouples and proximity probes in the region of the thrust and journal bearings for the turbine rotor. During normal operation, both types of instrumentation are used to measure important physical conditions within each bearing housing. Measurement is accomplished with external meters which receive electrical signals from the instrumentation through insulated wires or cables (hereafter referred to as wires or signal-bearing wires). By necessity, the wires pass through each housing at convenient penetration points which are sealed to prevent oil leakage. Externally, the wires are enclosed within a conduit to provide protection from hostile environmental conditions. Internally, the wires are enclosed within guide tubes securely mounted to and within each bearing housing. It is important to enclose the wires within the housing; because undue wire flexing, unless restricted, results in damage to the wires due to whipping or flailing of the wires caused by turbulent oil flow within the housing.
Bearing housings of a turbine rotor typically includes upper and lower housing sections split along a generally horizontal plane such that the upper housing section may be removed for inspection and maintenance of signal-bearing wires and protective guide tubes, associated with the bearings and other parts. Bearing instrumentation are generally located in the lower housing section. When it is desired to retrofit instrumentation components, guide tubes and wires into a bearing housing, general installation of the same has heretofore been possible in the field, or on other occasions in the factory, only after rotor removal and major tear-down of the turbine. It will also be appreciated that, with the upper bearing housing section removed, access to the lower bearing housing section is extremely limited due to the presence of the bearings and the rotor in the lower housing section. Moreover, it is costly and time-consuming to remove the rotor and other parts of the turbine to facilitate access into the lower housing for purposes of installing bearing instrumentation and related material. It will also be appreciated that the lower housing section is closed and generally inaccessible along its sides except for lubrication drain and supply penetration points which open through the end face or bottom of the bearing housing. Thus, limited access to the inside of the lower housing section has prevented ready retrofitting of protective guide tubes for instrumentation signal-bearing wires without major tear-down of the entire turbine and removal of its rotor. Normally, guide tubes are installed upon the initial manufacture of the turbine and general retrofitting heretofore has been considered clearly impractical due to the foregoing shortcomings.

Apparatus for installing guide tubes for instrumentation signal bearing wires in the bearing housing of a turbine


Various embodiments of the invention relate to orthotic apparatuses configured to apply a controllable, therapeutic force to a subject. In one embodiment of the invention, an orthotic apparatus includes a frame structure and an actuator system operable to provide input energy of a first type (e.g., fluid pumped by a pump or an applied voltage). At least one strap structure is attached to the frame structure and operably coupled to the actuator system. The at least one strap structure may be configured to convert at least a portion of the input energy to energy of a second type, the energy of the second type being strain energy. Additional embodiments are directed to inflatable structures and methods of operating the orthotic apparatuses and inflatable structures disclosed herein.

A variety of knee braces are currently available for treating different knee problems. Knee braces may be designed to impart forces on limbs surrounding the knee to relieve compressive forces in a portion of the knee. Additionally, knee braces are often employed to support the knee after a knee injury, such as a sprain, or to assist with rehabilitation of the knee after a traumatic event, such as knee surgery.
The human knee is a joint held together by small, powerful ligaments. The femur (i.e., the thighbone) meets the tibia (i.e., the large shin bone) to form the main knee joint called the femoro-tibial joint. The kneecap (i.e., the patella) joins the femur to form a second joint called the femoro-patellar joint. The patella protects the front of the knee. The knee is surrounded by a joint capsule with collateral ligaments strapping the inside and outside of the joint and cruciate ligaments crossing within the joint. The collateral ligaments run along the sides of the knee and limit the sideways motion of the knee. The anterior cruciate ligament ("ACL") connects the tibia to the femur at the center of the knee and functions to limit rotation and forward motion of the tibia. The ACL divides the knee into an inner (medial) and an outer (lateral) compartment. The posterior cruciate ligament ("PCL") is located aft of the ACL and limits backward motion of the tibia. The knee also includes a thickened cartilage pad known as a meniscus attached to the tibia and an articular cartridge attached to the femur. The meniscus and articular cartridge function as smooth bearing surfaces that allow for pain-free relative rotation of the femur and tibia.
The knee is still a relatively weak joint that can be easily damaged despite the knee being held together by powerful ligaments. For example, the knee may be damaged by participating in sporting events, overloading due to obesity, aging, or misalignment of the knee. Most knee problems are a result of damage of the cartilage of the knee and strain of the ligaments of the knee.
One important knee problem is unicompartmental osteoarthritis in which either the medial (inward) or the lateral (outward) compartment of the knee joint is deteriorated. In a proper functioning knee, both compartments are loaded generally uniformly. A knee joint that suffers from unicompartmental osteoarthritis is characterized by an uneven distribution of pressure in either the medial or lateral compartment of the knee. Such uneven distribution of pressure can wear away the smooth cartilage lining the inside of the knee, which may, consequently, lead to painful, direct contact between the femur and the tibia.
Unicompartmental osteoarthritis may be treated by using a knee brace that is configured to urge the femur and tibia apart in the affected compartment of the knee to reduce or eliminate the painful bone-to-bone contact between the femur and the tibia. Despite the availability of a number of different knee braces to treat unicompartmental osteoarthritis, there is still a need for an improved knee or other joint brace to treat unicompartmental arthritis and/or other knee or joint problems.

Orthotic apparatus and method of operation


A method and apparatus for debugging a sequence program by partially running the program by a programmable controller. The programmable controller includes memory to store the sequence program and memory to store partial run conditions comprising identity of a external device required for a partial run of the sequence program, a device access method and relevant data. An external i/o device interfaces with the programmable controller to store the partial run condition. The programmable controller includes a compare circuit for comparing the stored partial run conditions and the status of the program during a partial run. The comparison circuit outputs a signal which stops the run when the result of the sequence program operation is identical with the stored partial run conditions. The stop step and number of scans of the sequence program at the time the match is identified can be output for example, on a display.

1. Field of the Invention
This invention relates to a programmable controller and particularly to a method of debugging a sequence program.
2. Description of the Backqround Art
A programmable controller (hereinafter referred to as a "PC") is employed to control an object by means of a computer program. In practice, many PCs are used to control a wide variety of devices, machines and actuators in a broad spectrum of environments, e.g. processing plants, manufacturing facilities and the like.
FIG. 6 is a hardware configuration diagram of a conventional PC 10, wherein a CPU 11 is connected by a bus 18 to an OS 12 defining the operation of the CPU 11. A sequence program memory 13, which allows a user to store a user-written sequence program (hereinafter referred to as the "sequence program") for subsequent access, also is connected to the bus 18. A device memory 14 serves as an internal memory which allows the user to transfer data, as required. The user writes a sequence program by means of an external device 16 for input into the sequence program memory 13 via a communication interface 15. The external device 16, which allows the sequence program to be created, also permits data from the device memory 14 to be monitored and displayed. The monitoring capability is not illustrated but, as would be understood by one of ordinary skill, a monitor can indicate changes that occur as a result of a sequence program executed in accordance with a program running method. From external device 16, a full program run or a partial run command for the sequence program can be transmitted to the CPU 11.
A "partial run" of the sequence program is conducted when the sequence program is run instruction-by-instruction at particular instruction steps of the sequence program, is run up to a specified instruction step, or is run until it reaches a specified instruction step a specified number of times. Generally, a partial run is employed when debugging the sequence program without connecting the PC 10 to an object to be controlled (not illustrated) after the user has created the sequence program. The partial run permits efficient debugging since only the portions of a program that are of interest need be executed for test purposes. During the run, the program may operate to access or control any of several external devices D.sub.x, e.g. disk drives, modems etc. interfaced into the PC system, each being identified by a unique number "x".
FIG. 7 shows an example of a sequence program segment in the form of a ladder diagram and is useful in illustrating partial run of a sequence program. The sequence program segment shown in FIG. 7 is operative to run until the identifier X for the selected one of the several external devices D.sub.x changes to "9". Specifically, parameter values of X=9 are set at each of program steps 52, 54 and 56, which are followed by respective condition instructions 58. When run, the program permits an identification of the program step and scan at which the sequence program is stopped by means of the external device 16. For this purpose, a "scan" will be understood as the activity beginning with the execution of an instruction step 0 and proceeding to the occurrence of an END instruction that is followed by another instruction step 0 in the sequence program.
FIG. 8 is a flowchart illustrating a sequence for running the sequence program shown in FIG. 7.
Operation will now be described with reference to FIGS. 7 and 8 where X identifies a external device D.sub.x, Y identifies the number of scans and Z identifies a current program step number. In FIG. 8, the partial run of the sequence program is started at sequence step 100. Data X, identifying the external device D.sub.x, is changed at sequence step 101, i.e. X=1 is obtained by executing X=X+1 (initial value X=0) at program step 51 in FIG. 7. Then, whether X=9 or not is judged at sequence step 102, i.e. program step 52 in FIG. 7 is executed. If X=9, the operation proceeds to sequence step 108 where the current program step number is stored in an external storage device D.sub.z, i.e. program step 58 in FIG. 7 is executed. However, since X=1 in this case, sequence step 103, i.e. program step 53 in FIG. 7, is executed and X=3 is obtained according to X=X+2. Then, whether X=9 or not is judged again at sequence step 104, i.e. program step 54 in FIG. 7 is executed. Since X is not 9, sequence step 105, i.e. program step 55 in FIG. 7, is executed and X=6 is obtained according to X=X+3. Then, whether X=9 or not is judged again at sequence step 106, i.e. program step 56 in FIG. 7 is executed. Since X is not 9, sequence step 107, i.e. program step 57 in FIG. 7, is executed and "1" is added to an external storage device D.sub.y which counts the number of scans. If it is assumed that the external device D.sub.y already stores an initial value of Y=1, indicating the conduct of a first scan, Y=2 is obtained according to Y=Y+1. In FIG. 7, "INC Y" indicates the addition of 1 to the device D.sub.y, i.e. execution of Y=Y+1, and "JMP P1" indicates an instruction which causes a jump to instruction step P1, i.e. an END instruction step 60.
The operation then executes the END processing at sequence step 110, i.e. program step 60 in FIG. 7, returns to the instruction step 0, i.e. sequence step 101, thereby completing a "scan" sequence, and repeats the processing. As a result of the first scan sequence, for the second scan, the value of the device D.sub.z changes to X=7 according to X=X+1 at the sequence step 101, i.e. the program step 51 in FIG. 7. X will become equal to 9 according to X=X+2 at sequence step 103, i.e. upon execution of program step 53 in FIG. 7. Therefore, X=9 is established at sequence step 104, i.e. when at program step 54 in FIG. 7. As a result, a program step number, i.e. Z=2 in this case, is stored in device D.sub.z at sequence step 108, i.e. program step 58 in FIG. 7, and the operation jumps to instruction step P0.
Clearly, the operation is only caused to jump to instruction step P0 when the device identifier value X changes to "9". Thus, the setting of a "break point", i.e. a position to stop the sequence program, at instruction step P0 in advance allows the number of stop scans (Y) and a stop step (Z) to be identified. The device D.sub.y, which stores the number of scans Y, and device D.sub.z, which stores the stop step number Z at which the execution of the sequence program is to be stopped, can be used to control other operations. An NOP program step 59 in FIG. 7 indicates that instruction step P0 is a no-operation instruction and does not have any influence on the program control. JMP P1 in program step 57 causes a jump to instruction step P1, the END instruction.
However, when it is desired to change device data, the partial run may be performed only after adding (or changing) corresponding relative program steps. Specifically, it is necessary to add the program steps 52 and 58, the program steps 54 and 58, and the program steps 56 and 58 in correspondence with the program steps 51, 53 and 55 shown in FIG. 7, respectively. Therefore, the sequence program must be increased by six program steps and, as a result, becomes complicated and inefficient.
Also in this conventional technique, if it must be determined whether X or some other parameter has taken a particular value, an interrogation of the system for that criterion was required at each step. Such determination would have been made by checking whether a particular address has particular data values, thereby requiring extensive processing time.

Method and apparatus for partially running a sequence program for debugging thereof


A microelectromechanical system (MEMS) device is created by forming mechanical structures supported by a substrate having a bond ring area laterally spaced from the mechanical structures and having a sacrificial layer surrounding the mechanical structures. A bond ring material is formed on top of the sacrificial layer and the bond ring area. Some of the bond ring material is then removed to create a bond ring.

Micro-electromechanical system (MEMS) devices are very small and fragile. They need to be protected from physical harm and contamination. Some MEMS devices require a special environment, such as a gas or liquid fluid, in which to operate. Prior attempts to provide such protection involve the use of a cover, such as a window or plate fixed over the MEMS device to protect it. Such windows or plates may be fixed on an annular ring of a polymer extending above and around the MEMS device. It may be difficult to form the ring with desired materials due to thermal budget constraints. The ring may also need to be formed in such a manner to facilitate sufficient sealing of the cover.

Hewlett-Packard Development Company, L.P.


A pickup arm for use in phonographs or the like having a contactless inside-force cancelling device and/or a contactless stylus-force application device; the contactless inside-force cancelling device having a rotatable control magnet, a stationary control magnet, a cylindrical magnet fixed around the vertical pivot of the pickup arm, the rotatable and stationary control magnets combinedly forming a magnetic field in which the cylindrical magnet is rotatably placed, wherein rotation of the rotatable control magnet changes the magnetic flux density of the magnetic field to give the vertical pivot a torque sufficient to cancel the inside force of the stylus; the contactless stylus-force application device having a rotatable control magnet, a stationary control magnet, a cylindrical magnet fixedly provided on a horizontal axle fixed between the prongs of a forked end provided on the vertical pivot, the rotatable and stationary control magnets combinedly forming a magnetic field in which the cylindrical magnet is rotatably placed, wherein rotation of the rotatable control magnet changes the magnetic flux density of the magnetic field to give the vertical pivot a torque corresponding to the stylus force.

1. Field of the Invention
The present invention relates to a pickup arm or tone arm for use in phonographs or the like and, more particularly, to a pickup arm provided with an inside-force cancelling device and a stylus-force application device, both devices having a new and novel mechanisms for generating and controlling magnetic forces.
2. Description of the Prior Art
In reproducing the recorded sound from a record by the use of a pickup arm, the tip of the stylus is pulled in the direction tangent to the groove by a force f proportional to the stylus force. If the angle between the line connecting the vertical pivot of the pickup arm with the stylus point and the tangent to the groove is assumed to be .phi., a component of force f'=f tan .phi. will act toward the center of the record. The component of force f' is called the inside force. The inside force causes the stylus to laterally press the side walls of the grooves thereby deteriorating the quality of reproduction of the recorded sound.
The angle .phi. varies with the diameter of the groove. Therefore, the inside force also varies as the stylus point moves from the outside portion of the record toward the center thereof or as the pickup arm advances. In other words, the inside force is at a maximum when the stylus is at the outside portion of the record and decreases as the stylus approaches the center of the record as shown in FIG. 9. In order to cancel or eliminate the inside force, various technical means have been proposed to give the pivot of the pickup arm a torque having a characteristic curve opposite to that of the inside force. However, these inside-force cancelling means have some disadvantages. For instance, those with balance weights have a disadvantage in that they lose balance when the pivot of the pickup arm is placed obliquely. In other words, when the plane on which the pickup arm rotates is not horizontal, those with springs have a disadvantage in that it is difficult to obtain a repulsion performance sufficient to cope with close control, while those of the magnetic repulsion type are higher in repulsion performance than those of the above-mentioned type but not satisfactory.
Meanwhile, conventional means for controlling the stylus force which causes the occurrence of the inside force are usually divided into two types, namely static balance type and dynamic balance type. The static balance type means balance the weight of the arm containing the pickup cartridge with that of a counterweight. The dynamic balance type means utilize the repulsion of springs. These means, however, also have disadvantages similar to those mentioned hereinabove.
As is well known, the record is generally made of synthetic resin and, strictly speaking, is not uniform in thickness and therefore the stylus moves up and down while varying the stylus force. The smaller the stylus force, the smaller the inside force is. However, if the stylus force is too small, the stylus point cannot perfectly follow the wavy movement of the record surface. Therefore, it is required to provide a pickup arm mechanism that can keep the stylus force proper within the allowable limit.
The stylus-force application device of the present invention is of the dynamic balance type. The basic mechanism and principle on which it depends are similar to those of the inside-force cancelling device mentioned above.
This stylus-force application device is much superior in performance to the conventional device because such contains no resonant element such as a spring mechanism as in the conventional device which deteriorates the reproduced sound and can produce the stylus force by contactless means.
With this device, the stylus force may be closely controlled in an increment of about 10 mg. Accordingly, this device can achieve the so-called small-stylus-force control required for the high-speed rotation of the video disk record and can remarkably increase the service lives of the stylus and the record.
Therefore, the present invention is intended to eliminate the above-mentioned disadvantages of the prior art.


An insulated gate N-channel field effect transistor has a P-type semiconductor substrate, an N-type epitaxial layer disposed on the P-type semiconductor substrate, and a gate insulating film disposed on the N-type epitaxial layer. An N-type high concentration source region is formed in the N-type epitaxial layer. An N-type high concentration drain region is formed in the epitaxial layer in spaced-apart relation to the N-type high concentration source region. A channel forming region is disposed between the N-type high concentration source region and the N-type high concentration drain region. A gate electrode is formed on the channel forming region through the gate insulating film. An N-type low concentration region is disposed between the N-type high concentration drain region and the channel forming region and between the N-type high concentration source region and the channel forming region. An insulating film is disposed on the low concentration region. A P-type well layer surrounds the N-type high concentration drain and source regions and is disposed in a region including the channel forming region and only a part of the region under the insulating film.

1. Field of the Invention
The present invention relates to an insulated gate N-channel field effect transistor having a withstand voltage of 10 V or more at a semiconductor substrate which can incorporate a Bipolar or CMOS and on which an epitaxial layer is formed. The present invention also relates to a semiconductor device including this insulated gate N-channel field effect transistor.
2. Description of the Related Art
FIG. 5 is a sectional view of an example of BiCMOS integrated circuits, which is manufactured by using a P-type semiconductor substrate 1 and through an N-type epitaxial step. An N-channel insulated gate field effect transistor 101 is formed in a P-type well layer 4 formed in an N-type epitaxial layer 2. A P-type insulated gate field effect transistor 102 is formed in a region of the N-type epitaxial layer 2. An NPN vertical bipolar transistor 103 is manufactured in such a manner that a P-type base diffusion region 15 and an N-type sinker 14 are formed in the N-type epitaxial layer 2 on an N-type buried layer 13. Separation between respective elements, especially, the separation between the insulated gate field effect transistor and the bipolar transistor can be made in such a manner that a P-type buried layer 3 and the P-type well layer 4 are subjected to diffusion from an upper side and a lower side of the N-type epitaxial layer and are brought into contact with each other.
The thickness of the N-type epitaxial layer depends on the performance of an objective integrated circuit. As an example, when the withstand voltage of the NPN vertical bipolar transistor is set to 15 V or more, preferably the thickness thereof is set to 4 xcexcm or more. As for the N-type sinker 14, for the purpose of lowering collector resistance and lowering h fe of a parasitic bipolar, the concentration thereof is preferably selected from a range of 5xc3x971017 to 1xc3x971019/cm3. Also, the depth thereof is preferably selected from a range of 3 to 5 xcexcm.
FIG. 2 is a sectional view of an example of an insulated gate N-channel field effect transistor used at a semiconductor substrate including an epitaxial layer in a BiCMOS integrated circuit.
Reference numeral 1 denotes a semiconductor substrate, and a P-type semiconductor substrate is generally used. An N-type epitaxial layer 2 of 1xc3x971014 to 1xc3x971016/cm3 is formed on this P-type semiconductor substrate, and elements are formed therein. In case of the N-channel insulated gate field effect transistor, a P-type well layer 4 and optionally a P-type buried layer 3 are formed, and BiCMOS integrated circuit is formed in this P-type region. Reference numerals 5 and 6 each denote a source region and a drain region of the insulated gate field effect transistor, in which P (Phosphorus) or As (Arsenite) is implanted to make the concentration as high as 1xc3x971020/cm3 or more. A gate electrode 8 is formed over a channel forming region 11 through a gate insulating film 7. However, an N-type low concentration region 9 of 1xc3x971016 to 1xc3x971018/cm3 is formed between the drain region 6 and the channel forming region 11, with the result that a withstand voltage between the drain and source can be raised as compared with the case where this low concentration region does not exist.
This is because a depletion layer on the drain side is apt to extend in this low concentration region as compared with general insulated gate field effect transistors. As a result, there is an effect to suppress the avalanche breakdown from occurring in the junction between the drain region and the channel forming region. The length of this low concentration region depends on a desired withstand voltage. However, the length is preferably set between 1.5 xcexcm and 3 xcexcm in the case where the desired withstand voltage is within a range of 15 V to 40 V. When the insulating film on the N-type low concentration region is made thicker than the gate insulating film, it is possible to avoid occurrence of a high electric field between the gate and drain, as well as preventing a leak and breakdown caused by this. It is preferable to set the thickness of this insulating film 10 thicker than the gate insulating film be 0.1 xcexcm or more. For example, a field insulating film for separating elements may also be used as the film.
However, the insulated gate field effect transistor having the structure of FIG. 2 has a low ESD (electric static discharge) strength. Accordingly, there is a defect in that when a drain terminal is connected to an external pad, junction breakdown is liable to occur in the N-type low concentration region by static electricity entering the drain terminal from outside. In order to prevent the breakdown by the static electricity, for example, there is a method in which a specific protective element is provided at a wiring line communicating with a pad in a circuit. However, by providing this protective element, an area of a semiconductor integrated circuit is increased, resulting in an increase of the cost. In order to improve the ESD strength of the insulated gate type transistor without using the protective element (for preventing an increase of an area of a semiconductor integrated circuit), as shown in FIG. 3, there is a method in which a deep N-type diffusion region 12 is formed around a high concentration drain region as a center, for instance. However, this method also causes a cost increase arising from the increase of steps, since a mask step and a diffusion step must be newly added to form the N-type diffusion region. The higher the concentration of the N-type diffusion layer 12 is, and the deeper the depth of diffusion from the surface of the N-type epitaxial layer 2 is, the better the ESD strength can be increased. For example, in the case of HBM (human body model), in order to obtain an ESD strength of 2 kV or more, it is appropriate that the concentration of the N-type diffusion layer is 1xc3x971016/cm3 or more and the depth is 1.5 xcexcm or more.
As described above, in the insulated gate field effect transistor, for the purpose of making the high withstand voltage compatible with the high ESD strength, it is impossible to avoid the increase in the step corresponding to one masking process. In addition, a potential (herein referred to as xe2x80x9cbody potentialxe2x80x9d to be distinguished from a potential of the P-type semiconductor substrate) of a region of this element where a channel is formed becomes the same as a potential of the P-type semiconductor substrate that is the lowest potential on the circuit. Therefore, an application to a multi-system power source IC including a charge pump circuit having a circuit structure in which the element has a body potential different from the lowest potential on the circuit is difficult.
Then, for the purpose of solving such a problem inherent in the prior art, an object of the present invention is to make the high withstand voltage and high ESD strength of an insulated gate field effect transistor compatible with each other without using a protective element and without increasing steps, thereby realizing an element structure in which a body potential of the element can be freely changed.
In order to solve the above problem, according to the present invention, there is provided an insulated gate N-channel field effect transistor, comprising:
a source region and a drain region, each having an N-type and high concentration, formed on an N-type epitaxial layer formed on a P-type semiconductor substrate with an interval;
a channel forming region between the source region and the drain region;
a gate electrode formed through the channel forming region and a gate insulating film;
an N-type low concentration region formed between the drain region and the channel forming region;
an insulating film formed on the low concentration region and thicker than the gate insulating film;
a P-type well layer in a region including the source region, the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region
an N-type buried layer formed in a region, which is a boundary between the semiconductor substrate and the epitaxial layer, including the source region, the drain region, the channel forming region, and a region under the insulating film thicker than the gate insulating film; and
a P-type buried layer including the source region, the drain region, the channel forming region, and a region under the insulating film thicker than the gate insulating film, the P-type buried layer being contained within the N-type buried layer as viewed from above and being formed beyond the upper and lower sides of the N-type buried layer in its depth direction, the upper portion of the P-type buried layer having a width extending to the P-type well layer from the upper side of the N-type buried layer.
The insulated gate N-channel field effect transistor set forth in the above, further comprises:
an N-type low concentration region formed between the drain region and the channel forming region;
an insulating film formed on the low concentration region and is thicker than the gate insulating film;
an N-type low concentration region formed between the source region and the channel forming region;
an insulating film formed on the low concentration region and is thicker than the gate insulating film; and
a P-type well layer in a region including the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region and the source region.


A near-field light generator plate 36 of the present invention is arranged to face a medium 10, and one portion 36b and other portion 36a in a medium-facing surface S thereof are made of their respective electroconductive materials different from each other. Since the one portion and the other portion in the medium-facing surface are made of the electroconductive materials different from each other, this medium-facing surface is formed by a surface removing step such as polishing or etching from the medium-facing surface side so that a difference between heights of the one portion and the other portion is readily made based on the difference of the materials.

1. Field of the Invention
The present invention relates to a near-field light generator plate, a thermally assisted magnetic head for writing of signals by thermally assisted magnetic recording, a head gimbal assembly (HGA) with this thermally assisted magnetic head, and a hard disk drive with this HGA.
2. Related Background Art
As the recording density of the hard disk drive increases, further improvement is demanded in the performance of the thin film magnetic head. In order to increase the recording density, a recording medium is made of a magnetic material with large KU and the so-called thermally assisted magnetic recording is proposed as a method of applying heat to the recording medium right before application of a writing magnetic field to lower the coercivity of the magnetic material, and then performing writing.
As examples of such thermally-assisted magnetic head recording apparatus, Japanese Patent Application Laid-Open No. 2001-255254 and Japanese Patent Application Laid-Open No. 2003-114184 and T. Matsumoto et al., Near-Field Optical Probe with A Beaked Metallic Plate for Thermally Assisted Magnetic Recording, pp. 6-7, MORIS2006 WORKSHOP Technical Digest, Jun. 6-8, 2003 disclose the thermally-assisted magnetic heads in which an electroconductive near-field light generator plate of a plate shape is disposed on a medium-facing surface and in which light is guided onto the near-field light generator plate from the back side to generate near-field light. Particularly, Japanese Patent Application Laid-Open No. 2003-114184 and T. Matsumoto et al., Near-Field Optical Probe with A Beaked Metallic Plate for Thermally Assisted Magnetic Recording, pp. 6-7, MORIS2006 WORKSHOP Technical Digest, Jun. 6-8, 2003 disclose the structure in which a part of the near-field light generator plate is projected toward the medium, and it is considered that in this structure the near-field light is selectively radiated at high intensity from the projected part toward the medium.

Near-field light generator plate, thermally assisted magnetic head, head gimbal assembly, and hard disk drive


A container spout assembly including a neck member and a spout member is shown. The spout member is recessed into the container and held in the neck member by a flange. On extension an in-turned cuff on the neck member forms a space into which extends an out-turned cuff member of the spout member. The spout member is held in place so that a fluid can be poured from the container with the benefit of the spout member. The spout member can also be retracted if the container is to be used more than once.

In general, there are various containers which are known to dispense fluids. Specifically, U.S. Pat. Nos. 4,650,096 and 5,230,442 disclose containers having spouts which are used to dispense fluids.
There exists a need for a container spout assembly which improves upon the prior art and provides for a spout and container assembly adaptable for use with the containers employed by today's manufacturers. The container and spout assembly of the present invention provides a container spout assembly that is easy to use and is easily incorporated into the design of existing containers. In addition, the present invention provides a low cost container and spout assembly that is easily filled during the production process.


An electrically and mechanically modular design of a high impedance, passive transceiver is disclosed for use in distributed, serial transmission systems to provide half uplex interfacing to multiple users with minimum loading and reflection. The transceiver is selectively operable in either of two modes: a receive mode for receiving low-level serial, bi-phase (3 state) Manchester coded signals and transmitting (2 wire, 2 state) signals at transistor-transistor logic (TTL) levels; and a transmit mode for receiving (2 wire, 2 state) signals at TTL levels and transmitting the low-level, serial bi-phase, (3 state) signals on the bus.

The present invention relates to distributed transmission systems and more specifically to an electrically and mechanically modular transceiver design for passively coupling a maximum number of users to the transmission line. For any given distributed transmission system having the requirement of minimizing point-to-point wiring while maintaining optimum data communications between an optimum number of geographically and functionally distinct users, it is necessary to make numerous passive connections or taps to the transmission line. As the number of taps and users increase however, there are associated problems with loading and reflections on the transmission line which affect the integrity of the data and control information being transmitted and received over the line.
The present invention accommodates these requirements in a high impedance transceiver and combination transceiver design that maintains the integrity of the transmission line and acts as a fanout point to the associated input/output ports to the various users.

High impedance, Manchester (3 state) to TTL (2 wire, 2 state) transceiver for tapped bus transmission systems