An MPEG downdecoder is to be provided which eliminates dephasing of pixels of moving picture data without losing properties inherent in a picture obtained on interlaced scanning. In the case of a field DCT mode, 4xc3x974 decimating IDCT is executed for phase correction for a xc2xc pixel for pixels in the vertical direction of a top field and for phase correction for xc2xe pixel for pixels in the vertical direction of a bottom field. In the case of a frame DCT mode, the totality of coefficients of a DCT block are IDCTed and separated into two pixel blocks associated with interlaced scanning. The low-frequency components of these two pixel blocks are IDCTed to synthesize the two pixel blocks. The pixels in the vertical direction of the top field are phase-corrected by a xc2xc pixel, while those in the vertical direction of the bottom field are phase-corrected by a xc2xe pixel.

1. Field of the Invention
This invention relates to a picture decoding method and apparatus for decoding compressed picture data of a first resolution obtained on predictive coding by motion prediction in terms of a pre-set pixel block (macro-block) as a unit and on performing orthogonally-transform in terms of a pre-set pixel block (orthogonal transform block) as a unit. More particularly, it relates to a picture decoding method and apparatus for decoding compressed picture data of the first resolution and for decimating the data to moving picture data of a second resolution lower than the first resolution.
2. Description of the Related Art
There is now going on the standardization of digital television signals employing the picture compression system, such as Moving Picture Experts Group Phase 2 (MPEG2). Among the standards for digital television broadcast, there are a standard for standard resolution pictures, such as those with the number of effective lines in the vertical direction of 576, and a standard for high-resolution pictures, such as those with the number of effective lines in the vertical direction of 1152. Recently, there is raised a demand for a downdecoder for decoding compressed picture data of a high-resolution picture and for reducing the resolution of the compressed picture data by xc2xd to generate picture data of the picture data of standard resolution to display the picture data on a television monitor adapted to cope with the standard resolution.
There is proposed in a publication entitled xe2x80x9cScalable Decoder free of low-range Driftxe2x80x9d (written by Iwahashi, Kanbayashi and Takaya, Shingaku-Gihou CS94-186, DSP 94-108, 1995-01) a downdecoder for decoding a bitstream of, for example, MPEG2, obtained on predictive coding with motion prediction of a high-resolution picture and compression coding by discrete cosine transform, and for downsampling the picture to a picture of standard resolution. This Publication, referred to below as Publication 1, shows the following first to third downdecoders.
Referring to FIG. 1, this first downdecoder includes an inverse discrete cosine transform unit 1001, for processing a bitstream of a high resolution picture with 8 (number of coefficients as counted from the dc component in the horizontal direction) xc3x978 (number of coefficients as counted from the dc component in the vertical direction), an adder 1002 for adding a discrete cosine transformed high resolution picture and a motion-compensated reference picture, and a frame memory 1003 for transient storage of the reference picture. The first downdecoder also includes a motion compensation unit 1004 for motion-compensating the reference picture stored in the frame memory 1003 with xc2xd pixel precision, and a downsampling unit 1005 for converting the reference picture stored in the frame memory 1003 to a picture of standard resolution.
This first downdecoder reduces an output picture, obtained on decoding as a high resolution picture by inverse discrete cosine transform, by the downsampling unit 1005, to output resulting picture data with the standard resolution.
Referring to FIG. 2, the second downdecoder includes an inverse discrete cosine transform unit 1011 for performing 8xc3x978 inverse discrete cosine transform, as it substitutes 0 for the high-frequency components of the discrete cosine transform (DCT) block of the high resolution picture, an adder 1012 for summing the discrete cosine transformed high resolution picture to the motion-compensated reference picture, and a frame memory 1013 for transient storage of the reference picture. The second downdecoder also includes a motion compensation unit 1014 for motion-compensating the reference picture stored in the frame memory 1013 with xc2xd pixel precision, and a downsampling unit 1015 for converting the reference picture stored in the frame memory 1013 to a picture of standard resolution.
This second downdecoder performs inverse discrete cosine transform to obtain a decoded output picture, as a high-resolution picture, as it substitutes 0 for coefficients of high-frequency components among the totality of coefficients of the DCT block, and reduces the output picture in size by the downsampling unit 1015 to output picture data of standard resolution.
Referring to FIG. 3, a third downdecoder includes a decimating inverse discrete cosine transform unit 102 for doing e.g., 4xc3x974 inverse discrete cosine transform, using only the coefficients of the low-frequency components of the DCT block of the bitstream of the high resolution picture, for decoding to a standard resolution picture, and an adder 1022 for suiting the standard resolution picture processed with decimating inverse discrete cosine transform and the motion-compensated reference picture. The third downdecoder also includes a frame memory 1023 for transiently storing the reference picture and a motion compensation unit 1024 for motion-compensating the reference picture stored by the frame memory 1023 with a xc2xc pixel precision.
In this third downdecoder, IDCT is executed using only low-frequency components of all coefficients of the DCT block to decode a picture of low resolution from a picture of high resolution.
The above-described first downdecoder performs inverse discrete cosine transform on the totality of the coefficients in the DCT block to obtain a high-resolution picture on decoding. Thus, the inverse discrete cosine transform unit 1001 of high processing capability and the frame memory 1003 of high capacity are needed. The second downdecoder performs discrete cosine transform on the coefficients in the DCT block to obtain a high-resolution picture on decoding, as it sets the high-frequency components of the coefficients to zero, so that a lower processing capacity of the inverse discrete cosine transform unit 1011 suffices. However, the frame memory 1003 of high capacity is yet needed. In contradistinction from these first and second downdecoders, the third downdecoder performs inverse discrete cosine transform on the totality of the coefficients in the DCT block, using only coefficients of the low-frequency components of the coefficients in the DCT block, so that a low processing capability of an inverse discrete cosine transform unit 1021 suffices. Moreover, since the reference picture of the standard resolution picture is decoded, a lower capacity of the frame memory 1023 suffices.
Meanwhile, the display system of a moving picture in television broadcast is classified into a sequential scanning system and an interlaced scanning system. The sequential scanning system sequentially displays a picture obtained on sampling the totality of pictures in a given frame at the same timing. The interlaced scanning system alternately displays pictures obtained on sampling pixels in a given frame at different timings from one horizontal line to another.
In this interlaced scanning system, one of the pictures obtained on sampling pixels in a frame at different timings from one horizontal line to another is termed a top field or a first field, with the other picture being termed a bottom field or a second field. The picture containing the leading line in the horizontal direction of a frame becomes the top field, while the picture containing the second line in the horizontal direction of a frame becomes the bottom field. Thus, in the interlaced scanning system, a sole frame is made up of two fields.
With the MPEG2, not only a frame but also a field can be allocated to a picture as a picture compressing unit in order to compress the moving picture signals efficiently in the interlaced scanning system.
If, in the MPEG2, a field is allocated to a picture, the resulting bitstream structure is termed a field structure, while if a frame is allocated to a picture, the resulting bitstream structure is termed a frame structure. In the field structure, a DCT block is constituted by pixels in the field and discrete cosine transform is applied on the field basis. The processing mode of performing field-based discrete cosine transform is termed the field DCT mode. In the frame structure, a DCT block is constituted by pixels in the frame and discrete cosine transform is applied on the frame basis. The processing mode of performing field-based discrete cosine transform is termed the frame DCT mode. In the field structure, a macro-block is constituted from pixels in a field and motion prediction is performed on the field basis. The processing mode of performing motion prediction on the field basis is termed the field motion prediction mode. In the frame structure, a macro-block is constituted from pixels in a frame and motion prediction is performed on the frame basis. The processing mode of performing motion prediction on the frame basis is termed the frame motion prediction mode.
Meanwhile, a picture decoding apparatus, adapted for decoding compressed picture data for the interlaced scanning system, using the third downdecoder shown in the Publication 1, is proposed in, for example, a Publication entitled in xe2x80x9cA Compensation Method of Drift Errors in Scalabilityxe2x80x9d written by N. Obikane, K. Tahara and J. Yonemitsu, HDTV Work Shop ""93. This Publication is hereinafter termed the Publication 2.
Referring to FIG. 4, the conventional picture decoding device, shown in Publication 2, includes a bitstream analyzer 1031, fed with a bitstream obtained on compressing a high resolution picture in accordance with the MPEG2, for analyzing this bitstream, a variable length encoding/decoding unit 1032 for variable length encoding data for allocating codes of lengths corresponding to the data occurrence frequency and for decoding the variable length encoded bitstream, and a dequantizer 1033 for multiplying the respective coefficients of the DCT block with quantization steps. The conventional picture decoding device also includes a decimating inverse discrete cosine transform unit 1034 for decoding a standard resolution picture by e.g., 4xc3x974 inverse discrete cosine transform using only coefficients of low-frequency components of the totality of the coefficients of the DCT block, and an adder 1035 for summing the standard resolution picture processed with decimating inverse discrete cosine transform to a motion-compensated reference picture. The conventional picture decoding device also includes a frame memory 1036 for transiently storing the reference picture and a motion compensation unit 1037 for motion compensating the reference picture stored in the frame memory 1036 to a xc2xc pixel precision.
The decimating inverse discrete cosine transform unit 1034 of the conventional picture decoding device, shown in the Publication 2, performs the inverse discrete cosine transform, using only the coefficients of the low-frequency components of the totality of the coefficients in the DCT block. It is noted that the positions of the coefficients of the frame DCT mode, processed with the inverse discrete cosine transform, differ from those of the field DCT mode.
Specifically, in the field DCT mode, the decimating inverse discrete cosine transform 1034 applies the inverse discrete cosine transform only on the 4xc3x974 of 8xc3x978 coefficients in the DCT block, as shown in FIG. 5. On the other hand, in the frame DCT mode, the decimating inverse discrete cosine transform 1034 applies the inverse discrete cosine transform only on the 4xc3x972+4xc3x972 of 8xc3x978 coefficients in the DCT block, as shown in FIG. 6.
Also, the motion compensation unit 1037 of the conventional picture decoding device performs motion compensation to xc2xc pixel precision, adapted to cope with the field motion prediction mode or with the frame motion prediction mode, based on the information (motion vector) on the motion prediction performed on the high resolution picture. Specifically, while the MPEG2 usually provides that the motion compensation be preformed to xc2xd pixel precision, the number of pixels in a picture is thinned out to one-half if a standard resolution picture is to be decoded from a high resolution picture. Thus, the motion compensation unit 1037 performs motion compensation as it sets the pixel precision for motion compensation to xc2xc pixel.
Therefore, the motion compensation device 1037 performs linear interpolation on the pixels of the reference picture stored in the frame memory 1036 as a standard resolution picture to generate pixels to a xc2xc pixel accuracy.
Specifically, the processing for linear interpolation of pixels in the perpendicular direction for the field motion prediction mode and that for the frame motion prediction mode are explained with reference to FIGS. 7 and 8, in which the phase of pixels in the vertical direction is indicated in the perpendicular direction, with the phase of each pixel in a displayed picture being indicated by an integer.
Referring to FIG. 7, the processing for interpolation of a picture motion-predicted in the field motion prediction mode is explained. For a high resolution picture (upper layer), motion compensation is independently preformed to a xc2xd pixel precision, from field to field, as shown in FIG. 7A. On the other hand, for a standard resolution picture (lower layer), motion compensation is achieved by generating pixels dephased by xc2xc, xc2xd and xc2xe pixel in the perpendicular direction by linear interpolation in a field based on the pixel of an integer number precision, as shown in FIG. 7B. That is, in the standard resolution picture (lower layer), pixels with xc2xc pixel precision of the top field are generated by linear interpolation based on the pixels of the integer number precision of the top field, while those with xc2xc pixel precision of the bottom field are generated by linear interpolation based on the pixels of the integer number precision of the bottom field. It is assumed for example that the value of a pixel of the top field, having the phase in the perpendicular direction at the 0-position, is a, with the value of a pixel having the phase in the perpendicular direction at the 1-position is b. In this case, the pixel of the top field with the phase in the perpendicular direction of xc2xc is (3a+b)/4, while the pixel of the top field with the phase in the perpendicular direction of xc2xd is (a+b)/2, with the pixel of the top field with the phase in the perpendicular direction of xc2xe being (a+3b)/4.
Referring to FIG. 8, the processing of interpolation of a picture motion-predicted in the frame motion prediction mode is explained. For a high resolution picture (upper layer), interpolation processing is performed across the fields, that is across the bottom field and the top field, as shown in FIG. 8A, with the motion compensation precision being xc2xd pixel precision. For a standard resolution picture (lower layer), motion compensation is achieved by generating pixels dephased by xc2xc, xc2xd and xc2xe pixels in the perpendicular direction, based on the pixels of the integer number precision of two fields, that is the top field and the bottom field, as shown in FIG. 8B. For example, it is assumed that the value of a pixel of the bottom field having the phase in the perpendicular direction of xe2x88x921 is a, the value of a pixel of the top field having the phase in the perpendicular direction of 0 is b, the value of a pixel of the bottom field having the phase in the perpendicular direction of 1 is c, the value of a pixel of the top field having the phase in the perpendicular direction of 2 is d, and a pixel of the top field having the phase in the perpendicular direction of 3 is e. In this case, the pixels of xc2xc pixel precision, having the phase in the perpendicular direction in a range from 0 and 2, may be found as follows:
The pixel having the phase in the perpendicular direction of xc2xc is (a+4b+3c)/8, while the pixel having the phase in the perpendicular direction of xc2xd is (a+3c)/4. The pixel having the phase in the perpendicular direction of xc2xe is (a+2b+3c+2d)/8, while the pixel having the phase in the perpendicular direction of {fraction (5/4)} is (2b+3c+2d+e )/8. The pixel having the phase in the perpendicular direction of {fraction (3/2)} is (3c+e)/4, while the pixel having the phase in the perpendicular direction of {fraction (7/4)} is (3c+4d+e)/8.
With the above-described picture decoding device, disclosed in the Publication 2, the compressed picture data of the high resolution picture, associated with the interlaced scanning system, can be decoded to standard resolution picture.
However, with the conventional picture decoding device, shown in the above Publication 2, the pixels of the standard resolution picture obtained with the field DCT mode are dephased with respect to the pixels of the standard resolution obtained with the frame DCT mode. Specifically, with the field DCT mode, the phases of the pixels in the perpendicular direction of the respective pixels of the top field of the lower layer are xc2xd, {fraction (5/2)}, . . . , with the phases in the perpendicular direction of the respective pixels of the bottom field of the lower layer being 1, 3, . . . , as shown in FIG. 9. On the other hand, with the field DCT mode, the phases of the pixels in the perpendicular direction of the respective pixels of the top field of the lower layer are 0, 2, . . . , with the phases in the perpendicular direction of the respective pixels of the bottom field of the lower layer being 1, 3, . . . , as shown in FIG. 10. Thus, the pictures with different phases co-exist in the frame memory 1036, thus deteriorating the picture quality of the output picture.
With the conventional picture decoding device, shown in the Publication 2, correction is not made of phase deviations or dephasing of the pixels at the time of the motion compensation with the field motion prediction mode and the frame motion prediction mode resulting in the deteriorated picture quality.
It is therefore an object of the present invention to provide a picture decoding method and a picture decoding device for decoding standard resolution picture data from compressed picture data of the high resolution picture whereby phase deviations of pixels of output moving picture data may be eliminated without detracting from characteristics proper to a picture obtained on interlaced scanning.
In one aspect, the present invention provides a picture decoding apparatus for decoding moving picture data of a second resolution from compressed picture data of a first resolution, obtained on predictive coding by motion prediction in terms of a pre-set pixel block (macro-block) as a unit and on compression coding in terms of a pre-set pixel block (orthogonal transform block) as a unit, the second resolution being lower than the first resolution. The picture decoding apparatus includes first inverse orthogonal transform means for inverse orthogonal transforming an orthogonal transform block of the compressed picture data, orthogonal transformed by an orthogonal transform system (field orthogonal transform mode) associated with the interlaced scanning, second inverse orthogonal transform means for inverse orthogonal transforming an orthogonal transform block of the compressed picture data, orthogonal transformed in accordance with an orthogonal transform system (frame orthogonal transform mode) associated with the sequential scanning, addition means for summing the compressed picture data, inverse orthogonal transformed by the first inverse orthogonal transform means or the second inverse orthogonal transform means, to motion compensated reference picture data to output moving picture data of the second resolution, memory means for storing moving picture data outputted by the addition means as reference picture data, and motion compensation means for motion compensating the macro-block of the reference picture data stored in the memory means. The first inverse orthogonal transform means inverse orthogonal transforms coefficients of low-frequency components of respective coefficients of the orthogonal transform block and corrects the phase of a xc2xc pixel for the vertical direction of respective pixels of the top field obtained on inverse orthogonal transform, the first inverse orthogonal transform means correcting the phase of a xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform. The second inverse orthogonal transform means inverse orthogonal transforms the coefficients of the totality of the frequency components of the orthogonal transform block, separates the inverse orthogonal transformed block into two pixel blocks associated with the interlaced scanning, inverse orthogonal transforms low-frequency components of the coefficients of the two orthogonal transformed pixel blocks, corrects the phase of xc2xc pixel for the vertical direction of respective pixels of the top field obtained on inverse orthogonal transform, corrects the phase of xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform, and synthesizes the phase-corrected top and bottom fields.
In this picture decoding device, the coefficients of the totality of the frequency components of the orthogonal transform block are inverse orthogonal transformed, the inverse orthogonal transformed block are separated into two pixel blocks associated with the interlaced scanning, low-frequency components of the coefficients of the two orthogonal transformed pixel blocks are inverse orthogonal transformed, the phase of xc2xc pixel for the vertical direction of respective pixels of the top field obtained on inverse orthogonal transform is corrected, the phase of xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform is corrected, and the phase-corrected top and bottom fields are synthesized.
With the picture decoding device of the present invention, the motion compensation means includes first motion compensation means for motion compensating a macro-block of reference picture data motion-predicted in accordance with a motion prediction system associated with interlaced scanning (field motion prediction mode), and second motion compensation means for motion compensating a macro-block of reference picture data motion-predicted in accordance with a motion prediction system associated with sequential scanning (frame motion prediction mode). The first motion compensation means and the second motion compensation means interpolate respective pixels of the macro-block of reference picture data stored in the memory means to generate a macro-block constituted by pixels of the xc2xc pixel precision for the reference picture data stored in the memory means to execute motion compensation on the generated macro-block.
The present picture decoding device interpolates the pixels of the macro-block od stored reference picture data to generate a macro-block constructed by pixels of the xc2xc pixel precision.
In the present picture decoding device, the first and second motion compensation means switch the number of taps of a filter used for interpolating respective pixels of a macro-block of reference picture data stored in the memory means, every pre-set unit, to generate a macro-block constructed by pixels of xc2xc pixel precision for reference picture data stored in the memory means.
In the present picture decoding device, the number of tapes of a filter is switched to interpolate respective pixels of a macro-block of stored reference picture data to generate a macro-block constructed from pixels of xc2xc pixel precision.
In the present picture decoding device, the second motion compensation means interpolate respective pixels of the macro-block of reference picture data stored in the memory means between top and bottom fields to generate a macro-block constructed by pixels of xc2xc pixel precision for reference picture data stored in the memory means.
In the present picture decoding device, respective pixels of the macro-block of reference picture data orthogonal transformed by the frame orthogonal transform mode are interpolated between top and bottom fields to generate a macro-block constructed by pixels of xc2xc pixel precision.
In another aspect, the present invention provides a picture decoding method for decoding moving picture data of a second resolution from compressed picture data of a first resolution, obtained on predictive coding by motion prediction in terms of a pre-set pixel block (macro-block) as a unit and on compression coding in terms of a pre-set pixel block (orthogonal transform block) as a unit, the second resolution being lower than the first resolution. The picture decoding method includes inverse orthogonal transforming an orthogonal transform block of the compressed picture data, orthogonal transformed in accordance with an orthogonal transform system (field orthogonal transform mode) associated with the interlaced scanning, inverse orthogonal transforming an orthogonal transform block of the compressed picture data, orthogonal transformed in accordance with an orthogonal transform system (frame orthogonal transform mode) associated with the sequential scanning, summing the inverse orthogonal transformed compressed picture data to motion compensated reference picture data, storing moving picture data, obtained on summation, as reference picture data, motion compensating a macro-block of stored reference picture data, inverse orthogonal transforming coefficients of low-frequency components of respective coefficients of an orthogonal transform block orthogonal transformed in accordance with the field orthogonal transform mode, correcting the phase of a xc2xc pixel for the vertical direction of respective pixels of the top field obtained on orthogonal transform, correcting the phase of a xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform, inverse orthogonal transforming coefficients of the totality of frequency components of an orthogonal transform block in accordance with a frame orthogonal transform mode, separating the inverse orthogonal transformed orthogonal transform block into two pixel blocks associated with interlaced scanning, orthogonal transforming the separated two pixel blocks, inverse orthogonal transforming coefficients of the low-frequency components of respective coefficients of the two orthogonal transformed blocks, correcting the phase of a xc2xc pixel for the vertical direction of respective pixels of the top field obtained on inverse orthogonal transform, correcting the phase of a xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform, and synthesizing the phase-corrected top and bottom fields.
According to the present invention, an orthogonal transform block of the compressed picture data, orthogonal transformed in accordance with an orthogonal transform system (field orthogonal transform mode) associated with the interlaced scanning, is inverse orthogonal transformed, an orthogonal transform block of the compressed picture data, orthogonal transformed in accordance with an orthogonal transform system (frame orthogonal transform mode) associated with the sequential scanning, is inverse orthogonal transformed, and the inverse orthogonal transformed compressed picture data is summed to motion compensated reference picture data. The moving picture data, obtained on summation, are stored as reference picture data, a macro-block of stored reference picture data is motion compensated and coefficients of low-frequency components of respective coefficients of an orthogonal transform block orthogonal transformed in accordance with the field orthogonal transform mode are inverse orthogonal transformed. The phase of a xc2xc pixel for the vertical direction of respective pixels of the top field obtained on orthogonal transform is corrected, and the phase of a xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform is corrected. The coefficients of the totality of frequency components of an orthogonal transform block are inverse orthogonal transformed in accordance with a frame orthogonal transform mode. The inverse orthogonal transformed orthogonal transform block is separated into two pixel blocks associated with interlaced scanning. The separated two pixel blocks are respectively orthogonal transformed, and coefficients of the low-frequency components of respective coefficients of the two orthogonal transformed blocks are inverse orthogonal transformed, and the phase of a xc2xc pixel for the vertical direction of respective pixels of the top field obtained on inverse orthogonal transform is corrected, while the phase of a xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform is also corrected, and synthesizing the phase-corrected top and bottom fields. The present picture decoding device outputs moving picture data of a second resolution lower than a first resolution.
Thus, in accordance with the present invention, the processing volume necessary for decoding can be reduced, while dephasing of pixels of output moving picture data of the second resolution can be eliminated without impairing the characteristics proper to the interlaced picture. That is, output moving picture data can be displayed without filtering. In addition, the moving picture data of the second resolution can be improved in quality.
In the present picture decoding device, coefficients of the totality of frequency components of two orthogonal transform blocks in accordance with a frame orthogonal transform mode are inverse orthogonal transformed, and the inverse orthogonal transformed orthogonal transform blocks are separated into two pixel blocks associated with interlaced scanning. The separated two pixel blocks are orthogonal transformed, and the coefficients of the low-frequency components of respective coefficients of the two orthogonal transformed blocks are inverse orthogonal transformed. The phase of a xc2xc pixel for the vertical direction of respective pixels of the top field obtained on inverse orthogonal transform is corrected, while the phase of a xc2xe pixel for the vertical direction of respective pixels of the bottom field obtained on inverse orthogonal transform is also corrected, and the phase-corrected top and bottom fields are synthesized.
Thus, in accordance with the present invention, the processing volume necessary for decoding can be reduced, while dephasing of pixels of output moving picture data of the second resolution can be eliminated without impairing picture characteristics proper to the interlaced picture. Specifically, output moving picture data can be displayed without filtering. In addition, the moving picture data of the second resolution can be improved in quality.
In the present invention, pixels of a macro-block of stored reference picture data are interpolated to generate a macro-block constructed by pixels of xc2xc pixel precision.
Thus, according to the present invention, dephasing of pixels between the field motion prediction mode and the frame motion prediction mode is eliminated to prevent deterioration of the picture quality ascribable to motion compensation.
According to the present invention, the number of filter taps can be switched to interpolate the pixels of the macro-block of the stored reference picture data to generate a macro-block constructed by pixels of xc2xc pixel precision.
Thus, according to the present invention, the processing volume at the time of motion compensation can be reduced without deteriorating the picture quality to expedite the processing.
According to the present invention, the respective pixels of the macro-block of reference picture data orthogonal transformed by the frame orthogonal transform mode can be interpolated between the top and bottom fields to generate a macro-block constructed by pixels of the xc2xc pixel precision.
In this manner, it is possible with the present invention to prevent deterioration of the picture quality ascribable to motion compensation.


One aspect of the present invention is to provide a Connectivity Management (CM) function for use in networks such as a wireless network. The CM function can support both User Equipment (UE) and Machine Type Communication (MTC) devices in the network. In one embodiment of the first aspect, there is provided methods and systems for CM for a plurality of different types of devices that may evaluate tracking criteria to determine where and when wireless resources will need to be allocated to a wireless device. In some embodiments, these tracking criteria include location tracking and/or activity tracking. Another aspect provides for the instantiation of virtual CM functions established at appropriate physical nodes to provide device specific or service specific CM.

Wireless communications networks (WCNs) have undergone several generations of Radio Access Network (RAN) technologies, including so called second generation (2G), third generation (3G) and fourth generation (4G) access technologies. So called fifth generation (5G) RAN technologies are being proposed to various wireless standards groups. In addition to RAN technologies, wireless local area networks (e.g., Wi-Fi based on the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standards) have been developed.
Current WCNs, such as those based on Long-Term Evolution (LTE) standards specified by the Third Generation Partnership Project (3GPP), provide data connectivity to user equipment (UE). These networks have been designed to provide connectivity services to User Equipment (UE) (e.g., mobile phones, smart phones, laptops, tablets, computers, and other user devices). Because not all UEs served by the network are simultaneously active, WCNs are designed to allocate wireless resources to devices as needed. Typically, more resources are allocated to devices in an active state. A device is considered to be in an active state if it is transmitting data, receiving data, or preparing to do so. UEs are configured to enter an idle state while not actively transmitting to both conserve battery power and to reduce the demand on the network.
3G/4G networks have focused on connection management based on a binary status of a UE as being in either an active or an idle state. The allocation of resources to serve UEs is based on these two states for a connected device. Mobile networks, such as those following LTE standards, have been designed to support UE mobility. The assumption in the design of the network is that all UEs can move, either when active or when idle. Because it is important that network entities be able to reach connected UEs, the Mobility Management Entity (MME) has been responsible for connection management. The MME tracks the location of an active UE, with respect to the network topology, and assigns resources to the UE to facilitate both uplink and downlink communications. When a UE is in an IDLE state, the MME assigns a tracking area. When the UE determines that it has left the tracking area, it performs a tracking area update so that the MME can receive updated tracking information. Accordingly, the MME tracks UE location and activity in fairly coarse granularity.
Existing mobile networks have been used to support devices that are not intended to be mobile, such as meters and other sensors that form what is referred to as an "internet of things" (IoT). These devices have similar communication profiles to each other, but differ from many existing UEs. These devices, often referred to as machine-to-machine (M2M) device often generate infrequent small packet based traffic. The frequency with which an M2M device communicates with the network is often very predictable and in some situations it often scheduled. Although this communication profile, often referred to as Machine Type Communication (MTC), results in a small amount of traffic from a single device, an MTC device is rarely deployed as a single instance. Typically, a large number of M2M devices are deployed in a coordinated manner, resulting in a very large number of small messages being transmitted by the M2M devices. In an LTE network, all connected devices are provided the same tracking services, which typically allows a coarse tracking of the UE activity status (e.g. ACTIVE or IDLE) and a UE location (typically with respect to the topology of the network, with more precise location information stored for Active devices than for Idle devices).
As the number of devices connecting to networks increases, and as the needs and capabilities of these devices becomes more varied, a greater need for a more robust connection management system has arisen. Next generation networks could be better served by a connection management system that provided better granularity for both activity and location tracking, and provided different levels of resource allocation for different needs. There exists a need for better connection management for WCNs which provide communication services to both UE and MTC devices.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.

System and method for connectivity management


Novel structural configurations of a TFT-LCD (Thin Film Transistor Liquid Crystal Display) which results in both fast response to input data and provides wide-viewing-angles. The structure of the device is comprised of one pixel electrode layer and two common electrode layers. The structure of the invention can be used with liquid crystal display television (LCD-TV) monitors that require both fast-response as well as wide-viewing-angle. In addition, other liquid crystal technologies which require high speed response would benefit from the TFT-LCD of the present invention.

Slow response time and poor viewing angle of the conventional TFT-LCD are two of the major limitations for its otherwise potentially unlimited wide range of applications.
FIG. 1 shows the structure of a conventional TFT-LCD. A liquid crystal (LC) layer 10 is sandwiched between a top glass substrate 11 and a bottom glass substrate 12. A thin layer of transparent electrode, indium tin oxide (ITO), is coated on each substrate for the application of an electric field to switch the liquid crystals. Normally, the electrode 13 for the top substrate 11 is a common electrode, which has a constant voltage (e.g. 0V). 0V is used herein to mean low voltage. This common electrode is continuous and extends to all pixels in the whole display and hence is called a common electrode. On the other hand the electrode 14 on the bottom substrate 12 is called the pixel electrode since a transistor assigned to each individual pixel controls it. The voltage applied to the LC 10 is varied through this electrode. The electric field profile E is also shown in FIG. 1, when the pixel voltage is >0. As can be seen clearly there is only one type of electric field, a vertical field, for this device. This electric field is used to turn on the device by switching the liquid crystal molecules, which is a fast process. However, when we turn off the device, the pixel voltage is either removed or reduced such that the molecules gradually relax back to a lower state. With only one type of electric field generated, this results in a very slow relaxation and hence slow turn off time, and is a major limitation of liquid crystals for many potential applications today.
Discussed below are various relevant prior art references. The references are related to three key concepts used in the present invention: crossed-field effect, fringing field switching and multi-domain technology.
The concept of crossed-field effect first appeared in 1975 in an article by D. J. Channin, Applied Physics Letters', Vol. 26, No. 11, p. 603 (1975) and in a subsequent article by D. J. Channin and D. E Carlson, Applied Physics Letters', Vol. 28, No. 6 (1976). Six years later, an article was published by Akihiko Sugimura et al., Proceedings of 14th Conference on Solid State Devices, Tokyo (1982) and in 1985 Akihiko Sugimura and Takao Kawamura published another article in, Japanese Journal of Applied Physics, Vol. 24, No. 8, p. 905 (1985). The liquid crystal displays employing the crossed-field effect have various disadvantages, such as, high voltage requirement, low contrast, more complicated structure, non-uniform transmission, and more complicated driving. Driving refers to the electronic circuits used to supply (or drive) the required voltages (data or common) to the TFT-LCD. Some driving schemes are more complicated, e.g, requiring different types of voltage at different time intervals. In the crossed field effect, it normally requires the control of two types of electric field (both vertical and lateral) using extra electrodes and hence more complicated driving. The crossed-field effect concept has therefore not been used for TFT-LCDs since it tends to require much higher operation voltage, more complicated structure and driving and have lower contrast. The present invention however improves many of the above problems by using different electrode designs; thus, making the crossed-field effect possible for use in TFT-LCDs. Moreover, the use of the crossed-field effect in the present invention also provides the inherent wide-viewing-angle property, which is another very important requirement for TFT-LCD television sets (TVs).
Prior art research on fringing-field switching (FFS) has been published by Seung Ho Hong et al., Japanese Journal of Applied Physics, "Hybrid Aligned Fringing Field" Vol. 40, p.L272, (2001) and Seung Ho Hong et al., Japanese Journal, Applied Physics, Vol 41, pp. 4571-4576 (2001). The present invention adopts a structure that is very similar to the Fringing-Field-Switching FFS mode structure described by Seung Ho Hong et al. This mode was used for generating wide-viewing-angle using in-plane-switching with improved efficiency. By adopting this structure in the present invention, the required voltage can be reduced for generating the lateral or fringing field. The reduction in voltage is possible because the gap between electrodes for fringing field generation is small. Hence, the operating voltage is lowered. Moreover, the FFS structure can provide good uniform vertical field without a dead zone, which is defined as a gap between electrodes without an electric field. In the present invention, the gap between electrodes also has an electric field generated by a bottom substrate electrode configuration that consists of an electrode layer with gaps known as a discontinuous electrode separated from a continuous electrode layer by a electrical insulation layer. The segments of the discontinuous electrode are however all connected to the same transistor within a pixel. The bottom substrate electrode structure is similar to the structure of conventional FFS structure.
The present invention however has at least three important differences from the conventional FFS structure. First, the present invention has two common electrodes; whereas, the conventional FFS structure has only one common electrode of low voltage only. A recently reported FFS mode also used two common electrodes; however, in this case both common electrodes are of low voltage, e.g. 0V. In contrast, in the present invention, one common electrode is high voltage and one common electrode is low voltage. Second, the liquid crystal (LC) mode is different. Conventional FFS uses parallel alignment with in-plane-switching whereas the recently reported FFS mode with two common electrodes uses Hybrid-Aligned-Nematic (HAN). The present invention can use any liquid crystal mode and the wide-viewing-angle generation mechanism is also different compared with the FFS Prior Arts. Third, all prior art FFS structures have slow response time since they are not using the crossed-field effect and the turn-off process relies on natural relaxation of the LC molecules and is slow.
Further, prior art references relate to multi-domain technology LCDs. The present invention adopts a mechanism of forming wide-viewing-angle known as multi-domain. The present invention however has important differences from all the prior art using this technology since our invention uses FFS structure for generating the fringing field whereas other prior art references mainly use protrusions for generating multi-domains. See A. Takeda et al., SID '98, "MVA, Multi-Domain Vertical Alignment" p. 1077 (1998). An inter-digital structure for generating the fringing field to cause multi-domain was discussed by K. H. Kim et al., SID '98 p. 1085 (1998). Moreover, the present invention can use many different liquid crystal modes compared with mainly Vertical Alignment (VA) mode used in the prior art.
Thus, there is a need for improvement in today's thin-film transistor liquid crystal display (TFT-LCD) technology. It is desirable for crossed-field effect structures to have low operation voltage, high contrast, simple driving and easy fabrication. Faster response is desired for conventional structures using FFS or multi-domain LCDs.
The present invention affords a substantial improvement in the production and performance of TFT-LCDs. Different LC modes can be applied to this structure. Different LC modes can lead to different light efficiency, response time and viewing angle. The choice of the LC mode depends on the type of application.

High speed and wide viewing angle liquid crystal displays

University of Central Florida Research Foundation, Inc.


A semiconductor apparatus, includes a semiconductor substrate, a first wiring, a second wiring and a capacitance cell. The first wiring is provided in the semiconductor substrate. The second wiring is provided in the semiconductor substrate. The capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.

1. Field of the Invention
The present invention relates to a semiconductor apparatus and a semiconductor apparatus layout method. More particularly, the present invention relates to a semiconductor apparatus having a bypass capacitor and a layout method of a semiconductor apparatus having a bypass capacitor.
2. Description of the Related Art
A layout method using an automatic layout system is used in designing a semiconductor apparatus. Such a layout method is known in Japanese Laid Open Patent Application (JP-A-Heisei, 10-340959). In this known layout method, a hard macro is firstly arranged as shown in FIG. 1 (S101). At this time, a hard macro library 403 including a circuit connection information 401, a cell library 402, a terminal of a hard macro, a wiring inhibition and an external shape is inputted to an automatic layout system.
After the arrangement of the hard macro (S101), power supply wiring (S102), an automatic arrangement of a cell (S103) based on the circuit connection information, a schematic wiring (S104) and a detailed wiring process (S105) are carried out to then complete the layout. Japanese Laid Open Patent Application (JP-A-Heisei, 10-340959) also discloses a layout method which after the arrangement of the hard macro (S101), removes the terminal and the wiring within the hard macro and then generates a hard macro terminal.
In addition, in a semiconductor apparatus, there may be a case that a bypass capacitor is mounted between a power supply line and a ground line in order to suppress a noise. In this case, the bypass capacitor is manually arranged after the automatic layout. Thus, enormous labor is necessary for the arrangement of the bypass capacitor.
It is desirable to develop a method for arranging the bypass capacitor without requiring the enormous labor.
Also, a semiconductor apparatus having a bypass capacitor is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 10-284605). This known semiconductor apparatus having the bypass capacitor is provided with cell rows 101a, 101b and 101c, as shown in FIG. 2. The cell rows 101a, 101b include a feed through cell 102. The feed through cell 102 is also referred to as a width alignment cell. Its role is to align the widths of the cell rows 101a, 101b and 101c. Also, the feed through cell 102 is designed such that a wiring area can be reserved.
FIG. 3 shows a structure of the feed through cell 102. In FIG. 3, 103 denotes a silicon substrate. 104 denotes an inter-layer film formed on the silicon substrate 103. 105 denotes a first electrode formed on the inter-layer film 104. 106 denotes a second electrode which is formed on its dielectric film 107 so as to be located opposite to the first electrode 105 and constitutes a capacitance together with the first electrode 105 and the dielectric film 107. 108 denotes a first insulation oxide film formed on the second electrode 106. 109 denotes a second insulation oxide film formed on the first insulation oxide film 108. 110 denotes a power source wiring connected to the second electrode 106 through a contact hole 111 by using a first layer wiring. And, 112 denotes a ground wiring connected to the first electrode 105 through a contact hole 113 by using the first layer wiring.
The known semiconductor apparatus having the bypass capacitor uses the space between the first electrode 105 and the second electrode 106 as capacitance. The semiconductor apparatus is desirable which has the bypass capacitor in which the space is effectively used. At this time, it is further desirable that the bypass capacitor mounted in the semiconductor apparatus can have a structure for making an automatic design easy.
Japanese Laid Open Patent Application (JP-A-Heisei, 5-283615) discloses a power supply wiring of a semiconductor integrated circuit as described below. In order to effectively reduce a noise induced in a power supply of LSI, in the LSI having a Vcc power supply/GND wiring with two or more layers and two or more rows, one Vcc power supply wiring is arranged in an upper layer, and a GND wiring is arranged in a lower layer. In rows adjacent to each other, a Vcc power supply wiring is arranged in a lower layer, and a GND wiring is arranged in an upper layer.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-204766) discloses a method for designing a semiconductor integrated circuit as described below. This is a method for designing a semiconductor integrated circuit including a plurality of basic cells, a power supply line and a ground line placed over those basic cells, and a plurality of bypass capacitors electrically connected to the power supply line and the ground line. This carries out the layouts of the plurality of basic cells, the power supply line and the ground line, and after tentatively setting the sizes of the respective bypass capacitors and the arrangement intervals of the bypass capacitors, respectively places the respective bypass capacitors, in which the sizes and the arrangement intervals are tentatively set, in empty areas of the basic cells in accordance with the layout, and if obtaining the desirable arrangement of the bypass capacitors, determines its arrangement as the final arrangement, and on the other hand, if failing in the desirable arrangement of the bypass capacitors, repeats the procedure for again setting the sizes of the bypass capacitors and the arrangement intervals between them and again placing the respective bypass capacitors until obtaining the desirable arrangement of the bypass capacitors.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-233636) discloses a semiconductor integrated circuit as described below. A macro cell, which has a pad portion that is placed in an area around a chip and is intended to input and output a signal from or to an external portion of the chip, and a function area mounted in an entirely inner area of the chip except the pad portion and is configured so as to have at least a desirable function in advance, and an input/output buffer for sending to the function area a signal inputted to or outputted from the external portion of the chip through the pad portion are placed at any position within the function area.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor apparatus including a bypass capacitor having a structure that makes automatic design easy. Another object of the present invention is to provide a semiconductor apparatus having a bypass capacitor in which space is effectively used. Still another object of the present invention is to provide a layout method that can make a layout of a semiconductor apparatus having a bypass capacitor easy.
In order to achieve an aspect of the present invention, a semiconductor apparatus, includes: a semiconductor substrate; a first wiring provided in the semiconductor substrate; a second wiring provided in the semiconductor substrate; and a capacitance cell, and wherein the capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.
In this case, the capacitance cell is provided to overlap with the first and second wirings.
In order to achieve another aspect of the present invention, a semiconductor apparatus, includes: a semiconductor substrate; a function region provided in the semiconductor substrate, a predetermined function being performed in the function region; a first wiring provided in the semiconductor substrate; and a second wiring provided in the semiconductor substrate, and wherein the function region includes: a circuit cell having a circuit; and a capacitance cell, and wherein the capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring and the capacitance cell is arranged in a region where the circuit cell does not exist.
In this case, the capacitance cell occupies an entire portion other than the circuit cell of the function region.
Also in this case, the capacitance cell is arranged in a portion where the function region overlaps with the first and second wirings.
Further in this case, the capacitance cell is selected of a plurality of capacitance cells having different shapes with each other based on a shape of the circuit cell.
In this case, the bypass capacitor includes a first electrode section connected electronically to the first wiring, and the first electrode section is opposed to the second wiring.
Also in this case, the first electrode section includes two electrodes connected to the first wiring, and one electrode of the two electrodes is opposed to a surface in a side of the semiconductor substrate of surfaces of the second wiring, and the other electrode of the two electrodes is opposed to another surface in the other side of the semiconductor substrate of the surfaces of the second wiring.
Further in this case, the bypass capacitor further includes a second electrode electronically connected to the second wiring, and the second electrode is opposed to the first electrode.
In this case, the bypass capacitor further includes a third electrode connected to the first wiring, and the third electrode is opposed to the second electrode.
Also in this case, the function region is an I/O region, and the circuit cell is an I/O cell inputting a signal from an external portion of the semiconductor apparatus and outputting another signal to the external portion.
Further in this case, a portion opposed to the second wiring of the first electrode section extends in the same direction as an extending direction of the second wiring.
In this case, the bypass capacitor further includes a fourth electrode connected to the second wiring, and the fourth electrode is opposed to the first wiring.
Also in this case, a portion opposed to the first wiring of the fourth electrode extends in the same direction as an extending direction of the first wiring.
Further in this case, the bypass capacitor further includes: a first connection section connecting the first electrode section to the first wiring; and a second connection section connecting the fourth electrode to the second wiring, and wherein the first connection section extends in a depth direction of the semiconductor substrate from the first wiring, and wherein the second connection section extends in the depth direction of the semiconductor substrate from the second wiring, and wherein a third wiring passes between the first and second connection sections.
In this case, a first conductive type of a first semiconductor region is formed in a portion included in the function region of a surface portion of the semiconductor substrate, and wherein the bypass capacitor further includes a fifth electrode connected to the first wiring, and wherein the first semiconductor region is opposed to the fifth electrode.
Also in this case, a second conductive type of a second semiconductor region is formed in the portion included in the function region of the surface portion of the semiconductor substrate, the second conductive type being different from the first conductive type, and wherein the bypass capacitor further includes a sixth electrode connected to the second wiring, and wherein the second semiconductor region is opposed to the sixth electrode.
Further in this case, the first and second wirings extend in a first direction parallel to the surface portion, and wherein the first and second semiconductor regions in parallel are provided between the first and second wirings, and wherein the fifth electrode extends in a second direction which is normal to the first direction and is parallel to the surface portion from the first wiring to cross the second semiconductor region and a portion opposite to the first semiconductor region of the fifth electrode extends in the first direction.
In this case, the sixth electrode extends in a direction which is normal to the first direction and is parallel to the surface portion from the second wiring to cross the first semiconductor region and a portion opposite to the second semiconductor region of the sixth electrode extends in the first direction.
Also in this case, the function region is an inner primitive region, and the circuit cell is a basic cell indicating a region in which a predetermined circuit is mounted.
In order to achieve still another aspect of the present invention, a semiconductor apparatus layout method, includes: (a) arranging a first and second wirings on a semiconductor substrate; and (b) providing a capacitance cell, and wherein the capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.
In this case, the capacitance cell is provided to overlap with the first and second wirings.
In order to achieve yet still another aspect of the present invention, a semiconductor apparatus layout method, includes: (a) arranging a circuit cell in a function region provided in a semiconductor substrate, wherein the circuit cell is cell indicating a region in which a circuit is mounted; (b) arranging first and second wirings on the semiconductor substrate; and (c) arranging a capacitance cell in a region where the circuit cell does not exist of the function region, and wherein the capacitance cell is a cell indicating a region in which a bypass capacitor is mounted, the bypass capacitor being electronically connected to a power supply wiring and a grounded wiring.
In this case, the (c) includes arranging the capacitance cell to overlap with the first and second wirings.
Also in this case, the (c) includes arranging the capacitance cell in an entire region where the circuit cell does not exist.
Further in this case, the capacitance cell is selected of a plurality of capacitance cells having different shapes with each other based on a shape of the circuit cell.
In this case, the function region is an I/O region and the circuit is an I/O buffer.
Also in this case, the function region is an inner primitive region and the circuit cell is a basic cell indicating a region in which a predetermined circuit is mounted.
In order to achieve still another aspect of the present invention, a semiconductor apparatus layout method, includes: (d) arranging an I/O cell in an I/O region; (e) arranging a first capacitance cell in a portion where the I/O cell does not exist of the I/O region, wherein the first capacitance cell is a cell indicating a region in which a first bypass capacitance is mounted; (f) providing a power supply wiring and a grounded wiring, wherein the power supply wiring and the grounded wiring are electronically connected to the first bypass capacitance; (g) arranging a second capacitance cell in a region where an inner primitive region overlaps with the power supply wiring and the grounded wiring, wherein the second capacitance cell is a cell indicating a region in which a second bypass capacitance is mounted; (h) arranging a basic cell in the inner primitive region, wherein the basic cell is a cell indicating a region in which a predetermined circuit is mounted; and (i) arranging a third capacitance cell in a region where the basic cell and the second capacitance cell do not exist of the inner primitive region, wherein the third capacitance cell is a cell indicating a region in which a third bypass capacitance is mounted.
In order to achieve still another aspect of the present invention, a computer readable recording medium for recording a program for a process, includes: (a) arranging a first and second wirings on a semiconductor substrate; and (b) providing a capacitance cell, and wherein the capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.
In this case, the capacitance cell is provided to overlap with the first and second wirings.
In order to achieve yet still another aspect of the present invention, a computer readable recording medium for recording a program for a process, includes: (a) arranging a circuit cell in a function region provided in a semiconductor substrate, wherein the circuit cell is a cell indicating a region in which a circuit is mounted; (b) arranging first and second wirings on the semiconductor substrate; and (c) arranging a capacitance cell in a region where the circuit cell does not exist of the function region, and wherein the capacitance cell is a cell indicating a region in which a bypass capacitor is mounted, the bypass capacitor being electronically connected to a power supply wiring and a grounded wiring.
In this case, the (c) includes arranging the capacitance cell to overlap with the first and second wirings.
Also in this case, the (c) includes arranging the capacitance cell in an entire region where the circuit cell does not exist.
Further in this case, the capacitance cell is selected of a plurality of capacitance cells having different shapes with each other based on a shape of the circuit cell.
In order to achieve yet still another aspect of the present invention, a computer readable recording medium for recording a program for a process, includes: (d) arranging an I/O cell in an I/O region; (e) arranging a first capacitance cell in a portion where the I/O cell does not exist of the I/O region, wherein the first capacitance cell is a cell indicating a region in which a first bypass capacitance is mounted; (f) providing a power supply wiring and a grounded wiring, wherein the power supply wiring and the grounded wiring are electronically connected to the first bypass capacitance; (g) arranging a second capacitance cell in a region where an inner primitive region overlaps with the power supply wiring and the grounded wiring, wherein the second capacitance cell is a cell indicating a region in which a second bypass capacitance is mounted; (h) arranging a basic cell in the inner primitive region, wherein the basic cell is a cell indicating a region in which a predetermined circuit is mounted; and (i) arranging a third capacitance cell in a region where the basic cell and the second capacitance cell do not exist of the inner primitive region, wherein the third capacitance cell is a cell indicating a region in which a third bypass capacitance is mounted.

Semiconductor apparatus including bypass capacitor having structure for making automatic design easy, and semiconductor apparatus layout method


The present invention relates to a dehumidification system and method and, in particular, to a system and method for controlling the humidity of air in a process or location using a desiccant-coated fluid-air heat exchanger. The desiccant material adsorbs water at or above ambient temperatures during an adsorption cycle, and the resultant air stream is of a reduced humidity compared with the humidity of the supply air. The desiccant material may then be dried during a regeneration cycle through addition of heating fluid through the heat exchanger, driving water back into the vapor state with addition of latent energy of vaporization. The desiccant material may be cooled, during the adsorption cycle, through addition of cooling fluid through the heat exchanger to maintain the temperature within a range sufficient for water vapor to be removed from the stream of air.

It is well known that air conditioning systems must be designed to alter both the temperature and the humidity of supply air to achieve specified thermal conditions in a conditioned space. Typically, moisture vapour production within a conditioned space is modest, and so most of the latent thermal energy load on an conditioning system is incurred when reducing the humidity of supply (or fresh) air, to a specified range, rather than removing water vapour from recirculated air flow within the space.
In a building, for example, in addition to sensible heat that must be added or removed to maintain a specified internal building temperature, excess water vapour may also have to be removed from air entering the building to maintain a specified internal humidity range. Such sensible heat and humidity control typically forms part of an air-conditioning and ventilation system.
The typical specified range for ventilated air entering occupied buildings, which may include residential and commercial buildings and the like, lies in the range of 22° C. to 23° C., and relative humidity typically is in the range of 50% to 65%. This relative humidity corresponds to a range between 9.73 g and 13.4 g water per kilogram air (absolute humidity).
When outside conditions are hot and moist (for example, 33° C. and 90% relative humidity), humidity ratio is around 35.4 g of water per kilogram of air. If this air is transferred to a location and cooled to a lower specified temperature range by removal of sensible heat, the relative humidity may reach 100% as the air cools and condensation then occurs with further cooling. In this example, up to 20 g of water per kilogram of air must be removed in order to produce a specified relative humidity of 55% at 23° C., as the external air is cooled to the specified internal temperature.
There are various known techniques for dehumidifying air within a process or location. One method is by thermal condensation which involves drawing air across a cold surface. As the air cools and relative humidity reaches 100%, water vapour in the air condenses as liquid water droplets. For example, a fan may draw moist air over a condensing coil maintained at or less than 11° C. The condensing coil causes condensation of some of the water vapour in the air, leaving air at a maximum humidity ratio of 9.9 g/kg air. The air is then re-heated to a temperature suitable for supply to the conditioned space, for example to around 18° C.
However, this method requires large amounts of mechanical energy, usually converted from electrical energy. This mechanical energy is used to operate a reverse Rankine cycle heat pump that must provide refrigerant fluid cooled to temperatures at or below 11° C. in the condensing coil to achieve an absolute humidity of less than 9.9 g water per kilogram of air (corresponding to a specified relative humidity of around 50% at 22 C in the conditioned space). This method of cooling supply air results in a substantial sensible cooling load as the supply air is cooled to around 11° C., as well as the latent energy load required to condense water vapour from the supply air at this temperature. This latent energy component varies with ambient humidity. For example, removal of 20 g of water vapour requires removal of around 45,000 J of latent energy. This is a typical peak demand for 1000 m2 of office space, representing a continuous latent cooling load of up to 45 kW per thousand square meters of ventilated space. The supply air temperature is reduced to less than 12° C. and then re-heated to the specified final supply air temperature. Further sensible heat energy is required to cool and then reheat the air.
Reverse Rankine cycle heat pump air conditioning equipment of this type must be capable of handling the latent load imposed by high humidity supply air passing over a condensing coil, which is chilled to around less than 11° C. to produce the required final absolute humidity in the supply air. When operating in conditions of high ambient temperature and high humidity, both the sensible and latent cooling loads are large and these loads must be met by typically a reverse cycle heat pump. These pumps work less efficiently as the temperature differential increases in hot humid periods, requiring increased input of electrical or mechanical energy, usually sourced from a fossil or nuclear fuel powered generator. The plant must be sized to operate at the peak cooling load required by the supply air system but typically operates at a lower power resulting in further inefficiency of conversion of input energy during operation at these times. In urban areas building air conditioning can form up to 35% of the total load on the electrical grid, at peak times in summer months. This load contributes significantly to the required grid capacity and therefore the cost of the electrical grid, which may result in oversizing of electrical generating plants to meet this peak summer cooling load, and consumes large amounts of fossil fuels, producing very significant amounts of green house gases.
Another known dehumidification method uses ionic membranes. Apparatus employing ionic membrane technology operate at a molecular level. Water vapour is removed through electrolysis. This dehumidification occurs at rates too low for practical use in air conditioning systems.
Yet another method involves the use of adsorption/desiccant technology. Dehumidification apparatus utilizing this technology works by exposing the high relative humidity supply air to a desiccant, which adsorbs moisture when water molecules bind to the desiccant surface. When saturated, or nearly saturated, the desiccant is removed from the moist supply air path and the adsorbed moisture is removed from the desiccant, through the application of heat.
The only commercially available adsorption systems known to the Applicant that directly remove water from the air, utilise a large wheel containing an extensive honeycomb mesh coated with desiccant material that is rotated through two separated air streams. The first air stream is a stream of hot air to dry the desiccant material, and the second air stream is the supply air stream to remove water vapour from supply air. Water vapour is removed directly from the air stream by adsorption and then as the wheel rotates, the saturated desiccant is returned to the regenerating stream of hot air that vaporizes adsorbed water from the honeycomb mesh during the regeneration cycle. The desiccator wheel thus rotates through alternating adsorption and regeneration sections. The high temperature air required for regeneration of the desiccant is either provided by direct heating from a dedicated source (typically provided by burning fossil fuel), or by indirectly produced thermal energy supplied to large heat exchangers positioned in the air stream (the large size is dictated by the low specific heat capacity of air). The rotating wheel is expensive and prone to damage over time due to its large size, and delicate honeycomb structure. Seals are required to prevent admixing of the two streams of air, and these seals are also prone to mechanical failure over time. The regeneration cycle is performed at high temperatures, close to the boiling point of water requiring substantial thermal energy input, typically from a fossil fuel source such as a gas burner. The energy supplied must exceed the latent load of the supply air stream, to regenerate the desiccant material. The desiccant material on the honeycomb is at a high temperature at the conclusion of the regeneration cycle and on rotation into the supply air stream, adds temperature to the supply air resulting in an increased sensible cooling load which must be met elsewhere in the supply air conditioning process.
It is an object of the present invention to overcome at least some of the aforementioned problems or to provide the public with a useful alternative.
Any discussion of documents, acts, materials, devices, articles or the like, which has been included in the present specification is solely for the purpose of providing a context for the present invention. It should not be taken as an admission that any or all of the previous discussion forms part of the prior art base or was common general knowledge in the field of the invention as it existed before the priority date of any of the claims herein.


Apparatus for recording and reproducing video data is described that utilizes data compression to increase storage capacity. Real time input video data is decorrelated, quantized and entropy encoded. User control of a compression control parameter, such as quantization step width, is provided so that the user can adjust the loss of fidelity through compression to a desired level. The compressed data is output to a storage RAM 38 at an unregulated varying data rate. The system allows real time storage of video data in a manner in which the loss of fidelity is held constant and the amount of storage capacity required for particular sections of input video data varies with the information content of that input video data.

1. Field of the Invention
This invention relates to video data compression. More particular, this invention relates to the real time recording of video data as compressed video data.
2. Description of the Prior Art
Data compression is utilised in the still image field. The proposed JPEG standard provides a non real time image data compression technique for use in situations such as the compression of still images by and for storage within general purpose computers. The JPEG technique utilises quantization as One step in the compression process. The quantization step width applied may be changed to change the degree of compression achieved. Using a Small quantization step width will increase the length of time needed to encode the data (limited rate data channels within a computer) and the amount of storage space needed to store the compressed image. Conversely, using a large quantization step width will decrease the length of time needed to encode the data and the amount of storage space needed to store the compressed image. The asynchronous, non real time nature of the JPEG approach means that such variation is not an issue of importance.
It is also known to utilise real time compression systems in conjunction with storage applications in order to increase the storage capacity. A requirement in such systems is the achieving of a constant output bit rate compatible with the storage medium used. This approach results in a variable picture quality depending upon the image information content. Furthermore, since these systems have to achieve an acceptable picture quality with the most difficult of images, they produce an image quality in excess of that genuinely required for the majority of pictures with a consequential reduction in storage capacity.
The constant data rate approach is imposed on convention compression systems due to the nature of the storage media that are generally used. In particular, storage media such as magnetic tapes, hard-discs and magneto optic discs have mechanical inertia such that they are only able to deal with a constant data rate when operating close to their peak performance. Thus, for images with a small amount of information content, the image quality exceeds the specification (and is likely to be lossless) and for images with a large amount of information, the image quality can be below specification.

Video data compression apparatus for recording and reproducing compressed video data at their various compressed data rates


To prevent unauthorized duplication of important security documents, an improvement in security or protected documents is disclosed. The security document includes a substrate having top and bottom surfaces where at least one of the surfaces is adapted to carry printed copy thereon. A colored background is printed on at least a portion of one of the surfaces, such as the surface which is adapted to carry printed copy, using a temperature sensitive ink. The security document also includes copy printed on at least a portion of the one of the surfaces adapted to carry printed copy thereon. With these features of construction, the security or protected document contemplates the copy being printed by utilizing a temperature insensitive ink.

In the past, there have been many ways of attempting to prevent unauthorized duplication of important or sensitive documents. The development of xerography, and particularly color xerography, has provided the unscrupulous with the means for unauthorized duplication of original documents for the purpose of passing them off, with or without alteration, as an original document of the same kind. As a result of color xerography, the mere printing of an important document with a colored background is insufficient for preventing unauthorized duplication.
In fact, the problem is widespread and well known to the issuers of such original documentation which has led to considerable attention being given to ways to prevent the duplication of such documents by color xerography. While in no sense limited in practice, the documents will be understood to be of the type which include negotiable instruments, title instruments, identification instruments, and other similar security instruments or documents.
Because of these problems, there has been much attention given to the prevention of effective duplication of such documents by color xerography. It has become known, for instance, that xerographic copiers have a screen value, or dot frequency, threshold above which the copier is unable to distinguish the individual elements of the dot pattern of half-tone printing and that, as to color xerography, there are also spectral ranges of color in which the reproductive capability of the copier is relatively impaired. As a result of this knowledge of color xerography, the focus has been on using these facts to render unauthorized xerographic duplication difficult.
Typically speaking, the primary focus has been upon causing invalidating indicia of tampering to be essentially latent to the naked eye looking at the original document without the aid of magnification but to appear boldly in the xerographic copy.
In most earlier proposals, the invalidating indicia are printed in one dot frequency or screen value and the background is printed in another with the indicia camouflaged in one of a couple of different ways. In particular, this is achieved either with an intermediate third-dot frequency immediately surrounding the invalidating indicia or with a covering overlay of extraneous pattern intended to confuse the eye sufficiently to render the warning indicia indiscernible to ordinary observation. More recently, the invalidating indicia and the background have been printed in different screen values, one above and one below the dot frequency threshold of a xerographic copier, with the invalidating indicia as a compact all over pattern serving as its own camouflage.
While all of these techniques have their merits, there are certain important drawbacks that are inherent in each of them. These include the fact that there are continuously new improvements in the field of color xerography whereby exact reproductions of the original documents are or may become possible, i.e., the invalidating indicia may not appear in the xerographic copy. In order to keep pace, it is important to develop an improved security document that is independent of color xerography characteristics.
The present invention is directed to overcoming one or more of the foregoing problems and achieving one or more of the resulting objects.


A multiplex transmission system for a vehicle is constructed such that signals are given and received via a communication line between a plurality of peripheral stations and a central station. The plurality of peripheral stations are arranged at various places such as a door system, an engine system and the like. Each of the peripheral stations is constructed such that an input signal from the plurality of working members (a door lock, a power window and the like) is sent to the central station via the communication line. A control signal from the central station is input via the communication line 5 by the peripheral stations to output to the plurality of working members. Depending on the bit unit form of the control signal working members are actuated. The central station processes data sent by the peripheral stations to generate the control signal.

1. Field of the Invention
The present invention relates to a multiplex transmission system, which is used for a communication system such as LAN (Local Area Network).
2. Description of the Prior Art
Conventionally, for example, in a multiplex transmission system for a vehicle, processing units having the same communication processing capacity are used at each station (nodes) connected with a door system (a door lock installed at a door and the like), and an engine system and the like, thereby communication has been realized.
However, in the above mentioned conventional system, there are stations which only perform input of a signal or control of an actuator, and a station which also performs control of other systems and the like. The required communication processing capacity differs depending on a system.
Nevertheless, each station of the system uses a processing unit having the same communication processing capacity. This causes an extremely bad efficiency problem.
Namely, judgment for operating vehicle functions such as door locking and the like on the basis of an input signal is entrusted to a station (a central station) specialized in judgment processing. Peripheral stations receiving output data which includes a judgment result must be provided with functions for rearranging the output data and performing data conversion in order to provide an output form suitable for the peripheral station. Processing units having the same communication processing capacity are used for both the central station and peripheral stations in spite of the different output form conversion to be required. Therefore, there is an extremely bad efficiency problem.

Multiplex transmission system for vehicle


The carriage mounting the print head, for a printer, is supported at an upper guide bar with an upper bearing and at a lower guide bar with a lower-right bearing and a lower-left bearing. The printing device prints characters while driving the print head in reciprocal movement along the guide bars. The lower-left bearing has an eccentric center relative to the axis of the lower-guide bar. A lever fitted on the lower-left bearing allows the operator to rotate the lower-left bearing relative to the axis of the lower guide bar to adjust the height of print.

1. Field of the Invention
The invention relates to a printing device, and more particularly to a printing device with a tiltable head.
2. Description of the Related Art
Regarding printing devices in this category, a printing device with a rotatable dot matrix printing head for printing characters in condensed images was disclosed in Japanese Laid-Open Patent Publication No. 62-176852.
As shown in FIG. 6, the printing device according to the Japanese Laid-Open Patent Publication has a dot matrix head 52 rotatably supported at the rotation axle 54. The dot matrix head 52 comprises a plurality of printing pins 50 set along a line. The printing device prints characters having vertically-condensed images by adjusting the tilt angle of the dot matrix head 52 in a plane parallel to the printing surface.
However, printing devices with the above structure have an inherent problem, that is, the printing devices with the above structure require driving units, such as a motor or a solenoid, which bring an increase in the weight of the carriage and in the cost of the device.
In addition to the above problems, the angle of the printing head has to be adjusted, for example, within an accuracy of 0.1 degree, which requires precision parts in the driving unit thus making the construction very difficult and even costlier.

Printing device with a tiltable printing head


The degree of a structure change of the sugar chain of a glycoprotein caused by a disease can be measured with high precision rapidly by separating and measuring two or more forms of glycoproteins which are different in sugar chain structure but have substantially the same protein structure, by using a combination of a lectin capable of recognizing the specific sugar chain structure of at least one of these glycoprotein analytes to be measured, and a first antibody which has a property of binding to all the glycoprotein analytes but is kept from binding to glycoprotein analyte(s) having the lectin attached thereto; and separating and measuring glycoprotein analyte(s) having the first antibody attached thereto and glycoprotein analyte(s) having no first antibody attached thereto, by utilizing differences in properties between the former glycoprotein analyte(s) and the latter glycoprotein analyte(s).

This invention relates to a process for separating and measuring two or more forms of glycoproteins which are different in sugar chain structure.
In not only human beings but also most animals, many of proteins contained in body fluids are glycoproteins having one or more sugar chains. Recently, because of the diversity of its structure and the like, the sugar chain moiety is particularly noted as a substance carrying some information concerning the interior of a living body and is studied in many universities and research institutes both inside and outside Japan.
In the course of the study, a change in the sugar chain structure of a specific glycoprotein caused by some disease was often observed. For example, in human .alpha.-fetoprotein (AFP), it was confirmed that the addition of an .alpha.-L-fucose residue or an N-acetylglucosamine residue (bisecting N-acetylglucosamine) to AFP sugar chain is frequently observed with the progress of hepatic cellular carcinoma. Furthermore, the degree of such a change of the sugar chain structure is independent of the AFP concentration in serum and the change is confirmed even in early hepatic cellular carcinoma. Therefore, it is considered that the investigation of the degree of the change permits diagnosis of cancer. Thus, the change of the sugar chain structure is noted.
The degree of change of the sugar chain structure of a glycoprotein is measured mainly by an analytical method using a lectin, such as lectin column method or lectin electrophoresis method. The reason why the degree of change of the sugar chain structure is measured mainly by use of a lectin is, for example, as follows. Lectins are not expensive. Moreover, since the immunogenicity of the sugar chain moiety of a glycoprotein is lower than that of the protein portion of the glycoprotein, no effective anti-sugar chain antibody can be obtained except that for a part of the non-reducing terminal structure, namely, the preparation of an antibody to the sugar chain of the glycoprotein is very difficult.
However, although lectins have a high recognizing specificity for the sugar chain structure, their bonding strength (coupling constant) to the sugar chain is one over thousands to one over tens of thousands as high as that of the antibody. Therefore, it is difficult to form a complex of a lectin and the sugar chain which is stable like a complex formed by antigen-antibody reaction. Accordingly, when a lectin is used in place of an antibody in an analytical method requiring a washing procedure after the formation of a complex on a solid phase, such as an enzyme immunoassay (ELISA) using a solidified antibody, a complex of the lectin and a glycoprotein to be measured dissociates during the washing, resulting in causing problems such as a marked lowering of the measuring sensitivity. Thus, such a method cannot be said to be practical as a clinical diagnosis. In addition, because of the above-mentioned properties of lectins, there has been the following restriction: for measuring a glycoprotein by utilizing the reaction of a lectin with the glycoprotein, the measurement should be carried out in the presence of a large excess of the lectin over the glycoprotein to be measured, by use of a column coupled with the lectin, an agarose gel containing the lectin, or the like.
Therefore, there is desired the development of a process for rapid and easy separation and measurement of glycoprotein sugar chains, which has both the sugar-recognizing specificity of lectins and the high sensitivity of enzyme immunoassay.

Process for separating and measuring glycoprotein


An electrical junction box that includes a circuit board on which a coil element is installed; a partition wall that surrounds the coil element and separates an installation region on the circuit board on which the coil element is installed from a region around the installation region; a frame that is formed in one piece with the partition wall and surrounds the circuit board; a heat dissipation plate on which the circuit board and the frame are placed; and a cover that covers the circuit board from the frame side, wherein the coil element is fixed to the partition wall using a synthetic resin material, and wherein the frame and the heat dissipation plate are positioned relative to each other through a recess-projection engagement, and the cover is fixed to the heat dissipation plate using screws.

The technology disclosed in this specification relates to an electrical junction box.
A conventional electrical junction box including a case accommodating a circuit assembly in which various electronic components are installed on a conductive path of a circuit board is known as an apparatus for applying or interrupting an electric current to in-vehicle electrical equipment.
An example of the electronic components installed on a board in such an electrical junction box is a coil element such as an inductor obtained by winding a coil around a core. When a heavy electronic component such as a coil element is connected to the conductive path on the board only by soldering its terminals to the conductive path, there is a risk that cracks are formed in the solder due to the vibration during traveling. Therefore, the main body of the coil element is mechanically fixed to the board using a fixing means such as a screw or a leaf spring.


A trigger operated fluid dispensing device for mounting to a container comprising: a body having a front end including opposed side walls at the front end, a nose bushing extending from the front end between the body side walls and at least one, elongate, nozzle cap blocking member which extends from the body front end and which is adapted to engage and prevent rotation of a nozzle cap upon rotation of the cap without manipulation of the body side walls; a nozzle assembly at the body front end including the nose bushing, a nozzle cap received on the nose busing and cooperating structure on or in the nozzle cap and on or in the nose bushing for selectively establishing an off position, a spray position or a stream position of the nozzle cap upon rotation of the nozzle cap; the nozzle cap being mounted for rotation on the nose bushing between the three positions and the nozzle cap having engaging structure therein positioned adjacent the blocking member for engaging the blocking member when someone attempts to rotate the nozzle cap without manipulating the body side walls; and, the side walls of the body at the front end being deflectable inwardly of the body so that when the side walls are squeezed inwardly, they engage and move inwardly the blocking member to permit the engaging structure to move past the blocking member when the nozzle cap is rotated at the same time the body side walls are squeezed.

1. Field of the Invention
The present invention relates to a trigger operated dispensing device, e.g., a trigger sprayer, for mounting to a storage container, e.g. a bottle A pumping mechanism inside the dispensing device pumps a fluid out of the storage container into the discharge end of the dispensing device upon actuation of a trigger of the device A nozzle assembly is attached to the discharge end and includes a rotatable nozzle cap rotatable to three different discharge positions. A STOP position closes the discharge end, a STREAM position provides a focused stream of fluid, and a SPRAY position provides a spray or fog-like discharge of the fluid.
To avoid access to the contents of the bottle to children, the rotatable nozzle cap remains in the STOP position and cannot be moved easily by children unless the trigger sprayer is manipulated in a special manner. To ensure that the rotating nozzle cap remains in the desired position, i.e. the STOP position, the nozzle cap has at least one internal lug or catch adapted to engage at least one prong or leg extending from a body of the sprayer unless the body is squeezed to deflect the prong or prongs inwardly so the lug inside the cap can be rotated past the prong as the cap is rotated. The lug cannot be disengaged from the prong easily, thereby providing a child resistant trigger sprayer nozzle assembly.
2. Description of the Related Art Including Information Disclosed Under 37 CFR .sctn.1.97-1.99
Heretofore, various child resistant nozzle assemblies have been proposed. Some examples of previously proposed child resistant nozzle assemblies are disclosed in the following patents:
______________________________________ U.S. Pat. No. Patentee ______________________________________ 4,516,695 Garneau 4,346,821 Wesner et al. ______________________________________
The Garneau U.S. Pat. No. 4,516,695 discloses a child resistant nozzle assembly comprising a flexible lever with a shoulder engaging in a notch within a nozzle cap. After pushing the lever, the nozzle cap is free to rotate. After the nozzle cap is back in the desired position, the lever can be pulled back to fix the nozzle cap in the desired position.
In the Wesner et al. U.S. Pat. No. 4,346,821 a nozzle assembly including a planar safety closure is disclosed. The planar safety closure is mounted rotatably on a nose piece at an end portion of a trigger sprayer and is held tightly in place by the passing of an annular ridge on the planar safety closure over an annular lip on the nose piece. A generally flat tab is integrally connected to an overcap. The far end of this tab contains a tooth like detent member which extends rearwardly and is engagable in a slot in a top front wall of a trigger. In this position, the nozzle is locked and cannot easily be opened. To unlock the planar safety closure and to operate the trigger sprayer, the operator has to squeeze the trigger to lift the detent member out of its slot and then has to rotate the planar safety closure for about 180.degree. to a spray position. In this position, the trigger sprayer is ready to work.
The nozzle assembly of the present invention differs from the previously proposed nozzle assemblies by comprising a cap having at least one internal lug which is adapted to engage at least one prong extending from a body of the trigger sprayer to prevent rotation of the cap until the cap is squeezed to deflect the prong inwardly to allow the lug to be rotated past the prong as the cap is rotated. When the nozzle cap is rotated back to the STOP position the lug snaps back into a prong engaging "locked" position and the cap cannot be unlocked by accident such as to a spray position.

Child resistant nozzle for trigger sprayer