A carpet tape is disclosed with hooks projecting from the front side of a sheet for attachment to loops on the underside of the carpet and with an opposite adhesive side for attachment to the floor. Selected, non-contiguous areas of the sheet are removed to create holes to reduce the mount of material, to reduce seam telegraphing and to allow moisture to be released from beneath the tape. A covering provides integrity for the tape prior to installation.

In U.S. Pat. 4,822,658 entitled "Carpet Backing and Installation System" issued Apr. 18, 1989, the same inventor disclosed a new carpet backing and installation system. The disclosure of that patent is hereby incorporated by reference. This new carpet with its backing has proved to be commercially successful. Installation of carpet using tape as described with this system saves considerable time and energy. Further, once the tape has been installed, worn or damaged carpet can be easily replaced by removal of the carpet and by the installation of new carpet over the installed tape. The tape, once installed can be reused many times, and it is at this stage that significant economies can be achieved.
In U.S. Pat. 4,822,658 a tape is disclosed having hooks and a covering over the hooks to prevent premature attachment of the hooks onto loops contained on the bottom of a novel carpet backing. On the opposite side of the tape is a pressure sensitive adhesive for adhering the tape to the floor. A release paper is attached over the adhesive at the back of the tape to be removed prior to installation of the tape on the floor.
Owing to the expense of the tape disclosed in U.S. Pat. 4,822,658 and for ease of installation (particularly with respect to the removal of the tape covering) it was proposed to use that tape primarily along the edges and at the seams of the carpet and at a few selected intermediate locations.
This arrangement works fine in many installations. However, it has been found that in some carpets with low pile, such as some commercial carpets where the tape is placed only at the seams, there is a possibility of "telegraphing" so that the outline of the tape could communicate through the carpet at the seams or at other places where the tape has been placed to provide additional adherence to the floor.
In addition, because of the expense of the tape, it is difficult to justify laying the tape across the whole floor, with the result that the tape does not contact the entire installed carpet undersurface. If the carpet is fixed to the floor across its whole undersurface, less dimensional stability needs to be added to certain types of carpet with the subsequent decrease in costs of the carpet.
Further, when the tape is placed only at selected seams or other selected locations, it is advisable to have a release paper backing over the pressure sensitive adhesive to prevent the tape from attaching until it has been located to be under carpet seams or other desired locations.
Moreover, tape is conventionally made of polyethylene or polypropylene which can trap moisture between the tape and the floor and this can damage the adhesive over time. If tape as disclosed in U.S. Pat. 4,822,658 is laid along the entire floor, this problem can be increased.


A highly conductive region 18 serving as a surface of a drain layer 2 of a first conductivity type is diffused more deeply than a main diffused layer 36 and a diffused channel layer 37, and has a small conducting resistance. The highly conductive region 18 is surrounded by a diffused region 40 of a second conductivity type which comprises a diffused base layer 38 and a diffused guard ring layer 13. Therefore, the highly conductive region 18 does not form spherical junctions, and a depletion layer spreading in the highly conductive region 18 extends into the highly conductive region 18. The highly conductive region 18 thus has a high withstand voltage while maintaining the low conducting resistance.

1. Field of the Invention
The present invention relates to a power semiconductor device, and more particularly to a semiconductor device having a high withstand voltage.
2. Description of the Revelant Art
Heretofore, high-speed, high-withstand voltage semiconductor devices are used in apparatus for switching large currents in power supplies or the like. FIG. 33 of the accompanying drawings shows a semiconductor chip 101 of MOSFET which is generally used as one of those conventional semiconductor devices.
As shown in FIG. 33, the semiconductor chip 101 is made of a single crystal of silicon and has a drain layer 102 comprising an nxe2x88x92 layer 1021 of high resistance, an nxe2x88x92 layer 1022 of low resistance which is of the same conductivity type as the nxe2x88x92 layer 1021, and a highly conductive region 103.
The nxe2x88x92 layer 1022 is positioned centrally in the drain layer 102, the n+ layer 1022 in a back side of the drain layer 102, and the highly conductive region 103 in a face side of the drain layer 102. If an n type is a first conductivity type, then a number of p-type diffused base layers 108 which are of a second conductivity type are disposed on the surface of the highly conductive region 103.
The diffused base layers 108, each of a square shape, are arranged in a matrix. As shown in FIG. 34 of the accompanying drawings, each of the diffused base layers 108 comprises a central main diffused layer 106 having a large diffusion depth and a channel region 107 having a small diffusion depth and surrounding the main diffused layer 106. Therefore, each of the diffused base layers 108 is deeper in its central area and shallower in its peripheral area.
A ring-shaped n-type diffused source layer 105 is disposed in each of the diffused base layers 108. A gate insulating film 104 comprising a silicon oxide film and a gate electrode film 110 are deposited in the order named on the surfaces of the channel regions 107. When a positive voltage is applied to the gate electrode film 110, an n-type inverted layer is developed in the surface of the p-type channel region 107, electrically connecting the diffused source layer 105 and the highly conductive region 103 to each other.
The semiconductor chip 101 also has a source electrode film 111 and a drain electrode film 112 which are prevented from being short-circuited by an interlayer insulating film 115.
The MOSFET shown in FIG. 33 has a higher operating speed than bipolar transistors, and suffers a small current concentration upon transition from a conducted state to a cut-off state, allowing a semiconductor device having a high withstand voltage to be easily fabricated.
When a conducting current flows in the semiconductor chip 101, the resistance of the drain layer 102 and the resistance of a JFET between the diffused base layers 108 are effective enough to cause a larger loss than bipolar transistors.
With the highly conductive region 103 in the face side of the drain layer 102, the resistance of the drain layer 102 is reduced, resulting in a reduction in the forward resistance of the MOSFET. The withstand voltage of the MOSFET is lowered because a depletion layer is less liable to spread in the highly conductive region 103.
In a pn junction made up of the diffused base layer 108 and the highly conductive region 103, as shown in FIG. 35a of the accompanying drawings, depletion layers 120 tending to spread into the highly conductive region 103 are less liable to spread in the highly conductive region 103 as the highly conductive region 103 is of a higher concentration.
Generally, pn junctions are classified into planar junctions, cylindrical junctions, and spherical junctions in terms of the configuration of a diffused layer of higher concentration. Cylindrical junctions are formed on confronting sides of the channel regions 107, whereas spherical junctions are formed on vertexes of the channel regions 107.
It is known that the pn junctions have a withstand voltage which is progressively smaller in the order of planar junctions, cylindrical junctions, and spherical junctions. The withstand voltage of the pn junction between the diffused base layers 108 and the highly conductive region 103 is determined by the spherical junctions on vertexes of the diffused base layers 108. Particularly, an avalanche breakdown tends to occur on the surface of the highly conductive region 103.
If confronting diffused base layers 108 are displaced closely to each other until two depletion layers 120 extending in the highly conductive region 103 are brought into contact each other, then when a reverse bias greater than the voltage at which the depletion layers 120 contact each other is applied, the depletion layers 120 spread in their depth, and hence the withstand voltage is determined at a position deeper than the surface of the highly conductive region 103.
In this case, the withstand voltage is higher than if an avalanche breakdown occurs when the confronting diffused base layers 108 are spaced from other and before the depletion layers 120 contact each other.
With the conventional MOSFET, however, as shown in FIG. 35b of the accompanying drawings, a reverse biased state between the drain layer 102 and the diffused base layers 108 is so large that even when the depletion layers 120 are held in contact with each other between the sides of the channel regions 107, the depletion layers 120 are kept out of contact with each other between the vertexes of the channel regions 107 because the distance between the vertexes is large, so that the withstand voltage of the spherical junctions will not increase. The pn junctions are thus subjected to a breakdown in surface areas 111, tending to break the semiconductor device.
It is therefore an object of the present invention to provide a semiconductor device having a high withstand voltage.
Another object of the present invention is to provide a semiconductor device whose withstand voltage can be increased while preventing a conducting resistance from being increased.
According to the present invention, there is provided a semiconductor device having a drain layer of a first conductivity type formed in a semiconductor subtrate, the first conductivity type being either a p type or an n type of semiconductor, and a second conductivity type being the other of the p type or the n type, a diffused base layer of the second conductivity type formed in a surface of said drain layer, and a diffused source layer of the first conductivity type formed in a surface of said diffused base layer, said diffused base layer having a portion as a channel region between said diffused source layer and said drain layer, said channel region having on a surface thereof a gate insulating film and a gate electrode film, the arrangement being such that when a voltage is applied to said gate electrode film, forming an inverted layer in the surface of said channel region, said diffused source layer and said drain layer are electrically connected to each other by said inverted layer, characterized in that a portion of said drain layer which is connected to the diffused source layer by at least said inverted layer has a highly conductive region having a resistance lower than said drain layer and the same conductivity type as said drain layer, said highly conductive region having a surface surrounded by a diffused layer of the second conductivity type including said diffused base layer.
The surface of said highly conductive region may be divided into a plurality of regions by the diffused layer of the second conductivity type including said diffused base layer.
The diffused base layer may have a main diffused layer which is of the same conductivity type as said diffused base layer and is diffused to a depth greater than said diffused base layer, said highly conductive region being diffused to a depth greater than the depth to which said main diffused layer is diffused.
The semiconductor device may further comprise a diffused guard ring layer disposed around an outer peripheral portion of said diffused base layer, said diffused guard ring layer being of the same conductivity type as said diffused base layer and diffused to a depth greater than the depth to which said main diffused layer is diffused. The diffused guard ring layer may be held in contact with a base region. Another diffused guard ring layer may be disposed outside of the above diffused guard ring layer in spaced relationship thereto.
The surface of the highly conductive region of the first conductivity type may have an outer peripheral portion held in contact with said diffused layer of the second conductivity type which includes the diffused guard ring layer and the diffused base layer. The highly conductive region may be brought into contact with the diffused layer of the second conductivity type when a window is opened in an insulating film for forming an impurity layer to form the highly conductive region, or the highly conductive region and the diffused layer of the second conductivity type may be brought into contact with each other by the diffusion of an impurity in the lateral direction of the substrate when an impurity layer is diffused to form the highly conductive region.
Furthermore, a drain electrode film may be disposed on either a face side or a back side of said semiconductor substrate and electrically connected to said drain layer.
With the above arrangement of the present invention, if a first conductivity type is either a p type or an n type of semiconductor, and a second conductivity type being the other of the p type or the n type, then a diffused base layer of the second conductivity type is formed in a surface of a drain layer of the first conductivity type, and a diffused source layer of the first conductivity type is formed in said diffused base layer of the second conductivity type, among said diffused layer of the second conductivity type, regions between said diffused source layer and said drain layer being a channel region.
The channel region has on a surface thereof a gate insulating film and a gate electrode film. When a voltage is applied to said gate electrode film, forming an inverted layer in the surface of said channel region, said diffused source layer and said drain layer are electrically connected to each other by said inverted layer, and a current flows between the diffused source layer and the drain layer.
A surface portion of said drain layer which is connected to the diffused source layer by said inverted layer has a highly conductive region having a resistance lower than that in deep portion of said drain layer, reducing a conducting resistance.
In conventional semiconductor devices, the diffused base layer of the second conductivity type is surrounded by the highly conductive region. According to the present invention, however, the highly conductive region is surrounded by the diffused base layer of the second conductivity type. Therefore, a pn junction between the highly conductive region and the diffused base layer of the second conductivity type has no spherical junction, and has a high withstand voltage. In the pn junction, the depletion layer in the highly conductive region spreads into the highly conductive region from the outer peripheral portion thereof.
Since no spherical junction is present, the impurity concentration of the highly conductive region can be increased while maintaining its high withstand voltage. The withstand voltage is not reduced even if the highly conductive region is deeply formed. Particularly if the diffused base layer of the second conductivity type is joined to the channel region and has a deeper main diffused layer than the channel region, then the high withstand voltage can be maintained even though the depth of the highly conductive region is greater than the depth of the main diffused layer to reduce the effect of a JFET formed between diffused layers of the second conductivity type.
An example of an impurity concentration distribution in the direction of the depth of the main diffused layer is shown in FIG. 30 of the accompanying drawings. The horizontal axis of FIG. 30 represents the diffused depth and the vertical axis thereof represents the impurity concentration. Since the highly conductive region is diffused into the drain layer of the same conductivity type, the diffused depth thereof should be defined. According to the present invention, the diffused depth of the highly conductive region is where the impurity concentration of the drain layer is twice the impurity concentration before the highly conductive region is formed. In FIG. 30, the depth of the main diffused layer is about 3.8 xcexcm, whereas the depth of the highly conductive region exceeds 3.8 xcexcm.
The relationship between the diffused depth, the on resistance Ron per unit area, and the breakdown voltage VDSS of the highly conductive region is shown in the graph of FIG. 31 of the accompanying drawings. In the graph, a straight line l1 represents the relationship between the on resistance Ron and the breakdown voltage VDSS in the case where the highly conductive region is formed only in the vicinity of the surface, as shown in FIG. 32a of the accompanying drawings. A straight line l2 represents the relationship between the on resistance Ron and the breakdown voltage VDSS in the case where the diffused depth of the highly conductive region is greater than the diffused depth shown in FIG. 32a, but smaller than the diffused depth of the main diffused layer, as shown in FIG. 32b of the accompanying drawings. A straight line l3 represents the relationship between the on resistance Ron and the breakdown voltage VDSS in the case where the diffused depth of the highly conductive region is smaller than the depth of a main junction, as shown in FIG. 32c of the accompanying drawings.
The graph shown in FIG. 31 indicates that as the breakdown voltage VDSS increases, the on resistance Ron increases, and the on resistance Ron is smaller as the depth of the highly conductive region is greater for the same breakdown voltage VDSS.
In the case where the highly conductive region of the first conductivity type is formed within the diffused layer of the second conductivity type including the diffused base layer, then a depletion layer in a high-resistance portion of the drain layer tends to spread easily thereby to increase the withstand voltage if the outer side of the diffused layer of the second conductivity type forms a pn junction with the high-resistance portion of the drain layer. The withstand voltage is made higher if the four corners of the diffused base layer of the second conductivity type are rounded so as not to produce spherical junctions, and also if a diffused guard ring of the second conductivity type having a diffused depth greater than the main diffused layer is disposed around the diffused base layer.
The diffused guard ring layer may be held in or out of contact with the diffused base layer of the second conductivity type. The first diffused guard ring layer may be held in contact with the diffused base layer of the second conductivity type, and the second diffused guard ring layer may be disposed around the first diffused guard ring layer out of contact therewith.
These and other features of the invention wil be understood upon reading of the following description along with the drawings.

Semiconductor device with high withstand voltage and a drain layer having a highly conductive region connectable to a diffused source layer by an inverted layer

Shindengen Electric Manufacturing Co., Ltd.


An optical unit, in particular a facet mirror unit, includes an optical element and a supporting device. The optical element has an optical surface, in particular an elongate optical surface, which defines a plane of main extension and a direction of main extension in the plane of main extension. The supporting device includes a supporting unit and an actuator unit. The actuator unit is configured for tilting the optical surface, in that a tilting moment is exerted on the optical element by way of the actuator unit. The tilting moment runs in an inclined manner in relation to the plane of main extension. The supporting unit is configured to predefine a tilting axis for the optical surface that lies substantially in the plane of main extension of the optical surface when there is tilting of the optical surface by the tilting moment of the actuator unit.

In particular in the area of microlithography, apart from the use of components that are configured with the highest possible precision, among the desired properties are to set the position and geometry of optical modules of the imaging device, that is to say for example the modules with optical elements such as lenses, mirrors or gratings, but also the masks and substrates that are used, as precisely as possible according to predefined setpoint values during operation, or to stabilize such components in a predefined position or geometry in order to achieve a correspondingly high imaging quality.
In the area of microlithography, the accuracy requirements are in the microscopic range of the order of a few nanometers or below. They are in this case not least a consequence of the constant demand to increase the resolution of the optical systems that are used in the production of microelectronic circuits in order to advance the miniaturization of the microelectronic circuits to be produced.
With the increased resolution, and the generally accompanying reduction in the wavelength of the light used, the requirements for the accuracy of the positioning and orientation of the components used naturally increase. In particular for the low operating wavelengths that are used in microlithography in the UV range (for example in the range of 193 nm), but in particular in the so-called extreme UV range (EUV), with operating wavelengths between 5 nm and 20 nm (typically in the range of 13 nm), this of course has an effect on the effort that has to be expended to maintain the high requirements for the accuracy of the positioning and/or orientation of the components involved.
In particular in conjunction with the aforementioned EUV systems, refined influencing of the intensity distribution of the light that is used for the imaging is gaining ever increasing importance. For this purpose, generally so-called facet mirrors are used, in which a multiplicity of extremely small facet elements with an exactly defined position and/or orientation of their optically effective surface with respect to a predefinable reference are arranged in a grid that is as closely spaced as possible. It is in this respect often desired or required (e.g. for a change of the illumination setting) to change the alignment of the facet elements, consequently therefore to tilt their optical surface.
It is known from DE 102 05 425 A1 (Holderer et al.) and DE 10 2008 009 600 A1 (Dinger), the respective disclosure of which is incorporated herein by reference, in conjunction with the defined positioning and orientation of the facet elements of a facet mirror of an EUV system to adjust these facet elements individually. For this purpose, the facet elements are tilted about a tilting axis defined by the supporting structure via a corresponding tilting moment, which is exerted on the facet element by an assigned actuator unit.
In the case of some of the rotationally symmetric facet elements that are known from DE 102 05 425 A1, the tilting axis lies in the plane of main extension of the optical surface, with the tilting moment that is exerted by the actuator unit running parallel to the plane of main extension of the optical surface, and so the optical surface is just tilted, without the facet element undergoing any lateral displacement from the installation space that is provided for the facet element.
Because of the absence of lateral displacement during the tilting, the known facet elements can in principle be positioned particularly close to one another, and therefore do not require large gaps between the facet elements. It is problematic here however that the rotationally symmetric design itself causes comparatively low utilization of the surface area or comparatively large gaps between the facet elements, in which there may be a comparatively great loss of light.
To avoid such losses of light due to gaps between facet elements, or as a result of certain illumination settings, often elongate, non-rotationally symmetric facet elements, which in principle lie against one another almost without any gap in a certain alignment or in a certain switching state, are used. Such a configuration is known for example from DE 10 2008 009 600 A1, providing a cardanic support for the facet elements that has two orthogonal tilting axes which run parallel to the plane of the supporting structure of the facet elements.
A similar support for such elongate, non-rotationally symmetric facet elements is also known from DE 10 2012 223 034 A1 (Latzel et al.), the disclosure of which is incorporated herein by reference. There, the supporting of the respective facet element on a supporting structure is realized by way of a three-rod support in the manner of a ball joint, the optical surfaces of the facet elements running parallel to the plane of the supporting structure. The ball-joint-like support in this case defines an infinite number of tilting axes for the respective facet element, and so the actual tilting axis must then be predefined by the actuating mechanism. Here, too, the actuating mechanism again acts parallel to the plane of the supporting structure of the facet elements, and so the tilting moment that is exerted on the facet element lies in the optical surface. Therefore, here, too, the actuating mechanism consequently again provides tilting axes that run parallel to the plane of the supporting structure of the facet elements.
Certain settings require however that the planes of main extension of the optical surfaces of some (possibly even all) of the facet elements run in an inclined manner in relation to the plane of main extension of the base element of their supporting structure. Not least as a result of the existing restrictions with respect to installation space, this often means that the tilting moment produced by the actuating mechanism (in the region of the base element of its supporting structure) runs in an inclined manner in relation to the plane of main extension of the optical surface.
This inclination of the tilting moment in relation to the plane of main extension has the disadvantage that, apart from the desired component (producing the tilting of the optical surface) parallel to the plane of main extension, the tilting moment also has a parasitic component perpendicular to the plane of main extension, which brings with it an undesired rotation of the optical surface in the plane of main extension. Especially in the case of long, slender facet elements, this rotation of the optical surface in the plane of main extension leads to a greater or lesser degree of lateral displacement of the free ends of the facet elements, for which it is desirable to provide corresponding clearances between the facet elements that are undesired (from the aspect of the least possible loss of light).