A first rotating body heats media on which a toner image is formed at a heating temperature. A second rotating body sandwiches the media in cooperation with the first rotating body and presses the media. A first heat supplying part supplies the first rotating body with heat. A charging part charges the first rotating body, includes a discharging electrode and an auxiliary electrode to form an electric field in cooperation with the discharging electrode, causes the discharging electrode to discharge, and charges the first rotating body with a same polarity as polarity of toner. A second heat supplying part supplies the discharging electrode with heat. A controller controls the second heat supplying part in a period in a non-fixing operation and executes heat supplying mode.

The present disclosure relates to a fixing device and an image forming apparatus.
There has been widely used a fixing device that includes a rotating body having a heating source and a pressing member forming a pressure contact part in cooperation with the face of the rotating body, causes the pressure contact part to sandwich and convey a recording material, and thermally fixes a toner image, which is electrostatically adhered and formed on the face of the recording material, on the recording material. A charging means (corotron charger) that charges the face of the rotating body with the same polarity as that of toner (developer) is provided in the fixing device. The charging means provided in the fixing device prevents occurrence of electrostatic offset.

Fixing device and image forming apparatus


A method for a model predictive control (MPC) of a system determines entries of an approximate coefficient matrix only at locations identified in a map of locations as significant. The map of locations identifies each location of an entry in the approximate coefficient matrix as either significant or insignificant. The entries are determined using one or combination of an approximate coefficient function and an exact coefficient function. Next, the method determines a preconditioner using the approximate coefficient matrix and determines a solution vector by solving a matrix equation of the MPC with a coefficient matrix defined by an exact coefficient function at a current time step of a control using an iterative method with the preconditioner. The method generates a control signal for controlling the system using the solution vector.

Model predictive control (MPC) is used in many applications to control complex dynamical systems. Examples of such systems include production lines, car engines, robots, other numerically controlled machining, and power generators.
The MPC is based on a real time finite horizon optimization of a model of a system. The MPC has the ability to anticipate future events, and to take appropriate control actions. This is achieved by optimizing the operation of the system over a future finite time-horizon subject to constraints, and only implementing the control over a current time step.
The MPC can predict the change in dependent variables of the modeled system caused by changes in independent variables. In a chemical process, for example, independent variables that can be adjusted by the controller are often pressure, flow, temperature, opening of the valves, and stiffness of dampers. Independent variables that cannot be adjusted by the controller are treated as disturbances. Dependent variables in these processes are other measurements that represent either control objectives or process constraints.
The MPC uses models of the system, the current system measurements, the current dynamic state of the process, and the process variable targets and limits to calculate future changes in the dependent variables. These changes are calculated to hold the dependent variables close to target subject to constraints on both independent and dependent variables.
The MPC numerical methods are implemented on various computational apparatus, often designed specifically for a given system. Computational apparatus can range from inexpensive fixed-point precision embedded controllers to sophisticated multi-core computer processor units (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), or dedicated parallel computer clusters.
Model predictive controllers rely on dynamic models of the process, most often linear empirical models, in which case the MPC is linear. Nonlinear MPC (NMPC), which describes systems with nonlinear models or constraints, is often more realistic, compared to the linear MPC, but computationally more difficult. Similar to the linear MPC, the NMPC requires solving optimal control problems on a finite prediction horizon, generally not convex, which poses challenges for obtaining a numerical solution in real time. The numerical solution of the NMPC optimal control problems is often based on Newton-type optimization schemes.
Exact Newton-type optimization schemes require an analytic expression of a corresponding Jacobian matrix, which is rarely available in practice and is commonly replaced with a forward difference (FD) approximation. Such approximate Newton-type optimization schemes utilize the FD approximation of the original nonlinear equation during every time step of the control.
In an application to the NMPC, such an approximate Newton-type optimization can be performed by a Continuation NMPC (CNMPC) numerical method described by Ohtsuka, T., "A Continuation/GMRES Method for Fast Computation of Nonlinear Receding Horizon Control," Automatica, Vol. 40, No. 4, pp. 563-574, April 2004. One of the key repetitive and most computationally intensive steps in on-line calculations with CNMPC is numerical solution of a matrix equation Ax=b, where A is a coefficient matrix, x is a solution vector and b is a vector. The solution varies, from one time step of control to the next one, so do the coefficient matrix A and the vector b.
Entries of the solution vector x determine the output of the MPC method, which is used as an input control parameter for the system to control the system in real time. Therefore, there is a need for methods providing fast and accurate solution of the matrix equation Ax=b appearing in various MPC implementations, e.g., on embedded hardware controllers using inexpensive processing units and limited amount of often slow memory, connected to the processing units.
The coefficient matrix A in the CNMPC is not explicitly given and available only via matrix-vector products. Specifically, a computer code is available to compute a product A*X, where A is the coefficient matrix, * is a matrix-matrix product, and X is a single column-vector, or several column-vectors assembled into a matrix. In this disclosure, the action of this computer code is referred to as an application of "a coefficient function." The coefficient function applied to a vector returns a product of the coefficient matrix and the vector. Internally, the coefficient function requires, e.g., evaluation of the state and costate equations by solving a number of differential equations, as described by Ohtsuka.
Because the coefficient matrix A is only available via the coefficient function, rather than in the matrix format, direct matrix solvers, requiring access to matrix entries, are not used in the CNMPC. Instead, so-called "matrix-free" iterative methods are used, which can operate having only the coefficient function without the coefficient matrix A. One conventional matrix-free iterative method for solving the matrix equation Ax=b of the CNMPC is the generalized minimal residual (GMRES) method. The use of GMRES for the FD approximation of the nonlinear equation during every time step is commonly called FDGMRES, and can be interpreted as an inexact Newton's method. In the context of CNMPC, FDGMRES is named Continuation/GMRES (C/GMRES).
FDGMRES requires matrix-vector multiplications involving the coefficient function. The overall cost of computations is proportional to the maximal number of FDGMRES steps. Slow convergence of FDGMRES results in slowing down on-line computations of the control and reducing control quality obtained in real time calculations in the controller.
In CNMPC and many other MPC methods, e.g., based on interior-point approximations, on-line numerical solution of systems of linear equations can be main bottleneck limiting the number of states, constraints, horizon time, and other important MPC variables, thus, reducing applicability of MPC for difficult and fast practical systems. Accordingly, it is desired to increase efficiency and on-line performance of a model predictive control of a system developing preconditioners for iterative solution of the linear systems required for the controller in real time.

Method and apparatus for preconditioned model predictive control

Mitsubishi Electric Research Laboratories, Inc.


In one embodiment, the present invention is a dual-polarized antenna array constructed from first and second instances of a planar antenna that are co-located and orthogonal to one another. The planar antenna comprises three conducting elements and a transmission line. The first conducting element comprises a straight segment and two arms of equal length. The proximal ends of the two arms are attached to opposite ends of the straight segment. The arms extend away from the second and third conducting elements and towards one another. The second and third conducting elements are separated by a gap and together form a mirror image of the first conducting element. The transmission line has first and second conductors that are coupled to the second and third conducting elements, respectively. In another embodiment, the present invention is a tri-polarized antenna array constructed from three orthogonal co-located instances of the planar antenna.

1. Field of the Invention
The present invention relates to wireless communications systems, and, in particular to antenna arrays used by such systems that employ multiple polarizations.
2. Description of the Related Art
Multiple-input multiple-output (MIMO) technologies are well known in the field of wireless communications. In general, these technologies use multiple antennas at both the transmitter and the receiver of a communications system to perform communications. Communications systems that employ MIMO technologies may achieve certain performance improvements over single-input single-output (SISO) systems that use only one antenna at both the transmitter and the receiver.
For example, in fading environments, MIMO technologies may be used to improve reliability of communications. In such environments, a transmitted signal may travel over multiple different propagation paths to a receiver antenna. Each propagation path carries a version of the transmitted signal that is altered due to factors such as the length of the path, the number of reflections in the path, and the characteristics of any objects in the path. These factors may vary from one path to the next, and, as a result, each version of the transmitted signal may arrive at the receiver antenna with a delay, a signal attenuation, and a phase shift that are different from those of the other versions. As the multiple versions arrive at the receiver antenna, they may constructively or destructively interfere with one another such that the signal received by the receiver is an amplified or attenuated version of the transmitted signal. If attenuation is relatively severe, then errors may result when decoding the received signal, thereby preventing the receiver from recovering the communicated information.
MIMO technologies may be used to prevent these errors from occurring. In particular, MIMO technologies may be used to create multiple "diverse" copies of the information being communicated so that the receiver may have multiple opportunities to decode the information. When one or more copies experience relatively severe attenuation, the communicated information may be recovered from the remaining copies. Further, the receiver may combine all of the copies in an optimal way to recover as much of the communicated information as possible.
As another example, MIMO technologies, such as the Bell Labs Layered Space-Time (BLAST) technology, may be used to increase capacity of communications performed over a limited bandwidth. To achieve improved capacity, the information to be transmitted is divided into a number of separate information streams, where the number of separate information streams is equal to the number of transmitter antennas. The separate information streams are transmitted via different antennas to the receiver where they are decoded and reassembled into the original information generated at the transmitter. In essence, using MIMO technologies in such a manner creates parallel communications channels without requiring additional bandwidth. It is possible to construct a communications system with a transmission capacity that increases linearly as the number of transmitting and receiving antennas increase. For example, a MIMO system having two antennas at both the transmitter and the receiver may be capable of achieving double the capacity of a SISO system having only one antenna at both the transmitter and the receiver.
To achieve the advantages described above, a MIMO system should be capable of distinguishing between the signals transmitted via the multiple transmitter antennas. This may be accomplished by spacing the transmitter and receiver antennas apart such that the set of propagation paths generated by each transmitter antenna is different from those generated by the other transmitter antennas. The distance between the antennas may range from one-half the transmitter's operating wavelength to several operating wavelengths. These spacing requirements may make it difficult, if not impossible, to implement multiple antennas within a relatively small communications device.
The advantages of MIMO may be achieved for relatively small communications devices by employing polarization diversity. In polarization diversity, each of the multiple transmitter antennas transmits a signal using an antenna polarization that is different from that of the other antennas. Multiple antennas having polarizations that are orthogonal to one another may be placed together (i.e., co-located) and are not restricted by spacing requirements. As discussed in Andrews, "Tripling the capacity of wireless communications using electromagnetic polarization," Letters to Nature, Vol. 409, 18 Jan. 2001, pages 316-318, the teachings of which are incorporated herein by reference in their entirety, a MIMO system may be implemented using as many as three differently-polarized, co-located antennas.
Multi-polarized antenna arrays may also be used in wireless communications systems that employ polarization diversity without using MIMO technologies. For example, in wireless communications systems that transmit only one copy of a signal, the polarization of the signal relaying that single copy might not be aligned with the polarization of the receiver antenna. This misalignment may cause signal reception to be less reliable. To improve reliability in such cases, a multi-polarized antenna array may be used at the receiver. The multi-polarized antenna array receives multiple differently-polarized versions of the transmitted signal. The multiple differently-polarized versions may then be combined in a manner similar to the combining techniques employed for spatial diversity to improve reliability. Alternatively, the receiver may select the more reliable of the differently-polarized versions for decoding.


The present invention provides a gastric retention controlled drug delivery system comprising:                (a) a controlled release core comprising a drug, a highly swellable polymer and a gas generating agent, said core being capable of swelling and achieving floatation rapidly while maintaining its physical integrity in gastrointestinal fluids for prolonged periods, and        (b) a rapidly releasing coat composition comprising the same drug as in the core and pharmaceutically acceptable excipients, wherein the coating composition surrounds the core such that the system provides a biphasic release of the drug in gastrointestinal fluids.

Controlled drug delivery systems deliver drug to the body so as to establish therapeutically effective blood levels of the active ingredient and once these blood levels are achieved they continue to maintain constant blood levels for long durations by delivering the drug to the body at the same rate as the body eliminates the drug. By avoiding peaks and troughs in blood levels associated with conventional dosage forms, controlled drug delivery systems lower the incidence of adverse effects or side effects. Very importantly controlled drug delivery systems reduce the frequency of dosing leading to convenience to the patient in terms of dosing and compliance to the specified dosage regimens.
It is generally known that the rate at which an oral controlled drug delivery system delivers the drug into the blood is not the same as the rate at which it releases the drug into a test aqueous fluid because the gastrointestinal fluid's pH, composition and agitation intensity change with the specific location of the drug delivery system in the gastrointestinal tract i.e. from the stomach to the colon, fasted versus fed state, type and amount of food ingested, and also vary from individual to individual. In addition, the drug may not be absorbed in the same manner and propensity we move from the stomach to the colon. Some drugs have an "absorption window" i.e. they are absorbed only from the upper parts of the gastrointestinal tract, whereas there are others whose absorption from the colon is not uniform or complete. Thus, the location of the controlled drug delivery system in the gastrointestinal tract as well as the rate at which the controlled drug delivery system moves from the stomach to the colon represent important factors that need to be considered in the design of an oral controlled drug delivery system. It is thus known to those skilled in the art that an oral controlled delivery should be designed not only with a control on the rate at which it releases the drug over the drug delivery time period (temporal control) but also a control on the location from which it is delivered (spatial control). The spatial control can be achieved by prolonging the period of retention of the system in the stomach. Gastric retention systems are also beneficial when the drug is effective locally in the stomach. Drugs absorbed in the upper part of the gastrointestinal tract may exhibit variability in absorption due to inter and intra-individual variability in gastric emptying and gastrointestinal motility. This variation in absorption may be addressed by administering a dosage form comprising the drug such that a small part of the drug is available as immediate release, and a large part is available as sustained or controlled release.
One of the approaches that has been used for achieving spatial control involves increasing the gastric retention of sustained or controlled drug delivery systems by using a composition containing highly swellable polymers in admixture with a gas-generating agent to form systems that are large in size as well as capable of floating on gastric fluids. It has now become well recognized by those particularly skilled in the art that systems containing swellable polymers will instantly float on gastric fluids because the gas generated and entrapped within the system decreases the density. Swelling to a large size is an important factor in gastric retention of the system. Solids having a size less than 5 to 7 mm show delayed gastric emptying in fed conditions but they can still be emptied from the stomach because their size is smaller than the pyloric sphincter. Even floating systems of size less than 5 to 7 mm can be emptied if the patient is in supine position. The mean resting pyloric diameter is approx. 13+7 mm and it has been reported that dosage forms with a size of approx. 12-18 mm diameter in their expanded state would generally be excluded from the passage of the pyloric sphincter. The system should also be capable of retaining this size in the gastric fluids for long periods under agitational conditions created by gastric motility. Such large intact systems cannot be emptied until the arrival of the interdigestive migrating motor complex at the beginning of the interdigestive phase. The combination of increase in size and floatation results in increased gastric retention of the system. The prior art resulting in this current state of the art is described below.
U.S. Pat. No. 4,101,650 ('650) assigned to Zaidan Hojin Biseibutsu Kagaku Kenkyu Kai discloses a formulation in which granules containing sodium bicarbonate, lactose and polyvinylpyrrolidone are coated with a layer of hydroxypropyl methylcellulose. These are then further coated with a suspension containing the active ingredient pepstatin and hydroxypropyl methylcellulose to form floating minicapsules of a diameter in the range of 0.1 to 2 mm. The drawback of this system is that the minicapsules are much smaller in size than required for long durations of retention in the stomach.
U.S. Pat. No. 4,777,033 ('033) assigned to Teijin Limited, discloses an oral sustained release pharmaceutical preparation comprising a lower alkyl ether of cellulose, polyacrylic acid or its pharmaceutically acceptable salt, a drug, and an effective amount of effervescent foaming agent. Tablets made from the composition however still retained the above-cited major disadvantages associated with the '650 prior art in that the tablets of the '033 system did not remain intact when subjected to dissolution testing.
U.S. Pat. No. 4,844,905 assigned to Eisai Co. discloses granules comprising a drug containing core; a middle gas-generating layer comprising sodium carbonate and organic acid; and an outer coat of an expandable polymer film. Although intended for remaining in the stomach, the granules have the disadvantage of small size.
Japanese Patent No. 63014715 assigned to Zeria Shinyaku Kogyo KK discloses a slow releasing composition comprising (A) a high-viscosity water-soluble polymer, preferably cellulose ether or polyvinyl alcohol, (B) crosslinked insoluble polyvinyl pyrrolidone, and (C) a component to foam in contact with gastric juice, preferably carbonate, especially calcium carbonate or precipitated calcium carbonate. The system does not however contain a part of the drug in immediate release form and a part in controlled release form and does not provide a biphasic release pattern. Thus, even at the start of the dosage regimen when there is no drug available in the body, the system may begin with a relatively slow rate of release as compared to that from an immediate release composition. Another disadvantage is that whereas polymers that are highly swellable as well as rapidly swellable may be desirable for achieving gastric retention, we have found that several cellulose ethers do not conform to these requirements.
U.S. Pat. No. 5,651,985 assigned to Bayer AG, claims a pharmacologically active composition comprising a pharmacologically active compound dispersed in a homogenous mixture on the molecular level of polyvinylpyrrolidone and a methacrylic acid polymer having an acidic number between 100 and 1,200 mg of KOH/g of polymer solid substance, and optionally a gas-forming additive. The system does not however contain a part of the drug in immediate release form and a part in controlled release form and does not provide a biphasic release pattern. The rate of swelling of these systems is also slow so that they do not achieve the desired large size in a short period of 15 to 30 minutes. Moreover in order to achieve homogeneity of the two polymers on the molecular level a cumbersome and expensive process such as freeze-drying is required.
PCT publication No. WO 00/15198 assigned to Ranbaxy Laboratories relates to a pharmaceutical composition comprising a drug, a gas-generating component, a swelling agent, a viscolyzing agent, and optionally a gel-forming polymer. The gas generating agents used are carbonates or bicarbonates. The swelling agent is a superdisintegrant such as cross-linked polyvinylpyrrolidone, cross-linked carboxymethylcellulose and sodium starch glycolate. The viscolyzing agent is a carbohydrate gum that viscolyzes instantly. The system does not however contain a part of the drug in immediate release form and a part in controlled release form and does not provide a biphasic release pattern.
PCT publication No. WO 01/10419 assigned to Ranbaxy Laboratories relates to a pharmaceutical composition comprising a drug, a sugar, a diluent and a gas generating agent, and PCT publication No. WO 01/10405 also assigned to Ranbaxy Laboratories relates to a pharmaceutical composition comprising a drug, inert oil, a sugar, a diluent and a gas-generating agent. These systems however are not capable of swelling to a desirable large size suitable for gastric retention, as they do not contain any swellable substance.
PCT publication No. WO 00/23045 assigned to Sanofi-Synthelabo discloses a pharmaceutical composition containing two or three layers and contains an active principle in association with an excipient modifying its release and a system capable of generating carbon dioxide in a swelling polymer hydrophilic matrix. Examples are provided where the active principle is in one layer containing swellable polymers as the excipient modifying its release and the second layer contains swellable polymer in association with a carbonate. The composition is in the form of bilayer or trilayer tablets. The system does not however contain a part of the drug in immediate release form and a part in controlled release form and does not provide a biphasic release pattern.
PCT publication No. WO 01/10417 assigned to Galenix Development discloses and claims a pharmaceutical composition containing at least one phase comprising an active principle in association with one or many excipients and a second phase called non-active, consisting of at least one gas-generating system and at least one hydrophilic polymer or a porous mineral compound; and wherein the active phase comprises at least 80% active principle. The limitation of using not more than 20% of a release rate controlling excipient limits the flexibility that a formulator has for obtaining the desired rate of release while providing a higher level of assurance of reproducibility of the release profile from batch-to-batch. On the other hand when rate-controlling excipients are chosen judiciously such that they provide a highly reproducible release profile even when used in small amounts they may not be rapidly and highly swellable themselves. The system of WO 01/10417 uses the non-active phase to achieve floatation, which is achieved by a low density resulting from entrapment of carbon dioxide in the non-active phase matrix.

This patent is subject to a terminal disclaimer.

Gastric retention controlled drug delivery system

Sun Pharma Advanced Research Company Ltd.


An electronic apparatus includes an operation unit or a terminal device for inputting address information of the terminal device of a user who instructed execution of a job, and notification target information indicating whether the terminal device is a notification target to which an interruption of the job is to be notified, a network interface unit that performs data communication with a plurality of the terminal devices, and a controller that decides, when an interruption of the job is detected, whether the terminal device is the notification target, according to the notification target information, and causes the network interface unit to transmit interruption data indicating that the job has been interrupted to the terminal device, using the address information of the terminal device, when the terminal device is the notification target.

Recently, electronic apparatuses such as an image forming apparatus are given a function to notify a finish of a job to a terminal device, for example via E-mail, utilizing a communication protocol such as SMB or FTP. Such a function becomes available when the user registers E-mail address information, in advance of starting the job. The function enables the user to be aware that the job has been finished, thereby improving the convenience in use.
For example, Patent Literature (PTL) 1 discloses an image forming system that performs data communication with a terminal device. The system sets, when standby control information is received from the terminal device together with the job, a standby state for start of the job or a standby state for finish of the job, and transmits message information to the terminal device. Upon receipt of the message information, the terminal device notifies the user that the standby control has been set for the start of the job or finish of the job, according to the message information.

Electronic apparatus and image forming apparatus


A vehicle speed measuring method and apparatus which can cope accurately with several vehicle speed sensors which produce different numbers of pulses for one rotation. Such vehicle speed sensors prepared for the method and apparatus produce predetermined different numbers of pulses for one rotation, some of such sensors defining a group wherein such numbers of pulses have a greatest common divisor greater than 1. It is first determined whether or not a particular vehicle speed sensor employed belongs to this group of sensors. When the sensor belongs to the group, pulses therefrom are frequency divided by a value obtained by division of the number of pulses produced for one rotation of the sensor by the greatest common divisor, and time data indicative of the time of appearance of a pulse by frequency division are stored into a memory for one rotation of the sensor. A period for one rotation of the sensor is calculated from such stored time data, and a vehicle speed is calculated from the period and a distance over which the vehicle runs for one rotation of the sensor.

1. Field of the Invention
This invention relates generally to a method of and apparatus for measuring a speed of a vehicle in accordance with pulses generated by a vehicle speed sensor which is rotated in response to a movement of the vehicle, and more particularly to a method and an apparatus which is prepared to employ any one of a plurality of different types of vehicle speed sensors which produce different numbers of pulses for one full rotation thereof.
2. Description of the Prior Art
Digital vehicle speed measuring apparatus are conventionally known which record data of a movement of a vehicle including, for example, vehicle speed information in the form of a digital signal into a record medium. An exemplary one of such conventional digital vehicle speed measuring apparatus is shown in FIG. 7. Referring to FIG. 7, the conventional digital vehicle speed measuring apparatus shown includes a vehicle speed sensor 1 which may produce 4, 8, 10, 16, 20 or 25 pulses for one full rotation thereof depending upon a type thereof. The digital vehicle speed measuring apparatus further includes an interface (IF) 2 which shapes pulses generated by the vehicle speed sensor 1, a microcomputer (CPU=central processing unit) 3 which operates in accordance with a predetermined control program, a setting device 4 for setting a type of the vehicle speed sensor 1 by way of a combination of presence or absence of jumper lines, a display driver 5 for causing a digital display unit 6 to display thereon a vehicle speed transmitted from the CPU 3 which measures such vehicle speed in accordance with pulses from the vehicle speed sensor 1 and a set value from the setting device 4, and an external memory 7 for storing therein digital data representative of a vehicle speed measured by the CPU 3.
With the conventional digital vehicle speed measuring apparatus of the construction described above, the CPU 3 determines the type of the vehicle speed sensor 1 from a set value received from the setting device 4, and where the vehicle speed sensor 1 connected is of a type which produces 4, 8 or 10 pulses for one full rotation, the CPU 3 measures a period of a pulse and calculates a vehicle speed by calculation. On the other hand, where the vehicle speed sensor 1 connected is of another type which produces 16, 20 or 25 pulses for one full rotation, the CPU 3 sets a gate time in accordance with such pulse number of the sensor and measures a number of pulses which is produced by the vehicle speed sensor 1 for such gate time, and then calculates a vehicle speed from the number of pulses thus measured.
In order to perform such operation, the CPU 3 executes such jobs as illustrated in a flow chart of FIG. 8. Referring to FIG. 8, the CPU 3 starts its operation when power is made available, and at first step S1 of the operation, the CPU 3 receives a set value from the setting device 4. Then at step S2, the set value thus received is checked to judge whether or not the vehicle speed sensor 1 is of a type which produces 4, 8 or 10 pulses for one rotation. If the judgment is YES and the vehicle speed sensor 1 connected is of the type which produces 4, 8 or 10 pulses for one rotation, then a flag is set to "1" at step S3, but on the contrary if the judgment at step S2 is NO and the vehicle speed sensor 1 connected is of another type which produces 16, 20 or 25 pulses for one rotation, the flag is set to "0" at step S4, and then a gate time is set at step S5 in accordance with the type of the vehicle speed sensor 1 connected. After execution of the job at either of the steps S3 and S5, the control sequence advances to step S6 at which it is judged whether or not the flag is equal to "1".
If the judgment at step S6 is YES, then the control sequence advances to step S7 at which the CPU 3 waits a pulse to be received from the vehicle speed sensor 1 by way of the interface 2. After a pulse is received and the judgment at step S7 changes to YES, the control sequence advances to step S8 at which the count value of a free running counter which is constructed in the CPU 3 and incremented after lapse of each fixed interval of time by a clock of a fixed period is set as a capture value to a capture register also constructed in the CPU 3, whereafter the control sequence advances to step S9. At step S9, it is judged from the set value received at step S1 and representative of a type of the vehicle speed sensor 1 whether or not the vehicle speed sensor 1 is of the type which produces 4 pulses for one rotation. In case the judgment at step S9 is YES, the control sequence advances to step S10.
At step S10, contents of second to fifth ones T.sub.2 to T.sub.5 of eleven time registers T.sub.1 to T.sub.11 constructed in the CPU 3 are transferred to the first to fourth time registers T.sub.1 to T.sub.4, respectively, and at subsequent step S11, the capture value placed into the capture register at step S8 is transferred to the fifth time register T.sub.5. After then, the control sequence advances to step S12 at which a difference between contents of the first time register T.sub.1 and contents of the fifth time register T.sub.5, that is, T=T.sub.5 -T.sub.1, is taken to calculate a period T for one rotation of the vehicle speed sensor 1. After such calculation of a period T for one rotation of the vehicle speed sensor 1 at step S12, the control sequence advances to step S13 at which a vehicle speed is calculated by dividing a travel distance A of the vehicle for one rotation of the vehicle speed sensor 1 by the period T. Data calculated in this manner and indicative of a vehicle speed are inputted to the display driver (step S51), and consequently, such vehicle speed is displayed on the display unit 6. In addition, the data are also outputted to the external memory (step S52) so that they may be stored into the external memory 7.
In case the judgment at step S9 is NO, the control sequence advances to step S14 at which it is judged whether or not the vehicle speed sensor 1 is of the type which produces 8 pulses for one rotation. If the judgement is YES, then a period T is calculated at steps S15 to S17 in accordance with a similar algorism to that at steps S10 to S12 described hereinabove. After then, a vehicle speed is calculated at step S13 making use of the period T calculated in this manner. On the contrary if the judgment at step S14 is NO, it is determined that the vehicle speed sensor is of the type which produces 10 pulses for one rotation, and a period T is calculated subsequently at steps S18 to S20 in accordance with a similar algorism. After then, a vehicle speed is calculated at step S13 making use of the period T calculated in this manner.
On the other hand, in case the judgment at step S6 is NO and the vehicle speed sensor 1 connected is of any type which produces a number of pulses other than 4, 8 and 10 pulses for one rotation, the control sequence advances to step S21 at which the CPU 3 waits a pulse to be received from the vehicle speed sensor 1 by way of the interface 2. After a pulse is received and the judgment at step S21 changes to YES, the control sequence advances to step S22 at which a pulse counter constructed in the CPU 3 is incremented. After then, at step S23, it is judged whether or not the gate time set at step S5 has elapsed, and if the gate time has not yet elapsed, the control sequence returns to step S21 to repeat the jobs at step S21 and so forth. On the other hand, if the gate time has elapsed and the judgment at step S23 is YES, then the control sequence advances to step S24 at which a vehicle speed is calculated making use of the gate time, the count value of the pulse counter and so forth. Then at step S25, the count value of the pulse counter is cleared, whereafter the control sequence returns to step S21.
As described above, in the conventional digital vehicle speed measuring apparatus, where a vehicle speed sensor which produces 4, 8 or 10 pulses for one rotation is employed, a time necessary for the vehicle speed sensor to make one rotation, that is, a period, is measured, and then a vehicle speed is found out by calculation in accordance with the measured thus calculated. On the other hand, where another vehicle speed sensor which produces 16, 20 or 25 pulses for one rotation is employed, a number of pulses produced by the vehicle speed sensor for a gate time set in accordance with the type of the vehicle speed sensor is counted, and a vehicle speed is found out by calculation in accordance with the gate time, count value and so forth.
Consequently, since means for calculating a vehicle speed must be provided separately for different types of vehicle speed sensors as described hereinabove with reference to the flow chart of FIG. 8 and such calculating means cannot be used commonly for such different vehicle speed sensors, the conventional digital vehicle speed measuring apparatus is complicated in construction. Where a CPU which operates in accordance with a control program is employed as in the case of the conventional digital vehicle speed measuring apparatus described above, the control program involves a great number of steps for such calculation and a ROM (read only memory) for storing the control program therein must have a corresponding great storage capacity. Also, a RAM (random access memory) which is used as a working area must have a corresponding great storage capacity.
Further, since the gate time system is employed, where a high degree of accuracy of, for example, 0.1 km/h is required, the gate time is excessively long, and consequently, the responsibility is low. As a result, the digital vehicle speed measuring apparatus cannot be employed where such high accuracy is required.

Vehicle speed measuring method and apparatus


Ferricinium or ferricinium-based compounds are useful as blue redox dyes suitable for monitoring various enzymatic oxidation processes. A process for preparing such dyes is proposed which involves complexing ferrocene or its derivative with a cyclodextrin. The resulting yellow inclusion complex, an intermediate of the redox dye, is then oxidized electrochemically or by a reaction with bilirubin oxidase to form blue redox dyes which exhibit absorption peaks at 620 or 650 nm. Both the reduced form and the oxidized form of the dye are water-soluble.

Oxidase systems have been exploited for determination of various substrates for many years. For example, in the presence of oxygen the enzyme glucose oxidase catalyzes the oxidation of glucose by oxygen to gluconolactone (gluconic acid) and hydrogen peroxide; lactate is oxidized by lactate oxidase; glutamic acid is oxidized by glutamate oxidase, etc; hydrogen peroxide being the by-product of all these reactions.
The concentration of the substrate, e.g. glucose, can be followed by monitoring the concentration of H.sub.2 O.sub.2. For example, addition of enzyme peroxidase and a chromogenic oxygen acceptor, such as colorless o-dianisidine, results in the reaction of hydrogen peroxide and o-dianisidine with formation of a measurable color (oxidized o-dianisidine, brown, absorption at 500 nm). The method is not widely used because O-dianisidine is toxic. In any case, this approach requires more than one enzyme (oxidase and peroxidase). Alternatively, H.sub.2 O.sub.2 can be monitored by NADH peroxidase and the expensive cofactor, NADH (a reduced form of nicotinamide adenine dinucleotide).
It is desirable to eliminate the use of peroxidase. Also, the spectrophotometric determination of glucose in some body fluids or solutions with pronounced color faces serious difficulty because of color masking. Blue dyes are advantageous in this regard because their absorption peaks are distant from the bands characteristic of most biological fluids.
Water-insoluble ferrocene [bis(.eta..sup.5 -cyclopentadienyl)iron] and its derivatives have been studied by Cass, A. E. G. et al, Anal. Chem. 56, 667-671 (1984) and by Hill, H. A. O. et al, Biosensors, a Practical Approach (Cass, A. E. G., Ed.), pp. 19-46, IRL Press, Oxford (1990) to develop mediated amperometric biosensors because of their electron-exchange properties with various enzymes. To replace oxygen as an electron receptor, ferrocene must be first oxidized at a platinum or carbon electrode surface to ferricinium through the loss of one electron from the metal atom.
The ferricinium cation is water-soluble and able to react with several reduced oxidoreductases as follows: EQU Substrate+Enzyme.sub.ox .fwdarw.Enzyme.sub.red +Product (1) EQU 2 Ferricinium+Enzyme.sub.red .fwdarw.2 Ferrocene+Enzyme.sub.ox +2H.sup.+( 2)
The redox couple--ferrocene and ferricinium--exhibits a marked difference in UV-VIS absorption spectra. Ferrocene in 95% ethanol is yellow and features two wavelength bands at 325 and 440 nm. Ferricinium solutions exhibit a characteristic dichroism with an absorption peak at 620 nm, i.e. dilute solutions appear blue or green, while more concentrated solutions are blood red. Apparently, ferricinium or its derivatives could be used in spectrophotometric assays involving oxidoreductases if they can be prepared from water-soluble forms of ferrocenerelated compounds. However, ferrocene and its derivatives (except for carboxyl ferrocene) are virtually waterinsoluble.

Redox dye and method of preparation thereof using 2-hydroxypropyl-.beta.-cyclodextrin and 1,1'-dimethylferrocene


An apparatus permitting non-invasive electrical monitoring of the volume of flow of a fluid at relatively low pressures and flow rates. The apparatus comprises an analog flow gage having a housing with an inner flow chamber of upwardly increasing cross sectional area and a ball indicator received in the chamber. The flow chamber is in the shape of a cylinder with a plurality of longitudinal slits extending outwardly from the cylinder and equally radially spaced apart. Each of the slits has a wedge shaped tapered portion which accounts for the increasing cross sectional area of the chamber. The flow rate inside the chamber is directly linearly related to the amount of upward displacement of the ball indicator along the length of the tapered portions. The apparatus also includes associated electrical circuitry for providing infinite step position detection of the ball indicator, converting the analog position information into a digital output and displaying a digital readout of the accumulative volume of flow, scaled in cubic feet.

The present invention relates generally to the field of gas or liquid flow measurement devices used and, more particularly, to such devices which are especially useful for metering the volume of oxygen delivered to a patient from oxygen delivering equipment.
In certain medical situations it is desirable to deliver relatively high concentrations (approximately 98%) of oxygen to a patient. The period and course of administration of oxygen differs widely depending upon the precise situation, but can occur over extended periods of time, or over permanently. For medical reasons, it may be of interest to monitor the amount of oxygen which is delivered to the patient per unit time, such as minutes. For purposes of charging the patient for the use of the equipment, it is useful to meter the accumulative amount of oxygen delivered to the patient.
Due to the relatively low pressures and flow rates encountered in such situations (ranging usually from 1-10 p.s.i. and from 0.5-10 liters/min.), it is important for purposes of measurement accuracy to minimize any interruption of flow caused by the measuring device. Also, due to the fact that oxygen is highly explosive, the means by which measurement of flow volume is accomplished must be restricted to one which will not present a significant risk from this hazard.


A quick-release fastener for releasably attaching the head to the shaft of a lacrosse stick includes a fastener body and a tension pin, affixed to and extending through the fastener body, the tension pin including a compression spring and one or more end caps, the end caps protruding from one end, or two opposite ends, of the fastener body, and the tension pin being arranged such that when the end caps of the tension pin are compressed against the spring, the end caps are recessed into the fastener body.

1. Field of the Invention
The invention pertains to the field of sports equipment. More particularly, the invention pertains to a quick-release fastener for releasably attaching the head to the shaft of a lacrosse stick.
2. Description of Related Art
The game of lacrosse is considered to be the oldest team contact sport of North American origin. Historical evidence suggests that the game of lacrosse was played by various Indian tribes, such as the Iroquois and Hurons, as early in time as the 15th century. It generally is accepted that the original purpose of the sport of lacrosse was to physically and/or psychologically condition Indian warriors preparatory to actual combat or, in some instances, to itself function as a game forum for the settlement of tribal differences. While the equipment utilized in the sport of lacrosse has, of course, evolved substantially over the years, one all-important piece of equipment whose basic constructional characteristics have remained constant is the lacrosse stick or "crosse".
Since the inception of the sport, the lacrosse stick has comprised an elongate stick having a butt end and a forward end, and a head integral with or fixedly attached and coaxial to the forward end of said stick. Typically, the head comprises a frame including at least one side wall element extending forwardly of the forward end of the stick and in a laterally divergent manner from the center line thereof, and a nose element extending transversely across the forward end(s) of said side wall element(s), said nose element traversing the forwardly extended center line of said stick. The upper rim of said head frame defines an open mouth wherethrough the lacrosse ball is received into and shot, passed or checked from the lacrosse stick. In plan view, the head frame typically defines a generally isosceles triangular area extending coaxially and forwardly of the forward end of the stick. Generally, the rear portion of the head frame is arcuately formed, the radius of curvature of said rear portion being selected such that it defines an accommodating surface against which the lacrosse ball usually rests, while the ball is retained in the throat portion of the head frame. Suspended from the lower rim of the head frame is a netting defining a bottom closure of the frame.
With the decreasing availability of high-grade ash or hickory wood, decreasing availability of the woodworking skills necessary to form and fabricate lacrosse sticks having integral one-piece wooden stick/head frame constructions, and in further view of the labor intensive nature of the fabrication of such integral one-piece wooden stick/head frame constructions, it has become commonplace to fabricate lacrosse sticks using a straight stick or shaft element formed of straight grained wood or wood laminate or a tough, lightweight metallic or reinforced plastic tubular material, such as in the nature of a thin gauge metallic extrusion or a fiber reinforced composite plastic material, and to affix to the forward end of the shaft a separate head frame comprising a tough synthetic thermoplastic material, such as a high impact strength nylon material prepared and/or sold under the trademark, ZYTEL®, by DuPont de Nemours & Company, Inc., Wilmington, Del.
In such modem versions of a lacrosse stick, the head frame typically comprises a rearwardly oriented coaxial socket element to receive the forward end of the shaft therein. Typically, the head and shaft are fastened together at the junction thereof using a fastener, usually a screw, extending through a portion of the head and shaft at the junction, such as described in U.S. Pat. No. 3,910,578. Often, athletes also place tape around the junction of the head and shaft, for added safety to prevent the fastener from falling out.
Thus, the modem lacrosse stick, having a separate head and shaft, allows athletes to exchange the heads and shafts, such as in cases where the head or shaft becomes worn or damaged, or where a different head or shaft is desired for play or for various other reasons. Thus, often athletes exchange the head or shaft, even during a game. However, a screwdriver or other suitable implement typically is required to remove the screw, which also is relatively time-consuming, considering that often the exchange must be made during a brief time-out or between plays. Therefore, there is a long-standing need for a quick-release fastener for releasably attaching the head to the shaft of a lacrosse stick, allowing the head and shaft of a lacrosse stick to be quickly separated and exchanged, while still providing means for securely fastening the head and shaft during play.

Quick-release fastener for releasably attaching lacrosse stick head to shaft


Some embodiments provide a method for employing the management and control system of a network to dynamically recover from a split-brain condition in the edge nodes of the network. The method of some embodiments takes a corrective action to automatically recover from a split-brain failure occurred at a pair of high availability (HA) edge nodes of the network. The HA edge nodes include an active machine and a standby machine. The active edge node actively passes through the network traffic (e.g., north-south traffic for a logical network), while the standby edge node is synchronized and ready to transition to the active state, should a failure occur. Both HA nodes share the same configuration settings and only one is active until a path, link, or system failure occurs. The active edge node also provides stateful services (e.g., stateful firewall, load balancing, etc.) to the data compute nodes of the network.

In virtual networking, edge nodes handle the north-south traffic of one or more logical networks. In a multitenant datacenter, a logical network provides networking services to end machines (e.g., physical and virtual machines) of a tenant. An edge node can be a machine (physical or virtual machine) that connects a logical network to external networks (physical and/or logical networks). For providing high availability, some networks deploy a pair of active and standby edge appliances (e.g., gateways). High Availability (HA) ensures that the services provided by edge appliances are available even when a hardware or software failure renders a single appliance unavailable. One of the edges functions in active mode (i.e. actively forwards traffic and provides other logical network services), whereas the second edge node is in a standby state, waiting to take over should the active edge node fail. The active appliance maintains a heartbeat with the standby appliance and sends service updates through one or more internal interfaces (also referred to as HA interfaces).
When the active edge node is up and healthy but the two edge nodes cannot communicate with each other properly (e.g., a heartbeat is not received from the active edge node within a specified time), the standby edge node also declares itself as an active node. This scenario is known as split-brain. A split-brain can be a source of network disruption. For instance, the end virtual machines which require edge services (e.g., north bound routing, stateful services) might get the MAC address of either of the edge nodes (whichever responds first to an ARP request) since both edge nodes declared themselves as active nodes. As another example, when the edge nodes provide DHCP services, if both edge nodes are active and do not coordinate with each other, each edge node provides IP addresses to end machines that request for such independent of the other edge node. This could cause overlap in IP address assignments to the end machines (i.e., two end machines of the same network may have the same IP address). Typically, the edge nodes should be rebooted to resolve a split-brain failure.

Dynamic recovery from a split-brain failure in edge nodes


A refrigerator capable of supercooling a target liquid, housing a slush activation, and a control method thereof are provided. The refrigerator includes a temperature sensor which senses a temperature of the refrigerator's interior volume or of the target liquid therein and the temperature sensor is programmed to send warnings, alerts and messages to a user or as a default, activate a controller that cycles the compressor off and on to increase the temperature within the area where the ice nucleation and freezing is detected. In addition to a user-interactive warning system, a location system for a closed liquid container that is beginning to freeze is based on the detection of heat energy resulting from the exothermic crystallization reaction of a liquid that is beginning to freeze. A method, system and device is provided to prevent the unwanted occurrence of frozen, ruptured containers of supercooled liquid in closed containers. A refrigerator can have an inside compartment for chilling beverage containers to super cooled temperatures. A front door exterior port(s) on the refrigerator can be used for activating the slush formation from the super cooled liquid contents in the beverage containers. The front door exterior port can also be used as well for rapid chilling beverage containers to selected chilled temperatures with or with slush activation of the liquid contents in the beverage containers.

Supercooling is the process of lowering the temperature of a liquid or a gas below its freezing point without it becoming a solid. A liquid crossing its standard freezing point will crystallize in the presence of a seed crystal or nucleus around which a crystal structure can form creating a solid.
Freezing is almost always an exothermic process, meaning that as liquid changes into solid, heat and pressure are released. This is often seen as counter-intuitive since the temperature of the material does not rise during freezing, except if the liquid were supercooled. But this can be understood, since heat must be continually removed from the freezing liquid or the freezing process will stop. The energy released upon freezing is a latent heat, and is known as the enthalpy of fusion and is exactly the same as the energy required to melt the same amount of the solid.
Lacking any such nuclei, the liquid phase can be maintained all the way down to the temperature at which crystal homogeneous nucleation occurs. Homogeneous nucleation can occur above the glass transition temperature, but if homogeneous nucleation has not occurred above that temperature an amorphous (non-crystalline) solid will form.
Water normally freezes at 273.15 K (0° C. or 32° F.) but it can be "supercooled" at standard atmospheric pressure (15 psi) down to its crystal homogeneous nucleation at almost 224.8 K (−48.3° C./−55° F.). The process of supercooling requires that water be pure and free of nucleation sites, which can be achieved by processes like reverse osmosis, but the cooling itself does not require any specialised technique.
The melting of a solid above the freezing point, which is the opposite of supercooling, is much more difficult, and a solid will almost always melt at the same temperature for a given pressure. For this reason, it is the melting point which is usually identified, using a melting point apparatus; even when the subject of a paper is "freezing-point determination", the actual methodology is "the principle of observing the disappearance rather than the formation of ice".
Supercooling is often confused with freezing-point depression. Supercooling is the cooling of a liquid below its freezing point without it becoming solid. Freezing point depression is when a solution can be cooled below the freezing point of the corresponding pure liquid due to the presence of the solute; an example of this is the freezing point depression that occurs when sodium chloride is added to pure water.
Refrigerated glass-door beverage merchandisers have been used for many years to keep beverages chilled below room temperature yet above the freezing point of water (32 deg-F, 0 deg-C). In recent years, several beverage merchandiser manufacturers have introduced special refrigerated merchandisers (super-chillers) for beer and other alcoholic beverages that chill these items below the freezing point of water, with advertised chilling temperatures as low as 22-28 deg-F (−5.5 to −2 deg-C). Manufacturers claim these lower storage temperatures are possible due to the alcohol content of these beverages which lowers their freezing point (freezing point depression). These sub 32 deg-F storage temperatures are generally considered beneficial for beers and alcoholic beverages since the flavor is colder and the beverage stays colder longer during consumption than when stored above 32 deg-F. However, these new alcoholic beverage merchandisers generally do not allow storage temperatures below 22 deg-F (−5 deg-C) since the freezing point of most beer is between 24-28 deg-F depending on specific alcohol content. Thus the current temperature ranges generally available for commercial beverage merchandisers are between 22 deg-F and 50 deg-F (−5.5 to +10 deg-C).
One commercial application of supercooling is in refrigeration. For example, there are freezers that cool drinks to a supercooled level so that when they are opened, they form a slush. The SLUSH-IT!™ drinks mixer system uses stickers placed on the beverage which is then placed into a specially designed receptacle. The receptacle is then placed in a standard freezer. Another example is a product that can supercool the beverage in a conventional freezer. The Coca-Cola Company also briefly marketed special vending machines containing Sprite in the UK, and Coke in Singapore, which stored the bottles in a supercooled state so that their content would turn to slush upon opening. This system, however, requires the use of a specially designed bottle.
Thus, it has been known that non-alcoholic bottled and canned beverages of all varieties, including bottled water, can be supercooled below 32 deg-F (0° C.) while remaining liquid for short periods of time regardless of the various types of ingredients. What is not generally known is how to store these beverages indefinitely in a supercooled liquid state without allowing them to freeze solid.
When supercooling beverages, the liquid beverage is sensitive to temperatures even a few degrees below the set point which is a temperature within a range below the freezing point of the liquid and above the solid phase transition temperature. The sensitivity of a supercooled liquid beverage to temperatures below the set point can cause the liquid to nucleate inadvertently and begin to freeze.
A prior art reference, Chung et al., U.S. Pat. No. 8,572,990, discloses an apparatus for supercooling which stably maintains a liquid in a supercooled state below a phase transition temperature by mounting temperature sensors directly to tops of each container (i.e., such as a bottle) and applying energy to the surface of the liquid or contents or to a gas near the surface while the liquid is maintained in the supercooled environment.
The prior art references do not acknowledge and address one specific problem that occurs in the supercooling of liquids which is the fact that liquids held below a freezing point can and do inadvertently begin ice nucleation and freezing. The nucleation can have a domino effect meaning that several closed containers will begin to freeze.
Since a frozen can or bottle is undesirable in a supercooler; there is a need for a user-interactive method or system to obviate this condition and prevent inadvertent nucleation of supercooled liquids as provided by the present invention without mounting sensors directly to tops of the containers.
The present invention also contemplates a standard refrigerator that is customized to contain a supercooler unit or compartment and a slush activation device. The supercooler unit or compartment includes a user-interactive method or system of the present invention to warn and alert a user thus alleviating concerns for the inadvertent freezing of supercooled liquids stored in closed containers inside the refrigerator. The slush activation device is located in the front door of the refrigerator to safely and conveniently create a slush, icy beverage or drink in the home environment.

Precision supercooling refrigeration device


An improved word line driving circuit for a memory capable of decoding a free-decoded low address signal to an eternally applied voltage level and driving a word line using a power-up voltage level of a memory, thus advantageously achieving a low voltage consumption for driving a word line, which includes a decoder for decoding free-decoded first through third low address signals and an externally applied control signal and for outputting a decoding signal of a voltage level or a low level; a switch for outputting a free-decoded word line enable signal of a power-up voltage level or a low level switched in accordance with a decoding signal outputted from the decoder; a word line selector for outputting a word line selection signal of a power-up voltage and for selecting a word line in accordance with a word line enable signal outputted from the switch; and a word line stabilization circuit for stabilizing the level of a word line selected by the word line selector in accordance with a word line enable signal outputted from the switch.

1. Field of the Invention
The present invention relates to a word line driving circuit for a memory, and particularly to an improved word line driving circuit for a memory capable of decoding a flee-decoded low address signal to an externally applied voltage level and driving a word line using a power-up voltage level of a memory, thus advantageously achieving a low voltage consumption for driving a word line.
2. Description of the Conventional Art
Referring to FIG. 1, a first conventional word line driving circuit for a memory includes an NAND gate 100 for NANDing externally applied and free-decoded low address signal DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn and for outputting a logic signal of a power-up voltage V.sub.pp level or a low level, a latch 200 for delaying the logic signal outputted from the NAND gate 100 for a predetermined time and for outputting an inverted logic signal, an invertor 300 for inverting the logic signal outputted from the latch 200 and for outputting an inverted signal of a power-up voltage V.sub.pp level or a low level, a word line selector 400 for outputting a word line selection signal .phi.Xi free-decoded by the invertor 300 and for selecting a word line W/L, and a word line stabilization circuit 500 for stabilizing the level of a word line in accordance with the inverting signal .phi.XiB of the word line selection signal .phi.Xi.
The NAND gate 100 includes a PMOS transistor 51 having a source terminal connected to a power-up voltage V.sub.pp terminal and a gate terminal connected to an input line of a low address signal DRA.sub.ij, an NMOS transistor 52 having a drain terminal connected to the drain terminal of the PMOS transistor 51 and a gate terminal connected to the gate terminal of the PMOS transistor 51, an NMOS transistor 53 having a drain terminal connected to the source terminal of the NMOS transistor 52 and a gate terminal connected to the input line of the low address signal DRA.sub.kl, and an NMOS transistor 54 having a drain terminal connected to the source terminal of the NMOS transistor 53 and a gate terminal connected to the input line of the low address signal DRA.sub.mn.
The latch 200 includes a PMOS transistor 55 having a source terminal connected to the power-up voltage V.sub.pp terminal and a gate terminal connected to the common output line of the NAND gate 100, an NMOS transistor 56 having a drain terminal connected to the drain terminal of the PMOS transistor 55 and a gate terminal connected to the gate terminal of the PMOS transistor 55, and a PMOS transistor 57 having a source terminal connected to the power-up voltage V.sub.pp terminal and a gate terminal commonly connected to the PMOS transistor 55 and the NMOS transistor 56 and a drain terminal connected to the common output line of the NAND gate 100.
The invertor 300 includes a PMOS transistor 58 having a source terminal connected to the power-up voltage V.sub.pp terminal and a gate terminal connected to the common output line of the latch 200, and an NMOS transistor 59 having a drain terminal connected to the drain terminal of the PMOS transistor 58 and a gate terminal connected to the gate terminal of the PMOS transistor 58 and a source terminal connected to the ground voltage V.sub.ss terminal.
The word line selector 400 includes a PMOS transistor 60 having a source terminal connected to the input line of the word line selection signal .phi.Xi and a gate terminal connected to the common line of the invertor 300, and an NMOS transistor 61 having a drain terminal connected to the drain terminal of the PMOS transistor 60 and a gate terminal connected to the gate terminal of the PMOS transistor 60 and a source terminal connected to the ground voltage V.sub.ss.
The word line stabilization circuit 500 includes an NMOS transistor 500 having a drain terminal connected to the word line W/L and a gate terminal connected to the input line of the inverting signal .phi.XiB of the word line selection signal .phi.Xi.
In addition, referring to FIG. 2, a second conventional word line driving circuit for a memory includes an NAND gate 100' for NANDing free-decoded low address signals DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn and for outputting a logic signal of an external voltage V.sub.cc level or a low level, a latch 200' for delaying the level of the logic signal outputted from the NAND gate 100' and for outputting an inverted logic signal, an invertor 300' for inverting the logic signal outputted from the latch 200' and for outputting the invertor logic signal of a voltage V.sub.cc level, a level controller 600 for controlling the level of the logic signal outputted from the invertor 300' in accordance with the free-decoded word line selection signal .phi.Xi and the word line W/L, and a word line selector 400' for outputting a word line selection signal of a power-up voltage V.sub.pp level in accordance with a level of the logic signal controlled by the level controller 600 and for selecting a word line W/L.
The NAND gate 100' includes a PMOS transistor 71 having a source terminal connected to a voltage V.sub.cc terminal and a gate terminal connected to a low address signal DRA.sub.ij line, an NMOS transistor 72 having a drain terminal connected to the drain terminal of the PMOS transistor 71 and connected to a common output line and a gate terminal connected to the gate terminal of the PMOS transistor 71, an NMOS transistor 73 having a drain terminal connected to the source terminal of the NMOS transistor 72 and a gate terminal connected to the input line of the low address signal DRA.sub.kl, and an NMOS transistor 74 having a drain terminal connected to the source terminal of the NMOS transistor 73 and a gate terminal connected the input line of the low address signal DRA.sub.mn and a source terminal connected to a ground voltage V.sub.ss.
The latch 200' includes a PMOS transistor 75 having a source terminal connected to a voltage V.sub.cc and a gate terminal connected to a common output line of the NAND gate 100', an NMOS transistor 76 having a drain terminal connected to the drain terminal of the PMOS transistor 75 and connected to a common output line and a gate terminal connected to the gate terminal of the PMOS transistor 75 and a source terminal connected to the voltage V.sub.cc, and a PMOS transistor 77 having a source terminal connected to the power V.sub.cc and a gate terminal connected to a common output line of the PMOS transistor 75 and the NMOS transistor 76 and a drain terminal connected to a common output line of the NAND gate 100'.
The invertor 300' includes a PMOS transistor 78 having a source terminal connected to the voltage V.sub.cc and a gate terminal connected to a common output line of the latch 200', and an NMOS transistor 79 having a drain terminal connected to the drain terminal of the PMOS transistor 78 and a gate terminal connected to the gate terminal of the PMOS transistor 78 and a source terminal connected to the voltage V.sub.ss
The level controller 600 includes an NMOS transistor 80 having a drain terminal connected to a common output line of the invertor 300' and a gate terminal connected to the input line of the word line selection signal .phi.Xi, and a PMOS transistor 81 having a source terminal connected to a power-up voltage V.sub.pp and a gate terminal connected to a word line W/L and a drain terminal connected to the source terminal of the NMOS transistor 80 and connected to the common output line.
The word line selector 400' includes a PMOS transistor 82 having a source terminal connected to a power-up voltage V.sub.pp terminal and a gate terminal connected to a common output line of the level controller 600, and an NMOS transistor 83 having a drain terminal connected to the drain terminal of the PMOS transistor 82 and a gate terminal connected to the gate terminal of the PMOS transistor 82 and a source terminal connected to a ground voltage V.sub.ss.
In addition, referring to FIG. 3, a third conventional word line driving circuit for a memory includes an NAND gate 700 for NANDing free-decoded low address signals DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn and for outputting a logic signal of a power-up voltage V.sub.pp level and a low level, an invertor 702 for inverting the logic signal outputted from the NAND gate 700 to a power-up voltage V.sub.pp level or a low level, an invertor for inverting the logic signal inverted by the invertors 701 and 702, respectively, and for outputting a free-decoded word line selection signal .phi.Xi and for selecting a word line W/L.
The NAND gate 700 includes a PMOS transistor 101 having a source terminal connected to a power-up voltage V.sub.pp terminal and a gate terminal connected to an input line of the low address signal DRA.sub.ij, a PMOS transistor 102 having a source terminal connected to the source terminal of the PMOS transistor 101 and a gate terminal connected to the output terminal of the invertor 701 and a drain terminal connected to the drain terminal of the PMOS transistor 101, an NMOS transistor 103 having a drain terminal connected to a common output line of the drain terminals of the PMOS transistors 101 and 102 and a gate terminal connected to the gate terminal of the PMOS transistor 101, an NMOS transistor 104 having a drain terminal connected to the source terminal of the NMOS transistor 103 and a gate terminal connected to the input line of a free-decoded low address signal DRA.sub.lk, and an NMOS transistor 105 having a drain terminal connected to the source terminal of the NMOS transistor 104 and a gate terminal connected to the input line of a free-decoded low address signal DRA.sub.mn and a source terminal connected to a ground voltage V.sub.ss.
The word line selector 703 includes a transmission gate TM for transmitting a flee-decoded word line selection signal .phi.Xi to a word line W/L in accordance with a logic signal outputted from the invertors 701 and 702, and an NMOS transistor 108 for controlling the level of the word line selection signal .phi.Xi transmitted to the word line W/L in accordance with a logic signal outputted from the invertor 702.
The transmission gate TM includes a PMOS transistor 106 having a source terminal connected to the input line of the word line selection signal .phi.Xi and a gate terminal connected to the output line of the invertor 702, and an NMOS transistor 107 having an NMOS transistor 107 having a drain terminal connected to the source terminal of the PMOS transistor 106 and a gate terminal connected to the output line of the invertor 701 and a source terminal connected to the drain terminal of the PMOS transistor 106 and commonly connected to the word line W/L and the NMOS transistor 108.
The operation of the first word line driving circuit for a memory will now be explained.
To begin with, low address signals DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn are applied to each gate terminal of the PMOS transistor 51, the NMOS transistor 52, and the NAND gates 53 and 54 of the NAND gate 100, respectively.
Thereafter, the PMOS transistor 51 is turned on and the NMOS transistor 52 is turned off in accordance with a low address signal DRA.sub.ij of a low level commonly applied to the gate terminals, and the NMOS transistor 53 is turned off in accordance with a low address signal DRA.sub.kl of a low level applied thereto, and the NMOS transistor 54 is mined off in accordance with a low address signal DRA.sub.mn of a low level applied thereto.
Therefore, since a high level signal of a power-up voltage V.sub.pp level is outputted through the PMOS transistor 51 and the NMOS transistor 52, the node N1 outputs a high level signal of the power-up voltage V.sub.pp.
Thereafter, the PMOS transistor 55 and the NMOS transistor 56 of the latch 200 each are turned off and turned on in accordance with the power-up voltage V.sub.pp level applied to the node V1 and output the low signal through a common lie.
Therefore, a low signal is applied to a node N2.
The PMOS transistor 57 of the latch 200 receives the low signal from the node N2 through the gate terminal thereof and is turned on and outputs a high level signal of a power-up voltage V.sub.pp through the drain terminal thereof, and a high level signal of a power-up voltage V.sub.pp level is checked at the node N1.
In addition, since the high level signal of a power-up voltage V.sub.pp level is commonly applied to the gate terminals of the PMOS transistor 55 and the NMOS transistor 56, respectively, the PMOS transistors 55 and 57 and the NMOS transistor 56 of the latch 200 become alternately activated, so that a high level signal of a power-up voltage V.sub.pp level can be checked at the node N1 for a predetermined time.
Thereafter, since the PMOS transistor 58 and the NMOS transistor 59 of the invertor 300 each are turned on and turned off i accordance with a low signal outputted from the latch, high level signals of a power-up voltage V.sub.pp level is outputted from the PMOS transistor 58 and the NMOS transistor 59, so that a high level signal of a power-up voltage V.sub.pp can be checked at a node N3.
Thereafter, the PMOS transistor 60 and the NMOS transistor 61 of the word line selector 300 each are turned on and turned on in accordance with a high level signal of a power-up voltage V.sub.pp applied to the node 3.
Therefore, low level signals are outputted from the PMOS transistor 60 and the NMOS transistor 61 through a common output line, and the NMOS transistor 62 of the word line stabilization circuit 500 is turned on in accordance with a word line selection signal .phi.Xi and an inverting signal .phi.Xib applied thereto, so that the word line W/L does not become activated.
Thereafter, when low address signals DRA.sub.ij, DRA.sub.kl and DRA.sub.mn of a high level are applied to the PMOS transistor 51, the NMOS transistor 52, and the NMOS transistors 53 and 54, respectively, the PMOS transistor 51 and the NMOS transistor 52 are turned off and turned on, respectively, in accordance with a low address signal DRA.sub.ij of a high level commonly applied to the gate terminals thereof.
In addition, the NMOS transistor 53 is turned on in accordance with a low address signal DRA.sub.kl of a high level applied to its gate terminal, and the NMOS transistor 54 is turned on in accordance with a low address signal DRA.sub.mn of a high level applied to its gate terminal.
Therefore, a low level signal is outputted through the PMOS transistor 51 and the NMOS transistor 52, and a low level signal is checked at the node N1.
Thereafter, the PMOS transistor 55 and the NMOS transistor 56 are turned on and turned off in accordance with a low level signal outputted from the node 1 and output a high level signal of a power-up voltage V.sub.pp level.
Therefore, the a high level signal of a power-up voltage V.sub.pp level is checked at the node N2.
In addition, since the PMOS transistor 57 is turned off in accordance with a high level signal of a power-up voltage V.sub.pp level, and a low level signal is checked at the node N1.
Thereafter, the PMOS transistor 58 and the NMOS transistor 59 are turned off and turned on, respectively, in accordance with a high level signal of the power-up voltage V.sub.pp level checked at the node N2 and output a low level signal through a common output terminal. In addition, a low level signal is checked at the node N3.
Thereafter, the PMOS transistor 60 and the NMOS transistor 61 are turned on and turned off i accordance with a low signal checked at the node N3, and the NMOS transistor 62 is turned off in accordance with an inverting signal .phi.XiB of a word line selection signal .phi.Xi of a low level signal, and a word line selection signal of a high level outputted through a common output line of the PMOS transistor 60 and the NMOS transistor 61 is outputted and a word line W/L is driven in accordance with the word line selection signal outputted therefrom.
The operation of a second conventional word line driving circuit for a memory will now be explained with reference to FIG. 2.
To begin with, when low address signals DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn of a low level are applied to the PMOS transistor 71, the NMOS transistor 72 and the NMOS transistors 73 and 74 of the NAND gate 100', respectively, the PMOS transistor 71 and the NMOS transistor 72 are turned on and turned off, respectively, in accordance with a low address signal DRA.sub.ij of a low level signal commonly applied to the gate terminals thereof.
In addition, the NMOS transistor 73 is turned off in accordance with a low address signal DRA.sub.kl of a low level signal applied to its gate terminal, and the NMOS transistor 74 is turned off in accordance with a low address signal of a low level applied to its gate terminal.
Therefore, a high level signal of a voltage V.sub.cc is outputted from the PMOS transistor 71 and the NMOS transistor 72 through a common output line thereof, and a high level signal of a power-up voltage V.sub.pp is checked at a node N11.
Thereafter, the PMOS transistor 75 and the NMOS transistor 76 of the latch 200' are turned off and mined on, respectively, in accordance with a high level signal of a voltage V.sub.cc level checked at the node N11. Therefore, a low level signal is checked at a node N12.
In addition, the PMOS transistor 77 of the latch 200 is turned on in accordance with a low level signal checked at the node N12, and a high level signal of a voltage V.sub.cc level is checked at the node N11.
Therefore, since the high level signal of a voltage V.sub.cc at the node NIl is commonly applied to the gate terminals of the PMOS transistor 75 and the NMOS transistor 76, the PMOS transistors 75 and 77 and the NMOS transistor 76 alternately become activated, and a high level signal of a voltage V.sub.cc i checked at the node N11 for a predetermined time.
Thereafter, the PMOS transistor 78 and the NMOS transistor 79 of the invertor 300' are turned on and turned off, respectively, in accordance with a low level signal checked at the node N12 and output a high level signal of a voltage V.sub.cc level to the common output line thereof.
The NMOS transistor 80 of the level controller 600 is turned on in accordance with a word line selection signal .phi.Xi of a high level signal and output a high level signal of a voltage V.sub.cc through the common output line of the PMOS transistor 78 and the NMOS transistor 79.
Therefore, a high level signal of a voltage V.sub.cc is checked at a node N13.
The PMOS transistor 82 and the NMOS transistor 83 of the word line selector 400' are turned off and turned on, respectively, in accordance with a high level signal of a voltage V.sub.cc checked at the node N13 and output a low level signal through the common output line thereof.
Thereafter, the PMOS transistor 81 of the level controller 600 is turned on in accordance with a low level signal outputted from the PMOS transistor 82 and the NMOS transistor 83 and apply a high level signal of a power-up voltage V.sub.pp to the node N13, and the high level signal of a voltage V.sub.cc checked a the node N13 is convened into a high level signal of a power-up voltage V.sub.pp.
In addition, since the high level signal converted into the power-up voltage V.sub.pp level is commonly applied to the PMOS transistor 82 and the NMOS transistor 83, a low level signal is outputted to the word line W/L through the common output line of the PMOS transistor 82 and the NMOS transistor 83, so that the word line W/L is not driven.
Thereafter, when low address signals DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn of a high level are applied to the PMOS transistor 71, the NMOS transistor 72, and the NMOS transistors 73a and 74, respectively, the PMOS transistor 71 and the NMOS transistor 72 are turned off and turned on in accordance with a low address signal DRA.sub.ij.
In addition, the NMOS transistor 73 is turned on in accordance with a low address signal DRA.sub.kl of a high level, and the NMOS transistor 74 is turned on in accordance with a low address signal DRA.sub.mm of a high level applied to its gate terminal.
Therefore, a low level signal is checked at the node N1 since a low level signal is outputted from the PMOS transistor 71 and the NMOS transistor 72 through the common output line.
Thereafter, the PMOS transistor 75 and the NMOS transistor 76 are turned on and turned off, respectively, in accordance with a low level signal checked at the node N11 and output a high level signal of a voltage V.sub.cc.
Therefore, a high level signal of a voltage V.sub.cc is checked at the node N12.
In addition, the PMOS transistor 77 is turned off in accordance with a high level signal of a voltage V.sub.cc level checked at the node N12, and a low level is checked at the node N11 for a predetermined time.
Thereafter, the PMOS transistor 78 and the NMOS transistor 79 are turned off and turned on in accordance with a high level signal of a voltage V.sub.pp level checked at the node N12 and output a low level signal through the common output terminal, respectively.
The NMOS transistor 80 is turned on in accordance with a word line selection signal .phi.Xi applied thereto for a predetermined time, and a low level signal is checked at the node N13.
Therefore, the PMOS transistor 82 and the NMOS transistor 83 are tamed on and turned off, respectively, in accordance with a low level signal checked at the node N13, and output a high level signal of a power-up voltage V.sub.pp level.
The PMOS transistor 81 is mined off in accordance with a high level signal of a power-up voltage V.sub.pp level outputted from the common output line of the PMOS transistor 82 and the NMOS transistor 83, and a low level signal is checked at the node N13.
A power-up voltage V.sub.pp is checked at the PMOS transistor 82 and the NMOS transistor and applied to the word line W/L, so that the word line W/L is driven.
Next, the operation of a third conventional word line driving circuit for a memory will now be explained.
To begin with, when low address signals DRA.sub.ij, DRA.sub.kl and DRA.sub.mn of a low level are applied to the PMOS transistor 101 and the NMOS transistor 103 and the NMOS transistors 104 and 105 of the NAD gate 700, respectively, the PMOS transistor 101 and the NMOS transistor 103 are mined on and turned off, respectively, in accordance with a low address signal DRA.sub.ij of a low level applied to the gate terminals thereof.
In addition, the NMOS transistor 104 is tamed off in accordance with a low address signal DRA.sub.kl of a low level applied to its gate terminal, and the NMOS transistor 104 is turned off in accordance with a low address signal DRA.sub.mn of a low level applied to its gate terminal.
Therefore, the PMOS transistor 101 and the NMOS transistor 103 output a high level signal of a power-up voltage V.sub.pp , respectively, through the common output line thereof, and the high level signal of the power-up voltage V.sub.pp level is inverted by the invertor 701, and a low level signal is checked at a node N22.
In addition, the PMOS transistor 102 is turned on i accordance with a low level signal checked at the node N22, and a high level signal of a power-up voltage V.sub.pp level is continually applied to the input line of the invertor 700, and a low level signal is checked at the node N22 for a predetermined time.
Thereafter, the invertor 702 inverts the low level signal outputted from the invertor 701 to the high level signal of a power-up voltage V.sub.pp level.
The transmission gate TM of the word line selector 703 is turned off in accordance with a low level signal and a high level signal outputted from the invertors 701 and 702, respectively, and cuts the signal input thereto of the word line signal .phi.Xi.
That is, the PMOS transistor 106 of the transmission gate TM receives a high level signal of a power-up voltage V.sub.pp outputted from the invertor 702 through its gate terminal, and the NMOS transistor 107 is turned off in accordance with a low level signal outputted from the invertor 701.
In addition, the word line selector 703 is turned on in accordance with a high level signal of a power-up voltage V.sub.pp outputted from the invertor 702, and a low level signal is applied to the word line W/L, so that the word line W/L is not driven.
Thereafter, when low address signals DRA.sub.ij, DRA.sub.kl, and DRA.sub.mn are applied to the gate terminals of the PMOS transistor 101, the NMOS transistor 103 and the NMOS transistors 104 and 105, respectively, the PMOS transistor 101 and the NMOS transistor 103 are turned off and turned on, respectively, in accordance with a high level signal applied to the gate terminals thereof.
In addition, the NMOS transistor 104 is turned on in accordance with a low address signal DRA.sub.kl of a high level applied to the gate terminal thereof, and the NMOS transistor 105 is turned on in accordance with a low address signal DRA.sub.mn of a high level applied to the gate terminal thereof.
Therefore, a low signal is outputted through the common output line of the PMOS transistor 101 and the NMOS transistor 103 and inverted into a high level signal of a power-up voltage V.sub.pp by the invertor 701, and a high level signal of a power-up voltage V.sub.pp is checked at the node N22.
In addition, the PMOS transistor 102 is turned off in accordance with a high level signal of a power-up voltage V.sub.pp checked at the node N22, and a low level signal is continuously applied to the input line of the invertor 701, and a high level signal of a power-up voltage V.sub.pp level is checked at the node N22 continuously, and a low level signal is inverted by the invertor 702.
The PMOS transistor 106 and the NMOS transistor 107 are turned on in accordance with a low level signal and a high level signal, respectively, outputted from the invertors 702 and 701, and the NMOS transistor 108 is turned off in accordance with a low level signal outputted from the invertor 702, and a word line selection signal .phi.Xi is applied to the word line W/L, and the word line W/L is driven.
However, as described above, the conventional word line driving circuit for a memory has disadvantages in that when increasing an externally supplied voltage, an over load of a power-up voltage occurs because of using an externally applied power-up voltage so as to drive a word line, so that the power-up voltage becomes unstable due to errors or noise, thus disadvantageously increasing electric power consumption.


A drive configuration for driving one or more rotating sprockets (e.g., of an engine drive train), including a flexible force transmitting member forming a closed curve enclosing an area; a drive sprocket situated outside the area and driving the force transmitting member; first and second pulleys situated at least partially within the area and on opposing sides of the drive sprocket so as to urge the force transmitting member against the drive sprocket; and one or more driven sprockets each coupled to the force transmitting member. The drive configuration may include a cartridge including a base, one or more secondary pulleys being situated on opposing sides of the first pulley such that a timing belt is urged into contact with a drive sprocket and each of the pulleys. Accordingly, a timing belt may be rapidly installed or removed by inserting or removing the cartridge according to the present invention.

Typically, vehicles use a timing belt or a timing chain to operate one or more camshafts and/or other accessories (e.g., oil and/or water pumps, balance shafts, etc.). Timing belts are preferred over timing chains for many reasons. For example, timing belts cost less and emit less noise than conventional timing chains when used in automobiles and other vehicles. Moreover, timing belts do not require lubrication and initially cost less than a timing chain. However, timing belts have a limited life span and typically require replacement in as little as 25,000 miles (as opposed to timing chains which can last for the life of the vehicle).
Because of high replacement cost, timing belts are usually neglected until they fail. However, timing-belt failure can lead to engine failure-especially in interference-type engines.
In addition to the fact that timing belts require more frequent replacement, this replacement can be tedious (and require many hours of work). For example, engine mounts, various pulleys and/or accessories such as power steering pumps, air conditioning compressors, alternators, etc. and/or their associated belts, pulleys, wiring, etc. must be removed to gain access to one or more timing belt covers which must be removed to gain access to the timing belt cavity. Thereafter, one or more tensioners, idler pulleys, water pumps, etc. must be adjusted and/or removed so that the timing belt can be removed and replaced. This process can take several hours and can be further complicated when an engine is of a V- or H-type configuration and/or includes a double overhead camshaft (DOHC) arrangement (as opposed to single overhead camshaft (SOHC) arrangement). Accordingly, timing-belt replacement costs can range from several hundred to a thousand dollars or more, of which only a few dollars is attributable to the cost of parts. Thus, consumers are inconvenienced and mechanics, as opposed to manufacturers, reap most of the profits from timing-belt replacement procedures.
A front view diagram illustrating a conventional timing belt arrangement in a DOHC (double overhead cam) inline engine configuration is shown in FIG. 1. For the sake of clarity, components such as a timing-belt cover, alternator, air conditioning (A/C) compressor, hydraulic pumps and their associated drive belts and/or associated pulleys and/or sprockets are not shown. A timing belt 10 is driven by a crankshaft sprocket (whose teeth are not shown for the sake of clarity) 12 and drives one or more camshaft sprockets (whose teeth are also not shown for the sake of clarity) 14 and 16 and may also drive one or more accessories (e.g., oil pump, balance shaft, etc.) 20. A tensioner pulley 18 provides tension to the timing belt 10. A front engine cover (aka an engine front cover) 26 which, for the sake of this discussion, can include all or part the engine's cylinder block, cylinder head, oil pan, front engine case, cylinder-head cover, water pump, oil pump, other elements, and/or combinations thereof, forms at least a part of a cavity for protecting the timing belt 10 (and associated components such as the pulleys, tensioners, balance belts, etc.) from being contaminated by the elements. The other part of the cavity may be formed, for example, by one or more timing-belt covers, etc. which, for the sake of clarity, are not shown. As shown, in a typical front-wheel-drive transverse-engine layout, a side motor mount 24 may be attached to the front engine cover 26 (and/or engine block and/or cylinder head). However, for the sake of clarity, throughout this application, a front engine cover will be referenced. A fluid passage 28 provides a means for transferring fluid to/from the engine. For example, as shown, the fluid passage 28 is a coolant passage for transferring coolant to/from a water pump (not shown) which is mounted adjacent to the fluid passage 28. As shown in the present application, it will be assumed that the crankshaft sprocket 12 rotates in a clockwise direction. However, other directions are also envisioned.
Typically, after the timing-belt (or belts) is installed, the one or more timing belt covers are used to protect the timing belt from the elements. Then, other components such as pulleys (e.g., a crankshaft pulley, harmonic balancer, etc.) are attached to an exposed end of the crankshaft (not shown). The crankshaft pulley is used to drive accessories such as the water, air and/or power-steering/hydraulic pumps, alternator, A/C compressor, etc. using one or more accessory drive belts.
Moreover, as typical timing-belt installation is complicated, timing belts are often incorrectly installed. Accordingly, it is not uncommon for components (such as cams, balance shafts, etc.) to be misaligned (i.e., mistimed) which can adversely affect fuel economy, timing, engine life, balance (e.g., resulting in vibration), and can lead to unexpected engine failure—which can occur at critical times. Moreover, improper tensioning, can allow a timing belt to skip, which can also result in unexpected failure (e.g., of the belt and the engine) and lead to a dangerous situation. For example, when a driver accelerates to cross a busy three-lane boulevard, if a timing belt skips cogs when the driver begins to accelerate, the engine can stall and leave the vehicle unexpectedly in the path of oncoming traffic.
Furthermore, because of high timing-belt replacement costs, used car values are affected by mileage and/or age (e.g., 5 years or 60,000 miles), which corresponds with timing belt replacement intervals. Moreover, because of these high costs, owners may avoid changing the timing belts (and related components) at recommended intervals, which can lead to unexpected engine failure. Further, typical variable valve timing systems adjust a rotational angle of a camshaft relative to a corresponding cam sprocket which is attached to the camshaft. This system typically requires a large number of parts which increases cost and the likelihood of failure. Moreover, typical variable valve timing systems require high-oil pressure (e.g., 1700 psi) lines for proper operation.
Accordingly, there is a need for an apparatus and a method for easily replacing timing belts in vehicles that avoid the problems and disadvantages of the prior art.