The present invention relates to diamond targets for carbon K x-ray generators and to a method for exposing x-ray sensitive resists to carbon K x-rays using an x-ray generator with a diamond target. It has been discovered that diamond targets, preferably of Type IIb diamond, will dissipate considerably more power and thus produce higher intensity x-rays than graphite targets despite diamond's lower limiting temperature. Such x-rays allow one to expose an x-ray resist through a mask in only 67 seconds and achieve a resolution of 0.2.mu..

In the field of electronics an important goal has been to reduce the size of semiconductor devices and increase the number of electronic components which can be reliably placed on a given semiconductor chip. Recently developed devices such as magnetic bubble circuits have created renewed impetus for manufacturers to develop lithography techniques with improved resolution capabilities for making increasingly smaller features at reduced cost. The aim is to improve lithography resolution to the submicron range, and ultimately to only a few hundred angstroms. D. Maydan, G. A. Coquin, J. R. Maldonado, S. Somekh, D. Y. Low, and G. N. Taylor, "High Speed Replication of Submicron Features on Large Areas by X-Ray Lithography", IEEE Trans on Electron Devices, ED-22, 429, (1975)
Current assembly line techniques use a photo lithography process whereby a polymeric resist on a semiconductor chip is exposed through a mask to visible or ultraviolet wavelength radiation. Practically speaking, these processes are limited to making component features with a minimum size of about 2.mu. (2.times.10.sup.-4 cm). Exposure times are in the range of 20-60 sec. By the process of electron beam lithography, using focused electron beams, devices have been made with features in the submicron range but because the electron beam must be scanned in the desired pattern to expose each spot of resist in the pattern, such processes are inherently slow and expensive. T. H. P. Chang and W. C. Nixon, "Limits of Electron-Beam Nonthermal Interactions", Rec. 9th Symp. Electron, Ion, and Laser Beam Tech., 123 (1967); E. D. Wolf, F. S. Ozdemir, W. E. Perkins, and P. J. Coane, "Response of the Positive Electron Resist Elvacite 2041 to Kilovolt Electron Beam Exposure", Rec. 11th Symp. Electron, Ion, and Laser Beam Tech., 331 (1971); M. Hatzakis and A. N. Broers, "Electron-Beam Techniques for Fabricating Fine Metal Lines", Rec. 11th Symp. Electron, Ion, and Laser Beam Tech., 337 (1971); "Team Produces 80 A Metal Lines", Industrial Research, 19, No. 1, 19 (1977).
X-Ray lithography, because of the small wavelength of x-rays, has the potential to produce resist patterns of extremely high resolution i.e. with a minimum feature size to be measured in angstroms. A resolution of 200 A (200.times.10.sup.-8 cm) represents a factor of 100 improvement in resolution over photo lithography techniques. This means that the density of components in semiconductor devices may theoretically be improved by a factor of 100.sup.2.
X-Ray lithography has the additional advantages of being a one shot process, as opposed to electron beam techniques, and the ability to make deep patterns. This technique has the further, unique advantage of being much less sensitive to dust particles in the manufacturing environment for the reason that the x-rays tend to pass through such particles.
In an x-ray lithography process a substrate having an x-ray sensitive resist layer is exposed through a mask (consisting, for example, of Mylar with a heavy metal pattern deposited thereon) to soft x-rays; i.e. x-rays having wavelengths of greater than about 5 A (5.times.10.sup.-8 cm) or wave energies of less than about 2.48 keV. The resist is developed using a suitable solvent, and steps such as doping of the semiconductor substrate, deposition of conductive layers, or etching of the semiconductor substrate may follow. See: D. L. Spears, H. I. Smith and E. Stern, "X-Ray Replication of Scanning Electron Microscope Generated Patterns", Fifth Int. Conf. on Electron and Ion Beam Tech., 80 (1972); D. Maydan et al supra; Henry I Smith and S. E. Bernacki, "Prospects for X-Ray Fabrication of Si IC Devices", J. Vac. Sci. Technol., Vol. 12, No. 6, November/December 1975; D. L. Spears and H. I. Smith, "X-Ray Lithography--A New High Resolution Replication Process", Solid State Technol., 15, No. 7, 21 (1972). By way of example, the substrate used may be a silicon chip to be made into a semiconductor integrated circuit, or a glass blank to be made into a diffraction grating.
Optimum resolution depends in part on the thickness of metal used in the mask. The method of making very high resolution masks currently in use is electron beam lithography. In making such a mask, Mylar (polyethylene terephthalate film) is coated with a resist which is scanned in the desired pattern with an electron beam. The resist is developed in a suitable solvent and a heavy metal, (usually gold) which is substantially opaque to x-rays is deposited. The mask at this stage has metal deposited on the Mylar in the desired pattern and metal deposited on the remaining resist material which must be removed. A second solvent removes the resist/metal layer leaving only the desired metal pattern on Mylar. In order for the second solvent to work effectively there must be discontinuities in the metal layer at the edges of the pattern. Practical experience has shown that the ratio of the thickness of the metal to the minimum dimension of the pattern ought to be no greater than 1:1. This is known as the aspect ratio. While thinner metal layers permit smaller features, the metal must still be thick enough to effectively block or absorb the radiation. Although x-rays in the 5-15 A range have been used with good success at low cost, R. Feder, E. Spiller and J. Topalian, "Replication of 0.1 .mu.m Geometries with X-Ray Lithography", J. Vac. Sci. Technol., 12, 1332 (1975), because of the above considerations in designing the mask, they are too hard, relatively speaking, to provide optimum resolution.
Because of the softness of the characteristic x-ray emitted, and because of graphite's ability to withstand high temperatures in a vacuum, carbon, with a characteristic wavelength of 44.7 A (50.times.10.sup.-8 cm) and wave energy of 0.277 keV has been recognized as an ideal source for x-ray lithography. R. Feder et al, supra. The ultimate obtainable resolution for carbon sources is about 50 A (50.times.10.sup.-8 cm) but graphite anodes suffer the disadvantages of producing inadequate x-ray intensity. For exposure of a suitable resist such as polymethyl methacrylate (PMMA) with x-rays from a graphite anode, the exposure time is measured in hours. Thus graphite is not well suited for production line manufacturing techniques with the result that very high density semiconductor devices are necessarily very expensive.
In addition to being inadequate x-ray sources for x-ray lithography, carbon sources suffer other disadvantages brought out by attempts to maximize the x-ray output. In producing x-rays, a suitable target is bombarded with charged particles, such as electrons, of sufficient power to cause the target to emit x-rays. Only a small fraction of the energy of the ions is converted to x-rays, the remainder being converted to heat. In order to maximize the power of the charged particle beam being applied to the target, and consequently maximize the intensity of the emitted x-rays, a cooling means is provided for the target to carry away the excess heat. In the case of graphite anodes, this may involve means for rotating the target at high speed and cooling the anode with a fluid such as water. Since the device is operated in a vacuum and the target is rotating, expensive seals are required to keep the cooling water contained in the proper passages and to protect the vacuum. The seals and mechanical equipment tend to be unreliable and expensive.
For x-ray lithography to be competitive, the x-ray source must provide both high resolution and fast throughput at low cost.
It is an object of this invention to provide a device which produces carbon K x-rays of high intensity.
A further object of the present invention is to provide an x-ray device which produces high intensity carbon K x-rays without the need for rotating the anode or for expensive and unreliable coolant seals.
Another object of the present invention is to provide an extremely high resolution method of exposing x-ray sensitive resists.
A further object of this invention is to provide a method for exposing x-ray sensitive resists requiring only a relatively short exposure time.
An additional object of this invention is to provide a very high resolution method of exposing x-ray sensitive resists.
A further object of this invention is to provide a very high resolution method for exposing x-ray resists adaptable to assembly line techniques used in making semiconductor devices.

Diamond targets for producing high intensity soft x-rays and a method of exposing x-ray resists


An automatic exposure control system for a full-frame copier controls the illumination of a flash lamp in response to the reflectivity of a document to be reproduced. A photodetector senses exposure at the wall of a light housing and after sufficient exposure is reached, the light source is turned off (quenched). A compensation circuit anticipates the total energy emitted after quench (representing an over exposure potential) and terminates the light source energizing pulse so as to produce only desired exposure without over-exposure error.

The present invention relates to an automatic exposure control system for copier systems which utilize flash exposure of a document. More particularly, it relates to a control and compensation circuit which senses the amount of radiant energy reflected from the object onto walls of an optical housing while exposure of a photosensitive material is occurring and terminates the flash after sufficient exposure level is reached.
When an object is reproduced, either photographically or electrophotographically, by flash exposure of a light sensitive material, the density of the object (dark and light highlights) must be determined in some manner so that compensation can be made to maintain exposure uniformity. Prior art efforts to control exposure automatically are reflected in numerous publications. In photographic applications, an automatic exposure control for an electronic flash unit typically includes a light meter and electronic circuitry which detects the instantaneous amount of light reflected from the scene to be photographed onto the light sensitive element of the light meter. The light meter contains circuitry which integrates the signal derived from the light detecting element. When the integrated signals enter a predetermined level corresponding to required film exposure the flash is extinguished. Representative of various such arrangements are U.S. Pat. No. Re. 28,783; U.S. Pat. Nos. 3,350,604; 3,756,132; 3,776,112; 3,783,336 and 4,132,925.
In addition, various exposure control circuits are known in the photographic art which vary reference voltage with respect to time. The most relevant of these are disclosed in U.S. Pat. Nos. 3,737,721; 3,774,072; 3,985,440 and 4,101,812.
These photographic systems operate over relatively large dynamic ranges (compared to copiers) and the exposure control circuits are typically designed to tolerate errors upwards of 25% (1/4 f/stop). An exposure control system, in order to obtain uniform exposure of a photoreceptor, must be considerably more accurate; in the order of .+-.6% error, or better. Some representative automatic exposure control systems in a copying environment are disclosed in U.S. Pat. Nos. 3,985,440; 3,998,547; 4,017,180; 4,093,376 and 3,947,117. While these control systems reduce exposure errors considerably, they either require complex circuitry to implement or do not reduce exposure errors to the small tolerances required to produce increasingly upgraded copy quality.

Exposure compensation circuit for a copier


The present invention relates to blowing agent compositions for polymeric foams that contain carbon dioxide and a hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher and lower than about 120xc2x0 C. The present invention also relates to processes for preparing polymeric foam using such blowing agent compositions, foamable polymer compositions containing such blowing agents, and polymeric foams containing such blowing agent compositions.

1. Field of the Invention
The present invention relates to blowing agent compositions containing carbon dioxide (CO2) and a normally-liquid hydrofluorocarbon (HFC), foamable polymer compositions comprising a polymer and such blowing agent compositions, the use of such compositions for preparing polymeric foam, and polymeric foam containing residuals of the blowing agent composition. A normally-liquid HFC has a boiling point of 14xc2x0 C. or higher, preferably 30xc2x0 C. or higher, and lower than about 120xc2x0 C. at one atmosphere of pressure.
2. Description of Related Art
CO2 is an attractive blowing agent for preparing polymeric foam because it does not contribute to volatile organic compound (VOC) emissions and poses little, if any, risk to the Earth""s ozone layer. However, as a sole blowing agent, CO2 tends to produce polymeric foam having a higher percentage of open cells, smaller cell sizes, and a higher thermal conductivity than is desirable, particularly for thermal insulating applications. Furthermore, polymeric foams having infrared blockers such as carbon black are difficult to make using only CO2 as a blowing agent.
Hydrofluorocarbons (HFCs) are also attractive blowing agent components, particularly for preparing thermally insulating polymeric foams. HFCs are increasingly attractive as replacements for hydrochlorofluorocarbons (HCFCS) and chlorofluorocarbons (CFCs), which can contribute to ozone depletion. As with CO2, HFCs pose little, if any, risk to the Earth""s ozone layer. Furthermore, HFCs have a thermal conductivity lower than most polymers or blowing agents (other than HCFCs and CFCs) so HFC residuals in a polymeric foam can lower the foam""s thermal conductivity.
Typically, HFCs in blowing agent compositions have a boiling point of 14xc2x0 C. or less (HFC(g)). Unfortunately, HFC(g)s permeate out of polymeric foam and escape into the atmosphere, which can result in both an increase in the foam thermal conductivity and organic emissions.
A need exists in the art of blowing agents for a composition that is safe for the environment and produces thermally insulating polymeric foam. Preferably, the composition contains a HFC that remains in polymeric foam longer than HFC(g)s thereby slowing or reducing thermal conductivity increases and organic emission levels experienced when using HFC(g)s. More preferably, the composition comprises CO2 and a HFC that at least partially compensates for CO2 deficiencies.
xe2x80x9cHydrofluorocarbonxe2x80x9d and xe2x80x9cHFCxe2x80x9d are interchangeable terms and refer to an organic compound containing hydrogen, carbon, and fluorine. The compound is substantially free of halogens other than fluorine.
xe2x80x9cBoiling pointxe2x80x9d refers to the boiling point at one atmosphere pressure.
xe2x80x9cNormally-gaseous materialxe2x80x9d refers to a material that has a boiling point lower than 14xc2x0 C.
xe2x80x9cNormally-liquid hydrofluorocarbonxe2x80x9d, xe2x80x9cnormally-liquid HFCxe2x80x9d, and xe2x80x9cHFC(l)xe2x80x9d are interchangeable terms and refer to a HFC that has a boiling point of 14xc2x0 C. or higher and lower than about 120xc2x0 C.
xe2x80x9cNormally-gaseous hydrofluorocarbonxe2x80x9d, xe2x80x9cnormally-gaseous HFCxe2x80x9d, and xe2x80x9cHFC(g)xe2x80x9d are interchangeable terms and refer to a HFC that has a boiling point lower than 14xc2x0 C.
xe2x80x9cLow-boiling alcoholxe2x80x9d and xe2x80x9cLBAxe2x80x9d are interchangeable terms and refer to an alcohol having a boiling point lower than about 120xc2x0 C.
xe2x80x9cLow-boiling carbonyl compoundxe2x80x9d and xe2x80x9cLBCxe2x80x9d are interchangeable terms and refer to an aldehyde or a ketone having a boiling point lower than about 120xc2x0 C.
xe2x80x9cLow-boiling hydrocarbonsxe2x80x9d and xe2x80x9cLBHsxe2x80x9d are interchangeable terms and refer to hydrocarbons having a boiling point lower than 55xc2x0 C., including halogenated hydrocarbons.
xe2x80x9cLow-boiling ethersxe2x80x9d and xe2x80x9cLBEsxe2x80x9d are interchangeable terms and refer to ethers having a boiling point lower than 55xc2x0 C., including halogenated ethers.
xe2x80x9cFreshxe2x80x9d refers to within one month, preferably within one week, more preferably within one day, still more preferably within one hour, most preferably immediately after manufacture.
A polymeric foam or blowing agent composition that is xe2x80x9cessentially freexe2x80x9d of a specified component or components refers, respectively, to a polymeric foam or blowing agent composition that contains ten weight-percent (wt %) or less, preferably five wt % or less, more preferably one wt % or less, still more preferably 0.5 wt % or less, most preferably zero wt % of the specified component(s) based, respectively, on foam or blowing agent composition weight.
A blowing agent composition xe2x80x9cconsisting essentially ofxe2x80x9d a specified component or components is free from any unspecified components at concentrations that modify how the composition performs in preparing polymeric foam. Commonly, a blowing agent composition xe2x80x9cconsisting essentially ofxe2x80x9d a specified component or components refers to a composition that contains 90 wt % or more, preferably 95 wt % or more, more preferably 99 wt % or more, still more preferably 99.5 wt % or more, most preferably 100 wt % of the specified component(s). Wt % is relative to weight of blowing agent composition.
In a first aspect, the present invention is a blowing agent composition comprising: (a) carbon dioxide; and (b) at least one hydrofluorocarbon having a boiling point of 30xc2x0 C. or higher and lower than about 120xc2x0 C.; said composition being essentially free of low-boiling ethers and low-boiling hydrocarbons other than (b). 1,1,1,3,3-pentafluorobutane is a preferred hydrofluorocarbon in the first aspect.
In a second aspect, the present invention is a blowing agent composition comprising: (a) carbon dioxide; and (b) at least one hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher and lower than about 120xc2x0 C.; wherein greater than 50 weight-percent of the composition is carbon dioxide and wherein a sufficient amount of (b) is present to produce a polymeric foam having an improved skin quality, lower open cell content (according to ASTM method D-6226), larger average cell size, improved skin quality, or any combination thereof relative to the same foam prepared using only carbon dioxide as a blowing agent. Preferably, at least one hydrocarbon in (b) of the second aspect is 1,1,1,3,3-pentafluorobutane.
One preferred embodiment of the second aspect further comprises: (c) at least one hydrofluorocarbon having a boiling point lower than 14xc2x0 C.; and (d) at least one additional blowing agent selected from water, alcohols, ketones and aldehydes; said alcohols, ketones and aldehydes having a boiling point lower than about 120xc2x0 C. at atmospheric pressure.
The first and second aspects of the invention can further comprise additional blowing agents selected from water and alcohols having a boiling point lower than about 120xc2x0 C, particularly ethanol.
In a third aspect, the present invention is a blowing agent composition consisting essentially of carbon dioxide and one hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher and lower than about 120xc2x0 C. Carbon dioxide is preferably liquefied in each of the embodiments of the first three aspects.
In a fourth aspect, the present invention is a process for preparing polymeric foam comprising expanding a foamable polymer composition in a process suitable for forming a polymeric foam using a blowing agent composition selected from a group consisting of the blowing agent compositions of the first three aspects.
In a fifth aspect, the present invention is a polymeric foam comprising: (a) a polymer having cells defined therein; (b) carbon dioxide; and (c) at least one hydrofluorocarbon having a boiling point of 30xc2x0 C. or higher and lower than about 120xc2x0 C.; wherein at least a portion of (b) and (c) resides in said cells and said polymeric foam is essentially free of any low-boiling ethers or low-boiling hydrocarbons other than the hydrofluorocarbon (c).
In a sixth aspect, the present invention is a polymeric foam comprising: (a) a polymer having cells defined therein; (b) carbon dioxide; (c) at least one hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher and lower than about 120xc2x0 C.; (d) at least one hydrofluorocarbon having a boiling point lower than 14xc2x0 C.; (e) at least one additional blowing agent selected from water, alcohols, ketones, and aldehydes; said alcohols, ketones and aldehydes having a boiling point lower than about 120xc2x0 C.; and (f) an infrared blocker selected from a group consisting of carbon black, graphite, gold, aluminum, and titanium dioxide; wherein at least a portion of (b), (c), (d), and (e) reside in said cells and (f) is dispersed in said polymer.
Blowing agent components usually migrate from within polymeric foam and air migrates into polymeric foam over time. Therefore, preferably characterize polymeric foams within the time frame set forth by xe2x80x9cfreshxe2x80x9d, most preferably immediately after manufacture of the foam. Blowing agents have less of an opportunity to escape from a foam and air has less of an opportunity to migrate into a foam within the xe2x80x9cfreshxe2x80x9d time frame.
In a seventh aspect, the present invention is a foamable polymer composition comprising a thermoplastic polymer having dispersed therein a blowing agent composition selected from a group consisting of the blowing agents of the first three aspects of the present invention.
In an eighth aspect, the present invention is a foamable polymer composition comprising a thermoplastic polymer having dispersed therein an infrared blocker and a blowing agent composition that comprises carbon dioxide and a hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher.
The present invention addresses a need in the art for a blowing agent composition that is safe for the environment and produces a thermally insulating polymeric foam. The composition contains a HFC(l), which tends to remain in polymeric foam longer than HFC(g)s, slowing or reducing thermal conductivity increases and organic emission levels experienced when using HFC(g)s.
This invention relates to a blowing agent composition comprising CO2 and a HFC(l). Some embodiments of the present invention may also comprise additional blowing agents.
Blowing agent compositions of the present invention contain an amount of CO2 from greater than zero wt % up to, but not including, 100 wt % based on blowing agent composition weight. Herein, CO2 in a blowing agent composition is preferably liquefied CO2. The concentration of CO2 is generally greater than 20 wt %, preferably greater than 30 wt %, more preferably greater than 40 wt %, and most preferably greater than 50 wt %, based on blowing agent composition weight.
Blowing agent compositions that are mostly (greater than 50 wt % based on blowing agent composition weight) CO2 are desirable because CO2 is a readily available material that is safe for Earth""s atmosphere. However, experience shows that preparing thermoplastic foams using a blowing agent composition that is mostly CO2 is difficult to process, often resulting in a foam having poor foam skin quality and an open-cell structure. Foams having poor skin quality have an unacceptable level of surface irregularities such as cracks, stretch marks, and ripples. Fabrication of thermoplastic foams containing infrared blockers, such as graphite and carbon black, are particularly challenging with a CO2 blowing agent and often results in foams with smaller cell sizes, higher percentage of open cells, and/or more highly fractured skin surfaces than foams prepared without the infrared blockers.
The present invention is the result of discovering that including at least one HFC(l) with CO2 can overcome the difficulties associated with a CO2 blowing agent. Surprisingly, including one part per hundred or more, preferably two parts or more, more preferably three parts or more HFC(l), by weight of a polymer resin, in a CO2 blowing agent composition is generally sufficient to prepare a polymeric foam that has better skin quality (fewer surface irregularities), larger average cell size, lower open-cell content, or any combination thereof as compared to the same foam prepared using only CO2 as a blowing agent.
HFC(l)s are also particularly desirable in preparing thermally insulating foam. HFCs, in general, have a lower thermal conductivity than polymers. Therefore, residual HFC in a polymeric foam typically lowers the foam""s thermal conductivity relative to a similar polymeric foam without the residual HFC. HFC(l)s have a lower vapor pressure than HFC(g)s, therefore they tend to permeate out of polymeric foam less readily than HFC(g)s. As a result, blowing agent compositions containing an HFC(l) produce a polymeric foam that demonstrates a slower thermal conductivity increase over time than a polymeric foam prepared using a HFC(g) instead of HFC(l). Furthermore, because HFC(l)s tend to remain in a foam longer than HFC(g)s, they contribute less to organic emissions than HFC(g)s. HFC(l)s are also easier to handle than normally-gaseous materials because of their lower vapor pressure. For example, pressure liquefaction commonly used for normally-gaseous materials is not necessary for HFC(l)s.
HFC(l)s suitable for use in the present invention include any HFC having a boiling point of 14xc2x0 C. or higher, preferably 30xc2x0C. or higher, and lower than about 120xc2x0 C. Examples of suitable HFC(l)s include aliphatic compounds such as 1,1,1,3,3-pentafluoropropane (HFC-245fa), 1,1,1,3,3-pentafluorobutane (HFC-365mfc), 1-fluorobutane, nonafluorocyclopentane, perfluoro-2-methylbutane, 1-fluorohexane, perfluoro-2,3-dimethylbutane, perfluoro-1,2-dimethylcyclobutane, perfluorohexane, perfluoroisohexane, perfluorocyclohexane, perfluoroheptane, perfluoroethylcyclohexane, perfluoro-1,3-dimethyl cyclohexane, and perfluorooctane; as well as aromatic compounds such as fluorobenzene, 1,2-difluorobenzene; 1,4-difluorobenzene, 1,3-difluorobenzene; 1,3,5-trifluorobenzene; 1,2,4,5-tetrafluorobenzene, 1,2,3,5-tetrafluorobenzene, 1,2,3,4-tetrafluorobenzene, pentafluorobenzene, hexafluorobenzene, and 1-fluro-3-(trifluoromethyl)benzene. Aromatic HFCs may be especially compatible with aromatic polymers and, as a result, remain within polymeric foam prepared with an aromatic polymer longer than non-aromatic HFCs. Therefore, aromatic HFCs may be attractive for use with aromatic polymers. In general, HFC-365mfc and HFC-245fa are preferred due to their increasing availability and ease of use, with HFC-365mfc more preferred because it has a higher boiling point than HFC-245fa. The HFC(l)s having a boiling point higher than 30xc2x0 C., such as HFC-365mfc, are particularly desirable because they do not require liquefaction during foam processing.
Additionally, within the blowing agent compositions of the present invention, the HFC(l) preferably has a boiling point of 30xc2x0 C. or higher if the composition comprises CO2 and only one HFC(l); and the composition is essentially free of low-boiling ethers and low-boiling hydrocarbons other than the HFC(l).
The HFC(l) in a blowing agent composition can have a boiling point of 14xc2x0 C or higher to about 120xc2x0 C. if: (a) greater than 50 wt % of the blowing agent composition is CO2, and the composition contains at least one HFC(l); (b) greater than 50 wt % of the composition is CO2 and the composition further comprises a HFC having a boiling point lower than 14xc2x0 C. and at least one additional blowing agent selected from water, low-boiling alcohols and low boiling carbonyl compounds; or (c) the composition consists essentially of CO2 and one HFC.
The concentration of HFC(l), relative to the total weight of blowing agent composition, is greater than zero wt %, typically one wt % or more, preferably two wt % or more, more preferably three wt % or more; and typically 95 wt % or less. Above 95 wt %, excessive polymer plasticization occurs, yielding poor polymeric foam. The concentration of HFC(l) relative to the blowing agent composition, for example, can be 5 wt % or more, 10 wt % or more, 25 wt % or more; 50 wt % or more wt %, or 75 wt % or more as desired.
The blowing agent composition may further comprise at least one additional blowing agent. Additional blowing agents are useful for reducing polymeric foam density by increasing total moles of blowing agent. Preferably, additional blowing agents allow one to increase moles of blowing agent without suffering from at least one of the following: decreased cell size, increased density, decreased dimensional stability, and increased cost.
Additional blowing agents include physical and chemical blowing agents. Suitable physical blowing agents include water; HFC(g)s such as methyl fluoride, difluoromethane (HFC-32), perfluoromethane, ethyl fluoride (HFC-161), 1,1-difluoroethane (HFC-152a), 1,1,1-trifluoroethane (HFC-143a), 1,1,2,2-tetrafluoroethane (HFC-134), 1,1,1,2-tetrafluoroethane (HFC-134a), pentafluoroethane (HFC-125), perfluoroethane, 2,2-difluoropropane (HFC-272fb), 1,1,1-trifluoropropane (HFC-263fb), and 1,1,1,2,3,3,3 -heptafluoropropane (HFC-227ea); inorganic gases such as argon, nitrogen, and air; organic blowing agents such as aliphatic hydrocarbons having from one to nine carbons (C1-C9) including methane, ethane, propane, n-butane, isobutane, n-pentane, isopentane, neopentane, cyclobutane, and cyclopentane; fully and partially halogenated aliphatic hydrocarbons having from one to four carbons (C1-C4); and aliphatic alcohols having from one to five carbons (C1-C5) such as methanol, ethanol, n-propanol, and isopropanol; carbonyl containing compounds such as acetone, 2-butanone, and acetaldehyde. Suitable chemical blowing agents include azodicarbonamide, azodiisobutyronitrile, benzenesulfo-hydrazide, 4,4-oxybenzene sulfonyl semi-carbazide, p-toluene sulfonyl semi-carbazide, barium azodicarboxylate, N,Nxe2x80x2-dimethyl-N,Nxe2x80x2-dinitrosoterephthalamide, trihydrazino triazine and sodium bicarbonate. Preferred additional blowing agents include LBAs such as methanol, ethanol, and isopropanol; LBCs such as acetone, 2-butanone, and acetaldehyde; water; and HFC(g)s.
In general, the concentration of any individual additional blowing agent is desirably below the solubility limit of that blowing agent in the polymer, taking into account the presence of the rest of the blowing agent composition. A skilled artisan can, without undue experimentation, determine appropriate amounts of additional blowing agents for a given blowing agent composition. Additional blowing agents can comprise 20 wt % or less, more generally 30 wt % or less, still more generally 40 wt % or less, most generally 60 wt % or less of the blowing agent composition. The blowing agent composition can be substantially free of any additional blowing agent.
HFC(l), CO2, and any additional blowing agents account for 100 wt % of the blowing agent composition.
One example of a suitable blowing agent composition has 30 wt % to 70 wt % (inclusive) HFC-365mfc with the balance to 100 wt % being CO2.
Another example of a suitable blowing agent composition is 20-30 wt % HFC-365mfc, and the balance to 100 wt % being CO2 and at least one additional blowing agent (preferably HFC-134a, ethanol, or a mixture thereof).
The present invention further relates to a process for preparing a polymeric foam by expanding a polymer in a process suitable for forming a polymeric foam and using a blowing agent composition of the present invention. Typically, the blowing agent composition is present at a concentration, by weight relative to polymer weight, of greater than zero parts per hundred (pph) and less than or equal to 20 pph. Blowing agent compositions above 20 pph, based on polymer, produce polymeric foam having undesirable properties such as higher densities than desired for insulation applications. The concentration of blowing agent composition, based on polymer weight, desirably is 4 pph or more, preferably 5 pph or more; and 18 pph or less, preferably 15 pph or less, more preferably 12 pph or less.
Any conventional blown foam process is suitable for preparing a polymeric foam using the blowing agent composition of this invention. Generally, prepare a polymeric foam by plasticizing a polymer (typically heat plasticizing a thermoplastic polymer), incorporating therein a blowing agent composition at an initial pressure to form a foamable polymer composition, exposing the foamable polymer composition to a foaming pressure that is lower than the initial pressure, and allowing the foamable polymer composition to expand into a polymeric foam. Normally, plasticize a thermoplastic polymer by heating it to a processing temperature at or above the polymer""s glass transition temperature, forming a heat plasticized polymer composition. Add the blowing agent composition to the heat plasticized polymer composition to form a foamable polymer composition. Add components of the blowing agent composition individually or in any number of combinations. Incorporate the blowing agent composition into the plasticized polymer composition by a batch or continuous process, such as mixing with an extruder or mixer blender. The initial pressure is sufficient to prevent substantial expansion of the foamable polymer composition and to generally disperse the blowing agent therein. The initial pressure is often greater than atmospheric pressure (760 mm of mercury). Either reduce the pressure around the foamable polymer composition to a foaming pressure or transport the foamable polymer composition into a foaming zone at a foaming pressure to initiate expansion of the foamable polymer composition into a foam. The foaming pressure is less than the initial pressure and can be above or below atmospheric pressure, but is typically atmospheric pressure. The foaming pressure is sufficiently low to allow the blowing agent composition to expand the foamable polymer composition.
Cooling the heat plasticized foamable polymer composition below the processing temperature prior to exposing the foamable polymer composition to the foaming pressure can improve polymeric foam properties. One may cool the foamable polymer composition in an extruder or other mixing device or in separate heat exchangers.
A skilled artisan recognizes there are many variations of the general procedure as well as other ways to prepare polymeric foam that are suitable within the present invention. For example, U.S. Pat. No. 4,323,528, herein incorporated by reference, discloses a process for making polyolefin foams via an accumulating extrusion process. The accumulating extrusion process comprises: 1) mixing a thermoplastic material and a blowing agent composition to form a foamable polymer composition; 2) extruding the foamable polymer composition into a holding zone maintained at a temperature and pressure that precludes foaming; the holding zone has a die defining an orifice opening into a zone of lower pressure at which the foamable polymer composition foams and an openable gate closing the die orifice; 3) periodically opening the gate and, substantially concurrently, applying mechanical pressure by means of a movable ram on the foamable polymer composition to eject it from the holding zone through the die orifice into the zone of lower pressure, and 5) allowing the ejected foamable polymer composition to expand to form the polymeric foam.
Suitable polymers for use in the present invention include thermoplastic polymers, particularly those from a group consisting of vinyl aromatic polymers such as polystyrene; rubber-modified vinyl aromatic polymers such as high impact polystyrenes (HIPS); vinyl aromatic copolymers such as styrene/acrylonitrile or styrene/butadiene; hydrogenated vinyl aromatic polymers and copolymers such as hydrogenated polystyrene and hydrogenated styrene/butadiene copolymers; alpha-olefin homopolymers such as low density polyethylene, high density polyethylene and polypropylene; linear low density polyethylene (an ethylene/octene-1 copolymer) and other copolymers of ethylene with a copolymerizable, mono-ethylenically unsaturated monomer such as an alpha-olefin having from 3 to 20 carbon atoms; copolymers of propylene with a copolymerizable, mono-ethylenically unsaturated monomer such as an alpha-olefin having from 4 to 20 carbon atoms, copolymers of ethylene with a vinyl aromatic monomer, such as ethylene/styrene interpolymers; ethylene/propylene copolymers; copolymers of ethylene with an alkane such as an ethylene/hexane copolymer; thermoplastic polyurethanes (TPU""s); and blends or mixtures thereof, especially blends of polystyrene and an ethylene/styrene interpolymer.
Other suitable polymers include polyvinyl chloride, polycarbonates, polyamides, polyimides, polyesters such as polyethylene terephthalate, polyester copolymers and modified polyesters such as polyethylene terephthalate-glycol (PETG), phenol-formaldehyde resins, thermoplastic polyurethanes (TPUs), biodegradable polysaccharides such as starch, and polylactic acid polymers and copolymers.
The polymer is preferably polyethylene (PE), polystyrene (PS), polypropylene (PP), a blend of PS and an ethylene/styrene interpolymer (ESI), a blend of ESI and PE, a blend of ESI and PP, a blend of PS, PE and ESI or a blend of ESI with any one or more polyolefin or ethylene/alpha-olefin copolymers, terpolymers or interpolymers produced using a metallocene catalyst or a constrained geometry catalyst (such as The Dow Chemical Company""s INSITE(copyright) catalysts, INSITE is a trademark of The Dow Chemical Company). A more preferred polymer is PS.
Foamable polymer compositions can include additional additives, such as those that are common for use in preparing blown polymeric foam. Examples of suitable additional additives include pigments, viscosity modifiers, flame retardants, infrared blockers (such as those selected from a group consisting of carbon black, graphite, gold, aluminum, and titanium dioxide), nucleating agents, permeation modifiers, and extrusion aids. Additional additives typically become dispersed within the polymer.
The present invention still further relates to a blown polymeric foam containing residuals from the blowing agent composition including a HFC(l) and CO2. The polymeric foam may further contain additional blowing agents when they are included in the blowing agent composition. One may identify the presence of a HFC(l), CO2, and any additional blowing agents using standard analytical techniques, such as gas chromatography. Polymeric foams of the present invention are particularly useful as thermal insulators.
Polymeric foams of the present invention may take any physical configuration know in the art, such as sheet, plank, or coalesced, parallel strands and sheets. The polymeric foam is preferably a plank, more preferably a plank having a cross-section of 30 square centimeters (cm2) or more and a cross-section thickness in a minor dimension of 0.25 inch (6.4 millimeters (mm)) or greater, more preferably 0.375 inch (9.5 mm) or greater, and still more preferably 0.5 inch (12.7 mm) or greater. A polymeric foam having a minor dimension of up to 8 inches (200 mm) is possible. The upper limit for the minor dimension is limited by foaming equipment limitations. Given large enough equipment, a minor dimension above 8 inches (200 mm) is conceivable.
Polymeric foams of the present invention preferably have a density of 10 kilograms per cubic meter (kg/m3) or greater, normally 25 kg/m3 or greater; and 100 kg/m3 or less, normally 45 kg/m3 or less. Foams having a density below 10 kg/m3 generally lack a desired structural integrity. Polymeric foam of the present invention may have a density up to, but not including, that of a combination of the polymer and additives used in preparing the foam.
Polymeric foam of the present invention can be open-celled (having greater than 20% open-cell content) or close-celled (having less than 20% open-cell content), but foam that has less than 10 percent open-celled content is preferable because it generally has a lower thermal conductivity than a more open-celled foam. Measure open-cell content according to American Society for Testing and Materials (ASTM) method D2856-A. Typically, a polymeric foam of the present invention has a thermal conductivity 90 days after preparation (as determined according to standard method EN28301 using a sample temperature of 10xc2x0 C.) of 35 milliwatt per meter-Kelvin (mW/mxc2x7K) or less, preferably 33 mW/mxc2x7K or less.
Polymeric foams of the present invention have an average cell size greater than 0.05 millimeters (mm), preferably greater than 0.075 mm, more preferably greater than 0.1 mm, and less than 2 mm, preferably less than 1.2 mm. Determine average cell size using ATSM method D3576 with the following modifications: (1) image a foam using optical or electron microscopy rather than projecting the image on a screen; and (2) scribe a line of known length that spans greater than 15 cells rather than scribing a 30 mm line.

Blowing agent composition and polymeric foam containing a normally-liquid hydroflurocarbon and carbon dioxide

Abstract: Suitable blowing agent combinations include: (a) a composition containing carbon dioxide and at least one hydrofluorocarbon having a boiling point of 30xc2x0 C. to about 120xc2x0 C. that is essentially free of other low boiling ethers and hydrocarbons; (b) a composition containing greater than 50 weight-percent carbon dioxide and at least one hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher to about 120xc2x0 C.; and (c) carbon dioxide and one hydrofluorocarbon having a boiling point of 14xc2x0 C. or higher and lower than about 120xc2x0 C.


In a semiconductor integrated circuit device, at least one I/O cell can be disposed in a desired position within a chip. The semiconductor integrated circuit device includes an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to the center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.

The present invention relates to a semiconductor integrated circuit device in which an I/O cell can be disposed in a desired position within a chip, a design method for the same and a computer-readable recording medium in which an I/O cell library is recorded.
Recently, a development to build a whole system on one chip, namely, a system on chip technique, has been advanced. As a result, in accordance with increase in scale of semiconductor integrated circuits, the number of pins included in a semiconductor integrated circuit tends to increase.
In order to cope with the increased number of pins, a semiconductor integrated circuit device using bumps arranged in the form of a matrix within a chip, namely, area bumps, has been proposed. Furthermore, as a result of the appearance of the area bumps, a technique to provide I/O cells to be connected to the area bumps in desired positions within the chip has been proposed.
Now, a conventional semiconductor integrated circuit device having an area bump structure disclosed in Japanese Laid-Open Patent Publication No. 5-218204 will be described with reference to FIG. 13. Herein, an internal circuit cell means a basic cell in a gate array type semiconductor integrated circuit and a standard cell in a standard cell type semiconductor integrated circuit.
As is shown in FIG. 13, bumps (area bumps) 11 are arranged in the form of a matrix within a chip 10, and an I/O cell 12 is disposed below each bump 11 in the chip 10 so as to be inserted between cell lines 13 corresponding to lines of internal circuit cells (not shown), namely, so as to be buried between the internal circuit cells.
Furthermore, an internal circuit cell region RCELL where the internal circuit cells are arranged extends over the entire chip 10.
In the semiconductor integrated circuit device using the area bumps, however, since the I/O cells are inserted in the internal circuit cell region, the area of the internal circuit cell region is increased, which increases the total line length of inter-cell wires (wires for connecting the internal circuit cells to each other and wires for connecting the internal circuit cells to the I/O cells). Therefore, propagation delay time of signals is increased in the entire semiconductor integrated circuit (LSI), which causes a problem of a low operation speed of the LSI.
In consideration of the aforementioned conventional problem, an object of the invention is, in a semiconductor integrated circuit device in which an I/O cell can be disposed in a desired position within a chip, reducing the total line length of inter-cell wires by reducing the area of an internal circuit cell region.
In order to achieve the object, the present inventors have examined the layout of I/O cells.
Now, conventional I/O cells will be described with reference to FIGS. 14 and 15.
FIG. 14 is a schematic diagram for showing the layout of a conventional input I/O cell (hereinafter referred to as the input cell).
As is shown in FIG. 14, the input cell 12a includes a first partial circuit 21 composed of an input buffer and a logic circuit, an input ESD (electrostatic discharge) protection circuit 22 and an input pad 23. The input pad 23 is connected to a corresponding bump 11 by soldering or the like.
FIG. 15 is a schematic diagram for showing the layout of a conventional output I/O cell (hereinafter referred to as the output cell).
As is shown in FIG. 15, the output cell 12b includes a second partial circuit 24 composed of an output pre-buffer and a logic circuit, an output ESD protection circuit 25 and an output pad 26. The output pad 26 is connected to a corresponding bump 11, by soldering or the like.
The output cell 12b is different from the input cell 12a in the output ESD protection circuit 25 including an output buffer/ESD protection circuit 25a working also as an output buffer and an ESD protection dedicated circuit 25b not working as the output buffer.
ESD is a phenomenon that an LSI is damaged by momentary flow of a large current (surge current) derived from static electricity caused when the LSI is touched by a man during wafer fabrication or the like. Therefore, the ESD protection circuit is characterized by use of a transistor having a much larger size than a transistor used in the internal circuit cell so as to withstand a large current exceeding 1 A. Accordingly, the ESD protection circuit occupies the most of the area of the I/O cell.
The circuit is typically not powered during ESD events. Under normal operating condition, i.e., when the chip is powered up, the input ESD protection circuit 22 and the ESD protection dedicated circuit 25b do not affect the operation of the LSI and the output buffer/ESD protection circuit 25a works as the output buffer alone.
The output buffer/ESD protection circuit 25a transfers a signal of the chip 10 through the bump 11 to the outside of the chip 10, and hence, the output buffer/ESD protection circuit 25a is required to have large driving power. Also, when a distance between the output buffer/ESD protection circuit 25a and the bump 11 is large, a signal transfer rate between the bump 11 and the output cell 12b is lowered, and therefore, the distance between the output buffer/ESD protection circuit 25a and the bump 11 should be as small as possible.
The present invention was devised on the basis of the aforementioned findings, and specifically, the semiconductor integrated circuit device of this invention in which at least one I/O cell is able to be disposed in a desired position within a chip, comprises an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to a center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.
In the present semiconductor integrated circuit device, the ESD protection circuit that occupies the most of the area of a conventional I/O cell is separated from the I/O cell so as to be disposed in the ESD protection circuit region provided in the peripheral portion of the chip, and the I/O cell is disposed closer to the center of the chip than the ESD protection circuit region. Therefore, even when the I/O cell is inserted in an internal circuit cell region, the area of the internal circuit cell region can be reduced as compared with that in a conventional semiconductor integrated circuit device, resulting in reducing the total line length of inter-cell wires. Accordingly, propagation delay time of signals can be reduced in the entire LSI, resulting in realizing a high operation speed of the LSI.
In the semiconductor integrated circuit device, it is preferred that the I/O cell is an input cell or a power cell, and that the whole of the ESD protection circuit is separated from the I/O cell to be disposed in the ESD protection circuit region and is connected to the I/O cell through the wire.
In this manner, the area of the internal circuit cell region can be further reduced.
In the semiconductor integrated circuit device, it is preferred that the I/O cell is an output cell, and that an ESD protection dedicated circuit corresponding to a portion of the ESD protection circuit not working as an output buffer is separated from the I/O cell to be disposed in the ESD protection circuit region and is connected to the I/O cell through the wire.
In this manner, the area of the internal circuit cell region can be reduced without increasing signal transfer time between the I/O cell and a bump provided above the I/O cell.
The design method of this invention for a semiconductor integrated circuit device in which one or more I/O cells are able to be disposed in desired positions within a chip, comprises a first arrangement step of arranging the I/O cells and one or more internal circuit cells within the chip; a first wiring step of connecting the internal circuit cells arranged in the first arrangement step to each other or to the I/O cells through inter-cell wires; a second arrangement step of arranging one or more ESD protection circuits separated from the I/O cells in an ESD protection circuit region provided in a peripheral portion of the chip; and a second wiring step of connecting the I/O cells arranged in the first arrangement step to the ESD protection circuits arranged in the second arrangement step through ESD protection wires, and the I/O cells are disposed closer to a center of the chip than the ESD protection circuit region in the first arrangement step.
In the present design method for a semiconductor integrated circuit device, the ESD protection circuit that occupies the most of the area of a conventional I/O cell is separated from the I/O cell so as to be disposed in the ESD protection circuit region provided in the peripheral portion of the chip, and the I/O cell is disposed closer to the center of the chip than the ESD protection circuit region. Therefore, even when the I/O cell is inserted in an internal circuit cell region, the area of the internal circuit cell region can be reduced as compared with that in a conventional semiconductor integrated circuit device, so as to reduce the total line length of inter-cell wires. Accordingly, the propagation delay time of signals can be reduced in the entire LSI, resulting in realizing a high operation speed of the LSI.
Preferably, the design method for a semiconductor integrated circuit device further comprises, between the first wiring step and the second arrangement step, a layout abstraction step of drawing an inclusion line surrounding all of the I/O cells arranged in the first arrangement step and grating lines each extending between the I/O cells or between one of the I/O cells and the inclusion line, and defining a capacity of every grating line corresponding to the number of ESD protection wires permitted to cross the grating line; and an I/O cell allocation step of drawing, with respect to every I/O cell, an I/O cell allocation line extending between the I/O cell and a point on the inclusion line in a manner that the I/O cell allocation line does not cross another I/O cell allocation line and that the number of I/O cell allocation lines crossing every grating line does not exceed the capacity, and the ESD protection circuits are disposed in accordance with the order of the I/O cells each allocated to one point on the inclusion line by using the I/O cell allocation lines in the second arrangement step, and the ESD protection wires are provided in a single interconnection layer alone in the second wiring step.
In this manner, the ESD protection circuits separated from the I/O cells can be disposed so that the ESD protection wires can be provided on a single interconnection layer alone. Therefore, increase of the fabrication cost derived from increase of interconnection layers for providing the ESD protection wires can be avoided.
In the design method for a semiconductor integrated circuit device, it is preferred that the first wiring step includes a sub-step of providing, within the chip, a wire region where the inter-cell wires are disposed, that the design method further includes, between the first wiring step and the second arrangement step, a wire region detection step of detecting the wire region provided in the first wiring step, and that the second arrangement step includes a sub-step of disposing the ESD protection circuits in the wire region detected in the wire region detection step.
In this manner, the area of the ESD protection circuit region provided in the peripheral portion of the chip can be reduced, so as to reduce the area of the chip itself. As a result, the fabrication cost can be lowered and the yield can be improved.
In the computer-readable recording medium of this invention, an I/O cell library corresponding to a set of I/O cells for externally inputting a signal to or outputting a signal from a semiconductor integrated circuit is recorded, and the I/O cell library includes at least one ESD protection circuit separated from the I/O cells as a cell different from the I/O cells.
According to the present computer-readable recording medium, the design method for a semiconductor integrated circuit device of this invention can be easily practiced by utilizing the I/O cell library recorded in the recording medium on a computer.

Semiconductor integrated circuit device, design method for the same and computer-readable recording where medium I/O cell library is recorded

Matsushita Electric Industrial Co., Ltd.


A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample.

The present invention relates generally to data processing and communication systems, and, more specifically, to a system and method for removing glitches from a bit stream of serially transmitted data.
Electrical circuits generally operate in noisy environments. There are numerous sources that may introduce noise in input or output signals of electrical circuits, for example, reflection due to impedance mismatch between a source and load circuit, inductive and capacitive coupling in the circuit, cross-talk between signal lines, ringing, inter symbol interference (ISI) and other sources of disturbances. Such sources may generate unwanted components in the input or output signals of a transmitter or receiver circuit.
In serial communication systems, a data signal is transmitted serially through a transmission channel and noise from different sources adds glitches to the data signal. The serially transmitted data signal is received at the receiver and includes serially arranged data bits. Each data bit sent through the transmission channel is represented by a high or low voltage level for a predetermined time period or 'bit duration', resulting in logic values 1 and 0, respectively. Due to noise and other unwanted components as mentioned above, the logic low signal may overshoot during a bit transition for a short duration and produce a positive glitch. Similarly, the logic high signal may undershoot during a bit transition for a short duration and produce a negative glitch. Due to the overshoots and undershoots, the glitches occur near the bit transitions. However, glitches can occur anywhere in the bit duration due to other sources of disturbances, as mentioned above. For example, glitches can occur at the start, end or in the middle of the received bit stream.
Glitches may result in the wrong determination of the transmitted data bits that are received at the receiver. That is, a logic high signal sent by the transmitter may be determined as logic low and a logic low signal sent by the transmitter may be determined as logic high by the receiver. Thus, the glitches result in a high bit error rate (BER), and degrade the performance of the electrical circuit. Thus, if the glitches in the data signal are not removed, the overall function of the circuit is hampered and erroneous output may be produced.
Existing glitch removal circuits have several drawbacks. For one, they use delay-circuits to remove glitches from a bit stream. Drawbacks in such delay-circuit based glitch removal circuits will be explained in conjunction with FIGS. 1 and 2.
Referring now to FIG. 1A, a circuit diagram illustrating a conventional glitch removal circuit 100 is shown. The glitch removal circuit 100 includes a first combinational delay circuit 104a, a second combinational delay circuit 104b, and first and second NAND gates 108a and 108b. The first and second NAND gates 108a and 108b are connected in series. An input bit stream 102 is provided to a first input of the first NAND gate 108a. The input bit stream 102 is also provided to the first combinational delay circuit 104a and an output 106 of the first combinational delay circuit 104a is provided to a second input of the first NAND gate 108a. An output 110 of the first NAND gate 108a is provided to a first input of the second NAND gate 108b and to the second combinational delay circuit 104b. An output 112 of the second combinational delay circuit 104b is provided to a second input of the second NAND gate 108b.
FIGS. 1B and 1C illustrate first and second timing diagrams of various signals of the conventional glitch removal circuit 100. FIG. 1B shows the input bit stream 102; intermediate signals 106, 110, and 112; and an output signal 114. In this example, the input bit stream 102 includes a transition from a logic 1 to a logic 0 that has a positive or high glitch 'G' in the middle of the input bit stream 102. The first combinational delay circuit 104a introduces a delay 'd1' in the input bit stream 102 to generate the intermediate signal 106. The first NAND gate 108a performs a NAND operation on the input bit stream 102 and the intermediate signal 106 to generate the intermediate signal 110. The second combinational delay circuit 104b introduces a delay 'd2' in the intermediate signal 110 and generates the intermediate signal 112. The total delay introduced by the first and second combinational delay circuits 104a and 104b in the input bit stream 102 is 'd2−d1'. Finally, the second NAND gate 108b performs a NAND operation on the intermediate signals 110 and 112 to generate the output signal 114. In this case, to remove the glitch from the input bit stream 102, delay 'd1' introduced by the first combinational delay circuit 104a needs to be greater than the duration of the glitch 'G', i.e., d1>G. Additionally, the delay 'd2' introduced by the second combinational delay circuit 104b needs to be greater than the sum of the delay d1 and the duration of the glitch 'G', i.e., d2>d1+G. Thus, the combinational delay circuits 104a and 104b have to be designed specifically to meet the above-mentioned requirements.
The glitch is removed from the input bit stream 102 after performing the steps above and the output signal 114 is a glitch-free bit stream. However, the bit width L of the input bit stream 102 has been shortened to bit width L′, that is the bit width has been shortened by a width equal to 'd2−d1'. Similarly, if there is a negative or low glitch in the middle of the input bit stream 102 then the bit width L′ is elongated by a width equal to 'd2−d1' (see FIG. 1C). This is undesirable because bit width alterations may lead to a high BER at the receiver.
FIG. 1D is another example of a negative glitch in the input bit stream 102. In FIG. 1C, the glitch occurred near the middle of the input bit stream 102 while in FIG. 1D, the glitch occurs closer to a bit transition of the input bit stream 102. Referring to FIG. 1D, the input bit stream 102 includes a transition from a logic 0 to a logic 1 that has a negative or low glitch 'G' near the beginning of the transition end in the input bit stream 102. The first combinational delay circuit 104a introduces a delay 'd1' in the input bit stream 102 to generate the intermediate signal 106. The first NAND gate 108a performs a NAND operation on the input bit stream 102 and the intermediate signal 106 to generate the intermediate signal 110. The second combinational delay circuit 104b introduces a delay 'd2' in the intermediate signal 110 and generates the intermediate signal 112. Finally, the second NAND gate 108b performs a NAND operation on the intermediate signals 110 and 112 to generate the output signal 114. As shown in FIG. 1D, a glitch G′ occurs near the transition end in the output signal 114. The glitch in the input signal occurs at a distance X from the transition end, where the value of X is less than the total delay introduced by the first and second combinational delay circuits 104a and 104b (i.e. X<d1+d2). Thus, the glitch G has not been removed from the input bit stream 102 after performing the steps above and the output signal 114 includes the glitch G′.
It is evident from FIG. 1D, that the conventional glitch removal circuit 100 cannot remove glitches that are present near the transition ends of the signal received at the receiver. Further, it is evident from FIGS. 1B and 1C that the conventional glitch removal circuit 100 alters the bit width while removing glitches present near the middle of the signal received at the receiver. Additionally, in order to remove glitches from the input bit stream there are specific design requirements in the conventional glitch removal circuits.
Referring now to FIG. 2A, a block diagram illustrating another conventional glitch removal circuit 200 is shown. FIG. 2A includes three sequential delay circuits 204a, 204b, and 204c; an XOR gate 210; and a multiplexer 214 (hereinafter "mux 214"). Additionally, a single clock input (not shown in FIG. 2A) is connected to the three sequential delay circuits 204a, 204b, and 204c. The three sequential delay circuits 204a, 204b, and 204c; the XOR gate 210; and the mux 214 are connected in series. An input bit stream 202 is provided to an input of the first sequential delay circuit 204a and an output 206 of the first sequential delay circuit 204a is provided to the second sequential delay circuit 204b. The output 206 is also provided to a first input of the XOR gate 210 and to a first input of the mux 214. Further, an output 208 of the second sequential delay circuit 204b is provided to a second input of the XOR gate 210 and an output 212 of the XOR gate 210 is provided to a second input of the mux 214. The second input to the mux 214 is a control signal that is provided to a select line of the mux 214. An output 216 of the mux 214 is provided to the third sequential delay circuit 204c. Lastly, an output 218 of the third sequential delay circuit 204c is provided to a second input of the mux 214.
FIG. 2B is a timing diagram illustrating various signals in the conventional glitch removal circuit 200. FIG. 2B shows the input bit stream 202; intermediate signals 206, 208, and 212; and an output signal 218. The first sequential delay circuit 204a receives the input bit stream 202, which is generated by oversampling an input bit stream using an oversampling unit (not shown). The input bit stream 202 represents the bit stream that includes a transition from a bit 0 to a bit 1, and there is a negative glitch G near the transition end in the input bit stream 202. The first and second sequential delay circuits 204a and 204b generate the intermediate signals 206 and 208, respectively.
If the intermediate signals 206 and 208 have the same logic values, then the intermediate control signal 212 is logic low, and the intermediate signal 206 is provided as the output of the mux 214 to generate the intermediate signal 216. However, if the intermediate signals 206 and 208 have different logic values, then the intermediate control signal 212 is logic high, and the current output signal 218 is provided as the output 216 of the mux 214.
The third unit delay circuit 204c introduces a unit delay in the intermediate signal 216 to generate the output signal 218, which is fed back to the mux 214. The mux 214 holds the output at the previous logic value of the input bit stream 202 during bit transitions in the input bit stream 202 and updates the output when there is no bit transition in the input bit stream 202. The sequential delay circuits 204a, 204b, and 204c store previous and present values of the input bit stream 202 to be used by the mux 214. Thus, the glitch in the input bit stream 202 is removed by maintaining the previous logic value, i.e. high or low at the output signal 218 during the bit transitions in the input bit stream 202 and updating the new logic value at the output signal 218 during the bit non-transitions in the input bit stream 202. However, a major shortcoming of the conventional glitch removal circuit 200 is that the bit width L in the input bit stream 202 is shortened to bit width L′ in the output signal 216.
Data processing and communication systems based on serial data transmission are particularly sensitive to glitches. High-Speed serial interfaces, such as Mobile Industry Processor Interface (MIPI), Serial AT Attachment (SATA), Universal Serial Bus (USB) 3.0, and Peripheral Component Interconnect (PCI) Express, use various clock and data recovery schemes. These clock and data recovery schemes rely on accurate detection of bit boundaries. Therefore, the clock and data recovery schemes are particularly sensitive to glitches. Additionally, for error free clock and data recovery and to maintain low BER at the receiver of the High-Speed serial interfaces, the input bit stream provided to the clock and data recovery circuit should include bits of equal widths (i.e., no shortening or elongation of bit widths) corresponding to logic low and logic high data.
The conventional glitch removal circuits undesirably alter the bit widths while removing glitches from the received bit stream. Consequently, the probability of recovering correct data at the receiver by the clock and data recovery circuit decreases. It is desirable that the glitch removal circuits remove glitches of variable width and glitches that occur anywhere during the bit duration. Further, the delay introduced by the delay elements in the conventional glitch removal circuits varies with process, voltage, and temperature (PVT) variations, and hence, glitch removal operation is sensitive to the operating range of the circuit. It would be advantageous to have a glitch removal circuit that is independent of PVT variations. It also would be desirable to have a glitch removal circuit that can remove variable width glitches and does not alter the bit width of the input bit stream.

System and method for removing glitches from a bit stream


A deployable buoy having a nose cone and a tail section interconnected by a housing. The buoy comprises an outer shell and a canister with the outer shell axially moveable relative to the canister. An expansion chamber is provided between the outer shell and canister to produce and increase the axial length of the buoy and thereby increase the buoyancy of the buoy from a low buoyancy to a greater buoyancy and to orient and maintain the buoy in a substantially vertical orientation. The buoy is provided with a hot fluid generation source to melt a layer of ice and a nose cone ejection system to expose an antenna for the transmission of data to the central processing system.

In the prior art, deployable buoys are well known. However, many of these buoys are cumbersome and not well suited either for deployment by an underwater vehicle or for gently floating toward the surface and penetrating a substantial layer of ice, e.g. one to two meters thick, in order, to transmit information to a central processing system.

Communication buoy with ice penetrating capabilities


Provided is a digital filter device that causes the last data of an immediately precedent input block to overlap with the input block of a time domain and generates an overlap block. The overlap block and the immediately precedent input block are each converted into a frequency domain block, subjected to filter processing, and converted into first and second time domain blocks. Among the overlap section of the first time domain block and the second time domain block, the front-end data of the first time domain block and the rear-end data of the temporal axis of the second time domain block are removed as a section of data that is to be removed, and output data is generated. An overlap amount is controlled on the basis of a distortion amount that is determined by comparing the removed section of the data of the first time region domain with the output section of the data of the overlap section of the second time domain block other than the removed section of said overlap section.

Important processing types in digital signal processing include fast Fourier transform (hereinafter referred to as "FFT") processing. Further, as a technology of compensating for waveform distortion in signal transmission in wireless communication and wired communication, for example, a frequency domain equalization (FDE) technology is known. In frequency domain equalization, signal data in a time domain are first transformed into data in a frequency domain by a fast Fourier transform, and next, filter processing for equalization is performed. Then, data after the filter processing are retransformed into signal data in a time domain by inverse fast Fourier transform (hereinafter referred to as "IFFT") so that waveform distortion in the original signal in a time domain is compensated for. FFT and IFFT are hereinafter referred to as "FFT/IFFT" when they are not distinguished.
In general, "butterfly calculation" is used in FFT/IFFT processing. An FFT device using butterfly calculation is described in, for example, PTL 1. PTL 1 also describes "twiddle multiplication" to be described later, that is, multiplication using a twiddle coefficient.
As an efficient FFT/IFFT processing method, for example, butterfly calculation by Cooley-Tukey described in NPL 1 is well known. However, the FFT/IFFT processing method by Cooley-Tukey has a large number of points and therefore a circuit for providing the processing method is complex. Consequently, FFT/IFFT processing is performed by breaking down an FFT/IFFT into two smaller-sized FFT/IFFTs by use of, for example, a prime factor method described in NPL 2.
FIG. 7 illustrates, for example, a data flow 500 of a 64-point FFT broken down into sets of two-stage radix-8 butterfly processing by use of the prime factor method. The data flow 500 includes data sorting processing 501, a total of 16 sets of radix-8 butterfly calculation processing composed of butterfly calculation processing 502 and 503, and twiddle multiplication processing 504.
In the data flow illustrated in FIG. 7, input time-domain data x(n) (n=0, 1, . . . , 63) are Fourier-transformed into a frequency-domain signal X(k) (k=0, 1, . . . , 63) by FFT processing. In the example illustrated in FIG. 7, illustration of part of the data flow is omitted. Note that a basic configuration of the data flow illustrated in FIG. 7 is the same for IFFT processing.
When a number of points of an FFT is large, an enormous circuit scale is required in order to provide the entire data flow illustrated in FIG. 7 by a circuit. Consequently, when a number of points of an FFT is large, a method of providing the entire FFT processing by repetitive use of a circuit providing part of the processing of the data flow, depending on required processing performance, is common.
For example, in the data flow illustrated in FIG. 7, when an FFT device performing FFT processing on eight pieces of data in parallel (hereinafter simply referred to as "in 8-data-parallel") is created as a physical circuit, 64-point FFT processing can be provided by a total of eight sets of repetitive processing.
The eight sets of repetitive processing represent successively performing processing corresponding to each of partial data flows 505a to 505h performed on eight pieces of data, and are specifically performed as follows. That is, processing corresponding to the partial data flow 505a is performed in a first round, processing corresponding to the partial data flow 505b is performed in a second round, and processing corresponding to the partial data flow 505c (not illustrated) is performed in a third round. Thereafter, processing is successively performed in a similar manner up to processing corresponding to the partial data flow 505h in an eighth round. The processing described above provides the 64-point FFT processing.
In butterfly calculation, data arranged in sequential order are read in an order conforming to a predetermined rule, and processed. Thus, data sorting is required in butterfly calculation, and a random access memory (RAM) is used for the purpose. An FFT device performing data sorting using a RAM in butterfly calculation is described in, for example, PTL 2.
Further, as for an FFT calculation device with a reduced memory usage amount, an acceleration technology by parallel processing of butterfly calculation is described in, for example, PTL 3.
Meanwhile, in FFT, it is assumed that data identical with a range of an extracted input signal being a processing target, that is, a set of consecutive input data (hereinafter referred to as "processing block") are periodically repeated. However, an actual signal is not necessarily a periodic signal, and therefore there is a problem that calculation distortion occurs near both ends of a processing block after FFT.
As a technology solving the problem, for example, an "overlap method" may be cited. In the overlap method, adjacent processing blocks are overlapped by a predetermined number of pieces of data, and FFT processing is performed. Data after FFT processing undergo filter processing and then retransformed into a time-domain signal by IFFT processing. Then, partial data at both ends where calculation distortion occurs in an overlapped processing block are removed. A part of processing block data to be removed is hereinafter referred to as "removal part" and a part not removed but output is referred to as "output part."
The overlap method is also applied to FDE (refer to, for example, PTL 4 and 5). An overlap FDE method in which the overlap method is applied to FDE will be described. FIG. 8 is a block diagram illustrating a configuration example of a digital filter circuit 700 by the overlap FDE method. The digital filter circuit 700 is a frequency-domain filter circuit performing filter processing in a frequency domain. Specifically, a time-domain signal input as input data is transformed into frequency-domain data by FFT and subsequently undergoes filter processing. Then, the signal after the filter processing is retransformed into a time-domain signal by IFFT and output as an output signal.
The digital filter circuit 700 includes an overlap addition circuit 710, an FFT circuit 711, a filter calculation circuit 712, an IFFT circuit 713, and an overlap removal circuit 714.
The overlap addition circuit 710 successively generates a block composed of N pieces of data (where N is a positive integer) from input data which is a time-domain input signal, and outputs the block to the FFT circuit 711. At this time, the overlap addition circuit 710 causes each block to have M pieces of data (where M is a positive integer) overlapped with an immediately preceding block. The number of pieces of data to be overlapped M is hereinafter referred to as "overlap amount." Further, an overlapped part in each block is referred to as "overlap part."
An overlap amount M may be a predetermined fixed value. In that case, the overlap addition circuit 710 and the overlap removal circuit 714 are configured in accordance with a value of the overlap value M. Alternatively, for example, the overlap addition circuit 710 and the overlap removal circuit 714 may refer to a set value of an overlap amount M given by an upper circuit (not illustrated) such as a central processing unit (CPU) and set the value when in operation. Note that the overlap addition circuit 710 may be configured by, for example, a dual-port memory.
The FFT circuit 711 performs FFT on a time-domain input signal with M pieces of data overlapped thereon, being output from the overlap addition circuit 710, transforms the signal into a frequency-domain signal, and outputs the signal to the filter calculation circuit 712.
The filter calculation circuit 712 performs filter processing on a frequency-domain signal transformed by the FFT circuit 711, and outputs the signal to the IFFT circuit 713. For example, when the digital filter circuit 700 performs processing of equalizing signal distortion in a communication channel, the filter calculation circuit 712 may be configured with a complex number multiplier.
The IFFT circuit 713 performs IFFT on a frequency-domain signal after filter processing, output from the filter calculation circuit 712, to retransform the signal into a time-domain signal, and outputs the signal to the overlap removal circuit 714.
The overlap removal circuit 714 removes a total of M pieces of data from both ends of each block composed of N pieces of data which is a time-domain signal retransformed by the IFFT circuit 713. At this time, a part to be removed is the aforementioned "removal part" and the amount of the data is equal to the overlap amount M. Then, the overlap removal circuit 714 outputs data in an "output part" included in an overlap part and data in a middle part of a block not overlapped as output data.
An operation of the digital filter circuit 700 illustrated in FIG. 8 will be described below with reference to FIG. 9. FIG. 9 is an operation diagram illustrating an operation example of the digital filter circuit illustrated in FIG. 8. In the description below, processing steps (1) to (5) respectively correspond to processing steps (1) to (5) in FIG. 9.
(1) Overlap Addition Processing
The overlap addition circuit 710 successively generates a block composed of N pieces of data (where N is a positive integer) from input data which is a time domain input signal. At this time, the overlap addition circuit 710 causes the block to have M pieces of data overlapped with an immediately preceding block.
When input data are denoted asx(i)(i=0,1, . . . ),a block composed of N pieces of data is expressed asx(j)(j=m(N−M)−N to m(N−M)−1, where m is a positive integer).Note that N denotes an FFT block size and M denotes an overlap amount.(2) FFT Processing
The FFT circuit 711 performs FFT on a block composed of time-domain signal data, and transforms the block into a block composed of frequency-domain signal data.
Again, when a block composed of N pieces of time-domain signal data is denoted asx(n)(n=0,1, . . . ,N−1),a block in a frequency domain after the FFT processing is given byX(k)(k=0,1, . . . ,N−1).(3) Frequency Domain Filter Processing
The filter calculation circuit 712 performs filter processing on each piece of signal data in a frequency domain, composing a block after FFT processing.
A block after the filter processing corresponding to a block X(k) before the filter processing is given byX′(k)=H(k)·X(k)(k=0,1, . . . ,N−1).Note that H(k) denotes a filter coefficient.(4) IFFT Processing
The IFFT circuit 713 performs IFFT on a block composed of frequency-domain signal data after filter processing to retransform the block into a block composed of time-domain signal data.
A block after the IFFT processing corresponding to a block X′(k) before the IFFT processing is given byy(n)(n=0,1, . . . ,N−1).(5) Overlap Removal Processing
From the block y(n) composed of N pieces of signal data after the IFFT processing, the overlap removal circuit 714 extracts a middle part by removing M/2 pieces of overlapped data from the start and the end of the block, respectively, that is, data in a removal part.
Thus, data in the removal part are removed, and a sequence of (N−M) pieces of signal data composed of an output part included in an overlap part of the block y(n) and the middle part not overlapped, expressed asy′(j)(j=M/2 to (N−1)−M/2),is generated.
There exists a digital filter circuit using overlap processing for general filter processing, not being limited to FDE and the like (refer to, for example, PTL 6). The digital filter circuit in PTL 6 also performs overlap addition processing, FFT processing, frequency domain filter processing, IFFT processing, and overlap removal processing.
Meanwhile, an overlap amount required in a filter using overlap processing is determined in accordance with an impulse response length of executed filter processing. Additionally, a size of an FFT processing block needs to be greater than the required overlap amount. Consequently, a size of the FFT processing block is determined in accordance with an impulse response length of the filter processing.
There is a technology of decreasing a hardware amount of a processing device performing FFT on blocks with varying sizes (refer to, for example, PTL 7). An orthogonal transformation processor in PTL 7 determines a memory size adapting to a length of an FFT vector (corresponding to "processing block"), disables an unnecessary circuit block, and operates hardware in a time-division manner.

Digital filter device, digital filter processing method, and storage medium having digital filter program stored thereon


The invention relates to a bending press (1) for bending workpieces, comprising an upper tool (2) and a lower tool (3), a tool holder (4), in which the upper tool (2) is inserted, and a tool holder (5), in which the lower tool (3) is inserted, wherein the upper tool (2) and the lower tool (3) can be fixed in various positions within the respective tool holder (4, 5), a control device (13) for controlling the bending press (1), a sensor device (8), which is connected to the control device (13), and a stop (6) for positioning the workpiece within the bending press (1), wherein the stop (6) can be moved in relation to the tools (2, 3) by means of a drive (9) controlled by the control device (13). The sensor device (8) is designed to detect the position of the upper tool (2) and of the lower tool (3) within the bending press (1) without contact, and the control device (13) is designed to adapt the movement process by means of which the stop (6) is positioned in relation to the tools (2, 3), in dependence on the position of the upper tool (2) and of the lower tool (3) detected by means of the sensor device (8).

The selection and arrangement of workpieces in bending presses, also called press brakes or bending machines, is typically accomplished to a high degree manually, and only partly assisted by the machine control. To this end, a bending plan is created which calculates the product-specific upper and lower tools and their theoretical position. However, there is no monitoring as to whether these tools are or were actually inserted into the machine. Furthermore, the tools can be introduced at positions which do not correspond to the process and comprise a potential hazard.
However, the exact position of the tools is required to perform high-quality bending sequences and to align the back stop fingers or a robot accordingly. A corresponding positioning is only possible by precise and work-intensive measurement by hand, and transfer to the machine control.
Inaccurate positionings, non-allowance in the bending plan or an incorrect number of tools can result in damage to machine and peripheral. This is also possible as a result of an incorrect choice of tool geometry. Furthermore, upper and lower tools with maximum loads are defined—here also incorrect handling can result in damage. Damage caused by incorrect insertions on press brakes and tools can additionally lead to demands of any kind with respect to the manufacturer. Apparatuses are already known which attempt to solve these problems, in part, but have a number of disadvantages. Thus, for example, a display device on the machine can merely predefine a desired position but not monitor and detect this.
Published patent application JP H09-052124A discloses a bending machine with upper and lower tool, a stop and a barcode reader which is disposed on the stop. Upper and lower tool are each provided with a barcode on their rear side which can be read out by the barcode reader. The barcode contains information about the condition of the tool. This information is transferred to an NC controller. In addition to the barcode reader, a contact sensor or end switch is provided on the stop by which of which the dimensions of the respective tool can be determined. Such a procedure is complex and time-consuming since the contact sensor must be moved several times and in different positions directly onto the tool.
With such a system, for example, tools on the outer sides of the machine cannot be detected since no (rear) stop can travel here as a result of the mechanism. In addition, only individually positioned tools can be detected. A plurality of tools pushed together (or arranged in a row) on a tool holder cannot be distinguished since the central tools cannot be detected by the known system as such. In particular, individually positioned tools can only be detected when the distances between the tools are sufficiently large in order that the rear stop or the fingers can travel in between. A barcode requires a relatively large amount of space, so that such a barcode cannot be shown on very small punches (upper tool) and dies (lower tool). In addition, the detection of the barcode on sloping surfaces of the tool is very liable to error so that not all tools can be reliably detected. Also, specially shaped tools cannot be detected if the rear stop cannot be moved mechanically between the tools. If the approximate position of the tool is not known before the detection process, there is a high risk of a collision with the rear stop. Since the workpieces to be processed also impact against the rear stop during positioning, the contact sensors are severely stressed and are easily damaged.
WO 2012/103565A1 discloses a method for equipping a bending press with a bending tool. Here a controlled handling device with a gripper is used for the bending tool. A control device generates control commands in order to move the tool from an actual position into a desired position when inserting into the tool holder. Only when the tool has reached the desired position, is it inserted in the tool holder and fixed there. The tools held by the handling device must be approached directly by the (rear) stop in order to determine their actual position. The method is complex and based on the basic principle that the tools inside the tool holder must adopt an exact position so that the desired bending plan can be carried out.
EP 0919300B1 discloses a bending machine in which the upper tools are provided with barcodes. A guide running in the Z direction for a scanner for reading the barcode is provided on the tool clamp for the upper tools on the side facing the operator. A linear scale, e.g. magnetic scale as position detection device is further provided on this tool clamp on the side facing the operator. The position data of the upper tools detected by the scanner are stored and made available again subsequently in a display. For producing the same product again, using the stored data the operator must place the tools precisely by hand according to the stored position. This bending machine is also based on the basic principle that the tools must adopt an exact position inside the tool holder so that the desired bending plan can be executed. However, the exact positioning and adjusting of the tool position requires high expenditure of time and personnel.
EP 1517761B1 relates to special tools and tool holders which can detect tool positions relatively imprecisely by means of sensors. In this case, it is not possible in some cases to classify tools qualitatively and geometrically. In addition, the high acquisition costs of the required peripherals, the maintenance intensity, the necessary new acquisition of special punches and dies and their restricted geometry are disadvantages. Furthermore, as a result of the sensors introduced into the machine and tool, limiting pressing forces are to be expected. In addition, movable sensors on upper and lower beams as well as necessary data and supply cables reduce the variability of a press brake. The number of possible bending parts is limited.
EP 1510267B1 discloses a method for displaying a tool arrangement in a press brake. On the basis of a displayed diagram it is determined whether the planned bending process is possible. Subsequently further tools are added for specific bending line sections and the process is repeated with the new arrangement. This process requires an exact positioning of the tools in the tool holder precisely as the previous method.
DE 3830488A1 discloses an electronic tool recognition system for press brakes. By means of this system it is possible with the aid of an electronic control to recognize the built-in tool geometry, to protect the tools against overloading and ensure the working safety for the operator.
DE 4442381A1 relates to an apparatus for position and shape recognition of upper beam tools on swivel bending machines and press brakes. Located behind the upper beam in a guide is a motor-displaceable slide on which a holder for a laser light curtain is mounted. With this the length of the built-in upper beam tools and their intermediate spaces are determined. The values are displayed numerically and graphically. In addition, a write-read head which reads out codes on the rear side of the upper beam tools is located in the holder.
All the known systems relate to the readout of codes and/or the detection of tool dimensions. The precise positioning of the tools inside the tool holder plays an essential role. In the prior art therefore it is necessary to position the tools exactly in relation to the tool holder, which brings with it the disadvantage of a complex and time-intensive equipping of the bending machine.


The present invention provides a magnetic recording medium having excellent durability, high abrasive resistance and smoothness capable of suppressing development of uneven wear on a tape contact surface of a magnetic head at minimum. The magnetic recording medium has a base film and a magnetic layer provided on the base film. The magnetic layer includes metal magnetic powder of particles having an average long axis length of not more than 0.13 .mu.m, alumina powder of particles which have an average diameter of not more than 0.13 .mu.m, an .alpha.-rate of not more than 30% and pH of not more than 7.0, and a binder resin.

1. Field of the Invention
This invention relates to improvements of a magnetic recording medium used for a magnetic recording and/or reproducing apparatus, and it particularly relates to a coated-type magnetic recording medium having an excellent durability and surface flatness capable of suppressing development of uneven wear minimal on a tape contact surface of a magnetic head.
2. Description of the Related Arts
Presently, a magnetic recording medium such as a magnetic tape used for video tape recorders (referred to as VTR) or audio tape recorders is constructed by coating magnetic paint on a surface of a base film to form a magnetic layer on which information signals are to be recorded by magnetic heads. For the purpose of improving durability and abrasive resistance of the magnetic layer of the magnetic tape, non-magnetic particles selected from Al.sub.2 O.sub.3, Cr.sub.2 O.sub.3 and .alpha.-Fe.sub.2 O.sub.3 particles each having a Mohs hardness of more than 6 are added in the magnetic layer as abrasives or abrasive resistance additives.
As well known, these abrasives are effective to improve the durability and abrasive resistance characteristic of the magnetic tape, on the other hand, they polish and abrade a tape contact surface of the magnetic head. Thanks to the abrasive ability of the magnetic tape, such stains and foreign matters closely adhered to the tape contact surface of the magnetic head as magnetic particles along with binder separated from the magnetic layer are effectively removed by running the magnetic tape containing the abrasives along the tape contact surface thereof.
Along with magnetic recording mediums employing conventional oxide iron powder as magnetic powder, a ferrite magnetic head has been widely used as a recording and reproducing magnetic head so far. However, upon emergence of metal tapes having a higher coercive force (Hc), a metal type magnetic head (referred to as a metal head hereinafter) such as a Metal in Gap type head (referred to as MIG head), a metal laminated type head or a thin film type head is used in place of the ferrite magnetic head. Usually, the tape contact surface of the metal head is composed of a plurality of different materials each having a different hardness from one another. When the metal head is used for the magnetic tape containing the conventional abrasive made of particles each having a high mohs hardness such as alumina powder of which particles have a high .alpha.-rate (.alpha.-rate designates a degree of crystallization as mentioned hereinafter), the metal head tends to suffer from uneven wear in which wear occurs locally in metal materials having a lower hardness than those of other materials on the tape contact surface. Thus, the output level of the metal head is decreased upon reproducing recorded signal from the magnetic tape because of a spacing loss due to the uneven wear. Further, head cracks may be produced in the tape contact surface in the worst case.
Specifically, in the conventional ferrite head, the tape contact surface is composed of bonding glass portions and ferrite core portions which have a higher abrasive resistance than that of the bonding glass portions. Thus, even when the uneven wear occurs on the tape contact surface, the amount of wear is larger in the bonding glass portions than in the ferrite core portions, thus, the uneven wear does not prevent the ferrite core portions from contacting the magnetic tape closely. Therefore, degradation of the output level is negligible small in the ferrite head, if the uneven wear occurs.
On the other hand, in the metal head such as the MIG head, a magnetic gap which plays the most important role in recording and reproducing operation is formed between the metal cores. Thus, the metal core portions forming the magnetic gap therebetween readily wears compared with the other parts than the magnetic gap portion owing to lower hardness of the metal portions, which invites degradation of the output level of the metal head because of the spacing loss occurring due to a space between the magnetic gap and the magnetic tape.
Conventionally, in order to decrease the uneven wear produced on the tape contact surface, the abrasive is added into the magnetic layer of the magnetic tape so as to abrade equally the tape contact surface of the magnetic head so far. However, this causes a high degree of wear of the magnetic head, resulting in shortening the life of the magnetic head. When an abrasive made of smaller sized particles is employed in the magnetic layer to decrease the abrading ability of the abrasive, dispersiblity of particles of the abrasive is degraded. This causes the deterioration of the surface flatness of the magnetic tape, resulting in degradation of the electro-magnetic transfer characteristics, in addition, inviting the damage of the tape contact surface of the magnetic head upon operation.
In order to improve the dispersiblity of the small size particles, dispersant may be added into the magnetic paint, however, this dispersant has drawbacks that when the amount of the dispersant added is too small, the particles of the abrasive do not disperse in the magnetic paint throughly, and when the amount of the dispersant is too large, the dispersant seeps out on the surface thereof, i.e., a blooming phenomenon occurs on the surface of the magnetic tape.

Magnetic recording media having a magnetic layer including acicular magnetic metal powder and alumina powder