Methods and apparatus for determining at least one permutation of a set of a K number of values are disclosed. The methods and apparatus utilize a first permutation functionality that maps an index value to another value within the set of K values according to the first outputting the mapped value as a next value in the at least one permutation; setting the index value to a next index value according to a second predefined permutation function; and repeating mapping, outputting and setting until each operation is performed at least K number of times and a permuted sequence of the K number of values has been output.

1. Field
The present application relates to the generation of permutations and, more particularly, to generating pseudo-random permutations of a set of indices used for encoding information to be transmitted, such as via a wireless system.
2. Background
In encoding information, such as information to be transmitted in a wireless communication system, it is known to generate different random permutations of a number sequence. The more random the permutation, the more robust the data transmission will be and resilient against errors introduced during transmission of encoded data.
A particular example where permutations are utilized in encoding data includes a turbo encoder, which may be utilized in a wireless transmitter or transceiver, as examples. In particular, FIG. 1 illustrates a turbo encoder 100 that may be utilized in a wireless transceiver. The turbo encoder 100 receives an input of data signals identified by sequence of integers 102 (e.g., {0, 1, 2, . . . , K−1}, where K is an integer). As may be seen in system 100, the sequence 102 is input to an upper convolutional coder 104 that encodes the sequence and outputs the resultant convoluntially encoded sequence to a multiplexer 106. The multiplexer 106 also includes an input 108 to which the unaltered sequence 102 is delivered. Finally, a lower leg includes a permutation generator 110 and a convolutional coder 112 connected in sequence.
In particular, the lower leg of the turbo encoder 100 generates its signals by first permuting the data signals identified by the integer sequence 102 according to a prescribed algorithm or methodology. Examples of known algorithms or methodologies will be discussed later.
After the sequence 102 is permuted by permutation generator 110, a convolutional code is then applied to this permuted sequence by the convolutional coder 112. In the example encoder 100, the data symbols from each of the convolutional coders 104 and 112 and the K data symbols 108 are multiplexed by multiplexer 106 to be output as turbo encoded symbols 114.
As mentioned above, the permutation generator 110 may employ specific algorithms or methodologies for generating different permutations of the sequence 102. One such approach is to generate random permutations using a random number generator to produce the permuted sequence. Accordingly both the encoder and decoder can utilize the same random number generator and a same initial seed number to produce the same sequence. This approach, however, is disadvantageous in that each of the encoder and decoder must store the generated permuted sequence in memory. Accordingly, for large values of K and for a large number of different permutations, the amount of memory required for storing such permutations is costly.
Another approach that is known to generate permutations includes using a rectangular array. As an example, it is assumed that a permutation of numbers from 0 to 9 is desired. These numbers may be written into a rectangular array of a size two rows by five columns (2×5). The numbers zero through nine are then inserted in sequence into the rows and read out from the columns. An exemplary resultant array is illustrated as follows:
0123456789
As may be seen from the array above, a permuted sequence that would be generated by reading out the numbers by columns is {0, 5, 1, 6, 2, 7, 3, 8, 4, 9}. It will be appreciated by those skilled in the art that by choosing arrays of row and column numbers, different permutations can be generated. A disadvantage of this approach, however, is that the resultant sequences may not posses a sufficient degree of randomness, thus not providing a robust permutation.
A further methodology used for generating permutations of a sequence that is known includes use of a linear congruential technique. In particular, in such techniques a number A0 is chosen between 0 and K−1. Next, a recursive function is defined such that An equals (aAn-1+b) mod K for values of n=1, 2, . . . , K−1, where n is an integer. Along with this defined function, a number of conditions must also be met. The first condition is that the values a and b are less than K. Additionally, b must be relatively prime to K. Furthermore, the value (a−1) must be a multiple of p, for every prime number p dividing K. Additionally, the value (a−1) is a multiple of 4 if the value K is also a multiple of 4. Finally, it is desirable that a is relatively prime to K.
As an example of this technique, it is assumed that the value K=9, the prime factor is p is 3, and a value of a is chosen such that (a−1)=3x. Accordingly, if a equals 4 and b equals 7 and A0 equals 5, the generated permuted sequence would be {5, 0, 7, 8, 3, 1, 2, 6, 4}. A drawback to this approach, however, is that for a prime value of K, the only value of a that can be picked is 1. Accordingly, different permutations differ only in the value of A0 and b limiting the randomness that can be achieved.
As another example of a type of encoder known in the art utilizing permutations, FIG. 2 illustrates an encoder 200 utilizing a Low Density Generator Matrix encoder. As illustrated, the system receives an input sequence 202 that is delivered directly to a multiplexer 204 as well as a permuted sequence 206 output from a Low Density Generator Matrix encoder 208. Within the Low Density Generator Matrix encoder 208, coded symbols are generated by parallel concatenation of codes, which, in turn, consist of a permutation of K number of data symbols and a block code that encodes blocks of the permuted sequence. These block code symbols are combined together by the multiplexer 204 after being output in parallel 206 from the low density generator matrix 208. Again, the permutations performed by the low density generator matrix 208 may be effected by any of the known algorithms or methodologies described above. Accordingly, because each of the permutation algorithms or methods discussed has drawbacks, the low density generator matrix 208 accordingly suffers the same drawbacks.

Methods and apparatus for generating permutations


A low severity continuous reforming process that operates at conditions to provide a low coke production provides an improved reformulated gasoline fuel. The conditions for the reforming operation include high space velocity, relatively high temperature and low hydrogen to hydrocarbon ratios. Despite the higher temperature, the process provides stable coke production rates at a very low level while providing relative high hydrogen yields. The lower severity operation and the high hydrogen yield facilitate the removal of benzene from the reformulated gasoline pool while avoiding the anticipated hydrogen deficit that such operations would produce.

Catalytic reforming processes have long served as a primary means of upgrading hydrocarbon streams to increase the octane of gasoline products.
Generally the hydrocarbon feedstock comprises a petroleum gasoline fraction commonly referred to as naphtha. The naphtha stream usually comprises relatively large concentrations of naphthenic and substantially straight, chain paraffinic hydrocarbons. The reforming process performs a variety of concomitant reactions which consists principally of naphthene isomerization, dehydrogenation of naphthenes to aromatics, dealkylation and demethylation of aromatics to lighter aromatics, isomerization of normal paraffins to isoparaffins, and hydrocracking. Reforming is a catalytic process that relies on a substantial number of acid and metal sites on the catalyst. A typical reforming process mixes hydrogen with the hydrocarbon feedstock before entering a first reaction zone. The feed passes serially through at least one additional reaction zone before separation to provide a vapor phase comprising hydrogen for recycle of the feedstock and a liquid product phase providing the gasoline composition. Since the various reactions that take place are highly endothermic, the process takes place in a series of reaction zones with intermediate reheating between the reaction zones to maintain reaction temperatures. It has been taught that the reforming process can operate at a wide variety of conditions including temperatures in a range of from 800.degree.-1100.degree. F., pressures of from 0 to 1000 psig, liquid hourly space velocities (LHSV) of from 0.1 to 10, and hydrogen to hydrocarbon ratios of from 0.5 to 20.
Most reforming processes are designed to operate in either a continuous manner with a continuous catalyst regeneration section, or in what is generally referred to as a semi-regenerative operation. Reforming operations started out with a semi-regenerative process in which feed to a reactor or reactors is periodically stopped and the catalyst within that reaction zone is regenerated by steps of coke oxidation, halogenation, and reduction. Continuous catalyst regeneration is well known in the art and is used to continuously or intermittently remove small amounts of catalyst from an operating series of reforming reactors without stopping the feed to the series of reaction zones and returning the catalyst to the series of reaction zones after regeneration. Continuous catalyst regeneration operations have generally been favored in the past to permit the operation of the reformer at high severity and thereby maximize octane production. Where a reforming process operates at low severity, there is a disincentive to the use of a continuous catalyst regeneration system due to its added cost.
Historically, reformers have operated on naphtha-rich feeds to produce aromatics and in particular benzene with the additional benefit of producing large amounts of hydrogen through dehydrogenation reactions. In the past, a typical gasoline fraction for upgrading in a reforming process had initial boiling points of from 150.degree.-200.degree. F. and end boiling points of from 325.degree.-425.degree. F. New requirements for reformulated gasoline have profound impacts on the operation of reformers. Reformulated gasoline requirements impose limitations on gasoline end points, benzene as well as total aromatics, and reid vapor pressure (RVP). Benzene reduction poses one of the most severe problems for the operation of the reformer for benzene precursors must be removed prior to a reforming operation or removed from the product stream by either direct saturation or saturation through isomerization. In some cases benzene can be reduced by alkylation to cumene. The most advantageous way to eliminate benzene is by minimizing its production within the reformer. Benzene and benzene precursors may be removed prior to reforming or benzene may be treated after the reforming operation by saturation directly or through isomerization, alkylation to cumene or other higher aromatics or finally by direct extraction to recover benzene products where refiners are equipped to provide petrochemical benzene. Limitations on the amount of aromatics arise indirectly due to limitations on benzene and the function of aromatics as benzene precursors. Therefore, along with benzene reduction, reduction in aromatics will also follow from the revised role of reforming under the requirements of reformulated gasoline. Other effects of reformulated gasoline requirements such as limitations on end points and RVP will have less direct impact on the operation of the reforming zone but will nevertheless impact the operation severity of reforming units. However, requirements for oxygen containing compounds in the gasoline pool will increase gasoline octane via the addition of alcohols and ethers such as MTBE. These relatively high octane blending components reduce the overall octane requirement of the reformer thereby further altering operations. Thus, reformulated gasoline will have the effect of lowering octane requirements along with hydrogen production from the reformer.
Unfortunately, the lower production of hydrogen comes together with increased demands for hydrogen in most refineries. For example, reformulated gasoline will also emphasize the need to remove sulfur from feedstocks often through hydrodesulfurization. Increased hydrogen demands further arise from the hydrocracking of heavy naphtha components which come available from the decrease in the ASTM 90% distillation point (T-90) and the additional needs of sulfur removal. The necessity for direct saturation of benzene will require additional amounts of hydrogen. There will also be increased emphasis on isomerization and alkylation to provide lower RVP components to the gasoline pool which, with the concomitant side reactions, also consume more hydrogen.
External sources of hydrogen are available such as hydrogen plants, or other technologies for supplying hydrogen, however these methods are not favored due to their relatively high cost. Thus, there is a need for processing reforming feeds that will accommodate the requirements for reformulated gasoline. Such a method needs to provide high hydrogen production at low octane severity with a low production of benzene. An additional requirement is that such process operate without an increase in RVP.

High hydrogen and low coke reforming process


There is provided an image pickup apparatus comprising a plurality of pixels each including a photoelectric conversion unit which converts incident light into an electrical signal and accumulates the electrical signal, an amplifier transistor which amplifies and outputs the signal from the photoelectric conversion unit, a transfer transistor which transfers the electrical signal accumulated in the photoelectric conversion unit to the amplifier transistor, and a processing transistor which performs predetermined processing, and a control circuit which sets the signal level supplied to the control electrode of the transfer transistor in order to turn off the transfer transistor to be lower than the signal level supplied to the control electrode of the processing transistor in order to turn off the processing transistor.

1. Field of the Invention
The present invention relates to a solid-state image pickup device having a plurality of pixels each including a photoelectric conversion unit and a plurality of transistors, an image pickup apparatus using the solid-state image pickup device, and a scanning circuit used in the solid-state image pickup device or the like.
2. Related Background Art
In recent years, many studies have enthusiastically been made for image sensors called CMOS image sensors in which a photoelectric conversion signal is read by not a CCD (Charge-Coupled Device) but a MOS transistor. The CMOS image sensor is used particularly for a portable image sensor in terms of easy on-chip integration of a peripheral circuit because of high compatibility with a CMOS logic LSI process, low driving voltage, and low power consumption.
FIG. 1 is an equivalent circuit diagram showing one pixel of a solid-state image pickup device disclosed in, e.g., Japanese Patent Application Laid-Open No. 4-61573 and the periphery of the solid-state image pickup device. As shown in FIG. 1, each pixel of a conventional solid-state image pickup device comprises a photodiode 1 serving as a photoelectric conversion unit, an amplifier MOSFET 2 for amplifying the charges accumulated in the photodiode 1, a transfer MOSFET 3 for transferring charges from the photodiode 1 to the gate of the amplifier MOSFET 2, a selector MOSFET for turning on the amplifier MOSFET 2, a reset MOSFET for resetting the input node of the amplifier MOSFET 2, a vertical signal line 7 to which a signal amplified by the amplifier MOSFET 2 is read out, and a vertical scanning circuit 6 for outputting a control signal for switching the level between high and low levels to the gates of the amplifier MOSFET 2 and transfer MOSFET 3.
In the pixel shown in FIG. 1, the photodiode 1 converts incident light into an electrical signal, and accumulates the electrical signal. When the vertical scanning circuit 6 supplies a high-level control signal to the gate of the transfer MOSFET 3, the charges accumulated in the photodiode 1 are transferred to the amplifier MOSFET 2 at a predetermined timing. The signal amplified by the amplifier MOSFET 2 is read out to the vertical signal line 7.
FIG. 2 is a partial circuit diagram showing a portion for outputting a control signal ΦTX supplied from the vertical scanning circuit 6 to the transfer MOSFET 3. As shown in FIG. 2, the vertical scanning circuit 6 uses, e.g., a CMOS inverter for outputting the control signal ΦTX.
Two transistors constituting the CMOS inverter have a power supply VH for outputting a high-level control signal, and a power supply VL for outputting a low-level control signal. The ON/OFF states of the two transistors are switched to output a signal based on the potentials of these power supplies, and thus the ON/OFF state of the gate of the transfer transistor is switched.
The potential of each power supply is determined in accordance with a source-drain breakdown voltage VDSX of each transistor. For example, when the breakdown voltage VDSX of each transistor is 5 V, the voltage values of the power supplies VH and VL are set to 5 V and 0 V, respectively.
However, charges transferred to the amplifier transistor include a dark current component in the photodiode or transfer transistor. If charges include a large amount of dark current component, the S/N ratio of an amplified signal read out to the vertical signal line decreases. If light is incident on the Si—SiO2 interface of the gate oxide layer of a transistor forming the transfer transistor, charges are generated. These charges are also superposed on charges transferred from the photodiode, resulting in a lower S/N ratio.
To prevent this, a dark current in the transfer transistor must be stopped from being generated when the transfer transistor having a MOS transistor or the like is interposed between the photodiode and the amplifier transistor. To suppress a dark current generated in the transfer transistor, holes are sufficiently accumulated near the control electrode of the MOS transistor while the photodiode accumulates charges.
When holes are sufficiently accumulated near the control electrode of the MOS transistor, even if electron-hole pairs are generated below the gate oxide layer of the transfer MOSFET 3, the electrons quickly recombine with the accumulated holes, so no dark current flows.
To sufficiently accumulate holes near the control electrode of the MOS transistor, channel may be prevented from being formed in the MOS transistor serving as the transfer transistor. However, such the prevention of formation of the channel in the MOS transistor serving as the transfer transistor degrades the charge transfer characteristic from the photodiode. As a result, an afterimage or the like is generated in an obtained image.
A pixel in which a photodiode is depleted to reset the charges in the photodiode immediately after charges are transferred readily suffers an afterimage and must be improved.
In general, the MOS transistor of a transfer transistor, and a MOS transistor which constitutes a reset switch or selector switch for another purpose are often simultaneously formed. For this reason, channel formation also is prevented in the other MOS transistor, and the performance of the transistor other than the transfer transistor decreases.
As the MOS transistor shrinks in feature size, the power supply voltage applied to a circuit decreases. It is therefore not preferable to prevent channel formation in the MOS transistor in this sense.
Another conventional art will be described. FIG. 3 shows part of a conventional scanning circuit. A case in which this scanning circuit is applied to the vertical scanning circuit of the solid-state image pickup device in FIG. 1 will be explained. An arbitrary row in a pixel area is selected by an output ΦSR from a shift register, and control signals ΦSEL and ΦRES are generated by logical operation between the output ΦSR and an external input pulse ΦSEL′. ΦSEL is supplied to a selector MOSFET 4 for turning on an amplifier MOSFET 2 of a pixel, whereas ΦRES is supplied to a reset MOSFET 5 for resetting the input node of the amplifier MOSFET 2. ΦTX is supplied to a transfer MOSFET 3 for transferring charges from a photodiode to the amplifier MOSFET 2. The shift register shifts a scanning pulse to sequentially read out signals in units of rows, finally obtaining a 1-frame image signal.
In the conventional scanning circuit shown in FIG. 3, the shift register and pulse output circuit operate at the same power supply voltage, so a plurality of output control signals ΦSEL and ΦRES are output pulses within the same voltage range. This poses various limitations.


Silicon photomultiplier circuitry is provided that comprises at least one silicon photomultiplier pixel, each pixel comprising a plurality of silicon photomultiplier microcells. The silicon photomultiplier circuitry comprises control circuitry adapted to maintain a substantially constant voltage on a connection node between microcells of the pixel. The control circuitry is adapted to minimise the onset and recovery time of an output signal by maintaining a substantially constant voltage on the connection node.

The silicon photomultiplier (SPM) is a semiconductor detector which operates in a manner which is similar to the optical and electrical operation of the vacuum tube based photomultiplier tube, or PMT or the microchannel plate, or MCP. The SPM is designed so that the detector converts incident photons into charge, multiplies that charge through an internal gain mechanism and outputs the resulting charge to the output of the SPM detector. In this way photons are converted into currents which can be easily measured using external circuitry.
The basic SPM is a large array of microcells. This is known as a SPM pixel. An array of SPM pixels into a larger area SPM detector is known as a submodule. A larger array of submodules is known as a module. This is detailed in FIG. 1.
The basis for the SPM is the combination of a Geiger mode photodiode which is biased above the breakdown voltage of the diode and the quenching resistor which is used to quench the photodiode and allow the device to recover and allow detection of another photon. The operation of the SPM operation is described in a publication by Z. Y. Sadygov et al., "Avalanche Semiconductor Radiation Detectors", Trans. Nucl. Sci. Vol. 43, No. 3 (1996) pg. 1009-1013. This publication discusses the use of a photodiode which is biased above the breakdown voltage as described by Roland H. Haitz, Model for the electrical behavior of microplasma, Journal of applied physics, vol. 35, no. 5, May 1964, pg. 1370-1376. The use of a resistance to form the passive quenching element required to quench an avalanche breakdown event is discussed in detail in Sadygov. For details of the passive quenching operation, the references by Roland H. Haitz, Studies on Optical Coupling Between Silicon p-n Junctions, Solid-State Electronics, vol. 8, pg. 417-425, 1965 and Robert G. W. Brown and Kevin D. Ridley and John G. Rarity, Characterization of Silicon Avalanche Photodiodes for Photon Correlation Measurements. 1: Passive Quenching, Applied Optics, vol. 25, no. 22, pg. 4122-4126, November, 1986 are recommended. They show the passive quenching of the photodiode which is operated above the breakdown voltage result in a pulse of current flowing through the photodiode during a breakdown event. The full operation of the SPM is detailed in several prior art inventions by the current inventors. These prior art inventions are discussed below.
In our co-pending PCT/GB2006/050123, Light Sensor Module, this patent describes a light sensor module consisting of a number of light sensing elements arranged on a substrate. The module can be operated in a way that produces a combined output signal indicative of an overall level of light falling on the elements. Adjacent light sensing elements sit closely together to form a close-tiled arrangement of the elements covering a large area. This allows a larger area detector to be formed through the use of many smaller detectors combined together.
In our co-pending GB 0621495.1, Method of Assembling a Light Element Module and Light Element Module Assembly, we describe a method of assembling a light sensor module with a light sensing element optically coupled to another optical element, where an intermediate layer is adapted to provide a predetermined level of optical coupling between the optical element and the light sensing element. This allows the formation of a large area arrays of SPM detectors which use an optical layer to provide both electrical connections and the optical coupling to the optical element being viewed or imaged.
In our co-pending GB 0704206.2, Optical Position Sensitive Detector, we describe an optical position sensitive detector which has multiple photosensitive areas, each photosensitive area is capable of producing a signal in response to a photon incident thereon in Geiger mode. Each photosensitive area can provide a signal or signals which may be used to indicate the position of an optical beam incident on the detector surface. This uses a pixellated SPM output which allows for a position sensitive detector to be formed with a high internal gain.
In our co-pending GB 0714770.5, Light Sensor, we describe a method of producing a light sensing arrangement for use in a light sensor. The patent describes how a multiple of individual light sensing elements on a carrier each have a notch formed in them. The purpose of the notch is to allow for electrical connection between the carrier and a surface of the element when the elements are tiled together to form a customisable large detection area.
These allow for the formation of a large area SPM array which is then used to image or to detect light incident onto the array. An issue with the formation of large area detectors however, is the preservation of the timing response of the detectors when they are placed into a large area array. This is particularly important for areas such as high time resolution positron emission tomography, or PET. See reference, Prospects for Time-of-Flight PET using LSO Scintillator, W. W. Moses, and S. E. Derenzo, IEEE Transactions on Nuclear Science NS-46, pp. 474-478 (1999). This system describes a PET system in which the timing properties of lutetium orthosilicate LSO crystals are excited with a 511 keV photon. In a PET system, two 511 keV photons are emitted from the body which are approximately 180 degrees out of phase with one another. The single high energy photon is converted to a number of lower energy photons in the visible spectrum which are detected using a standard PMT in the current state of the art. For LSO approximately 20,000 to 30,000 lower energy visible wavelength photons are emitted for each of the 511 keV photons incident on the crystal. The decay time of the LSO output is approximately 40 ns (See Moses). The challenge for the detection system in a PET system is two fold: First the detectors must be of sufficient high detection efficiency to be able to convert the photons into a measurable response and the detection area is large enough to allow sufficient photons to be obtained. Second the detector must be sufficiently fast to allow the detection of the incident optical pulse with sufficient accuracy to allow the pulse to be measured and analysed. This results in two specifications for PET that must be meet with a detector. These are that the detector must be large area and also fast. As described in Moses, the coincidence resolving time is the time resolution that is obtained from detecting the coincidence between the two photons emitted during a positron annihilation in PET. Because of the speed of light which is a constant given by c=3×10{circumflex over ( )}8 m/s the detector, including both the scintallator crystal and the optical detector must be suitably fast to allow detection of the pulses under with a resolution under 500 ps. This fast resolution is required to allow position of the photon emission to be resolved to a 7.5 cm resolution(see Moses). To increase the resolution, faster detectors are required. It is possible to increase the resolution through repetitive measurements and signal processing, but this slows the data acquisition process and decreases overall system performance. High timing resolution detectors are therefore a requirement for PET. To perform this coincidence timing requires both a fast scintillator crystal, for high energy to lower energy conversion, and a subsequently fast and accurate optical detector with the ability to reconstruct the output pulse from the crystal.
To describe a problem with the current state of the art as appreciated by the present applicant, it is best to review several publications of the inventors and of other state of the art material in the literature. SPM detectors have been shown to have a fast rise time. See the publication by the inventors, Study of the Properties of New SPM Detectors, A G Stewart, E Greene-O'Sullivan, D J Herbert, V Saveliev, F Quinlan, L Wall, P J Hughes, A Mathewson and J C Jackson, SPIE: Semiconductor Photodetectors III, Vol. 6119, 2006. This describes a SPM detector with a 1 mm×1 mm active area with onset times of 1.4 ns and recovery times of 8.7 ns. This active area is too small for many applications requiring large area detection. The inventions of the authors, described in relation to the above-mentioned co-pending applications, were used to overcome the limitations of the smaller area and the subsequent publication, Tiled Silicon Photomultipliers for large area, low light sensing applications, P J Hughes, D Herbert, A Stewart, J C Jackson, Proc. of SPIE: Semiconductor Photodetectors IV, Vol. 6471, 2007 demonstrates the formation of a large area detector with area of 1.2 cm×1.2 cm. This represents a device structure which is 144 times larger than the previous generation of 1 mm×1 mm active area detector. However, as reported in the publication from 2007, the onset response times were on the order of 10 s of nanoseconds. Further analysis and work on this array structure show that the recovery times of the array were degraded significantly over the recovery time of a single SPM pixel. The recovery timing for the array appeared to increase with increasing number of active elements in the array. This results from reducing this to practice show that the output response times are too slow for the recovery of the fast response times that occur in a fast crystal such as LSO, as an example. This is shown graphically in FIG. 2 in which a fast optical source such as a light emitting diode is pulsed via an electrical stimulus. The electrical stimulus is shown in the Figure. This electrical stimulus causes the light source to emit a brief optical pulse which is detected by the SPM submodule. In this Figure we show the response times measured for the SPM submodule of quantity 8 of 3 mm×3 mm SPM pixels. The recovery time for a single SPM 3 mm×3 mm detector was on the order of 50 ns. When the SPM was placed into an array with 8 active elements, the recovery timing degraded to 400 ns which is a factor of 8 times degradation in the output response.
This is unsuitable for high time resolution and fast detection applications such as PET. In patent application WO06111883 A2: DIGITAL SILICON PHOTOMULTIPLIER FOR TOF-PET and WO06111869 A2: PET/MR SCANNER WITH TIME-OF-FLIGHT CAPABILITY the need for high time resolution detection is discussed. In these patent applications the need for high resolution detectors in a PET or PET/MRI system are described. These applications make use of PCT/GB2006/050123, PCT/GB2006/050122 Digital Avalanche Photodiode, WO04102680A1 A Photodiode, and other patents referenced in this invention claim.
An understanding of the problem was obtained by the present applicant after rigorous analysis of the SPM internal operation and the circuitry which is used to drive and measure the current through the SPM during operation of the array.

This patent is subject to a terminal disclaimer.

Method and apparatus to minimise the onset and recovery time of a silicon photomultiplier


Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

Up until now, a memory device including a plurality of non-volatile memory cells has been studied in terms of improvement in an integration degree of the memory cells. In recent years, in order to cope with still higher integration of the memory cells, a memory device has been proposed in which a plurality of memory cells are arrayed three-dimensionally (see, e.g., PTLs 1 to 3).

Sony Semiconductor Solutions Corporation


An integrated circuit includes a plurality of processing modules coupled by a network. A first processing module communicates with a second processing module based on transactions. A first wrapper means associated to the second processing module buffers data from the second processing module to be transferred over the network until a first amount of data is buffered and then transfers the first amount of buffered data to the first processing module.

Systems on silicon show a continuous increase in complexity due to the ever increasing need for implementing new features and improvements of existing functions. This is enabled by the increasing density with which components can be integrated on an integrated circuit. At the same time the clock speed at which circuits are operated tends to increase too. The higher clock speed in combination with the increased density of components has reduced the area which can operate synchronously within the same clock domain. This has created the need for a modular approach. According to such an approach the processing system comprises a plurality of relatively independent, complex modules. In conventional processing systems the systems modules usually communicate to each other via a bus. As the number of modules increases however, this way of communication is no longer practical for the following reasons. On the one hand the large number of modules forms a too high bus load. On the other hand the bus forms a communication bottleneck as it enables only one device to send data to the bus.
A communication network forms an effective way to overcome these disadvantages. Networks on chip (NoC) have received considerable attention recently as a solution to the interconnect problem in highly-complex chips. The reason is twofold. First, NoCs help resolve the electrical problems in new deep-submicron technologies, as they structure and manage global wires. At the same time they share wires, lowering their number and increasing their utilization. NoCs can also be energy efficient and reliable and are scalable compared to buses. Second, NoCs also decouple computation from communication, which is essential in managing the design of billion-transistor chips. NoCs achieve this decoupling because they are traditionally designed using protocol stacks, which provide well-defined interfaces separating communication service usage from service implementation.
Using networks for on-chip communication when designing systems on chip (SoC), however, raises a number of new issues that must be taken into account. This is because, in contrast to existing on-chip interconnects (e.g., buses, switches, or point-to-point wires), where the communicating modules are directly connected, in a NoC the modules communicate remotely via network nodes. As a result, interconnect arbitration changes from centralized to distributed, and issues like out-of order transactions, higher latencies, and end-to-end flow control must be handled either by the intellectual property blocks (IP) or by the network.
Most of these topics have been already the subject of research in the field of local and wide area networks (computer networks) and as an interconnect for parallel machine interconnect networks. Both are very much related to on-chip networks, and many of the results in those fields are also applicable on chip. However, NoC's premises are different from off-chip networks, and, therefore, most of the network design choices must be reevaluated. On-chip networks have different properties (e.g., tighter link synchronization) and constraints (e.g., higher memory cost) leading to different design choices, which ultimately affect the network services.
Introducing networks as on-chip interconnects radically changes the communication when compared to direct interconnects, such as buses or switches. This is because of the multi-hop nature of a network, where communication modules are not directly connected, but separated by one or more network nodes. This is in contrast with the prevalent existing interconnects (i.e., buses) where modules are directly connected.
Modern on-chip communication protocols (e.g., Device Transaction Level DTL and AXI-Protocol) operate on a split and pipelined basis with transactions consisting of a request and a response, and the bus is released for use by others after a request issued by a master is accepted by a corresponding slave. Split pipelined communication protocols are used especially in multi-hop interconnects (e.g., networks on chip, or buses with bridges), allowing an efficient utilization of the interconnect. The efficiently of a split bus can be increased for cases where a response generation at the slave is time consuming. On a pipelined protocol, a master is allowed to have multiple outstanding requests (i.e., requests for which the response is pending or expected).
The above-mentioned protocols are designed to operate at a device level, as opposed to a system or interconnect level. In other words they are designed to be independent of the actual interconnect implementation (e.g., arbitration signals are not visible) allowing the reuse of intellectual property blocks IP and their earlier integration.
In particular, the above-mentioned on-chip communication protocols comprise four main groups of signals, namely commands (or address), write data, read data and write response. The command group consists of command, addresses and command flags like burst length and mask. The command and write data groups are driven by the initiator to the target. The read data and write response are driven by the target to the initiator following a command from an initiator. All four groups are independent of each other with some ordering constraints between them, e.g. a response cannot be issued before a command.
These on-chip communication protocols also implement the concept of buffering data which is well-known in the art of chip design. Typically, buffering is used to decouple different modules, wherein one module produces data and the other consumes the data. Without buffering, the producing module would be blocked by the consuming module until it is ready to accept its data. In order to avoid the blocking of the producing module, a buffer may be introduced, storing the data produced by the producing module and thus allowing the producer to continue its execution even when the consuming module is not ready. When the consuming module is ready to accept some or all buffered data, the data stored in the buffer is immediately supplied to the consuming module.
On the other hand modern on-chip communication protocols also use the buffering of write commands or data in order to improve the interconnect utilization. Accordingly, small write bursts are stored or accumulated in a buffer before they are sent over an interconnect. Instead of being transferred in short burst, the accumulated data will be transported in a long burst over the interconnect, which usually leads to an improved interconnect utilization. This may be implemented by buffering first write data W1 (i.e. the data is not transferred over the interconnect) which is then not transferred until for example a second write data W2 arrives in the buffer, such that they are transferred as one burst with an optimal length with regards to the interconnect utilization.
Therefore, data from a number of writes can be buffered and aggregated in one burst. In addition, parts of the data in write commands may be sent in separate bursts.
The reason for the implementation of this buffering technique in the above-mentioned on-chip communication protocols is that the intellectual property blocks IP in a system on-chip connected by an interconnect should be able to communicate "naturally", i.e. the word width and the burst sizes are configured such that they rather suit the device than the interconnect. For example, if an intellectual property block IP processes pixels, then these intellectual property blocks consume and produce pixels, while in the case that they process video frames, they consume and produce video frames. By buffering the data, the data to be transmitted over the interconnect is forced to wait until a sufficient amount of data is gathered such that these data can be transferred at once in a burst.
The above-mentioned on-chip protocols have been designed mainly for buses with a small latency. In addition, these protocols have been designed based on the assumption that read operations are always urgent and should therefore be completed as soon as possible without unnecessary buffering. However, as systems grow larger and multi-hop interconnects like networks or buses with bridges, the latency grows as well. In these cases the communication granularity become coarser and the latency requirements become less strict.
In addition, these protocols comprise means to force some of the currently buffered data to be transferred although the optimal burst length has not been reached in order to prevent deadlock caused by buffering data indefinitely. The DTL communication protocol provides a flush signal forcing all data up to the current word to be transferred over the interconnect. The AXI protocol provide an unbuffered flag for write commands to force buffered data to be transferred.
It is therefore an object of the invention to provide an integrated circuit, a method for buffering as well as a data processing system with an improved interconnect utilization.
Therefore, an integrated circuit comprising a plurality of processing modules coupled by an interconnect means is provided. A first processing module communicates with a second processing module based on transactions. A first wrapper means associated to said second processing module buffers data from said second processing module to be transferred over said interconnect means until a first amount of data is buffered and then transfers said first amount of buffered data to said first processing module.
Accordingly, data is buffered on the slave side until a sufficient large amount of data to be transferred over the interconnect in a single package is reached. Reducing the number of packets sent over the interconnect reduces the overhead of the communication as less packet headers are required. The data to be sent is buffered until a sufficient amount of data is gathered.
According to an aspect of the invention, a second wrapper means is associated to the first processing module for buffering data from said first processing module to be transferred over the interconnect means to said second processing module until a second amount of data is buffered and said second wrapper means then transfers said buffered data to said second processing module. Therefore, data is buffered on the master as well as on the slave side until a sufficient large amount of data to be transferred over the interconnect in a single package is reached.
According to a further aspect of the invention said first and second wrapper means are adapted to transfer the buffered data in response to a first and second unbuffer signal, or a particular combination of a group of signals, respectively (even if less than the first and second amount of data is buffered in said first and second wrapper means). By issuing the unbuffer signals an occurrence of a deadlock due to a processing waiting for the buffered data can be avoided.
According to a further aspect of the invention said first and second wrapper means are adapted to transfer the buffered data according to a first and second unbuffer flag, respectively (even if less than the first and second amount of data is buffered in said first and second wrapper means). Therefore, an alternative approach to flush buffered data is provided. As opposed to the signal, which is given for each transaction, the flag may be set for a longer time. In this way, the buffering can be switched on or off. The flag can be set/unset in any way, e.g., with a signal from the IP as part of a transaction, or via separate configuration transactions (either special flush transactions or a memory-mapped reads and writes). These transactions can be issued either from the same IP, or from a separate configuration module.
According to a preferred aspect of the invention at least one of said first and second wrapper means comprise a determination unit BLDU for determining the optimal first or second amount of data to be buffered in said first or second wrapper means before said data is transferred according to the communication properties of said communication between said first and second processing module. Accordingly, the packet size of the data transferred over the interconnect can be adapted according to the properties of the actual communication and thereby the utilization of the interconnect can be improved.
The invention also relates to a method for buffering data in an integrated circuit having a plurality of processing modules being connected with an interconnect means, wherein a first processing module communicated to a second processing module based on transactions, comprising the step of buffering data from said second processing module to be transferred over the interconnect means until a first amount of data is buffered, wherein the buffered data are transferred when said first amount of data has been buffered.
The invention further relates to a data processing system comprising an integrated circuit comprising a plurality of processing modules coupled by an interconnect means is provided. A first processing module communicates with a second processing module based on transactions. A second wrapper means associated to said second processing module buffers data from said second processing module to be transferred over said interconnect means until a first amount of data is buffered and then transfers said first amount of buffered data to said first processing module.
Accordingly, the buffering of data as described above can also be applied in a system comprising a plurality of integrated circuits.
The invention is based on the idea to buffer data until the buffered data is sufficiently large to be transferred optimally over an interconnect means in a packet. The larger a packet is, the smaller is the amount of packet headers and therefore the overhead is reduced and the interconnect is utilized more efficiently. The data is only transferred when sufficient data for an optimal packet size has been buffered even when data can be sent earlier. The data is only transferred from the buffer when the conditions for an optimal transfer are satisfied.
Further aspects of the invention are described in the dependent claims.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiment (s) described hereinafter.

Integrated circuit and method for buffering to optimize burst length in networks on chips


According to one embodiment of the invention, there is provided a telephone system comprises a plurality of telephone terminals and a main unit. The main unit comprises an authentication processing unit performs login authentication MAC address authentication, and a mode specification unit receives specification of a plural terminal registration mode. The MAC address authentication refuses logins from telephone terminals differing in MAC address from a telephone terminal that has been allowed to log in firstly even if the logins are made by the same extension numbers. The plural terminal registration mode exclusively allows the simultaneous login by the same extension numbers from a plurality of telephone terminals having different MAC addresses. The authentication processing unit gives priority over the plural terminal registration mode higher than the MAC address authentication and makes the MAC address authentication void in the plural terminal registration mode.

1. Field
The invention relates to a telephone system for use in as a private extension telephone system, etc., and a main unit and a terminal registration method therefor. More specifically, the present invention relates to an improvement of a system in which a key telephone system and an Internet Protocol (IP) telephone terminal are combined.
2. Description of the Related Art
In recent years, as regards a telephone system, Voice over IP (VoIP) which enable voice communication over an IP network has become mainly used. This kind of system includes a login/logout function which is similar to a function applied to personal computers. Under this function, when logging in from a telephone terminal to the system, a user may use the terminal, by which the user has logged in, as a terminal specifically for his/her use. That is, the user may utilize original setting of a button function, telephone directory data, etc., without any concerns for the presence of himself/herself.
In authentication of a telephone terminal resulting from a login operation, a system referred to as media access control (MAC) address authentication has been generally used (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2005-117355). In this system, for performing the login operation, a password, and an extension number and an MAC address of the telephone terminal are reported to a main unit. The main unit refers to the information, and if the main unit OK'd the MAC address authentication, the main unit returns the fact to the terminal at a login origin, and completes the registration of the terminal in the system.
Meanwhile, a plurality of terminals which are located at different places request registration with the identical extension numbers in any cases. Under a service function frequently used and so called a mobile number, such requests are made often. For such a case, for example, the following (1)-(3) are possible approaches. 'A currently registered terminal' means a terminal which is registered at present, and 'a new registration requesting terminal' means a terminal which has requested later with the same number as that of the currently registered terminal.
(1) Takes preference the new registration requesting terminal and erases the registration of the currently registered terminal.
(2) Registers the new registration requesting terminal in addition to the currently registered terminal.
(3) If the currently registered terminal has been in speech when the new registration requesting terminal requested its registration, restricts the registration of the new registration requesting terminal.
The MAC address authentication are harder restricted than any of the given approaches (1)-(3), even if the user logs in with the identical extension numbers and passwords, only one terminal which has firstly requested its registration may be authenticated. To allow the registration for a plurality of terminals, a maintenance operator has to disable the MAC address authentication by a manual operation. Meanwhile, from the point of view of security, it is preferable to adopt the MAC address authentication; it has been required to cope with both security and convenience in some kind of forms. Further, it is needed to take time and effort or operation omission of an operator to release the MAC address authentication, and some sort of technical development has been expected.

Telephone system, and main unit and terminal registration method therefor


A housing and a power cable for supplying power to components within the housing wherein the power cable is attached to the appliance via a rotatable connection, the rotatable connection comprising a male connector having two longitudinally spaced connectors separated by a separator and a female connector comprising two longitudinally spaced receptacles. The two longitudinally spaced receptacles may be substantially identical and may be shaped to receive the longitudinally spaced connectors and may have a base portion and two upstanding portions forming a U-shape. The two upstanding portions may have a first straight section that extends from the base portion and may have a second section which extends from the first section and is adapted to receive a longitudinally spaced connector and may have a third section which extends from the second section and provides an opening into which a longitudinally spaced connector can be inserted.

Power cables on hand held appliances have two forms. Firstly where rotation of the appliance with respect to a user is unlikely such as with power tools or hairdryers. Secondly where rotation of the appliance with respect to the user is important to the function of the appliance such as hot styling appliances, straighteners and curling devices such as tongs, wands or irons. There is a requirement to provide a continuously rotating electrical connection in the second case so that power from a power cable can be provided to a heater and/or fan unit within the appliance without significant loss of contact otherwise the user could perceive a loss of connection by a drop in temperature and/or flow rate or a longer styling time.


A computer-executable information tracking method, an image forming apparatus, an information processing apparatus, and a program to adequately track the information flow of a paper document are disclosed. The method includes a first detecting step of, whenever an input or output of information is performed using a paper as a medium, detecting paper identification information that uniquely identifies the paper from other paper; a storing step of associating and storing the paper identification information with information regarding the input or output of information in a recording device; a second detecting step of detecting the paper identification information of a designated paper; an information searching step of searching for the information regarding the input or output of information on the designated paper by comparing the paper identification information of the designated paper with the paper identification information stored in the recording device.

1. Field of the Invention
The present invention generally relates to an information tracking method, an image forming apparatus, an information processing apparatus, and an information tracking program.
2. Description of the Related Art
Recently, with the development of IT systems, important documents have been widely leaked and the leakage (unauthorized disclosure) of information has become a serious problem. Various measures to prevent the leakage of electronic documents have been taken based on security technologies such as user identification and access control. However it is conceived that measures to prevent the leakage by delivering a paper document are being left behind. As a conventional example to prevent the leakage by delivering a paper document, there is a method of stamping a secret mark on the document. However it has nothing more than a psychological deterrent effect. There is another method of adding information of time and who printed or copied the output document. See, for example, Patent Document 1: Japanese Patent No. 3265621.
However, when information is leaked by delivering a paper document, conventional techniques do not provide sufficient measures to accurately determine who leaked the document and who received the document. Without being able to identify who leaked the information, even when the leakage is acknowledged, the leakage of the information may continue. Without being able to identify who receives the leaked information, there remains a problem that further leakage cannot be prevented.

Information tracking method, image forming apparatus, information processing apparatus, and information tracking program


Surgical procedures on the beating heart are enabled by an incision made in the xyphoid area and specially designed retractors and related devices to facilitate cardiac surgical procedures. Specifically, coronary artery bypass graft procedures (CABG) are achieved using a vertically offsetting retractor or access platform in combination with a beating heart stabilizer. The surgical methodology permits procedures such as the CABG procedure without penetrating the rib cage or performing a sternotomy or thorocotomy.

Prior techniques to reduce the trauma and expense of cardiac surgery include closed chest procedures using specially configured catheter-based apparatus to achieve cardiopulmonary bypass (CPB) combined with less invasive port-access type incision and special techniques and apparatus to eliminate CPB by employing a minimally invasive surgical technique and performance at the surgical procedure on the beating heart. These existing closed chest procedures eliminate the trauma associated with an open chest incision but still have the drawbacks associated with CPB. The existing beating heart procedures avoid CPB but still typically require a transthoracic incision, i.e., an incision that penetrates the rib cage in some fashion. Thus, while these approaches provide a less invasive procedure compared to the traditional medial sternotomy or thoracotomy, any procedure that traverses the ribs or sternum may cause complications and may slow the post-operative recovery of the patient.

Xyphoid access for cardiac surgical procedures


A chiral nematic type liquid crystal display device in which the twist angle of a torsional structure of a liquid crystal layer is as large as 180.degree. to 360.degree. and the birefringence of liquid crystal molecules is utilized. This liquid crystal display device is characterized in that: a liquid crystal layer is disposed between opposed substrates and orientation films formed of straight chain polymer having fluoro-alkyl side chain C.sub.n H.sub.m F.sub.2n+1-m (n being a natural number and m being a natural number of 0 or 2n or less) are provided on the respective inner surfaces of said substrates facing the liquid crystal layer.

1. Field of the Invention
This invention relates to a liquid crystal display device having a liquid crystal layer in which liquid crystal molecules are oriented in a twisted structure and more particularly it relates to a liquid crystal display device in which liquid crystal molecules are oriented stably in a state suited for high speed operation even if the twisted structure has a large twist angle.
2. Description of the Prior Art
U.S. Pat. No. 3,918,796 discloses a twist nematic liquid crystal display device in which liquid crystal molecules are oriented to have a twisted structure of 90.degree.. Such a liquid crystal display device having 90.degree. twisted orientation has however a narrow viewing cone and is not suited for high level multiplexing drive. For example, in a display device of a matrix type, the contrast is decreased as the multiplexing ratio is increased, and when the display device is driven by a multiplexing ratio of 1/100, the contrast value becomes 3 to 5, which value can not put the device to practical use. Moreover, this contrast value is a value in case of viewing the display from a specified direction and the range of the visual angle is limited to about 20.degree. or less in any direction with respect to a line perpendicular to the display face. Consequently, it follows that such a liquid crystal display device can not be applied to a large-area display (such as dot matrix display having a high resolution).
In view of the above described situation, studies were pursued as to the twist angle of liquid crystal. As a result, a liquid crystal display device using another display mode was proposed as disclosed in European Patent Application Laying-Open Gazette EPO-131,216. In this liquid crystal display device, the twist angle of a liquid crystal layer is made as large as 160.degree. to 360.degree. and by utilizing the birefringence of liquid crystal molecules, a practically applicable contrast value can be obtained even if the display device is driven at a multiplexing ratio of 1/100 to 1/200.
However, for a liquid crystal display device utilizing the above described display mode, it is required to make stable the orientation of liquid crystal molecules (namely, to take measures for undesirable domain and measures for pretilt angle control). To take measures for undesirable domain is to prevent lack of uniformity in the orientation due to increase of a twist angle. For example, if the liquid crystal molecules are forced to have a clockwise orientation, an anticlockwise orientation or an orientation of a different twist angle is partially occurred. When such phenomenon occurs, there is caused an ununiformity in the colors in the non-operated state or the response time in the operated state of the display device, resulting in a considerable decrease in the quality of display. On the other hand, to take measures for pretilt angle control is to prevent slow-down in the response time due to a low pretilt angle formed by liquid crystal molecules with respect to a substrate surface. Although a high molecule orientation film used for 90.degree. twisted orientation has a pretilt angle of 0.degree. to 2.degree. (low pretilt angle), a pretilt angle in this display mode is required to be 5.degree. or more, preferably 10.degree. to 30.degree. (high pretilt angle). Further, in case of a low pretilt angle in the above described mode, undesirable domains are liable to occur due to application of the threshold value.
In this regard, the above stated EPO-131,216 uses an orientation film obtained by evaporating an inorganic material obliquely onto a substrate so that a high pretilt angle orientation is obtained. However, since the incidence direction of evaporation is an important factor in making such an orientation film, such an orientation film obtained as a uniform film has a limited area, i.e., an area of only 10cm.sup.2 at most. In addition, an acceptable allowance of thickness of a liquid crystal layer is small in this display mode and as a result if the thickness of the orientation layer lacks uniformity, this display device can not be used. For those reasons, such an oblique evaporation method is not suitable for production of a large-area display device or mass production of such display devices.


A system provides high availability electronic message forwarding. When an electronic message is communicated to a first server, a copy of the electronic message is maintained at a second server. The electronic message is maintained on both servers until the electronic message is successfully communicated to a third server. After the message is delivered to the third server, the electronic message is removed from both the first server and the second server. If the first server fails to communicate the electronic message to the third server, the second server does so.

Electronic messaging systems such as those for providing, for example, electronic mail and instant messaging, have become ubiquitous in modern society. Electronic messaging systems have been used for years in academic and corporate settings, and are now widely used in the individual consumer market. Indeed, electronic messaging has become so pervasive that it is quickly becoming a preferred means of communication for many corporations and individuals.
Generally, an electronic message is communicated through a plurality of messaging servers before it ultimately is saved in a message box of the intended recipient. For example, an electronic message may be received at a first messaging server, and then forwarded to a second messaging server, and then to a third messaging server, and so on until the messaging server is received at the messaging server responsible for receiving messages for the intended recipient. At each in the series of messaging servers that are responsible for communicating the electronic message, the electronic message is deleted after the messaging server forwards it to the next in the series. When the electronic message is received at the messaging server that services the intended recipient, the electronic message is stored in the recipient's message box.


Disclosed is a method including receiving a rule having at least one rule case for producing an output value based on one or more input values, generating a transform for receiving data from an input dataset and transforming the data based on the rule including producing a first series of values for at least one output variable in an output dataset, at least one value in the first series of values including a second series of values, and providing an output field corresponding to the at least one output variable in the output dataset for storing the second series of values.

This description relates to processing data using vector fields.
Some computing systems provide an interface for specifying rules that are used for automated decision making in various data processing applications. Decisions associated with processing data representing credit card transactions or airline frequent flyer programs, for example, may be governed by a given set of rules. In some cases, these rules are described in human-readable form. The computing system may provide an interface for a user to define or edit these rules, and then incorporate the rules into a data processing system.


A facial support mask supports the face of a patient in the prone position during surgical procedures in spaced relation above a support surface and in a variety of selectively fixed positions relative to the torso and the support surface. The mask has a plurality of transversely spaced longitudinal crescent arms; at least one cross-strut interconnected with the longitudinal crescent arms; an inflatable chamber attached to the crescent arms and adapted to contact the patient's forehead and sides of his face; means and securement strap for securing the mask to the patient's face. The mask may also include an integral secretion collection dish for draining away secretions during the surgical procedure. The method includes providing a facial support mask for supporting a patient's face during surgical procedures in the prone position; anesthetizing the patient; placing said mask on patient's face such that no part of said mask contacts the patient's eyes, nose, or lips; securing said mask to patient's face; rolling the patient into the prone position; adjusting the inflation of the chamber to obtain correct inflation pressure; adjusting the patient's head orientation; and draining of any patient secretions.

1. Technical Field
The apparatus and method of the invention relate generally to the performance of surgical procedures. More specifically, they relate to an apparatus and method for protecting a patient's face during surgical procedures performed in the prone (face down) position while resting on a support surface.
It is well known in the art that a patient is especially vulnerable to facial injury when surgery is performed in the prone position. The nose, certain nerves, and especially the eyes are all at risk of compression injury any time an anesthetized patient is resting on his or her face during surgery. It is thus critically important that some means be provided for supporting the patient's head in a manner that protects the sensitive areas from any pressure during the surgical procedure.
2. Description of the Prior Art
Existing techniques for supporting the patient's head and protecting the face during prone-position procedures are generally unreliable and potentially ineffective. Commonly, anesthesiologists will use foam rubber donuts and stacks of small towels to support the head. However, the doctor frequently is operating in the blind, not knowing for certain the eyes and nose are not being subjected to pressure, since the position of the nose, mouth, or eyes can not be verified visually by the physician once the donut and towels have been installed.
Another prior art technique is to use a pair of pads connected by plastic arms with the forehead and chin resting on the pads. A major problem with this technique is that the total weight of the head is distributed on only these two points. This may cause skin sloughing at these two points.
An additional problem with prior art devices is their inability to provide for adjustment of the patient's head relative to the torso and support surface. Generally, these prior art devices limit the patient's head position to the "neutral" or centerline position. It is generally desirable however that a patient's head be adjustable relative to the torso and support surface to accommodate different surgical techniques and procedures.
A further limitation of prior art devices are their lack of any provision for the collection and draining away of any patient secretions during the surgical procedure. All patients to varying degrees "drool" during surgical procedures. Additionally, and of more concern, patients will often drain mucus or blood during the procedure. This is potentially hazardous to operating room personnel as it may expose them to infectious agents.
An illustration of these prior art devices and the problems associated therewith, is Voss, U.S. Pat. No. 4,752,064. Voss provides a means for supporting a patient's head over a large area by using a foam donut, thereby eliminating the problem of pressure points. However, there is no provision for drainage of any secretions. Neither is there any means for adjusting the position of the patient's head in either a rolling side to side direction or a pivot forward or backward. Additionally, due to the foam nature of the headrest, the physician is not able to visually verify the position of the patient's eyes and nose once the patient's head has contacted the headrest. Also, due to the fixed structure of the foam, points of relatively high pressure on the patient's face are still likely and somewhat unpredictable due to variations in facial structures.
Therefore, it is a prime objective of the present invention to provide an apparatus which is capable of supporting and protecting a patient's face during prone-position surgical procedures.
Another object of the present invention is to provide an apparatus which is capable of supporting a patient's face during prone-position procedures in a variety of selectively fixed angles relative to the patient's torso and the support surface.
Still another object of the present invention is to provide an apparatus which provides support for the patient's face over an extended region permitting the weight of the head to be distributed over a larger surface area.
Yet another object of the present invention is to provide an apparatus which permits the doctor to visually verify that the patient's nose, eyes, and other facial structures are not being exposed to any pressure during the surgery.
Another object of the present invention is to provide a facial support apparatus which is at least partially reusable.
Still another object of the invention is to provide an apparatus where the inflation of the mask may be varied to allow for maximum surface area contact with the skin, thereby minimizing the amount of pressure applied at any given point on the skin.
Finally, an object of the present invention is to provide an apparatus which permits the collection and drainage of any secretions by the patient during the surgical procedure.

Surgical face mask support apparatus and method


A component of a system accesses a link identifier that is associated with a mobile station. A component of the system modifies the link identifier to include a routing label that allows a base station to route one or more messages to a serving processor.

The invention in one embodiment relates generally to telecommunications and more particularly to support of messaging that is related to base stations.
One implementation of a network employs a frame relay interface between all base stations and serving general packet radio service support nodes. The frame relay interface generally comprises a point-to-point link. Each serving general packet radio service support node comprises a single processor. So, one-to-one relationships exist between the base stations and the serving general packet radio service support nodes. Typically, a mobile station sends a message to a closest one of the base stations for routing of the message to a serving general packet radio service support node that is dedicated exclusively to that particular one of the base stations.
As one shortcoming, such an implementation has undesirably limited capacity for a set amount of resources, since each base station requires the exclusive dedication of a serving general packet radio service support node to the base station. As another shortcoming, the implementation has disadvantageously limited reliability since an occurrence of unavailability of a serving general packet radio service support node that previously supported a particular base station, requires the implementation to have another serving general packet radio service support node available for exclusive dedication to the base station to effect continued processing support for messaging that is related to the particular base station.
Thus, a need exists for enhanced usability of a resource that supports messaging related to base stations. A further need exists for enhanced reliability of a resource that supports messaging related to base stations.
Pursuant to one embodiment of the invention, shortcomings of the existing art are overcome and additional advantages are provided through the provision of modification of a link identifier to include a routing label that allows base station message routing to a serving processor.
The invention in one embodiment encompasses a method. A link identifier that is associated with a mobile station is accessed. The link identifier is modified to include a routing label that allows a base station to route one or more messages to a serving processor.
Another embodiment of the invention encompasses a system. The system includes a component that accesses a link identifier that is associated with a mobile station. The system includes a component that modifies the link identifier to include a routing label that allows a base station to route one or more messages to a serving processor.
A further embodiment of the invention encompasses an article. The article includes a computer-readable signal-bearing medium. The article includes means in the medium for accessing a link identifier that is associated with a mobile station. The article includes means in the medium for modifying the link identifier to include a routing label that allows a base station to route one or more messages to a serving processor.

Modification of link identifier to include routing label that allows base station message routing to serving processor


An optical recording medium including a substrate, a metal underlayer deposited over the substrate wherein the underlayer has a substantially low thermal conductivity, a recording layer over the metal underlayer, and a transparent protective layer over the recording layer.

In magneto-optical recording medium frequently embodied in a disk, information in the form of magnetic domains is written on the recording layer having perpendicular anisotropy. This information is read by irradiating the medium with a linearly polarized laser beam and detecting the change of the incident laser beam caused by the interaction of the light with the magnetization. Kerr rotation, coercivity, sensitivity and carrier to noise ratio are critical parameters to be considered for achieving high performance magneto-optical medium.
Currently rare earth-transition metal alloy layers are used as the recording medium. An inherent disadvantage of such layers is that they are highly susceptible to corrosion and oxidation resistance.
When such a layer is deposited directly on the substrate made of organic material such polycarbonate (PC) and polymethylmethacrylate (PMMA), the MO layer does not possess a square Kerr hysteresis loop which is essential for obtaining high performance. For this purpose, the MO recording layer is sandwiched between two layers of ceramics such as, for example, AlN and SiN. These dielectric layers also enhance their environmental stability. However, these dielectric layers are difficult to deposit in a reliable fashion. The reactive sputtering process which is generally used to deposit the dielectric layers may also damage the sensitive substrate and generate mechanical stresses which also may cause the failure of the disk structure. Protective overcoats of active metals such Ti and Cr have been utilized earlier to protect the recording medium eliminating the top overcoat of dielectric (commonly assigned U.S. Pat. No. 4,877,690 to D. Glocker, T. K. Hatwar, S. T. Rao, G. L. McEntyre, and D. G. Stinson). For such a disk the recording and reading was done through the substrate. For front surface recording the metal overcoats can not be used because of their high absorption coefficient.

Magneto-optical structure having titanium underlayer


A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.

Lithographic processes may be used to manufacture electrical connections on a circuit board or a semiconductor package substrate to enable electrical connections between different components. It may be desired to reduce the costs, the complexity or the manufacturing time of circuit boards or package substrates or increase the flexibility of the wiring of circuit boards or package substrates.

Carrier substrate for a semiconductor device and a method for forming a carrier substrate for a semiconductor device


Incorporating into a fixed bed reactor for an exothermal reaction having a catalyst supported on a support having a thermal conductivity typically less than 30 W/mk within the reaction temperature control limits heat dissipative particles having a thermal conductivity of at least 50 W/mk less than 30 W/mk within the reaction temperature control limits helps control the temperature of the reactor bed.

U.S. Pat. No. 6,013,741 issued Jan. 11, 2000 to Ohtani et al., assigned to Mitsui teaches the design of a reactor to permit the rapid introduction of a kill gas into a fluidized bed reactor to rapidly stop a reaction in the event of an equipment failure.
U.S. Pat. No. 8,435,920 issued May 7, 2013 to White et al., assigned to Eltron Research & Development, Inc. refers at Col. 1 lines 45 through 66 to Lyon which teaches the use of metal oxide catalysts in the partial oxidation of hydrocarbon feeds. The reference does not refer to using inert metallic dilluents in a reactor bed.
There are a number of United States patents assigned to Petro-Tex Chemical Corporation issued in the late 1960's that disclose the use of various ferrites in a steam cracker to produce olefins from paraffins. The patents include U.S. Pat. Nos. 3,420,911 and 3,420,912 in the names of Woskow et al. The patents teach introducing ferrites such as zinc, cadmium, and manganese ferrites (i.e. mixed oxides with iron oxide). The ferrites are not inert and release oxygen to react with the hydrocarbon stream. The ferrites are introduced into a dehydrogenation zone at a temperature from about 250° C. up to about 750° C. at pressures less than 100 psi (689.476 kPa) for a time less than 2 seconds, typically from 0.005 to 0.9 seconds. The reaction appears to take place in the presence of steam that may tend to shift the equilibrium in the "wrong" direction. Additionally the reaction does not take place in the presence of a catalyst.
U.S. Pat. No. 2,267,767, issued Dec. 30, 1941 to Thomas, assigned to Universal Oil teaches the use of non porous metallic substrates as supports for catalysts for the treatment of hydrocarbons. The metallic substrates are treated with non aqueous solutions of a metallic alkoxide and an alkyl ortho silicate. The substrate appears to be a component for the reaction. The metal oxides may be alumina, zirconia, thoria, vanadia, magnesia and other metal oxides which are active in the cracking and or reforming reactions.
U.S. Pat. No. 2,478,194 issued Aug. 9, 1949 assigned to Houdry Process Corporation teaches a composite shaped catalyst and support comprising a metallic component such as iron or steel. The metallic component may take a number of shapes such as an "I" a cross, or even the shape of a child's jack. The catalytic component is then applied to the metallic support to form the catalyst. The metallic component provides an oxidation promoter not an inert heat sink.
The fixed bed reactor is a workhorse of the petrochemical and refining industry. In commercial reactors the ratio of reactor diameter to effective particle diameter is at least 50:1 generally greater than 500:1. Catalyst supports generally have a low thermal conductivity. Under these conditions there is a low transfer of heat from the interior of the fixed bed to the reactor wall where heat may be dissipated. These conditions may lead to localized hot spots which can be the center for a runaway reaction, particularly for exothermic reactions.
The present invention seeks to provide a fixed bed of catalyst and a metallic diluent having a thermal conductivity of greater than 30 W/mK (watts/meter Kelvin) within the reaction temperature control limits to permit the transfer of heat within the bed and also out of the bed.

Heat dissipating diluent in fixed bed reactors


A rotating type thin film deposition apparatus having an improved structure that allows continuous deposition, and a thin film deposition method used by the rotating type thin film deposition apparatus are provided. The rotating type thin film deposition apparatus includes a deposition device; a circulation running unit that runs a deposition target on a circulation track via a deposition region of the deposition device; and a support unit that supports the deposition target and moves along the circulation track. Thin layers can be precisely and uniformly formed on the entire surface of a deposition target, and since deposition is performed while a plurality of deposition targets move along a caterpillar track, a working speed is faster compared to a method involving a general reciprocating motion, and the size of the thin film deposition apparatus can be reduced.

1. Field of the Invention
One or more embodiments of the present invention relate to a thin film deposition apparatus, in which vapor generated in a deposition source is deposited on the surface of a deposition target, and more particularly, to a rotating type thin film deposition apparatus having an improved structure that allows continuous deposition, and a thin film deposition method used by the rotating type thin film deposition apparatus.
2. Description of the Related Art
A deposition process whereby vapor generated in a deposition source is deposited on the surface of a deposition target, such as a substrate, is widely used in a thin film manufacturing process, such as a thin film transistor manufacturing process of an organic light-emitting display apparatus.
An atomic layer deposition (ALD) process, whereby a thin film may be more uniformly and precisely formed, has been recently preferred. In such an ALD process, deposition is repeatedly performed at the same position of the deposition target more than 300 times.
When deposition needs to be performed on a deposition target several times, like in the ALD process, deposition is performed repeatedly while moving the deposition target relative to a deposition device in a reciprocating manner.
However, when deposition is performed while the deposition target is moved relative to the deposition device in a reciprocating manner, an acceleration and deceleration period is continuously generated whenever the direction of movement of the deposition target is changed. Thus, it is not easy to maintain uniform process conditions. That is, when the deposition target is moved relative to the deposition device only at a constant speed, the instants of time when the deposition target faces the deposition device are all the same, and thus, uniform deposition may be performed. However, during an acceleration and deceleration period, the instants of time when the deposition target faces the deposition device are different in every period, and thus, it is difficult to ensure uniform deposition.
In addition, in a method whereby the deposition target is moved relative to the deposition device in a reciprocating manner, since deposition on the deposition target is completed and then deposition on the next deposition target can be performed, a working speed is very slow. In order to solve this problem, if a plurality of deposition targets are arranged in one line and are simultaneously moved relative to the deposition device in a reciprocating manner, a space in which all the plurality of deposition targets are moved relative to the deposition device needs to be formed. Thus, the size of the deposition device needs to be considerably large.
Thus, a new type of deposition method for addressing these disadvantages is required.

Rotating type thin film deposition apparatus and thin film deposition method used by the same


Ceramics resulting from the oxide system barium oxide-rare earth oxide-titanium oxide have been found to exhibit an isotropy with respect to electrical properties such as the temperature coefficient of frequency at the first resonant frequency, dielectric constant, and, to some extent, the loss factor, Q. Such anisotropy effects reproducibility in fabricating ceramic articles for use in the microwave region and in the performance of these articles. Isotropic ceramics from the same ternary oxide system can be made by compacting non-nucleated powders followed by the usual sintering of the green compact. Anisotropic bulk ceramic workpieces can be machined to reproducibiy afford ceramic articles with the appropriate value of the electrical property in question by measuring the components of the electrical property along the three principal axes of the workpiece, and then determining the angles between the principal axes necessary to give a resultant having the preselected value.

Ceramics which are prepared from oxides of the system barium oxide-titanium oxide-rare earth oxide, where the rare earth is one of the lanthanum series, have found broad use in components used in the microwave region of the electromagnetic spectrum, especially as filters. Recently it was observed that certain electrical properties, such as the temperature coefficient of frequency, T.sub.f, were highly variable, depending upon the forming process used and the method of sampling the ceramic for electrical testing. Since reproducible electrical properties are a prerequisite in providing ceramics for the microwave industry these observations were understandably vexing and led to a program whose purpose was the elucidation of the origin of the observed variability. To our surprise we discovered that barium oxide-rare earth oxide-titanium oxide ceramics made via prereacting (calcining) a suitable powder, forming using uniaxial pressing, and sintering exhibited anisotropy with respect to the electrical properties in question. Although anisotropy in other ceramics has been recognized previously, there is no hint or suggestion of anisotropy in the class of ceramics under discussion. Once the existence of anisotropy was observed as the source of the problem of variability in electrical properties, two avenues of addressing the problem became clear. One avenue involved the preparation of the same class of ceramics but with the anisotropy eliminated. The second avenue accommodates anisotropy by first recognizing and measuring its degree, and then machining the apparatus along appropriate dimensions to reproducibly and consistently furnish ceramic articles reflecting the desired values of selected electrical properties. Quite related to the latter is the production of ceramic articles having the desired values of selected electrical properties maximized or minimized. In turn these are merely specific manifestations of the more general characteristic of reproducibly obtaining a preselected set of values of electrical properties from a bulk ceramic workpiece exhibiting anisotropy with respect to the electrical properties of interest.

Barium oxide-rare earth oxide-titanium dioxide based ceramics exhibiting isotropy


Pulse type activating system for power supply, composed of a boosting circuit, a pulse width modulating (PWM) circuit, a sine-wave generating circuit, an MOSFET output circuit, an analog-to-digital converting circuit (ADC), a temperature sensing circuit, an overload detecting circuit, a short circuit detecting circuit, a warning circuit and a CPU. The CPU collectively controls the above circuits and in the instant of activation of the load, the CPU provides intermittent high voltage for shortening the activation time of the load. The CPU also provides protection effect for the load.

The present invention relates to a pulse type activating system for power supply, in which a CPU collectively controls respective circuits and provides intermittent high voltage for shortening the activation time of the load. The pulse type activation system is especially applicable to those heavy tools necessitating great current and great voltage.
When activating a general electric appliance, the instantaneous activating current is very great. With 100 watt electric appliance exemplified, the instantaneous activating current is over 2-3 times higher than the original current. The instantaneous great current is extremely apt to damage the circuit of the electric appliance itself. A general DC-to-AC power supply is unable to provide sufficient high surge so that the ability in activating the electric appliance is affected. FIG. 1 shows a current versus time (A-T) curvature of a conventional power supply. It can be known from the diagram that for making the current reach the high surge point, a time period Tx is cost. During Tx, the load is repeatedly activated. After the load is warmed up, the amount of the activation current is time by time accumulated until the activation current is able to activate the load. Furthermore, when the activation current is close to the high surge point, sometimes the load will misjudge and shut down due to overload.
It is therefore a primary object of the present invention to provide a pulse type activating system for power supply, in which a CPU collectively controls respective circuits.
It is a further object of the present invention to provide the above pulse type activating system for power supply, which is able to quickly activate a load.
It is still a further object of the present invention to provide the above pulse type activating system for power supply, which is able to protect the circuit of the load.
According to the above objects, the pulse type activating system for power supply of the present invention is composed of a boosting circuit, a pulse width modulating (PWM) circuit, a sine-wave generating circuit, an MOSFET output circuit, an analog-to-digital converting circuit (ADC), a temperature sensing circuit, an overload detecting circuit, a short circuit detecting circuit, a warning circuit and a CPU. The boosting circuit is connected with the pulse width modulating (PWM) circuit. The output end of the boosting circuit is connected with the MOSFET output circuit. The sine-wave generating circuit is connected with the MOSFET output circuit. The MOSFET output circuit is connected with both the overload detecting circuit and the short circuit detecting circuit. The CPU is connected with the pulse width modulating (PWM) circuit, the sine-wave generating circuit, the temperature sensing circuit, the overload detecting circuit, the short circuit detecting circuit, the analog-to-digital converting circuit (ADC) and the warning circuit. The CPU collectively controls the above circuits and in the instant of activation of the load, the CPU provides intermittent high voltage for shortening the activation time of the load. The CPU also provides protection effect for the load.


A knee bolster for protecting the passengers of a motor vehicle comprises one or more deformable members positioned generally forward of each vehicle passenger; ultrasonic sensors for determining the position of the knees and tibiae of each passenger within the motor vehicle relative to the deformable members; and means responsive to the sensing means for articulating and translating each deformable member relative to the vehicle interior and, hence, relative to the knees and tibiae of each passenger corresponding thereto to provide optimum protection to the passengers in the event of a subsequent collision or marked vehicle deceleration.

The instant invention relates generally to a motor vehicle's interior structure and the use thereof to mitigate injury to vehicle passengers upon collision or marked deceleration of the vehicle.
Known knee bolsters comprise deformable elements which are fixedly located about the passenger compartment of a vehicle so as to be positioned opposite the knee and tibia of each vehicle passenger when the passenger is normally seated in the vehicle. See, e.g., U.S. Pat. No. 3,947,056 issued March 30, 1976 to Schwanz. Upon a collision or marked deceleration of the vehicle, such knee bolsters collapse in a controlled manner to absorb a portion of the kinetic energy of the vehicle passenger to slow same, thereby reducing the severity of passenger injuries sustained during the event.
Significantly, the position and angle of such fixed knee bolsters in relation to the knees and tibiae of each passenger at the time of collision or marked vehicle deceleration have a major effect of the stresses applied to the limbs of the passenger and, hence, the potential for injury. Since such fixed knee bolsters are optimized for passengers of average size, the protection afforded by such knee bolsters becomes increasingly unavailing to passengers whose size deviates from the norm. For example, a 5th percentile female will typically slide under the knee bolster, while a 95th percentile male is likely to suffer substantial injury from knee contact with irregularly shaped dashboard contours and/or vehicular controls situated above the knee bolster. Moreover, such fixed knee bolsters fail to accommodate even an average-sized passenger (1) when the passenger places his feet so as to cause the angle formed between the surface of the knee bolster and either of his tibiae to deviate from the ideal angle to be formed therebetween; (2) when the passenger shifts either of his legs to cause the spacing between the surface of the knee bolster and his tibiae to deviate from the ideal spacing therebetween; or (3) when the passenger shifts his legs so as to raise either of his knees above the knee bolster.
The prior art further teaches the use of knee bolsters in conjunction with an active passenger restraint, such as an air bag, to further restrict the passenger's movement relative to such other restraint, such as to prevent the "submarining" of the passenger beneath the air bag during a crash condition. In this manner, the effectiveness of the active restraint in preventing the serious injury to vehicle passengers is significantly increased. Such auxiliary knee bolsters typically comprise a secondary air bag deployable to engage the knees of the vehicle occupant prior to, or simultaneous with, deployment of the primary (torso) bag. See, e.g., U.S. Pat. No. 3,768,830 issued Oct. 30, 1973 to Hass, teaching a secondary air bag deployed to engage the knees of the vehicle occupant prior to deployment of the primary air bag; and U.S. Pat. No. 3,767,225 issued Oct. 23, 1973 to Mazelsky, teaching a knee bolster comprising a bag-within-a-bag positioned opposite the knees of the vehicle occupants and inflated simultaneously therewith. Alternatively, U.S. Pat. No. 4,198,075 issued April 15, 1980 to Kob et al. teaches a deformable knee impact plate which is pivotally deployed into a position near the knees of the passenger as by an air bag or belt tensioner upon the detection of a crash condition by suitable sensor means. Unfortunately, as with the fixed knee bolsters discussed hereinabove, such auxiliary knee bolsters are optimized for passengers of average size and present similarly increased likelihood of passenger injury when the passengers legs are shifted from their ideal position relative to the knee bolster prior to the deployment thereof upon the detection of a crash condition.
What is needed is a self-adjusting knee bolster whose position within the vehicle relative to the knees and tibiae of a passenger therein continuously adjusts to provide the passenger optimum protection against injury in the event of a subsequent collision or marked vehicle deceleration.