The present invention relates to new polynucleotides derived from the nucleotide sequence of the IFNα-7 gene comprising new SNPs, and new polypeptides derived from the wild-type IFNα-7 protein comprising at least one mutation caused by at least one SNP of the invention as well as their therapeutic uses.

1. Field of the Invention
The present invention relates to new polynucleotides derived from the nucleotide sequence of the IFNα-7 gene comprising new SNPs, and new polypeptides derived from the natural wild-type IFNα-7 protein comprising mutations caused by these SNPs, as well as their therapeutic uses.
2. Related Art
The interferon alpha 7 gene, hereinafter referred to as IFNα-7, is described in the following publications:                Olopade, O. I.; Bohlander, S. K.; Pomykala, H.; Maltepe, E.; Van Melle, E.; Le Beau, M. M.; Diaz, M. O.: "Mapping of the shortest region of overlap of deletions of the short arm of chromosome 9 associated with human neoplasia."; Genomics 14: 437-443, 1992.        Henco K, Brosius J, Fujisawa A, Fujisawa J I, Haynes J R, Hochstadt J, Kovacic T, Pasek M, Schambock A, Schmid J, et al.: "Structural relationship of human interferon alpha genes and pseudogenes."; J Mol Biol 1985 Sep. 20; 185(2): 227-60.        Ullrich A, Gray A, Goeddel D V, Dull T J: "Nucleotide sequence of a portion of human chromosome 9 containing a leukocyte interferon gene cluster."; J Mol. Biol. 1982 Apr. 15; 156(3): 467-86.
The nucleotide sequence of this gene is accessible under accession number X02960 in the GenBank database.
The IFNα are known for their cellular antiproliferative effects and their involvements in antiviral and antiparasitic responses.
The IFNα are also known to inhibit the expression of several other cytokines at the level of the hematopoietic stem cells, as well as to inhibit the cellular proliferation of certain tumors.
The IFNα are also known to reduce the expression of the receptors to the EGF in renal carcinomas, to inhibit the expression of certain mitochondrial genes, to inhibit the proliferation of fibroblasts, monocytes and B lymphocytes, especially in vitro, and to block the synthesis of antibodies by B lymphocytes.
The IFNα are also known to induce the expression of tumor specific antigens on the surface of tumor cells and also to induce the genes placed under the control of promoter regions of the ISRE type (Interferon-Stimulated Response Element) by acting on the specific transcription factors of these ISRE.
It is known that the IFNα are involved in different disorders and/or human diseases, such as the different cancers like for example, carcinomas, melanomas, lymphomas, leukemias and cancers of the liver, neck, head and kidneys, cardiovascular diseases, metabolic diseases such as those that are not connected with the immune system like, for example, obesity, infectious diseases such as hepatitis B and C and AIDS, pneumonias, ulcerative colitis, diseases of the central nervous system like, for example, Alzheimer's disease, schizophrenia and depression, the rejection of tissue or organ grafts, healing of wounds, anemia in dialyzed patients, allergies, asthma, multiple sclerosis, osteoporosis, psoriasis, rheumatoid arthritis, Crohn's disease, autoimmune diseases and disorders, gastrointestinal disorders or even disorders connected with chemotherapy treatments.
The IFNα are particularly used for the treatment of certain leukemias, metastasizing renal carcinomas as well as tumors that appear following an immunodeficiency, such as Kaposi's sarcoma in the case of AIDS. The IFNα are also effective against other types of tumors and against certain viral infections. The IFNα are also recognized by the FDA (Food and Drug Administration) for the treatment of genital warts or venereal diseases.
However, the IFNα, and in particular INFα-7, have numerous side effects when they are used in pharmaceutical compositions, such as reactions of acute hypersensitivity (urticaria, bronchoconstriction, anaphylactic shock etc.), cardiac arrythmias, low blood pressure, epileptic seizures, problems with thyroid functions, flu-like syndromes (fevers, sweats, myalgias), etc.
Furthermore, the patients treated with IFNα can develop antibodies neutralizing these molecules, thus decreasing their effectiveness.
The inventors have found new polypeptide and new polynucleotide analogs to the IFNα-7 gene capable of having a different functionality from the natural wild-type IFNα-7 protein.
These new polypeptides and polynucleotides can notably be used to treat or prevent the disorders or diseases previously mentioned and avoid all or part of the disadvantages, which are tied to them.


A retrofocus type lens having a plurality of lenses divided into three lens units, or, in the order from a screen, a first lens unit, a second lens unit and a third lens unit, wherein letting the focal length of the entire lens system be denoted by fT, and the distance from a lens surface on the side of an original image to the original image by SK, EQU SK>0.7 fT. is satisfied, and the second lens unit and the first lens unit or the third lens unit each is provided with at least one aspherical lens of which at least one of the lens surfaces is aspherical.

1. Field of the Invention
This invention relates to retrofocus type lenses and, more particularly, to a retrofocus type lens suited to a projection lens for a color liquid-crystal projection television system, in which, for example, a plurality of images having different pieces of color information are combined by using composition mirrors and then projected onto a screen in an enlarged scale.
2. Description of the Related Art
Various color liquid-crystal projection television systems of such a kind that images displayed on a plurality of color liquid-crystal display elements (liquid-crystal light bulbs) are optically superimposed and projected by a projection lens onto the screen, have been proposed.
FIG. 7 is a schematic view of the main parts of a general type of the color liquid-crystal projection television system in which the images formed in the color liquid-crystal display elements are projected onto the screen (not shown).
In FIG. 7, a white color light source 1 issues a bundle of collimated light rays. Liquid-crystal display elements 2a, 2b and 2c for red, green and blue respectively present images to be projected. Reference numerals 3a and 3b denote reflection mirrors. A red-reflection dichroic mirror 4 illuminates the liquid-crystal display element 2a for red. A green-reflection dichroic mirror 5 illuminates the liquid-crystal display element 2b for green.
The liquid-crystal display element 2c for blue is illuminated by the blue light which has passed through the red-reflection dichroic mirror 4 and the green-reflection dichroic mirror 5. Reference numeral 6 denotes a blue-reflection dichroic mirror. Reference numeral 7 denotes a projection lens.
In FIG. 7, white light issued from the light source 1 is separated into red light, green light and blue light by the dichroic mirrors 4 and 5. With the red light, green light and blue light, the liquid-crystal display elements 2a, 2b and 2c for red, green and blue are illuminated, respectively. Images formed on the liquid-crystal display elements 2a, 2b and 2c with these color rays of light are projected by the projection lens 7 in a superimposed relation on the screen (not shown) to obtain a color picture.
For the projection lens 7 employed in the above arrangement, a retrofocus type lens having a long back focal distance is frequently used in view of the necessity of disposing various kinds of optical members such as reflection mirrors and dichroic mirrors in a space between the last lens surface and the liquid-crystal display elements (corresponding to the back focal distance).
In general, the retrofocus type lens is constructed in the form comprising a lens unit of negative refractive power on the object side (the side of a conjugate point of long distance) and a lens unit of positive refractive power on the image side (the side of a conjugate point of short distance). For this reason, there is an advantage that a relatively long back focal distance is easily obtainable.
Since the lens configuration is asymmetric, however, there is a tendency to produce many asymmetric aberrations such as distortion and astigmatism.
Further, in a case where the retrofocus type lens is employed in the color liquid-crystal projection television system, because the dichroic mirrors used for color separation are disposed on the image side, in order that the color unevenness is removed to effect good reproduction of colors over the entire area of the picture frame, there is need to make an almost equal angle of incidence of the light beam on the dichroic mirror over the entire area of the picture frame. Thus, the lens system must be made almost like the so-called emergence telecentric system in which a principal light ray emerging from the image side is almost parallel to the optical axis.
However, the use of the emergence telecentric system results in the off-axial light beam entering the lens unit of positive refractive power on the image side at a high position above the optical axis. For this reason, a problem arises in that large barrel-type (negative) distortion and flare are produced so that it is very difficult to obtain a good projected image.
In Japanese Laid-Open Patent Application No. Hei 3-145613, there has been proposed a retrofocus type lens having a lens form similar to the emergence telecentric system suited to a projection lens used for the color liquid-crystal projection television system in which the above-described distortion and flare and other various aberrations are corrected by setting forth proper rules of lens design.


The invention generally refers to a cell-targeting nanoparticle, wherein the cell-targeting nanoparticle is directly conjugated to at least one cysteine-containing peptide, wherein the cysteine-containing peptide is selected from the group consisting of glutathione (GSM, a GSH-containing peptide, and a peptide comprising a nuclear localization signal (NLS) sequence and a transporter sequence, and methods of using the cell-targeting nanoparticle.

Optical imaging of biological and/or chemical conditions of cells and tissues of a living subject is an area of significant importance. One of the biggest challenges in cell biology is the imaging of living cells. Conventional optical labels such as fluorescent dyes or markers are typically introduced into tissue samples to signal changing biological and/or chemical conditions of tissues. However, these conventional labels have many drawbacks. Conventional labels are generally toxic to living cells and tissues comprised of living cells. Furthermore, conventional labels such as fluorescent dyes or green fluorescent proteins (GFP) generally suffer from short-lived fluorescence because the dyes undergo photo bleaching after minutes of exposure to an excitation light source. Therefore, they are unsuitable for optical imaging that requires extended time period of monitoring. Furthermore, these labels are sensitive to environmental changes such as pH and oxygen concentration. Finally, recombinant GFP fusion proteins are cumbersome to construct, and long-term imaging (more than 3 days for example) with GFP requires the time-consuming process of establishing stable-expressing clones.
Other types of labels such as polymeric, magnetic and metallic particles have been introduced into cells. An alternative technology is the use of inorganic semiconductor nanocrystals, or quantum dots. Quantum dots, such as CdSe/ZnS core/shell nanoparticles, are inorganic fluorophores and generally have a size below 10 nm in diameter. Compared to conventional dyes, they have a much higher photobleaching threshold and negligible photobleaching under biological imaging conditions. Quantum dots can be silanized and, in that form, have reduced phototoxicity and are highly resistant to chemical and metabolic degradation.
Typically, there are three steps before quantum dots (QDs) can be employed for biological applications: 1) synthesis; 2) coating; and 3) bio-conjugation. The as synthesized QDs are generally coated with trioctylphosphine oxide (TOPO), hexadecylamine (HDA) or octadecylamine (ODA) and therefore hydrophobic in nature, and are soluble only in organic solvents.
For the design of water-soluble QDs, different coating methods are available and are accomplished either by exchange of TOPO or through hydrophobic addition reactions. TOPO ligands are often exchanged with thiol-functionalized compounds such as mercaptoacetic acid, dihydrolipoic acid, dithiothreitol, and cysteine containing peptides. The QDs have also been coated with inorganic silica or organic protective polymer layer. The coated particles are then bio-conjugated to peptides, proteins or antibodies for cellular tracking applications.
Silica and polymer coatings significantly increased the overall size to about 20 nm and restricted their use in certain imaging applications as the size of QDs determines the renal clearance of the QDs. QDs of size less 5.5 nm resulted in rapid and efficient urinary excretion and elimination from the animal body.
Additionally, during coating and bio-conjugation, the QDs tend to lose their fluorescence (up to 30-40% from the original quantum yield). The labeling of stem cells is an important area in the context of human regenerative medicine for example. However, in most of the cases, the labeling of stem cells with QDs is non-specific. Even though in vitro and in vivo imaging with QDs has been demonstrated, there remains a need to address the problems that exists in the art especially in relation to cell imaging labels associated with the use of particles such as quantum dots and nanoparticles.

Cell-targeting nanoparticles and uses thereof

Agency for Science, Technology and Research


The image forming system includes an image forming apparatus, and an option device including a setting unit that includes a setting port where a value is set in a state of being connected to the image forming apparatus, and an input/output port. The setting unit transmits a response signal to the image forming apparatus according to a comparison result between a value of first data received from the image forming apparatus and the value of a signal set in the setting port. The image forming apparatus transmits recognition data on the option device to the option device according to the response signal. The setting unit sets a value of a signal at the input/output port based on the recognition data.

1. Field of the Invention
The present invention relates to an image forming system and an option device. This system includes an image forming apparatus for forming an image through an electrophotography process, performed in such as a copier, and the option device connected to the apparatus.
2. Description of the Related Art
Conventionally, an image forming apparatus, such as a copier or a laser printer, includes a multi-stage mechanism equipped with multiple sheet feeding option devices in a multi-stage configuration. This multi-stage mechanism includes a CPU mounted on a main body of the image forming apparatus, CPUs mounted on respective option devices, and signal lines for communication between the CPUs (e.g., Japanese Patent Application Laid-Open No. 2006-326861). Specific configuration of a multi-stage mechanism of conventional sheet feeding option devices is hereinafter described with reference to the drawings. FIG. 6 is a schematic diagram illustrating the multi-stage configuration of the conventional sheet feeding option devices. In FIG. 6, the image forming apparatus 1 is mounted with a CPU 1a. Each sheet feeding option device 23 is mounted with a CPU 2. In FIG. 6, three stages of the sheet feeding option devices 23 are stacked. In this configuration, sheet feeding option devices 23-a, 23-b and 23-c are mounted with CPUs 2-a, 2-b and 2-c, respectively. Each of the CPUs (CPUs 2-a, 2-b and 2-c) of the sheet feeding option devices 23 includes a RAM that is for storing after-mentioned unique address information but is not illustrated.
Here, it is assumed that the sheet feeding option device 23 that can be stacked in a multi-stage manner is used only in a single stage or in any number of stages. Accordingly, the following configuration is required. That is, the CPU 1a of the image forming apparatus 1 and the CPUs 2-a, 2-b and 2-c of the sheet feeding option devices 23 are connected to each other by bus lines for serial communication where the CPU 1a serves as a master. Through the bus lines, the CPU 1a and the CPU 2 of each sheet feeding option device 23 communicate with each other. Thus, CMD, STS and CLK lines connected to the CPU 1a of the image forming apparatus 1 are connected to the respective CPUs 2 (CPUs 2-a, 2-b and 2-c) of the sheet feeding option devices 23 in parallel. The CMD line connected to the CPU 2 of the sheet feeding option device 23 downstream of the bus line is provided with gate circuits G-a, G-b and G-c. The output terminal of the gate circuit is in a closed state so as not to transmit a signal to a downstream side until the CPU 1a of the image forming apparatus 1 recognizes the attachment state of the corresponding sheet feeding option device 23. Subsequently, communication between the CPU 2 of the sheet feeding option device 23 upstream of the bus line and the CPU 1a of the image forming apparatus 1 is established. A unique address is assigned to the corresponding CPU 2, and stored in the RAM, not illustrated. The CPU 2 then controls an output port P0 to open the output terminal of the gate circuit G. The CPU 1a can thus communicate with the CPU 2 of the sheet feeding option device 23 downstream of the bus line. Such a configuration allows the CPU 1a to correctly recognize the configuration of the sheet feeding option device 23 even in the case where the number of attached stages of the sheet feeding option devices 23 is not fixed.
However, according to the configuration illustrated in FIG. 6, if an unidentified number of sheet feeding option devices 23 are attached, the CPU 1a of the image forming apparatus 1 is required to correctly recognize the configuration of the sheet feeding option devices 23. For such recognition, unique addresses are required to be assigned to the respective sheet feeding option devices 23 for communication with the corresponding stages of these devices. Accordingly, the sheet feeding option device 23 is required to be mounted with the CPU 2 that includes the RAM for storing the unique address information from the CPU 1a. This requirement is a factor of increasing the cost.


A laser processing system includes a laser oscillator, a laser beam emitting tool connected to the laser oscillator and supported by a first robot, the laser beam emitting tool emitting a laser beam supplied by the laser oscillator, and a laser processing tool which is supported by a second robot and which receives the laser beam emitted by the laser beam emitting tool and emits the laser beam toward a predetermined processing position.

As this type of laser processing system, a system that includes a portal frame provided in a plant in a manner extending in a width direction of a steel plate, and two laser processing tools disposed with the portal frame, with a gap in the width direction of the steel plate, and that simultaneously performs laser processing at two positions using the two laser processing tools is known (for example, see PTL 1).
This laser processing system includes a single laser oscillator supported on the portal frame, a light duct fixed to an upper surface of the portal frame while extending in the width direction of the steel plate, and a guide means connecting a light emitting portion of the laser oscillator and a center portion, in a longitudinal direction, of the light duct, the guide means guiding a laser beam from the laser oscillator into the light duct and refracting the laser beam from the laser oscillator toward one end and the other end of the light duct in the longitudinal direction, and thus, a laser beam from the single laser oscillator is supplied to the two laser processing tools.


A shopping cart cushion for placement into the mini basket portion of a shopping cart is comprised of a body, left extension and right extension. A strap is attached to the left extension and passes through a loop on the right extension for securement of a child sitting within the device. An optional bar protector is either fixedly or removably attached to the body and is wrapped around the handle bar of the shopping cart. The device folds up and is easy to transport.

1. Field of the Invention
The present invention relates to a cushion and more specifically to a shopping cart cushion for use by a child within the rear mini-basket of a shopping cart.
2. Background of the Prior Art
Providing a seat cushion for use by a child within the rear mini-basket portion of a typical shopping cart is well-known. The prior art discloses many such seating devices. U.S. Pat. No. 4,204,695 to Salzman, U.S. Pat. No. 4,416,462 to Thompson, U.S. Pat. No. 4,568,125 to Sckolnik, U.S. Pat. No. 4,655,502 to Houllis, U.S. Pat. No. 4,666,207 to Quartano, U.S. Pat. No. 5,106,155 to Luehring, U.S. Pat. No. 5,238,293 to Gibson, U.S. Pat. No. 5,354,121 to Allum, U.S. Pat. No. 5,547,250 to Childers, U.S. Pat. No. Des 308,614 to Gordon, and U.S. Pat. No. Des 367,197 to Fuchs are exemplary of shopping cart seats for use by children. These prior art devices, while providing varying levels of comfort and effectiveness in their intended purpose, suffer from at least one of several drawbacks.
These drawbacks include seats that lack a high degree of comfort to the child. By providing little or no cushioning to parts of the child's body that make contact with the cart, these seating devices are undesirable. Many devices have limited use in that they will properly fit into a limited number of shopping cart types. Other devices are bulky and thus impractical to transport by the average user. Still other devices are unduly complex making them cost-prohibitive to manufacture.
Therefore, there is a need in the art for a shopping cart cushion that overcomes the problems associated with prior art devices. Such a cushion must be relatively soft and resilient providing cushioning to all parts of the child that contact the cart. Such a cushion must be useable with a broad range of shopping cart types. Finally, such a cushion must be relatively simple in design and construction and should be relatively compact and easy to transport.


A laser-based method of removing a target link structure of a circuit fabricated on a substrate includes generating a pulsed laser output at a pre-determined wavelength less than an absorption edge of the substrate. The laser output includes at least one pulse having a pulse duration in the range of about 10 picoseconds to less than 1 nanosecond, the pulse duration being within a thermal laser processing range. The method also includes delivering and focusing the laser output onto the target link structure. The focused laser output has sufficient power density at a location within the target structure to reduce the reflectivity of the target structure and efficiently couple the focused laser output into the target structure to remove the link without damaging the substrate.

1. Field of the Invention
The present invention relates to the field of laser processing methods and systems, and specifically, to laser processing methods and systems for processing conductive link structures formed on substrates. This invention is particularly applicable, but not limited to, laser repair of redundant semiconductor memory devices.
2. Background Art
Economics and device performance have driven the size for the DRAMs and logic devices to very small physical dimensions. Not only are the devices small, but the interconnects and links thickness have also decreased dramatically in recent years.
Some thermal laser processing of links, for example, as described in "Link Cutting/Making" in HANDBOOK OF LASER MATERIALS PROCESSING, Chapter 19, pp. 595-615, Laser Institute of America (2001), relies on the differential thermal expansion between the oxide above the link and the link itself. The differential expansion results in a high pressure build-up of the molten link contained by the oxide. The oxide over the link is necessary to contain the link in a molten state long enough to build-up sufficient pressure to crack the oxide and explosively expel the link material. If the pressure is too low, the link will not be removed cleanly. Alternative laser wavelengths and laser control strive to increase the laser "energy window" without damaging the substrate and material contiguous to the link.
Further information is available regarding link blowing methods and systems, including material processing, system design, and device design considerations, in the following representative U.S. patents and published U.S. applications: U.S. Pat. Nos. 4,399,345; 4,532,402; 4,826,785; 4,935,801; 5,059,764; 5,208,437; 5,265,114; 5,473,624; 6,057,180; 6,172,325; 6,191,486; 6,239,406; 2002-0003130; and 2002-0005396.
Other representative publications providing background on link processing of memory circuits or similar laser processing applications include: "Laser Adjustment of Linear Monolithic Circuits," Litwin and Smart, ICAELO, (1983); "Computer Simulation of Target Link Explosion In Laser Programmable Memory," Scarfone, Chlipala (1986); "Precision Laser Micromachining," Boogard, SPIE Vol. 611 (1986); "Laser Processing for Application Specific Integrated Circuits (asics)," SPIE Vol. 774, Smart (1987); "Xenon Laser Repairs Liquid Crystal Displays," Waters, Laser and Optronics, (1988); "Laser Beam Processing and Wafer Scale Integration," Cohen (1988); "Optimization of Memory Redundancy Link Processing," Sun, Harris, Swenson, Hutchens, Vol. SPIE 2636, (1995); "Analysis of Laser Metal Cut Energy Process Window," Bernstein, Lee, Yang, Dahmas, IEEE Trans. On Semicond. Manufact., Vol 13, No. 2. (2000); "Link Cutting/Making" in HANDBOOK OF LASER MATERIALS PROCESSING, Chapter 19, pp. 595-615, Laser Institute of America (2001).
Requirements for the next generation of dynamic random access memory (DRAM) include fine pitch links having link widths less than 0.5 microns and link pitch (center to center spacing) less than 2 microns (e.g., 1.33 microns). Current commercial laser memory link repair systems, which use Q-switched, Nd based solid-state lasers with wavelengths of about 1 to 1.3 microns and pulse widths about 4 to 50 nanoseconds (ns), are not well suited for meeting such requirements. The large (wavelength limited) spot size and thermal effect (pulse width limited) are two limiting factors.
In INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY (2001) 18:323-331, results of copper laser processing are disclosed. A frequency tripled Nd:YAG laser with 50 nanosecond (ns) pulse duration was used. The measured heat affected zones (HAZ) were about 1 micron for 6×108 W/cm2 irradiance and more than 3 microns for about 2.5×109 W/cm2 irradiance.
Attempts have been made to address the problems. Reference is made to the following U.S. patents and published applications: U.S. Pat. Nos. 5,208,437; 5,656,186; 5,998,759; 6,057,180, 6,300,590; 6,574,250; WO 03/052890; and European patent EP 0902474. In summary, the conventional q-switched, nanosecond solid state lasers, even at short wavelengths, are not able to process the fine pitch links due to its thermal process nature. Material interaction may be a substantially non-thermal process at femtosecond pulse widths, but the complexity, high costs, and reliability of femtosecond pulse lasers may limit practical implementations. Device and material modifications to support laser repair are expensive and alone may not be sufficient. An improved method and system for fine pitch link processing is needed to circumvent problems associated with thermal effects yet provide for efficient link removal at high repetition rates without the complexity associated with femtosecond laser systems.

Laser-based system for memory link processing with picosecond lasers


A strain detector includes a bridge circuit having at least two strain resistance elements, a substrate, a first fixed member, and a second fixed member. The substrate has a circuit portion electrically connected to the strain resistance elements. The strain resistance elements are arranged on the substrate. The first fixed member is fixed to a center of an area, where an outer periphery of the area is set at a position at which the strain resistance elements are arranged. The second fixed member is fixed outside the position, where the strain resistance elements are arranged at the substrate. A center of an axis of the first fixed member, a center of an axis of the second fixed member, and the center of the area are positioned on a straight line, and the first fixed member and the second fixed member are arranged on two mutually opposed surfaces of the substrate.

A conventional strain detector is disclosed in, for example, Japanese Patent Unexamined Publication No. H8-87375. FIG. 12 is a bottom view showing a conventional strain detector, FIG. 13 is a perspective view showing the strain detector, and FIG. 14 is a cross sectional view showing a state, in which the strain detector is mounted.
Insulating substrate (hereinafter referred to as substrate) 1 includes an elastic member and an insulating layer formed on the surface thereof. Insulating substrate 1 is fixed to a lower surface of push member 2. Four strain resistance elements (hereinafter referred to as elements) 3 are provided on a lower surface of insulating substrate 1. Four strain resistance elements 3 are electrically connected to a pair of source electrodes 4, a pair of output electrodes 5, and a pair of earthed electrodes 6. Thereby, a bridge circuit is constituted.
An operation of the conventional strain detector constructed as described above is discussed hereinafter. As shown in FIG. 14, the strain detector is fixed to fixed member 7 by screws 8 in use. When a push force is applied to an upper surface substantially centrally of insulating substrate 1 through push member 2, the push force generates a bending moment on insulating substrate 1. The bending moment generates a bending moment also on four elements 3 provided on the lower surface of insulating substrate 1. When the bending moment is generated on elements 3, elements 3 are varied in value of resistance. Such variation in value of resistance is output from pair of output electrodes 5 to an external computer (not shown), and a push force applied to substrate 1 is calculated.
In the conventional construction mentioned above, substrate 1 is clamped and fixed to fixed member 7 by screws 8. Therefore, a fixed position is displaced when a shock is applied, so that a fixed length constructed as a beam is varied and the strain detector is degraded in characteristics such as sensitivity and 0-point voltage.


A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.

One of the parameters which is tested to determine whether an IC chip is defective is I/O pin leakage current. A drawback in testing for leakage current has been the excessive test time that has been required. As illustrated by the prior art circuit of FIG. 1, test methods in common use apply a voltage through a large current sensing resistor to the pin under test, and measure any current which results therefrom by knowing the value of the resistance provided by the resistor, and determining the voltage across the resistor. Tests are conducted for both high voltage and low voltage leakage. Thus, when testing for high voltage leakage, a high voltage is applied to the pin under test, and all other I/O pins of the IC chip are forced to a low voltage. In contrast, when a low voltage leakage test is conducted, a low voltage is applied to the pin under test, and all other pins are forced to a high voltage level. The pin under test, therefore, is always at a voltage different from that of the other pins. As a result, a time equal to the settling time of the pin under test must occur before either an accurate measurement of the leakage current at the pin may be made, or a determination may be made as to whether the pin is operating within acceptable tolerances. Settling time is a function of desired accuracy, and the R-C time constant is determined by the resistance of the test sensor resistor, and the sum of the capacitance of the test fixture and the I/O pin under test. Thus, for a given R-C time constant, when the test voltage is applied, voltage across the test sensor resistor follows a known exponential curve with respect to time. Further, the voltage is asymptotic to a final value, and takes time to reach the final value and settle before accurate measurements may be made.
Referring to the prior art circuit of FIG. 1, a precision D/A voltage source 10 is shown, the output of which is electrically connected to the input of a unity gain buffer amplifier 11. The output of the amplifier 11 in turn is electrically connected to one terminal of a precision high resistance current sensing resistor 12, and to the positive input of an instrumentation amplifier 13 which is used to monitor the performance of an I/O pin of an IC chip such as, by way of example, a CMOS dynamic random access memory (DRAM). The other terminal of the resistor 12 is electrically connected to the pole input of a single pole, single throw switch, and to the negative input of the amplifier 13. The output of the amplifier 13 is electrically connected to the input of an AID converter 15, the output of which is electrically connected to the input of a processor 16 that is used to calculate the leakage current of the memory module pin under test. The output of the switch 14 is electrically connected to one terminal of a test fixture capacitance 21, and to an I/O pin 22 of the unit under test (UUT). The other terminal of capacitance 21 is electrically connected to ground. The I/O pin 22 is represented by an I/O pin capacitance 23 and a source of leakage current 24 which are electrically connected in parallel to ground.
In operation, all I/O pins of a memory module except the pin under test are forced to either a high or a low voltage. The pin under test is forced to a voltage at the opposite end of the voltage range from that of the other pins. For CMOS DRAMs, by way of example, a high voltage for test purposes would be of the order of 5.0 volts, and a low voltage would be of the order of 0.0 volts. Assuming that all pins of a memory module except a pin under test are at 5.0 volts, the voltage source 10 would apply 0.0 volts through sense resistor 12 to switch 14. Upon the switch 14 being closed, a voltage would be applied to the pin under test. A delay time thereupon would have to occur to allow the test fixture capacitance 21 and the I/O pin capacitance 23 to discharge, and to allow the voltage across the current sensing resistor 12 to settle. Thereafter, A/D converter 15 would digitize the voltage received from instrumentation amplifier 13. The processor 16 would normalize the digitized value received from the A/D converter 15 as necessary, and divide the digitized value by the known resistance of the current sensing resistor 12 to provide an accurate measurement of the leakage current in the pin under test. The processor 16 then would indicate to the user whether the pin under test was within acceptable operating tolerances.
The settling time for the voltage applied across current sensing resistor 12 to a pin under test is the primary cause of excessive test times in measuring DC leakage currents. With CMOS devices, the leakage current is very small. That is, of the order of 100 nanoamps. Current sensing resistors having high resistance, therefore, are required to achieve measurable resolutions. With current sensing resistors having a resistance of the order of one megaohm and higher, the charge and discharge times of the I/O pins are high. The number of processor sample cycles which are required before an accurate measurement can be made, therefore, is high. Each of these factors contribute to the time required to conduct leakage current tests.
Prior art systems include that disclosed in U.S. Pat. No. 5,696,773 issued to Miller, which describes an apparatus used for performing leakage current tests on digital logic circuits. A parametric signal source employs two precision 1 M.OMEGA. current-sensing resistors per pin under test one for positive leakage currents and one for negative leakage currents. Each of the resistors is electrically connected in series with a D/A converter. The parametric signal source applies positive and negative parametric signals through Schottky diodes in series to a pin under test. Leakage currents are determined by dividing a voltage value at the positive and negative D/A converter outputs by the value of respective positive and negative current sensing resistors. The leakage currents then are compared with threshold leakage currents to determine acceptability. This system sources a voltage through a current-sensing resistor to the pin under test, and is subject to a pre-measurement settling time imposed by an R-C time constant.
U.S. Pat. No. 3,976,940 to Chau describes a testing circuit for providing digital stimuli to and receiving digital responses from I/O pins of a device under test at speeds up to 10 MHz. A pair of comparators for comparing the digital responses with minimum thresholds, and a multiplexer selecting between comparator outputs, allow continuous operation of the comparator and accommodates certain digital testing at high speeds up to 10 MHz. However, leakage testing is not conducted at such speeds. The circuit requires a plurality of FET transistors in parallel to achieve a low electronic switch "ON" resistance, and uses electromechanical relays which require at least 5 milliseconds to settle. Further, ECL technology is used which exhibits high power consumption at any given speed.
U.S. Pat. No. 3,702,967 to McPhail discloses a unipolar electronic test system for semiconductor devices that is operable in either current or voltage sourcing modes to sense leakage current flowing through a measurement resistor. This system sources a voltage through a current-sensing resistor to the pin under test, and is subject to a pre-measurement settling time imposed by an R-C time constant.
U.S. Pat. No. 4,004,222 to Gebhard discloses a test system for semiconductor SRAM cells. The detection of failed memory cells caused by inoperative memory cell pull-up elements, however, may be masked when normal stray capacitance on the nodes of the memory cell cannot be charged or discharged in an acceptable amount of time while a pattern test is being conducted. Methods are proposed to increase memory cell leakage during test by increasing photocurrent through illumination, and by elevating device temperature by as much as 80.degree. C. to quicken stray capacitance discharge time and shorten overall test time. However, the Gebhard system is not useable with commercial grade ICs, which are packaged and not rated for elevated temperatures.
U.S. Pat. No. 4,542,340 to Chakravarti discloses a method of measuring leakage currents in FET (field-effect transistor) semiconductor memory arrays using test sites formed in the kerf or cut regions of a wafer to test for acceptable leakage currents before sawing the wafer into chips to be packaged. The test points used in the Chakravarti method and system are not available after chips are cut from the wafer or packaged.
U.S. Pat. No. 4,595,875 to Chan et. al. discloses a leakage current and pin short detector for bipolar PROMs based on the inclusion of fault detection circuitry incorporated into the memory device. By applying a selected positive voltage to a test node, and measuring the resulting current into the node, deviations from a characteristic current-voltage (I-V) curve are observed to detect faulty devices. The Chan test circuit tests for leakage currents in memory cells, and not for I/O pin leakage currents as with the present invention.
U.S. Pat. No. 4,685,086 to Tran discloses an SRAM cell leakage detection circuit that is built into the memory chip itself. The tests which are conducted are based upon the principle of sensing complementary logic levels from properly operating SRAM cells (by way of example "01" or "10"), and by using a simple 2-input gate with appropriate thresholds to sense the absence of complimentary logic levels in defective cells. The Tran circuit is used only for memory cell testing, and not for I/O pin testing as with the present invention. Further, the Tran is not available for testing after a chip is packaged.
U.S. Pat. No. 4,800,332 to Hutchins discloses a reconfigurable IC with a capability to test for memory cell leakage. A test voltage is connected to a particular node of a memory device, while the rest of the memory device remains at a normal operating voltage. The test voltage is modulated to determine the voltage at which stored charge begins to leak between memory cells. Tests occur during memory device manufacture, and once the tests are concluded, the memory device is reconfigured for normal operation. Hutchins conducts only memory cell tests, and does not perform I/O pin tests as with the present invention. Further, the Hutchins test system is not available after a chip is packaged.
U.S. Pat. Nos. 4,841,482 and 4,860,261 to Kreifels et. al. disclose a circuit and method for leakage verification for flash EPROM/EEPROM memory cells. The circuit switches from a logic zero voltage to a non-zero test voltage on the word select lines of a memory cell, thereby enabling a measurement of leakage current on the bit lines of all cells coupled to the bit lines. The Kreifels' system and method test memory cells only, and not contact points outside a memory cell as does the present invention.
U.S. Pat. No. 5,132,929 to Ochii discloses an enhancement to an SRAM which allows leakage current measurements to occur in a test mode when the common V.sub.SS terminal of a memory cell flip-flop is brought to the V.sub.DD potential. A current sensing resistor is switched between the bit lines and the V.sub.DD potential, and a voltage reflecting leakage current is measured from one terminal of the current sensing resistor. Again, memory cell rather than I/O pin testing occurs, and the Ochii test terminals are not available after a chip is packaged.
U.S. Pat. No. 5,351,214 to Rouy discloses a circuit for the detection of bit line leakage by employing an output comparator having one input switchable between normal operation and a leakage reference in test mode, and a second input receiving the output of a memory array. When the leakage current threshold is selected during test mode, all word lines are simultaneously deselected, thus allowing only leakage currents on memory bit lines. The Rouy circuit only tests memory cells, and not I/O pins as does the present invention.
U.S. Pat. No. 5,491,665 to Sachdev discloses electronic circuitry fitted to an array of memory cells, whereby in a test mode all cells are accessed in parallel so that an I.sub.DDQ test may discover whether there is a defect in any of the cells. The Sachdev circuit tests memory cells only, and not I/O pins.
U.S. Pat. No. 5,659,511 to Huang discloses a method for measuring the leakage current of a DRAM capacitive junction by defining a large test memory cell comprised of numerous memory cells, and calculating the leakage current density of the large test memory cell by dividing the contact area of the bottom plate of the capacitor of the memory test cell, into the difference in junction leakage current between the memory cell transistor on and off states. The leakage current density of the memory test cell is taken as representative of the individual memory cells.
In contrast to the above prior art, the present invention conducts I/O pin leakage measurements after the IC chips are packaged, and assembled into IC modules. Further, the process of leakage current testing is accelerated by precharging the capacitance of the I/O pin under test to a voltage near its settled voltage, thereby reducing overall test time. More particularly, the present invention: 1) may switch either a ground potential or a selected voltage in electrical series with a low value resistor to the pin under test for rapid discharge and precharge of pin capacitance, thus shortening overall measurement time; 2) requires only one D/A converter as a voltage source for a single precision current-sensing resistor; and 3) identifies acceptable leakage current comparisons, and provides actual leakage current measurements which are suitable for manufacturing process monitoring. In addition, the present invention obviates the need for measurement corrections due to variations in temperature coefficients of diodes in series with the pin under test, and employs electronic switches having switch times less than one microsecond. Still further, the present invention is fully bipolar with respect to the polarity of voltage sourced and the direction of current measured through adaptation of operational amplifier technology. In addition, the present invention exhibits an economy of electronic components for increased reliability.


A method is disclosed for alerting a mobile subscriber within a radio telecommunication system to wait for the connection of an incoming call which may have a delayed connection time due to network congestion or the implementation of flexible alerting features utilizing alert-and-answer-before-routing techniques. In flexible alerting extension phone service, each one of a plurality of mobile stations is assigned to a single pilot directory number (PDN), and a home location register (HLR) in an originating exchange maintains a list of parameters identifying each visited mobile switching center (V-MSC) in which mobile stations identified with the PDN are believed to be currently located. The HLR places a forward service indicator code in the routing request messages that it sends to the V-MSCs. After all mobile stations identified with the PDN are paged, voice channels are seized with those that responded. Alerting signals are sent to responding mobile stations, and the V-MSCs transmit a delayed connection message to the answering mobile stations. While the V-MSCs return routing numbers to the HLR, the message may be repeated periodically. If more than one routing number is returned to the HLR, the HLR selects a single mobile station to receive the call. The delayed connection announcement is stopped when a voice trunk is established between the originating MSC and the V-MSC serving the selected mobile station.

1. Technical Field of the Invention
This invention relates to radio telecommunication systems, and more particularly, to a method of providing an announcement to a called mobile subscriber indicating that the connection of an incoming call may be delayed.
2. Description of Related Art
In radio telecommunications networks, multiple exchanges may operate together, each exchange being defined as the service area of a mobile switching center (MSC). A mobile subscriber may roam from exchange to exchange, and at any given time, the exchange in which the subscriber is operating is referred to as the serving MSC. An incoming call for the mobile subscriber may originate in an originating MSC and be routed to the serving MSC for delivery to the mobile subscriber.
When an incoming call is received for a mobile subscriber in a radio telecommunication system, a system operator may selectively seize a radio voice channel to the mobile station and alert the mobile subscriber before a voice trunk is established between the originating and serving exchanges. Systems utilizing this alert-and-answer-before-routing feature may experience sigifficant delays between the time that the mobile subscriber is alerted, and the call is delivered. In addition, increased demands on the resources of the cellular system, as well as other commercial services, which use alert-and-answer-before-routing implementation, may lead to unexpected delays in call delivery. As a result, the called party may prematurely terminate the call by hanging up before call delivery is completed, thereby creating a loss of revenue to system operators.
Although there are no known prior art teaching of a solution to the aforementioned deficiency and shortcomings of alerting a called party before establishing a voice trunk U.S. Pat. No. 4,723,273 to Diesel et al (Diesel) discloses subject matter which bears some relation to the matters disclosed herein. Diesel discloses a call forwarding method that allows the called party to selectively forward alerted calls without first establishing a voice channel or requiring the called party to answer the call. This discretionary call forwarding feature utilizes an out-of-band signaling channel to receive and transmit calling party information. Review of Diesel reveals no teaching or suggestion of a system or method such as that disclosed herein for notifying a called party to wait for the delayed connection of an answered incoming call alert.
It would be a distinct advantage to have a method in a radio telecommunication system for notifying a called party to wait for the delayed reception of an incoming call after responding to a call alert, and thereby increase the percentage of completed incoming calls.

Method of providing a delayed connection announcement to a mobile subscriber within a radio telecommunication system


A snow blower is provided with cutting devices which are housed within, but project beyond, a housing provided for the blower's auger. As the cutting devices engage snow during the blower's advance, the cutting devices move in a direction which tends to urge the forward portion of the blower downwardly.

1. Field of the Invention
The present invention relates to a snow blower provided with an arrangement for cutting compacted snow so as to facilitate operation of the blower's operation.
2. Prior Art
A problem experienced in operating a snow blower is that which occurs when the blower is advanced in a path through snow which has a crusted surface or which has been compacted. The dense, hard snow impedes penetration of the blower into the snow. One must repetitively drive the blower into the snow mass until forward progress stops, back the blower and then move it forward.
The problem of dealing with compacted snow has previously been addressed. For example, in U.S. Pat. No. 5,398,431 an arrangement is disclosed wherein a pair of plates are positioned outwardly of the ends of a housing which encloses the snow blower's auger. When the auger is driven, the plates rotate so as to break up crusted snow and ice and assist in propelling the snow blower forward.
Another example of a snow blower provided with cutting elements for compacted snow is disclosed in U.S. Pat. No. 5,101,585. This patent discloses an arrangement similar to that described with respect to U.S. Pat. No. 5,398,431. However, the corrugated cutting plates employed in U.S. Pat. No. 5,101,585 are mounted within the housing which encloses the auger.


In a stator structure 1 of an outer rotor generator, a pressing portion 33 provided on a first portion 31 of a connecting terminal 30 is configured to protrude inward in the radial direction of an annular coupler 20 when the connecting terminal 30 is attached to the coupler 20. The coupler 20 is formed with a circular cylindrical guide protrusion 23, and an outlet of a stator winding 5 having wound on a salient pole 10b is configured to be guided by the guide protrusion 23, bent inward in the radial direction and reach the pressing portion 33. After fusing processing, the first portion 31 on which the pressing portion 33 is provided is bent at a right angle toward a side opposed to a side with which the stator winding 5 is connected, and then a distal end thereof is locked at a lock portion 26.

It has conventionally been known that a fusing (thermal caulking) technique by application of electric power and pressure is used as a method for connecting an end of an armature winding to a connecting terminal in order to connect the armature winding wound on a stator core of a magneto generator to an external wiring. Such a fused processed portion is desired not to be subjected to vibrations of an engine that drives the generator, etc.
Patent Literature 1 discloses a stator structure of an outer rotor magneto generator configured such that an end of a connecting terminal connected with an armature winding is bent along a flat surface portion of a stator core after fusing processing. According to this configuration, the end of the connecting terminal does not protrude to the flat surface portion side of the stator, whereupon the influence of vibrations can be reduced.
Further, Patent Literature 2 discloses an outer rotor magneto generator wherein an end of a winding that extends from a salient pole of a stator core is configured to be connected to a connecting terminal by once being drawn toward the back side of the stator core through a gap with an adjacent salient pole and then striding over one salient pole at the back side and once again being drawn toward the front side of the stator core. According to this configuration, slack at the winding end can be avoided, and the influence of vibrations can be reduced.

Stator structure of outer rotor multipolar generator


A flagpole assembly comprising a flagpole body having an aperture disposed in the side thereof, one or two internal fastening plates, disposed within the flagpole body, an external fastening plate and door assembly and a set of threaded fasteners securing the flagpole assembly together. A cleat or winch mount may be secured to the internal fastening plate, having a winch secured thereto for securement of a flag halyard inside the flagpole body.

It is often desirable to substantially eliminate exposed flag halyards, especially while a flag is flying from a flagpole. There are flagpole assemblies in which the halyard remains substantially concealed from view but allows the flag to be raised and lowered. The flagpole assembly includes a hollow pole mounted at its base to a support. A first end of a halyard is connected to a winch. The winch is typically mounted near the base of the pole. The halyard passes through the hollow pole and out an exit opening at the pole tip.
Paying out the halyard from the winch causes the flag to lower as the length of the halyard extending from the exit opening in the hollow pole increases. The halyard is retracted by winding the halyard onto the winch. If the halyard has a flag attached to it, the flag is raised by this operation. If not, substantially the entire halyard is housed within the hollow pole or on the halyard winch.
A primary advantage of this design is that it simplifies raising and lowering of a flag while keeping the halyard substantially concealed. Keeping the halyard substantially concealed reduces deterioration of the halyard by preventing its exposure to the elements. It also eliminates problems caused by tangled halyards and flags.

This patent is subject to a terminal disclaimer.


A method is described for measuring system latency and latency jitter on a near real-time basis regarding packets of information moving from sources to destination. The method for measuring system latency and latency jitter includes time-stamping packets of information as they pass through a plurality of locations between the source and destination of these packets, with the time-stamping being performed by real-time clocks set to a universal standard. The time-stamped packets are analyzed to determine latency and latency jitter. The measurements of system latency and latency jitter can be performed based upon packet types so as to obtain accurate information concerning different types of business bandwidths associated with an observed network.

In a networked environment, the length of time for packets to travel from a source to a destination can vary for many reasons, including delays due to routers, communication, media, and the like. Although attempts have been made to determine latency and latency jitter through use of remote monitoring devices (RMONSs) and the like, such efforts have generally been unsatisfactory. It is desirable to make such measures in an accurate and precise manner.

Real time mesh measurement system stream latency and jitter measurements


Provided is a production method for a thin birefringent film with a satisfactory alignment property, in which a refractive index is controlled three-dimensionally and optical properties are unlikely to decrease in the case where the birefringent film is placed under high temperature and high humidity. The production method for a birefringent film of the present invention includes: the step (1) of preparing a solution that exhibits a nematic liquid crystal phase, containing at least one kind of polycyclic compound containing a —SO3M group and/or a —COOM group (M represents a counter ion) and a solvent; the step (2) of preparing a base material at least one surface of which is subjected to a hydrophilization treatment; and the step (3) of applying the solution prepared in the step (1) to the surface of the base material prepared in the step (2), the surface being subjected to the hydrophilization treatment, followed by drying, in which a contact angle of water at 23° C. on the surface of the base material prepared in the step (2), the surface being subjected to the hydrophilization treatment is 45° or less.

A liquid crystal display (hereinafter, referred to as LCD) is a device which displays a character and an image using electro-optical properties of a liquid crystal molecule, and has been widely applied to a cellular phone, a notebook computer, a liquid crystal television, etc. However, since the LCD utilizes a liquid crystal molecule with optical anisotropy, there are such problems that excellent display properties are demonstrated in a certain one direction but, in another direction, a screen becomes dark or indistinct. In order to solve the above-mentioned problems, a birefringent film has been widely employed for the LCD,
As one kind of the birefringent film, a birefringent film in which a refractive index ellipsoid satisfies the relationship represented by nx>nz>ny is disclosed (see e.g., Patent Document 1). The birefringent film having such a relationship of refractive index has conventionally been produced by attaching a shrinkable film to both sides of a polymer film, and stretching the resultant in such a manner as to expand in the thickness direction. Therefore, a conventional birefringent film having the relationship of a refractive index is likely to increase in the thickness, which makes it difficult to reduce the thickness of the liquid crystal display.
Further, conventionally, the birefringent film having the above-mentioned relationship of a refractive index has the following problems: when the birefringent film is placed under high temperature and high humidity, the optical properties are likely to decrease, and light leakage is caused by the defects of an alignment property. Patent Document 1: JP 2006-072309 A

Production method for birefringent film, birefringent film, and laminate


An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.

1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology for storing information, and more particularly, to an integrated circuit that performs an operation similar to that of a fuse.
2. Description of the Related Art
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) has various circuits therein in order to perform various operations. As an example, a fuse circuit may be included as a circuit component. The fuse circuit performs an operation for storing desired information. To this end, the fuse circuit has a general fuse or an anti-fuse therein. The general fuse and the anti-fuse are elements have characteristics opposite to each other. The general fuse is fabricated in an initial short fuse state and is subsequently programmed (for example, to an open state) according to different use. However, the anti-fuse is fabricated in an open state and is subsequently programmed to a short fuse state according to different use. Here, the programming indicates a series of operations for storing desired information in the general fuse and the anti-fuse.
While the general fuse may be implemented in a relatively small area, its program is performed at a wafer state. On the other hand, while the anti-fuse can be programmed using a programming voltage in a package state, it occupies a relatively large area, is complicated, and uses precise control technology.

Integrated circuit for storing information


A lens structure for use with an ion beam implanter. The lens structure includes first and second electrodes spaced apart along a direction of ion movement. The lens structure extends across a width of the ion beam for deflecting ions entering the lens structure. The lens structure includes a first electrode for decelerating ions and a second electrode for accelerating the ions. A lens structure mode controller selectively activates either the accelerating or decelerating electrode to to cause ions entering the lens structure to exit said lens structure with a desired trajectory regardless of the trajectory ions enter the lens structure.

Axcelis Technologies, assignee of the present invention, sells products for treatment of silicon wafers during Integrated Circuit fabrication. One such product or tool creates an ion beam that modifies the physical properties of wafers that are placed into the ion beam. This process can be used, for example, to dope the silicon from which the untreated wafer is made to produce a semiconductor material. Controlled use of masking with resist materials prior to ion implantation as well as layering of different dopant patterns within the wafer produce an integrated circuit for use in one of a myriad of applications.
Prior art U.S. Pat. No. 5,177,366 to King et al and U.S. Pat. No. 5,091,655 to Dykstra et al. discuss methods of using two pair of electrostatic scanning electrodes to generate parallel ion beams. The '366 patent concerns an ion beam implantation system wherein an ion beam is controllably deflected from an initial trajectory as it passes through spaced parallel plates that are biased by a control circuit. Once deflected, the ion beam passes through electrodes positioned along a beam travel path that both re-deflect the once-deflected ion beam and accelerate the ions to a desired final energy. Ions within the beam exit the accelerator and impact a work-piece at a uniform, controlled impact angle due to ion focusing in a scanning plane and an orthogonal cross plane.
The '655 patent relates to an ion beam that is controllably deflected from an initial trajectory as it passes through spaced parallel plates that are biased by a control circuit. Once deflected, the ion beam enters an accelerator that both re-deflects the once deflected ion beam and accelerates the ions to a desired final energy. When the beam exits the accelerator it moves along a trajectory that impacts a work-piece. Ions making up the ion beam all impact the work-piece at a uniform, controlled impact angle.
A printed publication entitled "The Nissin NH-20SP medium-current ion implanter" to Nagai et al describes a medium current ion implanter. The implanter has a pair of so-called kickback electrodes H2 that compensate for side to side scanning introduced by an initial set of electrodes. The sweep-voltage waveform applied to the H1 and H2 electrodes is generated by a digital-waveform generator, or a waveform controller.


A vitreous bonded abrasive article such as a grinding wheel is provided comprising high density sol-gel alumina-based abrasive grains comprised of alpha alumina and a vitreous bond which binds together the abrasive grains. The grinding wheel of the invention exhibits enhanced G-ratio grinding performance over comparable wheels containing sol-gel alumina-based abrasive grain having a density less than 3.85 grams per cubic centimeter.

Vitreous bonded alumina abrasive grain grinding wheels have enjoyed large popularity and use for many years in grinding operations for a large variety of metal workpieces, particularly iron and steel workpieces. The principle alumina abrasive grain used in such grinding wheels has been and continues to be fused alumina abrasive grain. Such past and continued use of fused alumina grain has in large measure been based on economic considerations, even though less than desirable grinding performance was often achieved. Fused alumina grain is low cost. This less than desirable performance is often manifested not only in the reduced quality of the finished parts, but also in other considerations such as higher power consumption, heat generation, friction, reduced production rates, higher costs and low G-ratio.
The last factor (i.e., G-ratio) is the ratio of the volume of metal removed from the workpiece to the volume of wheel lost during the grinding operation. Thus it is the volume of metal removed per unit volume of wheel wear. A low G-ratio indicates a small amount of metal removed from the workpiece per unit volume of wear or loss of the grinding wheel and therefore indicates very little grinding is taking place and/or high wear of the grinding wheel. The high wear of the grinding wheel results in a short useful life of the wheel, increased wheel usage and increased wheel cost in the grinding operation. A high G-ratio shows a large amount of metal removed from the workpiece per unit volume of wheel wear or loss. Such high G-ratio indicates longer useful wheel life, lower wheel usage, greater cost effectiveness, higher production rates and more efficient grinding. Reduced power consumption, lower friction and reduced heat often accompany a high G-ratio grinding operation. As the G-ratio increases there often can be accompanying increases in wheel speed, infeed rates and workpiece rotation speed. These increases lead to higher production rates. Thus, higher G-ratio is desirable and sought after in the development and improvement of grinding wheels, especially in wheels employing costly abrasive grain (e.g., super abrasive grain). Increasing the G-ratio of grinding wheels containing more expensive grain makes such wheels more cost competitive with lower G-ratio wheels made with low cost abrasive grain and increases their cost effectiveness in precision, critical and difficult grinding operations (e.g., grinding tool steel and exotic alloys).
More recently an improved alumina abrasive grain was developed using a sol-gel and sintering process rather than the fusion process for producing alumina abrasive grains. Such newer abrasive grains proved to be more costly than the fused alumina grain. However, grinding wheels made with the sintered sol-gel alumina abrasive exhibited improved grinding performance over wheels made with fused alumina grain. This improved performance was obtained at a higher grinding wheel cost, particularly when such grain is used in vitreous bonded grinding wheels. Thus, sintered sol-gel alumina abrasive grain have not achieved the popularity and wide spread use found for fused alumina abrasive grains. Increasing the grinding performance, especially the G-ratio, of grinding wheels produced with sol-gel alumina abrasive grain , particularly vitreous bonded grinding wheels made with such abrasive grain, would make them highly competitive with wheels produced with fused alumina abrasive grain in a wide range of grinding applications.
The sintered sol-gel alumina abrasive grains can be produced by a process comprising the steps of preparing a dispersion of an alumina monohydrate to which a modifier may be added, gelling the dispersion, drying the gelled dispersion, crushing the dried gelled dispersion to form particles, calcining the particles, and firing the particles to form abrasive grains. Various adaptations and modification of this basic process have been developed and disclosed since the process was first discovered and disclosed to the art. The firing step is carried out to sinter the grains at temperatures below the fusion temperature of aluminum oxide. The sol-gel process of making alumina abrasive grains is more fully described in U.S. Pat. No. 4,314,827 to Leitheiser et al, which disclosure is incorporated herein by reference.
The first sol-gel alumina abrasive grains were disclosed in U.S. Pat. Nos. 4,314,827 and 4,518,397 to Leitheiser et al. These patents teach a non-fused abrasive grain comprising alpha alumina and at least one modifier selected from the group consisting of oxides of zirconium, hafnium, cobalt, nickel, zinc, and magnesium, and may include secondary modifiers such as samaria, titania and ceria.
In U.S. Pat. No. 4,623,364 to Cottringer et al disclosure is made of the addition of an alpha alumina seed material to the non-alpha alumina dispersion, in the sol-gel process, to enhance the transformation to alpha alumina during sintering.
Disclosure is made in U.S. Pat. No. 4,744,802 to Schwabel of a sol-gel process wherein iron oxide or an iron oxide precursor is added to the alumina dispersion for producing a durable alpha alumina abrasive grain.
A ceramic abrasive grain comprising alpha alumina and at least about 0.5% yttria modifier is disclosed in U.S. Pat. No. 4,770,671 to Monroe et al. The abrasive grain is especially efficient for abrading stainless steel and exotic alloys.
The impregnation of a metal oxide modifier into a porous sol-gel process alumina body is taught in European Patent Application, Number EP 293,163A, published November 1988, in a process comprising preparing a dispersion of alpha alumina monohydrate, gelling the dispersion, drying the gelled dispersion, crushing the dried dispersion to form particles, calcining the particles, impregnating the particles with a dispersion of a precursor of the metal oxide, drying the impregnated particles, calcining the dried particles and firing the dried particles to form abrasive grains. The modifier can be an oxide of magnesium, zirconium, hafnium, nickel, cobalt, zinc, titanium, yttrium, or a rare earth metal.
Sol-gel process ceramic abrasive grain comprising alpha alumina and at least 0.5% of a rare earth metal oxide is taught in U.S. Pat. No. 4,881,951 to Wood et al. The rare earth metal may be selected from praseodymium, samarium, ytterbium, neodymium, lanthanum, gadolinium, cerium, dysprosium, erbium and mixtures thereof. Impregnation of the rare earth modifier as in EP 293,163A into the unfired alumina particle is also taught.
The modification of sol-gel alumina abrasive grain with from 0.01 to 2% ceria is taught in U.S. Pat. No. 5,053,369.
There is disclosed in The Society of Manufacturing Engineers Paper EM 90-360, entitled "Use of Sintered Ceramic Aluminum Oxides in Vitrified Bonded Wheels", published Sep. 12, 1990, the grinding performance of vitrified bonded abrasive wheels employing ceramic alumina-based abrasive grains.
The use of sol-gel abrasive grain in bonded abrasive articles is known in the art. However, no recognition or significance is given or suggested in the art that the G-ratio of a vitreous bonded sol-gel alumina abrasive grain grinding wheel or other bonded abrasive article is particularly and significantly enhanced by the presence therein of sol-gel alumina abrasive grain having a high density, particularly a density of at least 3.85 grams per cubic centimeter (g/cc). It is known that a given abrasive grain can be produced with a range of densities by varying the pore content and composition of the grain. The greater the pore content the lower the density and conversely the lower the pore content the higher the density without composition variation. At zero pore content the maximum density is typically achieved. This maximum density can be the theoretical density of the grain. As used in this disclosure the phrases sol-gel alumina abrasive grain and sintered sol-gel alumina abrasive grain shall be used interchangeably and shall mean alpha-alumina-based abrasive grain produced by the sol-gel process.
Alumina-based abrasive grains produced by the sol-gel process are to be distinguished from alumina abrasive grains made by conventional sintering of particulate alpha-alumina and by fusion processes. The sol-gel process includes the preparation of an aqueous dispersion of alumina monohydrate to which modifiers may be added, gelling the dispersion, drying of the gel, crushing the dried gel to produce particles, calcining the dried particles and firing the calcined particles. These process steps are not included in the production of conventional sintered or fused alumina abrasive grain. Owing to the differences in the processes for producing sol-gel, sintered and fused alumina abrasive grains there are found differences in grain structure, grain properties and grain performance in grinding wheels and other abrasive articles, particularly vitreous bonded grinding wheels and other bonded abrasive articles (e.g., honing stones). While sol-gel abrasive grains have been recognized in the art to provide superior grinding performance over fused alumina abrasive grains in vitreous bonded grinding wheels, there has been no recognition that high density sol-gel alumina grains would produce an unexpectedly high performance improvement in vitreous bonded abrasive products.

High density sol-gel alumina-based abrasive vitreous bonded grinding wheel

Minnesota Mining and Manufacturing Company


An Fe—Ni-based alloy that has improved wear resistance at high temperature over Ni-based superalloys is provided. The alloy is particularly useful for manufacturing engine exhaust valves and other high temperature engine components subjected to corrosion, wear and oxidation.

High temperature strength, abrasion resistance and corrosion/oxidation resistance are required for materials of exhaust valves, which are generally subjected to temperatures exceeding 800° C. The exhaust valves used in most reciprocating engines can generally be divided into three sections; the head, stem and stem tip. The head and a portion of the head leading from the stem consist of a high temperature, high strength and corrosion resistant alloy such as an austenitic stainless steel or a superalloy. The sealing surface of the valve often includes a weld overlay material, such as a cobalt based, high temperature alloy. The remainder of the stem often is made of a hardenable martensitic steel welded to the high-temperature heat-resistant alloy of the valve head end.
As improved internal combustion engines are developed, addressing the increasing temperatures resulting from higher fuel economy, reduced emissions and yet higher output through newly designed engines has prompted the need for new cost effective materials. In addition, because the demand for and cost of nickel is on the rise, alternatives for high nickel content alloys are desired.
Austenitic stainless steels such as 21-2N, 21-4N-Nb-W and 23-8N have been used for the manufacture of engine valves for many decades. However, due to mechanical property limitations, these alloys are not suitable at operating temperatures above 1472° F. (800° C.) for current durability expectations.
Superalloys, including Fe—Ni-based and Ni-based alloys, have been used for exhaust valve applications typically when the less expensive iron-based stainless valve steel would not provide sufficient high-temperature strength or corrosion resistance, or both, for a given application. Some of the higher nickel alloys used for valve applications include Alloy 751, Alloy 80A, Pyromet 31 and Ni30, for example. Alloys 751, 80A and Pyromet 31 contain high amounts of Ni and are therefore expensive. Valves manufactured from these higher content Ni alloys are susceptible to abrasive and adhesive wear on the seat face due to the lack of wear resistance. Therefore, valves manufactured from some of the higher Ni alloys must be hard faced with a Co-based alloy on the seat face to improve wear resistance. This adds a manufacturing step that further increases the cost of the valve. Thus, there is a need for an intermediate strength valve alloy with properties and cost between that of the austenitic valve steels and the Ni-based superalloys such that the alloy has sufficient wear resistance without requiring a hard facing step.


An apparatus for covering goods, and goods stacked on a pallet with plastic wrap supplied in a roll comprises: a) a roll head adapted to rotatably carry the roll of plastic wrap, the roll head having a friction mechanism so that ease of rotation of the roll with respect to the head is controlled thereby facilitating stretching the wrap around the goods after an end portion of the wrap is initially secured adjacent to the goods; and, b) an elongate handle portion carrying the roll head and extending therefrom in a direction generally parallel to the axis of the roll of plastic wrap. A method of wrapping goods stacked on a pallet with plastic wrap supplied in a roll comprising the steps of: a) elevating the pallet and the goods stacked thereon so that there is sufficient clearance to readily pass the roll of plastic wrap beneath the pallet; b) providing a wrap apparatus as defined above; c) loading the roll head of the apparatus with a roll of plastic wrap; d) attaching an end portion of the plastic wrap to one of the pallet and the goods stacked thereon; and then, e) with the user standing adjacent to the elevated pallet having the goods stacked thereon, encircling the pallet and goods thereon with the roll head, by generally moving the handle in an outline of a cone, thereby encircling and securing the goods and pallet together with plastic wrap.

Shrink wrap, stretch film, or cellophane, of approximately one foot in width, is most commonly used to secure packaged product together, and to maintain that product carried on a pallet. Product stretch wrapped onto a pallet is better protected from being torn or otherwise damaged during transit. Product so wrapped on the pallet is so sufficiently attached to the pallet that straps are not required to maintain the product in position thereon. Products which are irregularly shaped or either substantially larger or smaller than the pallet can be quickly and securely attached to the pallet.
Particularly with products which are irregularly shaped or are substantially larger or smaller than the pallet it is advantageous to "belly wrap" these products to the pallet. Belly wrapping products better secures them to the pallet. Typically the pallet is lifted by a fork lift and wrap is positioned under the pallet and over and around the product on the pallet. Occupational Health and Safety Regulations prohibit individuals from positioning themselves even temporarily under temporarily raised items. It is difficult, if not impossible to belly wrap product on a pallet with currently available wrap dispensers without passing the applicator and one's body underneath the elevated pallet. There is a need for a wrap dispenser which facilitates quickly and safely belly wrapping a product on a pallet. There is also a need for a wrap dispenser which enables one to laterally wrap a product stacked on a pallet to the pallet without bending over.

Apparatus and method for dispensing stretch wrap


The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

FIG. 1 schematically illustrates an SRAM cell 110. The SRAM cell 110 comprises first and second drivers N1 and N2. Illustratively, the drivers N1 and N2 are pulldown NMOS devices N1 and N2. The source of N1 112 and the source of N2 114 are connected to a reference voltage Vss which, for example, is ground. The drain 116 of N2 is connected to the gate 118 of N11. The drain 120 of N1 is connected to the gate 122 of N2. The SRAM cell 110 of FIG. 1 also comprises two load devices L1 and L2. The load devices L1 and L2 each have one terminal 124, 126 connected to a supply voltage Vcc and another terminal 128, 130 connected to the drains 120, 116 of N1 and N2, respectively. The supply voltage Vcc is positive with respect to Vss.
The SRAM cell 110 also comprises two additional NMOS devices N3 and N4. The devices N3 and N4 are pass transistors. The gates 132, 134 of N3 and N4 are connected to a wordline whose signal value is designated WORD. The drains 136, 138 of N3 and N4 are connected to bit lines whose signal values are designated BIT and BIT, respectively. The sources 140, 142 of N3 and N4 are connected the drains 120, 116 of N1 and N2, respectively.
To write the cell, DATA (logic "1" or logic "0") is placed on the BIT line and DATA is placed on the BIT line. Then WORD is asserted. A read operation commences by precharging the BIT and BIT lines. The WORD line is asserted and either the BIT or BIT line will be discharged by one of the pull down transistors N1 or N2.
The purpose of the load devices L1 and L2 is to counteract the effect of charge leakage at the drains 120, 116 of N1 and N2. The load devices L1 and L2 may be polycrystalline silicon resistors.
A row 45 of SRAM cells 50 is shown in FIG. 2, where one of the SRAM cells 50 is shown in greater detail. The load devices of the SRAM cell 50 are polysilicon load resistors L.sub.1 and L.sub.2. Parasitic resistance Rvcc form the interconnect resistance between Vcc and the load devices L.sub.1 and L.sub.2 of the cells 50. As shown in FIG. 2, each cell 50 in the row 45 has associated with it an additional unit of parasitic resistance Rvcc. The Vcc interconnect parasitic resistance of each cell 50 is made up of one or more units of Rvcc as shown in FIG. 2. The actual voltage level of the "high" supply voltage received at the cell 50 will be much lower than Vcc if Rvcc is high or if the aggregate interconnect resistance from the Vcc pin to the cell 50 is high (i.e., if the total resistance of multiple internal parasitic resistance Rvcc from the Vcc pin to a specific cell 50 is high). Such a reduction in voltage level in the high supply voltage received at the cell 50 reduces the performance of the cell 50. Therefore, it is desirable for the Vcc interconnect resistance for each cell 50 to be as small as possible.
Lowering the value of the Vcc interconnect parasitic resistance Rvcc reduces the voltage drop between Vcc and the loads L.sub.1 and L.sub.2. This enhances circuit operation and reduces wasted power.
FIG. 3 shows a structure used to implement one leg of a conventional SRAM structure such as shown in FIG. 1. The structure 1 of FIG. 3 comprises a substrate 10 which is, for example, a P-type substrate. A driver device 12 is formed in the substrate 10. The driver device 12 is an NMOSFET and comprise N+ type drain region 14 and N+ type source region 16 which are separated by a channel 18. A thin gate oxide layer 20 is formed over the channel 18. A polysilicon gate 22 is formed over the gate oxide 20.
An inter-poly-dielectric layer (IPD) 30 is formed over the driver device 12. The (IPD) layer has a thickness of 1500 .ANG.-2000 .ANG.. A thick polysilicon layer 80 is formed on the IPD layer 30. A region 82 of the polysilicon layer 80 is heavily doped (N+ type) to form a low resistance Vcc interconnect. A region 84 of the layer 80 is heavily doped (N+ type) to form a low resistance interconnect to the drain region 14 of the driver device. This driver interconnect (also known as poly-2/poly-1 via) extends through a via opening 32 in the IPD layer 30. A region 86 of the polysilicon layer 80 is lightly doped (N-type) to form a poly-load resistance region. (There is also an additional via opening in the IPD layer 30 (not shown) for connecting the interconnect 84 to the gate of another driver.)
A problem with this structure is lateral diffusion from the heavily doped regions 82 and 84 into the lightly doped region 86.
Accordingly, it is an object of the invention to provide an SRAM cell with a poly-load resistor structure which overcomes the problems of the prior art.
Specifically, it is an object of the invention to provide an SRAM cell with a poly-load resistor structure in which lateral diffusion from highly doped interconnect regions into a lightly doped poly-load region is reduced. It is also an object of the invention to provide a method for fabricating such a poly-load resistor structure without increasing the number of photolithographic steps over the number of photolithographic steps used in the prior art.


The invention refers to a chuck pallet (1.3) with solid groove-sidewalls (2.3) for clamping chucks (1.1), whereby the x-y-references (2.5) of the chuck pallet (1.3) are allocated in the same plane (2.1) as the z-references (2.1) and the x-y-references (2.5) are also allocated at the solid groove-sidewalls (2.3). The solid groove-sidewalls (2.3) have thereby a tapered profile.

The present invention relates to a chuck pallet and a clamping system with such a chuck pallet.
Clamping systems with chuck pallets are commonly known in the field of workpiece machining with machine tools like milling, turning or electrical discharge machining (EDM). The clamping systems are used to hold the workpiece to be machined or the machining tools (particularly in the EDM applications). High cutting forces are sometimes exerted on the workpiece during its machining. These high forces are consequently also transmitted to the chuck systems holding the workpiece on the machining table. Clamping systems need therefore to be rigidly designed and constructed to withstand the applied forces and particularly to exactly maintain the positioning of the workpiece, avoiding therewith inaccurate machining of the workpiece.
Rigid versions of clamping systems are known. Such systems can for instance be designed to have six or more contact points between pallet and chuck, offering therewith a rigid clamping. Such known systems have on the other hand also some disadvantages. Clamping couplings with more than six contact points are overdetermined. Overdetermined couplings are favorable regarding the combination of high rigidity, high load capacity and accuracy. The problem is to design and manufacture them in a way that leads to contact with all the reference surfaces without any jam or play. This could be done with high manufacturing tolerances. However, this has until now not been sufficient for reaching the required position accuracy of the reference surfaces. The reason is that the designs have included tolerance chains leading to micro displacements of the reference surfaces. Such displacements affect both jam and micro play in high precision couplings.
The patent publication U.S. Pat. No. 3,741,573A describes an early EDM clamping coupling where the overdetermined principle was applied. However, in order to avoid jam a "close fitting" (see U.S. Pat. No. 3,741,573A col. 5, line 63) was used. This means there was a small play in the xy connection and such play is not accepted today or in applications for which the new invention here in matter is intended for.
The document EP 0 255 042 B1 discloses a clamping system known on the market as the "3R Macro system". This system uses elastic tongues. The principle with minimizing the tolerance chain was applied by having the xy contact edge where the z-plane meets the upper edge of the end surfaces of the tongues. The elastic tongues are very favorable regarding accuracy but give a lower load limit and rigidity compared to a solid coupling according to the new invention
EP1068919 B1 describes a clamping coupling where solid references are used. The xy contacts of the pallet are in a recessed position by a two-step design of the groove (see FIG. 3). This means that the tolerance of the height of these steps affect the contact edge position accuracy. This tolerance chain adds position error leading to a difficult and costly manufacturing or to a coupling with jam or play (this disadvantage is further discussed further down in relation to the document EP01529594 B1). The purpose with the two-step groove is to protect the contact edge when the pallet is placed on a table or in a magazine. However, in real use the pallet is often not carefully placed on the chuck but roughly. This is particularly the case at automatic loadings. The contact edges are then hitting the chuck lug references and could be damaged. This problem is not solved in EP1068919 B1 but will be by a preferred embodiment of the new invention.
The publication "Handbook of machine design" (see chapter 11 Bevel and Hypoid gears Krenzer, Hotchkiss, sec. 11.7.7) describes the basic rule of a bevel gear design. The contact pattern is expanding with the load but must never reach the boundaries of the tooth surface, i.e. never come across the edges of the tooth surface. This is emphasized in section 11.7.7 of the publication.
U.S. Pat. No. 3,880,267A describes an overdetermined coupling, where the basic rule of bevel gear design (see foregoing paragraph) is applied. In FIGS. 4 and 10 it is illustrated that the lug element 28 is curved in order to avoid edge contact on the lug element 26. FIG. 10 shows this in combination with having a z-surface contact against the top of lug 28. The combination with a curved against a straight surface leads to an expanded contact with increasing load and unfavorable tolerance displacements of the surfaces.
EP01529594 B1 describes an overdetermined coupling with surface expanding function in accordance to the already cited documents U.S. Pat. No. 3,880,267A and the publication "Handbook of machine design". In this patent document the length of the elastic steel material has been increased by having contact on only one side of the lugs and grooves. The disadvantages are that the one-side-contact reduces the translational rigidity in the xy-plane as well as the torsional rigidity. This is due to fewer available xy contacts. A further important disadvantage is that the axial distance between the z-plane and the xy contacts spots leads to an inaccuracy in spot location due to the tolerance chain created. This tolerance chain would have led to a jam or play in case of providing contacts at both sides in the grooves.
The document EP1266713 A2 describes an overdetermined clamping system, known on the market under the product name "Macro" from the company System 3R. The holder is made of sintered material. It utilizes the lower stiffness of sintered materials to allow an elastic deformation of the contact edges. That product was just manufactured during a short period, since it led to jam after a while. The friction became too high in repeated EDM usage.


A three-dimensional (3D) video codec encodes multiple views of a 3D video, each including texture and depth components. The encoders of the codec encode video blocks of their respective views based on a set of prediction parameters, such as quad-tree split flags, prediction modes, partition sizes, motion fields, inter directions, reference indices, luma intra modes, and chroma intra modes. The prediction parameters may be inherited across different views and different ones of the texture and depth components.

Three-dimensional (3D) video includes multiple views, each taken from a different camera perspective or angle. Each view includes a texture component (also referred to as a "texture view") and a depth map component. 3D video encoding includes encoding the multiple texture views and their associated depth maps, and then multiplexing the multiple encoded texture views and depth maps into a bit stream. Such 3D video encoding (or compression) employs different types of video prediction, such as inter and intra prediction, to eliminate redundancy in the texture and depth map components. Such prediction is performed using a set of prediction parameters to control the prediction. Current 3D coding standards and related techniques are inflexible and restrictive with regard to the conditions under which such prediction parameters may be inherited or passed between different contexts, such as different views and their corresponding texture/depth map components, to facilitate more efficient encoding and decoding processes.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.

Prediction parameter inheritance for 3D video coding


A dispenser for a roll of web material, such as a center feed roll includes: a body having a first end wall provided with a dispensing opening for dispensing a leading end of the web material at the center of the roll, a second end wall opposite to the first end wall, and a sidewall connecting to the first and second end wall. The dispenser also includes a stabilizing device that is insertable into the roll to prevent the roll from collapsing towards its center. The stabilizing device includes a plurality of protrusions protruding from at least one of the first or second end wall towards the other of the first or second end wall, and the protrusions are disposed closer to the sidewall than to a center axis of the body.

It is well known with respect to the aforesaid dispensers, that the roll of web material tends to collapse towards its center axis, particularly when a considerable proportion of the web material of the roll has already been dispensed from the center of the roll, whereby the dispensing process is interfered.
To counteract collapsing, WO 98/25848 A1 suggests to statically compress the roll between the opposite end walls of the dispenser to a degree sufficient to prevent collapsing.
Further, WO 2000/011998 A1 suggests to stiffen at least a region of the web material at at least one end of the roll by adding moisture and allowing the moisture to dry, whereby the separate sheets of the web material adhere to each other at said end in order to prevent collapsing.
EP 0 107 487 A1 and U.S. Pat. No. 5,215,211 A both suggest a protrusion depending from an upper end wall of the dispenser and insert into the void at the center of the roll.
Even though the above solutions provide satisfying results, statically compressing the roll to a certain degree requires the user to correctly refill and assemble the dispenser. At the same time, the distance between the opposite end walls of the dispenser need to remain exactly the same over the entire lifetime of a dispenser which will require a certain rigidity and durability. This, however, may increase the manufacturing costs.
Treating the roll itself leads to an additional step of manufacturing of the paper roll.
Furthermore, the stabilizing devices with protrusions inserted into the void at the center of the roll have shown good results at the beginning of depletion of the web material from the roll but do not show satisfactory results once a rather high proportion of the roll has already been dispensed from the center of the roll.


A semiconductor memory device includes a semi-conductor substrate, a MOS transistor formed on the semiconductor substrate and including a pair of impurity regions as a source and a drain, and a gate electrode, a first conductive plug formed in contact with an upper surface of one of the pair of impurity regions, and a planar ferroelectric capacitor formed by stacking a lower electrode layer, a ferroelectric layer and an upper electrode layer on the first conductive plug, a side face upper end of the first conductive plug being aligned with a corresponding part of a side face of the ferroelectric capacitor.

1. Field of the Invention
The present invention relates to a semiconductor memory device which comprises a ferroelectric capacitor, and more particularly to a semiconductor memory device which comprises a highly integrated ferroelectric memory cell array and a method of manufacturing the same.
2. Description of the Related Art
Recent popularization of portable type devices has been accompanied by frequent use of nonvolatile memories from which no stored contents are lost even when power is cut off. In addition to a flash memory or SRAM, one such nonvolatile memory is a ferroelectric memory (FeRAM) which preserves data in a ferroelectric capacitor.
For example, a ferroelectric memory is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-244426. The ferroelectric capacitor of the document is a so-called capacitor-on-plug (COP) type capacitor as shown in FIG. 1 of the Publication. A plug is formed on one of the source and drain regions of a MOSFET which is a memory transistor, and then the ferroelectric capacitor is formed thereon.
In the case of forming the FeRAM of the afore-mentioned constitution, the following-problems may occur. First, independent processes are necessary for plug formation and capacitor formation. Second, an alignment margin is necessary between the plug and the capacitor. Because of the necessity of such a lithography margin, a limit inevitably occurs in high integration. Third, contact resistance easily becomes high due to oxidation on the contact surface between the plug and the lower electrode of the capacitor.
Thus, there has been a demand for a ferroelectric memory which can achieve high integration by minimizing the lithography margin which is necessary to form a plug and capacitor and reduce contact resistance of the plug.

Semiconductor memory device and method of manufacturing the same