Clock circuitry supplies synchronized clock waves to loads on plural integrated circuit chips. The clock circuitry couples the synchronized clock waves to regions of the chips. There is a first clock wave route in a first direction from a first chip to a second chip and a second clock wave route in a second direction from the second chip to the first chip. The routes have substantially the same geometry and are in close proximity to each other so they have substantially the same effects on clock waves propagating therein in opposite directions. A phase detector and lowpass filter on the first chip responds to (1) a clock wave source and (2) a clock wave derived on a chip other than the first chip, to supply, via a common mode line, a control for voltage controlled delays of the chips other than the third chip.

Commonly assigned U.S. Pat. No. 6,594,772, issued Jul. 15, 2003, of which I am a co-inventor, discloses a single integrated circuit chip having clock circuitry for supplying clock waves to many loads on the chip. The chip includes several clock node circuits at different locations on the chip and clock coupling circuitry connected between a clock wave output and input of adjacent clock nodes. Each clock node circuit and the clock coupling circuitry are arranged for maintaining a predetermined phase relation between the clock wave output and input of adjacent clock nodes.
In one embodiment, the clock node circuits and the clock coupling circuits include feedback arrangements for maintaining the predetermined phase relation. The clock wave inputs and outputs of the nodes are connected so there is no direct feedback from the clock wave outputs and inputs of any of the different clock nodes.
In another embodiment, circuitry connected to be responsive to the clock waves at spatially displaced first and second nodes on the chip (a) compares the relative phases of the clock waves at the spatially displaced nodes, and (b) derives a signal.
Clock waves derived at disparate locations on the single integrated circuit chip of the co-pending application have substantially the same phase, or have predictable, stable phase differences. One embodiment of the device of the co-pending application is particularly adapted for use on a single relatively large integrated circuit e.g., 2 centimeters on a side, operating at a high clock frequency e.g., more than 1.0 gigahertz (GHz), wherein effects of semiconductor processing, as well as temperature and voltage variations as a function of time and/or space are minimized. The circuitry of the co-pending application is particularly adapted for resolving problems associated with clock skew. Circuitry for deriving the signal indicative of clock skew quality of the chip clock circuitry includes: (a) an additional clock node, (b) an additional coupling circuit responsive to a clock wave at the first node, and (c) a phase detector arrangement. The additional clock node responds to a clock wave derived from the additional coupling circuit. The phase detector arrangement responds to a clock wave at the second node and the clock wave output of the additional node to derive the clock skew quality signal.
Another aspect of the previously mentioned patent relates to clock circuitry for supplying clock waves to many loads on a single integrated circuit chip, wherein the clock circuitry includes several clock nodes at different locations on the chip and clock coupling circuitry connected between adjacent clock nodes. Each clock node includes (a) a clock wave input, (b) a clock wave output and (c) feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave input and clock wave output of the particular node. The clock coupling circuitry maintains a predetermined phase relation between the output and input of the adjacent clock nodes on the single chip.
In the previously mentioned patent, clock circuitry for supplying clock waves to many loads on a single integrated circuit chip comprises several clock nodes at different locations on the chip and clock coupling circuitry connected between a clock wave output and input of adjacent clock nodes. Each clock node includes an arrangement for maintaining a predetermined phase relation between clock waves at the clock wave input and clock wave output of the particular node. Each clock coupling circuit includes a feedback loop for maintaining a predetermined phase relation between the clock wave output of a first of the adjacent nodes and the clock wave input of a second of the adjacent nodes.
I have now realized that many of the principles of the previously mentioned patent are applicable, with modification, to arrangements including plural integrated circuit chips having interconnected clock circuitry.

Clock circuitry on plural integrated circuits

Hewlett-Packard Development Company, L.P.


A method and a device for signal transmission are provided, the method comprising: a terminal device determining a QCL relationship between a paging related signal and an energy saving signal, wherein the paging related signal comprises a physical downlink control channel (PDCCH) for scheduling a paging message and/or a physical downlink shared channel (PDSCH) carrying the paging message; and the terminal device receiving the energy saving signal on the basis of the QCL relationship, or the terminal device receiving the paging related signal on the basis of the QCL relationship.

Considering power saving of a terminal device, a Discontinuous Reception (DRX) mechanism is introduced. Each DRX cycle includes an on duration and an opportunity for DRX. Within the on duration, the terminal device detects a control channel. Within the opportunity for DRX (also called a sleep duration), the terminal device may stop receiving the control channel (in such case, the terminal device may stop blind detection for the control channel) to reduce power consumption, thereby prolonging the service time of a battery.
In a 5th-Generation (5G) system, a power saving signal is introduced to control a state of a terminal device to achieve a purpose of power saving. For example, the power saving signal may be a wakeup signal, and the wakeup signal is configured to instruct the terminal device to wake up in an "on duration" of a DRX cycle, the terminal device, responsive to that the wakeup signal is detected, may wake up in the "on duration" to detect a Physical Downlink Control Channel (PDCCH); and the terminal device, responsive to that no wakeup signal is detected, may not detect the PDCCH.
Therefore, how to ensure the transmission performance of such a power saving signal to further save power for a terminal device becomes a problem urgent to be solved.

Method and device for signal transmission

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


A method of making a deck for storing cargo in a shipping vehicle comprising: securing two pairs of braces to opposed surfaces associated with the shipping vehicle by engaging opposed ends of first elongated supports with the pair of braces such that each first elongated support interconnects one of the pairs of braces and extends substantially parallel to a base associated with the shipping vehicle; engaging second elongated supports with each of the braces, each second elongated support interconnecting a respective brace and the base; and positioning a decking on the first elongated supports for supporting the cargo. A brace for making the cargo deck engageable with a horizontally-extending support and a vertically-extending support.

Cargo transported for commercial and other uses is often shipped in semi-trailers or other trucks, railcars, ships, aircraft or other shipping vehicles. Stacking of the cargo within the shipping vehicle may provide efficiencies, however, certain types of cargo might not be readily stackable due to a variety of different reasons such as the nature or configuration of the cargo.

Method and device for making a cargo deck


A cryogenic processor is provided for liquid feed preparation of a free-flowing frozen product comprising. In accordance with one aspect of the invention, the cryogenic processor includes a freezing chamber having a substantially conical shape, at least one feed tray overlying the freezing chamber arranged and adapted to receive liquid composition from a delivery source, the tray having a plurality of orifices for the discharge of uniformly sized droplets of the composition from the feed tray, whereby the droplets are delivered by gravity into the freezing chamber there-below. The cryogenic processor also includes at least one sensor associated with the feed tray for determining a depth of liquid composition in the feed tray, at least one valve associated with a liquid composition delivery line, the valve being configured to control the rate at which liquid composition is delivered from the delivery source to the feed tray, and a controller responsive to the at least one sensor for controlling a position of the valve, and therefore the rate at which liquid composition is delivered from the delivery source to the feed tray.

This specification includes a microfiche appendix in compliance with 37 C.F.R. xc2xa71.96(c) consisting of two (2) slides and 166 frames.
1. Field of the Invention
The present invention relates generally to a frozen product preparation apparatus and, more particularly, to a cryogenic processor for liquid feed preparation of a free-flowing frozen product.
2. Description of the Prior Art
Sales of ice cream and frozen yogurt products have risen dramatically in recent years, and applicants herein have captured a portion of this product market through the development of a unique novelty ice cream, frozen yogurt and ice product in the form of beads. This product, marketed under the trademarks xe2x80x9cDippin"" Dots(copyright)xe2x80x9d and xe2x80x9cIce Cream of the Future(copyright)xe2x80x9d, has become very popular in specialty stores, at fairs and theme parks, and through vending machines.
Applicants have proprietary rights in the method of preparing and storing the product pursuant to U.S. Pat. No. 5,126,156, issued Jun. 30, 1992, herein incorporated by reference, as well as rights associated with improvements pursuant to U.S. Pat. No. 5,664,422, issued Sep. 9, 1997, and U.S. Pat. No. 6,000,229, issued Dec. 14, 1999, herein incorporated by reference. As is generally described therein, the patented method involves delivering flavored liquid dairy and other alimentary compositions to a feed tray and then dripping the composition into a freezing chamber. The feed tray comprises a plurality of orifices through which liquid composition passes to fall into the freezing chamber, either in the form of droplets or liquid streams, which streams break into droplets before freezing. Each orifice may also have a corresponding feed dropper, which is downwardly disposed in relation to the tray such that the liquid composition passes from the tray through an orifice and then through an associated feed dropper where a droplet or liquid stream is formed. The orifices or combination of orifices and feed droppers will hereinafter be referred to collectively as feed assemblies.
The falling droplets of liquid composition freeze rapidly (i.e., flash freeze) in the freezing chamber due to the presence of both gaseous and liquid refrigerant in the area between the orifices and the bottom of the freezing chamber, thereby forming solid beads of flavored ice cream, yogurt or other alimentary products, such as flavored ice. More specifically, as droplets of liquid free fall through a gaseous region of the freezing chamber, and before the droplets contact the liquid refrigerant, the outer spheres of the droplets form a thin frozen shell. This thin frozen shell serves to protect the spherical shape of the droplets as they impact the surface of the liquid refrigerant. The remainder of the droplets freeze completely as they pass through the liquid refrigerant, and before reaching the bottom of the freezing chamber. The frozen beads are removed from the freezing chamber and packed for distribution and later consumption.
It should be appreciated that the cryogenic processor used for preparing the above-described beaded ice-cream is a relatively sophisticated apparatus that should be tightly controlled for proper operation. For example, the liquid refrigerant preferably used is liquid nitrogen, which has an extremely high evaporation rate. It is typically desired to maintain approximately 19-21 inches of separation between the surface of the liquid nitrogen and the feed tray. If this separation distance is too small, then the liquid droplets may not have sufficient time during their free-fall from the feed tray to form the desired spherical shape. If the separation distance is too large then the impact of the droplets with the surface of the liquid nitrogen may become undesirably large. Accordingly, the introduction of liquid nitrogen into the freezing chamber should be closely controlled.
In addition, the rate at which liquid composition passes through the orifices of the feed tray and the size of the droplets is controlled by the level of liquid composition maintained in the feed tray. As a result, the delivery of the liquid composition to the feed tray should be tightly monitored and controlled.
In addition to the desire to closely control operation parameters of the cryogenic processor, other improvements are desired. For example, it is often desired to manufacture beaded ice-cream of various flavors. Often, unique flavors are created by mixing certain fundamental or base flavors. One way this may be accomplished is by manufacturing a first base flavor, then manufacturing a second base flavor, then mixing the two beaded ice-cream products. This approach, however, requires that piping and other machinery be cleaned between xe2x80x9cbatchesxe2x80x9d (i e., flavor changes). Another disadvantage of this approach is the added step of mixing the beaded form of the two base flavors.
Another way that a multi-flavor product may be created is by mixing the liquid form of the base flavors in appropriate proportions, before delivery to the feed tray. This approach, however, also requires that piping and other machinery be cleaned between batches.
Accordingly, it is desired to provide an improved cryogenic processor for preparing a unique, beaded ice-cream product.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a cryogenic processor for liquid feed preparation of a free-flowing frozen product comprising. In accordance with one aspect of the invention, the cryogenic processor includes a freezing chamber having a substantially conical shape, at least one feed tray overlying the freezing chamber arranged and adapted to receive liquid composition from a delivery source, the tray having a plurality of orifices for the discharge of uniformly sized droplets of the composition from the feed tray, whereby the droplets are delivered by gravity into the freezing chamber there-below. The cryogenic processor also includes at least one sensor associated with the feed tray for determining a depth of liquid composition in the feed tray, at least one valve associated with a liquid composition delivery line, the valve being configured to control the rate at which liquid composition is delivered from the delivery source to the feed tray, and a controller responsive to the at least one sensor for controlling a position of the valve, and therefore the rate at which liquid composition is delivered from the delivery source to the feed tray.
In accordance with another aspect of the invention, a method is provided for feeding liquid composition to a freezing chamber containing a refrigerant to form beads of frozen product. In accordance with this aspect of the invention, the method monitoring a level of liquid composition in each section of a multi-partition feed tray, closely controlling the delivery a liquid feed composition from a source to each section of the feed tray, discharging the liquid feed composition from each section of the feed tray through orifices in the form of droplets, via gravity, into a freezing chamber disposed below the orifices, monitoring a level of liquid refrigerant in a freezing chamber, and closely controlling the delivery of liquid refrigerant to the freezing chamber, in response to the step of monitoring the level of liquid refrigerant.

Control system for cryogenic processor for liquid feed preparation of free-flowing frozen product


A memory circuit includes a plurality of storage cells (100) arranged in rows and columns thus forming a storage matrix. The storage cells (100) corresponding to the same bit line (21-23) are divided into several groups (60-61) of cells for the same column, these groups having their own biasing circuit (200) in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.

1. Field of the Invention
The invention relates to an electronic memory and, more particularly, to a biasing circuit designed to bias the memory cells in groups.
2. Description of the Related Art
Memories are known electronic circuits that are in increasing use. A memory circuit comprises a plurality of storage cells organized in rows and columns. Each storage cell stores one data bit, that is to say a bit of information that can take the value "0" or "1". Address lines connect all the cells of the same row together in order to allow the selection of a row from amongst the plurality of rows forming the memory. Bit lines connect the cells of the same column together in order to allow the reading and writing of a bit in a memory cell belonging to a bit line and whose address line is selected.
The storage cells can be of various types depending on the type of memory used. Among the various types of storage cells, those having at least one transistor linking the element storing the data bit to the bit line are of more particular interest. By way of example, memories of the static RAM type generally have one or two link transistors for connecting the contents of the cell to one or two bit lines depending on whether the read operation is carried out directly on a single bit line, or differentially between two complementary bit lines. Also, some memories of the ROM type have a link transistor for connecting the contents of the storage cell to the bit line.
Memory circuits are continually increasing in size. Thus, a bit line for a large-sized memory may be connected to several hundred, or even several thousand, link transistors. In order to read a storage cell, an address line selects a storage cell whereas all the other address lines do not select any storage cells in the same column. The storage cell being read has its link transistor turned on and a large conduction current appears for charging or discharging the bit line in order to transmit the logic level stored by the cell to a read circuit.
One problem arises when there is a very large number of link transistors connected to a bit line, since the link transistors, even when turned off, exhibit a leakage current that becomes non-negligible when this leakage current is multiplied by a large number of link transistors. The problem is even more acute when it is desired to read a cell in a particular state, for example a "1" state corresponding to a high voltage, while all the other cells not selected are in the other state, for example the "0" state corresponding to a low voltage. Indeed, the sum of the leakage currents over the whole of the transistors may greatly reduce the read current delivered by the selected cell, thus greatly increasing the time required for reading a memory cell. But in the case of static RAM memories, if the leakage current is too large, this can make the state of the selected storage cell, and hence the stored value, change.
Currently, one solution to the aforementioned problem consists in using main bit lines and secondary bit lines. The secondary bit lines are parallel to the main bit lines and are connected to a reduced number of cells, for example 32 cells. A transfer gate links each secondary bit line to the main bit line. Thus, when a storage cell is selected, only the leakage currents of the group of cells connected to the same secondary bit line can influence the read time and the possible loss of data from the cell. However, in terms of read time, the propagation time through the link transistor and through the transfer gate is relatively long. Also, in terms of size, the bit lines are lines of metallization which must be disposed where no cell is situated and, therefore, doubling the number of bit lines by means of main and secondary lines is detrimental to the capacity for integration of a memory.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.

Memory with storage cells biased in groups


A cryogenic helium production system wherein a feed which includes carbon dioxide is processed in a dual temperature system including an upstream higher temperature and higher pressure column or dephlegmator, thus eliminating the need for a separate non-cryogenic carbon dioxide removal step.

Helium is generally produced by separation from a natural gas stream. An often used method for carrying out the separation is cryogenic processing.
Typically carbon dioxide is also present in the natural gas along with the helium. If cryogenic processing is to be employed to separate the helium from the natural gas to produce crude helium, it has heretofore generally been necessary to remove the carbon dioxide from the natural gas prior to the cryogenic processing. This is because at the low temperatures which cryogenic processing operates to produce crude helium, the carbon dioxide will freeze and plug or otherwise foul the processing equipment. Examples of carbon dioxide removal upstream of such cryogenic processing include contacting the feed with a liquid such as certain amines and/or passing the feed through molecular sieve beds for adsorption of the carbon dioxide. Such pretreatment systems increase both the capital and operating costs of a crude helium production system.
Accordingly it is an object of this invention to provide a cryogenic helium production system which can process a feed stream containing helium, hydrocarbon and carbon dioxide without need for a separate carbon dioxide removal step upstream of the cryogenic processing.
As mentioned, the helium is found with natural gas and the hydrocarbon is preferably recovered in addition to the helium. Typically the hydrocarbon is recovered at a relatively low pressure from the cryogenic separation and then compressed to higher levels for pipeline transmission. The relatively low pressure is the result of the cryogenic processing which operates more efficiently at lower pressures. However, it would be desirable to have a cryogenic processing system for producing crude helium which can also produce at least some hydrocarbon at higher pressure thus reducing compression requirements and therefore reducing costs.


A device is provided for retaining a respiratory disease management device and for displaying respiratory disease management information. The device comprises a rear wall, first and second opposing side walls adjoining the rear wall, and a front wall extending from the first side wall. An attachment component secures the rear wall to an upright structural surface. The walls of the device define a partially enclosed retention space for holding a respiratory disease management device such as a respiratory disease medicine delivery device or a peak flow meter. A substrate such as a card is secured to the holding device, and displays printed matter comprising information relating to respiratory disease management.

In the treatment of respiratory diseases such as asthma and allergies, the distribution of asthma or allergy management devices such as therapeutic dosage delivery devices and respiratory assessment devices is for self-use by a patient according to a management strategy prescribed by the patient's health care provider. As is well known to persons skilled in the art, dosage delivery devices typically include a cartridge or housing that contains an asthma medicament in liquid or powder form, and an outlet adapted for delivering dosages to the patient orally or nasally. The medicament is either pre-loaded in the cartridge, or a package containing the medicament is loaded in the cartridge by the patient. The whole of such delivery devices can be disposable after one or more uses, or the cartridge can be reusable indefinitely with the package containing the medicine replaced when depleted. Depending on the severity of the pulmonary disease, a number of different kinds of medicines may be prescribed to a patient. For example, some medicines are indicated for prevention and must be administered on a repeated, regular basis, while other medicines are indicated for emergencies and administered only on an as-needed basis.
When the medicament is a liquid, it can be provided in the cartridge in bulk quantity, which requires the patient to administer the proper dosage through an inhalation means such as a nozzle. One common type of delivery device, often termed a metered dose inhaler, consists of a housing having an internal passage and an orifice. A canister equipped with a valve and containing pressurized liquid medicament is inserted by the patient into the housing, such that the stem of the valve is seated in the internal passage of the housing. To administer a dosage of the medicine, the patient actuates the device by pushing the canister and the housing towards each other, thereby opening the valve and releasing a properly metered dosage from the orifice. Alternatively, when the medicament is a powder, it can be distributed in a package containing pre-metered doses in individual packets (e.g., blisters), in which case the delivery device includes a patient-actuated means for puncturing each packet to deliver the dosage to the patient.
One example of a respiratory assessment device is the peak flow meter. When properly used, the peak flow meter enables the patient to track the severity of his or her asthma or related pulmonary condition over time and evaluate the effectiveness of his or her prescribed management strategy. Such a self-assessment provides useful feedback for the patient's health care provider, and can indicate whether the management strategy should be modified such as by changing the dosage schedule or selecting a different medicine.
In view of the foregoing, and as well known to persons skilled in the art, the success of any given asthma management strategy depends significantly on the efforts, knowledge, and skill of the patient. For instance, the patient must make proper use of the asthma management products according to the instructions provided, whether those products include dosage delivery devices or testing devices. It has been found, for example, that the improper actuation of inhaler products can result in the delivery of therapeutically ineffective dosages of medicine to the patient's respiratory system. In the case of testing devices, improper use can produce inaccurate data. In addition, the patient must adhere to the prescribed management strategy, including administering the correct medicine according to conditions and administering the correct dosage or number or dosages per day and at the correct times. Common reasons for the failure of a patient's management strategy include the absence of means for reminding the patient to use the prescribed management devices, and the lack of readily available information to keep the patient informed about his or her disease and about the proper use of the prescribed management devices.
It would therefore be advantageous to provide a device for holding and storing respiratory disease management devices in a highly visible location so as to remind a patient suffering from chronic respiratory diseases to adhere to his or her treatment schedule. It would be further advantageous to provide such a holding device with a display of information useful to the patient in the management of his or her disease. The present invention is provided to address these and other problems attending the management of respiratory-related disease.

Respiratory disease management device and related method


A localization process in a network of source devices and sink devices on a 1394 bus, is performed by a source device while it is communicating to a sink device, which determines local network links from nonlocal ones. An actual round trip time calculation is performed only by the source device and the sink device can be relatively passive. The duties of the sink device are performed in hardware and involve (trivially) modifying the received message while moving the message from the input isochronous channel buffer to the output isochronous channel buffer.

The 5 C group of companies have developed DTCP/IP method that uses IP and asynchronous communications to accomplish localization determination. The IDB Forum developed a similar method for communication between source and sink devices in a 1394 network, which uses AV/C asynchronous communication and involves a sink device to cryptographically manipulate a message during round trip time measurements.
A typical 1394 includes at least one source device and at least one sink device among many devices connected to a 1394 bus. A localization process determines that the communication loop between the source device is within the network. Conventional methods (e.g., DTCP/IP), measure round trip time using software stacks, and so the majority of the time measured is really time spent in nodes of switching from one of software stack to another, rather than time data travels on the bus.

Localization determination process for 1394 serial bus


A technique for determining particulate density in a fluid monitors the changes in the speed of sound. Since the speed of sound is intimately related to the composites of the air mixture and since the speed of sound of clean air at any temperature and humidity can be calculated exactly, it is possible to estimate the density of any foreign particulates in the air by observing changes in the speed of sound. Formulations are derived that correlate the change in the speed of sound of the air mixture to their density fluctuations, thus allowing people to estimate the mass density of foreign particulates under any temperature and humidity. Alternatively, the change in density of the air mixture can be detected, thereby indicating the presence of contaminants and a possible alarm, even if the contaminants are not yet identified.

This invention provides a cost-effective methodology to measure the mass concentration of impurities in the air resulting from the exhaust of a combustion system such as diesel and gasoline engines used in the automotive industry. This methodology can also be used to measure any particulates in gas streams used in industry. It is drastically different from the conventional methods that are currently used by the automotive companies in monitoring particulates emissions. The invention can also be used to detect and/or identify and/or measure pollutants in ambient air.
Test data have shown that the average sizes of particulates from the exhaust of combustion systems are in the order of nanometers, or 10−9 meter, which are invisible but can be harmful when inhaled. The Environmental Protection Agency (EPA) has established strict regulations on the level of mass concentration of particulates discharged from the exhaust of combustion systems in order to reduce air pollution. The allowable level of particulates decreases every year as the demand on pollution control increases.
The conventional way of measuring the level of particulates concentration is to use a special filter to collect the residuals of the exhaust gases through a diluted chamber over certain period of time, and then weigh them on an electronic micro-scale inside a clean room. The equipment and facilities involved can be extremely expensive and the whole process can be very time consuming.
Quality of breathing air is an important health issue. While EPA has established outdoor air quality standards on ozone and particulates, no indoor air quality standards have been established except for the well known contaminants, such as Radon, as there are too many possible indoor air pollutants. Most people spend up to 90% of their time indoors. Although air contaminants in a private home may be limited to the owner's concern, air quality in office buildings, public transportations, theaters, stores, etc. is a public health issue. While it is possible that contaminated air in the outdoors manages to get inside a building, the source of air contamination is often found inside a building. Tobacco smoke, fungi, carbon monoxide, vapor from paint and carpet glue, and communication cables are well known sources of air pollution, but oftentimes the sensors are people who complain of nausea, headaches, red eyes, and dry mouths, many of which are dismissed as subjective sensations instead of serious illnesses. Thus, there is a need to be able to quantitatively detect the presence of various forms of air pollutants in a closed environment both timely and inexpensively. Such a sensor will be useful to locate the source of contaminations as well.
There are currently a number of airborne particle counters and toxin detectors available in the market, some of which are costly and require experienced operators.


The present invention consists of an improvement to a traditional cord-lock device. The combination cord-lock and light device of the present invention consists of a housing having a plunger and locking device including a biasing member and further adapted to encapsulate a light-emitting diode circuit assembly. The circuit assembly includes a switch mechanism coupling to an activator button located on the exterior of the cord-lock housing. The switch mechanism enables the LED to operate in a steady state, off, or in a pulsating mode. The housing is further adapted to direct the LED light exterior to the device.

The present invention relates to a combination light and cord-lock device.
Cord locking devices prevent longitudinal movement of the device on a rope, line, string, other similar cord. Conventionally, a cord lock device includes an interior channel or passage through which a cord passes, a self-locking mechanism for retaining the device in fixed location relative to the cord and further adapted to prevent movement of the device relative to the longitudinal axis of the cord, and a release mechanism for selective releasing of the lock mechanism.
A representative cord lock with depressible plunger, described by Boden in U.S. Pat. No. 4,288,891 issued on 15 Sep. 1981 includes a spring-resisted plunger that selectively retracts inwardly relative to the body when sufficient pressure is applied to the plunger. The plunger includes an interior passage that aligns with a corresponding interior passage of the cord-lock body when the plunger is depressed. When released, the plunger extends from the body and the two passages become mis-aligned. This mis-alignment, accordingly, causes an inserted cord to become lodged (or locked) in the device and, thus, preventing movement of the device relative to the longitudinal axis of the cord.
Although the art represented by Boden has improved, the basic cord-lock device and its operation remains, in essence, unchanged. Improvements include the cord lock of Bakker described in U.S. Pat. No. 4,453,292 issued on 12 Jun. 1984 wherein the cord lock device consists of only three pieces including a a molded plastic cylinder, molded plastic piston, and a biasing spring.
Another improved cord-lock, described by Krauss in U.S. Pat. No. 4,622,723 issued on 18 Nov. 1986, includes a rectilinear closed bottom molded housing member, a one-piece molded insert plunger, and internal spring.
Yet another improved cord-lock, described by Maurai in U.S. Pat. No. 4,839,946 issued on 20 Jun. 1989, includes a two-piece device including a molded socket with a pair of resilient flaps, and a one-piece molded plug with wedge-shaped end portion engaging the resilient flaps.
In each of the known cord-lock devices, and generally in the state-of-the-art cord-lock devices, little improvement to extending the functionality of cord-locks has been attempted. Although cord locks are well-suited to various applications including in garments and transport containers to keep, for example, pockets or compartments closed, little effort has been extended to make a traditional cord-lock serve additional functions. One function overlooked in the prior-art is adding a light source to the cord lock. One advantage of such a light source includes utilization in the garment industry where active garments needing a secure means for closing pockets, flaps, and the like, could further assist the wearer by providing an illuminating or safety-warning light. Thus, there is a need for a cord-lock device that includes a light source.
Some known combination devices combining a light with another function include the portable light with clip disclosed by Ford et al. in U.S. Pat. No. 7,438,431 issued on 21 Oct. 2008. Ford discloses a portable light comprising at least one light emitting diode, a power source, a switch operable for closing an electronic circuit between the power source and the LED and a body adapted to receive the LED, the battery and the switch and the body further comprising a loop portion towards one end. This structure, similar to a carabiner used in mountaineering or as a decorative key-fob, is well known in the art for quick attachment to a line or cord without locking to the cord and allows the cord to slide freely therethrough and does not lock to the cord by design.
Another example of a combination light and clip device includes the compact flashlight disclosed by Booty, Jr. in U.S. Pat. No. 7,357,540 issued on 15 Apr. 2008 wherein a compact flashlight is configured such that it can be coupled to a key ring or other devices and includes a locking mechanism that inhibits accidental opening and detachment from the ring or other device.
Yet, despite combination of flashlight-like devices there remains a need for a combination device that provides the cord-lock security of clasping a line or rope combined with the convenience of a small, portable light device. Such a device should provide superior cord or line locking ability, readily adapt to existing clothing, garments, outerwear or other gear-bags and the like, be able to readily be incorporated in the factory or in the field, and provide selectable operation of a compact, energy-efficient light source. And, because such devices will be used on a variety of outdoor garments and gear, any improved combination device should be rugged and water resistant.


The present invention relates to methods and kits for determining a predisposition and surveillance protocols for developing cancer of various sites due to specific mutation in at least one allele of CHEK2 gene and/or at least one allele of NOD2 gene and/or at least one allele of CDKN2A gene.

Up to now MSH2/MLH1 and APC gene mutations have been considered as the major cause of inherited colorectal cancer (CRC). Carriers of mutations within the above genes have a very high risk of cancer, but they constitute only a few percent only of all CRC.
It has been reported that having a chronic inflammatory status longer than 8-10 years is also related to an increased risk of CRC. Despite long-term efforts aimed to find the way of diagnosing the predisposition to CRC, a procedure allowing this has not yet been discovered.
NOD2 gene has been mapped on chromosome 16q12 (Ogura et al., J. Biol. Chem. 2001; 276: 4812-4818). It contains 12 exons and encodes a protein composed of 1040 of amino acids. In 2001, a correlation between 3020insC in exon 11 of NOD2 and the occurrence of Crohn's disease (CD) was shown. PCT Publication WO 02/44426 presents the sequence of NOD2 as well as the relation between distinct variants of this gene (including a variant with 3020insC) and CD. CD and ulcerative colitis are recognized as inflammatory bowel diseases.
CHEK2, (also known as CHK2 [MIM 604373]) is located on chromosome 22q and encodes the human analogue of yeast Cds1 and Rad53, which are checkpoint kinases. Activation of these proteins in response to DNA damage prevents cellular entry into mitosis. CHEK2 is activated through phosphorylation by ATM in response to DNA damage induced by ionizing radiation. Activated CHEK2 phosphorylates BRCA1 and TP53 proteins, regulating tumor suppressor function of these proteins (Matsuoka et al., Proc. Natl. Acad. Sci. USA, 97: 10389-10394, 2000, Chaturvedi et al., Oncogene, 18: 4047-54, 1999, Ahn et al., Cancer Res., 60: 5934-6, 2000, Falck et al., Nature, 410: 842-847, 2001, Chehab et al., Genes Dev., 14: 278-288, 2000, Shieh et al., Genes Dev., 14: 289-300, 2000, Lee et al., Nature, 404: 201-204, 2000.).
In Poland there are three polymorphic variants of CHEK2, which in aggregate are present in 5.7% of the population; two of these (1100delC and IVS2+1G>A) are rare and result in premature protein truncation. The third is a common missense variant (I157T) that results in the substitution of an isoleucine for a threonine. All three variants have been found to be associated with a predisposition to prostate cancer. The CHEK2 protein is expressed in a wide range of tissues and the full range of cancers associated with inactivating CHEK2 mutations has not yet been determined.
The IVS2+1G>A mutation creates a 4-bp insertion due to abnormal splicing, creates premature protein termination codon in exon 3 and leads to the disruption of protein expression. There are no reports suggesting correlation between the CHEK2 IVS2+1G>A allele alone and increased predisposition to cancer. The IVS2+1G>A variant has been reported previously only in a single family with prostate cancer in the United States (Dong et al., Am. J. Hum. Genet., 72: 270-280, 2003). However, the IVS2+1G>A allele did not segregate with prostate cancer within this family and it was not proven that the IVS2+1G>A confer increased prostate cancer risk.
The 1100delC variant of CHEK2 is present with a 1.1-1.4% frequency in normal population in the European countries studied so far but in North America the allele appears to be relatively rare (CHEK2 Breast Cancer Consortium, Nature Genet., 31: 55-59, 2002; Offit et al., BMC Med. Genet. 15: 1, 2003). This allele has been found to confer a modestly elevated risk of breast and prostate cancer.
The most common CHEK2 variant identified so far was Ile157Thr. The role of this variant, however, is controversial, even though both genetic and biochemical data from previous studies suggest that this mutation can be deleterious (Falck et al., Nature, 410: 842-847, 2001, Bell et al., Science 286: 2528-2531, 1999, Li et al., Mol Cell 9: 1045-1054, 2002). On the other hand, this mutation was found in 2.1% (2/95) of healthy population control individuals in Finland and was proposed as a polymorphism (Vahteristo et al., Cancer Res. 61: 5718-5722, 2001). Other reports also indicate that this mutation is relatively common in normal healthy control individuals (CHEK2 Breast Cancer Consortium, Nature Genet., 31: 55-59, 2002, Allinen et al., Am. J. Hum. Genet., 72: 1023-1028, 2003). This allele does not appear to increase the risk of breast and prostate cancers (Allinen et al., Am. J. Hum. Genet., 72: 1023-1028, 2003). On the other hand one report suggests that I157T variant is a low penetrance allele for prostate cancer (Seppala et al., Br. J. Cancer, 89: 1966-1970, 2003). Whether this functionally related CHEK2 variant confers susceptibility to prostate cancer, or even to other cancers, remained to be clarified.
CDKN2A gene (OMIM 60160) is a tumor supressor gene regarded as the major melanoma susceptibility gene. (Hashemi et al., Nature, 366: 704-707, 1993). Its protein product p16 is a cyclin-dependent kinase inhibitor that suppresses cell proliferation (Whelan et al., New Eng. J. Med. 33: 975-977, 1995). CDKN2A variants are associated with strong (it is with high penetrance—responsible for strong cancer familial aggregation) predisposition to melanoma and cancers of breast, pancreas and larynx (Whelan et al., New Eng. J. Med., 33: 975-977, 1995; Borg et al., J. Natl. Cancer Inst., 92: 1260-1266, 2000, Smigiel et al., Mol Carcinog., 39: 147-54, 2004).
In the U.S. Patent Publication U.S. 20030175721, CDKN2A variants associated with increased melanoma predisposition have been described. There is also some evidence to indicate a possible association between CDKN2A and head and neck cancer (Schneider-Stock et al., Am. J. Hum. Genet., 72: 216-218, 2003), respiratory malignancies (Belinsky et al., Proc. Natl. Acad. Sci. USA, 95: 11891-11896, 1998) and colorectal cancer (Burri et al., Lab. Invest., 81: 217-229, 2001).
In Poland common CDKN2A variants have been reported. One of them—an alanine to threonine substitution at codon 148 (A148T)—has been estimated to be present in approximately 3-3.5% of the population (Debniak et al., Int. J. Cancer, 110 :558-562, 2004; Lamperska et al., Acta Biochim. Pol., 49: 369-376, 2002). Functional studies suggest that this variant is a polymorphism which appears to have no major affect on p16 function (Ranade et al., Nature Genet; 10: 114-116, 1995; Lilischkis et al., Int. J. Cancer, 66: 249-254, 1996). Nevertheless, the A148T change has been found to be over-represented in melanoma kindreds (3%) in comparison to the general population (1.8%) (Queensland, Australia) (Aitken et al., J. Natl. Cancer Inst., 9: 446-452, 1999). Preliminary results of our recent population-based study also suggest that A148T change can be associated with increased melanoma risk. A series of around 400 melanoma cases and around 1000 controls (˜500 newborns and ˜500 adults) was examined. The Nt442g>a (A148T) prevalence was 2.5-fold increased among melanoma patients. No overrepresentation of the Nt500c>g and the Nt540c>t polymorphisms in Polish melanoma population was observed. The A148T carrier population (heterozygous G/A alleles) was more likely to have a relative with malignancy compared to the non-carrier population (57% versus 36%, respectively (p=0.03)).
Prostate cancer is a leading cause of morbidity and mortality in men. Outside of the context of a family history, relatively little is known about the genetic determinants that cause prostate cancer. Epidemiological studies suggest that 5-10% of all prostate cancers are attributable to high penetrance susceptibility genes. The strongest evidence for the role of inherited genetic factors in development of prostate cancer comes from a Scandinavian study on twins that suggested that as many as 42% of prostate cancer risk could be explained by an inherited predisposition (Lichtenstein et al., N. Engl. J. Med., 343: 78-85, 2000). Evidence also points at a complex genetic basis of prostate cancer, involving multiple susceptibility genes and variable phenotypic expression. Different chromosomal loci have been linked to prostate cancer including: HPC1, HPC2, PCAP, CAPB, HPCX, 20q13, 16q23. However, no major prostate susceptibility genes have so far been identified. Only two studies have shown any success cloning candidate susceptibility genes from these regions: HPC1 (MIM 601518) and HPC2/ELAC2 (MIM 605367) (Tavtigian et al., Nature Genet., 27: 172-180, 2001; Carpten et al., Nature Genet., 30: 181-184, 2002). However, other studies suggested a limited role for those genes in hereditary prostate canter (Wang et al., Cancer Res., 61: 6494-6499, 2001.; Xu et al., Am. J. Hum. Genet., 68: 901-911, 2001; and Rebbeck et al., Am. J. Hum. Genet., 67: 1014-1019, 2000).
Breast cancer is a common disease. Each year, approximately 200,000 women in the United States alone are diagnosed with breast cancer, and one in nine American women will develop breast cancer in her lifetime. Hereditary breast cancer is caused by a mutated gene passed from parents to their children. Estimates of the incidence of hereditary breast cancer range from between 5 to 10 percent to as many as 27 percent of all breast cancers.
In 1994, the first gene associated with breast cancer, BRCA1 (BReast CAncer1) was identified on chromosome 17. A year later, a second gene associated with breast cancer, BRCA2, was discovered on chromosome 13. When individuals carry a mutated form of either BRCA1 or BRCA2, they have a high risk of developing breast cancer. Not all hereditary breast cancers are caused by BRCA1 and BRCA2. In fact, a large proportion of breast cancers is not associated with mutation of these two genes.
Despite of longstanding research efforts aimed to develop a mode of diagnosing increased predisposition to cancers of various sites, such diagnostic methods are still needed.
Accordingly, there is a need for the identification of genetic markers that indicate a predisposition for developing cancer and/or malignancies of various sites, (e.g., colorectal cancer, malignant melanoma, such tumors as cancers of the prostate, breast, thyroid, stomach, colon, kidney, lung, pancreas and larynx and myeloproliferative syndrome), that can be used to identify subjects that have an increased susceptibility for developing cancer and/or malignancies, i.e., they are predisposed to develop cancer and/or malignancies.


An image is formed by thermally transferring dyes of a thermal transfer sheet onto a print recording medium, and then a protection layer is formed on the formed image. The transport speed of the print recording medium in the event of thermal transferring the dyes onto the print recording medium is set higher than that in the event of thermal transferring the protection layer onto the print recording medium. Thereby, the amount of thermal energy for application in the event of protection layer formation is increased to be greater than that in the event of image formation. Thereby, occurrence of concave-convex portions formed on the printed surface in association with a density difference in the event of image formation is prevented, and concurrently, the surface pattern in the event of image protection layer formation is improved.

1. Field of the Invention
The present invention relates to an image forming apparatus and method for performing image formation and lamination of a protection layer on an image to protect the image formed on a print recording medium.
2. Description of the Related Art
Image forming apparatuses include those of a sublimation type in which color materials, such as dyes, of a thermal transfer sheet are transferred onto a print recording medium to thereby form an image on the medium. In an apparatus of this type, a transparent protection layer is additionally formed on an image to protect the image formed on the print recording medium. The protection layer has functions of, for example, shielding an image from gases potentially causing image deterioration, preventing the image from discoloration associated with absorption of UV light, preventing image-forming color materials, such as dyes, from being transferred to an article including various plasticizers, such as erasing rubber, preventing the image from frictional wear, and protecting the image from sebum.
Such a protection layer is provided by being laminated on, for example, a film-shaped base material, and is thermally transferred thereonto by a thermal head. In addition to the image protection capability, the protection layer thus thermally transferred onto the image is able to prevent curling of the print recording medium. Further, depending on the case, in the event of thermal transfer being performed by using the thermal head, thermal energy incoming from the thermal head is arbitrarily varied. In this case, a small concave-convex pattern is formed with the protection layer on the surface of the medium, and the surface is arbitrarily treated to form a silky pattern, mat pattern, or lustrous pattern.
However, problems such as described below can occur when performing the surface treatment of the image during image formation and protection film lamination. In the event of image formation, concave portions occur on a printed surface in a high density print region such as dark color region. Thereby, cases can take place in which concave-convex portions corresponding to the gradation level of the image mixedly occur in the print region to the extent of degrading quality of the printed surface. This problem can possibly provide adverse effects on print quality after the protection layer is formed on the image. More specifically, in a portion where concave portions attributed to the high density print region have occurred, the concave portions affect the surface pattern of the protection layer, which is formed in the subsequent stage, to be nonuniform. As such, in the event of the surface treatment of the protection layer, also the profile of a small concave-convex pattern formed by the surface treatment becomes nonuniform, thereby degrading quality of the printed surface.
The image forming apparatuses of the above-described type include those that implement high speed printing by increasing a travel speed of a print recording medium to a highest possible level. In this case, the travel speed of the print recording medium is increased to the highest possible level not only in the event of image formation, but also in the event of protection layer formation. As such, depending on the case, compared to the past or existing techniques in which a transport speed of the print recording medium is not increased, the time period for application of pressure and thermal energy to the protection layer is shorter, thereby causing the profile of the small concave-convex pattern formed after image protection layer transfer to be unclear.


A mining shovel includes a dipper assembly comprising a dipper arm coupled to a dipper, a boom assembly configured to support the dipper assembly, and an overcrowd prevention system including one or more sensors configured to monitor an axial force. The mining shovel also includes a swing abuse prevention system, including one or more sensors configured to monitor one or more compound loading forces, and one or more sensors configured to monitor a torsion loading force. The mining shovel also includes a control module configured to receive signals from the sensors, and to control at least the crowding force applied to the dipper.

This section is intended to provide a background or context to the invention recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
Typical mining shovels or excavators use a dipper assembly to scoop earth or other material from horizontal or vertical faces. These conventional mining shovels typically have a fixed boom, and the dipper assembly is mounted on the boom via a crowd mechanism. The fixed boom extends upwardly and outwardly from the frame. The dipper assembly is typically forced into a generally vertical face (i.e. a bank, etc.) by a crowding force, digging into the bank and filling the dipper assembly with material. Once the dipper is filled with material, the dipper is moved to a deposit point to unload the material.
As the dipper assembly digs into the bank, the shovel operators are able to continue to apply a crowding force, perhaps excessively, forcing the dipper assembly into the bank. This excessive crowding force can cause damage to the dipper assembly or to other components of the mining shovel. The excessive crowding force can also cause a "boom jack" condition, where the boom pivots and "jacks" away from the ground as a result of the excessive force. Also, following loading of the dipper, operators often attempt to swing the dipper assembly before the assembly is sufficiently free of the bank. This swing force can cause the mining shovel to twist, creating a torsion force or compressive loading force on the mining shovel. This excessive force can also damage the mining shovel or its components.
Conventional mining shovels may include a crowd force control to prevent excessive crowd force. An example of such a conventional crowd force control can be found in U.S. Pat. No. 7,519,462 issued Apr. 14, 2009, for "Crowd Force Control in Electrically Propelled Machine." This patent discloses a method for limiting the output torque of an electric propulsion motor based upon the occurrence of a crowd force condition of the machine. This conventional method limits crowd force based on a crowd force threshold, however, and is susceptible to damage by an applied crowd force below the specified threshold.


A system for binary code instrumentation to reduce effective memory latency comprises a processor and memory coupled to the processor. The memory comprises program instructions executable by the processor to implement a code analyzer configured to analyze an instruction stream of compiled code executable at an execution engine to identify, for a given memory reference instruction in the stream that references data at a memory address calculated during an execution of the instruction stream, an earliest point in time during the execution at which sufficient data is available at the execution engine to calculate the memory address. The code analyzer generates an indication of whether the given memory reference instruction is suitable for a prefetch operation based on a difference in time between the earliest point in time and a time at which the given memory reference instruction is executed during the execution.

1. Field of the Invention
The present invention is directed to computer systems. More particularly, it is directed to techniques to reduce latency of memory access operations within instruction streams executed at computer processors.
2. Description of the Related Art
Microprocessor speeds have been increasing dramatically as the underlying semiconductor technology has advanced. Central processing units used in single-user workstations and even in laptops today are often, at least in terms of clock rates, several times faster than the fastest processors in use just a few years ago. However, changes in processor clock rates do not always result in similar relative improvements in application performance as perceived by end users. A number of factors may affect overall application performance in addition to processor clock rates, among which one of the more important factors may be latency to memory: that is, the time it may take to transfer data and instructions between the memory hierarchy and the processor at which the instructions manipulating the data are executed. Improvements in memory access times have in general not kept pace with improvements in processor speeds. If processors frequently have to wait for data or instructions to be received from memory, many processor cycles may be wasted instead of being used for doing "useful" work, thus reducing the impact of faster clock rates on application performance.
A variety of techniques have been developed in attempts to address the mismatch between memory latency and processor speeds. For example, a number of hierarchical cache architectures have been developed to store frequently accessed data and instructions closer to the processors than main memory. However, cache implementations usually involve tradeoffs between cache size and proximity to the processors; it may not always be feasible to implement large enough caches sufficiently close (in terms of access latency) to the processors to overcome the memory latency problems. In many processor architectures, for example, relatively small and fast Level-1 (L1) caches may be employed, together with larger but not as fast Level-2 (L2) caches. Lookups for data and/or instructions may be performed hierarchically. First, the L1 cache may be examined; if the data/instructions are not found in the L1 cache, the L2 cache may be examined; and if the data/instructions are not found in the L2 cache, the data/instructions may be fetched from main memory. More than two layers of caches may be implemented in some processor architectures. While accesses to L1 caches may be fast (e.g., a few processor cycles), the latency to the L2 caches may still be sufficiently large with respect to processor clock rate (e.g., tens or hundreds of processor cycles) that for many applications, the cache latency (as well as the latency to main memory) may still have a significant impact on overall application throughput.
In another complementary approach to the memory latency problem, some processor architectures may support prefetch instructions that allow data to be fetched from memory prior to the time that it may be needed, thus masking at least some of the effects of long memory access times. Such prefetch instructions may typically be inserted into applications at code generation time (e.g., at compile time). However, determining exactly which memory reference candidates are the best candidates for prefetch may be hard, especially when only binary or compiled versions of the application code are available for instrumentation. In addition, when more than one technique for inserting prefetch instructions into program code may be available, it may be difficult to determine the relative efficiency of the various techniques.

Binary code instrumentation to reduce effective memory latency


Method and apparatus for pumping drilling fluid (mud) containing drill cuttings, comprising a centrifugal pump with screw pump accelerator. The screw pump creating positive pressure for centrifugal pump inlet to increase performance. The screw pump mud level fluctuations are compensated by the vertical screw pumping unit. Adjusting the elevation of pump will adjust the quantity of mud pumping, which is not possible with ether one pump alone. Air is allowed to mix with the mud in the centrifugal pump to create air bubbles to decrease density of the mixture and decrease the head pressure.

During the drilling of a well, mud is circulated down hole to carry away drilling cuttings. On the surface the mud is recirculated in different tanks using pumping units for delivering the mud to de-silter and de-sander. This pump is delivering the mud to the sample catcher, which need consistent flow for analytical measurement on drilling cuttings contained in the mudflow.

Centrifugal pump with screw pump accelerator


An equalizer is disclosed. The equalizer includes a filter, configured to receive the first transmission signal, to perform a filtering operation on the first transmission signal according to a feedback signal to generate an output signal; a first slicer, configured to generate a first sliced signal according to a signal level of the output signal and to adjust an amplitude of the first sliced signal according to an amplitude control signal; a boost control module, configured to generate the feedback signal according to the output signal and the first sliced signal; and a control circuit, configured to receive a second transmission signal on the transmission line and to output the amplitude control signal according to an amplitude of the second transmission signal.

1. Field of the Invention
The present invention relates to an equalizer, and more particularly, to a continuous-time adaptive equalizer.
2. Description of the Related Art
As is well known in the art, when a signal is transferred via a transmission line, the signal decays during the transmission process. This means that for transmission lines having a great length, the signal decay is more obvious. Therefore, when the signal arrives at the destination (for example, a receiver), the signal received by the receiver may contain distortions.
In order to solve the above-mentioned problem, an equalizer is often established logically in front of (i.e., before) the receiver such that the original signal can be recovered from the decayed signal. This allows the receiver to correctly process the received signal.
For example, in the data transmission of a USB interface, a PCI-E interface of a computer system, or the data transmission of an HDMI interface of an LCD, high-frequency portions of the signal often decay in the transmission process. Therefore, the aforementioned equalizer is often established at the receiving ends of the above-mentioned interfaces to provide an appropriate gain for the high-frequency portions of the signal such that the original signal can be recovered from the decayed signal. In this way, said computer system or said LCD can process the recovered signal.
In "ISSCC2005/SESSION18/HIGH-SPEED INTERCONNECTS AND BUILDING BLOCKS/18.1 (A 10 Gb/s CMOS Adaptive Equalizer for Backplane Applications)" published by Srikanth Gandi, Jri Lee, Daishi Takeuchi, and Brhzad Razavi, a continuous-time adaptive equalizer is disclosed. Please refer to FIG. 1. FIG. 1 is a block diagram of a conventional continuous-time adaptive equalizer 100. As shown in FIG. 1, the continuous-time adaptive equalizer 100 comprises an active high-pass filter 110, a slicer 120, a boost control module 130, a swing control module 140, and a buffer 150.
The active high-pass filter 110 is utilized to perform the above-mentioned amplifying (signal recovery) operation. In other words, the active high-pass filter 110 performs the amplifying operation on the high-frequency portions of the received data signal Din to output a processed data signal Dout. The processed data signal Dout is then buffered by the buffer 150, and is further outputted to a following receiver (not shown in FIG. 1).
However, when the equalizer 100 receives the data signal Din, the equalizer 100 cannot predict the condition of the data signal Din. For example, the equalizer 100 cannot determine the degree of signal decay. Therefore, the equalizer 100 requires an adjusting mechanism to dynamically adjust the filtering frequency band of the active high-pass filter according to the properties of the data signal Din.
In this case, the slicer 120 and the boost control module 130 are utilized as the above-mentioned adjusting mechanism. As shown in FIG. 1, the slicer 120 and the boost control module 130 form a feedback loop to control the filtering frequency band of the active high-pass filter 110.
The slicer 120 converts the signal at node A (Dout) into a square wave. The boost control module 140 outputs a feedback signal to the active high-pass filter 110 according to the difference between the signals at the node A and node B such that the filtering frequency band (i.e., the frequency response) of the active high-pass filter 110 can gradually approach a desired frequency band according to the feedback signal. In this way, the data signal Dout eventually may resemble the originally transmitted data signal.
However, if only the boost control loop is utilized, the accuracy of the data signal Dout cannot be guaranteed. Please note, the equalizer 100 cannot determine the amplitude of the data signal Dout when receiving the data signal Dout. It is apparent that if the square wave outputted from the slicer 120 does not correspond to the signal Dout at the node A, then the boost control module 130 may lock the entire equalizer 100 on an incorrect operational point. This will cause the active high-pass filter 110 have incorrect frequency responses such that the data signal Dout cannot be recovered as the original data signal.
Therefore, the swing control module 140 is established to solve the above-mentioned problem. In this case, the slicer 120 and the swing control module 140 form another feedback loop. The additional feedback loop is utilized to control the slicer 120 to output a square wave having a desired amplitude. In other words, the swing control module 140 outputs another feedback signal according to the amplitude differences between the signals at node A and node B such that the slicer 120 is controlled to output the square wave having the same amplitude as the signal at the node A.
Utilizing these two above-mentioned feedback loops, the equalizer 100 can ensure that the outputted data signal Dout is very close to corresponding to the original data signal. This results in an improvement to the signal transmission quality.
Unfortunately, the above-mentioned equalizer 100 has disadvantages. As shown in FIG. 1, two feedback loops lie in the same signal route. As is well known, the, two feedback loops cannot work simultaneously. In fact, if the two feedback loops were simultaneously in operation then the stability of the entire equalizer 100 may be reduced. For example, the two feedback loops may introduce an oscillation, and thus the stability of the equalizer 100 is reduced by said oscillation. Therefore, in the actual application, in order to increase the stability of the equalizer 100, the operational speed (i.e., the frequency band) of the swing control module 140 (the swing control loop) must be greater than that of the boost control module 130. In other words, the equalizer 100 should firstly use the swing control module 140 to make the amplitudes of the signals at the node A and node B equal. Secondly, after the amplitudes of the signals at the node A and node B are adjusted, the equalizer 100 is switched such that the boost control module 130 becomes active and starts operation. In this way, the boost control module 130 can start to perform the above-mentioned feedback control to adjust the high frequency swing of the data signal Dout such that the high frequency swing of the data signal Dout can be outputted correctly.
To speak more simply, the circuit designer must evaluate and analyze the stability of the equalizer 100 and thereafter implement a more complex design to ensure that the equalizer 100 operates correctly. If the equalizer 100 is poorly designed, (for example, the operating time of the swing control module 140 is insufficient to make the amplitudes of the signals at the node A and node B equal to one another), the boost control module 130 cannot correctly perform the feedback control such that the active high-pass filter 130 has incorrect frequency responses and the original data cannot be recovered.
Furthermore, if the frequency bandwidth of the boost control module 130 is lower than the swing control module 140, larger capacities must be utilized in the boost control module 140. This increases the space requirements of the entire circuit and thereby increases the power consumption of the equalizer 100.

Equalizer and related signal equalizing method


An electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages. For adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, there is provided a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip.

1. Field of the Invention
The present invention relates in general to electronic packages and methods of forming thereof, and in particular pertains to an electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages.
In essence, a particular type of electronic package which consists of a PBGA (plastic ball grid array) package, and which is applicable to chip-scale or near-chip-scale applications, and is essentially constituted of a chip mounted on an organic, wire carrier or circuitized substrate the size of which may extend beyond the peripheral dimensions of the semiconductor chip. The foregoing relates to both wire-bond and flip chip packages and wherein in order to protect the semiconductor chip from the deleterious or debilitating effects of the environment, it is generally desirable to form an insulating body about the chip, this body generally being in the form of a molded epoxy material forming an encapsulant. Generally, as is well known in the technology, interfacial stresses which are generated between the encapsulating molded material, such as the epoxy which may be a thermoset plastic resin, and the circuitized substrate or chip carrier, can be quite considerable in magnitude and may result in delamination of the components as a result of exposure to moisture or during thermal cycling. This will adversely affect the reliability and possibly even completely destroy the electrical interconnections of the electronic package and the functional integrity thereof, leading to potentially extensive financial and economic losses. Heretofore, when applying the molded material producing the protective structure encompassing the semiconductor chip and forming the physical bond with the carrier or circuitized substrate on which the chip is positioned, the molded material has been confined to engagement with the surface on the side of the carrier or substrate on which the semiconductor chip is mounted, whereby the opposite or distal side of the carrier, on which there is normally disposed an array of solder balls (BGA""s) is left unencapsulated so as to provide electrical connecting access for the solder balls. Although the encapsulation of the semiconductor chip and the resulting bonding with the circuitized substrate or carrier is effected by a molded compound generally constituted of an epoxy, the tendency in industry, at this time has been a shifting towards the use of mold compounds or bodies forming the encapsulate for the electronic package which has a lower coefficient of thermal expansion (CTE) than heretofore, whereby the interfacial stresses which extend normal to the surface of the carrier or circuitized substrate facing towards the semiconductor chip are reduced in the region extending about the periphery of the semiconductor chip. This, in essence, increases the bending of the electronic semiconductor chip-mounting package and decreases the fatigue life expectancy of the ball grid arrays (BGA). Although the stresses which are generated as a result of bending are ordinarily not a problem to the degree in chip-scale packages as they would be in larger PBGA""s, these stresses must be still minimized due to the effect on BGA fatigue and to enable an increase in their length of service life. The fatigue life of such BGA""s represents a particular problem for chip-scale packages, inasmuch as the solder ball size and the pitch between balls must be decreased in order to be able to provide sufficient numbers of interconnections with the small package size, whereby both of these decreases in pitch and size result in a shorter fatigue life for the structure.
Although the prior art has addressed itself to this problem by providing various improved bonding interconnections between the mold compound or material encapsulating a semiconductor chip and by also concurrently encapsulating the surface and, as required, potentially the peripheral side surfaces of the carrier or circuitized substrate, problems are still encountered in providing an adequate degree of adhesion between the components which will prevent delamination under conditions of bending or thermal cycling This problem has been addressed to some extent in co-pending U.S. patent application Ser. No. 09/430,075, (Attorneys Docket EN998109), in which there are disclosed various embodiments directed to the encapsulation of semiconductor chips or electronic packages with a mold material, such as a thermoset plastic or molded epoxy resin, and wherein the encapsultaing material also encompasses the periphery of the chip-mounting substrate or circuitized carrier and the surface thereof which faces towards the mounted semiconductor chip.
2. Discussion of the Prior Art
A number of publications are disclosed in the technology which concern themselves with the use of an encapsulating material extending about and bonding semiconductor chips to diverse kinds of circuitized substrates or carriers.
Thus, Hiruta U.S. Pat. No. 5,998,861 discloses a semiconductor device with a ball grid array (BGA) wherein an epoxy material provides an encapsulant between a semiconductor chip and the facing surface of a carrier for the ball grid array.
Odashima, et al. U.S. Pat. No. 5,998,243 discloses a method for the manufacturing of semiconductor devices and an apparatus, whereby a resin material forms an encapsulate between a semiconductor chip and a carrier on which the chip is mounted.
Yamada, et al. U.S. Pat. No. 5,864,178 discloses a semiconductor device with an encapsulating material constituting of a curable resin for bonding a flip-chip bonded semiconductor chip to the facing surface structure of a substrate or circuitized carrier body mounting the chip.
Other publications which concern themselves to some extent with various encapsulating materials adapted to be employed in electronic packages are Wang et al., U.S. Pat. No. 5,817,545; Thompson et al., U.S. Pat. No. 5,218,234, and Banerji et al., U.S. Pat. No. 5,203,076.
Although the foregoing publications each deal in different measures or degrees with various aspects in providing apparatus and methods for encapsulating semiconductor chips in order to protect the components of the electronic package against potentially deleterious environmental influences, and by utilizing various suitable encapsulating resins or thermosetting plastic materials, such as molded epoxy compounds or silicones, all of these publications limit the encapsulating interconnections or bonding between the circuitized semiconductor chip and the carrier or substrate in that the adhesion or bonding is only effected between the semiconductor chip and the surface of the substrate facing towards the superimposed semiconductor chip, and, at times as required, extending about the peripheral sides or edges of the substrate.
Accordingly, in order to significantly improve upon the foregoing methods and structure for adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, the present invention provides for a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip, which will counteract any tendency towards delamination between the components of the electronic package, in effect, between the semiconductor chip and the circuitized substrate or carrier; and considerably reduce stresses and strains so as to preserve the reliability of the electronic package.
In particular, in the utilization of transfer molding when encapsulating a semiconductor chip in an electronic package, such as a PBGA package, heretofore the mold material has been confined to the side of the carrier or substrate on which the chip is mounted, with the opposite or distal side of the carrier on which there is disposed an array of solder balls (BGA) being left exposed and unencapsulated.
In contrast with the foregoing, pursuant to the present invention, the encapsulant, such as a thermoset plastic or molded epoxy, is extended about the peripheral sides of the substrate or circuitized carrier so as to contact and sealingly cover at least the lower edge surface portions of the carrier, preferably a portion of the surface mounting the BGA and perimetrically surrounding the latter. This, as a result, will considerably reduce the generating and intensity of any interfacial stresses on the chip-side of the carrier so as to thereby increase the resistance to delamination during potential exposure to moisture, or due to the effects which are encountered as a result of thermal cycling.
Another feature which can be employed pursuant to the invention is the use of through-holes which are formed in the carrier so as to extend between the opposite surface thereof proximate its peripheral edges, beyond or outwardly the dimensional confines of the semiconductor chip, and wherein these through-holes in the substrate or carrier can also be filled by the encapsulating material, thereby further increasing the degree of adhesion thereof to the carrier. The carrier or substrate edges can also be of scalloped configurations in order to enhance the encapsulating and adhesion action by the encapsulating material, and thereby still further strengthening the interconnection or adhesive bonding between the semiconductor chip and the carrier, and resisting any tendency towards delamination between the components of the electronic package.
In view of the foregoing, inventive aspects, it is also possible that the structure of the electronic package in providing this type of a more comprehensive adhesive encapsulation, reduces the likelihood of delamination between the carrier and the mold compound, thereby enabling a material with a higher coefficient thermal expansion to be employed, whereby bending of the composite structure is reduced as the coefficient of thermal expansion (CTE) of the encapsulating material approaches that of the chip carrier or substrate, typically such as 17 ppm/xc2x0 C.
Accordingly, it is an object of the present invention to provide a novel electronic package which is imparted an enhanced degree of interconnection or bonding between a semiconductor chip and a circutized substrate carrier on which the chip is mounted.
Another object of the present invention is to provide a novel encapsulating arrangement interconnecting a semiconductor chip and a circuitized or substrate or carrier on which the chip is mounted so as to increase the degree of adhesion between these components and to thereby reduce the possibility of delamination taking place therebetween.
A further object of the present invention is to provide an electronic package of the type described wherein an encapsulant, such as a thermosetting plastic, encompasses a semiconductor chip which is positioned on a circuitized substrate, and whereby at least portions of a surface of the substrate facing away from the semiconductor chip, and mounting BGA is encompassed by the encapsulating material so as to further enhance the strength of the package against bending and resulting strains causing delamination between the components of the package.
Another object resides in the provision of a method for forming the electronic package comprising the semiconductor chip and the circuitized substrate having the novel encapsulating structure as described herein.

Molded body for PBGA and chip-scale packages

International Business Machines Corporation


The present Field Effect Real Space Transistor, or FERST, is a four terminal device with S, G, C, and D representing the source, gate, collector, and drain, respectively. The S, G, and D terminals can be likened to those of the MODFET. The collector name is borrowed from other real space transfer devices. Surrounding the entire device is an oxygen implant isolation. The source and drain ohmic contacts penetrate to the 150 .ANG. GaAs channel while the collector ohmic contact does not penetrate due to its position upon an elevated submesa. AlGaAs layers are used as etch stops during processing of the device and a Schottky barrier gate is placed on an undoped layer. Channel carriers are provided by modulation doping the lower barrier of the channel. An Al.sub.0.35 Ga.sub.0.65 As layer on the upper channel side is used as a real space transfer barrier. In operation and under appropriate bias conditions, real space transfer occurs across this upper barrier and into the collector. Voltage is applied to the device between the drain and source which heats up electrons in the channel to an energized state. Field effect control by the gate then adjusts the voltage distribution throughout the device due to both ohmic voltage drops and the variation in channel conductance under the gate.

Heretofore, solid-state devices have been grouped into three categories based on commonality of their physical operation. These three categories are: 1) the "potential effect" in which the adjustment of barrier height controls operation; 2) the "field effect" in which variation of a depletion region controls the operation; and 3) the "real space transfer effect" in which carriers are energized, or heated, and transferred over a physical barrier. The common bipolar junction transistor, BJT, and field effect transistor, FET, are common examples of potential effect and field effect device types, respectively.
These types of heterostructure semiconductor devices have enjoyed considerable interest in the last several years as candidates for high-speed switches and for transistors that can generate and amplify high frequency electronic signals. One class of these devices (real space transfer) operates on the principle of transfer of hot electrons between two different semiconductor layers separated by a potential barrier, where the temperature of the electrons is controlled by an applied electric field. Because the temperature of these electrons responds very rapidly to the applied field, and because the transit time of these electrons can be very short, such devices offer the promise of very high frequency operation.
These heterostructure devices have evolved from the well-known Gunn diode, which is a monolithic semiconductor structure that also employs a "transferred electron" mechanism. In the Gunn diode, a semiconductor material has a filled valence band and a partially filled conduction band. This conduction band has a central minimum-energy valley of electron states that are occupied up to the Fermi level, and one or more "satellite-valleys" at higher energies that are normally unoccupied. An example of such a material that is used in these devices is GaAs, in which the satellite valley minimum is 360 meV above the central valley minimum. If the GaAs is subjected to an electric field sufficiently large to give some of the conduction electrons more energy than this energy gap, they can be transferred into, and remain in, the satellite valley. Being in a different region of quasi-momentum space (or "k-space"), these satellite valley electrons have a different effective mass, which in GaAs is about 20 times higher than that in the central valley. The corresponding electron mobility is much smaller than that of the central valley electron states. The conductivity of the electrons is therefore reduced by the field, and the material exhibits a negative differential resistance. Semiconductor materials exhibiting such nonlinear behavior can be used to construct electronic oscillators, amplifiers, and switching and storage devices.
The heterostructure devices that are related to the present invention comprise adjacent layers of different semiconductor materials in which the conduction bands of the materials have different mobilities. Instead of transferring electrons into lower mobility states in k-space, the applied electric field causes the conduction electrons in a high-mobility material to become heated and transferred in "real space" into an adjacent material of lower mobility. This means, again, that the conductivity of these electrons is effectively reduced by the applied field, and these heterostructures also exhibit negative differential resistance.
Negative resistance heterostructures have been disclosed in U.S. Pat. No. 4,257,055 (Hess et al.), and are described also in the following articles: "Negative Differential Resistance Through Real-Space Electron Transfer", K. Hess, H. Morkoc, H. Shichijo and B. G. Streetman, Appl. Phys. Lett. 35 (6), Sep. 15, 1979; "Measurements of Hot-Electron Conduction and Real-Space Transfer in GaAs-Al.sub.x Ga.sub.1-x Heterojunction Layers", M. Keever, H. Shichijo, K. Hess, S. Banerjee, L. Witkowski, H. Morkoc, and B. G. Streetman, Appl. Phys. Lett. 38 (1), Jan. 1, 1981; "Fast Switching and Storage in GaAsAl.sub.x Ga.sub.1-x Heterojunction Layers", M. Keever, K. Hess and M. Ludowise, IEEE Electron Device Letters, Vol. EDL-3, No. 10, October 1982. These references all describe semiconductor heterostructures having adjacent alternate layers of high-mobility GaAs and low-mobility Al.sub.x Ga.sub.1-x As. Conduction electrons are supplied by donors in the Al.sub.x Ga.sub.1-x As and migrate to the GaAs layer, which has a smaller band gap and lower scattering. When an electric field is applied in a direction parallel to the interface between the layers, the electrons in the conduction band of the GaAs will be rapidly heated to energies well above their thermal equilibrium value, and acquire sufficient energy to overcome the conduction band discontinuity between the two materials and move back into the Al.sub.x Ga.sub.1-x As layer. This propagation can be described as a kind of thermionic emission. Once these electrons reach the low-mobility layer, their conductivity is reduced and the heterostructure displays the negative differential resistance described above.
The above references describe the basic principles of real space electron transfer and their application to switching and storage devices. These principles are well understood for the most part, although some of the details have yet to be elucidated, such as the precise physical location at which the electrons transfer. Interest has been growing in the application of these principles in order to design transistors that can amplify and generate high frequency signals.
One transistor design based on these principles is described in the article "Charge Injection Transistor Based on Real-Space Hot-Electron Transfer", S. Luryi, A. Katalsky, A. Gossard and R. Hendel, IEEE Transactions on Electron Devices, Vol. ED-31, No. 6, June 1984. This reference describes a transistor having a conducting n-GaAs substrate that acts as the collector of the device. Over this substrate, an undoped Al.sub.x Ga.sub.1-x As barrier layer is grown, then an undoped GaAs channel layer, and a layer of n-Al.sub.0.34 Ga.sub.0.66 As which provides a source of electrons capped by an n-GaAs layer. A source electrode (serving as the "emitter") and a drain electrode ("base") extend downward through the top three layers into, but not through, the barrier layer. A gate electrode is also provided, redefined in the charge injection transistor as a collector due to the large currents which flow making it unlike traditional field effect controlled gates. This gate allows the device to function in a negative resistance field effect transistor mode (NERFET), as well as a charge injection transistor mode (CHINT). A variation to the original structure which placed the collector on the top side is shown in FIG. 1 with the corresponding band diagram for this device being shown in FIG. 2. This design has inherently less parasitic capacitance and a demonstrated fmax=18 GHz and fT=60 GHz.
In the CHINT mode of operation with a common base (drain) configuration, positive voltages (with respect to the drain) are applied to the source and collector electrodes. The source-drain field causes an electron flow in the channel layer and raises the temperature of these electrons. They are normally confined to the channel layer, until the temperature becomes sufficiently high that they can overcome the barrier layer. The hot electrons are thereby injected by thermionic emission into the barrier layer region and drift to the substrate collector. As the drain voltage increases, the drain current initially rises, and then decreases as the electron temperature exceeds the barrier height and the collector current rises.
The transistor structure described in this Luryi reference has several limitations, however. One problem arises from parasitic leakage, i.e. direct injection of electrons from the source electrode into the collector. Another limitation arises from the delay time caused by the electron time of flight in the channel and barrier. A third limitation arises from the large capacitance between the substrate collector and the source (or drain). A fourth limitation is the low current gain ratio between the input control and output terminals. All of these limitations adversely affect the high frequency performance of this device. An improved version of this transistor structure is described in the article "High-Frequency Amplification and Generation in Charge Injection Devices", A. Katalsky, J. H. Abeles, R. Bhat, W. K. Chan, and M. A. Koza, Appl. Phys. Lett. 48 (1), Jan. 6, 1986. These references report measurements on CHINT devices indicating power gain up to 9.8 GHz and extrapolated current gain up to 29 GHz. These appear to be the upper frequency limits for CHINT devices attained to date.
Due to these limitations, the real space transfer effect has been the least utilized method of operation in solid state devices. For example, in the area of applications, a digital "NORAND" structure was built using real space transfer devices, S. Luryi, P. M. Mensz, M. R. Pinto, P. A. Garbinski, A. Y. Cho, and D. L. Sivco, "Charge Injection Logic," Appl. Phys. Lett., vol. 57, pp. 1787-1789, October 1990. Although conceptually interesting as an attempt to achieve higher functional density, the circuit only had a fanout of one, which, as those skilled in the art will realize, is not very useful for practical circuits. For analog circuits, an A.C. power gain of 20 dB has been demonstrated at 1 GHz; this performance, however, is mediocre when compared with other available FET devices. An oscillator circuit was fabricated using the real space transfer device, described above as a NERFET; however, no unique performance or application was achieved with this device.
Accordingly, real space transfer has remained under utilized for beneficial applications. Although a few application ideas have been demonstrated, their competitiveness with other devices is limited by their maximum demonstrated d.c. current gain of approximately 1.1. Therefore, real space transfer device research has not had success in trying to incorporate this physics into the conventional transistor structure as previous research has sought to do.

The United States of America as represented by the Secretary of the Army


A cast architectural element is provided, including a stone shell having front, end, side and rear walls defining an internal cavity, the rear walls defining a rear opening. A core is disposed in the internal cavity, and at least one attachment clip is provided having a first portion extending from the shell, and a second portion engaged in the core. A layer of mesh is disposed upon the core and the second clip portion, and a settable filler layer is disposed upon the mesh in the rear opening, such that upon setting, the filler retains the clip in position.

The present invention generally relates to cast architectural elements, and more specifically to such elements used as simulated stone blocks for replacing more expensive and heavy solid ornamental stone on building exteriors and interiors.
For reasons of esthetics, lower maintenance and/or fire retardant properties, stone exteriors are preferred. However, due to the relatively high cost of the stone, particularly blocks of granite, marble or even limestone, as well as the technical challenge of handling and securing stone blocks to building substrates, there has been a demand for architectural elements made of simulated or artificial stone. Also, with the current interest in preserving resources, the use of solid stone blocks requires significantly more fuel for transportation due to vehicle weight restrictions. In many cases, cast architectural elements have a facing of relatively expensive pure or composite stone, with backings of less expensive, and typically relatively lighter weight materials.
One such product is a foam core architectural element that is coated to resemble stone and is sold under the trademark ELEGANT STONE™ by L&W Supply of Chicago, Ill. (www.lwsupply.com). As is well known in the art, such products include an exterior surface of ornamental stone, such as limestone, marble, quartz, silica or the like in a cement matrix with aggregate in a castable formulation. Using a known foam casting technique, the element is produced so that the exterior shell is fused to an interior core of expanded polystyrene foam (EPS). The interior core is thus significantly lighter and easier to handle and install than conventional solid stone blocks. Also, this type of architectural element costs a fraction of solid stone.
Conventional cast architectural elements are secured to building exterior or interior substrates using adhesive and/or clamps which are fastened to the building substrate and grip the cast element in a peripheral groove. However, a drawback of such clips is that the installer needs to assemble them on site, and each clip requires multiple components which must be inventoried on site, and are easily misplaced during construction.

Embedded clip attachment for cast architectural element