The present invention discloses a smart driver used in flyback converters adopting a transconductance amplifier to turn on a synchronous rectifier FET, and a comparator to quickly turn off the synchronous rectifier FET.

The majority of notebook power adapters use a flyback converter as shown in FIG. 1. To improve efficiency over diode rectification, most notebook power adapter manufacturers use synchronous rectification (SR). In other words, a synchronous rectifier FET is used to replace diode D on the secondary winding T1 of the transformer T in the flyback converter shown in FIG. 1. A major disadvantage of SR over diode rectification is the higher cost, which is associated with the control signal that needs to be sent across the isolation barrier (the transformer).
Instead of sending the control signal across the isolation barrier, in certain prior art systems, the signal can also be derived from the voltage across the synchronous rectifier FET. One of the issues in doing this is that the voltage signal across the FET is very small compared to the dynamic range (millivolts versus tens of volts). To avoid false triggering, bandwidth is sacrificed. This leads to increased turn-off times, leading to efficiency losses.
Some prior art systems use a transconductance amplifier to slow the turn on of the synchronous rectifier FET, which solves the false triggering problem. However, slow turn-on makes it not useful in continuous conduction mode (CCM) applications. Furthermore, the transconductance amplifier brings a slow turn-off, which causes even more switching losses.
Therefore, there is an unmet need to provide a solution having a much faster turn-off and hence reduced switching losses. Moreover, the solution should be used in any type of flyback converter (CCM, discontinuous conductance mode (DCM), and quasi-resonant).

Driver for a flyback converter using a transconductance amplifier and a comparator


A three-phase, pulse-width-modulated, switching rectifier, with zero-voltage-switching.

1. Field of the Invention
This invention relates to a novel, single stage, isolated, three-phase switching rectifier capable of high switching speeds, and more particularly, to a six-step, zero-voltage-switching rectifier, with power factor correction.
2. Description of the Prior Art
Increasing emphasis on power quality has placed a stronger demand on the performance of ac-dc converters as the front end power processing block of many electronic systems. The requirements often include:
1. unity input power factor; PA1 2. very low harmonic distortion of the input current; PA1 3. transformer isolation between source and load; and PA1 4. high efficiency and high power density.
These requirements are especially critical in high power applications, when three-phase ac-dc converters are usually employed.
Several types of three-phase ac-dc converters have been proposed which satisfy one or more of the above requirements. All of them use some form of high-frequency pulse-width-modulation (PWM) controlled rectification in order to minimize the size and weight of reactive filtering components. The first two requirements are easily met using the conventional six-step PWM technique for control of a three-phase forced-commutated bridge rectifier. Additionally, it provides maximum achievable output dc voltage without any low frequency harmonics, thus minimizing both the input and output filter requirements. Electrical isolation can be efficiently accomplished if the conversion process is divided in two stages: three-phase to high-frequency single-phase, cyclo-conversion and high-frequency ac to dc rectification. A small and efficient high-frequency transformer can then be placed between the two stages.
For an improved power density, higher switching frequencies should be used, but that would decrease efficiency due to the increased switching losses. These losses can be significantly reduced or eliminated if the zero-voltage-switching (ZVS) technique, similar to that used in the ZVS full-bridge (FB) PWM dc-dc converters as described in "Designing a High Frequency Snubberless FET Power Inverter," by Z. D. Fang et al., Proc. of POWERCON 11, D1-4, PP. 1-10, 1984, and "High-Voltage, High-Power, ZVS, Full-Bridge PWM Converter Employing an Active Snubber," by J. A. Sabate et al., IEEE APEC '91 Proc., pp. 158-163, 1991, is implemented.

Zero-voltage-switched, three-phase pulse-width-modulating switching rectifier with power factor correction


Direction control assembly for a material handling car having travel wheels mounted thereon and adapted to operate on parallel rails, the control assembly comprising a ramp assembly adapted to receive and respond to a signal from a computer to direct a next approaching car onto one of a main track and a side track, a sensor upstream of the ramp assembly operative to detect the approach of the car and initiate the signal from the computer to the ramp assembly, a first guide wheel mounted on a first arm extending outwardly from the car on a first side of the car, a second guide wheel mounted on a second arm extending outwardly from the car on a second side of the car, each of the guide wheels being connected to a divert arm pivotally mounted on the car and having mounted thereon a divert wheel, the ramp assembly being adapted in response to the signal to assume a position in which part of the ramp assembly is engageable by one of the guide wheels, causing one of the divert arms to pivot and one of the divert wheels to engage a selected one of the first and second rails, whereby to lock the car to the selected rail, such that the car follows the selected rail into the selected one of the main track and the side track.

1. Field of the Invention
This invention relates to a material handling car and track assembly and is directed more particularly to direction control means for directing the car along a selected one of a plurality of track avenues.
2. Description of Prior Art
A number of mechanisms have been devised for switching of track supported cars between alternative paths. In U.S. Pat. No. 3,626,857, issued Dec. 14, 1971 to A. G. Omar, there is disclosed a pivotally moveable track section which may be moved to place tracks thereon in alignment with a selected distal track section. Omar also discloses another mechanism wherein one of a plurality of selected switch tracks is raised into a gap between a base track and a selected distal track. The plurality of switch tracks is interconnected such that when a selected switch track is raised to fill the aforesaid gap, the remainder of the switch tracks are necessarily held below the level of the gap, so that only one switch track at a time can occupy the gap.
In the U.S Pat. No. 3,847 086, issued Nov. 12, 1974 to Ulf Steenbeck, there is disclosed a suspended railway system in which switch tracks are immoveably disposed with each switch track section having thereon a plurality of paths. Each of the paths is provided with electromagnetic means which guide a car onto a selected path in the switch track section, and thereby onto a selected distal track section.
A U.S. Pat. No. 4,484,526, issued Nov. 27, 1984 to Yukio Uozumi, there is disclosed a switching system in which the car supporting tracks remain immoveable, and a guide rail adapted for guiding guide wheels of the car includes moveable guide rail switch sections which are vertically moveable into and out of active position in the guide rail.
U.S. Pat. No. 3,628,462, issued Dec. 21, 1971, to William J. Holt discloses a track system for suspended vehicles. The system utilizes horizontal guide rollers on a car which engage a vertical surface of a channel structure. Each car is provided with guide rollers on each side of the car. The car is provided with a solenoid which operates armature elements to raise the guide rollers of one side or the other. The guide rollers are disposed on both ends of a single crankarm which is acted upon by the armature elements. The crankarm is pivotally mounted such that when the guide roller on one side is raised to actively engage the channel structure, the other guide roller on the other side is necessarily removed from engagement with the channel structure.

Direction control assembly for a material handling car having pivoted divert aims engaging tracks for guidance in switch area


The application relates to biaryl compounds, pharmaceutical compositions comprising the compounds, and methods of use the compounds for treating cell proliferation disorders.

Signal transduction is any process by which a cell converts one kind of signal or stimulus into another. One class of molecules involved in signal transduction is the kinase family of enzymes.
Protein kinases are a large class of enzymes which catalyze the transfer of the □-phosphate from ATP to the hydroxyl group on the side chain of Ser/Thr or Tyr in proteins and peptides and are intimately involved in the control of various important cell functions, perhaps most notably: signal transduction, differentiation, and proliferation.
Phosphorylation of proteins by kinases is an important mechanism in signal transduction for regulation of enzyme activity. The tyrosine kinases are divided into two groups; those that are cytoplasmic proteins and the transmembrane receptor-linked kinases.
Because kinases are involved in the regulation of a wide variety of normal cellular signal transduction pathways (e.g., cell growth, differentiation, survival, adhesion, migration, etc.), kinases are thought to play a role in a variety of diseases and disorders. Thus, modulation of kinase signaling cascades may be an important way to treat or prevent such diseases and disorders. One promising potential therapeutic use for protein kinase or protein phosphatase inhibitors is as anti-cancer agents.
Small molecule interference with tubulin dynamics has broad and profound effect on a cell. When small molecules bind to tubulin they can interfere with the dynamics of microtubules formed from tubulin, either by stabilizing the formed microtubules so they cannot break down or by preventing new formation of microtubules by polymerization.
The effect of small molecules interfering with tubulin dynamics can manifest in the suppression of the cell's ability to proliferate. Interference by small molecules on tubulin dynamics can force the cell to arrest at the G2/M point in the cell cycle, ceasing mitosis, and triggering apoptosis. This action makes these small molecules efficacious in treating human diseases associated with uncontrolled cell proliferation. Efficacy in treating hyper-proliferative disorders has been proven by compounds such as Paclitaxel (a microtubule stabilizer) and Vinblastin (a tubulin polymerization inhibitor) in human subjects.
Tubulin-targeting small molecules can also affect vascularization of tissue. Several tubulin polymerization inhibitors have been demonstrated to affect the abnormal vascularization of tumors. These effects manifest in, e.g., normalization of the vascular network and cutting off blood flow to cancerous tumors, resulting in necrosis. These vascular effects may also be useful for other disease states resulting from abnormal vascularization, such as ocular myopathy.
There is a need for small molecule compounds that modulate the kinase signaling cascade as well as tubulin dynamics. The present application addresses such need.

This patent is subject to a terminal disclaimer.

Biaryl compositions and methods for modulating a kinase cascade


The present invention provides a connection structure between a printed circuit board and a flexible circuit board that enables the number of assembly steps including steps using soldering to be reduced and enables detachment of the flexible circuit board to be prevented. Printed-side conductive patterns formed on a printed circuit board is connected with flexible-side conductive patterns formed on a flexible circuit board. The connection structure comprises: two printed-side openings provided in the printed-side conductive patterns of the printed circuit board; two flexible-side openings provided in the flexible circuit board to align with the printed-side openings when the flexible-side conductive patterns are brought into contact with the printed-side conductive patterns; a frame having two leg parts that are inserted through the both openings; and an elastic pressing member interposed between the frame and the flexible circuit board. The leg parts are fixed on a bottom surface of the printed circuit board.

1. Field of the Invention
The present invention relates to a connection structure between a printed circuit board and a flexible circuit board, the connection structure connecting printed-side conductive patterns formed on the printed circuit board with flexible-side conductive patterns formed on the flexible circuit board.
2. Description of the Related Art
Japanese Unexamined Utility Model Publication No. 64-9376 (Patent Literature 1) discloses a connector used for connecting printed-side conductive patterns formed on a printed circuit board with flexible-side conductive patterns formed on a flexible circuit board in an electronic device.
The connector is mounted on the printed circuit board and has a connector housing made of an insulating material and terminal pieces that are built in the connector housing and are brought into contact with the printed-side conductive patterns formed on the surface of the printed circuit board when the connector is mounted on the printed circuit board. The flexible circuit board is inserted from a cable guiding window provided in the connector housing, and the flexible-side conductive patterns formed on the flexible circuit board are electrically brought into contact with the terminal pieces.
Other connectors having no component corresponding to the above connector housing are disclosed in Japanese Unexamined Patent Publication No. 10-74566 (Patent Literature 2) and Japanese Unexamined Utility Model Publication No. 04-36779 (Patent Literature 3).
The connector disclosed in Patent Literature 2 has: an elastic pressing member made of an elastic material and used as a press-bonded connection part located between a flexible circuit board and a printed circuit board; a retaining member for elastically deforming the elastic pressing member to exert a pressing force on the press-bonded connection part; and screws for fixing the retaining member to the printed circuit board.
The connector disclosed in Patent Literature 3 has: a connection cover member that is rotatably supported by a printed circuit board and that is attachable to and detachable from flexible-side conductive patterns of a flexible circuit board; an elastic pressing member positioned between the connection cover member and the printed circuit board; and fixation means for fixing the connection cover member to the printed circuit board in the state where the connection cover member is rotated in a direction to printed-side conductive patterns of the printed circuit board.
Patent Literature 1
Japanese Unexamined Utility Model Publication No. 64-9376 (pp. 1, FIG. 11)
Patent Literature 2
Japanese Unexamined Patent Publication No. 10-74566 (pp. 2, FIG. 1)
Patent Literature 3
Japanese Unexamined Utility Model Publication No. 04-36779 (pp. 1, FIG. 1)
However, in the connector disclosed in Patent Literature 1, soldering is employed in the step of mounting the connector to the printed circuit board. Additionally, there is required a step of inserting the flexible circuit board into the connector mounted on the printed circuit board.
In the connector disclosed in Patent Literature 2, there is required a screwing step of fixing the retaining member to the printed circuit board.
In the connector disclosed in Patent Literature 3, when the flexible circuit board is pulled downward, the flexible circuit board is likely to be detached.

Connection structure between printed circuit board and flexible circuit board


An integrated circuit with a scan testing circuit which enables reducing power consumption in normal operation mode is provided. A power-supply controller applies a power-supply voltage to internal and external transmission circuits in scan test mode and stops applying the power supply voltage in normal operation mode. Thus, power consumption associated with operations of the internal and external transmission circuits is eliminated, thereby reducing power consumption in normal operation mode.

1. Field of the Invention
The present invention relates to an electronic circuit and an integrated circuit including a scan testing circuit, and a power consumption reducing method used for the integrated circuit and, in particular, to an electronic circuit and an integrated circuit including a scan testing circuit that are capable of reducing power consumption in normal operation mode other than in scan testing mode, and a power consumption reducing method used for the integrated circuit.
2. Description of the Related Art
LSIs (Large Sale Integrated circuits) comprising multiple flip-flops (FFs) also have an embedded circuit for a scan being carried out as an operation test of the LSIs at manufacturing time. These LSIs are called scan-testable integrated circuits. In scan-based testing, each of the FFs of the LSI enters scan test mode in which the FFs are chained together into a shift register called a scan chain. A test input signal is input to the first-stage FF of the scan chain and a test result signal is output from the last-stage FF. The test result signal output from the last-stage FF is compared with a predetermined expected signal in a scan test device. If they do not match, some of the FFs scan-tested supposed to be faulty and the LSIs should be rejected.
FIGS. 3A to 3C show such a conventional LSI for example. The LSI in these figures has a p-channel MOSFET (Metal Oxide-Semiconductor Field-Effect Transistor, herein after referred to as a "pMOS") 1, an n-channel MOSFET (hereinafter referred to as an "nMOS") 2, a pMOS 3, an nMOS 4, a pMOS 5, an nMOS 6, inverters 7 and 8, a pMOS 9, an nMOS 10, a pMOS 11, an nMOS 12, inverters 13 and 14, a pMOS 15, an nMOS 16, and inverters 17 and 18 as shown in FIG. 3A, and inverters 19 and 20 shown in FIG. 3B, and inverters 21 and 22 shown in FIG. 3C. These elements constitute a scan FF. The whole LSI includes a plurality of FFs, not shown, similar to the scan FFs described above. As shown in the table in FIG. 3D, the LSI enters scan test mode when "1" is input as a mode setting signal (SCANMODE) which is input in SCANMODE terminal shown in FIG. 3C. FIG. 4 shows an operation of the conventional circuit shown in FIG. 3A to 3C. As shown in FIGS. 3D and 4, a scan output signal SCNOutPin (SOUTB) alternately changes in accordance with an input signal. When another mode setting signal (SCANMODE) "0" is input, the LSI switches to normal operation mode. Also in normal operation mode, the scan output signal SOUTB alternately changes in accordance with an input signal, same as in scan test mode.
Referring to FIGS. 3A to 3C, the operation will be described in detail. When the mode setting signal SCNMODE "1" is input, the LSI enters scan test mode. Because input to SCANMODE is "1", a control signal SMCB becomes "0" and another control signal SMCT becomes "1" in the circuit shown in FIG. 3C. As a result, the pMOS 1 and nMOS 2 in the circuit shown in FIG. 3A turn on and the pMOS 3 and nMOS 4 turn off. Since the pMOS 3 and nMOS 4 turn off, a DATA signal is not input in the pMOS 5 and nMOS 6. On the other hand, because the pMOS 1 and nMOS 2 turn on, a SCANDATA signal output from the preceding FF, not shown, is input in pMOS 5 and nMOS 6. The pMOS 5 and nMOS 6 turn on at the trailing edge of a clock CLK and the SCANDATA signal is input in the inverter 7.
At the leading edge of the clock CLK, the pMOS 5 and nMOS 6 turn off and the pMOS 9 and nMOS 10 turn on, and thus a master latch composed of inverters 7 and 8 holds the SCANDATA signal. Since pMOS 11 and nMOS 12 are in the on state, the held SCANDATA is input in the inverter 13 and is also output as a normal operation output signal Q to the outside through the inverter 18. At the trailing edge of the clock CLK, the pMOS 11 and nMOS 12 turn off and the pMOS 15 and nMOS 16 turn on, and thus a slave latch composed of the inverters 13 and 14 holds the SCANDATA. The held SCANDATA is output as a scan output signal SOUTB through the inverter 17 and is provided to the subsequent FF, not shown.
When "0" is input in SCANMODE, the LSI enters normal operation mode. Since the input into SCANMODE is "0", the control signal SMCB in the circuit shown FIG. 3C becomes "1" and the control signal SMCT becomes "0". As a result, the pMOS 1 and nMOS 2 in the circuit shown in FIG. 3A turn off and the pMOS3 and nMOS 4 turn on. Since the pMOS 3 and nMOS 4 are on, the normal operation data "DATA" is input in the subsequent-stage circuit through the pMOS 3 and nMOS4. Thus, the DATA signal is input in place of the SCANDATA signal and subsequently the LSI operates as in scan test mode.
There is a strong demand for reduction of power consumption in LSIs in these years. However, there is a problem with LSIs including a scan testing circuit that the scan testing circuit also operates during normal operation and thus wastes power. More specifically, the scan output signal SOUTB for example is output from the inverter 17 in the LSI described above and shown in FIG. 3A to 3C in normal operation mode as well and therefore power is wasted. To solve the problem, LSIs that deactivate hardware components that are not needed in normal operation mode have been proposed.
For example, there are techniques described in the following documents.
Japanese Patent Laid-Open No. 2001-201542 proposes a technique for reducing power consumption in a scan flip-flop circuit. FIG. 5 shows FIG. 1 of Japanese Patent Laid-Open No. 2001-201542. In the scan flip-flop described in Japanese Patent Laid-Open No. 2001-201542, when an active mode "1" is input as a test enable signal to the circuit shown in FIG. 5 and the circuit enters in scan test mode, a NAND circuit outputs a scan output signal that depends on an input signal. When a non-active mode "0" is input as the test enable signal to the circuit and the circuit enters in normal operation mode, the scan output signal is fixed to "1" regardless of an input signal. Thus, power consumption brought by variations of the scan output signal in normal operation is reduced.
National Publication of International Patent Application No. 2004-536487, which is the published Japanese translation of PCT international publication for International Publication No. WO2002/080368, proposes a technique for reducing power consumption in a buffer circuit. FIGS. 6A and 6B show FIG. 4 of the National Publication of International Patent Application No. 2004-536487. The buffer circuit described in National Publication of International Patent Application No. 2004-536487 has first and second inverters interconnected in series. A pMOS transistor is connected between the first inverter and a power supply potential and an nMOS transistor is connected between the second inverter and a ground potential. The pMos and the nMOS transistors are turned on through a memory cell when the buffer circuit is in use. When the buffer circuit is not in use, they are turned off through the memory cell.
However, these conventional techniques have the following problems.
The technique described in Japanese Patent Laid-Open No. 2001-201542 requires a full-set NAND gate which fixes the scan output signal. Power consumption for driving a full-set gate scale circuit is not small. A NAND gate also consumes not small power and requires current for driving such as operation current and standby current.
The buffer circuit described in National Publication of International Patent Application No. 2004-536487 is intended for reduction of leakage current in a static CMOS circuit. Transistors are added to the buffer circuit and are controlled by using a memory cell. That is, the technique described in National Publication of International Patent Application No. 2004-536487 suites in the buffer circuit because it requires a memory cell. Because of the same reason, the technique does not suite for reducing power consumption of flip-flop with scan testing circuit.
The present invention has been made in view of these circumstances and an object of the present invention is to provide an electronic circuit and an integrated circuit including a scan testing circuit that reduce power consumption in normal operation mode and a power consumption reducing method used for the integrated circuit.

Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit