A condensation chamber and method for condensing a metal connate from a metal rich gaseous mixture. The condensation chamber includes top and sidewall surfaces that together define a central bore. A gas supply is received in the bore, and as the gas begins to cool, a metal connate condensate forms on the surfaces of the condensation chamber. A moveable surface is received in the bore for removing the connate from the surfaces adjacent the bore. To facilitate removal of the connate, the surfaces adjacent the bore are heated to ensure that the connate remains substantially in the liquid state while in the condensation chamber. The moveable surface helps direct the connate into a cooling chamber supported by the condensation chamber. In the cooling chamber, the connate is cooled to a plastic state. The cooled connate may be formed into pellets and stored for later use.

Various types of apparatuses and methods may be used to condense a metal from a gaseous mixture including a vaporized metal constituent. Often, the gas is mixed with an inert gas or liquid carrier. If the inert carrier is a vapor, the mixture may be cooled adiabatically by expanding the mixture through a convergent-divergent nozzle to produce a condensate containing metal particulates. The metal condensate is generally self-discharged from the nozzle. If the carrier is a liquid, the gas may be condensed and dissolved in the liquid carrier and further processed to recover the desired metal constituent.
A system is needed that would ensure that substantially all of the condensate formed during the condensation process is removed or collected from the condensation chamber, thus reducing the amount of material wasted during the process. Additionally, a system is needed that would eliminate the need to mix the gas to be processed with an inert carrier of any nature.

Process of condensing metal in condensation chamber


A method, an apparatus, a storage medium and an electronic device for processing an application of a mobile terminal are provided. The method includes the following acts. It is detected whether the mobile terminal is currently in standby state. All available sensor connection interfaces are traversed in responding to detecting that the mobile terminal is currently in standby state. It is determined whether an application corresponding to each of the available sensor connection interfaces is in accordance with a filtering condition. The application is exited in responding to determining that the application corresponding to each of the available sensor connection interfaces is not in accordance with the filtering condition, and the application is restrained from holding a corresponding sensor connection.

Presently, an intelligent system has been an operating system platform of an intelligent terminal, which has the largest user base. The intelligent terminal is the most common and most important electronic device for many users at present. Various sensors in the intelligent terminal provide hardware foundation for application of diversification. However, non-standard methods for using the sensors, such as not releasing the sensors during standby state, which causes the system to fail to sleep and the sensors to continue to consume power, thus obviously increasing power consumption of the intelligent terminal during standby state.

This patent is subject to a terminal disclaimer.

Method, apparatus and storage medium for processing application of mobile terminal and electronic device

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.

This application is related to Japanese application No. 2000-133752 filed on May 2, 2000, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a process of manufacturing the same. In particular it relates to a semiconductor device of an LDD structure comprising a MOS transistor in which a silicide film is provided at least on a surface of a source/drain region, and a process of manufacturing the same.
2. Description of Related Art
As integration of semiconductor integrated circuits progresses, MOS transistors comprising the circuits are required to be further miniaturized. For example, gate length typically in the order of submicron or half micron tends to become as small as 0.35 xcexcm, 0.25 xcexcm or 0.18 xcexcm.
Smaller gate length is advantageous in high-speed operation. However, it causes short channel effect, reduction of threshold voltage (Vth) and decrease in dielectric strength at a source/drain region. Further, favorable contact holes of minuscule area and low resistance are required.
To inhibit the short channel effect, commonly known is a technique for forming a shallow source/drain region and utilizing an LDD (Lightly Doped Drain) structure. Further, also known is a method of forming a silicide film on the surfaces of a source/drain region and a gate electrode to reduce contact resistance.
However, according to the miniaturization of the gate length, the source/drain region tends to be shallower. For example, in the case where the gate length is 0.50 to 0.35 xcexcm, the depth of the source/drain region is 200 to 150 nm, and in the case where it is 0.25 xcexcm, the depth of the source/drain region is as extremely small as about 80 nm. Accordingly, where the silicide film is formed on such a shallow source/drain region, it is required to reduce an amount of the silicon substrate to be consumed by the formation of the silicide film. If the silicon substrate is consumed in a large amount, the silicide film will penetrate the source/drain region to reach a PN junction and break the PN junction.
For example, it has been reported that, when a cobalt silicide film is formed on the surface of the source/drain region of a transistor, a spike of about 100 nm in length is generated so as to extend along the source/drain region. Thereby leak current at the PN junction of the source/drain region is increased (cf. Conference of the Japan Society of Applied Physics, 1996 Autumn, Summary II, p589).
Accordingly, as shown in FIG. 2, a monocrystalline or polycrystalline silicon layer is selectively and epitaxially grown on a source/drain region 21. Then a titanium film is formed thereon and thermally treated to form a titanium silicide film 23 on the surface of the monocrystalline or polycrystalline silicon layer 22 (cf. Japanese Unexamined Patent Publication No. Hei 10 (1998)-92949). According to this method, silicon can be supplied by the monocrystalline or polycrystalline silicon layer 22 even if the silicon is largely consumed at the formation of the titanium silicide film 23, so that the titanium silicide film 23 is prevented from penetrating the source/drain region 21.
However, by the selective epitaxial growth of the monocrystalline or polycrystalline silicon layer 22 on the source/drain region 21, the monocrystalline or polycrystalline silicon layer 22 is also deposited on sidewall spacers 25 of a gate electrode 24. Therefore the titanium silicide film 23 is also formed on the sidewall spacers 25, which causes short circuit between the source/drain region 21 and the gate electrode 24.
Further, as shown in FIG. 3, there has been proposed a method of forming a source/drain region 33 of sufficient thickness by providing a gate electrode 31 in a recess of a silicon substrate 32 (e.g., see Japanese Unexamined Patent Publication No. Hei 11 (1999)-154749). According to this method, the source/drain region 33 is formed with a sufficient thickness so that penetration of a silicide film 34 through the source/drain region 33 is prevented.
However, in comparison with a MOS transistor formed on a flat silicon substrate, the thus formed transistor increases parasitic capacitance between the gate electrode 31 and the source/drain region 32, which harmfully influences on high-speed operation.
Still further, as shown in FIGS. 4(a) to 4(e), a method has been proposed by, e.g., Japanese Unexamined Patent Publication No. Hei 11 (1999)-40817 in which a LOCOS film 42 is formed on a surface silicon layer 41 of an SOI substrate (FIG. 4(a)), the LOCOS film 42 is etched away (FIG. 4(b)) to thin a channel region 43 (a recessed channel region; FIG. 4(c)), and then a metal film 45 is formed on the entire surface of the substrate (FIG. 4(d)) to form a silicide film 46 (FIG. 4(e)). Since this method utilizes the SOI substrate, the depth of a source/drain region 44 can be controlled by adjusting the thickness of the surface silicon layer 41. Accordingly the source/drain region 44 of relatively large depth can be formed by a common step for forming the source/drain region.
However, when this method is applied to a bulk substrate, diffusion of impurities in the source/drain region due to thermal treatment must be strictly controlled in order to adjust the depth of the source/drain region. Further, an additional step of forming the sidewall spacers on the gate electrode is required for the formation of an LDD region to prevent short channel effect and for the formation of the silicide film to prevent short circuit between the gate electrode and the source/drain region. Moreover, since a common step of forming the LDD region requires a thermal treatment for forming the source/drain region and another thermal treatment for forming the silicide film after ion implantation for forming the LDD region, the resulting LDD region is diffused too much in the lateral direction, which leads to insufficient prevention of the short channel effect.
The present invention has been achieved in view of the above-described problems. An object of the present invention is to provide a highly reliable semiconductor device in which short channel effect and short circuit are effectively inhibited by a relatively easy technique even if the semiconductor device includes an LDD region and a silicide film in the source/drain region, and a process of manufacturing the same.
According to the present invention, provided is a semiconductor device comprising: a gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.
Further, according to the present invention, provided is a process of manufacturing a semiconductor device comprising the steps of: forming a LOCOS oxide film on a semiconductor substrate; partially removing the LOCOS oxide film to form a recess on the semiconductor substrate; burying a gate electrode in the recess through the intervention of a gate insulating film; performing ion implantation using the gate electrode and the remaining LOCOS oxide film as a mask to form a source/drain region; forming a silicide film at least on a surface of the source/drain region; and forming an LDD region in the semiconductor device below both sides of the gate electrode.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

Semiconductor device and process of manufacturing the same


A touch sensing film structure including a touch-sensitive device layer, a water/oxygen barrier layer and a flexible substrate is provided. The touch-sensitive device layer has a first surface and a second surface opposite to the first surface. The water/oxygen barrier layer is formed on the first surface or the second surface or integrated with the touch-sensitive device layer to form a multi-function layer. The flexible substrate can stack with the water/oxygen barrier layer and the touch-sensitive device layer, or stack with the multi-function layer.

Flexible display, having the features of lightweight, portability and rollability, is a focus of the next generation products for display panel manufacturers. In the large-scale production flexing test of flexible display, a bending stress applied to the control element is over the limit, the bending stress may cause the flexible display fail.
In the field of consumer electronic products, touch panels have been widely used in portable electronic products. For the users, the flexible touch display device with tortuosity and bendability will be a technology in the manufacturing of flexible electronic products. When the flexible substrate is in a bending state, a film material receives a stress and deteriorates the electrical properties of the sensing elements. In terms of the flexible touch display device, these changes will make touch detection become abnormal and deteriorate the sensitivity of detection. The flexible substrate used in the flexible display has high water/oxygen penetration rate and is susceptible to high temperature processing. Consequently, the flexible substrate cannot avoid water/oxygen penetrating to the flexible substrate, and the lifespan of the flexible display is affected.

INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE


The present invention provides a positioning method and layout that can be used to dispose robots efficiently in an automobile painting and sealing line. This invention relates to the positioning of robots in an automobile painting line in which a downflow circulatory system is established. The main body of a sealing robot is positioned in a location at which it does not cause a large disruption in the downflow circulation along the side of an automobile body, and a robot for painting the under-surface of the floor of the automobile body is provided therebelow. Sealing and painting of the under-surface are performed in parallel.

The present invention relates to a method and layout for positioning robots in an automobile painting line. More specifically, it relates to a method and layout for positioning robots that makes it possible to halve the total length of an automobile line, especially in a sealing line and a painting line for applying a rust-prevention material on the automobile body.
In a conventional automobile manufacturing line, a number of robots such as spot-welding robots, sealing robots, and painting robots are disposed in series, divided in stages dependent on the work to be done thereby. Dividing the robots into work stages and disposing them in series in this manner has the advantage of making it unnecessary to consider the effects that the operation of each robot will have on the other stages, and it also facilitates tasks such as work management, stage management, and robot control.
The positioning of robots within a painting line for applying a rust-prevention material and chip guard to the hidden reverse under-surface of the floor of an automobile body B together with that of a sealing line for water-proofing the joints of the automobile body B, which is provided after an electrodeposition painting line constructed according to the above design concept, is shown in FIGS. 7 to 15. In these figures, P denotes a painting robot, S denotes a sealing robot, F denotes a hood-operating robot, and G denotes a trunk-operating robot (a robot for opening and closing the luggage compartment of an automobile).
However, if robots are disposed in the above layout to form a manufacturing line, the length of this line is inevitably long, resulting in the following problems:
1. A large area on site is necessary for the factory building in which the robots are disposed. PA0 2. The conveyor facilities will also become longer, making it necessary to increase the conveyor length and the numbers of hangers and dollies correspondingly. PA0 3. The installation and running costs for air conditioning (including temperature, humidity, and cleanliness control) also increase. PA0 4. It is difficult to recycle non-attached paint materials (which are environmental pollutants) and thus a large quantity of sludge processing water is used. PA0 5. The total time required of tasks (work tasks) for each automobile increases. PA0 6. Since most of the problems with automobile manufacturing lines are related to the conveyor facilities, lengthening the manufacturing line will increase the likelihood that the manufacturing line will be halted by problems in the conveyor facilities. PA0 7. When a manufacturing line has been halted, the quality of paint layers in the painting line deteriorates. Lengthening the manufacturing line increases the drawbacks that such deterioration will occur in the paint quality of large number of automobiles.
It should be noted that a previous proposal related to the positioning of robots for an automobile manufacturing line was disclosed in Japanese Laid-Open Patent Publication (KOKAI) No. 6-654. The objective thereof is to implement uniform additional welding for an entire automobile body at a welding station at the initial end of an additional welding (Mashiuchi) line, to prevent the occurrence of welding distortion at the additional welding stage of this automobile manufacturing line. Side frames 110, each having an upper level 111 and a lower level 112, are provided on each side of a welding station 100, as shown in FIG. 16. The additional welding is performed on joint portions between the floor and side panels of an automobile body B by robots 120 which are mounted on the lower levels 112 and are capable of moving towards and away from the sides of the automobile body B, while the additional welding is performed on joint portions between the roof and side panels of the automobile body B by robots 120 which are mounted on the upper levels 111 and are capable of moving towards and away from the sides of the automobile body B. In addition, two suspended robots 140 are mounted fore and aft from a ceiling framework 130 of the welding station 100 in such a manner that they are free to travel horizontally and are capable of moving vertically. These robots 140 are intended to perform the additional welding on joint portions for other structural members of the automobile body B such as the dashboard.
However, a downflow circulatory system is established in such a painting line to prevent flying dust and dirt from attaching to the automobile body B. When a bulky robot body is moved vertically above the automobile body B, a large disruption (turbulence) is caused in the downflow circulation and the resultant dust and dirt is entrained in the airflow and can attach to the layers of paint, leading to deterioration of the paint quality. Similarly, when such a bulky robot body travels toward the automobile body B when in the vicinity of the automobile, the movement of the robot causes a large disruption in the downflow circulation, and the resultant dust and dirt is entrained in the circulation as described above and can attach to the layers of paint, leading to deterioration of the paint quality. For that reason, the robot positioning layout proposed by the above laid-open patent publication cannot be applied as is to a painting or sealing line.

Method of positioning robots in an automobile painting line and positioning layout therefor


The present invention is to provide an Ethernet switch fabric controller requiring output port buffer unit of less capacity while still working with an Ethernet switch to smoothly forward the packet from each input port of the Ethernet switch to an output port corresponding to the packet header at the input port. It is featured by the use of proper number of temporary buffer units each of proper length, and output port buffer unit of proper length.

The present invention relates to a device and method to be applied to a switch fabric controller, particularly applied to an Ethernet switch fabric controller for reducing circuit capacity demand or circuit size.
As shown in FIG. 1, a conventional Ethernet switch fabric controller 10 for controlling the switching operation of an Ethernet switch 20, comprises a plurality of command interpreters 13 each associated with an input port of the Ethernet switch, a read/write server 14, and an output port buffer composed of a plurality of output port buffer units 16. When an input port requests packet forwarding (or switching) to an output port, its packet header will be temporarily saved in the command interpreter 13 waiting for the polling by the Read/Writer Server. The Read/Writer Server periodically checks each command interpreter 13 to decode the packet header therein and forward the packet header to a corresponding output port buffer unit according to the decoding. The Ethernet switch 20 forwards the packet in the input port which has had packet header forwarded to the corresponding output port buffer unit, to the output port which is associated with the corresponding output port buffer unit.
The Read/Writer Server 14 comprises a sequential polling controller for polling each command interpreter 13 to forward the packet header in an input port to a corresponding output port buffer unit indicated by the packet header. The polling operation of an Ethernet switch fabric controller is subject to two requirements: fair and fast. Fair operation means each input port must be polled periodically with the same period or the same frequency while fast operation means Full Line Traffic characterized in that the processing time for a packet header in a Ethernet switch fabric controller shall be no more than 960 ns, in order to eliminate the possibility of Latency Delay longer than 960 ns for a packet forwarding in an Ethernet Switch Fabric controller.
The output port buffer unit is for saving packet header when there are two or more than two packet headers to be forwarded to the same output port, or when a packet header is to be forwarded to an output port which has not yet completed the processing of a packet header already saved therein.
The Ethernet switch forwards the packet in an input port (which had requested a packet switching) to an output port which corresponds to the packet header of the packet in the input port. A packet header is saved in a corresponding output port buffer unit before forwarding (or switching) of its packet is completed or processed. An overflow occurs when the number of input ports requesting packet switching to the same output port is larger than the length of the output port buffer unit. The length of an output port buffer unit means the number of memory units each for saving a packet header corresponding to the output port buffer unit. The simplest way to design the output port buffer unit is to have it composed of N memory units to avoid the overflow, with N equal to the number of input ports. For example, N equals 32 (means that the length of each of 32 output port buffer units is 32) if the number of input ports of the Ethernet switch is 32. The kind of design, however, inevitably results in a large number of logic gates in an Ethernet switch fabric controller, and leads to significantly low capacity utilization rate. For example, such a conventional design requires 32*32=1024 memory units for a system with 32 input ports. A better design is therefore strongly expected.
The length of the output port buffer unit shall be designed so as to minimize the number of logic gates required for an Ethernet switch fabric controller. The Read/Writer Server must be so designed that it can determine and/or control the forwarding operation of each packet header from a input port to an output port.
Definitions
A*B: mathematical product of A and B where A and B are any numbers.
Corresponding output port buffer unit of a packet header: the output port buffer unit with identification code corresponding to a code indicated by the packet header usually for selecting the output port to which the packet containing the packet header shall be forwarded (or switched).
Destination output port buffer unit of a packet header: the output port buffer unit with identification code corresponding to a destination address code indicated by the packet header usually for pointing to the output port to which the packet containing the packet header shall be forwarded (or switched).
Length of a buffer unit (temporary buffer unit or output port buffer unit): number of the buffer unit""s memory units each for saving a packet header.
Memory unit: each memory unit for saving a packet header.
Recognize a packet header: read the code or destination address code indicated by a packet header in order to know the destination output port of the packet header.
Retrieve a packet header from an input port: move a packet header from an input port and decode the packet header to know the destination output port of the packet header.
Objects
An object of the present invention is to provide an Ethernet switch fabric controller requiring output port buffer unit of less capacity (output port buffer unit of length smaller than the number of input ports, for example) while still working with an Ethernet switch to smoothly forward the packet from an input port to an output port.
Another object of the present invention is to provide a method for designing an Ethernet switch fabric controller requiring output port buffer unit of less capacity (output port buffer unit of smaller length) while still working with an Ethernet switch to smoothly forward the packet from an input port to an output port.
A further object of the present invention is to provide an Ethernet switch fabric controller requiring less logic gates while still working with an Ethernet switch to smoothly forward the packet from an input port to an output port.
Another further object of the present invention is to provide a method for designing an Ethernet switch fabric controller composed of circuits of smaller size while still working with an Ethernet switch to smoothly forward the packet from an input port to an output port.
The present invention is characterized in that at least one temporary buffer unit is used to temporarily save a packet header when there""s no available memory unit in the output port buffer unit corresponding to the packet header given that the length of the output port buffer unit is smaller than the number of input ports of the Ethernet switch.
An aspect of the present invention is a device for processing the forwarding of the packet header received by each input port of an Ethernet switch to an output port buffer unit, thereupon the Ethernet switch switches (or forwards) the packet at each input port to an output port according to the packet header in each output port buffer unit. Assume the Ethernet switch comprises M input ports and Q output ports. The device thus suggested by the present invention comprises:
Q output port buffer units each of length N;
J temporary buffer units each of length K, where J and K being integers; and
a processor possibly embodied by a CPU or logic circuit for forwarding the packet header received by the input port to a corresponding output port buffer unit in case the corresponding output port buffer unit is in a first state, the corresponding output port buffer unit is one output port buffer unit corresponding to the packet header, and forwarding, in case the corresponding output port buffer unit is in a second state, the packet header to a corresponding temporary buffer unit which is one temporary buffer unit in a first state, and forwarding the packet header in the temporary buffer unit to the output port buffer unit having at least an available memory unit and corresponding to the packet header of the data packet in the temporary buffer unit. The corresponding output port buffer unit is in the first state when having at least an available memory unit therein, and is in the second state when having no available memory unit therein. The temporary buffer unit is in the first state when having at least an available memory unit therein and having no packet header which is corresponded by any output port buffer unit different from the corresponding output port buffer unit that is an output port buffer unit corresponding to the packet header currently considered for being forwarded to the temporary buffer unit, i.e., a temporary buffer unit is in the first state when having at least an available memory unit therein and each packet header therein is corresponded by the corresponding output port buffer unit (the output port buffer unit which corresponds to the packet header currently considered for being forwarded to the temporary buffer unit).
In the embodiment M is equal to Q, N is smaller than M, J is chosen to equal [(M/N)xe2x88x921], and K is chosen to equal (Mxe2x88x92N), as suggested by the present invention and explained below.
It is reasonable to have a condition that no packet header will be admitted to an input port unless the input port currently has no packet header therein or has completed the processing (forwarding to a proper temporary buffer unit or output port buffer unit) of a packet header previously received, i.e., there are at most 32 packet headers in an Ethernet switch fabric controller if there are 32 input ports in the Ethernet switch working with the Ethernet switch fabric controller, for example.
Let""s first consider the length of the temporary buffer unit. Assume the number of input ports is M and the length of output port buffer unit is N (here N less than M), the worst case is that the destination output port buffer unit (corresponding output port buffer unit) of the packet header in each of the N input ports is the same at one time, resulting in the need of forwarding N packet headers to the destination output port buffer unit and forwarding (Mxe2x88x92N) packet headers to the same temporary buffer unit, leading to the consideration of designing the temporary buffer unit of length (Mxe2x88x92N).
Let""s now consider the number of temporary buffer units for the case that M is divisible by N. In case the number of full output port buffer units (the output port buffer unit with every memory unit therein saving a packet header) at one time is M/N, there""s no need of forwarding any packet header to a temporary buffer unit. Another case is that the number of full output port buffer units is (M/Nxe2x88x921) while there are N requests for entering these (M/Nxe2x88x921) full output port buffer units at the same time (there are N packet headers waiting to be forwarded to these full output port buffer units at the same time), therefore we may choose (M/Nxe2x88x921) as the number of temporary buffer units each of length (Mxe2x88x92N). It can be seen the total number of the memory units, including those [(M/Nxe2x88x921)*(Mxe2x88x92N)] of all temporary buffer units and those M*N of all output port buffer units, is {M*N+[(M/N)xe2x88x921]* (Mxe2x88x92N)}. For an example of 32 input ports and 32 output ports in an Ethernet switch, a feasible configuration suggested by the present invention is that there are 32 output port buffer units each of length N, and [(M/N)xe2x88x921] temporary buffer units each of length (32xe2x88x92N), with N to be selected for minimizing the number of memory units represented by {M*N+[(M/N)xe2x88x921]* (Mxe2x88x92N)}. The selection of N can be easily done by computation, especially by using a computer.
In case M is not divisible by N, let M/N=U+R where U is the largest integer less than the real value of MIN and R is the remainder of M/N (i.e., R is the difference value between the real value of M/N and U. and is obviously less than N), the number of temporary buffer units is Uxe2x88x921+[R/U] where [R/U] is the largest integer less than the real value of R/U, and the total number of memory units required is M*N+(Uxe2x88x921+[R/U])*(Mxe2x88x92N).
It can be easily computed that the relatively smaller number of memory units totally required is 324, 295, 296, 324, and 328 respectively for N=4, N=5, N=6, N=7, N=8 in case M=32. Because the overflow probability of output port buffer for N=8is lower than that N=4, N=5, N=6, and N=7, 8 is selected to be the length of each of the 32 output port buffer units, and the number of temporary buffer units is 3, leading to the need of only 324 of total memory units, reducing 68.36 percent of memory capacity demand compared to the conventional system where 32*32=1024 memory units are required.
The above processor according to the present invention may comprise: a retrieving controller, and a contention resolution controller; the retrieving controller forwards the packet header from the input port to the contention resolution controller, the contention resolution controller checks if the corresponding output port buffer unit is in the first state, and forwards the packet header to the corresponding output port buffer unit in case the corresponding output port buffer unit is in the first state, while forwards the packet header to the corresponding temporary buffer unit after identifying the corresponding temporary buffer unit among the temporary buffer units. For example, a temporary buffer unit in the first state (a temporary buffer unit having at least an empty memory unit therein, and with each packet header saved therein being corresponded by the destination output port buffer unit of the packet header currently considered for being forwarded, i.e., a temporary buffer unit having at least an empty memory unit therein, and with each packet header saved therein having the same destination output port buffer unit as that of the packet header considered for being forwarded, or a temporary buffer unit having at least an empty memory unit therein, and with each packet header saved therein corresponded by an output port buffer unit which corresponds to the packet header currently considered for being forwarded) is identified to be the corresponding temporary buffer unit for the packet header.
The above processor may further comprise a temporary buffer unit controller for checking if the output port buffer unit corresponding to the packet header in the temporary buffer unit has at least an available memory unit, and for forwarding the packet header in the temporary buffer unit to the output port buffer unit which corresponds to the packet header in the temporary buffer unit and has at least an available memory unit.
The above retrieving controller is a sequential polling controller polling each input port cyclically to forward the packet header from the input port to the contention resolution controller.
The above processor further comprises a plurality of command interpreters each associated with one input port, and in a busy state when a packet header is received thereat the associated input port to wait for being forwarded to the contention resolution controller, and wherein the retrieving controller recognizes the busy state to forward the packet header at the associated input port which is in the busy state to the contention resolution controller.
Another aspect of the present invention is a device for processing the forwarding of the packet header received by each input port of an Ethernet switch to an output port buffer unit of length N, the Ethernet switch comprises M input ports and Q output ports, N is less than M, the number of the output port buffer units is L which may or may not be equal to Q, the device comprises:
J temporary buffer units each of length K, where J and K being integers; and
a processor comprising a plurality of P retrieving controllers assigned to respectively correspond to different groups of the input ports, where P being an integer larger than one;
each of the retrieving controllers forwarding the packet header received by the corresponded group of the input ports to the processor, in case the corresponding output port buffer units of the packet headers forwarded by the retrieving controllers to the processor are different from each other, the processor respectively sends the packet headers to the output port buffer units respectively corresponding to the packet headers and having at least an available memory unit, and in case the corresponding output port buffer units of the packet headers forwarded by the retrieving controllers are not different from each other, the processor sends the packet headers having the same corresponding output port buffer units, in the order according to the timestamps representing the time of receiving the packet headers by the input ports, to the same corresponding output port buffer units having at least an available memory unit, while in case the corresponding output port buffer units having no available memory unit, the processor sends the packet headers to the temporary buffer units in a first state after identifying the temporary buffer units in the first state among all the temporary buffer units, the processor sends the packet header in the temporary buffer units to the output port buffer units which respectively correspond to the packet headers in the temporary buffer units and have at least an available memory unit.
The processor according to another aspect of the present invention aforementioned further comprises: a contention resolution controller; and a temporary buffer unit controller; each of the retrieving controllers forwarding the packet headers received by the corresponded group of the input ports to the contention resolution controller, in case the corresponding output port buffer units of the packet headers forwarded by the retrieving controllers are different from each other, the contention resolution controller sends the packet headers to the output port buffer units respectively corresponding to the packet headers and having at least an available memory unit, and in case the corresponding output port buffer units of the packet headers forwarded by the retrieving controllers are not different from each other, the contention resolution controller sends the packet headers having the same corresponding output port buffer unit, in the order according to the timestamps representing the time of receiving the packet headers by the input ports, to the same corresponding output port buffer unit having at least an available memory unit, while in case the corresponding output port buffer unit has no available memory unit, the contention resolution controller sends the packet headers to the temporary buffer unit in the first state after identifying the temporary buffer unit in the first state among the temporary buffer units; the temporary buffer unit controller sends the packet headers in the temporary buffer units to the corresponding output port buffer units (the output port buffer units which respectively correspond to the packet headers in the temporary buffer units) having at least an available memory unit.
An algorithm aspect of the present invention is a process for forwarding the packet header received by each input port of an Ethernet switch to an output port buffer unit of length N, the Ethernet switch comprises M input ports and Q output ports, the number of the output port buffer units is L which may be selected so as to equal Q, the process comprises the steps of:
(a). recognizing the packet header received by the input port (another way is retrieving the packet header from the input port);
(b). identifying the output port buffer unit which corresponds to the packet header as a destination output port buffer unit;
(c). checking if the destination output port buffer unit has at least an available memory unit;
(d). in case there is at least an available memory unit in the destination output port buffer unit, forwarding the packet header from the input port to the destination output port buffer unit;
(e). in case there is no available memory unit in the destination output port buffer unit, forwarding the packet header from the input port to the temporary buffer unit which is in a first state;
(f). whenever one corresponding output port buffer unit, which is one output port buffer unit corresponding to the packet header in the temporary buffer unit, has at least an available memory unit, forwarding the packet header in the temporary buffer unit to the corresponding output port buffer unit.
The above temporary buffer unit is in the first state when having at least an available memory unit and having no packet header therein corresponded by one output port buffer unit different from the destination output port buffer unit.
Another aspect of the above temporary buffer unit is that it is in the first state when having at least an available memory unit therein and the destination output port buffer unit corresponds to each packet header therein.
The above process further comprises a step of computing the J, and the K, so that the J is equal to [(M/N)xe2x88x921], and the K is equal to (Mxe2x88x92N), where N is computed so as to reduce the number of logic gates (memory units) constituting all the output port buffer units and the temporary buffer units, while the process can still avoid the overflow possibly caused by the fact that the length of the output port buffer unit is less than the number M of the input ports.
Another algorithm aspect of the present invention is a process for forwarding the packet header received by each input port of an Ethernet switch to an output port buffer unit of length N, the Ethernet switch comprises M input ports divided into P groups and Q output ports, the N is less than the M, the process comprises the steps of:
(a). simultaneously applying pooling in each of the groups for recognizing, one by one, the packet headers received by the input ports in each of the groups;
(b). identifying destination output port buffer units among the output port buffer units, the destination output port buffer units are the output port buffer units which respectively correspond to the recognized packet headers;
(c). in case the destination output port buffer units are different from each other, respectively sending the recognized packet headers to the destination output port buffer units having at least an available memory unit, and in case the destination output port buffer units are not different from each other, sending the recognized packet headers corresponded by the same destination output port buffer unit, in the order according to the timestamps representing the time of receiving the packet headers by the input ports, to the same the destination output port buffer unit which has at least an available memory unit, while in case the destination output port buffer unit has no available memory unit, sending the packet headers to the temporary buffer units in a first state after identifying the temporary buffer units in the first state among all of the temporary buffer units, the temporary buffer units in the first state are the temporary buffer units which have at least an available memory unit and have the packet headers therein corresponded by the destination output port buffer unit.
(d). sending the packet header in the temporary buffer unit to the destination output port buffer unit (one output port buffer unit which corresponds to the packet header in the temporary buffer unit) having at least an available memory unit.
The above process may also comprise a step of computing the number J of the temporary buffer units, and the length K of each of the temporary buffer units, so that the J is equal to [(M/N)xe2x88x921], and the K is equal to (Mxe2x88x92N), where N is computed so as to minimize the total capacity (number of memory units or logic gates) of all buffer including the temporary buffer units and the output port buffer units, while the process can still avoid the overflow possibly caused by the fact that the length of the output port buffer unit is less than the number M of the input ports.
Another further algorithm aspect of the present invention is a process for forwarding the packet header received by each input port of an Ethernet switch to an output port buffer unit of length N, the Ethernet switch comprises M input ports in P groups and Q output ports, the number L of the output port buffer units may be so selected that the L is equal to the Q, the process comprising the steps of:
(a). simultaneously applying pooling in each of the groups for retrieving, one in one time interval, the packet headers received by the input ports in each of the groups;
(b). identifing destination output port buffer units among the output port buffer units, the destination output port buffer units are the output port buffer units which respectively correspond to the retrieved packet headers;
(c). in case the destination output port buffer units are different from each other, respectively sending the packet headers retrieved from the input ports to the destination output port buffer units having at least an available memory unit, and in case the destination output port buffer units are not different from each other, sending the packet headers which have been retrieved from the input ports and which are corresponded by the same destination output port buffer unit, in the order according to the timestamps representing the time of receiving the packet headers by the input ports, to the same destination output port buffer unit which has at least an available memory unit, while in case the destination output port buffer unit has no available memory unit, sending the packet headers retrieved from the input ports to the temporary buffer units in a first state after identifying the temporary buffer units in the first state among all of the temporary buffer units, the temporary buffer units in the first state are the temporary buffer units which respectively correspond to the retrieved packet headers and have at least an available memory.
(d). sending the packet header in the temporary buffer unit to the destination output port buffer unit (one output port buffer unit which corresponds to the packet header in the temporary buffer unit) having at least an available memory unit.
The another algorithm aspect of the present invention is a process for forwarding the packet header received by each input port of an Ethernet switch to an output port buffer unit of length N, the Ethernet switch comprises M input ports and Q output ports, the number of the output port buffer units may be selected to equal the Q, the process comprises the steps of:
(a). separating (or dividing) M input ports into at least two groups;
(b). simultaneously applying pooling in each of the groups for recognizing, one in one time interval, the packet headers received by the input ports in each of the groups;
(c). identifying destination output port buffer units among the output port buffer units, the destination output port buffer units are the output port buffer units which respectively correspond to the recognized packet headers;
(d). in case the destination output port buffer units are different from each other, respectively sending the recognized packet headers to the destination output port buffer units having at least an available memory unit, and in case the destination output port buffer units are not different from each other, sending the recognized packet headers corresponded by the same destination output port buffer unit, in the order according to the timestamps representing the time of receiving the packet headers by the input ports, to the same the destination output port buffer unit which has at least an available memory unit, while in case the destination output port buffer unit has no available memory unit, sending the packet headers to the temporary buffer units in a first state after identifying the temporary buffer units in the first state among all of the temporary buffer units, the temporary buffer units in the first state are the temporary buffer units which have an available memory unit and have the packet headers therein corresponded by the destination output port buffer unit.
(e). sending the packet header in the temporary buffer unit to the destination output port buffer unit (one output port buffer unit which corresponds to the packet header in the temporary buffer unit) having at least an available memory unit.
Again the above process may also comprise a step of computing the number J of the temporary buffer units, and the length K of each of the temporary buffer units, so that the J is equal to [(M/N)xe2x88x921], and the K is equal to (Mxe2x88x92N), where N is computed so as to minimize the total capacity (number of memory units or logic gates) of all buffer including the temporary buffer units and the output port buffer units, while the process can still avoid the overflow possibly caused by the fact that the length of the output port buffer unit is less than the number M of the input ports.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:

System and method for reducing capacity demand of ethernet switch controller


A solution for determining the accuracy of a speech recognition system. A first graphical user interface (GUI) is provided for selecting a transaction log. The transaction log has at least one entry that specifies a speech recognition text result. A second GUI is also provided for selecting at least one audio segment corresponding to the entry. The second GUI includes an activatable icon for initiating transcription of the audio segment through a reference speech recognition engine to generate a second text result.

1. Technical Field
This invention relates to the field of speech recognition, and more particularly, to determining the accuracy of a speech recognition system.
2. Description of the Related Art
Speech recognition is the process by which an acoustic signal received by microphone is converted to a set of text words, numbers, or symbols by a computer or a microprocessor based device. These recognized words may be used in a variety of computer-based software applications for purposes such as document preparation, data entry, and command and control. Improvements to speech recognition systems provide an important way to enhance user productivity.
Speech recognition systems can model and classify acoustic signals to form acoustic models, which are representations of basic linguistic units referred to as phonemes. Upon receiving and digitizing an acoustic speech signal, the speech recognition system can analyze the digitized speech signal, identify a series of acoustic models corresponding to the speech signal, and derive a list of potential word candidates based upon the identified series of acoustic models. The speech recognition system also can determine a measurement reflecting the degree to which the potential word candidates phonetically match the digitized speech signal.
Speech recognition systems further can analyze the potential word candidates with reference to a contextual model. This analysis can determine a probability that one of the word candidates accurately reflects received speech based upon previously recognized words. The speech recognition system can factor subsequently received words into the probability determination as well. The contextual model, often referred to as a language model, can be developed through an analysis of many hours of human speech. Typically, the development of a language model can be domain specific. For example, a language model can be built reflecting language usage within a telephony context, a legal context, a medical context, or for a general user context.
The accuracy of speech recognition systems can be dependent on a number of factors. One such factor can be the audio environment in which speech is detected. The audio environment can significantly affect the resulting quality of the speech audio signal. User speech obtained from high noise environments, for example automobiles or public places such as where one communicates with a speech recognition system using a public telephone, can include a significant amount of environmental noise. This can lead to poor speech recognition. Further, telephony systems often utilize low quality audio signals to represent speech. The use of low quality audio signals within a voice processing system can exacerbate the aforementioned problem, as a low quality audio channel may result in noise which overpowers the user speech.
Another factor that can significantly affect the accuracy of a speech recognition system is the configuration of the speech recognition system itself. System configuration can be particularly relevant with regard to speech recognition systems which operate in diverse audio environments and/or audio environments having a significant amount of noise.

Graphical user interface for determining speech recognition accuracy

International Business Machines Corporation


Systems, methods, and computer-readable media for intelligent caching of content items are provided. A content item may be received by a caching device from a content provider based at least in part on a first request from a user. The caching device may determine a content viewing profile. The caching device may direct storage of the received content item for later retrieval. Additionally, the caching device may provide the stored content item to the user in response to a second request for the content.

A wide variety of service or content providers, such as cable providers and satellite providers, provide broadband communications services, such as television, movies, video games, music services, and/or other digital content to customers. Many customers utilize set-top boxes to present such content on one or more televisions or display devices within a single location, such as a home. Set-top boxes are typically dedicated devices that are situated within a customer's home, and allow users to schedule programming content for display, recording, and/or storing. However, content providers may have to transmit identical content multiple times to a single location if multiple users within the location request the same content. For example, if the first and second customers request to view the same show at first and second set-top boxes, respectively, the content provider may have to send the identical content to the same home twice. Moreover, interactive programming guides ("IPGs") are often requested from the content provider every few seconds by multiple set-top boxes within the same home. Again, here the content provider may need to transmit multiple IPGs every few seconds to the same location. Accordingly, finding improved ways to provide digital content to customers continues to be a priority.


Disclosed is an anti-spying encrypted keyboard, particularly an anti-spying encrypted keyboard having an anti-spying detection protective system in multiple aspects. The anti-spying encrypted keyboard comprises a key panel and a main control board. The main control board includes a control circuit with self-destruct function. The control circuit is fixedly sealed on the back of the main control board by an anti-spying protective mechanism. The anti-spying protection mechanism is electrically connected with the control circuit. The anti-spying protection mechanism comprises: an anti-spying cover (31) having a bottom surface (311) and a side wall (312) extending perpendicularly along the edge thereof, the side wall (312) together with the bottom surface (311) forming a first cavity (313); a rigid anti-spying circuit board (32) being placed inside the first cavity (313), and a second cavity (326) being formed by a bottom side and a side wall with the circular edge, the bottom side of the second cavity (326) is provided with at least one pair of connecting fingers (3252) for the anti-spying circuit (32); and a conductive adhesive (34) placed inside the second cavity (326) to make the connecting fingers (3252) on the rigid anti-spy circuit board (32) and the connecting fingers (3252) on the control circuit of the main control board connect electrically.

The hard encryption keyboard of a bank self-service equipment bears works of inputting and encrypting a bank password of a user, and thus a working key and a master key of the bank are stored in a core processing part of the keyboard. For an unspeakable purpose, some criminals usually jimmy or poke the keyboard to steal the user password and even to decrypt the working key and master key of the bank in order to steal bank information, which threatens the security of information and money of the user and the bank directly.
The encryption keyboard is generally provided with a poking detection and protection structure and a poking detection and protection circuit. When the keyboard is subjected to a physical poking, the poking detection and protection circuit outputs a self-destruction signal to realize a self-destruction function of the encryption keyboard, so as to prevent the criminals from stealing bank information.
The Chinese patent application CN201489599U discloses an encryption keyboard and a poking detection and protection structure thereof. The disclosed encryption keyboard includes an anti-peeping cover, an anti-peeping cover bracket, a poking detection and protection net and conductive adhesive. The poking detection and protection net is received inside the anti-peeping cover, and is clamped and fixed between the anti-peeping cover and the anti-peeping cover bracket by the anti-peeping cover bracket, and is provided with a plurality of first gold fingers thereon. A main control board in the keyboard is provided with a poking protection circuit provided with a plurality of second gold fingers thereon. The first gold fingers and the second gold fingers are electrically connected via the conductive adhesive. The anti-peeping cover bracket is provided with a cavity at the position corresponding to the first gold fingers, and the conductive adhesive is filled in the cavity.
The above poking detection and protection net is a double-layer flexible circuit board, and the periphery edges thereof is folded such that the poking detection and protection net is formed into a cuboid shape and covers a main control circuit board required to be protected. Thus, there is no gap between the main control circuit board and the exterior, which achieves the anti-poking purpose. An anti-poking detection circuit is provided in the flexible circuit board and is covered with detection wirings by using the maze wiring method. The anti-poking detection circuit is directed onto a surface of the flexible circuit board by a gold finger, and is electrically connected with the control circuit of the main control board for realizing the self-destruction function via the gold finger. When the flexible circuit board is subjected to the physical poking, a self-destruction signal can be output by making short circuit between any two adjacent wirings or breaking any one wiring. Thus, the self-destruction function of the encryption keyboard is realized, and sensitive information is deleted immediately, so as to prevent the criminals from stealing bank information.
This technology has following disadvantages.
First, since the flexible circuit board can only be made with two layers, with an outer layer being ground layer without wiring and an inner layer being maze wiring layer, and the gold fingers at the connection between the flexible circuit board and the protected main control circuit board are relatively thick, the criminals can easily scrape the ground layer and connect the gold fingers at the two ends of the inner layer. In this way, the whole maze wiring layer fails to function by making short circuit between the wirings, and thus loses the protective effect.
Second, Because of the flexibility of the flexible circuit board, the criminals may only tightly press the connection wires between the flexible circuit board and the protected circuit board, and then turn over the other parts of the circuit board to expose the protected circuit and to thereby lose the protective effect.
Therefore, it is very important to provide an encryption keyboard having a multi-directional anti-poking detection and protection system.


Various embodiments include a DC switch for disconnecting a DC line. The switch may include: a power semiconductor switch arranged in a current path of the DC line; a first sensor for measuring the input and output voltages; a second sensor for measuring the current flowing through the DC line; and a controller for the power semiconductor switch. The control device is configured to: switch on the DC switch for a first time period; determine the input voltage present; determine the output voltage present at the end of the first time period; determine the current intensity present at the end of the first time period; and determine an inductance and/or capacitance from the determined values.

Owing to their ability to switch off DC currents rapidly and without an arc arising, it is technically expedient to use semiconductor switches as switches for DC networks. In this case, the semiconductor switch is typically arranged directly in the current path. In the switched-on state, the semiconductor switch therefore accepts the full load current and is permanently switched on during normal operation. If a fault occurs in the network to be protected, the semiconductor switch must be able to switch off said fault.
Two types of load are problematic here, namely capacitive loads with particularly small or particularly large supply line inductances. In DC networks with capacitive loads without relatively large supply line inductances, very high rates of current rise result. If the latter are so high that, for a given switch-off delay of the switch (caused by dead times during the current measurement, switch-off time delay, etc.), the maximum controllable current of the semiconductor switch is exceeded, said semiconductor switch can no longer switch off the fault. The DC switch is destroyed as a consequence. DC switches therefore provide a minimum supply line inductance, which is specified in the data sheet.
DC networks with very large supply line inductances constitute the other extreme. Here the limiting element is not the switch-off delay of the switch, but rather the energy stored in the supply line inductance. For dissipating this energy, DC switches usually have a protective network for overvoltage limiting, here also referred to as a load relieving network. In this case, the energy stored in the supply line inductance is converted, for example into heat (when varistors are used), or stored (for example in capacitors). Since the loading capacity of the load relieving network is limited, usually a maximum supply line inductance is also provided for DC switches.
In real installations, it is often unclear what supply line inductance is installed. As a result, it is also unclear what loading should be expected during switching processes for a switch. The loading can only be established by means of complex measurements on site or by means of short-circuit tests according to the trial and error principle.


A threaded trigger travel adjustment insert to be located in the existing grip screw hole of a lower receiver commonly associated with a rifle or a pistol to connect the hand grip to the receiver. The trigger travel adjustment insert has a trigger contact tip at one end thereof for receipt within the fire control cavity of the lower receiver at which to contact the trigger tang of the weapon. Rotating the threaded trigger travel adjustment insert through the grip screw hole causes the trigger contact tip of the insert to elevate the trigger tang resulting in a corresponding reduction in the overlap between the trigger sear and the hammer sear notch prior to the trigger being pulled. Accordingly, the distance traveled by the trigger through the fire control cavity after the trigger is pulled and released is advantageously shortened to improve trigger predictability and reliably, thereby facilitating improved accuracy.

1. Field of the Invention
This invention relates to a trigger travel adjustment insert to be located in the existing grip screw hole of a lower receiver that is commonly associated with the AR 15, or similar weapons platforms. The trigger travel adjustment insert has a trigger contact tip at one end thereof which is located in contact with the trigger, thereby establishing the home position to which the trigger will return after the trigger has been pulled to fire the weapon. Adjustment of the trigger travel adjustment insert towards the trigger correspondingly reduces the length of the trigger pull required to release the hammer and fire the weapon. The trigger travel adjustment insert facilitates improved shooter accuracy by promoting predictable and reliable hammer release and subsequent discharge of the weapon.
2. Background Art
In the case of a shooter aiming and firing a rifle or a pistol, accuracy is significantly influenced by the predictability of trigger function, specifically in terms of trigger pull distance and the force required by the shooter to actuate the trigger. Once a trigger has been actuated to the point of hammer release, i.e., the break point, the trigger may be released at which time it will travel backwards, at a minimum to the point of trigger reset, at which point the trigger may again be actuated to fire the weapon. Excessive backward travel, beyond the point of trigger reset, is undesirable and only serves to lengthen trigger pull distance and add to inconsistency of trigger function. Under normal conditions, trigger backward travel, beyond the point of trigger reset, is limited either by the full depth of trigger sear engagement into the opposing hammer sear notch or by interference between the trigger tang and the floor of the fire-control cavity, whichever occurs first.
Accordingly, it is desirable to be able to selectively adjust and shorten the length of the trigger pull required to fire the weapon and also limit the backward travel of the trigger once it is released and permitted to travel minimally beyond the point of trigger reset (i.e., the home position) in order to improve both trigger function and shooter accuracy.


A method, apparatus, and system for obtaining a solution from a solid product are disclosed. A solid product is housed in a dispenser. A liquid is introduced into the housing of the dispenser to interact with the solid product to form a solution. To control the concentration of the formed solution, the turbulence of the liquid introduced to the dispenser is controlled and adjusted either manually or on a real time basis to account for varying characteristics of either or both of the solid product and the liquid. The dispenser will adjust the turbulence based on the characteristics to maintain a formed solution within an acceptable range of concentration. The concentrated solution can then be discharged from the dispenser to an end use application.

Dissolution parameters of a solid product into a liquid solution, such as a liquid detergent used for cleaning and sanitizing, change based on the operating parameters of and inputs to the dissolution process. Spraying liquid onto a solid product to dissolve it into a liquid solution is one technique. With this technique, the operating parameters change in part based on characteristics within the dispenser, such as the distance between the solid product and the spray nozzle and the change in the pressure and temperature of the liquid being sprayed onto the solid product. Changes in a nozzle's flow rate, spray pattern, spray angle, and nozzle flow can also affect operating parameters, thereby affecting the chemistry, effectiveness, and efficiency of the concentration of the resulting liquid solution. In addition, dissolution of a solid product by spraying generally requires additional space within the dispenser for the nozzles spray pattern to develop and the basin to collect the dissolved product, which results in a larger dispenser.
Therefore, there exists a need in the art for a dispenser having the capability to adjust the flow scheme or turbulence of a liquid contacting a solid product based on a characteristic of either an uncontrolled parameter or condition, such as an environmental condition or a condition of the solid product to maintain a dispensed solution having a concentration within an acceptable range. There also exists a need to update the turbulence based upon the dispensing concentration.

Controlled dissolution solid product dispenser


The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.

All cellular telephones contain an amplifier for amplifying transmit signal. Because cellular telephones are small in size and preferably contain a single rechargeable battery, the amplifier is preferred to operate with a single polarity power supply. Moreover, it is preferred that the amplifier consumes low power, particularly when the cellular telephones are in a "standby" mode. A cellular telephone is in a "standby mode" when it is able to receive a ring signal indicating an incoming call but cannot send a transmit signal unless it is activated. It is further preferred that the amplifier has high power capability, is durable and can be made at low cost.
Power amplifiers used in cellular phones typically include at least one transistor for signal amplification and a transistor biasing circuit. A known amplifier includes a discrete silicon power transistor such as a silicon bipolar transistor or an enhancement-mode silicon MOSFET, and a transistor biasing circuit which is not monolithically integrated with the power transistor. This amplifier has certain advantages: silicon technology is well understood and well developed; silicon power transistors are readily available; a discrete silicon transistor can be individually optimized for power or efficiency. It however suffers the following drawbacks.
First, as compared with GaAs transistors, silicon transistors are generally slower in speed and have lower power capability. Second, it is difficult to monolithically integrate a silicon power transistor with its biasing circuit, because a silicon integrated circuit ("IC") has large parasitics especially at high frequencies. The large parasitics are caused by the pn junctions used in a silicon ICs for device isolation. In comparison, device isolation in a GaAs IC is typically accomplished by simply forming each device on a mesa on a semi-insulating substrate, which results in lower parasitics.
Further, because of its lower electron mobility and velocity, silicon transistors need to be optimized for power. The optimized transistors generally have structures not compatible for monolithic integration. Consequently, a silicon power transistor used in a power amplifier is normally a discrete device, which results in increased assembly cost and reduced reliability.
GaAs based transistors are more preferable than silicon transistors for use in amplifiers because they provides higher power and are capable of operating at higher frequencies. Moreover, they can be monolithically integrated with a GaAs biasing circuit. Among GaAs field effect transistors ("FETs"), depletion-mode GaAs FETs are most suitable for cellular communications because they provide higher power and operate at higher frequencies than enhancement-mode GaAs FETs.
To bias a depletion-mode GaAs FET at a desired operating point, a negative bias must be applied between the gate and source of the FET. The amplitude of this bias depends on the particular application the amplifier is intended. For a class A amplifier, the FET is biased at one half of its zero-bias saturation current, I.sub.dss ; the FET conducts current for an entire input cycle and consumes power continuously. For a class AB amplifier, however, the depletion-mode FET is biased at one quarter of I.sub.dss so that the FET is "slightly on" when there is no input signal. For a Class B amplifier, which typically include two depletion-mode FETs arranged in a push-pull fashion such that only one of the FETs is turned on during any half cycle of an input sinusoidal RF signal, the two FETs are biased at pinch-off.
In addition to the negative bias, a depletion FET also requires a positive bias between its drain and source. Thus, a depletion-mode FET requires two biases to operate, a positive bias between the drain and source, and a negative bias between the gate and source. For a typical depletion-mode GaAs MESFET, the positive bias required is about 3 to 12 volts, and the negative bias is about -0.5 to -4 volts. To provide the positive and negative biases, one may use two power supplies, one for the positive bias and the other for the negative bias. It is preferred, however, to use only a single polarity power supply.
There are several known power amplifiers which operate with a single polarity power supply. FIG. 1 depicts a self-biased GaAs amplifier containing a depletion mode GaAs FET 10. The drain of the FET is connected to a positive dc voltage supply, +V.sub.DD, through an inductor 15; the source is connected to ground through a resistor 20; the gate is dc biased to ground through an inductor 25. A capacitor 30 is connected in parallel to resistor 20 for providing an ac path from the source to ground. An input ac signal is provided at the gate of the FET.
In this amplifier, resistor 20 operates to establish a negative bias between the gate and the source. More specifically, because the gate is grounded through inductor 25 and the source is at a positive potential which equals to the voltage on resistor 20, the gate is biased at a potential that is negative with respect to the source. The amplitude of the negative bias approximately equals to the voltage on resistor 20.
This self-biased amplifier is not suitable for cellular communications because, under high power and high frequency conditions, the impedance of inductor 25 and capacitor 30 are no longer negligible. As a result, the amplitude of the negative bias is affected by the input signal. Moreover, the source of the FET is required to directly connect to ground for high frequency operations, a topology not available in this amplifier.
An improved self-biased amplifier is described in U.S. Pat. No. 5,374,899 to Griffiths et al. As depicted in FIG. 2, this amplifier includes, in addition to capacitor 20 and resistor 30, a diode 35 connected in parallel to the resistor. With increased input ac signal, the diode becomes more conductive and consequently, the variation of the source voltage is reduced. Although this circuit appears to have improved power and gain operation over the conventional self-biased amplifier, it remains a disadvantage that the source of the FET is not directly connected to ground.
Referring to FIG. 3, another known amplifier uses a portion of the input ac signal rectified by a rectifier 36 to generate a negative bias. The rectifier consists of a diode 37, a resistor 38 and a pair of capacitors. A major drawback of this amplifier is that in order to generate the negative voltage, it consumes a portion of the input RF signal, thus diminishing the already precious RF source signal. Another problem is that the rectifier generates a relatively stable negative voltage only when the input RF signal is an analog signal. When the input RF signal is digital, the amplitude of the negative voltage varies and it depends on the density of transmit data.
U.S. Pat. No. 5,327,583 to Yamada et al. describes generating a negative bias using a clock signal of a microcomputer. As depicted in FIG. 4, the clock signal is provided from a microprocessor (not shown) to a CMOS invertor and then to a circuit 39 which generates a negative voltage.
We believe this circuit has some significant drawbacks. First, due to process variations in fabricating FETs, the zero-bias saturation current of each FET varies slightly from device to device. As a result, circuit 39 appears to require individually tuning in order to provide a precise negative bias, which requires additional manufacturing steps. Second, this amplifier is not power efficient because one half of the clock signal passes through diode 45 to ground. Further, although circuit 39 includes two capacitors to smooth ripples in the negative bias, we believe that certain amount of ripples still exist, which interferes with input ac signal and causes the noise level to increase. It is preferred that the ripples be reduced.
It is therefore an object of the present invention to provide an amplifier having at least one depletion-mode FET and operating with a single polarity power supply;
it is a further object to provide a negative voltage generator within the power amplifier to generate a negative voltage for biasing the FET;
it is still a further object to make the negative voltage generator power efficient, particularly when the amplifier is in a standby mode;
it is still another object to regulate the negative voltage generated by the negative voltage generator to a desired level before providing it to the depletion-mode FET;
it is another object to reduce the ripples in the negative voltage generated by the negative voltage generator;
it is still a further object to regulate the negative voltage generated by the negative voltage generator and to make it insensitive to small variation in the negative voltage; and
it is a further object to make the negative voltage regulator power efficient and particularly when the amplifier is in a stand-by mode.

Amplifier using a single polarity power supply


A keyboard having six keys. Characters are entered in two strokes. That is, the user selects a group including a desired character by the first stroke, and selects the desired character by the second stroke. On the key top, each key has legends of characters corresponding to key layout so that it is intuitively recognizable which keys the respective characters are assigned to after the group is selected. By means of such a keyboard, characters can be entered with the fewer keys. This facilitates key entry by touch typing.

1. Field of the Invention
The invention relates to a character input technology, and more particularly to a technology for entering characters by using a keyboard.
2. Description of the Related Art
Among input devices for issuing predetermined instructions to a computer is a keyboard. In general, a keyboard has a plurality of keys, and a single character is assigned to each of the keys. Such a keyboard is considered to be a direct extension of a typewriter, having at least 26 keys to enter 26 alphabetical characters, for example. When a single character is thus assigned to each single key, the large number of keys makes it difficult to remember the key layout. Touch typing has thus required considerable time to learn. Moreover, the keyboard is large in size and inconvenient to carry. In view of this, there have been proposed keyboards which allow character input with fewer keys (Japanese Patent Laid-Open Publications Nos. Hei 7-200120 and Sho 60-231253).
Recently, with the development of network technologies, the numbers of users who, for example, use emails and access websites are increasing sharply. Even for users who have had nothing to do with keyboards so far, the chances to use keyboards to enter characters are on the increase accordingly. In addition, using a keyboard becomes increasingly inevitable in information society, and there are growing needs for input means that are friendly to all people.


Radiation detection assemblies and related methods, including methods of making radiation detection assemblies and devices, as well as methods of performing radiation detection. A radiation detection assembly includes a radiation detector comprising a scintillator layer and an optically transparent substrate, the detector having a first side and a second side, a first imaging photodetector optically coupled to the first side of the detector, and a second imaging photodetector optically coupled to the second side of the detector, wherein at least one of the photodetectors is a position-sensitive imaging photodetector.

The present invention relates generally to radiation detectors and methods. More specifically, the present invention relates to radiation detection assemblies and methods including a radiation detector having multiple photodetectors optically coupled to at least two sides of the detector so as to allow improved scintillation based radiation detection.
Scintillation spectrometers are widely used in detection and spectroscopy of energetic photons and/or particles (e.g., X-rays and gamma-rays). Such detectors are commonly used, for example, in nuclear and particle physics research, medical imaging, diffraction, non destructive testing, nuclear treaty verification and safeguards, nuclear non-proliferation monitoring, and geological exploration.
A wide variety of scintillators are now available and new scintillator compositions are being developed. Among currently available scintillators, thallium-doped alkali halide scintillators have proven useful and practical in a variety of applications. One example includes thallium doped cesium iodide (CsI(Tl)), which is a highly desired material for a wide variety of medical and industrial applications due to its excellent detection properties, low cost, and easy availability. Having a high conversion efficiency, a rapid initial decay, an emission in the visible range, and cubic structure that allows fabrication into micro-columnar films (see, e.g., U.S. Pat. No. 5,171,996), CsI(Tl) has found use in radiological imaging applications. Furthermore, its high density, high atomic number, and transparency to its own light make CsI(Tl) a material of choice for X-ray and gamma-ray spectroscopy, homeland security applications, and nuclear medicine applications such as intra-operative surgical probes and Single Photon Emission Computed Tomography or SPECT.
Scintillation spectrometry generally comprises a multi-step scheme. Specifically, scintillators work by converting energetic particles such as X-rays, gamma-rays, and the like, into a more easily detectable signal (e.g., visible light). Incident energetic photons are stopped by the scintillator material of the device and, as a result, the scintillator produces light photons mostly in the visible light range that can be detected, e.g., by a suitably placed photodetector. Various possible scintillator detector configurations are known. In general, scintillator based detectors typically include a scintillator material optically coupled to a photodetector. In many instances, scintillator material is incorporated into a radiation detection device by first depositing the scintillator material on a suitable substrate. A suitable substrate can include a photodetector or a portion thereof, or a separate scintillator panel is fabricated by depositing scintillator on a passive substrate, which is then incorporated into a detection device.
Improving performance of scintillator detectors is generally of great interest, for example, in order to make scintillation based detectors more useful and capable of filling existing and emerging technical needs. One important performance consideration of particular interest in scintillator detector utilization is light output. More light leads to a higher signal-to-noise ratio (SNR) and, therefore, improved time resolution and higher energy resolution. Thus, increasing light output leads to improved detection power, performance, and overall utility of scintillators.
Generating an increase in light output is currently accomplished by increasing light output from one side of the detector. For example, when a scintillator is formed on an opaque substrate, a known way to improve light output is to deposit a reflective coating on the substrate prior to deposition of the scintillator. Although efficacious in increasing light output from the scintillator surface opposed to the substrate, the process is inefficient for several reasons. First, light needs to travel through the scintillator for an additional distance equal to the thickness of the scintillator plus a fraction (between 0 and 1) of the scintillator thickness. As a result of the increase travel distance, light is lost due, for example, to scattering and absorption in the process. Second, the reflectors themselves are inefficient and do not necessarily reflect all of the light photons in the desired direction. Photons are often reflected into another portion of the scintillator (e.g., neighboring microcolumns), are reflected to a place where they are absorbed, or can be absorbed directly by the reflector.
Thus, there is a need for improved techniques and methods, as well as detection assemblies, for increasing light output of scintillation detectors.

Two-sided scintillation detectors and related methods


A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability.

Embodiments of the present disclosure generally relate to error correction codes for encoding and decoding data, and more particularly to selecting error correction codes based on data size attributes.
A namespace may be distributed across one or more dies (e.g., NAND dies) of a memory device, as well as across multiple memory devices. Data written/read by a host is typically addressed to a logical block address (LBA) in a namespace, and accompanied by metadata related to the LBA. Although the total size of the LBA and related metadata may be fixed from the perspective of the host, the field sizes within the metadata may vary.
Typically, the internal variance of host metadata size is normalized by padding the data to achieve an expected total data size. This padding results in unused space that could be repurposed to increase the performance of a data storage device.
What is needed are systems and methods to utilize bytes that the prior approaches would allocate to padding in useful ways to increase the performance of a data storage device.

Optimizations for variable sector size in storage device namespaces


A method for harmonizing an equipment relative to a vehicle, such as a helicopter, based upon sensing of gravitational and magnetic fields in a number of reference systems. The equipment is installed fixedly on board the vehicle which, relative to a first absolute reference system (RM), has an orientation defined by a second reference system (R2) tied to the vehicle. The equipment is subjected to the earth's gravitational field represented by a gravity vector g oriented along its gradient, as well as to the earth's magnetic field represented by a vector H oriented along its gradient. The orientation of the equipment is defined, relative to the first absolute reference system (RM), by a third reference system (R3). The equipment includes a device for measuring the components of the gravity vector g, fixed to the equipment (2), and the vehicle carries a computer; a memory associated with the computer; an equipment magnetometer, fixed to the vehicle, whose orientation, relative to the first absolute reference system (RM), is referenced by a fourth reference system (R4); and a link connecting the equipment and the equipment magnetometer to the computer and to the memory. The gravitational and magnetic fields are measured when the vehicle is in a number of different orientations, and the equipment is harmonized to the vehicle based thereon.

The present invention relates to a method, and a system employing same, enabling one or more equipments set up on board a vehicle to be harmonized in a self-contained manner. In particular, and in a non-limiting manner, the invention applies to aircraft.
It is known that certain equipments loaded on board a vehicle must have a fixed orientation relative to the latter; this is the case in particular for inertial navigation instruments, detection instruments and armaments systems. The collection of these equipments must operate using common reference axes, which requires an initial setting of each of their reference axes. To do this, a reference trihedral is defined for the vehicle, which serves as basis of reference for the orientation of reference trihedrals relating to the various equipments. Such a setting operation is called harmonization or alignment.
Various procedures are known for carrying out this operation.
A first procedure consists in mounting the equipment to be harmonized on a rack comprising a fixed part, integral with the vehicle, and an adjustable part integral with the equipment, the position of this equipment being referenced by optical sighting and modified by reference to another optical measurement appertaining to an already harmonized reference system. This procedure customarily serves for the harmonization of the inertial modules mounted on board aircraft.
Such a procedure is fairly tricky to implement since it requires sighting means external to the vehicle, and, furthermore, it necessitates being able optically to access the equipments to be harmonized, this being a significant constraint in the choice of their location.
This procedure determines the harmonization error angles for each equipment and requires them to be corrected later by a mechanical rotation. By virtue of this, it is lengthy and tricky to implement.
Another procedure consists in using fitment planes produced with the desired accuracy and harmonized, This requires accurately positioning an appliance relative to the vehicle and later making it carry out an accurate machining of the fitment plane, which is thus harmonized. This fitment plane later receives two accurately machined centering pins on which the equipment will be mounted.
This procedure, which uses successive transfers of accuracy of mechanical positioning, is awkward to implement. In particular, it requires as many fitment planes as there are equipments to be installed, and the latter must also have available accurately machined fixing means, this raising the cost.
A more sophisticated procedure, following French Patent 2 610 101, consists in arranging the equipment in a fixed rack and in determining the harmonization error by comparing between an appliance, serving as reference to define the axes of the vehicle, and another appliance temporarily substituted for the equipment to be harmonized. The harmonization error, which is stored in the memory of a computer of the vehicle, serves subsequently for the latter to correct, through calculation, the values output by the equipment. The latter must clearly have an accurate fixing device which is a copy of that of the appliance which has been substituted.
This procedure thus avoids mechanical adjustments, but requires, however, a reproducibility of the fixing means, as well as measurements by optical sighting.
For its part, the U.S. Pat. No. 4,134,681 describes a harmonization procedure using two laser beams, the orientation of each of which is detected by two equipments which define the components of these beams in their characteristic trihedral. A computer receives these data and has available sufficient equations to determine the three angles of error between these two equipments. Since one of these equipments is already harmonized, the calculated error in angle is thus the harmonization error of the other equipment.
Such a procedure thus avoids a mechanical adjustment since the computer will be capable of correcting, through calculation, the data provided by the equipment which is not mechanically harmonized. However, it requires optical measurements and therefore imposes constraints as regards the positioning of the equipments.

Method and self-contained system for harmonizing equipments on board a vehicle, using means of measuring the earth's gravitational and magnetic fields

Societe Nationale Industrielle et Aerospatiale


To provide an image processing apparatus, an image processing method and a program that can decrease the frequency at which the object is externally referenced at the time of drawing and improve the drawing efficiency by suitably adjusting the bandwidth so that each element block of a structured document data may be included in one band. Therefore, the image processing apparatus scans the page of the structured document data in dividing the structured document data having plural element blocks into plural bands. The number of element blocks where an object to be externally referenced on the scanned line is arranged is detected. And the line at which the detected number of element blocks is decrease is set up as a divided line of the structured document data.

Conventionally, when digital contents such as an HTML file distributed by using data communications through the digital data broadcasting or the Internet is printed by the printer, the layout information of one page is divided into plural bands. A drawing process for each band is performed. That is, a rendering process for converting an object included in each band into the drawing data is performed.
This is because a printer having insufficient memory capacity can not hold the drawing data of one page at any time. In this case, it is required to perform a process for converting the object included in the area of band to be drawn into the drawing data by referring to the object from the printer side (external reference process). In such an external reference process, the printer analyzes the contents described in the input HTML file, and acquires an address at which the object such as image data is actually stored. And it accesses a device corresponding to the address and acquires the object such as image data.
Therefore, when the same object covers plural bands, the printer is required to make the external reference to the same object many times, every time the drawing process for each band is performed. Consequently, the print processing time is longer, and the drawing efficiency is worse.
On the contrary, there is a technology in which the band height is temporarily decided to set an initial value for every band sequentially, the total sum of object drawing areas within the height is calculated, and the band height is adjusted to be a preset threshold or less sequentially (U.S. Pat. No. 6,542,255).
However, the above-mentioned technology of U.S. Pat. No. 6,542,255 does not decrease the frequency at which the object is externally referenced. In this prior technical document, a technology is disclosed in which it is judged whether or not a figure takes long time for processing, and for the figure that takes long time for processing, a band of the minimum height containing its drawing range is set to improve the processing efficiency. However, with the constitution of achieving the technology concerned, it is not possible to decrease the frequency at which the object is externally referenced, because the object of graphic or text to be processed relatively simply may continue to extend over plural bands.
For instance, in the case of analyzing a structured document data and dividing the layout information of one page obtained into plural bands to make the drawing, if an object extending over plural bands appears, not only the band dividing process becomes complex, but also the drawing efficiency is lower because external reference to the same object occurs every time. Especially when the address of the object is one of an external apparatus via a network, for example, the Internet, the drawing efficiency is remarkably worse.
Generally, in the digital television, and recently the portable equipment such as a cellular phone or a digital camera, the digital contents described in a markup language are often handled. However, the hardware resources are limited for the small portable equipment as mentioned above. Therefore, a rendering process of digital contents described in the markup language, especially the rendering process that draws the intermediate data already laid out becomes a large load on the hardware resources in the portable equipment. Accordingly, it is necessary to decrease the frequency at which the object is externally referenced, even for the object such as graphic or text that is relatively simply processed.
This invention has been achieved in the light of the above-mentioned circumstances, and it is an object of the invention to provide an image processing apparatus, an image processing method and a program that can decrease the frequency at which the object is externally referenced at the time of drawing and improve the drawing efficiency by suitably adjusting the bandwidth so that each element block of a structured document data may be included in one band.

Image processing apparatus, image processing method and program