A semiconductor device generates battery state information including information of a capacity that can be extracted from a battery in the case of discharging from a full charge state until a discharge cutoff voltage at a predetermined discharge rate, based on measurement results of battery voltage, current, and temperature. The device calculates a first estimate value of capacity that can be extracted in the case of discharging the battery from the full charge state until the discharge cutoff voltage and calculates a second estimate value of capacity that can be extracted in the case of discharging the battery until a voltage larger than the discharge cutoff voltage. The device corrects the first estimate value based on a difference between a capacity value extracted from the battery by discharging the battery from the full charge state until the voltage larger than the discharge cutoff voltage and the second estimate value.

The present invention relates to a semiconductor device, a battery pack, and an electronic device, and particularly to a technique effectively applied to a semiconductor device for monitoring the state of a secondary battery.
It is necessary to inform a user of information indicating a battery state in the case of using a secondary battery as a power source for an electronic device such as a notebook computer. The information indicating the battery state includes information (Full Charge Capacity: FCC) indicating a capacity that can be extracted from the secondary battery in the case of discharging the secondary battery from a full charge state until a discharge cutoff voltage at a predetermined discharge rate, information (Remaining Capacity: RC) indicating the remaining capacity of the battery, and information (State of Charge: SOC) indicating the charge state of the battery. Accordingly, the electronic device incorporates the secondary battery and a state detection circuit for detecting the state of the secondary battery and outputting it to the outside, and the state information of the secondary battery detected by the state detection circuit is displayed on a display device such as an LCD (Liquid Crystal Display) and is used to determine whether or not to restrict the use of the secondary battery. For example, the following Patent Documents 1 and 2 disclose related arts for detecting the state of the battery.
Japanese Unexamined Patent Publication No. 2006-177764 (Patent Document 1) discloses a learning capacity correction method of a battery for, at the time of fully charging the battery from a predetermined charge start remaining capacity, detecting a charge capacity from the charge start remaining capacity to the full charge capacity, detecting an addition capacity obtained by adding the detected charge capacity to the charge start remaining capacity, comparing the detected addition capacity with the previous learning capacity, and using the addition capacity as the learning capacity if the difference between the addition capacity and the learning capacity exceeds a set error.
Japanese Unexamined Patent Publication No. Hei 5 (1993)-87896 (Patent Document 2) discloses a battery remaining-capacity detection/correction method in which there is provided a battery remaining-capacity correction unit for correcting a battery remaining-capacity calculation value obtained from a cumulative value of a consumption current from the battery based on an actual battery remaining capacity at a plurality of predetermined voltages of the battery, and there is displayed a value obtained by subtracting the cumulative value of the consumption current from the battery remaining-capacity calculation value corrected by the battery remaining-capacity correction unit based on the predetermined voltages.

Semiconductor device, battery pack, and electronic device


A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventional TFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects.

An integrated circuit has been developed, which uses a semiconductor substrate so-called a silicon-on-insulator (hereinafter also referred to as an SOI) that has a thin single crystal semiconductor layer over an insulating surface, as an alternative to a silicon wafer that is manufactured by thinly slicing an ingot of a single crystal semiconductor. The integrated circuit using the SOI substrate attracts much attention because the use of the SOI substrate enables the reduction of parasitic capacitance between a drain of a transistor and the substrate, which contributes to the improvement in performance of a semiconductor integrated circuit.
There are various methods for manufacturing an SOI substrate, and Smart Cut (registered trademark) is known as a method which allows easy production (high throughput) of SOI substrate having a SOI layer with high quality. The SOI substrate is formed in the following manner: hydrogen ions are implanted into a base wafer which is to be a base of a silicon layer, and the resulting wafer is bonded to another wafer (a bond wafer) at room temperature. A strong bond can be formed between the base wafer and the bond wafer even at room temperature due to van der Waals force. The base wafer bonded to the bond wafer is subjected to heat treatment at a temperature of about 500° C., and a silicon layer is separated from the base wafer utilizing a layer to which the hydrogen ions are implanted as a boundary.
As a method for forming a single crystal silicon thin film obtained by utilizing Smart Cut (registered trademark) over a crystallized glass, which is a high heat resistant glass, a method invented by the applicant of the present invention is known (Patent Document 1: Japanese Published Patent Application No. H11-163363).
Further, a thin film transistor which is included in a driving circuit and a control circuit of a display, such as a liquid crystal display and an organic EL display, is formed of an amorphous silicon film, a polycrystalline silicon film, or the like which is formed over a glass substrate. In recent years, demand for higher definition or higher speed driving of the display has been increased. Therefore, many attempts have been made to form a single crystal silicon film with higher carrier mobility over a glass substrate.
With recent increase in the size of a screen and improvement of productivity by increasing the number of panels obtained from one substrate, the size of mother glass has been increased. For example, although practice application has not been made, a mother glass whose size is 2850 mm×3050 mm (so-called tenth generation) is known as the largest mother glass at the present time.
On the other hand, the largest size of a silicon wafer is 300 mm in diameter. Therefore, in order to form an SOI layer throughout a surface of a large glass substrate a plurality of silicon wafers is required to be bonded. In this case, it is difficult to manufacture a large SOI substrate over the large glass substrate without the formation of a joint portion (gap) between adjacent SOI layers.

Semiconductor Energy Laboratory Co., Ltd.


A low-voltage detection circuit detects a low voltage using a voltage follower type operational amplifier and an A/D converter instead of a conventional low-voltage detection circuit. That is, a reference voltage is applied from a reference voltage generating circuit to the A/D converter through the voltage follower type operational amplifier. The voltage follower type operational amplifier is used to reduce output impedance. The power supply voltage can be detected by a converted value (a digital value) from the A/D converter since the reference voltage is independent of the power supply voltage and the converted value varies depending on the power supply voltage. The converted value (the digital value) from the A/D converter is set in a register and statuses of a microcomputer are set as in the conventional art, using the converted value as a flag.

1. Field of the Invention
This invention relates to a low-voltage detection circuit to detect reduction in a power supply voltage that is supplied to a semiconductor integrated circuit.
2. Description of the Related Art
A microcomputer conventionally incorporates a low-voltage detection reset circuit that detects reduction in the power supply voltage and generates a reset signal and a low-voltage detection circuit to detect the reduction in the power supply voltage in advance of the generation of the reset signal in order to set various statuses of the microcomputer.
FIG. 5 is a circuit diagram of such a low-voltage detection circuit. A programmable low-voltage detection circuit 10 is provided with a first comparator circuit 11 and a first detection level setting circuit 13 capable of variably setting a first detection level that corresponds to the power supply voltage Vdd. A reference voltage Vref (1.0 V−1.5 V) that is independent of the power supply voltage Vdd is applied from a reference voltage generating circuit 14 to a positive terminal (+) of the first comparator circuit 11. The first detection level is applied from the first detection level setting circuit 13 to a negative terminal (−) of the first comparator circuit 11. The reference voltage generating circuit 14 can be made of a so-called band gap type reference voltage generating circuit.
The first detection level from the first detection level setting circuit 13 can be set at any of 2n levels corresponding to n bits of control signals from a register 15. Control data is set in the register 15 through bus lines 16 of the microcomputer. If the first detection level is set so as to be the reference voltage Vref when the power supply voltage Vdd is 2.5 V, for example, the first comparator circuit 11 outputs a reset signal of a high level when the power supply voltage Vdd drops to 2.5 V or below. The microcomputer is reset by the reset signal.
A low-voltage detection circuit 20 is provided with a second comparator circuit 21 and a second detection level setting circuit 22 capable of variably setting a second detection level that corresponds to the power supply voltage Vdd. The reference voltage Vref is applied from the reference voltage generating circuit 14 to a positive terminal (+) of the second comparator circuit 21. The second detection level is applied from the second detection level setting circuit 22 to a negative terminal (−) of the second comparator circuit 21. The second detection level set by the second detection level setting circuit 22 is usually set to be larger than the first detection level set by the first detection level setting circuit 13. An output of the second comparator 21 is inputted to and retained in a register 23 which is connected to the bus lines 16.
With the circuit described above, when the power supply voltage Vdd is reduced so that the second detection level becomes equal to or lower than the reference voltage Vref, the low-voltage detection circuit 20 detects it and sets the register 23. And the statuses of the microcomputer are set using data set in the register 23 as a flag. For example, the microcomputer is set in a HALT mode or data is saved. When the power supply voltage Vdd is farther reduced so that the first detection level becomes equal to or lower than the reference voltage Vref, the programmable low-voltage detection reset circuit 10 generates the reset signal and the microcomputer is reset. Therefore, with the circuit described above, it is made possible that the reduction in the power supply voltage Vdd is detected to set the statuses of the microcomputer in advance of the generation of the reset signal.
With the circuit described above, however, there is a problem that a size of the circuit is increased because the low-voltage detection circuit 20 dedicated to detect the reduction in the power supply voltage Vdd is required.


A flat pack electrolytic capacitor includes an aluminum end cap having an electrolyte fill hole that is sealed with a seal mechanism to preclude electrolyte leakage under normal operating conditions. The end cap is welded to an open-ended aluminum case in which a capacitor is inserted and the hole is sealed with an O ring and closed end pop rivet after the case is filled with electrolyte. The O ring is initially compressed during positioning of the rivet and further compressed when the closed end rivet is installed.

This invention relates generally to capacitors and specifically to metal cased electrolytic capacitors having an epoxy sealant.
Flat pack electrolytic capacitors are well known in the art as exemplified by U.S. Pat. No. Des. 353,575, issued Dec. 20, 1994 and assigned to the assignee of the present invention. While the design patent does not indicate the manner of construction of the flat pack capacitor, in practice, an open-ended aluminum case is sealed with a welded end cap that includes an electrolyte fill hole (and connecting leads for the capacitor in the case). Welding the case and cover after installation of the electrolyte often leads to boiling away of the electrolyte with consequent deterioration in the life of the capacitor. Filling the case with electrolyte after welding eliminates the above-mentioned problem, but requires that an elastic plug seal or the like be installed in the fill hole and further that the entire end cap (which is dish-shaped) be filled with an epoxy sealant. The present invention utilizes low cost off-the-shelf parts to provide a seal mechanism for the fill hole to preclude leakage of electrolyte under normal operating conditions. As is common practice vents are provided in the case to permit any gases that may be generated under abnormal operating conditions to be safely vented to the atmosphere. With the invention, the need for the epoxy sealant is obviated. The method of manufacture also lends itself to automation.
In accordance with the invention, an electrolytic flat pack capacitor is constructed by welding an end cap to a case containing the capacitor and filling the case with an electrolyte via a fill hole in the end cap. A seal mechanism is installed in the fill hole, which seal mechanism precludes leakage of electrolyte under normal operating conditions in the preferred embodiment of the invention, the seal mechanism comprises an elastic O ring that is controllably compressed by a closed end pop rivet.

Sealing device for electrolytic capacitor and method


In one embodiment, a router includes a star switching fabric operable to receive a plurality of optical signals each having a wavelength and each associated with a payload received by the router and to communicate from the switching fabric a plurality of substantially similar sets of the optical signals. The router further includes a plurality of tunable filters each having a configuration speed and each associated with a communication path coupled to one of a plurality of destination elements. Each filter is operable to receive one of the sets of optical signals from the switching fabric and to selectively tune to a wavelength of one of the plurality of optical signals received to facilitate communication of at least the payload associated with that optical signal toward the destination element associated with that filter. The router also includes a plurality of line cards operable to facilitate generation of at least some of the optical signals for transmission to the star switching fabric. At least one of the plurality of line cards includes a switching enhancer operable to increase the switching speed of the router without modifying the configuration speed of any of the tunable filters.

As optical systems continue to increase the volume and speed of information communicated, the need for methods and apparatus operable to facilitate high speed optical signal processing also escalates. Information providers make significant investments in communication equipment only to have that equipment become obsolete as the demand for increased bandwidth quickly swamps the equipment's capacity. Information providers, therefore, value enhancements to existing equipment that can extend the viability of that equipment at a fraction of the cost of replacement.
Overview of Various Example Embodiments
The present invention recognizes a need for a method and apparatus operable to efficiently and effectively facilitate high speed optical routing. At least some aspects of this invention facilitate increasing switching speed, thereby increasing system bandwidth, without the need to completely replace existing system infrastructure. Various aspects of the invention can also be applied to new equipment designs, rendering those designs more cost efficient and desirable to information providers.
In one embodiment, a router comprises a star switching fabric operable to receive a plurality of optical signals each having a wavelength and each associated with a payload received by the router and to communicate from the switching fabric a plurality of substantially similar sets of the optical signals. The router further comprises a plurality of tunable filters each having a configuration speed and each associated with a communication path coupled to one of a plurality of destination elements. Each filter is operable to receive one of the sets of optical signals from the switching fabric and to selectively tune to a wavelength of one of the plurality of optical signals received to facilitate communication of at least the payload associated with that optical signal toward the destination element associated with that filter. The router also comprises a plurality of line cards operable to facilitate generation of at least some of the optical signals for transmission to the star switching fabric. At least one of the plurality of line cards comprises a switching enhancer operable to increase the switching speed of the router without modifying the configuration speed of any of the tunable filters.
In one particular embodiment, the switching enhancer comprises an aggregator operable to combine information from a plurality of packets associated with a common output communication path into an aggregated frame.
In another embodiment, the switching enhancer comprises an optical transmitter operable to receive an electrical signal representing a packet received by the line card having an original duration and to generate a packet representing the received packet but having a shortened duration compared to the original duration.
In still another embodiment, the switching enhancer comprises a plurality of tunable filters associated with a single output optical link from the router and operable to receive one of the sets of optical signals from the star switching fabric. At least one of the plurality of tunable filters is operable to reconfigure while another of the plurality of tunable filters processes a signal received from the star switching fabric.
In yet another embodiment, the switching enhancer comprises a plurality of tunable optical transmitters associated with a single input optical link to the router and operable to generate at a selected wavelength one of the optical signals for transmission to the star switching fabric. At least one of the plurality of tunable transmitters is operable to reconfigure without emitting light while another of the tunable transmitters generates a signal for transmission to the star switching fabric.
In still another embodiment, the switching enhancer comprises an express lane associated with at least one of the plurality of filters, wherein the express lane bypasses all of the plurality of line cards.
Any of these switching enhancing enhancements could be combined with any one or more of the other enhancements to further increase the speed of the router.
Depending on the specific features implemented, particular embodiments may exhibit some, none, or all of the following technical advantages. One embodiment provides one or more novel switching enhancing mechanisms in connection with routing optical signals using a star switching fabric.
In some embodiments, associating a plurality of tunable filters with one or more output links from the router provides an advantage of allowing one or more of the plurality of filters to retune to other wavelengths while another of the plurality processes a signal from the switching fabric. Likewise, in these or other embodiments, associating a plurality of tunable filters with a single input port to the router allows one or more of the plurality of transmitters to retune to other wavelengths while another of the plurality of transmitters generates, based on a signal received at the input port, a signal for transmission to the switching fabric at a different wavelength. These techniques hide switching delays that would otherwise occur when waiting for tunable filters and/or transmitters to reconfigure to process another wavelength.
Implementing express channels can provide significant advantages in avoiding unnecessary processing of particular groups of optical signals that require no electronic signal processing. Aggregation of packets within the router reduces the number of switching operations the tunable elements undertake, further increasing the speed of the router. Similarly, reducing the duration of the packets traversing the router helps speed the router's operation.
Some embodiments use tunable lasers and fixed wavelength transmitters. These embodiments provide an advantage of minimizing cost by implementing low cost tunable filters as compared to relatively higher cost tunable lasers. In addition, implementing tunable filters readily facilitates multicast and/or broadcast operation simply by provisioning a plurality of the tunable filters to receive a particular optical router signal communicated from the switching fabric.
Other technical advantages are readily apparent to one of skill in the art from the attached figures, description, and claims.

Optical routing using star switching fabric with reduced effective switching time


A multistage exhaust turbocharger is easily mountable in a narrow engine compartment of a vehicle by simplifying its construction and reducing its bulk. The multistage exhaust turbocharger has a high-pressure stage turbocharger and a low-pressure stage turbocharger. A cover of the high-pressure stage turbocharger has a compressor inlet passage, a bypass inlet passage, a switching aperture between the passages to be opened and closed by a valve body of the compressor bypass valve device, and a bypass outlet pipe part connecting to the bypass inlet passage to introduce bypass air passed through the aperture opened by the bypass valve to the compressor bypass channel which is to be connected to the bypass outlet pipe part.

In recent years, in the field of on-vehicle engines, particularly on-vehicle diesel engines, a multistage (two-stage) exhaust turbo-charging system has been adopted in which a high-pressure stage turbocharger having a high-pressure turbine drivable by exhaust gas from the exhaust manifold of the engine cylinder and a low-pressure stage turbocharger having a low-pressure turbine drivable by exhaust gas from the high-pressure turbine are arranged sequentially in the flow path of the exhaust gas, and supply air for the engine pressurized by a low-pressure compressor of the low-pressure stage turbocharger is supplied via an air supply channel to a high pressure compressor of the high-pressure stage turbocharger to be further pressurized by the high-pressure compressor and charged to the engine.
With an engine equipped with a multistage exhaust turbocharger as mentioned above, stable operation of the engine with high turbo-charging efficiency is attained, by increasing super charge pressure in a low and middle speed operating range of the engine by performing two-stage supercharging by allowing both the high-pressure stage and low-pressure stage turbocharger to operate, and by performing single-stage supercharging in a high speed operating range of the engine by allowing only the low-pressure stage turbocharger to operate by allowing the exhaust gas and supply air to bypass the high-pressure stage turbocharger.
FIG. 9 is a schematic representation of such a two-stage supercharging system as disclosed for example in US 2003/0159442 A1, U.S. Pat. No. 6,378,308 B1, and JP 59-82526.
In FIG. 9, reference numeral 103 is an exhaust manifold, 1 is a high-pressure stage turbocharger having a high-pressure turbine 1a and a high-pressure compressor 1b connected to the turbine 1a by a shaft, 2 is a low-pressure stage turbocharger having a low-pressure turbine 2a and a low-pressure compressor 2b connected to the turbine 2a by a shaft.
Reference numeral 117 is an exhaust bypass valve device for controlling the flow rate of exhaust gas flowing in an exhaust bypass pipe 116, 5 is a compressor bypass valve device for controlling the flow rate of bypassed supply air flowing in a high-pressure compressor bypass pipe 111.
When allowing the engine equipped with the two-stage turbocharger to operate in a two-stage supercharging state by allowing both the high pressure stage and low-pressure stage turbocharger 1 and 2, both the exhaust bypass valve device 117 and compressor bypass valve device 5 are closed.
In this state, the exhaust gas flowing out from the exhaust manifold 103 drives both the high-pressure turbine 1a of the high-pressure stage turbocharger 1 and low-pressure turbine 1b of the low-pressure stage turbocharger 2. On the other hand, supply air pressurized by the low-pressure compressor 2b connected to the low-pressure turbine 2a is further pressurized by the high-pressure compressor 1b connected to the high-pressure turbine 1a, and supplied to each cylinder of the engine as charge air for combustion in the cylinders.
Supercharge pressure can be increased in order to increase charging pressure and output of engine by performing two-stage supercharging like this in a low, middle speed operating range of the engine.
When allowing the engine to operate in a single-stage supercharging state by the low-pressure stage turbocharger 2 in a high-speed operating range by allowing the exhaust gas and supply air to bypass the high-pressure stage turbocharger 1, the compressor bypass valve device 5 is opened and the opening of the exhaust bypass valve device 117 is controlled so that desired pressure of charge air is produced.
Most of the exhaust gas flowing out from the exhaust manifold 103 bypasses the high-pressure turbine 1a and joins with a small portion of the exhaust gas flowed through the high-pressure turbine 1a to drive the low-pressure turbine 2a.
On the other hand, most of the supply air pressurized by the low-pressure compressor 2b connected to the low-pressure turbine 2a bypasses the high-pressure compressor 1b via the high-pressure compressor bypass pipe 111 and joins a small portion of the supply air flowed through the high-pressure compressor 1b to be supplied to each cylinder of the engine as charge air.
In a high speed operating range of the engine, stable operation of the engine with high turbo-charging efficiency is realized by performing single-stage supercharging by the low-pressure stage turbocharger 2 by allowing most of the exhaust gas and supply air to bypass the high-pressure stage turbocharger 1.
A comparatively large installation space is required in the engine room to install an engine equipped with a two-stage exhaust turbocharger of this type because it is inevitably increased in bulk as compared with a single-stage one.
It is required in the case of on-vehicle engine to reduce the bulk of the two-stage exhaust turbocharger as far as possible in order to mount an engine equipped with a two-stage exhaust turbocharger in the conventionally narrow engine room of the vehicle.
However, in engines equipped with a two-stage exhaust turbocharger disclosed in U.S. Pat. No. 6,378,308 B1 and JP 59-82526, particularly an air supply path from a low-pressure compressor 2b to a high-pressure compressor 1b and an air supply bypass path from the low pressure compressor 2b to a compressor bypass valve device 5 on a high-pressure compressor bypass pipe 111 are arranged in a horizontal plane, so the size in the horizontal direction of the two-stage exhaust turbocharger is large, and it is difficult to secure an installation space for mounting the engine in a narrow engine room of a vehicle.
As to the engine equipped with a two-stage exhaust turbocharger disclosed in US 2003/0159442 A1, a high-pressure stage turbocharger 1 and low-pressure stage exhaust turbocharger 2 are arranged three dimensionally in order to make it possible to connect them with exhaust and air supply paths of minimum length and reduce the bulk of the two-stage exhaust turbocharger assembly. However, as the casings of the high-pressure stage and low-pressure stage turbochargers are composed completely separately with exhaust and air supply channels for connecting them being provided, the bulk of the two-stage exhaust turbocharger assembly is still not reduced enough, and it is still not easy to secure an installation space for mounting the engine in a narrow engine room of a vehicle.


Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.

The following description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Electrical devices tend to be more compact, and need to be capable of handling many tasks. Consequently, integrated circuits, especially in computers and smartphones, need to be small and complicated to achieve compactness of the devices with handling of many tasks.
In an integrated circuit, there are many electrical pathways presented and these electrical pathways are layered. Vias or trenches connect circuits on layers and various adjacent layers in an integrated circuit. For example, a via can connect circuits on adjacent layers or distal layers separated by one or more layers in the circuit. As vias and trenches provide conductive connections between layers, the vias and trenches are typically plated with a metal or other appropriate conductor. As integrated circuits are reduced in size to increase capacity, dimensions (e.g., diameter) of the vias and trenches are also reduced, further increasing the difficulty of plating metal in the vias or trenches. For example, as the diameter of surface openings of vias or trenches continue to shrink, metal carrying fluids are prevented from accessing the interior of the via or trench as the surface tension of the fluid is too high. This is problematic as electroless metal plating is preferred as it allows electroless metal to be deposited evenly along edges, inside of holes, and over irregular shaped objects.
U.S. Pat. No. 6,211,073 teaches a coating of a trench using diffusion barriers inside the trench. A diffusion barrier is used and presented inside of the cavity with the thickness of the diffusion barrier between 50 and 100 nanometer. Therefore, this method only works when the thickness of the cavity is greater than 50 nm. In addition, specific expensive machines are required to perform sputtering and jet-vaporing.
All publications identified herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
Thus, there is still a need for coating inside surface of a cavities, especially of a nano-scaled cavities.


The present invention discloses cyclopentane carboxylate compounds. The 1-hydrocarbyl-2-acyloxy-cyclopentane carboxylates according to the invention have a general formula (I):

It has been known to use a Ziegler-Natta catalyst containing a titanium compound and an electron donor compound supported on active magnesium halide in olefin polymerization. U.S. Pat. No. 4,544,717 teaches that stereospecificity of a catalyst can be improved by introducing an electron donor compound into a solid component containing a titanium compound. EP 0 045 977 discloses a polymerization catalyst having higher activity and stereospecificity, wherein phthalates are used as internal electron donor compound, silicone compounds containing at least one Si—OR bond (wherein R represents alkyl) are used as external electron donor compound, and aluminum alkyls are used as cocatalyst.
Many electron donor compounds useful in the preparation of Ziegler-Natta catalysts as well as catalysts for olefin polymerization comprising these electron donor compounds have been disclosed. For example, EP0361493 and EP0728724 disclose 1,3-diether compounds, CN1105671A discloses 1,3-diketone compounds, CN1236372A and CN1292800 discloses specific substituted malonate compounds, WO03022894 discloses diesters of maleic acid as electron donor compound. Additionally, CN1446787A and CN1490340A disclose γ-acyloxy-substituted ether compounds having a formula (III), and catalysts for propylene polymerization and exhibiting excellent performance can be prepared using said compounds as internal electron donor added during the preparation of solid component of catalytic system for olefin polymerization through a preparation process similar to that used in the preparation of N-Catalysts (trade name of polypropylene catalyst by Beijing Research Institute of Chemical Industry, SINOPEC, China).

However, known literatures disclose neither 1-hydrocarbyl-2-acyloxy-cyclopentane carboxylate compounds having a general formula (I) as described hereinafter as well as a process for the preparation thereof nor use of the compounds of the formula (I) as electron donor in the preparation of catalysts for olefin polymerization.

Cyclopentane carboxylate compounds, process and intermediates for preparing the same and use thereof

Abstract: wherein groups R1, R2 and R3, which are identical or different, are independently selected from the group consisting of linear or branched C1-C20alkyl, C3-C20cycloalkyl, C6-C20aryl, C7-C20alkaryl and C7-C20aralkyl. The present invention also discloses a process as well as intermediate compounds for preparing the compounds of formula (I), and use of the compounds (I) as electron donor in the preparation of catalysts for propylene polymerization.


A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Recently, concerning low voltage class power MOSFETs of 100 V or less, development of a power MOSFET having a trench gate (hereinafter, "power MOSFET") is actively pursued aiming at reducing ON-resistance by reducing channel resistance. Various structures have been proposed for such a power MOSFET.
FIG. 21 is a cross-sectional view of components of a conventional power MOSFET. The power MOSFET includes an n− epitaxial layer (hereinafter, "n− epi layer") 52 that is disposed on an n+ drain layer 51 and that is an n− drift layer; a p-channel layer (p-base layer) 53 that is disposed on a surface layer of the n− epi layer 52; an n+ source layer 61 and a p+ contact layer 64 that are disposed in a surface layer of the p-channel layer 53; a trench 57 that passes through the n+ source layer 61 and the p-channel layer 53 to the n− epi layer 52; a gate oxide film 59 that is disposed along an inner wall of the trench 57; a gate electrode 60a that is made of doped poly-silicon and that is embedded in the trench 57 through the gate oxide film 59; an interlayer insulating film 62a that is disposed on the gate electrode 60a and that fills an upper portion of the trench 57; a source electrode 65 that is disposed spanning across the n+ source layer 61, the p+ contact layer 64, and the interlayer insulating film 62a; and a drain electrode 66 that is disposed on a back face of the n+ drain layer 51 (see, e.g., Patent Literature 1 below).
A manufacturing method of the power MOSFET depicted in FIG. 21 will be described. After the p-channel layer 53 is formed, the trench 57 that passes from the p-channel layer 53 to the n− epi layer 52 is formed. The trench 57 is formed by dry etching using an oxide film (hereinafter, "CVD oxide film") formed by chemical vapor deposition (CVD), as a mask. The gate oxide film 59 is formed in the trench 57 and the trench 57 is filled with poly-silicon forming the gate electrode 60a. The position of a surface of the gate electrode 60a is lower than a surface of the p-channel layer 53, a principal surface of the substrate. To form the n+ source layer 61, arsenic (As) ion is obliquely ion-implanted from a side wall of the trench 57 to the p-channel layer 53 using, as a mask, the CVD oxide film that is used to form the gate electrode 60a and the trench 57. Therefore, a diffusion source that forms the n+ source layer 61 is introduced into the side wall of the trench 57. The CVD oxide film is removed. A resist mask that has an opening corresponding to an area to form the p+ contact layer 64 is formed. Using this resist mask, boron (B) ion or boron fluoride (BF2) ion is implanted into a surface of the p-channel layer 53.
The impurity ion introduced into the surface of the p-channel layer 53 is activated by a heat treatment and thereby, the n+ source layer 61 and the p+ contact layer 64 are formed. The n+ source layer 61 is formed by a diffusion of arsenic having a short diffusion length diffused from the side wall of the trench 57. Therefore, the width (hereinafter, meaning a "lateral diffusion width") w of a surface of the n+ source layer 61 that is exposed to the surface of the p-channel layer 53 becomes narrow. The interlayer insulating film 62a made of Boron Phosphor Silicate Glass (BPSG), etc., is deposited. The interlayer insulating film 62a is etched to the surface of the p-channel layer 53, the principal surface of the substrate. The source electrode 65 in contact with the n+ source layer 61 is formed using a metal such as aluminum (Al). The drain electrode 66 is formed on the posterior surface of the n+ drain layer 51 using a metal such as gold (Au).
A feature of the above manufacturing method is that the n+ source layer 61 is formed by self-alignment using the mask that is used to form the gate electrode 60a and the trench 57. As a result, effects described in (1) to (3) herein are obtained. (1) In forming the n+ source layer 61, any shift of the mask made during the patterning, any tolerance for etching back the gate electrode 60a, etc., do not need to be taken into account. (2) A cell may be downsized because the lateral diffusion width of the n+ source layer 61 can be reduced. (3) Because the n+ source layer 61 is formed using the gate electrode 60a as a mask, an overlapped portion of the gate and the source regions can be reduced and therefore, source-gate parasitic capacity can be reduced.
A method of forming an L-shaped source region by obliquely implanting ion using a resist mask having a narrower width than that of a mask for forming a trench has been proposed as another manufacturing method of a power MOSFET. The ion is implanted into the inside of the trench using a gate electrode as a mask. Therefore, a same effect as that in (3) above is obtained (see, e.g., Patent Literature 2 below).
A method of filling a recess on a gate electrode with a CVD oxide film and poly-silicon (to be oxidized) aiming at securely and stably obtaining a gate electrode layer and a cap insulating layer each having a predetermined thickness has been proposed as another method (see, e.g., Patent Literature 3 below).
A method of forming an n+ source layer by diffusing an impurity into an interlayer insulating film (Inter Layer Dielectrics (ILD)) has been proposed as another method. According to this method, the n+ source layer may be formed evenly along the direction of the thickness of a trench groove. The width of the n+ source layer along the direction of the trench width may be reduced. As a result, reduction of ON-resistance and finer processing can be facilitated (see, e.g., Patent Literature 4 to 6 below).
For electrical contact of a p-channel layer for which trench intervals are finely narrowed, a method of newly forming a trench to cross a gate trench, thereby, bringing a p-channel layer in electrical contact with a source electrode has been proposed as another method (see, e.g., Patent Literature 7 below).
A method of providing a contact of an n+ source layer also for a side wall of a trench has been proposed as another method. According to this method, the contact of the n+ source layer in the device surface portion does not affect contact resistance and therefore, the width of the n+ source layer along the direction of the trench width may be narrow. Therefore, finer processing is enabled (see, e.g., Patent Literature 8 below).
A method of forming a gate region in a two-stage trench to narrow the width of a unit cell that includes a source region and a gate region, aimed at reducing "Ron*A (ON-resistance per unit area)" has been proposed as another method (see, e.g., Patent Literature 9 and 10 below).
A method of forming a p-channel layer after forming a trench has been proposed as another method. According to this method, doping to form the p-channel layer is executed from a side wall of the trench. Thereby, control in forming the p-channel layer with respect to a trench gate electrode portion is improved (see, e.g., Patent Literature 11 below).
A semiconductor apparatus whose insulating layer under a gate electrode embedded in a trench is configured by a multi-layer insulating layer, aiming at reducing gate-drain capacity, has been proposed in, for example, Patent Literature 12 below.
A method of forming an n+ source layer similar to the method recited in Patent Literature 1 above is also proposed in, for example, Patent Literature 13 below. A semiconductor apparatus having a substantially identical structure as the semiconductor apparatus proposed in Patent Literature 2 above is also proposed in Patent Literature 3 to 13 above.

MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device


A high-speed, directly modulated ridge waveguide laser includes: a ridge structure at a junction surface of the laser chip; and a plurality of pads only on non-active areas of the junction surface, where the plurality of pads protrude beyond an edge of the ridge structure. The laser chip can thus be held by a manufacturing tool, such that the manufacturing tool abuts the pads without abutting the ridge structure. In this manner, the ridge structure of the laser is protected from damage due to contacts by manufacturing tools, increasing the device yield of a wafer. By providing the pads only on the non-active areas of the junction surface, parasitic capacitance for contacts in the active areas can be properly controlled.

High-speed, directly modulated semiconductor ridge waveguide lasers are well known in the art. "Directly modulated", as used in this specification, relates to lasers where the source current is modulated in time. "High-speed", as used in this specification, relates to lasers functioning at a frequency of 1 GHz or higher. FIGS. 1A and 1B illustrate a top view and a cross-sectional view, respectively, of a conventional high-speed, directly modulated ridge waveguide laser chip. The laser chip 100 comprises a substrate 102 with a mounting surface 110 and a junction surface 112. At the mounting surface 110, the laser chip 100 is eventually coupled to a submount, a printed circuit board, or some other surface. The laser chip 100 is thus mounted "junction side up". The junction surface 112 comprises a contact pad 108 and a ridge structure 104. Typically, the ridge structure 104 protrudes beyond the edge of the junction surface 112.
In large scale manufacturing of laser chips, a multitude of laser chips are formed on a semiconductor wafer. Each of these chips are then handled mostly with pick-and-place tools 106. Most pick-and-place tools possess vacuum collets for holding the laser chip. FIG. 2 illustrates a conventional pick-and-place collet. The collet typically comprises a shank 202 and a tip 204. The inner diameter of the tip 204 can be approximately 152 microns. To pick up a laser chip, a vacuum is created within the collet. The vacuum is released to place the laser chip 100.
However, because the ridge structure 104 protrudes beyond the edge of the junction surface 112, the ridge structure 104 suffers from mechanical damage due to the impact from the tool 106. This can render many laser chips on a wafer non-functional, adversely affecting the device yield of the wafer.
One approach for lower-speed lasers is described in U.S. Pat. No. 5,305,340. FIG. 3 illustrates this conventional approach for a "junction side down" mounted laser. The laser includes a substrate 30, cladding layers 32 and 36, an active region layer 34, and a ridge part 38. A protective material 40, specifically gold, are disposed on the surface of the active region layer 36. Protective walls 48, comprising gold as well, are formed on either side of the ridge element. These walls 48 prevent damage to the ridge element, whether the laser is mounted junction side down or up.
However, this conventional approach is problematic for high-speed, directly modulated ridge waveguide lasers. Due to the small size of such lasers, the connection of the walls 48 to the material 40 on the active region layer 36 would cause problems with parasitic capacitance at the contacts (layer 40). To properly control parasitic capacitance, contacts to the active region must be sufficiently small. For high-speed, directly modulated ridge waveguide lasers, this cannot be accomplished when the conductive material on the active region layer is connected to the conductive materials of the walls 48.
Accordingly, there exists a need for a method and apparatus for preventing damage to a ridge of a high-speed, directly modulated ridge waveguide laser during manufacturing. The method and apparatus should be easy and cost effective to implement, and be easily practiced with standard pick-and-place tools. The method and apparatus should also allow for the proper control of parasitic capacitance. The present invention addresses such a need.

Mechanical protection for semiconductor edge-emitting ridge waveguide lasers


An apparatus for crimping a stent to a catheter as well as a method for crimping a stent to a catheter are disclosed in several embodiments. The apparatus in its various embodiments involves the application of a uniform radially inward force to a compressible tube in which the stent and catheter are situated.

This invention relates to an assembly and a method for fastening a stent onto a catheter. This kind of device finds routine use in the area of percutaneous transluminal coronary angioplasty (PTCA) procedures, although it may be used in other types of procedures, as well.
Stents and stent delivery assemblies are utilized in a number of medical procedures and situations, and as such their structure and function are well known. A stent is a generally cylindrical prosthesis introduced via a catheter into a lumen of a body vessel in a configuration having a generally reduced diameter and then expanded to the diameter of the vessel. In its expanded configuration, the stent supports and reinforces the vessel walls while maintaining the vessel in an open, unobstructed condition.
Inflation expandable stents are well known and widely available in a variety of designs and configurations. Inflation expandable stents are crimped to their reduced diameter about the delivery catheter, then maneuvered to the deployment site and expanded to the vessel diameter by fluid inflation of a balloon positioned between the stent and the delivery catheter. The present invention is particularly concerned with the crimping of inflation expandable stents although self-expanding stent may be used as well.
An example is the stent described in PCT Application NO. 960 3092 A1, published Feb. 8, 1996, the content of which is incorporated herein by reference.
In advancing an inflation expandable balloon through a body vessel to the deployment site, the stent must be able to securely maintain its axial position on the delivery catheter, without translocating proximally or distally, and especially without becoming separated from the catheter. Stents that are not properly secured or retained to the catheter may slip and either be lost or be deployed in the wrong location. The stent must be crimped in such a way as to minimize or prevent altogether distortion of the stent and to thereby prevent abrasion and/or reduce trauma of the vessel walls.
In the past, this crimping has been done by hand resulting in non-uniform crimps due to the application of uneven force to the stent. A non-uniformly crimped stent must either be discarded or re-crimped. Stents which have been crimped multiple times can suffer from fatigue. Moreover, a non-uniform crimping can result in scoring or other marking of the stent which can cause thrombosis. A poorly crimped stent can also damage the underlying balloon. Other methods of crimping stents include the use of mechanical devices such as those disclosed in U.S. Pat. No. 5,546,646 to Williams et al, U.S. Pat. No. 5,183,085 to Timmermans et al., U.S. Pat. No. 5,626,604 to Cottone, Jr. and WO 97/20593.
It is a goal of the present invention to produce a device, optionally portable, to crimp a stent onto a catheter uniformly while minimizing the distortion of and scoring and marking of the stent and due to the crimping. This goal is accomplished in the present invention in its many embodiments by applying a uniform force to a compressible tube in which the stent and catheter are situated.
In the description that follows it is understood that the invention contemplates crimping a stent to a catheter with an expandable region. Thus, when reference is made to crimping a stent to a catheter, a balloon may be situated between the stent and the catheter,or the stent may be crimped to a region of a catheter having some other means for expanding.


A transmission circuit and method for transmitting a bit sequence to be transmitted is provided that includes a dividing device for dividing the bit sequence into an even-numbered bit sequence and into an odd-numbered bit sequence, a first device for forming the first sampled values of a first fundamental wave depending on the even-numbered bit sequence, a second device for forming second sampled values of a second fundamental wave depending on the odd-numbered bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period, and includes a summator for summation of the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

1. Field of the Invention
The present invention relates to a transmission circuit and a method for transmitting a bit sequence to be transmitted.
2. Description of the Background Art
A binary phase transformation (BPSK: binary phase shift keying) for the 868/915 MHz band with a data rate of 20 kb/s in the 868 MHz band and 40 kb/s in the 915 MHz Band is known from the industry standard IEEE 802.15.4. Spreading using two spreading codes (binary) and pulse shaping occurs in a transmission method. Bits in a bit sequence here have precisely one position, so that several bits are not transmitted in parallel.

Transmission circuit and method for transmitting a bit sequence to be transmitted


A bearing which can be used between two coaxial flywheels has an inner race, an outer race, one or more annuli of antifriction bearing elements between the two races, a metallic or plastic enclosure which surrounds the peripheral surface of the outer race and a portion of the internal surface of the inner race and has a wall extending along first axial ends of the races. The wall has an outwardly bulging pocket for confinement of lubricant in addition to that which is confined in the space between the inner and outer races. Such space is sealed at the second axial ends of the races by a ring which is installed between the two races or surrounds a portion of the peripheral surface of the outer race and sealingly engages the inner race.

The invention relates to improvements in apparatus for damping fluctuations of torque in power trains, particularly in the power trains of motor vehicles. More particularly, the invention relates to improvements in bearings between rotary components (such as coaxial flywheels) which can be utilized in the above outlined apparatus. Still more particularly, the invention relates to improvements in friction reducing units which can be utilized between the flywheels of clutch plates, torque damping apparatus and like assemblies.
Apparatus in which the improved bearings can be put to use are disclosed, for example, in commonly owned U.S. patent application Ser. No. 07/708,934 filed May 31, 1991 by Wolfgang Reik et al. for "Apparatus for transmitting torque in the power trains of motor vehicles"; in commonly owned German patent application Serial No. P 40 27 6295; in commonly owned copending U.S. patent application Ser. No. 07/708,930 filed May 31, 1991 by Oswald Friedmann for "Apparatus for transmitting torque to between the engine and the transmission of a motor vehicle"; and in commonly owned copending U.S. patent application Ser. No. 07/708,935 filed May 31, 1991 by Oswald Friedmann for "Twin-flywheel apparatus for transmitting torque in the power train of a motor vehicle".

Antifriction bearing for use in apparatus for damping fluctuations of torque in power trains of motor vehicles


A method and system for conveying backhaul link information for intelligent selection of a mesh access point (MAP) in a mesh network are disclosed. The mesh network includes a plurality of MAPs. The MAPs send backhaul link information regarding backhaul connections between each MAP and any interconnections in the mesh network to a wireless transmit/receive unit (WTRU). The WTRU then determines a performance value with respect to the MAPs based on the backhaul link information and selects one of the MAPs to associate with based on the performance value. The WTRU may send information about interconnection needs of the WTRU to the MAPs, and the MAPs may generate the backhaul link information based on the interconnection needs of the WTRU.

A conventional wireless network includes a set of access points (APs), (also known as base stations), each of which is connected to a backhaul network. In certain deployments, the cost of directly connecting a given AP to the backhaul network is too high. Thus, indirectly connecting the AP to the backhaul network may be more attractive. This indirect connection is typically accomplished by relaying information to and from neighboring APs in a mesh network. This is referred to as a mesh architecture.
A mesh network is a local area network (LAN) including a plurality of mesh points (MPs). The connections between the MPs may be wired or wireless. The points of interconnection between a mesh system and a non-mesh system are referred to as portals. A mesh system with multiple portals is referred to as a multi-portal mesh system. A node capable of both AP and MP functionalities is referred to as a mesh access point (MAP). FIG. 1 shows an exemplary mesh network 100. The mesh network 100 includes a plurality of MPs 102, a plurality of MAPs 104 and a mesh portal 106. The MPs 102 serve as forwarding and relaying nodes in the mesh network 100. The MPs 102 receive traffic on incoming links and forward the traffic on outgoing links. The MAPs 104 are also MPs with an interface to provide radio access to a plurality of wireless transmit/receive units (WTRUs) 108 to provide wireless services in a certain geographic area. The mesh portal 106 provides connectivity to a backbone network 110, (such as the Internet), in the mesh network 100. Thus, the mesh portal 106 acts as an MP with a special interface to the backbone network 110. Each of the WTRUs 108 communicates with another WTRU in the mesh network 100, or to the backbone network 110, via the MAPs 104 and the mesh portal 106. The MAPs 104 forward the traffic generated by the WTRUs 108 to another MAP 104 or the mesh portal 106 by relaying the traffic via intermittent MPs 102 and/or MAPs 104.
A mesh network is reliable and offers redundancy. Even if one or more of the MPs can no longer operate, the rest of the MPs can still communicate with each other, directly or through one or more intermediate MPs such that the network may function properly. Other considerations, such as ease and speed of deployment, are advantages of the mesh network since a mesh network may be deployed without having to provide direct backhaul links and interconnection modules for each MP in the mesh network.
In conventional non-mesh wireless communication systems, a WTRU needs to estimate which AP will provide the best communication link to the WTRU. WTRUs typically use the following information and methods for determining which AP to associate with:
1) the identity of the network of which a candidate AP is a part of, (e.g., in IEEE 802.11 systems, this identity corresponds to the service set identifier (SSID) provided to the WTRUs in a beacon frame or a probe response frame);
2) the capabilities of the candidate AP including information regarding which services the AP supports, (e.g., in IEEE 802.11 systems, this capability information is included in a capability information field in a beacon frame or a probe response frame); or
3) the expected achievable data throughput, (e.g., the WTRU may estimate the expected throughput by measuring a received power it perceives from an AP on beacon frames, probe response frames or any other frames). The received power, a signal-to-interference-plus-noise-ratio (SINR) or similar measurements typically sets the maximum rate the WTRU may achieve on a given communication link. The WTRU can also use channel occupancy or channel load measurements, whether measured by the WTRU or collected from the AP, to refine the expected throughput estimate.
The above-described information and methods utilized to select an AP that a WTRU should associate with are no longer adequate in a mesh network. For example, in a conventional infrastructure mode WLAN, the throughput achieved on a given WTRU-AP link depends only on the characteristics of that particular radio link between the AP and the WTRU, (i.e., channel occupancy, received power, a signal-to-interference and noise ratio (SINR), or the like). However, in a mesh network, the throughput not only depends on the characteristics of the radio link between a given WTRU and its serving MAP, but it also depends on the characteristics of the radio link(s) between the serving MAP and other intermediate MPs that forward the traffic from the serving MAP to the mesh portal.
FIG. 2 illustrates an example of an intelligent association problem in a conventional mesh network 200. In this example, the mesh network 200 comprises three MAPs 201, 202 and 203. The MAPs 201 and 203 are mesh portals which have connectivity to the Internet 230 via a router 220. The interconnection resources of the MAPs 201, 203 may be Ethernet-based. In this example, the MAP 202 and the MAP 203 are candidate MAPs for a WTRU 210. If the WTRU 210 is associated with the MAP 102, traffic to/from the Internet 230 is routed via radio links L2 and L1 via the MAP 201. If the WTRU 210 is associated with the MAP 203, the traffic to/from the Internet 230 is routed via radio link L3. An exemplary set of radio link characteristics for the radio links L1, L2 and L3 is illustrated in Table 1 below.
TABLE 1RadioTransmissionSingle-linklinkNodesSNRratethroughputL1MAP1MAP210 dB12 Mbps 5 MbpsL2STAMAP235 dB54 Mbps20 MbpsL3STAMAP320 dB36 Mbps15 Mbps
According to Table 1, if the WTRU 210 associates with the MAP 203, the throughput would be 15 Mbps. However, if the WTRU 210 associates with the MAP 202, the throughput would be determined by the combination of data throughput of two links L1, L2, which is typically estimated as follows:1/(1/troughput_L1+1/throughput_L2).  Equation (1)
Applying Equation (1) to radio links L1 and L2, the combined throughput would be 1/(⅕+ 1/20) or 4 Mbps. From this calculation it becomes evident that the WTRU 210 will experience a better throughput by associating with the MAP 203 than by associating with the MAP 202. From the perspective of the overall mesh network 200, the preferred association of the WTRU 210 is to the MAP 203. The radio connection of L1 and L2 between the WTRU 210 and the MAP 201 offers 3.75 times (i.e., 15 Mbps/4 Mbps) less throughput than the multi-hop radio connection between the WTRU 210 and the MAP 203.
According to the prior art, in the foregoing example, the radio link L2 between the WTRU 210 and the MAP 202 seems more attractive, (in terms of signal-to-noise ratio (SNR), estimated achievable transmission rate, estimate single-link throughput, channel occupancy, or the like), than the radio link L3 between the WTRU 210 and the MAP 203. In the prior art, since the WTRU 210 has no means of knowing that associating with the MAP 203 will result in a better throughput than associating with the MAP 202, the WTRU 210 may end up with a less favorable MAP.
Accordingly, it is desirable to have a method and apparatus for enabling a WTRU to intelligently associate with a MAP in a mesh network.

Method and system for conveying backhaul link information for intelligent selection of a mesh access point


An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.

A fluxgate device generally includes a magnetic core structure and coil members coiling around the magnetic core. A fluxgate device can be used as a magnetometer for detecting a change in magnetic flux in an environment adjacent to the magnetic core structure. Attempts have been made to interface a fluxgate device with an integrated circuit for adapting to various industrial applications. For instance, a fluxgate device interfaced with a control circuit can be adapted as current measurement devices for use in motor control systems, or as position sensing device for use in robotic systems. However, these solutions involve tradeoffs between high sensitivity and low noise performances.


A gas turbine engine having a compressor section using blades on a rotor to deliver a gas at supersonic conditions to a stator. The stator includes one or more of aerodynamic ducts that have converging and diverging portions for deceleration of the gas to subsonic conditions and to deliver a high pressure gas to combustors. The aerodynamic ducts include structures for changing the effective contraction ratio to enable starting even when designed for high pressure ratios, and structures for boundary layer control. In an embodiment, aerodynamic ducts are provided having an aspect ratio of two to one (2:1) or more, when viewed in cross-section orthogonal to flow direction at an entrance to the aerodynamic duct.

A continuing interest exists in industry for improved gas turbine engines. Gas turbine engines continue to be useful in a wide variety of applications. Operational costs could be substantially improved in many applications by adoption of an improved gas turbine engine that would increase operating efficiency as compared to currently-utilized gas turbine designs. Further, from the point of view of maintenance costs, it would be desirable to develop improved gas turbine engine designs that would reduce the mass of rotating components, since such rotating components are costly when replacement or repair becomes necessary, as compared to non-rotating parts, which although subject to stress and strain from temperature and pressure, are not subject to additional loads due to rotary motion. Thus, it can be appreciated that it would be advantageous to provide a new, high-efficiency gas turbine engine design which minimizes moving parts. Generally, it would be advantageous to provide more horsepower with less weight. And more specifically, it would be advantageous to provide small gas turbines having a relatively high overall efficiency, particularly in the one-half to three megawatt range
A key component of gas turbine engines is the compressor section. Although supersonic compressors have been contemplated for use in gas turbine engines, there remain various technical problems in the field and with respect to which better solutions are required in order to improve operational capability and compression efficiency. In particular, although relatively low pressure ratio supersonic compressors have been proposed for gas turbine engines, there still remains a need for compressors for gas turbine engines that can be easily started, yet be operated at high compression ratios. Further, it would be advantageous to avoid configurations that present moving shocks, such as between moving blades, between moving and fixed blades, or between moving and fixed walls, in order to more simply achieve stability for a normal shock at a selected location in the compressor section of a gas turbine engine.
In short, there remains a need to provide a design for a gas turbine engine with a high pressure ratio supersonic compressor that simultaneously resolves various practical problems, including (a) providing for starting of a compressor designed for high pressure ratio operation, so as to enable control of a normal shock at an effective location in a supersonic diffuser when configured as a stator and designed for high pressure ratio and efficient compression, (b) avoiding excessive numbers of leading edge structures (such as may be encountered in prior art multi-bladed stators), and minimizing other losses encountered by a high velocity supersonic gas stream upon entering a stator, and (c) providing for effective boundary layer control, especially as related to retention of a normal shock at a desirable location, in order to achieve high compression ratios in an efficient manner.

Gas turbine engine with supersonic compressor


A pen having a barrel with a transparent sleeve to hold a refill for writing, wherein an intricate network of winding passage ways is formed around the barrel, where by tilting and turning the ball finds its way starting from its designated point.

The present invention relates to a pen which can be used as a tool for writing as well as a toy for playing the game of labyrinth.
Different writing apparatus may be used for different purposes. However, a pen is simply designed for writing and does not provide any other functions. Recently, there are manufactures who combine a pen with a digital watch, clipper, lighter or other small devices for multiple purposes. Since writing is a tiresome activity one has to take a rest from it. Thus, you can now convert it as toy for fun and relaxation.

Pen with a toy labyrinth incorporated therein


A system, for determining a starting position angle of an electric motor, includes a plurality of windings, a circuit, a processor, and at least one voltage sensor. The circuit is configured to create a pulse current field in at least one of the plurality of windings. The sensor is configured to sense a pulse current field response in a corresponding winding of the plurality of windings. The processor is in communication with the voltage sensor and is configured to determine the position angle of the rotor based on the pulse field response.

1. Field of the Invention
The present invention generally relates to a system for determining a starting position angle for a rotor of a DC motor.
2. Description of Related Art
Actively controlled power electronic switches (such as MOSFETs', IGBTs', SCRs', etc.) can substantially improve the performance of some alternators and motors. MOSFETs' have been employed in a variety of rectifier designs for automotive alternator applications. When switches are used in an alternator rectifier, the firing of the switches can be manipulated in such a way that the alternator can function as a DC motor to start the vehicle engine. The electric machine used both as starter and alternator in a vehicle is called alternator/starter. It can be used to implement the stop/start feature of a vehicle and this feature can substantially improve the overall fuel efficiency of a vehicle.
When electric switches, such as MOSFETs', are used for controlling an electric machine, detection of the rotor angle position forms an integral part of the control algorithm. Current in each phase of the machine is controlled by the MOSFETs' based on rotor angle position. Traditionally, external rotor angle position sensors, such as, optical encoders, Hall-effect magnetic sensors, and resolvers, are used to directly detect the angular position of the rotor. Unfortunately, these sensors are often expensive, temperature sensitive, and difficult to package within an alternator. A sensorless control approach can provide increased power density while minimizing the cost of the machine.
Sensorless techniques typically monitor phase back EMF, phase terminal voltages, or phase currents in order to determine the rotor angle position. When the electric machine is not spinning, pre-existing sensorless techniques are not adequate for determining the rotor position.
In most DC motor applications utilizing sensorless techniques, the rotor is pre-positioned to a known rotor angle position by energizing particular windings of the electric machine. With the rotor in a known position, standard 6-step control process is implemented to drive the electric machine. If the rotor is pre-rotated to a known position, the pre-rotated angle could be clockwise, or counter-clockwise, depending on the initial rotor angle position.
When the alternator function as a vehicle starter (DC motor), the alternator rotor starts at an arbitrary angle. Because the alternator is connected to the engine crankshaft through a drive belt and since the engine can only rotate in one direction, the alternator must turn the drive belt in only one direction. For example, a clockwise direction assuming the engine normal operation direction is clockwise. The present sensorless techniques for pre-positioning the rotor cannot ensure a clockwise rotation to the known position.
In view of the above, it is apparent that there exists a need for an improved system for determining a starting position angle of an electric motor.

Electric machine with actively controlled switches


A modulator, and more particularly an HPSK modulator, is disclosed that enables the circuit scale to be reduced and also enables power consumption to be reduced. An HPSK modulator 209 incorporated in a radio communication apparatus or the like is equipped with a spreading code multiplication section 11, a complex arithmetic section 101, a coefficient determination section 51, and raised COS filters 41 and 42. Spreading code multiplication section 11 multiplies transmit data DPDCH1 by a spreading code Cd1. Complex arithmetic section 101 performs complex arithmetic on an output signal output from spreading code multiplication section 11 and a scrambling code Sn, and performs conversion to complex data. Coefficient determination section 51 determines a filter coefficient Ad1n based on a gain factor βd1 that determines transmission power. Raised COS filters 41 and 42 band-limit the complex data using the filter coefficient.

1. Field of the Invention
The present invention relates to a modulator, and more particularly to a digital modulator used in radio communications and so forth. Furthermore, the present invention relates to a technology that is effective for application to a Hybrid Phase Shift Keying (HPSK) modulator used with the W-CDMA (Wideband—Code Division Multiple Access) method.
2. Description of the Related Art
In a communication system that uses the W-CDMA method, in reception a control channel is inserted into a transmit channel by time division. In transmission, on the other hand, the HPSK modulation method is used. With this HPSK modulation method, orthogonal components of spread data of multiple channels are converted to vector values, and these are further rotated using a scrambling code. When the HPSK modulation method is used for normal transmission (single mode), two channels—a transmit channel and a control channel—are provided, and multimode operation is established if transmit channels are further superimposed in this state.
Concrete examples of multimode operation include a case where image data is sent at the same time as voice data, and a case where mail data is sent at the same time as voice data. As the amount of data transmitted differs for voice data and image data, voice data is transmitted at low speed and mail data at high speed. The transmission data rates are in the range from 15 kbps to 960 kbps, and are variable. The chip rate (spreading code rate) is 3.84 MHz, and one data is spread using a ratio of 4 chips to 256 chips.
In a communication system using this kind of HPSK modulation method, reception becomes difficult on the receiving side at high speeds, and therefore transmission power is varied according to the transmission data rate of the transmitting side. That is to say, control is performed so that the speed of the transmission data rate and the magnitude of the transmission power are made proportional, and transmission power is increased as the transmission data rate becomes faster, enabling reception to be performed easily during high-speed communication. This function was previously relegated to the high-frequency region (RF region), but when the W-CDMA method is used this function tends to be used in the baseband region in order to handle multimode operation.
Transmission gain that makes transmission power variable is called β. In the baseband section, since a voltage is output, the transmission gain β value is made proportional to the transmission data rate, and is set in the range 0 to 15 (4 bits).
A single-mode HPSK modulator is disclosed in Unexamined Japanese Patent Publication No. 2001-339365. as shown in FIG. 12, this HPSK modulator is equipped with multipliers 11 and 17, a complex arithmetic section 101 composed of multipliers 21, 27, and 37, raised COS filters 41 through 44, envelope generators 91 and 92, multipliers 81 through 84, and adders 71 and 72.
Multiplier 11 multiplies transmit data 1 of dedicated physical data channel DPDCH1 by a spreading code. Multiplier 17 multiplies control data 7 of dedicated physical control channel DPCCH by a spreading code. Complex arithmetic section 101 performs complex arithmetic between the outputs of multipliers 11 and 17 and a scrambling code, and generates real part data and imaginary part data for each channel. Raised COS filters 41 through 44 band-limit the output data of each channel from complex arithmetic section 101. Multipliers 81 through 84 multiply the output data of raised COS filters 41 through 44 by a gain factor. Adder 71 adds together the real part data output from multipliers 81 and 82, and adder 72 adds together the imaginary part data output from multipliers 82 and 84.
To be more specific, multipliers 11 and 17 each comprise an exclusive-OR circuit. Multipliers 21, 27, and 37 each comprise an exclusive-OR circuit or two exclusive-NOR circuits. Raised COS filters 41 through 44 each comprise a 1-bit-input FIR filter (Finite Impulse Response Filter).
Multiplier 11 multiplies transmit data 1 input via dedicated physical data channel DPDCH1 by a transmit data spreading code Cd1, and outputs output data I (=Cd1×DPDCH1) to multiplier 21. Here, transmit data 1 is 1-bit data with a data rate of 15 kbps to 960 kbps, for example, and transmit data spreading code Cd1 is 1-bit data with a chip rate of 3.84 MHz, for example. Therefore, multiplier 11 output data I is 1-bit data that varies on a chip-by-chip basis.
Multiplier 17 multiplies control data 7 input via dedicated physical control channel DPCCH by a control data spreading code Cc, and outputs output data Q (=Cc×DPCCH) to multiplier 37. Here, control data 7 is 1-bit data with a data rate of 15 kbps, for example, and control data spreading code Cc is 1-bit data with a chip rate of 3.84 MHz, for example. Therefore, multiplier 17 output data Q is 1-bit data that varies on a chip-by-chip basis.
Multiplier 21 performs complex arithmetic in which output data I from multiplier 11 is multiplied by a scrambling code Sn, and outputs 1-bit complex data comprising real part data Ii1 (=SIn×I) and imaginary part data Iq1 (=SQn×Q). Here, scrambling code Sn comprises complex data with a chip rate of 3.84 MHz, each of 1 bit, for example. SIn is scrambling code Sn real number data, and SQn is scrambling code Sn imaginary number data.
Multiplier 27 has, as input, output data jQ from multiplier 37 in which output data Q from multiplier 17 has been multiplied by an imaginary number j. Multiplier 27 performs complex arithmetic in which output data jQ is multiplied by a scrambling code Sn, and outputs 1-bit complex number data comprising real part data Qi1 (=SIn×Q) and imaginary part data Qq1 (=−SQn×I).
Raised COS filter 41 outputs multi-bit data Ii2 in which multiplier 21 output data Ii1 has been band-limited. Raised COS filter 42 outputs multi-bit data Iq2 in which multiplier 21 output data Iq1 has been band-limited. Raised COS filter 43 outputs multi-bit data Qi2 in which multiplier 27 output data Qi1 has been band-limited. Raised COS filter 44 outputs multi-bit data Qq2 in which multiplier 27 output data Qq1 has been band-limited. Here, 10-bit impulse response FIR filters are used for raised COS filters 41 through 44, and each of output data Ii2, Iq2, Qi2, and Qq2 is 10-bit data.
Envelope generator 91 outputs gain factor βd1′ for which smooth envelope control is performed when gain factor βd1 is changed. Envelope generator 92 outputs gain factor βc′ for which smooth envelope control is performed when gain factor βc is changed. Here, βd1=βd1′ and βc=βc′.
Multiplier 81 performs multiplication of output data Ii2 from raised COS filter 41 and gain factor βd1, generates multi-bit data Ii3, and outputs this to adder 71. Multiplier 82 performs multiplication of output data Iq2 from raised COS filter 42 and gain factor d1, generates multi-bit data Iq3, and outputs this to adder 72.
Multiplier 83 performs multiplication of output data Qi2 from raised COS filter 43 and gain factor βc, generates multi-bit data Qi3, and outputs this to adder 71. Multiplier 84 performs multiplication of output data Qq2 from raised COS filter 44 and gain factor βc, generates multi-bit data Qq3, and outputs this to adder 72.
Adder 71 generates output data Iout (=Ii3+Qi3) comprising multi-bit data in which output data Ii3 from data channel multiplier 81 and output data Qi3 from control channel multiplier 83 have been added, and outputs this output data Iout. Adder 72 generates output data Qout (=Iq3+Qq3) comprising multi-bit data in which output data Iq3 from data channel multiplier 82 and output data Qq3 from control channel multiplier 84 have been added, and outputs this output data Qout. Output data Iout output from adder 71 and output data Qout output from adder 72 undergo digital-analog conversion in next-stage D/A converters, and are sent to the high-frequency area.
However, in the above-described HPSK modulator, consideration has not been given to the fact that, since outputs from raised COS filters 41 through 44 and gain factors βd1 and βc are multiplied, multi-bit multipliers operating at a rate of n times 3.84 MHz are necessary, increasing circuit scale and power consumption.


Telecommunications apparatus between a voice frame network gatekeeper and an intelligent peripheral, e.g. an interactive voice response unit (IVR), includes a voice frame network connection for coupling the same. The apparatus further includes a protocol over the connection that provides supplemental service messaging therebetween, the protocol enabling the gatekeeper to selectively insert one or more messages to the intelligent peripheral and to selectively intercept one or more messages therefrom. Preferably such insertion is of one or more GR-1129-CORE send-to-resource (STR) messages and such interception is of one or more ITU-T H.323 FACILITY messages including a RETURN RESULTS component. An invocation mechanism within the gatekeeper and a performance mechanism within the IVR permits the gatekeeper to set a defined task to the IVR, also preferably in accordance with the ITU-T H.323 and H.450 standards. The method involves configuring the gatekeeper as a supplemental services provider (SSP) and configuring the IVR as an intelligent peripheral, under ITU-T H.450. The method further involves conveying requests from the gatekeeper to the IVR and conveying responses thereto from the IVR to the gatekeeper, wherein the gatekeeper selectively intercepts one or more messages from the IVR and, optionally, also selectively inserts one more messages to the IVR.

The present invention relates generally to voice frame network gatekeepers and intelligent peripherals such as interactive voice response units (IVRs), and more particularly it concerns method and apparatus for interfacing gatekeepers to intelligent peripherals via the ITU H.323 and H.450 standards.
Previously, intelligent peripherals have been connected to gatekeepers within the Internet using proprietary interfaces. One such proprietary interface is (Bellcore) GR-1129-CORE, which can be used to connect an intelligent peripheral such as an IVR into an advanced intelligent network (AIN). The AIN includes a switch service point (SSP) with call-processing software and voice channel control and a service control point (SCP) with data-based (e.g. 800 or LNP) information required by the SSP to route a call. The intelligent peripheral is a special resource that provides additional functionality, e.g. IVR, to the SSP that may be required by the SCP. When the SSP receives a GR-1129-CORE message from the SCP containing an operation value, e.g. a '0' (play announcement), '1' (play announcement and collect digits) or '4' (flex parameter block), it passes the content to the intelligent peripheral through ISDN or Q.931. When the intelligent peripheral, e.g. an IVR, starts the specified function, it establishes a voice channel to the user through the SSP. Because the SSP controls the voice channel, it can provide such services as call transfer after the IVR transaction is finished.
Those of skill in the art will appreciate that the referenced ITU and related standards are well known, evolving standards. Accordingly, reference herein to these standards will be understood to mean the standards as they existed at the time of the earliest effective filing date of the present application, and as they have evolved to date, and as they continue to evolve over the term of any patent that issues herefrom. Applicants note that an instructive earlier version of the ITU H.450.1 standard is described in Generic functional protocol for the support of supplementary services in H.323, date unknown; that the GR-1129-CORE standard is described in AINGR: Switch—Intelligent Peripheral Interface (IPI), Revision 1, October, 1998 and AINGR: Switch—Service Control Point (SCP)/Adjunct Interface, September 1997; that the ITU-T H.225.0, ITU-T H.450.2 and ITU-T Q.931 standards are described in Call Signaling Protocols and Media Stream Packetization for Packet Based Multimedia Communications Systems, February 1998, Call Transfer Supplementary Service for H.323I, September 1997 and ISDN User-Network Interface Layer 3 Specification for Basic Call Control, March 1993, respectively.
No intelligent peripheral interface has been proposed heretofore that is compatible with the ITU-T H.323 or related H.225, H.245, H.450 and Q.931 standards, and the GR-1129-CORE standard.

Interception call signaling method and apparatus between a gatekeeper and an intelligent peripheral in a voice frame network


A cannula casting mould and casting method for improving quality by making it possible to cast a smooth surface. An opening is formed in the side of the front side and a casting mould for casting a cylindrical cannula formed with a liquid flow path that is connected inside to the opening that comprises a mould body in which a casting groove is formed, a core area placed in the casting groove forming a casting open area between the surfaces of the casting groove, and an angle pin prepared in the mould body in an elongated state of the area corresponding to the open area of the casting groove. Furthermore, the injection opening for injecting casting material into the casting opening is prepared on the opposite side of the core area centre of axis from the area where the angle pin was placed in the mould body.

To date, normal saline water and liquid medicine and the like that are stored in containers such as vials or ampoules are suctioned using a syringe with a cannula attached to the tip, and this liquid medicine and the like is supplied to the patient through filling a prescribed area of a transfusion line connected to the patients body. The tip of this cannula comprises a narrow cylindrical needle, and there is an opening for injection and extraction of liquid medicine and the like formed in the tip of this cylindrical needle. Of the types of cannulae, there are those that are formed out of resin material to enable expanding shape selection width and to ensure safety. Furthermore, there are those where the opening is not prepared in the tip of the needle but in the side area of the tip of the needle (for example Patent reference 1: Published unexamined patent application 2002-17856).
In the case that this type of cannula is cast using injection moulding equipment prepared with a casting mould, a core area that forms the cast open area is placed between surfaces of the groove for casting and in addition, opening forming pins that correspond to the opening of the cannula in the mould body extend towards the core area from both sides and the tip areas contact the core area and in this state, casting material is injected into the casting open area through the injection opening of the mould body. Furthermore, in the case that an opening is not formed on both sides, but only one side of the tip, a pin for preventing inclination due to injection pressure of casting material contacts the tip area of the core on the surface opposite the surface where the opening forming pin in the core area contacts and injection moulding is performed with this condition. In addition, processing treatment to fill the hole cast by the pin for preventing inclination is performed after casting.
However, of the aforementioned conventional cannulae manufactured using a resin, when producing a cannula with an opening formed on one side of the tip area, there was the problem that manufacturing processes increased due to the necessity of processing treatment to close the hole formed by the pin for preventing inclination and in addition there was the possibility that the surface of the cannula would be rough after closing the hole, lowering the quality of the cannula.
Taking these circumstances into consideration, the purpose of the present invention is to provide a casting mould and casting method for cannulae enabling a reduction of manufacturing processes and increasing quality by enabling the forming of a smooth surface.

Cannula casting mould and casting method


A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level packages (WLP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
In a semiconductor package, a semiconductor die is encapsulated by a molding material using a process which leaves the active surface of the semiconductor die exposed after encapsulation. An interconnect build-up layer, including dielectric layers, metalized redistribution layers, and under bump metallurgy layer, is disposed over the active surface of the chip and the molding compound. Solder bumps or other electrical interconnections are then formed on the interconnect build-up layer, making the semiconductor die capable of electrically connecting to external devices.
The encapsulation of the semiconductor die includes using a substrate on which the die is set facedown and allowing the molding compound to flow around and over the die without coating the active surface. In the resulting semiconductor package, the molding material is thinner over the semiconductor die than the surrounding area. Thus, delamination can occur between the semiconductor die and encapsulating material as a result of the difference between the coefficients of thermal expansion (CTE) of the molding material and the semiconductor die.
A mismatch of CTEs can also damage the area where the solder bumps connect to the interconnect build-up layer. Solder joints are fragile elements of a semiconductor package due to their small size and use at high temperatures relative to their melting points. Solder joint failure can occur for a variety of reasons. One category of failure arises from the application of cyclical stresses, primarily from temperature swings and the different CTEs of the solder joints and application board. As solder joint failures can result from standard daily events, such as powering on and off electrical equipment, solder joint reliability is important in the manufacture of WLCSPs.
A need exists to resolve solder joint failure and intermediate interconnect build-up layer delamination issues on WLCSPs due to CTE mismatch between the die and mounting board or interconnect build-up layer.

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer