A biological sample analyzer, and a method and system for operation thereof, wherein instrument systems used to perform an assay of each of the biological samples loaded into the analyzer are operated in accordance with a schedule developed by a scheduler routine. The scheduler routine determines a time allowance for performing operations by instrument systems for conducting an assay on each biological sample from a load list indicating the type of assay to be conducted upon each biological sample. The time allowance determined is adapted to accommodate variations in actual performance of instrument system operations on each sample so that the assays of the biological samples can be performed by the instrument system operations in accordance with a reliable and reproducible schedule.

The present invention relates generally to biological sample analyzers used to perform assays of patient specimen samples. More particularly, the present invention relates to a method and system for the scheduling the operating steps for performing assays of biological samples in an automatic analyzer with reproducible and reliable performance.
Biological sample analyzers, of the type considered herein, are automated instruments that may be used in hospitals, clinics, laboratories, or other locations, to run routine tests (assays) on samples of patient specimens such as blood, spinal fluid, urine, serum, plasma, and so on. An automated analyzer of the type discussed herein includes an analyzer unit that runs tests on a number of patient specimen samples that are loaded into the unit. An operator-user prepares the samples by placing portions of the patients' specimen samples into a number of like-sized sample containers. These samples may be diluted or otherwise treated, depending upon the type of analyzer used, the type of assay being performed, and other factors. The containers are then placed in the analyzer unit. The containers may first be placed in a rack or carousel that is then placed in the analyzing unit. The rack may accommodate a number of sample containers, e.g. 24. In addition, one or more appropriate chemical reagents, needed to perform the assays, are also placed in the analyzer unit. In order to mix reagents with the samples, the analyzer unit may also include a fluid moving system, such as a robotic probe mounted on a boom, which is adapted to draw up portions of the reagents and/or samples and expel them into appropriate locations, e.g. additional cells such as reaction cells provided in the sample containers, where a reaction can take place. The analyzer unit also may include a means for detecting a reaction in the reaction cells. This may include an optical detector to observe fluorescence reactions and make optical measurements to obtain a result for each sample. The analyzer unit may also typically include other mechanical systems to move the sample containers and the probe. The analyzer unit may also provide for cleaning the probe between certain tasks in order to avoid contamination between samples. For this purpose, the analyzer unit may also include a washing station and a waste dispensing container to hold the used rinse solution.
After the operator-user loads the specimen samples, enters appropriate instructions, and starts the unit, the analyzer runs unattended. When placed in operation, the analyzer unit, using the appropriate chemical reagent, runs the same test on each of the samples in the sample containers and will perform identical operations on each of the samples loaded in the rack. When it is finished, the analyzer prints out or otherwise reports on the results of its testing.
Biological analyzers utilize different chemistries for performing assays of specimen samples. One type of assays used in biological analyzers includes immunoassays and solid phase procedures. Analyzers for performing immunoassays in general and enzyme immunoassays in particular are known in the art.
A biological analyzer that utilizes immunoassay chemistry to perform assays of specimen samples loaded therein is the IMx.RTM. analyzer introduced in 1988 by Abbott Laboratories, of North Chicago, Ill. (A description of the IMx analyzer is included in "The Abbott IMx Automated Benchtop Immunochemistry Analyzer System", by Fiore, M. et al., Clinical Chemistry, Vol. 34, No. 9, 1988, which is specifically incorporated herein by reference in its entirety). The IMx analyzer is a biological sample analyzer that has been developed for use in conjunction with solid phase immunoassay procedures to perform a variety of assays (such as sandwich and competitive assays). The IMx analyzer uses a technology referred to as microparticle capture enzyme immunoassay (MEIA) and fluorescence polarization immunoassay (FPIA). The IMx analyzer includes a microprocessor used to control a robotic arm with 2 degrees of freedom and a rotating carousel to process the samples for assay. One assay can be done on each of 24 specimen samples in 30-40 minutes or more unattended after loading (i.e. with "walk away" automation). Assay results are output to a printer or a computer interface.
A biological sample analyzer, such as the IMx analyzer described above, can execute the steps required for performing assays of up to 24 specimen samples, including the steps of counting the samples, identifying which assay to run, warming the reagents and reaction cells to appropriate temperatures, pipetting the reagents and samples, diluting samples if required, timing critical assay steps such as incubations, washing unbound conjugate, quantifying the fluorescence signal and performing data reduction to yield a useful result.
The container used for holding each of the specimen samples for a biological sample analyzer, such as the IMx analyzer, may be a disposable assay cartridge having a plurality of wells, with at least one reaction well and one separation well. The separation well may contain a fibrous matrix positioned across its entrance and an absorbent material positioned below the fibrous matrix. Microparticles react with an analyte containing sample and one or more reagents to form a complex. This complex is immobilized on the matrix of the separation cell. The excess sample and reagent are washed through the matrix and captured in the absorbent material below.
The results of the reactions may be read using known optical detection techniques. For example, using conventional solid phase procedures, an analyte can be labeled or tagged with an enzyme which in the presence of its substrate fluoresces, and emits light at a known wave length. The rate at which the fluorescent product is produced is indicative of the concentration of the analyte in the biological sample. A conventional fluorometer is suitable for illuminating the fibrous matrix with a beam of light having the appropriate excitation wave length. The fluorometer also detects the intensity of the light at the emission wave length. Assays using this type of solid phase technology has been found to provide a high degree of sensitivity.
A biological sample analyzer, such as the IMx analyzer, provides for performing assays of patients' specimen samples and reading the results of such assays in a mass production type manner. This allows such assays to be made available quickly and conveniently.
Even though such analyzers can provide significant advantages by performing assays quickly and conveniently, further advantages for the user could be obtained if the overall through put of the analyzer could be increased. One way to provide even more advantages and convenience for users of biological analyzers would be to provide the capability to perform more than one assay on the specimen samples in an unattended run. Although a biological analyzer like the IMx analyzer can perform different types of assays and can perform assays on a number of specimen samples unattended, the analyzer can run only one type of assay at a time. If a different type of assay is to be performed, the analyzer would have to be reloaded with different reagents. Also, because different types of assays may require different amounts of the sample specimen, different amounts of reagents, different processing steps, different incubation times, etc., the analyzer would also be reset at the beginning of the run to perform the new assay. In the case of the IMx analyzer, a different memory module may have to be inserted containing the instructions for the analyzer unit for performing the different assay. Thus, even if only a few of several different types of assays need to be run, the operator-user has to load and run the analyzer for the first type of assay for only a few samples and then reload the analyzer to run the second type of assay on another batch of samples using perhaps different reagents. It is recognized that for many users of the IMx analyzer, or other biological sample analyzers, it would be convenient and advantageous to be able to perform more than one type of assay during an unattended run.
Although it may be desirable to provide a biological analyzer with the capability to perform more than one assay in an unattended run, there are several obstacles that make providing this feature complicated. For example, different assays require different functions or operations to be performed upon the sample specimens in the carousel rack by the mechanical or optical systems of the analyzer. In the prior IMx analyzer, or in other analyzers in which only one type of assay is being performed during an unattended run, it can be difficult to determine when each of the operations upon each of the samples will be performed so that sufficient time allowance can be provided to ensure that incubation periods limits are not exceeded or that the samples or reagents do not evaporate. This is even more difficult in an analyzer in which the user is permitted to select the type and number of assays to be performed in an unattended run. For example, if there are 24 specimen samples in the carousel rack and the operator-user is permitted to select any one of three different assays to be performed on the samples, there are almost 2500 different permutations of possible combinations of assays and samples that the user can select. (The number is 2925 if all possible combinations, even those that an operator-user would never run are considered). If the user is permitted to select any one of four different assays to be performed on the 24 samples, there are approximately 10,000 different permutations of possible combinations. This presents an operating problem because certain tasks in the automatic analyzer must be performed on the samples at certain times or within certain specific time limits. Thus, there is a requirement to efficiently schedule the activities being performed by the automatic analyzer. Considering that 100 or more different mechanical operations can be performed on each sample, and that due to chemical reaction constraints certain operations must be performed within certain rigidly specified time durations from other operations in order to obtain valid results, it can readily be appreciated that scheduling and operating an analyzer to perform more than one assay unattended is considerably more complicated than scheduling and operating an analyzer in which only one assay is performed in an unattended run.
One automatic assay device is known having the capability to perform more than one assay on specimen samples loaded therein in an unattended (e.g. "walk-away") run. That device is the ADx.RTM. biological analyzer available from Abbott Laboratories. Although the ADx analyzer can perform more than one type of assay on samples loaded in its carousel rack, the ADx analyzer is used primarily for assays that are different than those performed by the IMx analyzer. The assays performed by the ADx analyzer are, in general, simpler and typically include fewer steps. Also with respect to the assays performed by the ADx analyzer, there are, in general, fewer constraints on incubation periods between steps. Accordingly, when the ADx biological sample analyzer is used to perform more than one assay in a run, the scheduling of the various operations to be performed by the analyzer systems on the specimen samples can be accomplished by using the minimum incubation time interval between operations. However, when the minimum incubation period is used, the throughput of the analyzer can decrease (i.e., the overall time to run the assays increases) due to conflicts among the schedules of the assays. Moreover, with the type of assays performed by the IMx, such as MEIA and FPIA, there are usually more steps for each assay and there are more constraints that certain steps must be performed within certain incubation time limits to produce valid data. Further, with the types of assays performed on the IMx analyzer, there is also greater variability in the assay steps and incubation limits between different steps among different assays. Accordingly, it is difficult to schedule an analyzer such as the IMx analyzer to perform more than one assay in an unattended run.
One of the factors affecting the scheduling of instrument operations is the variation in time that it takes to perform certain operating steps by the analyzer on the specimen samples. Such variations in operation can arise in numerous ways. One of the ways that variations can arise relates to the number of possible schedule permutations as a result of scheduling more than one assay to be performed in a run.
With an analyzer capable of performing more than one assay in a run, the number of possible permutations of load lists is high thereby complicating the scheduling of the analyzer instrument system operations to account for such variations. It can be appreciated that the functions being performed by the analyzer instrument systems involve certain mechanical operations, such as moving a boom and probe, aspirating a reagent, sample, or rinse, moving the carousel rack, "step-look" operations to find a fluid level, etc. The amount of time that these operations take is a function of the start and stop positions of the probe, the rack, the reagents, etc., and can also vary depending upon the number and location of each type of sample being run for each type of test.
For example, the movement of the carousel can take different amounts of time depending upon whether the carousel has to move only a few degrees or whether it has to move a complete half revolution. Evidently, the half rotation takes longer to perform than the movement of only a few degrees. However, when attempting to schedule the operation of the analyzer instrument systems, these variations in position are a factor and can add up over a run. Since such variations in movement time are a function of both the previous and subsequent positions of the instrument system, these variations cannot be accounted for until both all these positions are established.
Also, there may be certain variations related to training calibration points, interrupt latencies, the clock speed of the microprocessor, code running overhead, motor controller variations, etc. In addition, there may be variations between different machines due to design tolerances among machines. Also, certain analyzers may have minor idiosyncracies that affect the time that it takes to perform certain instrument system operations but that do not detract from safe reliable performance.
Although it may be technically possible to calculate a prediction that closely approximates the amount of time variations in instrument activities should take based upon the start and stop location of the instrument systems, such an effort would be burdensome and require a significant amount of processing power. Moreover, such detailed calculation might not necessarily account for the design tolerances from one analyzer to the next mentioned above or certain idiosyncracies associated with certain analyzers.
These variations in performance times can complicate the operation of the analyzer because certain assay steps such as incubation periods, must be performed within specific defined time periods of other steps to provide valid data. Because these incubation periods must be strictly observed if the analyzer completes certain instrument operations too quickly or too slowly it can exceed the required time limits.
Thus, the scheduling of the operating steps of an analyzer becomes very burdensome and complicated especially when more than one assay is being performed in an unattended run.
Accordingly, it is an object of the present invention to provide a biological analyzer that is capable of performing more than one assay on specimen samples loaded therein in an unattended run in a manner that provides reasonable through put.
It is a further object to provide a biological analyzer that accounts for variations in instrument system movements and locations, machine tolerance variations and other factors and provides a reliable and reproducibly consistent assay performance.

Adaptive scheduling system and method for a biological analyzer with reproducible operation time periods


A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.

Along with the demand for miniaturized and high-capacity electric/electronic products, a wide variety of techniques for providing high-capacity semiconductor devices are researched and developed. One of the techniques for providing high-capacity semiconductor devices is to stack semiconductor dies. In stacking the semiconductor dies, a memory chip is stacked on a logic chip, and the memory chip and the logic chip are connected to each other using a conductive wire or a conductive bump.
However, when a conductive wire or a conductive bump is used in electrically connecting semiconductor chips, a process of applying heat is required, making it difficult to employ this technique on a wafer level.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

Semiconductor device utilizing redistribution layers to couple stacked die


In a method for determination of coronal and sagittal planes for the subsequent acquisition of new magnetic resonance slice images or the representation of magnetic resonance slice images from an existing image data set of a shoulder joint starting from a data set representing a transversal slice image of a shoulder joint, the slice image is analyzed using at least one analysis algorithm to determine the shoulder blade and for two points lying on the shoulder blade that define the coronal plane. The slice image also is analyzed using at least one analysis algorithm to identify the shoulder blade and the half-moon-shaped arc of the joint connection between the had of the upper extremity of the humerus and the shoulder blade, and two points on the arc in the region of the joint connection with the shoulder blade that define the sagittal plane. A coronal slice image or a sagittal slice is then acquired or represented at the display dependent on the orientation of the identified planes.

1. Field of the Invention
The present invention concerns a method for determining of distinguished coronal and sagittal planes from an already-present image data set of a shoulder joint for the subsequent acquisition of new magnetic resonance slice images or the representation of magnetic resonance slice images.
2. Description of the Prior Art
Diseases in the region of the shoulder joint are painful and impair the patient in terms of freedom of movement. Magnetic resonance tomography is a gentle method for examination of the shoulder joint. In order to acquire an optimally large amount of information from the examination region, so as to be able to generate meaningful slice image therefrom, the shoulder joint is acquired in the form of a number of slice image sets that are respectively acquired in specific planes. The data acquisition ensues in the transversal, coronal and sagittal directions, but these planes need not be exactly perpendicular to one another but can, if applicable, be tilted relative to one another. Each slice image set is composed of, for example, twenty to forty individual slice images that all have been acquired in parallel slice planes abutting one another. The entire examination volume can be acquired in this manner.
Difficulties arise, however, when a follow-up examination is to ensue at a later point in time in order to implement therapy monitoring. Because the individual slice image groups, or the various measurement protocols (for example T1 or T2), typically are set manually in coronal, sagittal and transversal orientation by the apparatus operator (technician), difficulties occur with regard to reproducing the original slice plane positioning. This applies even when the same operator does the setting at a later point in time, but is particularly a problem when a different operator acquires the later data. The slice images previously acquired do not normally exist as references, such that the later technician cannot make use of them for orientation purposes.
Similar problems also occur when acquired slice images are to be evaluated at a later point in time. Here as well each image representation ensues using slice images in coronal, transversal or sagittal orientations. Depending on how the diagnosing physician now places the respective orientation, different plane orientations and therewith different image representations can occur. Again, no reproducibility is achieved.

MR method and apparatus for determining coronal and sagittal image planes from an image data set of a shoulder joint


Control circuit for an IGB transistor, which comprises means (T1, V1, C3, C4) for generating auxiliary voltage, a first and a second controllable control switches (V8) connected in series between the auxiliary voltage, and a gate resistor (Rg). The control circuit further comprises a boost capacitor (Cg) connected in series with the gate resistor (Rg), a resistor (R3) whose first terminal is connected to the second terminal (4) of the boost capacitor and whose second terminal is connected to the intermediate voltage level of the auxiliary voltage of the control switches, a Zener diode (V9) whose anode is connected to the point between the gate resistor and the boost capacitor and whose cathode is connected to the point between the boost capacitor and the resistor (R3), and a diode (V10) whose anode is connected to the cathode of the Zener diode (V9) and whose cathode is connected to the positive terminal of the auxiliary voltage of the control switches.

The invention relates to a control circuit of the preamble of claim 1 for a semiconductor component, particularly to a control circuit for an IGB transistor, to enable faster turn-on and turn-off of the transistor.
High-power IGB transistors typically have a gate charge of several microcoulombs and therefore in order to change transistor state quickly and with low losses, a current of several amperes has to be applied to control the gate. The gate voltage of an IGB transistor in a conducting state is typically of the order of +15 volts; if the voltage is too low, it may increase conduction losses in the component, whereas a gate voltage that is too high may destroy the component in case of a short-circuit. In a non-conducting state the gate voltage should achieve a negative value of at least 5 to 7 volts to prevent the capacitance between the collector and the gate from affecting the state of the gate in case of a rapid change in the collector voltage.
In change-over switches IGB transistors are usually in pairs and therefore to avoid a breakthrough situation during which the amount of current passing through the components might reach a full short-circuit current, the transistor that is currently on must be turned off before the opposite transistor is turned on. For this reason delays in power components should be as short and stable as possible. This can be achieved by providing the circuit with delay circuits that add what is known as dead time to the gate control of opposite components.
Accelerated gate control typically enables to achieve a decrease of as high as 20% in switching losses, which accounts for 10% of total losses.
The switching losses of IGB transistors depend on how rapidly a gate charge providing full conductivity can be fed to or removed from the component gate. The Miller plateau of an IGB transistor is typically at 10 to 11 volts and therefore the output voltage of the gate driver must be sufficiently high to allow current to be generated through the gate resistor.
It is easy to imagine that with an auxiliary voltage at +15 volts and the Miller plateau at 11 volts, an IGB transistor gate cannot be fed with a particularly high current. In a stationary state an increase in the auxiliary voltage alone may cause the risk of a component breakdown in case of short-circuit.
Although inexpensive gate driver microcircuits provided with a buffered output stage and galvanic separation implemented by means of optoelectronics are available, these circuits do not have a sufficient current supply capacity to control high-power IGB transistors. In addition, they usually have an output stage provided by means of bipolar technology, in which voltage loss in the direction of turn-on may be of the order of 2.5 volts. In other words, the difference to the voltage level of the Miller plateau of the IGB transistor is only 1.5 to 2.5 volts and thus rapid transfer of gate resistance is not possible.
To reduce voltage loss and to increase current supply capacity, the output of the circuits may be provided with a separate power stage, which is usually implemented by means of a p-type MOSFET connected from its source terminal to the positive supply voltage and by means of an n-type MOSFET correspondingly connected from its source terminal to the negative supply voltage. However, a problem that arises is that the gates of the buffer stage FET should be biased so that breakthrough cannot occur. This easily leads to a complicated and expensive end result.
Optically separated control circuits may have a transfer delay of several nanoseconds, and it may depend on the temperature, for example. For this reason dead time must be increased in the IGB transistors to be controlled in order to obtain a sufficient margin of certainty. On the other hand, using an extremely high-speed transformer connection for signal transfer usually increases costs and further complicates the circuit configuration.
Although gate drivers that remove the above problems are commercially available, they are usually very expensive and therefore not applicable to bulk products, such as frequency converters.

Control circuit for semiconductor component


A hydrogen G-cycle rotary vane internal combustion engine has a sodium vapor chamber transferring excess combustion heat into combustion chambers. An active water cooling system captures heat from the engine housing stator, rotor, and sliding vanes and transfers it back into the combustion cycle by premixing it with hydrogen to reduce peak combustion temperature and with an early an late stage combustion chamber injection to help transfer heat from the sodium vapor chamber, to control chamber temperature, and to increase chamber vapor pressure. A combustion chamber sealing system includes axial seals between the rotor and the stator, vane face seals, and toggling split vane seals between the outer perimeters of the sliding vanes and the stator. Sliding vanes reciprocate laterally in and out of the rotor assisted by a vane belting system. A thermal barrier coating minimizes heat transfer and thermal deformation. Solid lubricants provide high temperature lubrication and durability.

The growing demand for oil from various nations around the world is resulting in higher energy prices that have the potential to increase inflation and geopolitical tensions between the nations competing for the same limited oil reserves. Even if the supply of oil could be increased to meet the demand, doing so has the further potential of producing higher CO2 emissions with the possibility of more rapid global warming.
Currently many transportation, oil, and energy companies and governments are investing billions of dollars in hydrogen related research and development programs to produce a fuel source that will gradually replace fossil fuels. For example, many car companies have been developing hydrogen fuel cell vehicles. However, fuel cell durability, efficiency, fuel purity requirements, hydrogen storage, and cost limitations are major implementation barriers.
Automakers are also developing hybrid electrical/internal combustion engine propulsion systems as a transition stage between current internal combustion engine vehicles and future fuel cell vehicles. It is unclear, however, whether hybrid electrical propulsions systems provide high enough value added efficiency benefits to consumers to justify their higher cost.
Converting existing internal combustion engine systems to operate on hydrogen is also not without problems. The combustion temperature for hydrogen is much higher than for gasoline, resulting in high amounts of NOx emissions being formed. Using lean hydrogen fuel mixtures to reduce potential NOx emissions, but also greatly reduces the power output performance levels. Direct hydrogen injection can improve this problem, but the injectors are very expensive and require high pressures and tolerances. The injection pulse provides limited amount of hydrogen fuel making it insufficient for larger power applications. The dryness of the hydrogen gas also makes it more difficult for the pulsing injectors to work and increases injector wear. Moreover, the high diffusiveness of hydrogen gas often results in the hydrogen gas passing through engine sealing systems into crank shaft regions, resulting in very undesirable combustion that can damage the engine and/or ignite the oil lubricant.

Hydrogen G-cycle rotary internal combustion engine


An aircraft landing gear assembly comprises a four bar linkage arranged to be pivotably attached to an aircraft fuselage and movable between a deployed position and a retracted position, wherein when in the retracted position at least a first portion of the landing gear assembly is housed within a wing at the aircraft.

For larger civil or military aircraft it is conventional practice for the aircraft to have a single landing gear assembly located in the nose of the aircraft and a matched pair of landing gear assemblies located on either side of the aircraft in the proximity of the wing roots. The latter landing gear is generally termed the main landing gear assembly. It is conventional practice for both the nose landing gear assembly and main landing gear assembly to be arranged to be movable between a deployed position and a stowed position.
When the main landing gear is in the deployed, down, position it is beneficial for the distance between the pair of landing gear assemblies (the "track") to be as wide as possible, since this maximises the stability of the aircraft on the ground during taxiing and runway manoeuvres. A well known way to achieve a wide track for the main landing gear is to mount each main landing gear assembly in each of the respective wings and to arrange for the main landing gear assemblies to retract to their stowed positions within the wing body and in some cases also partially within the fuselage body. However, for large aircraft, such as a commercial passenger airliners or freight aircraft, this results in relatively large loadings being transferred from the main landing gear assemblies into the wing structures. This requires the wing structures themselves to often be larger and heavier to carry these loads than would otherwise be required purely for the aerodynamic loading of the wing. Apart from the undesirable increase in weight, the increased wing structures also reduces the amount of space available within the wing structure for use in packaging wing service actuator systems (e.g. flaps), electrical systems, fuel tanks and ultimately space to stow the landing gear itself.
Another arrangement for the main landing gear that avoids placing large loads through the wing structures is the well known alternative of using body mounted landing gear, in which the main landing gear assemblies are mounted within the fuselage of the aircraft and are arranged to be stowed also within the aircraft fuselage. However, in order to maximise the landing gear track for body mounted landing gear assemblies it is known to use cantilevered main landing gear assemblies that position the actual wheels of the landing gear towards, if not beyond, the far extremities of the aircraft fuselage and with the wheels of the landing gear assemblies being further apart than the points at which the landing gear assembly is pivotably connected to the fuselage. As a corollary to this, such arrangements of main landing gear tend not to be capable of being housed in their stowed position completely within the nominal outline of the main fuselage and require a fuselage belly fairing, which is an enlarged area of the lower part of the fuselage, to enclose the landing gear in the stowed position. For larger belly fairings this can be detrimental to the overall aerodynamics of the aircraft, thus reducing the aircraft's theoretical performance. Additionally, the large belly fairings give rise to relatively large landing gear bay doors that must be arranged to fold out of the way when the landing gear is deployed. The large landing bay doors can limit the size of the movable wing surfaces closer to the junction between the wing and fuselage, again reducing the theoretical aerodynamic performance of the aircraft. In addition, since the landing gear assembly is stowed within the aircraft fuselage, this space cannot be used for other purposes, such as cargo stowage.
The main landing gear assembly arrangement of the present invention seeks to at least mitigate some of these problems.


A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.

According to a conventional network system, a client node makes an inquiry to another node group about processing performance and an intention to participate; based on the response from the other node group, determines nodes capable of accepting job processing; distributes and requests execution of the job; and totals the results of the job processing. According to another network system that includes many subscribers, a processor unit, and a switching device executing communication between the subscribers and the processor unit, is equipped with a distributed processing processor unit that enables each of processors in the processor unit to be accessed (see, for example, Japanese Laid-Open Patent Publication Nos. 2006-201896 and 2003-235083).
However, in the case of a system that executes parallel processing using terminals capable of wireless communication, when a terminal moves, the state of objects that momentarily block signals varies. As a result, communication quality may be degraded. For example, even when the communication quality is excellent at the start of the parallel processing, during the parallel processing: the communication quality may be degraded; communication may take a significant amount of time and may not be able to be continued. In this state, problems arise in that a tremendous amount of time is consumed for the parallel processing to be completed and the parallel processing may not be able to be completed.

Data processing method and data processing system


A method of ultrasound nonlinear imaging with high-bit Golay code excitation includes transmitting a first, a second, a third and a fourth Golay code signal wave which have more than four bits and are orthogonal pairs to each other; making the second and the forth Golay code signal wave be subtracted from the first and the third Golay code signal wave respectively to eliminate noise interference wave; performing compression filtering process to the above generated waves and taking a cross sum to generate two compressed code waves; taking the difference between the two compressed code waves to generate an image wave which includes at least two second-order harmonic waves; processing ultrasound nonlinear imaging by using the second-order harmonic waves and to generate an ultrasound image.

Traditional ultrasound imaging method adopts linear scattered fundamental signal to image. However, the fundamental signal is susceptible to phase aberration due to the presence of fat layer in the shallow tissue or skin and will result in low imaging quality. As the sound wave is traveling in human tissues during the imaging process, the wave signal will have finite amplitude distortion or generate harmonic signals when encountering strong nonlinear medium such as microbubble contrast agents. When processing tissue imaging, because the magnitude of harmonic signals is lower than the fundamental signal in the beginning, the scattered harmonic signal will suffer from less phase aberration when penetrating the shallow tissue. Thus, tissue harmonic imaging can provide better contrast resolution because it is less susceptible to phase aberration and thus is broadly used in clinical diagnosis.
The contrast agents being used for harmonic imaging are composed of microbubbles. These small bubbles will have harmonic oscillation to generate lots of strong harmonic signals back to the probe when being excited by sound waves. Clinically, the contrast agents are injected into the blood vessel such that the blood vessel would be filled with micro bubbles to strengthen harmonic signals so as to generate a clearer image of blood vessel structure and blood perfusion. That is, the image contrast is enhanced.
A major difference between ultrasound fundamental signal and harmonic signal is the frequency range of echo signal. If the central frequency of the ultrasound signal travelling into the human body is f0, the imaging method using the frequency signal f0 of the echo signal is called fundamental imaging, but the imaging method using the harmonic signals with higher frequency, such as 2f0, 3f0, is called harmonic imaging. Because these harmonic signals are originated from the nonlinear reaction of the medium to the emitted ultrasound signal, harmonic imaging can be also regarded as nonlinear imaging. As mentioned, it is understood that by using a low frequency filter or high frequency filter to select the frequency range to be received, it is capable to decide whether fundamental imaging or harmonic imaging is performed. The discussion focuses on the analysis of components of second harmonic signal because the second harmonic signal is the strongest one among the various harmonic signals.
Although harmonic imaging is of great importance in clinical diagnosis due to better imaging quality, its weak signal intensity is a major drawback and may significantly degrade imaging sensitivity and penetration. Generally speaking, harmonic signal can be at least 20 db weaker than the fundamental signal even at the focus. Thus, there have been some researches and inventions focusing on using code excitation to enhance harmonic wave intensity. Among the various coding technologies, Golay code is easy to use and is quite applicable to code excitation. Golay code is performed by phase coded sequence. That is, the emitted signal has the phase 0° is represented by the symbol [1], the emitted signal has the phase 90° is represented by the symbol [j], the emitted signal has the phase 180° is represented by the symbol [−1], and the emitted signal has the phase 270° is represented by the symbol [−j]. Golay code featuring phase coding can be easily implemented on the hardware. However, Golay code excitation needs two emitting processes A and B to generate the corresponding echo signals complementary to each other. That is, the autocorrelation results of the two echo signals can be summed to totally remove the sidelobe interference.
Multi-frequency excitation has been developed in ultrasound nonlinear imaging. The feature of multi-frequency excitation is to emit multiple frequency components rather than single frequency component. If only considering the second-order nonlinear components, the ultrasound nonlinear signals generated by multi-frequency excitation will include the second harmonic signals of each emitting frequencies and the inter-modulation signal between the emitting frequencies. Thus, in addition to the second harmonic signals being used in typical harmonic imaging, the inter-modulation signals can also be used for generating image. However, multi-frequency excitation using Golay code excitation for imaging will result in incorrect coding of some harmonic wave components, such as second-order harmonic wave and fourth-order harmonic wave. These incorrectly coded components will interfere with the correctly coded signals to cause degradation in imaging quality.
Take nonlinear imaging using two-bit dual-frequency Golay excitation as an example, it is capable to have the frequency components f2−f1 and 2f1 of the second-order harmonic wave showing the correct code [1, −1] during emission A and the correct code [−1, −1] during emission B as shown in the following table. The above mentioned frequency components of the second-order harmonic wave are usually within the pass band of the probe and thus serve as the major signal components for imaging.
Transmit2nd-order Harmonic4th order HarmonicFrequencyf1f2f2 − f12f1f2 + f1f2 − f12f1f2 + f1Golay code[1, j][1, −j][1, −1][1, −1][1, 1][1, 1][1, −1][1, −1][1, 1][1, 1](Emission A)Golay code[j, j][−j, −j][−1, −1][−1, −1][1, 1][1, 1][−1, −1][−1, −1][1, 1][1, 1](Emission B)
However, as shown in this table, it is understood that among the other harmonic wave components, component f2+f1 of the second-order harmonic wave and components f2−f1 and 2f1 of the fourth-order harmonic wave may not accord with the designed Golay code. The codes are all [1, 1]. These frequency components with incorrect code will result in unremovable sidelobe signals during the compression process and the method nowadays cannot effectively resolve this problem.

Method of ultrasound nonlinear imaging with high-bit golay code excitation


A hybrid vehicle 10 including a power take off assembly 20 which is selectively and solely operated by the cooperative combination of a battery 22 and a motor 16 with the amount of electrical charge which is resident within the battery 22 is depleted by a certain amount. Upon such depletion, the internal combustion engine 12 is activated to provide electrical charge to the battery 22.

The present invention generally relates to a hybrid vehicle and more particularly, to a hybrid electric vehicle having a power take off portion which is operated by a vehicle battery which selectively receives electrical charge from an internal combustion engine.
Hybrid electric vehicles typically include an internal combustion engine and an induction motor (or another type of energy source) which are each respectively adapted to selectively provide torque or rotational energy to a driveshaft. The induction motor is typically operated by the use of an electrical battery.
A hybrid electric vehicle may further include a xe2x80x9cpower take offxe2x80x9d assembly which allows a portion of the provided torque or rotational energy which is coupled to the driveshaft to be used to operate a variety of auxiliary or utility type of assemblies (i.e., a xe2x80x9cliftxe2x80x9d assembly). Such a hybrid electric vehicle could be used, for example and without limitation, by a wide variety of business enterprises such as an electrical utility enterprise and/or a telephone enterprise which selectively and respectively employs these power take off assemblies to power or operate a lift assembly, effective to place an individual in close proximity to a portion of a telephone or power system which is to be repaired or serviced. Other business enterprises may use these power take off assemblies to perform a variety of other operations (e.g., selectively moving a tilt bed).
While hybrid electric vehicles do allow for the selective operation of these power take off assemblies, they require the concomitant and continued operation of an internal combustion engine which xe2x80x9cpowersxe2x80x9d or operates the various assemblies. The internal combustion engine therefore continuously creates undesired noise and undesirably increases overall fuel consumption. Such noise generation is of particular concern to homeowners and other individuals in close proximity to one of these prior vehicles since these power take off assemblies are typically operated for a relatively long period of time in order to allow a necessary repair or other operation to be completed.
There is therefore a need for a hybrid vehicle having a power take off assembly which overcomes at least some of the previously delineated drawbacks associated with the power take off assemblies of prior hybrid vehicles.
It is a first object of the present invention to provide a hybrid vehicle which overcomes some or all of the previously delineated drawbacks of prior hybrid vehicles.
It is a second object of the present invention to provide a hybrid vehicle which overcomes some or all of the previously delineated drawbacks of prior hybrid vehicles and which selectively and quietly operates a power take off assembly.
It is a third object of the present invention to provide a hybrid electric vehicle which overcomes some or all of the previously delineated drawbacks of prior hybrid electric vehicles and which includes a power take off portion or component which is cooperatively operated by a battery and an induction motor.
It is a fourth object of the present invention to provide a method for operating a power take off assembly which overcomes some or all of the previously delineated drawbacks of prior methods.
According to a first aspect of the present invention, a hybrid vehicle is provided. The hybrid vehicle comprises a first source of energy; a second source of energy; a power take off assembly; a controller which is coupled to the first source of energy, to the second source of energy, and to the power take off assembly and which causes the first source of energy to selectively and solely operate the power take off assembly until the first source of energy is depleted by a certain amount and then which causes the second source of energy to provide energy to the first source of energy.
According to a second aspect of the present invention, a power take off assembly for use within a hybrid vehicle of the type having a first and a second energy source is provided. The power take off assembly comprises a power take off portion; and a controller which is coupled to the first and second energy sources and which selectively causes the power take off portion to be solely operated by the first energy source while allowing the second energy source to be operated only when a certain amount of energy has been depleted from the first energy source.
According to a third aspect of the present invention, a method for operating a power take off assembly by the use of a pair of energy sources is provided. The method comprises the steps of operating the power take off assembly by use of a first of the pair of energy sources while temporarily deactivating the second of the pair of energy sources and then activating the second of the pair of energy sources to provide energy to the first of the pair of energy sources.
These and other features, aspects, and advantages of the present invention will become apparent from a reading of the following detailed description of the preferred embodiment of the invention and by reference to the following drawings.


An apparatus includes: a latent image carrier which is freely rotatable in a predetermined sub scanning direction; a latent image carrier gear which is attached to an end portion of the latent image carrier; a drive motor which applies drive rotation force upon the latent image carrier via the latent image carrier gear and which rotates the latent image carrier; a line head which forms on the latent image carrier a line latent image which extends in a main scanning direction which is approximately orthogonal to the sub scanning direction; an exposure controller which provides an image signal to the line head and controls writing of the line latent image; a phase detector which detects the phase data regarding the latent image carrier gear; and a timing controller which adjusts the write location of the line latent image on the latent image carrier based on the phase data detected by the phase detector.

1. Technical Field
The present invention relates to an image forming apparatus which has a line head, and a control method for such an apparatus. The apparatus forms line latent images using the line head, develops the latent images with toner and accordingly forms an image.
2. Related Art
Known as an image forming apparatus which uses a line head in which light emitting elements such as light emitting diodes (LEDs) are arranged in rows is the image forming apparatus. The apparatus is described in JP-A-6-177431 for instance. In this apparatus, a latent image carrier such as a photosensitive member drum is driven into rotations in a sub scanning direction. A line head is disposed facing the photosensitive member drum. In this line head, plural light emitting elements are arranged in rows along a main scanning direction which is approximately orthogonal to the sub scanning direction. The elements turn on and off under control in response to an image signal. In consequence, a line latent image corresponding to the image signal is formed on the photosensitive member drum. In this manner, the light emitting elements are driven in response to an image signal covering one line while rotating the photosensitive member drum, whereby a line latent image is written. A two-dimensional latent image is thus formed on the photosensitive member drum. As the two-dimensional latent image is developed with toner, an image is formed.
Some use a line head which is comprised of multiple organic EL (electroluminescence) elements (See JP-A-2003-19826.). In such line heads, the multiple organic EL elements are arranged in rows (in a two-row staggered pattern) along the main scanning direction which is approximately orthogonal to the sub scanning direction. The elements turn on and off under control in response to an image signal. As a result, a line latent image corresponding to the image signal is formed on a photosensitive member drum.

Apparatus for forming latent image using line head and control method for such apparatus


A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.

Financial transactions are beginning to be offered in wired networks, such as the world wide web, and are desirable in wireless networks, such as paging networks and cellular networks. The need for secure communication of financial transactions is paramount in order for them to be successfully used in such environments. Methods of providing the needed security include the use of finite field arithmetic, such as Galois Field (GF) arithmetic, for encryption and decryption of secure messages. For optimal speed of calculations using Galois Field arithmetic, Galois Field arithmetic logic units (ALUs) that are designed especially for Galois Field arithmetic are employed. One implementation of a Galois Field ALU is a special-purpose ALU that implements addition (subtraction), squaring, multiplication, and inverse in a finite field. A specific Galois Field typically used is a field with 2.sup.M elements, denoted by GF(2.sup.M). Herein, M is called the field size. Any element in the field (there are 2.sup.M total) can be represented as an M-bit binary string. This field is closed under all of the above operations. Closed essentially means that the result of performing any of these arithmetic operations always is another element in the field.
An example of a prior art Galois Field ALU is described herein as one which provides the functions of Galois Field addition (GF addition), GF squaring, and GF multiplication. Other functions, such as the important function of finding a GF inverse (GF inversion) can be performed using combinations of one or more of the three functions of GF addition, GF squaring, and GF multiplication. Examples of an ALU providing these three functions are described herein using a GF(2.sup.6), which has 64 elements. Each of the 64 elements in the GF(2.sup.6) is preferably represented by a unique 6 bit pattern. (There are exactly 64 unique patterns possible.)
FIG. 1 is an electrical block diagram of a prior art GF ALU 100 of size M=6 that shows the GF ALU 100 configured for the GF addition function. The GF ALU 100 comprises an A field element register 105 and a B field element register 110 which are input registers, a C field element register 115, which is a result field element register, and logic gates 130. The A, B, and C field element registers 105, 110, 115 each comprise, respectively, six single bit registers 120, that are identified as single bit registers A0' to A5', B0' to B5', and C0' to C5', each comprising a conventional D input 121, a conventional Q output 122, and a conventional clock input 123. The A, B, and C field element registers 105, 110, 115 further comprise six switches 135, having one switch coupled to each D input 121. The GF ALU 100 comprises logic gates other than logic gates 130, and the switches 135 have inputs other than those shown in FIG. 1, as will be described with reference to FIGS. 2 and 3. A control signal (not shown in FIGS. 1-6) that is coupled to each of the switches selects one of the inputs to each switch in a conventional manner, depending on the configuration needed to perform the desired function, and couples the selected input to the D input of the associated single bit register 120. FIG. 1 shows a configuration of the GF ALU 100 after the single bit registers 120 of the A and B field element register 105, 110 have been loaded with bits A0-A5 and B0-B5 of first and second GF elements. (The bits are coupled to the switches 135 by paths not shown in FIG. 1.) Thus, the values at the Q outputs 122 of the A and B field element registers 105, 110 have the values A0-A5 and B0-B5 that have been loaded.
The outputs 122 of the single bit registers 120 of the GF ALU 100 are logically combined in different manners to perform the three functions cited above. The logical combination is provided by the logic gates 130, the inputs to the logic gates 130 from the single bit registers 120, which are identified by the values A0-A5 and B0-B5 shown at outputs of the single bit registers 122 and at the inputs 129 to the logic gates 130, and a coupling of outputs 131 of the logic gates 130 to the single bit registers 120 of the C field element register 115. In the case of this GF addition function, the logic gates 130 are all conventional Boolean Exclusive OR gates. An output 131 of each of the Boolean Exclusive OR gates 130 is coupled to a D input of one of the single bit registers 120 of the C field element register 115 through one of the switches 135. The coupling of the logic gates 130 is such that when a clock cycle is coupled to the clock inputs 123 of the C field element register 115, the outputs C0-C5 of the C field element register 115 are given by the following equations: EQU C0"=A0+B0 EQU C1"=A1+B1 EQU C2"=A2+B2 EQU C3"=A3+B3 EQU C4"=A4+B4 EQU C5"=A5+B5
After being clocked, the outputs C0"-C5" of the C field element register 115 are those of a GF element that is the GF addition of the A field element and the B field element. In all equations shown herein, the addition operation (+) is implemented by the Boolean Exculsive OR function.
FIG. 2 is an electrical block diagram of a prior art GF ALU 100 that shows the GF ALU 100 configured for the GF squaring function. The GF ALU 100 comprises the A, B, and C field element registers 105, 110, 115, the switches 135, and the logic gates 130 (not shown in FIG. 2). As in the case of the GF addition function described with reference to FIG. 1, the single bit registers 120 of the A field element register 105 have been loaded with bits A0-A5 of a first GF element and the single bit registers 120 of the B field element register 110 have been loaded with bits B0-B5 of a second GF element. The switches 135 control the intercoupling of the single bit registers 120 of the A field element register 105 such that the outputs of each of the single bit registers 120 are coupled to a single bit register 120 of a next higher order (as indicated by a next higher number in the identifiers; e.g., A2' is coupled to A3') of the single bit registers 120. A first clock cycle is applied to the single bit registers 120 of the A field element register 105, which shifts the values that had been loaded to the single bit registers 120 of a next higher order, except for the value in single bit register A5' 120, which is shifted into single bit register A0' 120. The registers are identified with the prime indication to signify that their contents is not necessarily equal to the originally loaded input values (which are designated without the prime indication). The outputs of the single bit registers 120 are also indicated with the prime designation for the same reason. In this squaring configuration of the GF ALU 100, the switches 135 on the D inputs to the single bit registers 120 of the C field element register 115 are controlled such that the outputs A0'-A5' of the single bit registers 120 are coupled to the D inputs 120 on a one for one basis. When a second clock cycle is coupled to the clock inputs 124 of the C field element register 115, the outputs C0-C5 of the C field element register 115 are given by the following equations: EQU C0"=A0'=A5 EQU C1"=A1'=A0 EQU C2"=A2'=A1 EQU C3"=A3'=A2 EQU C4"=A4'=A3 EQU C5"=A5'=A4
The Q outputs of the C field element register 115, comprising the Q outputs C0"-C5", is the squared result of the original input to the A field element register 105. The GF ALU 100 can also be configured to square the GF element B, loaded in the C field element register 115, by control of the switches 135. In alternative embodiment, the output of the GF ALU 100 is generated directly from the A field element register 105 (or the B field element register 110), avoiding a need for the second clock cycle to obtain the result.
It will be appreciated that in general, for Galois Fields of size M, if the Galois Field can be represented in an optimal normal basis, there is a set of GF multiply equations comprising M equations in which each has 2M-1 terms, as is well known to one of ordinary skill in the art. When a multiply function is performed by the GF ALU 100, the values of C0-C5 that must be obtained are given by the GF multiply equations, which are shown below for a Galois Field of size 6: EQU C0=A0B1+A1(B4+B0)+A2(B3+B4)+A3(B2+B5)+A4(B2+B1)+A5(B5+B3) EQU C1=A1B2+A2(B5+B1)+A3(B4+B5)+A4(B3+B0)+A5(B3+B2)+A0(B0+B4) EQU C2=A2B3+A3(B0+B2)+A4(B5+B0)+A5(B4+B1)+A0(B4+B3)+A1(B1+B5) EQU C3=A3B4+A4(B1+B3)+A5(B0+B1)+A0(B5+B2)+A1(B5+B4)+A2(B2+B0) EQU C4=A4B5+A5(B2+B4)+A0(B1+B2)+A1(B0+B3)+A2(B0+B5)+A3(B3+B1) EQU C5=A5B0+A0(B3+B5)+A1(B2+B3)+A2(B1+B4)+A3(B1+B0)+A4(B4+B2)
In the equations shown herein, the product operation is implemented by the Boolean AND function. No symbol is used for the Boolean AND function in the equations--the normal convention of adjacency of two symbols indicates a Boolean AND function of adjacent symbols. It will be appreciated that the above equations could be implemented using a purely combinatorial logic configuration that could be accomplished by sixty 2 input Boolean Exculsive OR gates and thirty 2 input Boolean AND gates. However, this is logic gate intensive and would take up a lot of circuit area, so an alternative has been devised, which is illustrated in FIG. 3.
FIG. 3 is an electrical block diagram of a prior art GF ALU 100 that shows the GF ALU 100 configured for the GF multiply function. The GF ALU 100 comprises the A, B, and C field element registers 105, 110, 115, the switches 135, the logic gates 130 (not shown in FIG. 3), and logic gates 140. As in the case of the GF squaring function described with reference to FIG. 2, the single bit registers 120 of the A field element register 105 are initially loaded with bits A0-A5 of a first GF element and the single bit registers 120 of the B field element register 110 are initially loaded with bits B0-B5 of a second GF element. The switches 135 control the couplings of the Q outputs 122 of each of the single bit registers 120 of the A field element register 105 and the B field element register 110 are coupled to a D input 121 of a single bit register 120 of a next higher order of the respective field element register 105, 110. The logical combination of this multiplying configuration of the GF ALU 100 is provided by the intercoupling of the logic gates 140, by inputs 129 to the logic gates 140 from the single bit registers 120 (which are identified by the values A0'-A5' and B0'-B5' shown at the Q outputs 122 of the single bit registers 120 and at the inputs 129 to the logic gates 140), and a coupling of outputs 141 of the logic gates to the single bit registers 120 of the C field element register 115. In the case of this GF multiply function, the logic gates 140 are conventional Boolean Exclusive OR and AND gates. An output 141 of each of the Boolean Exclusive OR gates 140 is coupled to a D input of one of the single bit registers 120 of the C field element register 115 through one of the switches 135. The logic gates 140 are intercoupled such that when a clock cycle is coupled to the clock inputs 123 of the C field element register 115, the outputs C0"-C5" of the C field element register 115, which are intermediate outputs until a last clock cycle is completed, are given by the following equations: EQU C0"=A0'B1'+C5' EQU C1"=A2'(B5'+B1')+C0' EQU C2"=A4'(B5'+B0')+C1' EQU C3"=A0'(B5'+B2')+C2' EQU C4"=A2'(B0'+B5')+C3' EQU C5"=A4'(B4'+B2')+C4'
In these equations, the single prime notations indicate prior values; that is, the values prior to the clock cycle that generates the double prime values. The single bit registers 120 C0'-C5' are initially loaded with Boolean 0's.
It will be appreciated that the terms of the logical combination for each intermediate value C0"-C5" are the respective term of the GF multiply equations, plus a feed forward term that is the next less significant intermediate value, in a cyclical sense. Thus, for example, C3" is given by the third term of the C3 equation in the GF multiply equations, A0'(B5'+B2'), plus C2'.
It will be further appreciated that when all the single bit registers 120 are clocked simultaneously for six consecutive clock cycles, a GF multiply function is completed and the outputs C0"-C5" after the sixth clock cycle will have the values given by the GF multiply equations for GF(2.sup.6) shown above, shifted by one position (thus, the result for C0 is in C5', the result for C1 is in C0', etc.).
This approach has the advantage of substantially reducing the number of logic gates needed to eleven two input Boolean exclusive OR gates and six Boolean AND gates, but it has a disadvantage of requiring six clock cycles. This decrease in speed is particularly problematic in security related applications because of the number of times the multiply function must be used. It will be appreciated that the speed decrease of the technique used in FIG. 3 is directly proportional to the size, M, of the GF multiply function. In contrast, although the purely combinatorial logic approach is fast, requiring only one clock cycle to load the result into the C field element register, it requires a number of two input logic gates that exceeds 2M.sup.2.
Thus, what is needed is a circuit that performs the GF multiply function more speedily than the circuit described with reference to FIG. 3, but without the large number of gates described above with reference to the purely combinatorial logic approach.

Galois field arithmetic logic unit circuit


A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.

In a digital device, when a clock signal is defective or unstable, a system may malfunction. A bad connection of a portable terminal and distortion of data transmitted from a facsimile are mostly attributed to instability of a clock signal. The clock signal may be used as an operation source of a digital circuit serves as the core of the circuit. Therefore, frequency accuracy and stability are requirements of the clock signal. Their importance is increasing along with an increased demand for high-speed computation and fast processing. Moreover, the role of the clock signal is so significant to fields requiring reliability, such as communication equipment, that double or multiple clock signals are used for a normal operation in case one clock generation source has errors.


Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the compacted test response includes one or more compacted test response values that are dependent on one or more respective unknown values. The compacted test response is filtered to remove the dependency of at least some of the compacted test response values on the one or more respective unknown values, and a filtered test response is output. Various filtering circuits and testing systems are also disclosed.

As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee high fault coverage while minimizing test costs and chip area overhead have become essential. The number of transistors that can be placed on a chip has been doubling roughly every eighteen months, as predicted by Moore's law. The amount of data required to test such massively complex chips has been increasing even more rapidly. In practical terms, for very large integrated circuits, the test cost is approaching (and may even exceed) the design cost. To address the rapid increase in volume of test data, a number of compression schemes have been developed.
Many integrated circuits are tested using structured design-for-testability ("DFT") techniques, which employ the general concept of making some or all state variables (for example, memory elements, such as flip-flops and latches) directly controllable and observable. Preferably, a circuit is treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology assumes that during testing all (or almost all) memory elements are connected into one or more shift registers termed "scan chains." See, for example, U.S. Pat. No. 4,503,537.
A circuit that utilizes scan chains for testing typically has two basic modes of operation: a normal mode and a test (or scan) mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of scan chains. These scan chains are used to shift test patterns into the circuit and to shift out circuit responses to the test patterns (referred to as "test responses"). The test responses can then be compared to fault-free responses to determine if the circuit-under-test ("CUT") works properly.
Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation ("ATPG") and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns and expected test responses) that guarantee almost complete fault coverage of several types of fault models including stuck-at and transition faults. It is also possible to target other fault models, such as path delay and bridging faults. As part of ATPG, unknown states (sometimes referred to as "X" states or "unknowns") in the test responses that are created upon application of one or more of the test patterns to the circuit-under-test are identified. Thus, the expected test responses may contain one or more unknown values. Unknown values typically result from limitations of simulation technology that cannot accurately predict the logic values of certain signals in a circuit during simulation. Because the actual logic values that these signals will assume in a manufactured circuit cannot be determined during simulation, the signals are designated as unknowns.
One type of scan design methodology that has gained widespread adoption is termed "full scan" and does not utilize any type of decompression or compression technique to reduce the size of the test data being sent and received by the external test hardware. Although full scan enables high test quality, the cost of full scan testing has become prohibitive because the number of scan cells in designs is increasing while the number of chip test pins and tester channels that can be used for scanning in and scanning out are limited. To compensate for this limitation, longer scan chains are typically used, implying larger test data volumes and longer chain load-unload times.
To overcome these issues, several test data compression techniques can be used that involve breaking long scan chains into a large number of shorter chains. To access the shorter chains using a relatively small number of test pins, test data decompression hardware (referred to herein as a "decompressor") is typically used on the input side of the CUT. Similarly, to reduce the number of test output pins, a test response compactor is used on the output side of the CUT to receive the test responses and to compact the responses, thereby producing "compacted test responses."
FIG. 1 shows an example of such a configuration. In particular, FIG. 1 is a block diagram of a system 100 for testing digital circuits with scan chains and compression hardware. During a typical scan mode, external automated test equipment ("ATE") or tester 102 applies a set of compressed test patterns 104 to a CUT 106 via input test pins 114. The compressed test patterns are input into a decompressor 110, which decompresses the compressed test patterns into the test patterns that are applied to the scan chains 108 within the CUT 106. Typically, the test patterns comprise a number of deterministically specified bits targeting one or more defects, and thus are termed "deterministic test patterns." Examples of compactors as may be used in the system 100 are described, for instance, in J. Rajski et al., "Embedded deterministic test for low cost manufacturing," Proc. IEEE International Test Conference, pp. 301-310 (2002). Once the scan chains 108 have been loaded with a decompressed test pattern, the CUT 106 is run in normal mode using the test patterns for input values. The CUT 106 may be run for a designated period of time (for example, one clock cycle) after which the circuit response to the test pattern (the test response) is captured and stored in the scan chains 108. With the circuit again in scan mode, the test response is clocked out of the scan chains 108 and into the compactor 112. The compactor 112 produces a compacted version of the test responses (in space, time, or both space and time), which is routed back to the tester 102 through output test pins 116. The tester 102 compares the compacted test responses 118 to expected, fault-free, versions 120 of the compacted test responses. From this comparison, a determination can be made as to whether the CUT 106 is operating as expected (for example, producing a "go" signal at node 122), or is not operating as expected (for example, producing a "no go" signal at the node 122).
Currently available test response compaction schemes can be grouped into three classes: (1) infinite input response compaction schemes (also known as "time compactors"); (2) finite memory compaction schemes; and (3) space compaction schemes (also known as "spatial compactors," "linear compactors," or "space compactors").
Time compactors typically have a feedback structure with memory elements for storing a signature, which represents the results of the test. After the signature is completed, it is read and compared to a fault-free signature to determine if an error exists in the circuit-under-test. Time compactors, for example, may use polynomial division, counting-based techniques, and check-sum-based methods, and are typically employed in built-in self-test (BIST) applications. The actual compaction is usually performed by linear finite state machines, such as a linear feedback shift register ("LFSR"), a MISR, or cellular automata. In general, time compactors cannot handle unknown states in a test response. For example, because these systems include feedback, an unknown state will circulate in the compactor endlessly until the compactor is reset. Thus, all states can become unknown after a few cycles, thereby corrupting the test signature and rendering the test useless.
Finite memory compactors are compactors that have memory but produce a finite response to a test response vector. Thus, for example, test response values that are input into the compactor can be clocked completely out of the compactor after a finite period of clock cycles and before an entire test response is loaded or an entire signature is output. Examples of such compactors are described in further detail in U.S. Published Patent Application No. 2004/0230884 entitled "Compressing Test Responses Using a Compactor," which is hereby incorporated herein by reference.
Space (or spatial) compactors comprise combinational circuits that are often predominantly built from XOR (or XNOR) networks and do not typically contain memory elements or any feedback structure. (Note, however, that a space compactor with memory elements inserted for pipelining purposes is still considered to be a space compactor). Spatial compaction networks are generally configured to generate m compacted test outputs from n scan chain outputs of the CUT, where m<n.
Space compactors typically offer smaller compaction ratios than time compactors, but are generally better suited to handle unknown states in a test response. For example, some spatial compaction schemes use coding theory to guide the design and implementation of the compactor. Such compactors are referred to generally as compactors using error correcting codes (ECC) or ECC-based compactors. However, in order to use ECC-based compactors in the presence of unknown values and to still detect an error, enhanced ATE support is usually needed (for example, for each scan out cycle, one might need to compare the compacted response to several different possible correct responses). This is not easily done in a conventional scan test environment. Alternatively, proper error detection may require post-processing, off-chip analysis of test responses in order to determine if they passed or failed. This can be problematic in "go/no-go" production testing, and can also increase the test time because storing test responses on a tester is slower than just comparing responses on chip pins.
In order to address these issues, one can expend more on chip as well as in tester data resources. One way to do this is to use specialized codes for designing the compactor that segregate the unknowns from the error information in the compacted response. However, creating such specialized codes can be extremely difficult, especially for multiple unknowns. In one known approach, referred to herein as the X-Compactor approach, for example, special codes to handle only a single unknown are presented. See Mitra, S., et al., "X-Compact: An Efficient Response Compaction Technique," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol, 23, no. 3 (March 2004). Creating codes for handling more than one unknown requires solving an NP-complete problem. Moreover, approaches using these specialized codes, such as the X-Compactor approach, require many more output pins than other compactors using ECC. Consequently, the output response data storage requirement and the memory requirements on the ATE are significantly increased. The use of additional output pins to handle unknowns can be undesirable because only a fraction of the shift cycles ordinarily contain unknown values.
Another way to achieve the above objective is to mask the output response bits that are unknowns before compaction. This method typically does not increase the number of output pins, but requires additional input pins to pass the information concerning the location of the unknowns ("X" values) in the test response to the masking hardware. So, in order to mask up to x unknowns, the masking logic will require xlogn inputs (where n is the number of bits in the uncompacted test response). Once the unknown values are masked, the test response can be compacted using "off-the-shelf" error correcting codes. Because masking is done before the test response is compacted, however, this approach requires O(nx) additional hardware.

This patent is subject to a terminal disclaimer.

Removing the effects of unknown test values from compacted test responses


A showerhead engine includes a first plate joined to a second plate with a cavity therebetween. Water enters the cavity through an angled hole in the first plate and flows in a swirling motion about the central axis. A paddle wheel is spun within the cavity by the swirling water. A notched cutout in the paddle wheel forms an exit passage through a through hole in the second plate allowing the water to exit when the notched cutout lines up with slots in the second plate. The revolving paddle wheel continues to revolve thereby revolving the notched cutout and producing a revolving spray pattern.

Showerhead engines are used to provide a unique showering experience. Showerhead engines may be configured to produce a wide array of spray patterns and features. For example, many showerhead engines are designed to minimize water consumption. Water consumption is typically minimized with introduction of an orifice restrictor in the water inlet path or the outlet.
A known issue with restricting the water inlet is that a longer shower is needed to thoroughly wet and rinse an area. This increased time in the shower duration is perceived as a great inconvenience to the user.
A known issue with restricting the water outlet is that the water droplets formed are very small, thereby losing thermal energy in the process due to the increased surface area of the fine droplets and contact with the surrounding air.
Yet another known issue with showerhead engines is that many small parts are required, thereby increasing the mechanical complexity of the engine. This increased complexity increases the cost and the potential for a failure due to scale build-up or mechanical failure.
What is therefore needed is a showerhead engine that restricts water flow while providing a comparable shower experience as a higher flow rate showerhead. What is also needed is a showerhead engine that wets a similar area as a higher flow rate showerhead. Finally, what is needed is a showerhead engine that addresses the known issues without complex parts.


A band gap discontinuity is propagated across a Photonic Crystal (PC) to capture thermal energy in a region near the primary emission wavelength of the Planck spectral distribution and transfer that energy to a different spectral region where it is emitted. To extend the range of frequency shifting beyond the width of a single band gap, the intrinsic control parameters (e.g., lattice geometry factors, scattering element geometric factors, and variations in the index of refraction) are spatially varied across the PC to form a band gap gradient. Propagation of the band gap discontinuity, starting in the infrared wavelength region where the thermally generated electromagnetic energy is concentrated and propagating towards the long wavelength region, locally captures the thermal electromagnetic radiation, shifts it downwards in frequency, and pushes the lower-frequency thermal electromagnetic radiation on to the next region. The same principles apply to shift the frequency to shorter wavelengths. A PC-based power combining and waveguide structure can be constructed in the same or a surrounding structure to combine and guide the shifted radiation to an antenna or exit aperture.

1. Field of the Invention
This invention relates to the use of Photonic Crystals as a source of electromagnetic radiation at THz or other frequencies, and more specifically to dynamically propagating a band gap discontinuity through a Photonic Crystal to modify the spectral distribution of thermal electromagnetic radiation.
2. Description of the Related Art
At quite modest temperatures, small objects possess significant free energy, which is emitted in the form of thermal electromagnetic radiation across a broad spectral band, including visible, infrared (IR), THz, etc. For a perfect blackbody emitter, the thermal electromagnetic radiation follows the Planck spectral distribution 10 shown in FIG. 1. The blackbody emitter has a primary emission wavelength (peak) 12 in the IR band around 5-10 μm, depending upon temperature. Common materials can have more complex emission spectra, but always maintain the Planck distribution as an upper limit to emission peaks rather than being distributed evenly across all frequency bands.
A Photonic Crystal (PC) structure contains a periodic high-contrast modulation of the local index of refraction (or dielectric constant, for non-magnetic materials) in one, two or three dimensions. The underlying materials, processing, fabrication and tuning mechanisms are well developed (see for example C. Lopéz, Advanced Materials 15, 1679 (2003)). Any two substances having sufficient contrast between their respective indices of refraction can be placed in a stable periodic arrangement with a particular geometry, spacing and shapes of the constituent substances to create a photonic band gap (PBG) for a particular range of photon wavelengths. Electromagnetic radiation propagating in such a structure will undergo multiple Bragg scattering from the lattice array. Under certain conditions, the multiply-scattered waves interfere destructively, resulting in minimal transmission over a broad range of wavelengths, which is termed the "band gap" (a term borrowed from semiconductor physics). The PBG is said to be complete when transmission is blocked for all polarizations and all angles of incidence within the wavelength band. The PC material can be actively controlled to open or close the PBG, or shift the edges of the band gap. This can be accomplished by modulating the index of refraction contrast, changing the geometric arrangement or altering the symmetry of the scattering objects. If the periodic lattice is strained in such a manner as to maintain its periodicity but change its lattice spacing, the deformation simply alters the symmetry parameters thereby shifting the edges of the band gap. Or, if the periodic lattice is strained in such a manner to create aperiodic lattice deformation, the band gap can be switched off.
An object's Planck spectral distribution may be modified when the object is a PC. The existence of a PBG can be used to suppress radiated power in certain wavebands and enhance radiated power in other wavebands (Z. Li, Physical Review B 66, R241103 (2002), and S. Lin et al., Physical Review B 62, R2243 (2000)). This effect is most obvious when the band gap is positioned around the main peak (e.g., 5-10 μm) of the Planck spectral distribution. A three-dimensional (3D) PC can induce strong redistribution of the photon Density of States (DOS) among different frequency bands to modify the thermal electromagnetic radiation. Li supra designed the DOS of a PC to provide orders-of-magnitude enhancement in the low-DOS band of the short-wavelength region. This leads to significantly enhanced emission of thermal electromagnetic radiation in the visible waveband (approximately 0.5 μm) for a modest cavity temperature.
E. J. Reed et al., Physical Review Letters 90, 203904 (2003a); E. J. Reed et al., Physical Review Letters 91, 133901 (2003b); and E. J. Reed et al. in U.S. Pat. No. 6,809,856 entitled "Shock-wave Modulation and Control of Electromagnetic Radiation" and issued on Oct. 26, 2004 describe a technique for frequency shifting (upward or downward) single-frequency electromagnetic radiation injected into the PC from an external single-frequency laser. Reed et al. consider a particular form of a temporally-varying PC by simulating the propagation of a lattice-distorting (or index-of-refraction-changing) pulse ("shockwave") in a PC having a PBG. The incident light encounters the shock wave (i.e., the upshifted first band gap) moving in the opposite direction and is reflected backwards so that the light rides up on the shock wave and is pushed over the band gap to a higher frequency. In their implementation, the incident radiation was confined to the visual spectrum with frequency shifts limited to the width of the PC's first static band gap. In a later publication (Reed 2003b) they illustrate shifting frequencies downward by a compression induced wave in the dielectric constant of the material.
One of the major bottlenecks for the successful implementation of THz-frequency systems has been the limited output power of conventional THz sources. Most systems produce THz radiation via optical techniques, but those require massive lasers, complex optical networks and cooling systems. There are other reports on generating THz radiation using PC structures. Lu et al., IEEE Journal of Quantum Electronics 38, 481 (2002), discuss optical rectification in a nonlinear PC, requiring pump light and converting it to THz with an efficiency of approximately 1%. Iida et al., CLEO-QELS 2003 Conference Paper CMI2 (2003), place a photomixing antenna in a high-Q defect cavity in a PC.
None of these approaches offers a compact, reliable and low-cost radiation source, nor the bandwidth and frequency agility to source electromagnetic energy at THz and other frequencies.

Dynamic control of planck radiation in photonic crystals


A multi-layered printed wiring board for high frequency application includes a first board of polytetrafluoroethylene (PTFE) having a metallic sheet on each side. The first side is etched to form high frequency circuity using micro-strip technology and the second side being a metallic sheet forming the ground plane. Laminated to the ground plane of the first board is a fiberglass board of thickness, A. Further, laminated to the fiberglass board is a second board of fiberglass having a thickness, A. The second board also has metallic sheets on both side, the side being laminated to the fiberglass board being etched to form strips, prior to being laminated, forming signal and transmission lines utilizing strip-line technology. Vias are formed to interconnect predetermined metallic layers.

The present invention relates to printed circuit wiring boards, and more particularly, to multi-layer printed circuit wiring boards (sometimes referred to herein as multi-layer printed wiring boards, PWB) for microwave circuits employing microstrip line and/or stripline techniques, and a method for making same.
Circuity designed for high frequency application, including radars, transponders, . . . in the gigahertz range, cannot be designed utilizing lumped elements such as resistors and capacitors. Various design techniques are utilized including techniques well known in the art as microstrip and stripline. Microstrip consists of a wire above a ground plane, being analogous to a two-wire line in which one of the wires is represented by an image in the ground plane of the wire that is physically present. The metallic strip conductor is bonded to a dielectric sheet, and a metallic ground plane (or plate) is bonded to the other side of the dielectric sheet. [Strip transmission lines differ from microstrip in that a second ground plane is placed above the strip conductor (or conductor strip).] Conductor pads, having a variety of geometric patterns, are also bonded to the dielectric and exhibit resistive, capacitive, and inductive properties at the frequency range of interest thereby forming the high frequency circuit. The dielectric sheet utilized for these high frequency circuit include fiberglass of various types having a variety of parameters. Fiberglass has a dielectric constant which is about 4, and has high power loss (an order of magnitude as that of PTFE) and the size of the elements on the fiberglass sheet would be substantially bigger.
Polytetrafluoroethylene (PTFE), more commonly known as "TEFLON", a trademark of the Dupont Co., has also been used for the dielectric sheet of circuits of 1 gigahertz (GHZ) or higher. Generally, PTFE has low power loss at the high frequencies as compared to fiberglass. Further, the dielectric constant of PTFE can range in value from about 2 to 11 and is very constant across the entire printed wiring board and constant from lot-to-lot.
However, there are some drawbacks with the use of PTFE dielectric sheets for PWBs. These boards are very flexible, unless brass backed, which adds weight and cost. The flexibility of these PWBs cause solder joint failures due to handling. Signal routing, which includes bias lines, modulation, . . . , is accomplished utilizing "feed-thru" capacitors which are expensive, costly to install, and very unreliable due to the internal multi-layer ceramics make-up of such capacitors. Multi-layered PWBs for high frequency applications currently exist utilizing multi-layers of PTFE in an attempt to reduce board flexibility and signal routing; however, these boards are very costly due to the high cost of PTFE.
Thus, it is desired to provide a new and unique printed wire board which is reliable, eliminates the need for utilizing feed-thru capacitors, is substantial rigid thereby eliminating solder joint failures due to flexure, has a high dielectric constant permitting the size of the PWB to remain relatively small and to have the low power loss, and permits signal lines and transmission lines carrying bias, modulation, . . . to be routed internally as a stripline thereby eliminating the need for coaxial cables and wires including the hand soldering of the connections made by the coax cables and wires. The new and unique board of the present invention solves the above-mentioned problems by providing a "hybrid" board; namely, a board constructed of two dissimilar materials --PTFE and fiberglass. The board flexibility is greatly reduced increasing board reliability, and the cost of the board is substantially reduced. Further, both microstrip and stripline techniques are used on the "hybrid" board.

Microstrip printed wiring board and a method for making same


An image forming device measures calibration patterns printed on a conveying belt and stores the measurement data, which includes data for the density and position of the patterns. Measurement data is deleted from memory when the position of the pattern matches positional data stored in a flash memory for indicating unusable or abnormal positions on the conveying belt. Next, the density data and positional data in each measurement data is checked. If either the density or positional data falls outside of a specified range, then the measurement data is considered abnormal. In this case, the pattern forming position in the measurement data is stored as positional data and the measurement data is deleted. Subsequently, color registration correction is performed based on the remaining normal measurement data.

1. Field of the Invention
The present invention relates to an image forming device for correcting errors in registration between monochromatic images that are superimposed to form a multicolor image.
2. Description of Related Art
Conventional image forming devices employing an electrophotographic system, such as laser printers and copy machines, perform image formation in an image forming unit provided with a photosensitive drum. The photosensitive drum includes a charge-generating layer and a charge-transporting layer formed over a base layer. A charge is applied to the photosensitive drum by a corona discharge, and the charged drum is exposed to light, such as laser light or LED (Light Emitting Diode) light, to form an electrostatic latent image on the surface of the drum. After the image is developed with toner or another developer, the developed image is transferred onto a recording medium such as paper. Image formation is completed by a fixing unit or the like that fixes the image onto the recording medium with heat.
Image forming devices employing an electrcphotographic system form color images using colored toner of cyan, magenta, yellow, black, and the like and superimposing monochromatic toner images formed of each color to form a single multicolor image. Normally, this type of image forming device is provided with an image forming unit for each color, but only one fixing unit. A monochromatic toner image formed in each image forming unit is transferred onto a recording medium either directly or via an intermediate transfer member. Registration errors among the superimposed images may occur at this time when there are alignment errors in the relative positions at which the monochromatic images are formed. To avoid this problem, these image forming devices perform a calibration process to correct any registration errors when the image forming device is first turned on and during idle times when a printing operation is not being performed, for example.
In the calibration process, the image forming unit measures the position, density, and the like of each monochromatic image formed on the intermediate transfer member, such as a transfer belt, and the image carrying member, such as a conveying belt. The image forming unit then calibrates the relative positions and adjusts the color densities of each image formed in each image forming unit, based on the results of these measurements. However, the image carrying member on which the monochromatic images are formed may suffer from wear, abrasions, or the like due to extended use and other circumstances. Monochromatic images formed over these abrasions or the like during the calibration process can adversely affect measurements.
In a calibration method described in Japanese patent-application publication (kokai) No. HEI-11-258872 (paragraph 0122), a laser beam is irradiated onto the transfer belt and the amount of light reflected off the transfer belt is measured for one cycle. The density of the monochromatic image (monitor pattern) on the transfer belt is detected at the position having the highest measured value.