An excitation control device controls excitation of a synchronous machine so as to absorb the harmonic current of a specified order superposed onto the current flowing between an electric power system to the synchronous machine.. A harmonic detector selectively passes a harmonic component of the order of 6n.+-.1 in the detection signal detected by a current transformer. A pass signal of the harmonic detector is. 3-phase/2-phase converted by a rotating coordinate circuit into components on the orthogonal 2 axes on the rotating coordinate system rotating at an angular frequency of a fundamental current of the electric power system. At this time, the pass signal is calculated as a 6n-order harmonic current represented by the components on the normal two axes. The obtained 6n-order harmonic current is retrieved through a 6n-order harmonic filter, amplified by a power amplifier, and provided as an excitation current for the synchronous machine. Using the excitation current, a current having the same amplitude as, but opposite phase to, the harmonic current of the order of 6n.+-.1 flows as an armature current in the synchronous machine. Thus, the harmonic current of the specified order superposed onto the system current can be canceled.

1. Field of the Invention
The present invention relates to an excitation control device for absorbing specified order harmonics superposed onto a fundamental current of an alternating current (AC) system in a synchronous machine linked to the AC system.
2. Description of the Related Art
The conventional synchronous machine excitation control device provides an excitation winding of an object synchronous machine with a direct current controlled such that the component of the fundamental current in the output voltage of the synchronous machine indicates a predetermined value.
However, the synchronous machine connected to an electric power system and controlled by the conventional excitation control device has no function of absorbing a harmonic current generated in the power system. As a result, there has been a problem of the harmonic current flowing into the synchronous machine a which current is correspondingly generated in an armature winding of the synchronous machine, thereby distorting the output voltage of the armature winding. Furthermore, a negative-phase current generated by the distortion of the system voltage flows through other apparatuses, including the synchronous machine, connected to the electric power system. This may cause various problems such as over-heating, insufficient output, etc for the apparatus.

Synchronous machine excitation control device for absorbing harmonics superposed onto fundamental current


Disclosed is a semiconductor apparatus that prevents diffusion of materials of a magnetic film during the process for manufacturing the semiconductor apparatus. The semiconductor apparatus includes: a substrate; a semiconductor device formed on a principal surface of the substrate and including an interconnect layer; a magnetic shielding film of a magnetic material covering the semiconductor device; and a buffer film disposed between the semiconductor device and the magnetic shielding film. The buffer film prevents diffusion of the magnetic material of the magnetic shielding film.

1. Technical Field
The present invention relates to a semiconductor apparatus having a magnetic shielding film and to a method for manufacturing the semiconductor apparatus.
2. Related Art
In the trends of miniaturization and improved performances of electronic devices in recent years, enhancements in the response speed of semiconductor apparatus such as large scale integrated circuit (LSI) incorporated in these electronic devices are required. In order to meet such requirements, operating frequency of the semiconductor apparatus is increased, resulting in an increased frequency of signal that is propagated through interconnects of the semiconductor apparatus. This causes generation of electromagnetic radiation noises, thereby causing a problem of inducing electromagnetic interferences to other electronic devices. On the contrary, miniaturizations in the electric wiring configurations of the semiconductor apparatus causes considerable noise generated between adjacent interconnects (interconnect crosstalk), causing a problem of inducing malfunctions of the semiconductor apparatus. Therefore, in order to ensure higher reliability of semiconductor apparatus, it is desirable to reduce electromagnetic radiation noise so long as I am possible.
An approach of utilizing magnetic loss of magnetic material is well known as a procedure for reducing electromagnetic radiation noise. For example, Japanese Patent Application Publication No. H06 (1994)-21060 discloses a semiconductor device having a multiple-layered interconnect structure including a ferrimagnetic material film. In the multiple-layered interconnect structure, an interconnect layer, an interlayer insulating film, a ferrimagnetic material film, an interlayer insulating film and an interconnect layer are formed on the semiconductor substrate in this sequence. The ferrimagnetic material film is disposed between one interconnect layer and the other interconnect layer to exhibit an electromagnetic shield function. On the other hand, Japanese Patent Application Publication No. H09 (1997)-330929 discloses a semiconductor device having a layer of a magnetic material formed on an insulating layer including a metallic interconnect layer. Japanese Patent Application Publication No. H06 (1994)-120027 discloses a structure including a FeCo ferromagnetic thin film having positive magnetostriction and an intermediate layer composed of an RFeCo alloy thin film having negative magnetostriction or a spinel ferrite magnetic thin film deposited thereon. The deposited structure allows reducing effective magnetostriction in the whole film.
However, when a semiconductor device includes a film of a magnetic material, a metallic material of this film of the magnetic material may be diffused, considerably deteriorating electrical characteristics of the semiconductor device. The reason for the deterioration is considered that the diffusion of the materials composing the magnetic film is promoted during the manufacturing processes for the semiconductor device, reaching to the interconnect layer to cause a contamination with a metal. For example, in the multiple-layered interconnect structure disclosed in Japanese Patent Application Publication No. H06-21060, the material from the ferrimagnetic material film may be diffused through the interlayer insulating film during manufacturing process to cause a fear for creating contamination with metal.


A twelve-point rocker-arm adjusting nut (10) designed to be threaded into a rocker-arm stud to adjust the height/clearance between a valve and a rocker arm (44). The nut (10) consists of an axially elongated cylindrical body (12) and a hex-socket tipped set screw (32). the nut (10) has a threaded bore (20) therethrough that extends to near the lower surface (18) of the nut. From this lower surface extends upwardly a thread-free stud entry port (24). Around the upper section of the nut (10) is located a twelve-point wrenching section (26) that includes at its lower end a wrench non-slip lip 30. The wrenching section (26) serves both as a wrench gripping section and for directing oil to provide cooling for the rocker arm base and pivot ball washer (46) interface. To operate the nut (10), a standard twelve-point wrench is used to rotate the nut until the proper height/clearance between the valves and the rocker arm is achieved. A T-handle hex key is then inserted into the hex socket (34) of the screw (32) and rotated to allow the tipped end of the screw to tighten against the upper surface of the stud (40) thus, holding the nut (10) in place.

Conventional overhead-valve internal-combustion engines incorporate a cylinder head in which the intake and exhaust valves are movably mounted and oriented such that the valve stems extend from the valve head in a direction generally away from the top of the cylinder bore. Push rods, engaging valve lifters activated by a cam shaft located in the cylinder section of the engine, extend into the cylinder head alongside the valve stems.
Between each valve stem and its corresponding push rod is a rocker arm pivotally mounted on a rocker-arm stud connected to the cylinder head. The rocker arms are maintained in place by a rocker-arm adjusting nut, whereby a frictional movement occurs between a pivot ball washer and the inner surface base of the rocker arm. The push rod has a bottom end which rests on the cam shaft and moves move up and down as the cam shaft rotates. The up and down motion of the push rod causes the rocker arm to rock back and forth which, in turn, causes the valve which is connected to the rocker arms to also move up and down. When the valve moves up, it seals the combustion chamber thereby stopping the fuel from entering through the engine intake port or leaving through the exhaust port. Thus, it can be seen that it is of the utmost importance that the rocker arm be properly adjusted to enable the valve to completely seal the combustion chamber.
The rocker-arm studs are conventionally attached at their lower end to the cylinder head by either a tight press-fit into a corresponding bore or by threading. The upper end of the rocker arm stud is usually threaded and is received loosely through an elongated hole in the bottom of the rocker arm. Between a spherical bearing surface inside the rocker arm and the upper threaded end of the rocker arm stud is located the pivot ball washer. A locking-type adjusting nut is threaded onto the upper end of the rocker arm stud above the pivot ball washer. This nut is used to adjust the valve lash by moving the rocker arm pivot point up or down by turning the adjusting nut with respect to the fixed rocker arm stud to a selected position.
One of the fundamental problems associated in the manipulation of a rocker arm adjusting nut is in the method and tools required to make the adjustment. In these prior art designs, the wrench used to make the adjustment can easily slip over the body of the nut adding to the difficulty in making a final adjustment. By using the twelve-point rocker-arm adjusting nut of the instant invention in combination with a corresponding twelve-point wrench, the problem of wrench slippage is virtually eliminated and the twelve-point design also prevents the wrench from vibrating off the nut when adjustments are made with the engine running.
A search of the prior art did not disclose any patents that read directly on the claims of the instant invention, however the following U.S. patents are considered related:
______________________________________ U.S. Pat. No. INVENTOR ISSUED ______________________________________ 4,856,467 Kronich 15 August 1989 4,784,095 Golding et al 15 November 1988 4,561,392 Jette 31 December 1985 3,189,011 Briggs 15 June 1965 ______________________________________
The U.S. Pat. No. 4,856,467 Kronich patent discloses an adjustable valve lash train for an overhead valve engine that includes a rocker-arm stud having a threaded shank received in a threaded bore in the cylinder head. The rocker-arm stud includes a head having a spherically shaped bearing surface that engages a similar shaped bearing surface on the rocker arm and has a hexagonally shaped recess on its top surface for receiving an adjustment tool. A threaded jam nut is located above the threaded shank of the rocker arm stud for locking the threaded shank against rotation with respect to the threaded bore of the cylinder head.
The U.S. Pat. No. 4,784,095 Golding et al patent discloses a rocker arm adjusting nut particularly adaptable for use with steel rocker arms as employed in automotive engines. The nut consists of an integral unit having a hex nut, an upper collar, a bottom flange and an axially elongated body having a central portion provided with axial grooves. The upper collar and grooves in combination, deflect oil axially towards the bottom flange when the nut is in use. The enlarged mass and surface area of the nut also helps, by conduction, to dissipate temperature from the pivot ball-rocker arm interface and deflect oil towards the interface.
The U.S. Pat. No. 4,561,392 Jette patent discloses a girdle assembly for stud mounted rocker arms. The assembly is particularly adapted for use in racing engines where the valve stud structure is unified to prevent stud fatigue failure and adverse harmonics. The girdle is self aligning to the studs over a suitable range of positions, uses clamping forces developed without screws tension in the plane of the girdle and can be readily removed and replaced after being installed.
The U.S. Pat. No. 3,189,011 Briggs patent discloses a self adjusting valve actuating mechanism. The mechanism consists of an arrangement whereby the upper end of the push rod is automatically movable to and from a post having a spherical bearing head. The push rod movement varies its effective length by shifting the position of the cam surface on the cam carrier with respect to the cam follower bearing surface.
For background purposes and as indicative of the art to which the invention is related reference may be made to the following remaining patents found in the search:
______________________________________ U.S. Pat. No. INVENTOR ISSUED ______________________________________ 4,686,946 Umeda et al 18 August 1987 4,393,820 Maki et al 19 July 1983 4,314,732 Murphy 9 February 1982 3,754,539 Bandimere 28 August 1973 3,219,019 Palmer 23 November 1965 RE 24,035 Leach 12 July 1955 ______________________________________


Technology for reporting radio access network (RAN) user plane congestion (UPCON) is disclosed. In an example, a core network (CN) device can include computer circuitry configured to: receive an UPCON event report using an UPCON container that includes a congestion situation indicator to indicate a UPCON situation; and change an UPCON process based on the congestion situation indicator. The core network device can include a mobility management entity (MME), a serving gateway (S-GW), a packet data network (PDN) gateway (P-GW), a policy and charging enforcement function (PCEF), a policy and charging rules function (PCEF), a serving general packet radio service (GPRS) support node (SGSN), a gateway GPRS support node (GGSN), an access network discovery and selection function (ANDSF), an operation and maintenance (O&M) subsystem, an UPCON server, a proxy, or a standalone function entity.

Wireless mobile communication technology uses various standards and protocols to transmit data between a node (e.g., a transmission station) and a wireless device (e.g., a mobile device). Some wireless devices communicate using orthogonal frequency-division multiple access (OFDMA) in a downlink (DL) transmission and single carrier frequency division multiple access (SC-FDMA) in an uplink (UL) transmission. Standards and protocols that use orthogonal frequency-division multiplexing (OFDM) for signal transmission include the third generation partnership project (3GPP) long term evolution (LTE), the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard (e.g., 802.16e, 802.16m), which is commonly known to industry groups as WiMAX (Worldwide interoperability for Microwave Access), and the IEEE 802.11 standard, which is commonly known to industry groups as WiFi.
In 3GPP radio access network (RAN) LTE systems, the node can be a combination of Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node Bs (also commonly denoted as evolved Node Bs, enhanced Node Bs, eNodeBs, or eNBs) and Radio Network Controllers (RNCs), which communicates with the wireless device, known as a user equipment (UE). The downlink (DL) transmission can be a communication from the node (e.g., eNodeB) to the wireless device (e.g., UE), and the uplink (UL) transmission can be a communication from the wireless device to the node.
A core network (CN), or network core, can be a central part of a telecommunication network that provides various services to users who are connected by the radio access network (RAN). One of the functions of core network can be to route a packet from the RAN to the Internet.
The core network can provide high capacity communication facilities that connect primary nodes. Core network (or backbone network) can provide paths for the exchange of information between different sub-networks. For enterprise private networks serving one organization, the high capacity communication facilities can be referred to as the backbone, while for service providers, the high capacity communication facilities can be referred to as the core network.
Telecommunications network can include three parts, or planes: the control plane, the user plane (data plane or bearer plane), and the management plane. The three parts can be referred to as planes because each part can be separate overlay networks. The control plane can carry control information (also known as signaling). The user plane can carry the network's users traffic. The management plane can carry the operations and administration traffic used for network management.
In the 3GPP LTE wireless communication standard, a system architecture evolution (SAE) can use a core network architecture. The SAE can have a flat, all-Internet protocol (all-IP) architecture with separation of control plane and user plane traffic. A main component of the SAE architecture can be the evolved packet core (EPC), or SAE core.
Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended.

This patent is subject to a terminal disclaimer.

Reporting of user plane congestion (UPCON) using a UPCON container


Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the transfer gate is embedded in the device isolation region. The buried gate includes a gate dielectric film and gate electrode formed in a trench of the semiconductor substrate.

1. Field of the Invention
The present invention relates to a solid-state image sensing device and a manufacturing method thereof. Specifically, the present invention relates to a solid-state image sensing device and a manufacturing method thereof in which miniaturization of device does not deteriorate image properties.
2. Description of the Prior Art
In recent years, among solid-state image sensing devices, a solid-state image sensing device using an amplification-type MOS sensor has been a subject of interest. In this solid-state image sensing device, a signal detected by a photodiode is amplified by a transistor on a pixel to pixel basis. Such solid-state image sensing device is characterized by high sensibility. Moreover, due to miniaturization of pixels in recent years, a device isolation structure formed by Shallow Trench Isolation (STI) is employed for solid-state image sensing devices. STI is the technique of forming a trench on a principal surface of a semiconductor substrate, forming a dielectric film, such as oxide film, in the trench, and performing planarization, so that a device isolation region is formed. Side surfaces of the trench can be formed by STI at a steep angle to the principal surface of the semiconductor substrate. Therefore, the width of the device isolation region formed by STI is narrower than that of a device isolation region formed by LOCOS (Local Oxidation of Silicon).
However, progressing miniaturization of device requires a high impurity concentration and a deep diffusion region of the photodiode in order to improve saturation characteristics of the solid-state image sensing device. However, an incident light at an oblique angle to the deep diffusion region may produce charges in a deep portion of the photodiode, and the generated charges may be stored as signal charges in an adjacent photodiode, which may cause a problem, so-called cross talk.
A method to solve the above-mentioned problem, that is, the cross talk due to a deep photodiode, is disclosed in Gazette of Japanese Laid-Open Patent Publication No. 2003-142674 (patent document). Referring to FIG. 16, a solid-state image sensing device disclosed in the document will be described below.
As shown in FIG. 16, a P-type silicon substrate 101 has a trench isolation region 102 which isolates a pixel region. The pixel region has a charge storage portion (photodiode) 103 formed by an N-type impurity layer, a transfer gate 104 for transferring charges stored in the charge storage portion 103, and a floating diffusion (FD) portion 105 for storing the transferred charges.
In this case, a P-type device isolation diffusion region 106 surrounds the trench isolation region 102. The P-type device isolation diffusion region 106 extends under a bottom surface of the trench isolation region 102 to a position deeper than the charge storage portion 103. This structure allows to block a transfer of charges between pixels and thus to prevent the cross talk even in a case of a deep charge storage portion 103 due to the progressing miniaturization of device.

Solid-state image sensing device and manufacturing method thereof


A pet door protection apparatus for movable placement adjacent to an existing pet door, the collapsible apparatus having a first end and an open second end, the base having an adjustment plate and mechanism for adjusting the height of the interior floor, which is fitted atop the adjustment plate. The apparatus further provides a transparent side panel removably and vertically fitted within each groove of the interior base, each of an opposed pair of transparent roof panels hingedly attached to one of the side panels, respectively, the roof panels further hingedly attached to each other, a pair of opposed transparent triangular roof end panels vertically fitted between the roof panels, a protective cap fitted atop the hinged attachment of the roof panels, and a strip anchor with a plurality of weighted flexible transparent strips selectively fitted to the first end of the side panels.

Pet doors are a useful means for pets to enter and exit an indoor facility, while at the same time attempting to resist the invasion of unwanted creatures, people, and inclement weather. Pet doors have suffered from inclement weather, however, due to the nature of the rubberized flaps which allow the pet's entrance and exit. Winds, rain and snow can easily enter the flaps. Some devices and adaptations of pet doors have been proposed which are highly exclusive, and therefore not useful to many pets. Some devices are exclusive to the point of negating a pet's use of the pet door device. Most of these devices are also attached to the pet door or to the doorway which houses the pet door, not an always desirable adaptation for the indoor facility structure. What is needed is an apparatus which forms a removably placed vestibule adjacent to a typical pet door. The apparatus should not discourage pet use, and therefore is ideally transparent. The apparatus should not require a significant learning curve for the pet. Further, the apparatus should be collapsible. The apparatus should also be height adjustable in order to best align with a given pet door. The present apparatus provides these problem solutions.


In a liquid-filled anti-vibration mounting device suitable such as for an engine mount, an accommodation room containing a rubber movable plate is formed inside a partition member partitioning a liquid chamber into a pressure receiving chamber and a balancing chamber. The partition member includes a pair of division walls, one adjoining the pressure receiving chamber and the other adjoining the balancing chamber. Each division wall is formed with a plurality of communication holes. The communication holes are arranged to undulate at least a portion of the movable plate towards the peripheral edge thereof at specified circumferential intervals or greater by the action of the liquid pressure through the communication holes. The movable plate thus deformed, particularly its portion towards the peripheral edge, has a small area to come into contact with the division walls at a time, which effectively disperses and lessens a shock due to contact.

(a) Field of the Invention
This invention relates to liquid-filled anti-vibration mounting device used, for example, in motor vehicles, and particularly relates to the structure for restraining the production of abnormal noise due to abutment of a movable plate against a partition member in a liquid-filled anti-vibration mounting device in which the movable plate is contained in the partition member in a liquid chamber.
(b) Description of the Related Art
An example of known liquid-filled anti-vibration mounting devices of such kind is an engine mount for a motor vehicle. The engine mount has a basic structure in which a rubber elastic material is interposed between a mounting member for an engine and a support member for a vehicle body, a liquid chamber is formed between both the members to change its volume with deformation of the rubber elastic material and partitioned into a pressure receiving chamber and a balancing chamber and an orifice passage is provided for communicating the pressure receiving chamber with the balancing chamber.
The orifice passage is tuned to relatively low-frequency and large-amplitude vibrations, such as vibrations at engine start-up, jerky vibrations at gear change or shaking, and such vibrations to be input to the engine mount can be effectively damped by a resonance (liquid column resonance) generated when the liquid flows via the orifice passage between the pressure receiving chamber and the balancing chamber.
The partition member partitioning the liquid chamber into the pressure receiving chamber and the balancing chamber is composed of a pair of division walls disposed with a specified distance between them, one division wall adjoining the pressure receiving chamber and the other adjoining the balancing chamber. An accommodation room containing a movable plate is defined between the pair of division walls. The pair of division walls are each formed with communication holes, the communication holes in one of the division walls communicate the accommodation room with the pressure receiving chamber and the communication holes in the other division wall communicate the accommodation room with the balancing chamber. When a change in the liquid pressure in the liquid chamber is transmitted via the communication holes to the accommodation room, the movable plate moves to absorb the change.
Specifically, when vibrations are input to the engine mount with such a relatively high frequency and a small amplitude that the orifice passage may be clogged, changes in the liquid pressure in the pressure receiving chamber due to the vibrations are transmitted via the communication holes in the associated division wall to the accommodation room and the movable plate in the accommodation room vibrates in synchronization with the changes in the liquid pressure to absorb the changes. On the other hand, when relatively low-frequency and large-amplitude vibrations are input to the engine mount as described above, the movable plate responding to changes in liquid pressure due to the vibrations is pressed against the associated division wall to close the communication holes.
When the movable plate moves in the accommodation room in the partition member as described above, a shock occurs upon abutment against the division wall and is transmitted to the vehicle body, which may produce abnormal noise in the passenger compartment. Such abnormal noise, though its magnitude differs depending upon the vibration transmission characteristics of the vehicle body, can be reduced by lessening the shock.
To attain this, for example, in an engine mount disclosed in Published Japanese Patent Application No. 2006-38016, each surface of the movable plate is formed with a large number of dimples so that upon abutment against the facing division wall (referred to as the top plate or the bottom plate in the document), voids can be locally created by the dimples. Thus, the contact area of the movable plate with the division wall can be reduced to lessen a shock due to the abutment.
In another engine mount disclosed in Published Japanese Patent Application No. 2006-207630, a set of communication holes (referred to as slot openings in the document) in each division wall are offset in a radial direction, or towards a lateral side, with respect to the center of the movable plate. When a liquid pressure acts through the communication holes on the movable plate, the movable plate is radially inclined and thereby brought into gradual contact with the division wall with its lateral side end first and the rest delayed. Thus, the shock due to the contact can be dispersed in a time-shared manner and thereby eased.

Liquid-filled anti-vibration mounting device


A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device is used to find a faulty cell address in the memory device under test during a pre-fuse stage. The built-in self test device is used to detect whether the memory device under test has any error during a post-fuse stage. The memory apparatus is capable of promptly finding the address of a defect cell in the memory device under test such that repairs can be performed during a fuse stage. Furthermore, the invention reduces the pin count required during testing the memory device under test. Thus, the cost of testing equipment is reduced and the performance of memory testing is enhanced.

1. Field of the Invention
The invention relates to a memory apparatus and a test method, and in particular relates to an apparatus and a test method for a memory chip with reduced pin count circuit.
2. Description of the Related Art
With increased scope of memory chip and the complication of design thereof, test speed and accuracy of chips has become critical in determining efficiency of memory chip production. For example, design for testability (DFT) has been developed, in which enhanced circuit design during chip design stage efficiently reduces the time for chip tests, to improve failure coverage rate and product quality and production speed, as well as reducing the time for chip tests by a built-in self test (BIST).
A memory chip comprises a plurality of memory cells, some of which may be defective. Preparing faulty cells with redundant memory cells can address the problem. Defective memory cells are replaced with redundant memory cells by laser fuses. This stage is called as a fuse stage. The process to find the defective memory cells in a memory before the fuse stage is called a pre-fuse stage. After the fuse stage, the memory chip needs to be verified again. This process is called as a post-fuse stage.
Some memory chip test techniques check each memory cell in a memory chip during the pre-fuse stage, and then perform the fuse operation. Then an I/O compressor or a BIST determines whether the memory chip is recovered during the post-fuse stage. This techniques requires more time to find the defective memory cells in a chip during the pre-fuse stage, and testing apparatus requires more pin count to input the test data into the memory chip. Other memory chip test techniques find the defective memory cells in a memory chip during the pre-fuse stage and verify whether a defective memory cell exists during the post-fuse stage both by a BIST. This technique is less time-consuming and reduces pin count required but increases the manufacture cost of a chip by the high efficient (fast and correct verification) BIST which occupies more chip area and requires more complicated circuit design.

Memory apparatus and method and reduced pin count apparatus and method


A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.

DRAMs are dynamic memory devices that store data by electrical charge. The electrical charge representing stored data has to be restored after it is read. The data also has to be refreshed periodically, even when the data is not read, because the charge representing the data dissipates.
A large part of the current that a DRAM uses is in refreshing the memory cells. The current used is determined by how many cells are refreshed at one time. Every cell along a selected row is refreshed periodically. When a cell is refreshed, the corresponding bit line lines are either pulled to a reference voltage, usually ground, or a power supply voltage (VCC).
For example, in a DRAM the "battery back-up mode," sometimes known as self-refresh mode, is a cycle that the system uses to save power. The system is not accessing (reading) any cells; it just maintains the data in the DRAM. This mode uses as little power as required to maintain the data in the memory cells. Other refresh modes are column address strobe before row address strobe (known in the art as "CAS before RAS") and suspend mode.
FIG. 8 represents a conventional memory array configuration with associated row decoders and row address buffers. The memory array is divided into four subarrays 200. Each subarray represents one-quarter of the storage capacity of the total memory. For example, if the total memory is four megabits (2.sup.22 =4,194,304), then each subarray 200 would be 1 megabit (2.sup.20 =1,048,576) configured to have 1,024 columns and 1,024 rows. Each subarray 200 has a corresponding decoder 202. Decoders 202 are coupled to address buffers 204 which receive row addresses.
The subarrays are accessed by the user or system by supplying a row address to address buffers 204. Address buffers 204 pass buffered row addresses to decoders 202. Selected ones of decoders 202 supply decoded row addresses to the corresponding subarrays 200. Since each subarray 200 has 1,024 rows, the corresponding decoder 202 provides one of 1024 decoded row addresses. The address is provided from decoders 202 to subarrays 200 via word lines 205 i.e. by raising the voltage on the selected word line(s).
FIG. 9 shows a more detailed diagram of the subarrays 200 and decoders 202 in a block 206 in FIG. 8, and the address buffers 204 in a block 204. As illustrated in a block 200 of block 206 of FIG. 9, each subarray 200 is broken down into further subarrays ("SA") 208. Subarrays 208 a-d represent one subarray 200 and subarrays 208e-h represent another subarray 200. Hence, FIG. 9 depicts two subarrays 200 of FIG. 8 for a total memory capacity of 2 megabits (2.sup.21 =2,097,157).
A block 202 in FIG. 9 shows a decoder 202 of FIG. 8 in more detail. Block 202 contains subarray decoders ("SAD") 210a-d and predecoders ("PD") 212a-d. A block 204 shows in more detail address buffers 204 of FIG. 8 to include low address buffers 204a and high address buffers 204b.
The operation of the FIG. 9 configuration will be explained in terms of addressing the subarrays 208a-h. First a row address is supplied to low and high address buffers 204a and b. Since each subarray 200 has 1,024 rows, the row address must have ten address bits (A0-9). It follows that each subarray 208a-h has 256 kilobits of memory.
Low address buffers 204a receive the first eight (lower) address bits A0-7. High address buffers 204b receive the two high address bits A8-9. Address bits A0-9 are supplied to predecoders 212a-d. High address bits A8-9 are typically used to enable by selection predecoders 212a-d. Two high address bits (A8-9) select one predecoder 212 out of four in each 1 megabit block. The selected predecoder 212 passes the low address bits to its corresponding subarray decoder 210 to be decoded.
In the corresponding subarray 208, a row will be accessed corresponding to the word line activated by the decoded low address bits A0-7. The row of subarray 208 corresponding to the activated word line can then be accessed and refreshed. Each of the four subarrays 200 of FIG. 8 has a respective one of its rows accessed. Hence, four rows will be accessed for the entire memory in response to a received row address.
FIG. 1 shows a typical configuration of row address buffer and decoder circuits. Input buffers circuit 10 is coupled to receive an address signal A0-AN. A buffers latch circuit 12 is coupled to receive an output signal from circuit 10 via a bus 14. A buffers output enable circuit 16 is coupled to receive an output signal from circuit 12 via a bus 18. An address decoder circuit 20 is coupled to receive an output signal from circuit 16 via a bus 22. Address decoder circuit 20 outputs a word line enabling signal WL0-WLM via a bus 24.
The FIG. 1 row address circuit receives an address signal A0-AN from a bus or a device such as an external processor or memory controller. Input buffers circuit 10 converts the address signal to CMOS levels. For example, if address signal A0-AN is a TTL signal with a high level (2.4 V) and a low level (0.8 V), it will be converted to a CMOS high level (5.0 V) and low level (0.0 V).
Latch circuit 12 receives from input buffers circuit 10 a buffered or converted address signal A0-AN. Latch circuit 12 latches the address signal A0-AN in latches (not shown) and provides complementary bits of the address signal A0-AN. Latch circuit 12 provides the latched address signal to buffers output enable circuit 16. Circuit 16 outputs the latched address input signal and its complements to address decoder circuit 20. Circuit 20 decodes the latched address signal and outputs memory enabling signal WL0-WLM to the memory array (not shown).
FIG. 2 is a detailed schematic of the FIG. 1 circuit. FIG. 2 illustratively shows a three-bit address (N=2), and an 8-bit output (M=7). Address bits A0-A2 are input to block 10, which represents the input buffers circuit 10 shown in FIG. 1. Input buffers 11a, 11b, and 11c (collectively "buffers 11") represent individual buffers of circuit 10. Outputs of buffers 11 are respectively provided on lines 14a, 14b and 14c, which are the individual lines of bus 14 in FIG. 1. Lines 14a, 14b and 14c are input to block 12, which represents the buffers latch circuit 12 shown in FIG. 1. Lines 14a, 14b and 14c are respectively coupled to source-drain paths of pass transistors 26a, 26c and 26e (collectively "pass transistors 26"). Lines 14a, 14b and 14c are also respectively coupled to source-drain paths of pass transistors 26b, 26d and 26f (collectively "pass transistors 26") through inverters 28a, 28b and 28c (collectively "inverters 28"), respectively. Inverters 28 provide complements of address signals A2-A0. Gate electrodes of the aforementioned pass transistors 26 are coupled to receive an address transfer signal ADDXFER.
The source-drain paths of pass transistors 26a and 26b, 26c and 26d, and 26e and 26f are respectively coupled to inverters 30a and 30b, 30c and 30d, and 30e and 30f (collectively "inverters 30"). The source-drain paths of pass transistors 26 are respectively coupled to lines 18a, 18b, 18c, 18d, 18e and 18f. Lines 18a, 18b, 18c, 18d, 18e and 18f are the individual lines of bus 18 as shown in FIG. 1.
Lines 18a, 18b, 18c, 18d, 18e and 18f are input to a block 16 which represents the buffers output enable circuit 16 of FIG. 1. Lines 18a, 18b, 18c, 18d, 18e and 18f are coupled to first inputs of NAND gates 32a, 32b, 32c, 32d, 32e and 32f (collectively "NAND gates 32"), respectively. Second inputs of NAND gates 32 are each coupled to receive an address buffer enable signal ABE. Inverters 34a, 34b, 34c, 34d, 34e and 34f (collectively "inverters 34") are coupled to receive outputs of NAND gates 32, respectively. Outputs of inverters 34 are respectively provided on lines 22a, 22b, 22c, 22d, 22e and 20f (collectively "lines 22"). Lines 22a, 22b, 22c, 22d, 22e and 22f are individual lines of bus 22 as shown in FIG. 1.
Lines 22 a-f are input to a block 20 which represents the address decoder circuit 20 as shown in FIG. 1. It is formed illustratively of NAND gates, each having three inputs. It will be understood, however, that other logic circuitry could be used, such as AND gates. In FIG. 2, NAND gates 36a, 36b, 36c, 36d, 36e, 36f, 36g and 36h (collectively "NAND gates 36") have inputs that are coupled to various combinations of lines 22. NAND gates 36 decode signals on lines 22 to generate a row address (identify a row) to be accessed in the memory (not shown). Inverters 38a, 38b, 38c, 38d, 38e, 38f, 38g and 38h (collectively "inverters 38") are coupled to receive outputs of respective NAND gates 36. Inverters 38 provide word line enabling signals WL0-WL7 on respective lines 24a, 24b, 24c, 24d, 24e, 24f, 24g and 24h. Lines 24a, 24b, 24c, 24d, 24e, 24f, 24g and 24h are the individual lines of bus 24 shown in FIG. 1.
Buffer 11a, inverters 28a, 30a, 30b, 34a and 34b, NAND gates 32a and 32b, and pass transistors 26a and 26b form an address A2 buffer for address bit A2. Address bits A0 and A1 have respective buffers that are configured like the devices of the address A2 buffer. Hence, FIG. 2 illustrates three address buffers.
The operation of the FIG. 2 will now be explained. Address signals A0-A2 are input with, for example, a value 1,0,1 (A0=1, A1=0, A2=1) to their respective buffers 11. Buffers 11 supply address signals A0-A2 to respective pass gates 26, either directly or through inverters 28. Inverters 28 supply the complements of address signals A0-A2, i.e. A0 (=0), A1 (=1) and A2 (=0).
Address transfer signal ADDXFER becomes active (high) to turn on pass transistors 26 to supply address signals A0-A2 and A0-A2 to inverters 30. Inverters 30 function as a latch to maintain the address signals A0-A2 and A0-A2. Pass transistors 26 also supply address signals A0-A2 and A0-A2 to NAND gates 32 via lines 18a, 18b, 18c, 18d, 18e and 18f (respectively 1,0,0,1,1,0). NAND gates 32 pass complements of address signals A0-A2 and A0-A2 to inverters 34 when address buffer enable signal ABE is active (high). The outputs of NAND gates 32a, 32b, 32c, 32d, 32e and 32f are respectively 0,1,1,0,0,1.
Inverters 34 complement the outputs of NAND gates 32 to provide address signals A0-A2 and A0-A2 to NAND gates 36 to be decoded. The outputs of inverters 34a, 34b, 34c, 34d, 34e and 34f are respectively 1,0,0,1,1,0. NAND gates 36 decode address signals A0-A2 and A0-A2 to provide decoded signals to inverters 38. Inverters 38 complement (invert) the outputs of NAND gates 36 to provide enabling signals WL0-WL7. It can be seen from FIG. 2, block 20, that enabling signals WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7 have respective values of 0,0,0,0,0,1,0,0 when A0=1, A1=0 and A2=1. The circuit of FIG. 2 refreshes a row of memory cells according to the address that is supplied from buffers 11.
Many DRAMs are manufactured by an advanced process technology that allows the device to hold data longer than other process technologies allow. The longer data holding time can be taken advantage of by restoring fewer rows at a time, thus saving power. Further, other DRAMs may be fabricated via processes where less power is required to restore the data memory. These devices can have more rows restored without prohibitively increasing the power requirements of the device.
For example, using a 64 megabit DRAM manufacturing process for a one megabit DRAM would lessen the power requirements to restore the data because the geometries of the former devices are smaller than those of the latter devices. The typical row address circuit explained above and shown in FIGS. 1 and 2 does not take advantage of these superior processes.
Additionally, industry standards dictate such requirements as, for example, the number of rows a given generation of DRAMS will have. This makes all DRAM devices somewhat uniform regardless of the manufacturer. A user can employ DRAMs made by different manufacturers knowing that they will have the same specifications, such as the same page size. Therefore, any alterations to the functions of DRAMs must be transparent to the user.
Therefore, it is a general object of the present invention to provide a circuit which allows a DRAM to save power while refreshing, or to refresh more quickly, and still conform to industry standards.
A further object of the present invention is to provide a circuit to save power for refreshing a DRAM that requires a minimum number of devices, and thus requires a small area.
A still further object of the present invention is to provide a circuit to decrease and/or increase the number of rows refreshed regardless of the circuitry used to input the address.


A semiconductor memory device has a matrix of memory cells interconnected by a plurality of column and row lines to form a channel between one of the column lines and a voltage source corresponding to a specified status. A sensing circuit connects or disconnects an output node where the current is supplied from the voltage source with the input node which indicates the status of the specified memory cell. A reference voltage generation circuit generates the reference voltage. A comparison circuit generates a signal to indicate the specified status of the selected memory cell. Between the output and input nodes of the sensing circuit, a first transistor under gate control by a reverse voltage of the input node voltage is connected and between the input node of the sensing circuit and the input node of the reference voltage generation circuit, a second transistor under gate control by the reverse voltage is also provided. The column line of the selected memory cell is charged by the voltage source of the sensing circuit via the first transistor and also by the voltage source of the reference voltage generation circuit via the second transistor.

1. Field of the Invention
This invention relates to a semiconductor memory device, and in particular relates to a semiconductor memory device featuring high speed data reading realized by higher speed charging up of column lines.
2. Description of the Prior Art
Semiconductor memory devices include the non-volatile semiconductor memory device using as its memory devices MOS type field effect transistors (hereinafter "MOS FET") having double gate structure with a floating gate and a control gate.
FIG. 8 is a cross sectional view of such a MOS FET, and FIG. 9 shows its symbolized view. The MOS FET is provided with N-channel type source-drain diffusion layers 82 and 83 on a P-channel type substrate 81 and a floating gate 84 electrically insulated from outside and a control gate 85 for switching control both in an insulation layer (not shown) on the substrate. When the floating gate 84 is electrically neutral (hereinafter "non-write status"), the MOS FET becomes conductive under low control gate voltage (2 V, for example) as shown by 101 in FIG. 10. However, if high voltage (12.5 V, for example) is applied to the control gate 85 and the drain 83, electrons are supplied to the floating gate 84, which results in higher threshold voltage at memory devices seen from the control gate 85 (hereinafter called "write status"). In this case, the MOS FET becomes conductive only when high voltage (7 V, for example) as shown by 102 in FIG. 10 is applied to the control gate 85. Such a change in threshold voltage is utilized for data storage.
FIG. 6 is a schematic diagram to show the configuration of a conventional non-volatile semiconductor memory device using memory devices comprising MOS FETs as described above.
This semiconductor memory device has a memory array 40 comprising a plurality of column lines D1 to Dn connected to the drains of a plurality of memory devices MC11 to MCmn and a plurality of row lines SX1 to SXm serving as common gate electrodes for the memory devices on the column lines D1 to Dn.
The row lines SX1 to SXm control switching among memory devices according to row selection signals from a row decoder 41. The column lines D1 to Dn are connected to an input terminal SIN4 of a sensing circuit 44 via a column selection circuit 42 consisting of N-channel type MOS FETs MY1 to MYn, which are in turn controlled for switching according to column selection signals SY1 to SYn from a column decoder 43.
The sensing circuit 44 has its input terminal SIN4 connected with both the source of an N-channel type MOS FET MN41 and the input of an inverter circuit INV41, and the inverter circuit INV41 has its output VO4 connected with the gate of the above N-channel type MOS FET MN41. A P-channel type MOS FET MP41 serving as a load MOS FET has its source connected with the power supply VC and its gate and drain connected with the drain of the N-channel type MOS FET MN41. From the contact N400 where the gate and drain of the P-channel type MOS FET MP41 and the drain of the N-channel type MOS FET MN41 are connected, the output Vsa4 of the sensing circuit 44 is output.
A reference voltage generation circuit 45 has a configuration similar to the sensing circuit 44 with an N-channel type MOS FET MN42, an inverter circuit INV42 and a P-channel type MOS FET MP42. Input is provided to a reference memory device MCR4 equivalent to the memory devices MC11 to MCmn via an N-channel type MOS FET MYR4 equivalent to the N-channel type MOS FETs MY1 to MYn constituting the column selection circuit 42. The reference voltage generation circuit 45 generates reference voltage Vra4. A comparison amplifier 46 compares the output Vsa4 from the sensing circuit 44 with the output Vra4 from the reference voltage generation circuit 45 and outputs the result data output DAT4.
Now, the data reading operation is described. Suppose the memory device MC11 in the memory array 40 is selected.
If this selected memory device MC11 is in non-write status, the column line D1 and the input SIN4 of the sensing circuit 44 are discharged via the memory device MC11. This lowers the potential at the input SIN4 of the sensing circuit 44, which causes the output VO4 at the inverter circuit INV41 to have higher voltage and the N-channel type MOS FET MN41 to become conductive. Accordingly, the potential of the output Vsa4 from the sensing circuit 44 becomes low.
On the other hand, if the selected memory device MC11 is in write status, the column line D1 and the input SIN4 of the sensing circuit 44 are charged via the P-channel type MOS FET MP41 and the N-channel type MOS FET MN41. This increases the potential at the input SIN4 of the sensing circuit 44, causing the output VO4 at the inverter circuit INV41 to become low and the N-channel type MOS FET MN41 to become non-conductive. This results in high level output Vsa4 at the sensing circuit 44 under the effect of the P-channel type MOS FET MP41.
In the reference voltage generation circuit 45, the reference memory device MCR4 connected to its input RIN4 is in non-write status and its gate terminal connected to the power supply VC is conductive. Accordingly, the output Vra4 of the reference voltage generation circuit 45 is at low level as in the case of sensing circuit 44.
The output Vsa4 of the sensing circuit 44 thus changing depending on the status of the selected memory device is compared with the potential at the output Vra4 of the reference voltage generation circuit 45 by the comparison amplifier 46 so as to obtain the output DAT4 corresponding to the status of the selected memory device.
In a conventional semiconductor memory device, if a memory device in write status is selected, proper data is output only when the potential of the selected column line and the sensing circuit 44 are charged via the P-channel type MOS FET MP41 and the N-channel type MOS FET MN41, the output VO4 of the inverter circuit INV41 becomes low, the N-channel type MOS FET MN41 becomes non-conductive and the output Vsa4 of the sensing circuit 44 is brought to high level by the P-channel type MOS FET MP41.
For example, as shown by the voltage waveform in FIG. 7, if the column selection signals SY1 and SYn changes at the time T71 with shifting from the selection of a memory device in non-write status on the column line D1 to the selection of another memory device in write status on the column line Dn, the data output DAT4 is at high level during charging of the newly selected column line Dn (the period from the time T71 to T72) and becomes low upon completion of charging of the column line Dn (at T72). For this reason, when many memory devices are connected to each of the column lines D1 to Dn, causing large capacity to depend on the column lines, charging of the column lines D1 to Dn requires long time, which results in long time required for data reading.


This invention relates to a method for manufacturing a composite member, where a number of different material layers including at least one layer of gelcoat are applied in a mold, and where resin is applied for joining of the layers. The method is new in that particles are added to the gelcoat, whereby the gelcoat comprising such particles forms an outermost layer on at least a part of the manufactured composite member. Hereby is obtained a composite with a hydrophobic and lotus-like surface yielding good self-cleaning properties and which is on the same time self-regenerating. The invention furthermore relates to composite members comprising such a gelcoat layer with particles and to the use of gelcoat comprising particles for giving regenerating self-cleaning properties.

Components made of composite materials play an increasing role in everyday life and are increasingly used for structural components, where the possibility of obtaining parts with high stiffness and strength properties yet low weight are important or advantageous. Thus, composite structures are used more and more in the manufacture of parts and finished goods in various industries such as in the wind turbine, automotive, trucking, aerospace, marine, rail, appliance, container, construction, anti-corrosion, electrical and medical industries as well as in athletic equipments, recreation vehicles and such.
For most components, the properties of the surfaces play an important role such as for instance high resistance to UV-light, hardness, low friction coefficients in specific areas, surfaces that are easy to repair without visual impair, and low or high reflection coefficients etc. depending on the specific requirements and use of the component in question.
Hydrophobic properties are very advantageous especially in many outdoor applications in yielding a self-cleaning and dirt-repelling effect as small particles, contaminants and insects etc are more easily washed off with the water being repelled from the hydrophobic surface due to its low surface energy. A similar self-cleaning effect is obtained on surfaces with the so-called lotus effect characterized by small elevations and depressions, or a very porous surface structure in the micro- and/or nano-scale containing trapped air. Such surfaces are also advantageous in reducing the noise, e.g. arising from the blades on a wind turbine, in use and in reducing the drag from a surrounding fluid. Such surfaces and methods for their manufacture are described in EP1141543, EP0772514, DE102004037812 and U.S. Pat. No. 7,258,731 among others. A significant disadvantage with the described self-cleaning surfaces is, however, that the self-cleaning and dirt-repelling effect is prone to be worn off after a relatively short period of time of course depending on how the component in consideration is used. The surface properties will then have to be renewed for instance by spraying, painting or in another way applying a new coating. This is in many applications a very impractical or perhaps even impossible procedure to perform and is in all cases both very time-consuming and costly.
EP1283076 describes a method of obtaining a hydrophobic surface structure which is at least partly self-regenerating. The surface is formed by securing particles on and in a carrier layer. When the carrier layer and the particles on the surface along with it are worn off, new particles are gradually exposed regenerating the surface properties. The coating is applied by spray, brush, a jet or the like which, however, is disadvantageous for a number of applications as only a relatively thin layer thickness can be obtained by these methods as the layer otherwise has a tendency to become wrinkled and uneven and the strength of the layer will be limited. Alternatively, in order to obtain a thicker surface layer of a higher strength, the coating must be applied by a number of thin layer applications which then render the manufacturing method time-consuming and uneconomical.

Regenerating surface properties for composites


A method and system of wireless signal repeating. A wireless signal repeater may receive a group of signals and select signals to be amplified so as to produce amplified signals. The repeater may also select antenna elements to re-transmit the amplified signals. The repeater may further select areas to direct the elements' radiation patterns in order to provide extensive wireless service to desired areas. The repeater can perform any of these selection functions simultaneously and/or independently, and based on any desired criteria. For example, each signal received into the wireless signal repeater may carry an identifier. The repeater may perform the selection functions based at least in part on the identifiers of the signals.

A. Field of Invention
The present invention relates to wireless communication systems, and more particularly, to a method and system of wireless signal repeating.
B. Description of Related Art
In a typical wireless communication system, an area is divided geographically into a number of cells, each defined by one or more radiation patterns created by an emission of radio frequency (RF) electromagnetic (EM) waves from a respective base transceiver station (BTS) antenna or antenna array. Further, each cell may be divided into a number of sectors, each defined respectively by radiation patterns from directional antenna elements of the cell's BTS. Each sector typically has a beam width of about 120 degrees. However, sectors can have any desired beam width.
For wireless communications, EM signals are not sent through a transmission line, and therefore antennas and/or antenna arrays are required for the transmission and reception of the signals. An antenna array is a set of antennas working together to produce a particular radiation pattern. Each antenna in the array is referred to as an antenna-element (or simply an element).
The radiation pattern of each sector in a cell produces an air interface, which defines a respective coverage area. When a mobile station (MS), such as a cellular telephone, is positioned within such a coverage area of a sector in a cell, the air interface provides a communication path between the MS and the BTS. And the MS can then communicate through this path with entities of the wireless communication system.
Wireless communications from a BTS to an MS are considered to be in a "forward" direction, and therefore such communications are referred to as "forward link" communications. Conversely, wireless communications from an MS to a BTS are considered to be in a "reverse" direction, and therefore such communications are referred to as "reverse link" communications.
Unfortunately, however, both forward and reverse link communications (and other wireless communications) can suffer from varying levels of signal degradation as signals are carried over the air interface between the MS and an antenna of a BTS. For instance, the strength (i.e., power level) of signals transmitted in a forward link direction can diminish substantially as the signals travel over an increased distance to the MS. Further, obstructions such as buildings and foliage can attenuate or otherwise degrade signals passing over the air interface. As a result, forward link signals that arrive at the MS may be too weak to be detected and/or used by the MS, and therefore forward link signals could be undetectable and wireless communications could be blocked or dropped. In addition, the strength of signals transmitted in a reverse link direction can also suffer from similar reductions as the signals travel to the BTS.
One approach that can be used to overcome this difficulty is to increase the power of a signal transmitted by a BTS. A disadvantage with this approach, however, is that the increased power can lead to increased interference in adjacent cells. The power increase can also interfere with other wireless devices in use near the BTS.
Also, this approach does not aid a BTS in receiving a signal transmitted from an MS. Wireless communications are primarily bi-directional communications, in which signals are sent between a BTS and an MS. Therefore, in order to support bi-directional communications, an increase in the transmission power of the BTS would require a corresponding increase in the transmission power of the MS. However, again, an increase in transmission power of the MS could lead to interference with other wireless devices.
Another approach that can be used to increase wireless signal strength is to use wireless signal repeaters. A wireless signal repeater may be able to receive a signal distorted by transmission losses and to regenerate or replicate the signal. Analog repeaters frequently can only amplify the signal while digital repeaters can reconstruct a signal to near its original quality.
For instance, a repeater may be positioned between an MS and a BTS to intercept signals sent between the MS and the BTS. The repeater may amplify the power of these signals and send amplified versions of these signals to the MS or the BTS.
This approach may work in some cases. However, in general not all signals that need to be amplified are intercepted by the repeater. Further, some signals that do not need to be amplified may be amplified, resulting in distorted signals. In addition, existing repeaters lack flexibility in extending coverage to isolated or desired areas. Consequently, a system that overcomes these problems is desirable.

Method and system of wireless signal repeating


A resin-retained denture bridge having an improved bonding between a false tooth or teeth of the bridge and a retainer wire of the bridge is provided in the present invention, wherein a coupling recess is formed on a lingual side of the false tooth and a protrusion or an omega-shaped bend is formed on the retainer wire. The protrusion or omega-shaped bend is received in the coupling recess of the false tooth after or prior to a resin being filled in the coupling recess, which is then cured to form a secure engagement, so that the false tooth is bonded to the retainer with the end portions of the retainer wire extending laterally from the false tooth.

Maryland bridge is a popular resin-retained bridge (a fixed dental prosthesis) replacing a missing tooth that relies for its retention on a composite resin cement. This special bridge is designed for temporary use, for example, between the implantation of a dental implant root and the installation of the abutment (for the two-stage design), normally 4-6 months or longer, depending on osteointegration process of the patient. However, the false tooth retained by the bridge falls accidently, for example an occlusion on hard food during the patient's chewing, or even falls due to a gradually weakening bonding between the false tooth and the retainer.


The present disclosure relates the use of a stamping surface enhanced Raman scattering (S-SERS) technique with nanoporous gold disk (NPGD) plasmonic substrates to produce a label-free, multiplexed molecular sensing and imaging technique. A NPGD SERS substrate is stamped onto a surface containing one or more target molecules, followed by SERS measurement of the target molecules located between the surface and SERS substrate. The target molecules may be deposited on the surface, which may be a carrier substrate such as polydimethylsiloxane (PDMS).

Surface-enhanced Raman spectroscopy (SERS) is a spectroscopic technique, where Raman scattering is boosted primarily by enhanced electric field due to localized surface plasmon resonance (LSPR). With advances in nanofabrication techniques, SERS has attracted great attention for label-free molecular sensing and imaging. However, the practical use of SERS has often encountered a couple of inherent issues. The first one is regarding a molecule transfer step where target molecules need to be within the close proximity of a SERS-active surface by either mixing with nanoparticles or coating onto surface-bound nanostructures. In other words, target molecules are required to be transferred from non-SERS-active surfaces to SERS-active ones, normally in the solution phase, which can be problematic due to issues such as surface affinity variability and uncertainty, competitive adsorption among different molecules, and contamination issues, causing irreproducible results and erroneous or biased interpretations. More importantly, if the spatial distribution of molecules on the surface prior to the transfer step is of importance, such information is completely lost. Practically, solution-phase processes are relatively more labor and time-consuming and require a "wet" laboratory. Furthermore, SERS measurements are always restricted to molecules adsorbed on metals such as Ag, Au, and Cu.
To address the aforementioned issues, many approaches have been developed, and can be broadly classified into chemical and physical means. Chemical approaches employ functionalized surfaces to improve affinity and selectivity of target molecules. For example, Au nanoparticles were surface-modified by cystamine and cysteine for detecting perchlorate and trinitrotoluene, respectively. Physical approaches, in contrast, attempt to bring the target molecules to the SERS-active surface by physical manipulation. A potential advantage of physical approach lies in that the SERS enhancement depends solely on distance, rather than surface affinity. For example, tip-enhanced Raman scattering (TERS) technique introduces enhanced electromagnetic field by bringing a nano-tip into the vicinity of target molecules. Although TERS provides diffraction-unlimited spatial resolution similar to that from atomic force microscope, it is time-consuming for large area imaging. Li et al. developed shell-isolated nanoparticle-enhanced Raman spectroscopy (SHINERS), in which SERS-active nanoparticles are coated over the surface with target molecules via wet processes. Lee et al. demonstrated using gold nanorod-loaded filter paper for SERS measurement by pre-wetting and swabbing it on the surface to be probed.
SERS analyses have been performed to analyze biological samples. For example, urine is an easily-accessible bodily fluid that provides metabolic information, including the renal status. Creatinine, a protein metabolite, is one of the major components of human urine besides urea. Since the content of creatinine excreted into the urine is relatively constant in the absence of renal disease, it is used as an internal standard to normalize variations in other urine analytes. Moreover, the detection of creatinine concentration in the urine is important for renal clearance tests, which monitor the filtration function of the kidney. Serum creatinine concentrations are routinely monitored as an indicator of clinical renal function. In clinical diagnostics, serum and urine creatinine concentrations are measured, and generally a high creatinine level indicates kidney problems. For example, normal levels of blood creatinine are approximately 0.6 to 1.2 mg/dl in adult males and 0.5 to 1.1 mg/dl in adult females. In urine, however, creatinine is found to be 500-2000 mg over a 24-hour period. By simply dividing 500-2000 mg to the average urine volume of 1-2 L in an adult male, the lower limit of urine creatinine concentration is estimated to be ˜25 mg/dL.
Due to the importance of creatinine in clinical research, a variety of analytical methods have been developed for detecting creatinine in urine, including Jaffe reaction spectrophotometric method, enzymatic method, capillary zone electrophoresis, high performance liquid chromatography (HPLC), high performance thin-layer chromatography (HPTLC), liquid chromatography tandem mass spectrometry (LC-MS), gas chromatography mass spectrometry (GC-MS), isotope dilution extractive electrospray ionization tandem mass spectrometry (ESI-MS), Raman spectroscopy and surface-enhanced Raman scattering (SERS). Compared to traditional analytical methods, Raman and SERS methods offer several advantages. They require no reagents or separation, are non-invasive, are capable of qualitative and quantitative measurements, and provide molecular structure information. In particular, SERS is a highly-sensitive Raman spectroscopic technique where Raman scattering is enhanced primarily by near-field electromagnetic enhancement due to localized surface plasmon resonance (LSPR). Recent advances in the field of nanotechnology have paved the way for the development of SERS based detection.
Most creatinine SERS analyses have thus far been performed on metallic (e.g., Ag and Au) colloidal nanoparticles. In general, Au-based SERS substrates are more stable, nontoxic and biocompatible compared to Ag-based ones, although they have inherently lower (i.e. 102-103 fold) SERS effects than Ag-based substrates. By using gold colloids, the potential of SERS for qualitative and quantitative creatinine measurements was illustrated by W. R. Premasiri et al., and the measurement of creatinine in human urine at concentrations ranging from 2.56 to 115.2 mg/dl was reported by T. L. Wang et al. Y. Wang et al. performed the detection of creatinine water solution with concentrations ranging from 10-280 mg/dl by mixing with silver colloids. R. Stosch et al. described the determination of creatinine in human serum at physiologically relevant levels using silver colloids as SERS substrates. In addition, nanostructured metal surfaces have been employed for SERS measurements. Compared to metallic colloids, a significant advantage of nanostructure based approach is that SERS signals are more stable against sample ionic strength. This is because the ionic strength can affect the aggregation of metallic colloids and adversely influence reproducibility. H. Wang et al. conducted quantitative analysis of creatinine in the urine of healthy and diabetic patients using Ag-coated parylene nanostructures as the SERS substrate, and successfully detected as low as 6.1 mg/dl urine creatinine. K. W. Kho et al. analyzed urine samples in a microfluidic device embedded with Au-coated polystyrene nanosphere arrays as the SERS substrate. Among existing reports, the lowest detectable concentration was 0.1 μg/ml (˜0.88 μM) in water, and 2.56 mg/dl in real urine samples.
Although SERS has the potential for creatinine sensing, both the limit of detection and reproducibility need further improvement for practical application. As mentioned previously, colloidal SERS substrates suffer from sample ionic strength dependent aggregation. Planar nanostructures, on the other hand, may not provide low enough detection limit, because the surface area within the source laser footprint is small and the light-matter interaction is limited. This calls for the development of robust, uniform, and reproducible SERS substrates and reliable measurement techniques.

Method of stamping surface-enhance Raman spectroscopy for label-free, multiplexed, molecular sensing and imaging


An interproximal brush for carrying on the person has an elongated one piece body member of elastomeric material forming a planar surface disposed between two leg members from which a substantially rigid boss extends for supporting a brush member. A plurality of hinges are formed in the body member at either side of the boss and the oppositely extending leg members are folded one adjacent the other and attached for slidable movement relative to one another. The planar surface is disposed transverse to the direction of relative movement of the leg members and rotates to move the brush from a position in alignment with the direction of movement of the leg members to a position forming an angle with the direction of movement of the leg members, when the leg members are moved relative to one another. The one piece body member may also be made foldable in the opposite direction to encase the brush within the leg members.

The present invention relates to interproximal brush devices for oral care, and more particularly to a brush device which is compact in structure and capable of being carried on the person of the user.
Various teeth cleaning aids have been provided which perform the cleaning of ones teeth and massaging of the gums, the brushes taking on various forms such as wire bristles or foam material and generally are designed to rub or wipe perpendicularly across the gum and tooth surfaces. One brush which has been found useful in this manner is a small, twisted, wire-type, disposable brush wherein bristles are captured between, and extend radially from a pair of twisted metal wires. Brushes of this type are shown and described in U.S. Pat. No. 4,780,923 issued to Schultheiss and U.S. Pat. No. 5,029,358 issued to Zimmerman, both assigned to the assignee of the present invention. These devices have met with commercial success, however due to their construction they are primarily limited for usage in the home as they are not simple to carry on the person of the user. It is therefore necessary to employ the use of toothpicks of wood, or other material, when it is desired to perform a cleaning function between the teeth when the user is at locations other than in the home. However, the use of such devices often is not as satisfactory as the employment of a brush of the type set forth above.
In view of the present emphasis on oral hygiene, and in particular the maintaining of cleanliness in those areas between the teeth on a daily basis, a need has arisen for an interproximal brush which may be easily carried on the person and which is simple to use.
It is therefore an object of the present invention to provide an interproximal brush which is compact in structure and easily carried on the person.
Another object of the invention is to provide an interproximal brush of the type set forth above which is simple in construction and easy to manufacture.
A further object of the invention is to provide an interproximal brush of the type set forth above which is economical to manufacture and therefore economical for the user to replace after a period of usage.


A method and apparatus for an FCC process uses means for dissipating turbulent flow at the outlet of a disengaging vessel to provide a quick separation of catalyst from product vapors and to prevent reentrainment of catalyst into the disengaging vessel. The process and apparatus use a riser for the conversion of an FCC feedstock and direct the effluent from the riser directly into a disengaging vessel to separate catalyst from the product vapors. Catalyst is directed downwardly out of the outlet of the disengaging vessel and through a series of dissipator plates that dissipate turbulent flow by eliminating the tangential velocity that would be other-wise introduced by the vortex and would lead to reentrainment of catalyst. A stripping vessel is located immediately below the disengaging vessel outlet to receive catalyst as it leaves the dissipator plates.

1. Field of the Invention
This invention relates generally to methods and apparatus for fluidized catalytic cracking (FCC) units. More specifically this invention relates to methods for separating catalyst from product vapors in an FCC reaction zone.
2. Description of the Prior Art
The fluidized catalytic cracking of hydrocarbons is the main stay process for the production of gasoline and light hydrocarbon products from heavy hydrocarbons such as vacuum gas oils. Large hydrocarbon molecules associated with the heavy hydrocarbon feed are cracked to break large hydrocarbon chains thereby producing lighter hydrocarbons. These lighter hydrocarbons are recovered as product and can be used directly or further processed to raise the octane barrel yield relative to the heavy hydrocarbon feed.
The basic equipment or apparatus for the fluidized catalytic cracking of hydrocarbons has been in existence since the early 1940's. The basic component of the FCC process include a reactor, a regenerator and a catalyst stripper. The reactor includes a contact zone where the hydrocarbon feed is contacted with a particulate catalyst and a separation zone where product vapors from the cracking reaction are separated from the catalyst. Further product separation takes place in a catalyst stripper that receives catalyst from the separation zone and removes entrained hydrocarbons from the catalyst by countercurrent contact with steam or another stripping medium. The FCC process is carried out by contacting the starting material, whether it be vacuum gas oil, reduced crude or another source of relatively high boiling hydrocarbons with a catalyst made up of a finely divided or particulate solid material. The catalyst is transported like a fluid by passing gas or vapor through it at sufficient velocity to produce a desired regime of fluid transport. The contact of the oil with fluidized material catalyses the cracking reaction. During the cracking reaction coke is deposited on the catalyst.
Coke is comprised of hydrogen and carbon and can include other materials in trace quantities such as sulfur and metals that enter the process with the starting material. Coke interferes with the catalytic activity of the catalyst by blocking active sites on the catalyst surface where the cracking reactions take place. Catalyst is transferred from the stripper to a regenerator for purposes of removing the coke by oxidation with an oxygen-containing gas. An inventory of catalyst having a reduced coke content, relative to the catalyst in the stripper, hereinafter referred to as regenerated catalyst, is collected for return to the reaction zone. Oxidizing the coke from the catalyst surface releases a large amount of heat, a portion of which escapes the regenerator with gaseous products of coke oxidation generally referred to as flue gas. The balance of the heat leaves the regenerator with the regenerated catalyst. The fluidized catalyst is continuously circulated from the reaction zone to the regeneration zone and then again to the reaction zone. The fluidized catalyst, as well as providing a catalytic function, acts as a vehicle for the transfer of heat from zone to zone. Catalyst exiting the reaction zone is spoken of as being spent, i.e., partially deactivated by the deposition of coke upon the catalyst. Specific details of the various contact zones, regeneration zones, and stripping zones along with arrangements for conveying the catalyst between the various zones are well known to those skilled in the art.
The rate of conversion of the feedstock within the reaction zone is controlled by regulation of the temperature of the catalyst, activity of the catalyst, quantity of the catalyst (i.e., catalyst to oil ratio) and contact time between the catalyst and feedstock. The most common method of regulating the reaction temperature is by regulating the rate of circulation of catalyst from the regeneration zone to the reaction zone which simultaneously produces a variation in the catalyst to oil ratio as the reaction temperatures change. That is, if it is desired to increase the conversion rate an increase in the rate of flow of circulating fluid catalyst from the regenerator to the reactor is effected. Since the catalyst temperature in the regeneration zone is usually held at a relatively constant temperature, significantly higher than the reaction zone temperature, any increase in catalyst flux from the relatively hot regeneration zone to the reaction zone affects an increase in the reaction zone temperature.
The hydrocarbon product of the FCC reaction is recovered in vapor form and transferred to product recovery facilities. These facilities normally comprise a main column for cooling the hydrocarbon vapor from the reactor and recovering a series of heavy cracked products which usually include bottom materials, cycle oil, and heavy gasoline. Lighter materials from the main column enter a concentration section for further separation into additional product streams.
The catalyst particles employed in an FCC process have a large surface area, which is due to a great multitude of pores located in the particles. As a result, the catalytic materials retain hydrocarbons within their pores and upon the external surface of the catalyst. Although the quantity of hydrocarbon retained on each individual catalyst particle is very small, the large amount of catalyst and the high catalyst circulation rate which is typically used in a modem FCC process results in a significant quantity of hydrocarbons being withdrawn from the reaction zone with the catalyst.
Therefore, it is common practice to remove, or strip, hydrocarbons from spent catalyst prior to passing it into the regeneration zone. It is important to remove retained spent hydrocarbons from the spent catalyst for process and economic reasons. First, hydrocarbons that entered the regenerator increase its carbon-burning load and can result in excessive regenerator temperatures. Stripping hydrocarbons from the catalyst also allows recovery of the hydrocarbons as products. Avoiding the unnecessary burning of hydrocarbons is especially important during the processing of heavy (relatively high molecular weight) feedstocks, since processing these feedstocks increases the deposition of coke on the catalyst during the reaction (in comparison to the coking rate with light feedstocks) and raises the combustion load in the regeneration zone. Higher combustion loads lead to higher temperatures which at some point may damage the catalyst or exceed the metallurgical design limits of the regeneration apparatus.
The most common method of stripping the catalyst passes a stripping gas, usually steam, through a flowing stream of catalyst, countercurrent to its direction of flow. Such steam stripping operations, with varying degrees of efficiency, remove the hydrocarbon vapors which are entrained with the catalyst and hydrocarbons which are adsorbed on the catalyst. Contact of the catalyst with a stripping medium may be accomplished in a simple open vessel as demonstrated by U.S. Pat. No. 4,481,103.
The efficiency of catalyst stripping is increased by using vertically spaced baffles to cascade the catalyst from side to side as it moves down a stripping apparatus and countercurrently contacts a stripping medium. Moving the catalyst horizontally increases contact between the catalyst and the stripping medium so that more hydrocarbons are removed from the catalyst. In these arrangements, the catalyst is given a labyrinthine path through a series of baffles located at different levels. Catalyst and gas contact is increased by this arrangement that leaves no open vertical path of significant cross-section through the stripping apparatus. Further examples of these stripping devices for FCC units are shown in U.S. Pat. Nos. 2,440,620; 2,612,438; 3,894,932; 4,414,100; and 4,364,905. These references show the typical stripper arrangement having a stripper vessel, a series of baffles in the form of frusto-conical sections that direct the catalyst inwardly onto a baffle in a series of centrally located conical or frusto conical baffles that divert the catalyst outwardly onto the outer baffles. The stripping medium enters from below the lower baffle in the series and continues rising upward from the bottom of one baffle to the bottom of the next succeeding baffle. Variations in the baffles include the addition of skirts about the trailing edge of the baffle as depicted in U.S. Pat. No. 2,994,659 and the use of multiple linear baffle sections at different baffle levels as demonstrated by FIG. 3 of U.S. Pat. No. 4,500,423. A variation in introducing the stripping medium is shown in U.S. Pat. No. 2,541,801 where a quantity of fluidizing gas is admitted at a number of discrete locations.
As the development of FCC units has advanced, temperatures within the reaction zone were gradually raised. It is now commonplace to employ temperatures of about 525.degree. C. At higher temperatures, there is generally a loss of gasoline components as these materials crack to lighter components by both catalytic and strictly thermal mechanisms. At 525.degree. C., it is typical to have 1% of the potential gasoline components thermally cracked into lighter hydrocarbon gases. As temperatures increase, to say 550.degree. C., most feedstocks can lose up to 6% or more of the gasoline components to thermal cracking. However, the loss of gasoline can be offset by the often more desirable production of light olefins.
One improvement to FCC units, that has reduced the product loss by thermal cracking, is the use of riser cracking. In riser cracking, regenerated catalyst and starting materials enter a pipe reactor and are transported upward by the expansion of the gases that result from the vaporization of the hydrocarbons, and other fluidizing mediums if present upon contact with the hot catalyst. Riser cracking provides good initial catalyst and oil contact and also allows the time of contact between the catalyst and oil to be more closely controlled by eliminating turbulence and backmixing that can vary the catalyst residence time. An average riser cracking zone today will have a catalyst to oil contact time of 1 to 5 seconds. A number of riser reaction zones use a lift gas as a further means of providing a uniform catalyst flow. Lift gas is used to accelerate catalyst in a first section of the riser before introduction of the feed and thereby reduces the turbulence which can vary the contact time between the catalyst and hydrocarbons.
In most reactor arrangements, catalysts and conversion products still enter a large chamber for the purpose of initially disengaging catalyst and hydrocarbons. The large open volume of the disengaging vessel exposes the hydrocarbon vapors to turbulence and backmixing that continues catalyst contact for varied amounts of time and keeps the hydrocarbon vapors at elevated temperatures for a variable and extended amount of time. Thus, thermal cracking can be a problem in the disengaging vessel. A final separation of the hydrocarbon vapors from the catalyst is performed by cyclone separators that use centripedal acceleration to disengage the heavier catalyst particles from the lighter vapors which are removed from the reaction zone.
In order to minimize thermal cracking in the disengaging vessel, a variety of systems for directly connecting the outlet of the riser reactor to the inlet of a cyclone are suggested in the prior art. A majority of the hydrocarbon vapors that contact the catalyst in the reaction zone are separated from the solid particles by ballistic and/or centrifugal separation methods within the reaction zone. Directly connecting the inlet of a first cyclone and the outlet the first cyclone to the inlet of a second cyclone in what has been termed a "direct connected cyclone system" can greatly reduce thermal cracking of hydrocarbons. Unfortunately in most cases direct connected cyclones will increase the complexity of operating an FCC unit. When the cyclones are directly connected to the riser any pressure surges that normally occur in the FCC unit can cause the cyclones to malfunction and lead to the carry-over of catalyst into the main column and separation facilities for the recovery of the product. A number of different riser and cyclone arrangements are shown in the prior art to increase the reliability of the cyclone operation when the riser is directly connected thereto.
One way in which to overcome the problem of pressure surges and catalyst carry over is to connect a separation device having a large capacity to the outlet of the riser. Such a separation device is shown in FIG. 8 of U.S. Pat. No. 4,689,206. This separation device provides a disengagement of the catalyst and product vapor mixture before the mixture enters the relatively small volume of an ordinary cyclone. Due to its large volume the separation device is not easily overloaded and ordinary pressure surges will not interrupt its operation. However such large separation devices suffer from low separation efficiencies that increase the particle load on the downstream cyclones or require the use of two stage cyclones or must have a relatively long length to provide a high separation efficiency. Reduced efficiencies are in large part caused by the reentrainment of catalyst particles with the gas as it flows out of the separation device.

Integrated disengager stripper and its use in fluidized catalytic cracking process


The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

1. Field of the Invention
The present invention relates to a method for forming a semiconductor microstructure and a method for fabricating a resonance tunneling device. More particularly, the present invention relates to a method for forming a silicon (Si) microstructure on an SIMOX (separation by implanted oxygen) substrate by use of crystal anisotropic etching and a method for fabricating a resonance tunneling device having such a silicon microstructure.
2. Description of the Related Art
In recent years, quantization functional devices utilizing a quantum effect have been studied and developed. Among these quantization functional devices, a resonance tunnel diode utilizing a resonance tunnel effect has been proposed and studied. A method for fabricating such a resonance tunnel diode is disclosed in Japanese Laid-Open Patent Publication No. 7-312419, where an etching mask having two etching windows which are close to each other and parallel to the <211> direction is formed on a (110) SIMOX substrate, and a narrow Si microstructure is formed under the etching mask by controlling an Si etching amount by crystal anisotropic etching, to be used as a quantum well of a resonance tunnel diode.
The above conventional method for forming a semiconductor microstructure has the following problems. First, due to limitations of the present alignment technique or an error in the measurement of the orientation of a substrate, the direction where the etching windows extend and the <211> direction of the substrate may not be strictly parallel, but may be deviated from each other to some extent. When the etching mask has long etching windows for the formation of a long Si microstructure, the etching proceeds toward a direction parallel to the <211> direction, finally reaching an edge of the etching mask, and thus an Si microstructure cut halfway may be formed.
Secondly, in the conventional lithographic technique, the space between the etching windows cannot be made so narrow for the reason of the limitation of the light wavelength. A very narrow space between the etching windows is also difficult for other reasons. For example, if the space is very narrow, extremely high a precision is required at the alignment in the subsequent lithographic step. A method employing electron beam drawing and the like has been proposed to overcome these problems. However, this method does not seem to be practical in consideration of the drawing cost and throughput. This method entails difficulty even when used for research.
Thirdly, in the conventional method for forming a semiconductor microstructure, though the width of the semiconductor microstructure is controlled by the etching amount, the etching amount is difficult to be monitored during etching.
Therefore, there is a strong need in the art for a method for fabricating a semiconductor microstructure and a resonance tunneling device which overcomes the above-mentioned problems associated with conventional methods.

Method for forming semiconductor microstructure, semiconductor device fabricated using this method, method for fabricating resonance tunneling device, and resonance tunnel device fabricated by this method

Matsushita Electric Industrial Co., Ltd.


A spring clip is arranged to include confronting first and second clamp plates biased together by a spring member mounted between first and second actuator plates, with the actuator plates biased towards one another by the spring member. The first and second actuator plates are arranged in a parallel fixed relationship relative to the first and second clamp plates and pivotal relative to one another about an axle shaft. The first and second clamp plates include resilient engaging projections to enhance securement of a paper workpiece directed therebetween. Further, second actuator plates of a plurality of the spring clip members may be assembled together by utilizing fastener plugs directed through the respective second actuator plates.

1. Field of the Invention
The field of invention relates to paper clip structure, and more particularly pertains to a new and improved spring clip wherein the same is arranged to secure workpieces, and particularly flexible web workpieces together.
2. Description of the Prior Art
Clamp structure of various types have been utilized throughout the prior art to permit the securement and fastening of various paper webs together. Such clip structure is exemplified in the U.S. Pat. No. 4,562,618; 4,594,016; 3,531,841; and U.S. Design Pat. No. 257,924.
The mounting of various files together in a convenient and accessible manner as addressed by and exemplified in the prior art has heretofore been arranged to confront various problems in the association of such file structure. The instant invention attempts to overcome deficiencies of the prior art in addressing the securement of a plurality of clip members together, as well as the positive mounting of various filing webs to include sheets of paper and the present invention sets forth such structure in a convenient and compact organization and in this respect, the present invention sets forth improvements of the prior art not addressed therein.