A cross-sectionally substantially-semicircular portion of an edge portion adapted to connect an outer periphery of a diaphragm to a speaker frame is configured to have an uneven-thickness structure in which the thickness of the portion gradually decreases toward a sticking portion of an outer peripheral portion of the speaker frame from a sticking portion of the outer periphery of the diaphragm. Thus, the propagation characteristic of vibrations generated on the edge portion is improved. Disturbance is prevented from occurring in an mid-range frequency characteristic due to inverse resonance caused by the edge portion.

1. Field of the Invention
The present invention relates to a speaker apparatus in which an outer periphery of a diaphragm is supported by a speaker frame through a cross-sectionally semicircular edge portion and in which an inner periphery of the diaphragm is supported by the speaker frame through what is called a corrugation damper.
2. Description of the Related Art
FIG. 1 is a longitudinally cross-sectional view illustrating a related speaker apparatus.
This speaker apparatus 1 has a magnetic circuit 3, a speaker frame 5 having a rear portion to which this magnetic circuit 3 is attached, a cone diaphragm 7 having an outer periphery to which a cross-sectionally substantially-semicircular edge portion 9 is continuously provided, a cylindrical voice coil bobbin 11 attached to an inner peripheral edge of the diaphragm 7, and a voice coil 12 wound around this voice coil bobbin 11.
The magnetic circuit 3 consists of a yoke 15 in which a cylindrical center pole 15b is provided on a disk-like plate 15a to protrude therefrom, a ring-like magnet 16 loosely fitted to an outer periphery of the center pole 15b, and a ring-like top plate 17 loosely fitted to a front end side of the center pole 15 to sandwich the magnet 16 between the plate 25a and the top plate 17. The top plate 17 is fixed to a rear end of the speaker frames.
In this magnetic circuit 3, the gap between the inner periphery of the top plate 17 and the center pole 15b is a magnetic gap in which the voice coil 12 is disposed.
The voice coil bobbin 11 fixed to the inner peripheral edge of the diaphragm 7 is connected to the speaker frame 5 through the corrugation damper 19 of a structure in which ridge and groove portions are alternately and coaxially arranged along a radial direction, thereby being hung movably in the direction of an axis of the center pole 15b.
A mounting flange portion 9a extended from the outer peripheral rim of the outer peripheral edge member 9 connected to the diaphragm 7 is stuck to an outer peripheral portion 5a of the speaker frame 5. Thus, the diaphragm 7 is displaceably supported by the edge member 9.
That is, the diaphragm 7 has an outer peripheral portion connected to the outer peripheral portion 5a of the speaker frame 5 through the edge member 9, and also has an inner peripheral portion connected to the speaker frame 5 through a corrugation damper 19. Thus, the diaphragm 7 is elastically supported to be able to displace back and front.
It has turned out that in this speaker apparatus, the insurance of amplitude symmetry, that is, the equalization of forward and backward amplitudes of the diaphragm 7 is a major factor of suppressing occurrence of distortion of speaker sound to thereby improve sound quality.
Thus, hitherto, to ensure the amplitude symmetry, the stiffness of the edge member 9, which supports the diaphragm, and that of the corrugation damper 19 are adjusted by conditioning materials to be used.
Incidentally, in the related apparatus, usually, the edge member 9 has a cross-sectional structure in which the thickness of a cross-sectionally substantially-semicircular part thereof is uniform. However, an edge member, which is configured to have a laminated structure made of different kinds of materials to thereby obtain desired stiffness, has been proposed (See, for example JP-A-11-187481).
Further, the corrugation damper 19 is usually set, as shown in FIG. 2. That is, a bending radius Ry of the top part of the ridge portion and a bending radius Rt of the top part of the groove portion satisfy the following equation.Ry=Rt.Also, a corrugation height Hy of the ridge portion and a corrugation depth Ht of the groove portion meet the following equation.Hy=Ht.That is, the corrugation damper 19 is usually designed so that the ridge portion and the groove portion have symmetric shapes, respectively. However, a speaker apparatus, which is adapted to obtain desired stiffness by setting the corrugation heights, the corrugation depths and the bending radii R of the ridge and groove portions to vary with the outer periphery and the inner periphery, has been proposed (see, for instance, JP-A-2003-37893).


The present invention relates to an NPN transistor, the base and the emitter of which are formed within a window defined in a thick oxide according to a first substantially rectangular mask. At least a portion of the area defined by the first mask is covered with a polysilicon layer, preferably along a side of this first mask, a base contact area being formed under this polysilicon layer, the three other sides of the emitter-base area being delimited by a protection layer, an intrinsic base area, and then an emitter area covered with a doped N-type polysilicon layer, being formed in the opening thus defined.

1. Field of the Invention
The present invention relates to the field of integrated circuits and more specifically to the fabrication of an NPN transistor.
2. Discussion of the Related Art
In patent application filed on even day herewith under attorney docket number S1022/7945 and incorporated herein by reference, a method for fabricating a bipolar transistor compatible with a BICMOS technology (that is, a technology enabling the simultaneous fabrication of bipolar transistors and of complementary MOS transistors) is described.
An example of NPN transistor obtained by using a BICMOS technology is shown in FIG. 12A of the above-mentioned patent application, which is reproduced in appended FIG. 1.
This NPN transistor is formed in an epitaxial layer 2 which is above a buried layer 3 formed in a P-type silicon substrate (not shown). The transistor is formed in a window made in a thick oxide layer 5. References 21 and 22 designate thin silicon oxide and silicon nitride layers which are used to protect other elements of the integrated circuit (such as CMOS transistors) during the fabrication of the bipolar transistor. Reference 23 designates a portion of a P-type doped polysilicon layer called base polysilicon since the base contact diffusion 32 is formed from this silicon layer. Polysilicon layer 23 is coated with an encapsulation silicon oxide layer 24. A central emitter-base opening is formed in layers 23 and 24 altogether. A thin silicon oxide layer 31 covers the sides of polysilicon layer 23 and the bottom of the opening. In this opening, an N-type high energy implant meant for forming a sub-collector region with a selected doping level is performed. The walls of the emitter-base opening are coated with a silicon nitride layer 44. Polysilicon lateral spacers 43 are formed on the sides of the opening. Before the forming of silicon nitride region 44 and of polysilicon spacers 43, an intrinsic base implant 33 is formed. After the spacers have been formed, a highly-doped N-type polysilicon layer 46 from which is formed emitter region 49 is deposited. Polysilicon layer 46 is coated with an encapsulation oxide layer 47. The general structure is coated with an insulating and planarizing layer 51 through which are formed emitter contact openings 55 joining polysilicon layer 46 and base contact openings 56 joining polysilicon layer 23. Further, a collector contact (not shown) is made via an N-type drive-in 30 towards buried layer 3.
This transistor has a circular symmetry, the emitter being centrally positioned and the base polysilicon being ring-shaped around this emitter.

Method for fabricating an NPN transistor of minimum surface


A semiconductor device has a semiconductor substrate and a breakdown voltage adjusting first conductivity type low concentration region provided on the semiconductor substrate. A second conductivity type high concentration region is provided near a surface within the breakdown voltage adjusting first conductivity type low concentration region so as to be surrounded by the first conductivity type low concentration region but not surrounded by any low concentration region other than the first conductivity type low concentration region. A first conductivity type high concentration region is provided on the surface within the breakdown voltage adjusting first conductivity type low concentration region without being held in contact with the second conductivity type high concentration region.

1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a clamp diode used in a semiconductor device.
2. Description of the Related Art
A clamp diode is a device which uses a junction breakdown voltage between the p-type semiconductor and the n-type semiconductor to maintain (clamp) a voltage supplied to a circuit constant in a semiconductor device. Since a clamp diode is a device capable of limiting a voltage easily, there is a high demand and a wide usage in electronic devices.
When manufacturing a clamp diode, which limits a voltage to be constant, it is extremely important for the clamp diode to have small fluctuations in breakdown voltage within a wafer, among wafers, and among lots, and to have little change over time. In addition, it is also important for the clamp diode to have a small leakage current until breakdown occurs. Even though the structure of the clamp diode is simple, it is not easy to produce a clamp diode which satisfies all of the above-mentioned characteristics.
Japanese Published Patent Application No. 11-307787 discloses the invention for improving the above-mentioned change over time. FIG. 7 is a cross-sectional view of the structure illustrated in FIG. 1 of the Japanese Published Patent Application. There is described that, as illustrated in FIG. 7, a second conductivity type high concentration region 1 is placed away from an element isolation insulating film 2 by a predetermined distance, and further, an electrode 8 is provided through the intermediation of an insulating film 9, thereby adjusting a voltage of the electrode 8 to improve the change in the clamp diode over time. FIG. 8 is a cross-sectional view of the structure illustrated in FIG. 6 of the Japanese Published Patent Application. As shown in this structure, there is described that the same effect can be obtained even without the electrode 8 of FIG. 7.
Though the change over time can be improved by the invention disclosed in the Japanese Published Patent Application, there is no description, however, on the degree of fluctuations within a wafer, between wafers, and among lots, and the presence or absence of leakage before breakdown occurs. Indeed, in the invention disclosed in the Japanese Published Patent Application the fluctuations within a wafer, between wafers, and among lots are not reduced because of the following reasons.
Since an electric field corresponding to a voltage applied to the electrode 8 is applied to a p-n junction through the oxide film 9 in the structure illustrated in FIG. 7, the electric field is thought to be constant and the p-n junction breakdown voltage does not seem to fluctuate due to the electric field. Ideally, when the same voltage is applied to the electrodes 8, the breakdown voltages are the same. However, actually, the thicknesses of the oxide films 9 are not the same within a wafer, between wafers, and among lots, and hence the electric fields applied to the p-n junctions by the voltages of the electrodes 8 fluctuate. As a result, the p-n junction breakdown voltages fluctuate.
Further, due to the presence of a first conductivity type region 7 below the element isolation insulating film 2 of FIGS. 7 and 8, impurities in the first conductivity type region 7 affect impurity distribution near the p-n junction, and the breakdown voltage of the p-n junction changes. Also in this regard, ideally, when the first conductivity type regions 7 are produced in the same condition, the breakdown voltages of the p-n junctions are the same. Actually the concentrations of impurities in the first conductivity type regions 7, however, are not the same within a wafer, between wafers, and among lots, and the p-n junction breakdown voltages are affected to various degrees. As a result, the p-n junction breakdown voltages fluctuate.
According to the Japanese Published Patent Application No. 11-307787, a planar shape of the second conductivity type high concentration region 1 of FIG. 7 is octagon (not shown in this specification). In such a structure having corners, electric field strength is high at a corner portion, and therefore the breakdown voltage is determined by the corner portion. FIG. 9 shows the breakdown voltages in the case where the planar shape of the second conductivity type high concentration region 1 is rectangular and in the case where the planar shape thereof is circular. It is apparent that the breakdown voltage is lower in the case of the clamp diode having the rectangular second conductivity type high concentration region 1 than in the case of the clamp diode having the circular second conductivity type high concentration region 1. That is, it is apparent that the electric field is concentrated at the corner portions of the rectangle, and the corner portions determine the breakdown voltage. Ideally, the breakdown voltages of the p-n junctions will be the same since the shapes of the corner portions are always the same when lithography is performed in the same condition. Actually the electric field strength at the corner portions, however, fluctuates within a wafer, between wafers, and among lots. As a result, the p-n junction breakdown voltages fluctuate.
As described above, there are many factors that cause the breakdown voltages of the p-n junctions to fluctuate, and, in order to suppress such fluctuations, the clamp diode needs to have a structure as simple as possible, and the factors that cause fluctuations need to be eliminated as much as possible.


An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n− semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n+ first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.

The present invention relates to a vertical power semiconductor device (hereinafter referred to as "power device") primarily made of a silicon carbide (SiC) semiconductor material and capable of voltage driving through an insulated gate.
Devices that handle a large amount of electric power, so-called power devices, have been conventionally manufactured by primarily using silicon semiconductors. Since a power device can have a large electric current capacity, it often has a structure in which electric current flows in the thickness direction (vertical direction) between the two principal planes of the chip. Among such conventional power devices is a vertical insulated gate field effect transistor. FIG. 9 is a cross-sectional view of a conventional representative vertical insulated gate field effect transistor (MOSFET).
The cross-sectional view shown in FIG. 8 is the basic structure of a well known device called a static induction transistor (hereinafter abbreviated as "SIT"). The SIT structure includes gates obtained by selectively burying p+ regions 54 in an n-type high-resistance (low-concentration) drift layer 53 deposited on an n+ semiconductor substrate 51. When a negative bias is applied to the gate with respect to a drain 56 provided on the underside of the semiconductor substrate 51, a depletion layer expands in a pinch-off region 52 provided between each pair of the p+ regions 54, which are the gates, and blocks the electric current path from the drain 56 through the pinch-off region 52 and an n+ source region 57 to a source 58. Such SIT devices are characterized by a monopolar structure in which electric current basically only flows through n-type regions, so that small on-resistance close to an ideal value is likely provided. Prototype devices have been reported having the SIT structure using SiC semiconductors with excellent characteristics as well as those using silicon semiconductors. However, the basic structure of the SIT device is in the conducting state when no bias is applied to the gate (normally-on). Therefore, when the gate drive circuit malfunctions due to noise or the like and hence no gate voltage is applied, the device remains conducting, possibly resulting in a serious failure, such as breakdown of the circuit in the worst case. Use of the SIT device requires caution in the gate bias conditions, which poses difficulty in using the SIT device.
The vertical MOSFET, an insulated gate-driven device, is frequently used as the power device described above. FIG. 9 shows a typical planar gate MOSFET in which gate insulating films 124 and gate electrodes 111, each having a flat shape, are formed on the principal plane of a semiconductor substrate (100+103). In FIG. 9, n+ surface regions 121 provided immediately under the gate insulating films 124 located on both sides of a p-well 113 in the substrate surface are not formed in many cases. When reduction in size of the unit pattern for lowering on-resistance of the power device narrows the region immediately under the gate insulating film 124 sandwiched between the p-wells 113 in adjacent unit patterns, the pinch-off resistance increases because a depletion layer expands when a bias is applied to a drain electrode 106. To prevent the pinch-off resistance and hence the on-resistance from increasing, the high-concentration n+ surface regions 121 are provided. The concentration (impurity concentration) is approximately 1×1018 cm−3 at the most, because higher concentrations prevent the depletion layer from expanding along the surface, resulting in reduction in blocking voltage. Reference numeral 111 denotes the gate electrode. Reference numeral 104 denotes an interlayer insulating film. Reference numeral 105 denotes an emitter electrode. Reference numeral 114 denotes an emitter region. Reference numeral 115 denotes a contact high-concentration p+ region.
In the vertical MOSFET, unlike the SIT shown in FIG. 8, the on-resistance of the element includes not only the resistance of the n-type semiconductor region (the high-resistance drift layer 103, in particular) but also the resistance in channel regions that are located immediately under the gate electrodes 111 and the gate insulating films 124, and formed in the surfaces of the p-well 113 sandwiched between the emitter regions 114 and the high-concentration n+ surface regions 121. The total resistance of the channel regions in the whole element decreases when the size of the unit pattern is reduced to increase the channel density, since the channel regions are arranged in parallel. Accordingly, to lower the on-resistance of the whole element, the unit pattern is preferably configured in such a way that the channel density is maximized.
The cross-sectional view of FIG. 10 shows a conventional trench gate MOSFET devised in such a way that more reduction in channel resistance through the size reduction described above is achieved than in the planar gate MOSFET. In the trench gate structure indicated by a gate electrode 223, a gate insulating film 224, and a trench 235, the trench 235 extends downward perpendicularly to the principal plane, so that the trench density along the surface can be easily increased. The trench gate structure (223, 224, and 235) therefore easily achieves a higher channel density than that in the planar gate structure shown in FIG. 9. Furthermore, in the trench gate structure, the fact that the pinch-off resistance in the region sandwiched between p-wells 225 structurally decreases makes the trench gate MOSFET more advantageous than the planar gate MOSFET from the viewpoint of the pinch-off resistance. Reference numeral 220 denotes an n+ semiconductor substrate. Reference numeral 222 denotes a high-resistance drift layer. Reference numeral 228 denotes an n+ emitter region. Reference numeral 226 denotes a p+ contact region. Reference numeral 230 denotes an interlayer insulating film. Reference numeral 227 denotes an emitter electrode.
However, in a silicon power device, since the channel density has already been almost maximized by making full use of the process technology of the trench gate structure and the LSI microprocessing technology, the semiconductor characteristics of the silicon power device have approached the limit determined by the material. To break through this material limit, there have been attempts to change the semiconductor material from silicon to any of those having broader band gaps, such as SiC and GaN. Since the maximum breakdown fields of these materials are larger by approximately one order of magnitude than that of silicon, it is expected that use of any of these materials for a power device lowers the resistance of the element to one hundredth or smaller. Prototypes of SiC-MOSFET devices and SiC-SIT devices having structures similar to those of silicon devices have been built and have shown excellent characteristics.
JP-A-2006-147789 and corresponding European Patent Publication EP 1,814,162 A1 describe a SiC-MOSFET in which the on-resistance is lowered by forming a structure including an n+ SiC substrate, an n-type high-resistance (low-concentration) drift layer stacked thereon, a high-concentration p-gate layer buried therein, and a MOS channel region further formed thereon, the MOS channel region being a low-concentration p-type deposition layer. It is necessary to selectively convert the p-type deposition layer into an n-type base region through ion implantation to form an electric current path. However, the n-type base region cannot be thick due to the practical limit of depth to which ions can be implanted (equal to the thickness of the p-type deposition layer), so that a high electric field is applied to the gate insulating film and hence the off-state voltage is not improved. To solve this problem, the above-referenced documents reported interposing a low-concentration n-type deposition layer between the low-concentration p-type deposition film and the high-concentration gate layer of a SiC MOSFET. The base region converted into the n-type through ion implantation is selectively formed in the low-concentration p-type deposition film so as to increase the thickness of the n-type deposition film between the high-concentration gate layer and the low-concentration p-type deposition film (channel region).
JP-A-2001-94097 discloses a MOSFET device as shown in the cross-sectional view of the semiconductor substrate of the MOSFET in FIG. 11. This device includes an n+ channel layer 305a deposited on the exposed surface of an n− epitaxial layer 302a stacked on an SiC-n+ substrate 1 and on part of the surfaces of p− base regions 303a and 303b, n+ source regions 304a and 304b formed in the surface portions of the p− base regions 303a and 303b, ion implanted p-type channel layers 305b, one of the channel layers sandwiched between the n+ source region 304a and the n-type channel layer 305a and the other sandwiched between the n+ source region 304b and the n-type channel layer 305a, and a gate electrode 308 formed above the channel layers 305b and the n-type channel layer 305a via a gate insulating film 307. This SiC semiconductor device not only has the MOSFET channel structure having the normally-off capability but also a capability to lower the on-resistance even when the depletion layer expands between the p− base regions 303a and 303b at the time of ON by increasing the concentration in the n-type channel layer 305a.
As described above, a MOSFET made of a silicon carbide semiconductor is expected to have an excellent blocking voltage characteristic because the dielectric breakdown field of a silicon carbide semiconductor is higher than that of a silicon semiconductor by one order of magnitude. However, a SiO2 film is primarily used as the gate insulating film as in silicon semiconductor, that is, a large blocking voltage cannot be provided in many cases. Corners are formed on the gate insulating film and the electric field concentrates at the corners of the gate insulating film, so that an excessive electric field is applied, particularly in a trench MOSFET. An electric field normally applied in SiC therefore cannot be applied, so that only a much lower blocking voltage is provided. Accordingly, to avoid the problem of reduced blocking voltage due to dielectric breakdown of the gate insulating film in silicon carbide semiconductor, a planar gate MOSFET has been fabricated as a prototype in many cases.
Since a SiC semiconductor has lower channel mobility in a MOSFET than a silicon semiconductor, a high-density channel structure is more desirable to lower the channel resistance than in silicon semiconductor. However, a sufficiently high-density channel structure is not always provided since a SiC semiconductor needs to employ a planar gate MOSFET as described above, which suffers from a low level of channel size reduction. Since a SIT uses no gate insulating film, it does not have the problem of insulating film breakdown described above. However, a SIT is a so-called normally-on device, that is, it has source-drain continuity in the no-bias state in which no voltage is applied to the gate. This becomes a problem when a SIT is actually applied to a circuit, and hence a SIT is regarded as a hard-to-use device. In a practical circuit, when a problem occurs in a gate circuit and no voltage can be applied to the gate, a so-called normally-off device is preferable from the viewpoint of safety because a normally-off power device having such a defective gate automatically blocks electric current.
As a method to eliminate the normally-on device phenomenon from a power device having the SIT structure, there has been proposed a complex device structure shown in an equivalent circuit in FIG. 2. This device has a structure in which a SIT 16 and a MOSFET 15, which is a low blocking voltage normally-off device, are serially cascaded. When an off-state signal is applied to the gate 18 of the MOSFET 15, the MOSFET 15 becomes blocked, so that the potential at the source region of the SIT 16 increases. A negative bias is therefore applied to the gate of the SIT 16, so that the SIT 16 is also turned off. The device having such a configuration is a normally-off device without the normally-on device phenomenon. This configuration, however, results in a large on-resistance device in which the MOSFET 15 is added to the SIT 16, which means that the advantage of a SiC semiconductor device, namely small on-resistance with a small area, is lost.
In view of the points described above, it would be preferable to provide an insulated gate silicon carbide semiconductor device and a method for manufacturing the same, wherein the semiconductor device has small on-resistance, the advantage of the static induction transistor structure is fully used, and the advantage of the field effect transistor structure characterized by the normally-off operation is obtained, in a structure obtained by combining the static induction transistor structure with the insulated gate field effect transistor structure.

Insulated gate silicon carbide semiconductor device and method for manufacturing the same


An ultrasonic etching apparatus for chemically-etching a workpiece is disclosed. The apparatus includes an outer tank at least partially filled with an aqueous solution, an inner tank at least partially disposed within the outer tank and in contact with aqueous solution, the inner tank at least partially filled with an etching solution, a lid engaged with the mouth of said inner tank; and an ultrasonic transducer coupled to the outer tank to impart ultrasonic energy to the etching solution in said inner tank. Also disclosed are methods of using the apparatus to etch workpieces.

In a number of modern industrial processes it is necessary to etch materials uniformly. The etching may be confined to the material, or the etching process may be continued until the material is etched through, thereby exposing an underlying material. In many industrial applications such as, for example, the fabrication of electronic, optical or optoelectronic workpieces, the etching steps form a very critical phase of workpiece fabrication, as the etching process typically dictates the accuracy to which the workpieces are ultimately manufactured.
There are often more than one hundred processing steps in the fabrication of semiconductor chips, including oxidation, diffusion, ion implantation, deposition of conductors and insulators, photolithography and etching. Various conducting and insulating layers are deposited uniformly over the wafer to a thickness of a few microns. In critical applications, certain new or used parts of semiconductor processing equipment need to be cleaned prior to installation and use in order to remove residual contamination from the initial machining or manufacturing process, or from the processing steps, in order to achieve levels of cleanliness similar to the semiconductor wafer itself and have its surface morphology restored. Furthermore, after many wafers have been processed, the equipment used in the semiconductor processing process becomes contaminated or deposits build-up and therefore becomes unusable.
For example, in an etching machine, polymer deposits on the outer circumference of electrodes or chucks supporting the wafers until it becomes thick enough to interfere with the wafer's contact with the electrode. This results in non-uniform etching across the wafer as well as missed transfers due to a wafer sticking to polymer buildup on the electrode. Non-uniformity exceeding seven percent is beyond some specified limits, in turn affecting side wall profile variance across the wafer. In addition, other components in the equipment chamber, e.g. roofs/domes and liners are also coated with polymers and contaminants which contribute particles, metallic and organic impurities to the wafers. Therefore, it is then necessary to disassemble the parts in the equipment chamber and clean the individual parts. Most types of dry processing equipment used for the manufacture of semiconductor devices utilize processes involving high temperatures, plasmas and gaseous mixtures for film deposition and etching. During these manufacturing processes, organic and inorganic by-products are deposited on the surfaces of workpiece parts.
Some apparati and devices are commercially available to etch workpieces, however, none is ideal. FIG. 1 shows a representative small-scale apparatus 100 of the prior art used to ultrasonically etch a semiconductor fabrication workpiece 102. An acidic solution 110 is placed into inner container 104 and ultrasonically agitated through aqueous solution 120 held in outer container 130. The entire apparatus is contained within an exhaust hood 150 for the capture of gases 140 that are emitted from the aqueous and acidic solutions as the etching reaction occurs. While representing an advance over earlier etching processes that did not include a concentrated acid or an ultrasonicator, apparatus 100 does not provide the ability to rotate workpiece 102 or create safe working conditions. Nor does apparatus 100 have capability to contain the gases or prevent unwanted components, e.g. impurities from environment and aerosol gases from the aqueous solutions, from entering the etching solution during the etching process, or to increase the partial pressure of the volatilized etching solution and to prevent change in the concentration of the etching solution due to aerosol or volatilisation losses. It also lacks a heating mechanism, probe, etc for regulating the temperature and a ultrasonic buffer for dampening and diffusing the energy for better control over the etch process.
Prior art apparatus 200 shown in FIG. 2 contains two beakers 202 and 204, which contain deionized water that is provided through opening 206, and which overflows into the beakers, which then overflows into the sonication tank 210. Ultrasonication transducer 220 is connected to power oscillator 220 to provide ultrasonic energy to the deionized water. This apparatus lacks a number of desired features, including, most significantly, the ability to contain an acid, the ability to rotate a workpiece being sonicated, a heating element, and an ultrasonic diffuser.
U.S. Pat. No. 6,199,563, which is incorporated by reference herein, adds a modest improvement to ultrasonicators of the prior art by including a rotational mechanism for sonicating a workpiece in an acid solution, but it fails to provide means for containing the acidic gases, preventing unwanted contaminants from the aqueous solution and/or rotational mechanism wear and tear from entering the acidic solution, the ability to increase the partial pressure of the acidic solution, or provide a safer working environment.
What is needed is a method and apparatus for containing the gases produced during ultrasonic agitation, minimizing exposure of the etching solution to the immediately surrounding environment which would thus prevent unwanted contaminants from the aqueous solution and/or rotational mechanism wear and tear from entering the etching solution during the etching process, the ability to increase the partial pressure of the etching solution which would inhibit the formation of dangerous vapors by keeping them in a liquid state, keeping the concentration of the etching solution stable, and the ability to provide a safer working environment. The present invention is designed to meet these needs by providing a more efficient, contaminant-free apparatus and method than those currently available such that semiconductor workpieces can be effectively cleaned and recycled to reduce manufacturing costs.

Ultrasonic assisted etch using corrosive liquids


Provided are an apparatus and method that obtain a numerical value for an evaluation value of an appearance of noise in a plurality of videos and that coordinate the appearance of noise based on the evaluation value. In an image processing apparatus that coordinates an appearance of noise among a plurality of videos, noise properties are obtained from the videos, and a noise evaluation value is calculated based on the noise properties. Based on the calculated noise evaluation value, noise to be added to the videos is calculated, and the added noise is then added to the videos.

1. Field of the Invention
The present invention relates to techniques for correcting an appearance of noise in a video.
2. Description of the Related Art
With recent advancements in digitization of videos, controlling an appearance of noise in digital videos has become an issue. Here, techniques such as that disclosed in Japanese Patent Laid-Open No. 2007-174667, which add noise that resembles film grain, and techniques such as that disclosed in Japanese Patent Laid-Open No. 2008-187260, which add noise to the location of a primary subject in order to improve a sense of sharpness, have been proposed as techniques for controlling the appearance of noise in a video.
When editing videos so as to synthesize videos, stitch videos together, or the like, a plurality of videos shot using different imaging devices, under different shooting conditions, and so on are edited into a single video. However, there are cases where differences in the appearance of noise between videos are evident after the editing, leaving a viewer with a sense of incongruity. Accordingly, it is necessary, when synthesizing videos, stitching videos together, or the like, to coordinate the appearance of noise between the plurality of videos in advance.
However, Japanese Patent Laid-Open No. 2007-174667 only discloses a technique for adding noise, such as grain noise, universally throughout videos. Accordingly, in order to cause the appearance of noise to match throughout the videos, there are cases where it is necessary to add noise in such an amount that the noise originally contained in the videos does not stand out, and it is also necessary for the editor him/herself to adjust the amount of noise.
Meanwhile, although Japanese Patent Laid-Open No. 2008-187260 does implement noise addition in accordance with the videos, the noise addition is based on the location of the primary subject, and thus it is ultimately necessary for the editor him/herself to adjust the amount of noise in order to coordinate the appearance of noise throughout the plurality of videos.

Image processing apparatus and processing method thereof


A musician can simulate participation in a concert by playing a musical instrument and wearing a head-mounted 3D display that includes stereo speakers. Audio and video portions of a musical concert are pre-recorded, along with a separate sound track corresponding to the musical instrument played by the musician. Playback of the instrument sound track is controlled by signals generated in the musical instrument and transmitted to a system interface box connected to the audio-video play back device, an audio mixer, and the head-mounted display. An external bypass switch allows the musician to suppress the instrument sound track so that the sounds created by actual playing of the musical instrument are heard along with the pre-recorded audio and video portions.

The present invention relates generally to audio and video simulations of a pre-recorded musical performance.
More particularly, this invention pertains to the generation and control of a simulated musical concert experience and participation by a musician in a pre-recorded musical performance using a musical instrument as the control device.
Virtual reality systems are generally recognized to be a combination of computer hardware, software, and peripherals which recreate a virtual world or virtual environment using a video display, often in combination with an audio sound system. Conventional virtual reality systems are quite complex, combining the hardware, software, and peripheral devices in a specific manner to immerse or subject the user of the system to visual and sound stimuli which simulate a real world experience. Typically, a virtual reality system further includes one or more input devices and interface software so that the user of the system can interact with the virtual environment that is being recreated, such as to simulate the user movement in the environment or manipulation of virtual objects reproduced in the virtual environment.
Virtual reality systems in the prior art have been used for entertainment purposes, to conduct scientific experiments, or to allow a user to indirectly carry out tasks which would otherwise be too difficult or dangerous when conducted in a real environment.
To a lesser extent, virtual reality systems have been used to create and control a virtual world that responds to music signals or to pre-recorded control tracks corresponding to music signals. Such a system is disclosed in U.S. Pat. No. 5,513,129, which describes a virtual reality in which a music source is connected to an electronic interface and to a virtual reality processor. The system is further controlled by one or more input devices, such as a head tracker and manipulator glove. The pre-recorded music, along with an optional pre-recorded control track, controls and manipulates objects within the virtual environment such that the music effectively drives the display of an animated graphical scene. However, the system described in U.S. Pat. No. 5,513,129 does not provide a simple and effective method for allowing a musician to participate in and control a "virtual environment" through the actual operation of a musical instrument, such as an electric guitar. Such a system would provide a source of entertainment to professional and amateur musicians alike. It also would assist musical instrument manufacturers in promoting the sale of their instruments by allowing a prospective purchaser to recreate a musical concert, to simulate the musician's participation in the concert, and to control the sound portion of the concert through operation of the guitar or other instrument. Preferably, such a simulation system would minimize the use of complex and expensive hardware and software so that the system would be easy to set up and affordable even at the retail store level. Such a system is lacking in the prior art.

System and method for generating and controlling a simulated musical concert experience


A method for determining concentration of an analyte in a sample includes generating a spectrum of a selected analyte and interferents, generating a spectrum of an unknown sample, computing first and second derivatives of the sample spectrum, deriving a matrix model that includes the analyte spectrum and the derivatives, and applying the matrix model to the sample spectrum so as to yield a parameter representing concentration of the selected analyte in the unknown sample. Multiple linear least squares regression is utilized to fit the model and calculate the parameter.

It is often desired to isolate and determine the concentration of a particular element or species contained in an unknown sample. This is conventionally done for molecular species by a spectrometer operating, for example, in the infrared region of the spectrum. More recently, it might be accomplished for elements by an atomic emission spectrometer such as an inductively coupled plasma (ICP) spectrometer. One of the major problems in handling spectral data of this type arises from overlapped responses from various chemical species in the unknown mixture. Such responses may, for example, completely hide the response from the element or species which it is desired to measure.
One prior art technique for solving this problem is to separately measure and record the spectral responses of components known or suspected to be in the unknown sample. Coefficients are then selected which are employed to multiply each of the preselected spectral patterns such that, when summed together, they will minimize the root mean square difference between such sum and the spectral data from the sample. For example, in an abstract "A Multiple Regression Procedure for Elemental Analysis at Low Concentrations" by Z. Mencik, P.L. Berneburg and M.A. Short, Advances in X-ray Analysis 18, 396-405 (1974), multiple regression is disclosed for relating x-ray intensities to calibration standards, whereby regression coefficients are used to solve for the contents of elements in unknown samples.
Another prior art method is by use of the Kalman filter, as disclosed in an article "Some Spectral Interference Studies Using Kalman filtering in Inductively Coupled Plasma-Atomic Emission Spectroscopy" by E.H. van Veen, F.J. Oukes and M.T.C. de Loos-Vollebregt, Spectrochimica Acta 45B, 1109-1120 (1990). This is an iterative process. A set of coefficients is estimated. These coefficients are employed to multiply each data point in the spectrum. The error between the results and each data point is computed. A derivative is then estimated that indicates the direction in which to shift the estimates of the coefficients. Accordingly, there is a successive refinement of the error which, after many iterations, converges.
One of the problems with both of the aforementioned methods is that they are computational and time intensive. This becomes a particular problem in the case of ICP atomic emission spectra wherein there might be, for example, data points at 64 discrete frequencies and several unknowns. This would result in the need to solve simultaneously 64 different equations having, for example, 3 unknowns.
Another problem with the prior art techniques arises from spectral wavelength shifts in the unknown sample. Such shifts cause the peaks of components in the unknown sample to appear to be at different wavelengths than the previously recorded peaks of the pure components. Such apparent shifts may occur, for example, between instruments and even, with time, in the same instrument. In dealing with this problem, the prior art approach has been to use interpolation. The spectral information is collected at discrete points. If a wavelength shift is required, it is necessary to know what the data is between such points. However, since the amount of interpolation is not known, it is required to successively check the error and iterate. This also is a mathematically and time intensive procedure.
U.S. Pat. No. 5,023,804 (Hoult) discloses comparing spectral data with a standard spectrum by computing a normalized dot product of a sample spectrum and the standard spectrum. The two spectra are weighted by filtering to remove short and long periodicities, the filtering being effected with a triangular wave using a simplified algorithm.
U.S. Pat. No. 4,997,280 (Norris) discloses a spectrophotometric instrument in which rapid scanning causes distortion of the spectrum. A first derivative is determined from the spectrum and multiplied by a constant selected to correct for the distortion. The resulting product values are added to the distorted spectrum to provide a set of corrected values for intensity. The selected constant is determined by comparing data acquired from operation of the instrument at a normally rapid speed and slowly to eliminate the distortion.

Method and apparatus for comparing spectra


In an embodiment, a processor includes at least one core to execute instructions and a system management monitor to receive a platform query request from an external system, obtain status information regarding a configuration of one or more privileged resources of the processor, and report the status information to the external system. Other embodiments are described and claimed.

In typical computer platforms, there is no external visibility into the present state of low-level platform configuration. Additionally, a more secure and privileged environment based in system firmware is typically not used to report the platform state to an external monitor. It is further possible that malware or other attack can be triggered that causes a platform configuration change that opens up the platform to an attack. Current software antivirus programs are unable to detect such changes, and are thus ineffective at thwarting or even reporting such possible attacks.

Reporting platform information using a secure agent


The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

1. Field of the Invention
The present invention relates to a disk array controller comprising a plurality of central processing units (CPUs) for controlling the interface between a host computer or disk device(s), and a plurality of memories for storing the control data.
2. Description of Related Art
A structure of a disk array controller of the conventional art utilizing a shared memory multiprocessor system is shown in FIG. 21. In the controller shown in FIG. 21, a plurality of CPU-PK (packages) 2101, a shared memory package (SM-PK) #A 2103 equipped with the shared memory for storing control data, and a shared memory package (SM-PK) #B 2104 are connected by way of the shared memory path 2102. Each CPU-PK is connected to either the host computer or the disk device. Each CPU-PK contains a plurality of CPUs and each CPU performs transfer of data from the host computer or disk device, or controls the transfer of data to the host computer or disk device by utilizing the control data stored in the shared memory.
The memory controller of the conventional art has a plurality of paths connecting between a plurality of central processing units (CPU) and memories in order to shorten the response time for memory access and increase the number of processable transactions. In order to increase the number of processable transactions, the processable transactions must be optimally distributed along the plurality of paths. A technology for distributing the transactions is disclosed in Japanese Published Unexamined Patent Application No. 9-146863 for distributing transactions by checking flags indicating the use or non-use of a path.
Another method is known in the memory controller of the conventional art for improving reliability by duplication of paths and duplication of the memory. Such a memory controller device is for instance, disclosed in Japanese Published Unexamined Patent Application No. 9-325916 and utilizes two paths for memory access to increase the number of processable transactions and at the same time increase reliability of the data by dual writing of important data onto two memories. In this kind of method however, in order to write the same data on a plurality of non-synchronous memories, problems such as data mismatches or deadlocks may occur when simultaneously attempting a plurality of dual writing. In this kind of dual write, simplifying of the access paths and elimination of the data mismatch or deadlock problems was attempted by establishing fixed buses for use by each memory address.
However, in this method, the response time during serial processing on the bus becomes a problem when multiple accesses occur, and performance bottlenecks relating to the number of processable transactions are also a disadvantage. Also, in spite of the duplication of buses, all the connected central processing units (CPU) are affected when a problem occurs on a bus.
In an attempt to improve both performance and reliability, the star connection which connects the CPU and memory in a ratio of one to one was contrived. In the method disclosed in Japanese Published Unexamined Patent Application No. 58-16362 each duplicated memory from each CPU is connected by one bus line each. In this method, an increased number of paths can be simultaneously accessed compared to the above methods, and the number of processable transactions can be further increased. Each CPU is connected to a path so that compared to the above methods, the range of CPU likely to be affected by a problem on one path is limited and the reliability is also high. Still further in this technology, interfaces are provided between the shared memories in order to avoid problems during dual write processing such as deadlocks or data mismatches.
The shared memory in the disk array controller does not require data transfer in as large amounts as the cache memory, however increasing the number of transactions and shortening the response time for each data transfer is necessary. A one-to-one connection between each CPU and the shared memory is therefore suitable as disclosed in the technology of Japanese Published Unexamined Patent Application No. 58-16362.
The transfer of large quantities of data at high speed however, is necessary between each CPU and cache memory so that increasing the number of access paths is required. Establishing connections in a ratio of one to one between each CPU and memory is therefore a suitable method as disclosed in Japanese Published Unexamined Patent Application No. 58-16362.
However, as previously mentioned, there is a physical limit on how many connectors can be mounted on the package comprising the cache memory or how many pins can be mounted on the LSI comprising each memory. This physical limit on the amount of hardware also limits an increase in the number of access paths that can be installed between each CPU and shared memory.
As mentioned above, the star connection method is an excellent bus connection method for increasing the number of processable transactions and improving reliability. The technology disclosed in Japanese Published Unexamined Patent Application No. 58-16362 however has the disadvantage that since an interface connects with the shared memory for dual write, the entire shared memory becomes unusable in the event a problem occurs on this interface. Also, since both of the shared memories lock up during dual write, other access is refused, creating the problem that the number of processable transactions decreases. Further, even if simply increasing the number of paths is attempted, serial processing of dual write must be performed just as with the previously related method, so that a significant increase in the number of transactions cannot be achieved. One path connects between each CPU and shared memory so that accessing data might become impossible if a problem occurs on that path.
Whereupon, it is therefore an object of this invention to provide a disk array controller having a shorter memory access response time between a plurality of CPUs and duplicated memories, and further capable of an increased number of processable transactions.
Another object of this invention is to provide a selection control means to select a path that will not cause data mismatches or deadlocks during dual write.
In order to resolve the above mentioned problems, this invention is installed with a path lock table to indicate the usage status of each path on the shared memory path interface for connecting and controlling the CPU and each memory path, and is further installed with a memory lock table indicating memory lock information for the shared memory control circuit for connecting and controlling the shared memory and each memory path. In processing (single read, single write, atomic modify) for other than dual write, the number of waiting transactions (transactions awaiting processing) on each path is shown, and a path with a short path queue length selected. In processing for dual write and dual write atomic modify, the path lock table is referred to when selecting the path, and if the number of dual write transactions already being processed is less than a fixed number, then dual write processing starts, and if greater than a fixed number, then dual write processing sets to standby. Further, when selecting a path for dual write, paths are selected that are different from those paths where dual write processing is already being performed.

Duplicated shared memory controller for disk array

Hitachi Video and Information System, Inc.


Mesenchymal precursors cells have been isolated from perivascular niches from a range of tissues utilizing a perivascular marker. A new mesenchymal precursor cell phenotype is described characterized by the presence of the perivascular marker 3G5, and preferably also alpha smooth muscle actin together with early developmental markers such as STRO-1 and CD146/MUC18. The perivascular mesenchymal precursor cell is shown to induce neovascularization and improvement in cardiac function. Suitable administration of preparations of the mesenchymal precursor cells are useful for treatment of cardiovascular diseases, cerebrovascular diseases and peripheral vascular diseases.

Vascular conditions constitute a major health problem, particularly in western countries. Vascular conditions include heart conditions, peripheral vascular disease and cerebrospinal vascular conditions.
A major proportion of these conditions result from a lack of supply of blood to the respective tissues which thus are either chronically or acutely deprived of necessary levels of oxygen and nutrients. Typically these conditions result in ischemias where there has been blockage of the blood vessel by build up of, for example, plaque or physical blood vessel damage such that these are either blocked or constricted.
Heart conditions are perceived as the most prominent vascular disease. About 11 million adults in the United States of America (1995) had coronary heart disease, that however is out of a total of about 60 million adults with cardiovascular disease. Other vascular conditions thus affect a greater number of adults.
A relatively common cerebrovascular condition can manifest as a stroke, where an occlusion can lead to an acute attack. A gradual diminution of supply may also lead to decreased capacity of the brain to function and it has been postulated that such conditions may be associated with the onset of certain dementias.
Peripheral vascular disease are associated with a number of conditions, for example, as a complication of diabetes where a typical inadequacy of the microcirculation depletes supply to the extremities particularly the feet and legs of oxygen and nutrients.
Another example of reduced localized supply can occur with the treatment of various wounds including severe burns or chronic wounds such as bed sores. Chronic wounds are difficult to heal, partly due to an insufficient vascular bed supply of nutrient and healing compounds.
Scar formation may also be exacerbated because the healing process often involves a highly fibrotic tissue forming within minimal blood vessel formation. Scar formation is also a difficulty associated with achieving an adequate vascular supply in circumstances where a prosthesis or other implant is surgically position in a human tissue. An inadequate blood supply to the interface between the implant and the surrounding tissue can lead to medical complications and necrosis. This is of far more noticeable relevance where the implant is intended as a long term slow release depot of for example a pharmaceutical.
Treatment of myocardial ischemias are probably the most advanced of current treatments of vascular conditions. Present treatments include pharmacological therapies, coronary artery bypass surgery and percutaneous revascularization using techniques such as balloon angioplasty. Standard pharmacological therapy to aims either increase blood supply to the heart muscle or decreasing the demand of the heart muscle for oxygen and nutrients. Increased blood supply to the myocardium by relaxation of smooth muscle is achieved by administering agents such as calcium channel blockers or nitroglycerin. Decreased demand of the heart muscle for oxygen and nutrients is accomplished either by agents that decrease the hemodynamic load on the heart, such as arterial vasodilators, or those that decrease the contractile response of the heart to a given hemodynamic load, such as β-adrenergic receptor antagonists. Surgical treatment of ischemic heart disease is based on the bypass of diseased arterial segments with strategically placed bypass grafts. Percutaneous neovascularization is based on the use of catheters to reduce the narrowing in diseased coronary arteries. All of these strategies are used to decrease the number of, or to eradicate, ischemic episodes, but all have various limitations, and particularly the pharmaceutical approach can have severe side effects.
Preliminary reports describe new vessel development in the heart through the direct injection of angiogenic proteins or peptides. The several members of the fibroblast growth factor (FGF) family (namely acidic fibroblast growth factor, aFGF; basic fibroblast growth factor, bFGF; fibroblast growth factor-5, FGF-5 and others) have been implicated in the regulation of angiogenesis during growth and development. Gene therapy has been suggested by Hammond et al in U.S. Pat. No. 5,792,453 as a delivery mechanism for these angiogenic compounds.
Another suggested approach to promoting new blood vessel formation for treatment of vascular conditions is the administration of stem cells which can differentiate and give rise to cells required for such blood vessels to form. One problem associated with this approach is that it is not entirely clear which progenitor cells are responsible for formation of blood vessel or whether indeed more than one cell type is required or whether other angiogenesis promoters are required.
One reported approach described in U.S. Pat. No. 5,980,887 (to Isner et al) has resulted from the isolation of an endothelial progenitor cell and the discovery that such cells play a role in blood vessel formation.
Numerous attempts at isolating and enriching mesenchymal precursor cells have been made because of the potential that these cells have for medicinal use. Pittinger et al., (1999) show the expansion of clonogenic cells from bone marrow and describes a preparation of enlarged mesenchymal stem cells. A more recent example of such a method providing for a relatively high yield from bone marrow is disclosed in publication WO01/04268 to Simmons et al. Neither of these reported mesenchymal cells were indicated as being capable of regeneration vascular lineages of cells capable of leading to blood vessel formation.
To date however there have been no examples of isolated mesenchymal precursor cells capable of forming vascular tissues in vivo.

Perivascular mesenchymal precursor cell induced blood vessel formation


A communication system enabling a switching procedure for a multiple-input multiple-output orthogonal frequency division multiplexing (MIMO OFDM) based flexible rate intra-data center network DCN, includes a MIMO OFDM DCN with optical burst switching OBS capability, an optical burst switching OBS procedure for influencing the MIMO OFDM DCN, and a centralized control configuration coupled to the MIMO OFDM DCN and enabling a software defined network SDN configuration in the communication system.

The present invention relates generally to optical networks, and more particularly, to a switching procedure for multiple-input multiple-output-orthogonal-frequency-division-multiplexing (MIMO-OFDM) based flexible rate Intra-data center network.
The following prior documents referenced in the background discussion, not material to patentability of the claimed invention, nevertheless provide additional information.
General Survey of DCN Architectures:                [Kachris] C. Kachris and I. Tomkos, "A Survey on Optical Interconnects for Data Centers", IEEE Communications Surveys and Tutorials, Vol. 14, Iss. 4, pp. 1021-1036, 2012
Inventor's Prior Works on MIMO OFDM DCN:                [Ji1] P. N. Ji, T. Wang, and Y. Aono, "MIMO-OFDM-based flexible rate intra-data center network", NECLA IR 11101;        [Ji2] P. N. Ji, T. Wang, et al., "Demonstration of High-Speed MIMO OFDM Flexible Bandwidth Data Center Network", Proceedings of ECOC 2012, paper Th.2.B.1, 2012;        [Ji3] P. N. Ji, D. Qian, et al., "Design and Evaluation of a Flexible-Bandwidth OFDM-Based Intra Data Center Interconnect", IEEE Journal of Selected Topics in Quantum Electronics (in press)
Background of OBS:                [Qiao] C. Qiao and M. Yoo, "Optical Burst Switching (OBS)—A New Paradigm for an Optical Internet", Journal of High Speed Networks, Vol. 8, Iss. 1, pp. 69-84, 1999        [Chen] Y. Chen, C. Qiao & X. Yu, "Optical Burst Switching (OBS): A New Area in Optical Networking Research", IEEE Journal of Networking, Vol. 8, Iss. 3, pp. 16-23, 2004
Introduction of Intune's OPST Technology:                [Dunne] J. Dunne, "Design Principles for Optical Packet Switch and Transport (OPST) Networks", Intune white paper, 2010
Introduction of Software-Defined Optical Network:                [Ji4] P. N. Ji, "Software Defined Optical Network", Proceedings of 11th International Conference on Optical Communications and Networks (ICOCN 2012), paper THU-07, 2012
As the global Internet traffic growing exponentially, the data centers, which host many Internet application servers, are also facing rapid increase in bandwidth demands. In recent years, large-scale data centers continued to be built out. Due to emerging applications such as cloud computing and "Big data" processing, next generation data centers need to achieve low latency, high throughput, high flexibility, high re-source efficiency, low power consumption, and low cost. Furthermore, as more and more processing cores are integrated into a single chip, the communication requirements between racks in the data centers will keep increasing significantly. By integrating hundreds of cores into the same chip (e.g. Single-chip Cloud Computer) we can achieve higher processing power in the data center racks. However these cores require a fast and low-latency interconnection scheme to communicate with the storage system and the other servers inside or outside of the rack. This communication network between racks is referred to as the intra-data center network, as oppose to the inter-data center network for long distance communication between data centers at different geographical locations. In the following, we focus on the intra-data center network and will thus simply refer it as the data center network (DCN).
Optical technology has been adopted in DCN due to its high bandwidth capacity. However, it is mainly used for point-to-point link, while the DCN interconnect is still based on electrical switching fabric, which has high power consumption and limited bandwidth capacity. Currently, the power consumption of the data center networks account for 23% of the total IT power consumption. However, due to the anticipated high communication requirements in the future, it is estimated that the DCN will account for much higher percentages of the overall power consumption. Therefore it is expected that data center network may evolve to all-optical networks, similarly to the telecommunication networks that have been evolved from opaque to transparent networks using all-optical switches.
In recent years, several hybrid optical/electrical (O/E) or all-optical interconnect schemes for DCN have been proposed [Kachris]. Many of them rely on large scale fiber cross-connect (FXC) or multiple wavelength-selective switches (WSS), which are costly and have slow switching speed (at millisecond level). Having a large scale FXC also present an undesirable single source-of-failure. A recent work used silicon electro-optic mirroring WSS and semiconductor optical amplifier-based switch to achieve nanosecond scale switching, making all-optical packet level routing possible. However the key components are not commercially available and have low scalability. Other architectures use tunable wavelength converters (TWC). They are also costly and do not allow bandwidth resource sharing among the connections. Some of them also require electrical or optical buffers.
In most of these all-optical or hybrid O/E DCN architecture designs, the switching is performed at the circuit level because the optical switch hardware is not fast enough to process IP packets (which is the main type of traffic in data centers). This is called optical circuit switching (OCS). This limitation makes the optical DCN solution less efficient and thus less attractive. Some hybrid O-E architectures use the optical switching portion only for large volume, slow varying traffics, and still rely on the electrical portion for regular IP traffics. Having both types of switching hardware in a DCN requires high equipment cost and cannot solve the high power consumption problem in electrical switching DCN.
Recently we proposed and experimentally demonstrated a novel all-optical DCN architecture that combines a passive cyclic arrayed waveguide grating (CAWG) core router with orthogonal frequency division multiplexing (OFDM) modulation and parallel signal detection (PSD) technologies [Ji1, Ji2, Ji3]. FIG. 1 is the schematic of the DCN architecture. The architecture achieves fast switching (nanosecond speed capable) with low and uniform latency (single hop), low power consumption, and multiple-input multiple-output (MIMO) switching capability, while allowing fine granularity bandwidth sharing (at Mb/s level) and having low cost (does not require any FXC, WSS, or TWC). We also proposed and analyzed various subcarrier allocation algorithms to efficiently use the bandwidth resource and optimize the throughput in the DCN.
However, the MIMO-OFDM DCN research so far is on physical layer hardware implementation, as well as subcarrier allocation algorithm. There is no control system to utilize them in practical DCN application. Furthermore, despite the high switching speed capability, the work so far is based on circuit switching only. In other words, there is no solution to enable packet switching in this DCN architecture.
Optical packet switching (OPS) has been studied for many years to enable packet switching function in the optical domain, because it will provide better flexibility, efficient resource utilization, potential functionality and finer switching granularity. Some OPS prototype systems have been built and demonstrated. However, OPS is not efficient because in OPS the data payload must wait in the optical buffers before it can be forwarded to the next node since the packet header needs to be processed either all-optically or electronically after an optical-to-electrical (O-E) conversion at each intermediate node. And there are many major challenges for it to be solved before OPS can be practical enough for actual application. For example, there is no optical equivalent of RAM and logic devices for optical signal processing (such as optical packet header processing). And even if the header is processed electronically, there is no flexible optical buffer with practical buffering capability currently available (a less flexible alternative, namely the fiber delay line, is currently used in the OPS research testbeds), and the optical switching hardware at packet speed level is still very expensive and large.
A good compromise between OCS and OPS is optical burst switching (OBS) [Qiao, Chen]. In an OBS network, various types of client data (including asynchronous traffics such as Ethernet, and synchronous traffics such as SONET, SDH, OTN, Fiber Channel, FICON . . . ) are aggregated at the ingress (an edge node) and transmitted as data bursts (FIG. 2(a)) which later will be disassembled at the egress node (FIG. 2(b)). During burst assembly/disassembly, the client data is buffered at the edge where electronic RAM is cheap and abundant. Even though the client data go through burst assembly/disassembly only at the edge of an OBS network, nevertheless, statistical multiplexing at the burst level can still be achieved in the core of the OBS network.
Another feature of OBS is that data and control signals are transmitted separately on different channels or wavelengths, as illustrated in FIG. 3. For each data burst, a control packet containing the usual "header" information (such as the burst length information) is transmitted on a dedicated control channel. Since a control packet is significantly smaller than a burst, one control channel is sufficient to carry control packets associated with multiple (e.g., hundreds of) data channels. A control packet goes through OEO conversion at each intermediate OBS node and is processed electronically to configure the underlying switching fabric. There is an offset time between a control packet and the corresponding data burst to compensate for the processing/configuration delay. For multi-hop network, the offset time at each hop is different, as illustrated in FIG. 3. If the offset time is large enough, the data burst will be switched all-optically and in a "cut-through" manner, i.e., without being delayed at any intermediate node (core). In this way, no optical RAM or fiber delay lines is necessary at any intermediate node. This is an advantage over OPS. Furthermore, it allows a lower control overhead per bit than that in OPS. In OBS, costly OEO (optical to electrical to optical) conversions are only required on a few control channels instead of a large number of data channels. Compared to OCS, the burst-level granularity leads to a statistical multiplexing gain and thus more efficient use of the bandwidth, which is absent in OCS.
Therefore OBS presents a good solution for DCN because it combines the advantages of optical switching (low power consumption, high capacity) and the advantage of sub-wavelength switching (statistical multiplexing gain, better bandwidth utilization) in a practical way.
So far, there is only one carrier grade OBS architecture and product in the world. This is developed by Intune Networks. The technology is called the Optical Packet Switch and Transport (OPST) and is based on their fast tunable optical transmitters [Dunne]. Despite what the name (which includes "optical packet switch") suggests, the OPST is actually a type of OBS technology. In fact, it was claimed to be "the world's first carrier grade OBS architecture". In such architecture (FIG. 4), every node is attached to the OPST fabric (ring) through a fast tunable laser (with nanoseconds tuning speed) and a burst mode receiver (BMR) under that port's local control. Each receiver node is assigned a unique wavelength in which every other node can transmit to this node by tuning the transmitter in real-time. At each BMR, the ingress packets are queued by class of service per wavelength. Each port can send and receive frames to and from all other ports, providing a fully distributed switching capability with no intervening OEO between source and destination.
Intune's OPST architecture is most suitable for shorter distance networks (up to a few hundreds of kilometers). Although it is advertised mainly for transport networks, it could be also used to replace the core network of the data centers [Kachris].
There are several limitations to this OPST architecture. For example, due to its ring topology, it is difficult to inset new nodes without interrupting the existing traffics, because even though each node has its own dedicated wavelength, all wavelengths are transmitted within the same fiber using wavelength division multiplexing (WDM). Therefore in-service upgrade cannot be achieved. Secondly, at the receiver of each node, a passive optical coupler is used to combine all the signals from all other nodes. If the coupler has large port count to accommodate all existing and potential future nodes, the optical loss will be very large. On the other hand, if the port number of the coupler is limited to a certain quantity, the number of nodes that can simultaneously transmit to the particular destination node will be limited too. Therefore this architecture is not very scalable. So far the product can support only up to 16 nodes in a ring, which is not sufficient for regular data centers. Thirdly, the ring topology also leads to the fact that different source-destination pairs go through different numbers of hops (one hop is between two adjacent node), such as the yellow traffic vs. the red traffic in FIG. 4, making the propagation delay uneven, and thus the latency is also not uniform.
Accordingly, there is a need for a switching procedure for MIMO-OFDM based flexible rate intra-data center network that overcomes the shortcomings of prior efforts.

Switching for a MIMO-OFDM based flexible rate intra-data center network


A container comprising a first material and a second material, the first material being a flexible material and the second material being a rigid or semi-rigid material and at least partially defining an interior compartment for keeping a fluid inside the container characterized in that the flexible material and/or the semi-rigid or rigid material have thermoplastic properties and wherein the flexible material and the semi-rigid or rigid material are joined together by a seal or joint which comprises a heat seal and an adhesive seal.

Single-use or disposable systems are rapidly increasing in biopharmaceutical industry due to the flexibility and cost-effectiveness of such systems. Disposable components in the systems are presterilized and qualified to regulatory requirements. Disposable systems are easy to adapt to different production purposes and it is easy and inexpensive to change a product line while good process reliability is at least maintained or even improved.
There are several kinds of biopharmaceutical systems, such as mixing systems, in which disposable containers or bags may be used. These containers or bags are made of sheets of flexible material, such as plastic, plastic laminates or corresponding materials.
One type of mixing systems in which such containers can be used is a bioreactor system in which cells or microorganisms can grow. Mixing systems include also systems used to prepare for example buffer and media.
Mixing systems may comprise a support or vessel which supports or houses a disposable bag or container of the above-mentioned type. The support may be a support plate or tray for a bioreactor bag of a kind used in GE Healthcare WAVE BioreactorTM systems. The vessel may be a tank-type support which has a substantially cylindrical form, for example substantially circular cylindrical and is made of rigid material such as stainless steel to provide sufficient support for a flexible bag or container. The flexible container or bag is placed on the tray or in the inside of the vessel in an accurate manner so that for example different pipelines or tubes, mixers and sensors can be connected to the bag properly and accurately. US2011/0310696 and EP1842800 disclose mixing systems of this kind
As mentioned above, disposable containers are often mainly made of sheets of flexible materials. To stabilize or reinforce the containers or to enable the connection of different pipelines or sensors to the containers they may comprise parts of rigid or semi-rigid materials. These rigid or semi-rigid parts provide a platform for safe and secure attachment of for example sensors, pipelines for fluids (both gas and liquid) and mixers. Further, the rigid or semi-rigid parts can reinforce and stabilize the containers and therefore facilitate placing of the containers into mixing vessels in accurate manner.
However, seals between rigid/semi-rigid and flexible materials may involve a safety risk, since the seals may be weak and thereby cause leakage of the liquids in the container and/or contamination of the liquids inside the container by the surrounding environment. Therefore, it is essential that the risk for leakage and/or contamination can be minimized and the seal between these different materials can be made as safe and secure as possible.
Containers may vary in size from about 1 liter to about 2000 liters and especially, if containers are large and leakage occurs from the material seals, there may be catastrophic consequences both in respect of loss of material and consequences to the surrounding environment, since the liquids leaked may cause damage to the surrounding equipment, such as control computers. Of course, the leaked liquid has to be cleaned which is both expensive and labour consuming.
Another problem which may occur in the seals of traditional type is micro leakage, i.e. leakage in very small amounts which is due to the unevenness of the sealing. Micro-leakage may cause contamination of sensitive cultivations and also on the other hand the environment surrounding the cultivation.

Container with a seal and a method of making the seal


An optical communication equipment comprises shared optical sources 88a–88d to be shared by communication nodes 100a–100d, the wavelengths of optical signals 76a–76d are converted into desired wavelengths λa–λd according to the addressed information of the corresponding optical label signals 77a–77d by using the shared optical sources 88a–88d, and routed to the addressed communication nodes without being converted into electrical signals by using the wavelength routing function of the cyclic-wavelength arrayed-waveguide grating (AWG) 120. The load of each communication node can be reduced by incorporating the multi-wavelength optical sources, which can be shared among individual communication nodes, into the router 80. Further, each communication node is provided with an optical gate or the like for returning the optical signal to the communication node from which the optical signal has been transmitted through the router 80 in order to adjust the transmission time lag between the optical signal and the corresponding optical label signal by the controllers 110a–110d.

1. Field of Invention
The present invention relates to an optical packet routing system for routing an optical signal by using the optical label signal carrying the control information necessary for the routing of the optical signal, more particularly, to a multiple-wavelength optical source unit to be used for a network system whose a plurality of communication nodes are connected by the wavelength routing system and an optical communication unit and an optical communication method to be used for an optical communication system whose internode communication among the communication nodes is made through a routing unit.
2. Description of the Art
With the explosive spread of the internets, and portable personal telephones and the like, the research and development activities for the establishment of large-capacity network are under way both at home and abroad. With the communication nodes constituting each of the existing networks, an optical signal transmitted through an optical fiber transmission line is converted into an electric signal; an address information and the like carried by the signal is read out; the signal is electrically switched to a desired output port according to the information; the signal is converted into an optical signal at the output port; and the optical signal is then transmitted through the optical fiber transmission line. However, with the exponential-growth in the communication traffic, in the near future, the routing processing capacity by the electrical routing processes is considered to reach its limit. To overcome this problem, it is important for the communication nodes to establish a routing method for enabling the routing of the signal within the optical layer, that is, a routing method for enabling the routing without converting the optical signal into the electric signal.
As a technique for realizing the above goal, the wavelength routing technique is coming to the fore. In the case of the wavelength routing technique as schematically illustrated in FIG. 1, any optical signal fed into a given input port can be routed selectively to different output ports according to its wavelength without being converted into an electric signal, by using an optical device (e.g., arrayed-waveguide grating) having a wavelength selectivity.
FIG. 2 schematically illustrates the general composition of the network system interconnecting a plurality of communication nodes by utilizing the wavelength routing function of the cyclic-wavelength arrayed-waveguide grating. In the case of this network system, with a cyclic-wavelength arrayed-waveguide grating 60 having a wavelength routing processing function, the optical signal transmitted from a communication node is routed in the form of the light according to its wavelength without undergoing any electrical processing for routing, so that high-speed routing is possible.
To illustrate the composition of FIG. 2, the network system comprises N number of communication nodes 30 (communication nodes #1–N) and a cyclic-wavelength arrayed-waveguide grating 60 having a wavelength routing processing function. Each communication node 30 comprises transmitter equipment 40 and receiver equipment 50. The transmitter equipment 40 comprises N number of optical sources 41 for transmitting optical signals having wavelengths λ1–λn.
The optical signals (wavelength: λ1–λn) transmitted from the transmitter equipment 40 of each communication node 30 are introduced into the input ports of the cyclic-wavelength arrayed-waveguide grating 60 having the wavelength routing processing function. The cyclic-wavelength arrayed-waveguide grating 60 routes the optical signals incoming from various communication nodes 30 to different output ports according to the wavelengths, λ1–λn, of the optical signals. Since this routing processing of the optical signal is carried out according to the wavelength of the optical signal while maintaining the form of the light without being subjected to any electrical processing, the high-speed routing is possible.
The optical signals (wavelength: λ1–λn) came out from the output ports of the cyclic-wavelength arrayed-waveguide grating 60. is introduced into the receiver equipment 50 in each communication node 30.
The detail of the wavelength routing processing by the cyclic-wavelength arrayed-waveguide grating 60 will be described referring to FIG. 3. Optical signals (wavelength: λ1–λ4), varying in wavelength transmitted from various communication nodes (#1–#4) are fed to the input ports 61a–61d of the cyclic-wavelength arrayed-waveguide grating 60. In this case, the optical signal transmitted from the communication node #1 to the input node 61a is outputted from the output port 62a when its wavelength is λ1, from the output port 62b when its wavelength is λ2, from the output port 62c when the wavelength is λ3 and from 62d when the wavelength is λ4.
The optical signal to be transmitted from the communication node #2 to the input port 61b is outputted from the output port 62d when its wavelength is λ1, from the output port 62a when its wavelength is λ2, from the output port 62b when its wavelength is λ3, and from the output port 62c when its wavelength is λ4.
The optical signal to be transmitted from the communication node #3 is outputted from the output port 62c when its wavelength is λ1, from the output port 62d when its wavelength is λ2, and from the output port 62a when its wavelength is λ3, and from the output port 62b when its wavelength is λ4.
The optical signal to be transmitted from the communication node #4 to the input port 61d is outputted from the output port 62b when its wavelength is λ1, from the output port 62c when its wavelength is λ2, from the output port 62d when its wavelength is λ3, and from the output port 62a when its wavelength is λ4.
Thus, by the routing to be carried out as described above, the optical signals having the same wavelengths respectively transmitted from the communication nodes #1–#4 will never be outputted from the same output port. In other words, the wavelength routing by using the cyclic-wavelength arrayed-waveguide grating as is shown in FIG. 3 is characterized by that the optical signals having the same wavelengths fed to different input ports of the grating are outputted from different output ports of the grating respectively, so that the conflict among the data having the same wavelengths with respect to the output port can be prevented.
However, in the case of conventional network system as is shown in FIG. 2, especially in the case of the network comprising N number of communication nodes, it is necessary to provide N number of optical sources with wavelengths strictly adapted to the wavelength characteristic of the cyclic-wavelength arrayed-waveguide grating with respect to each of the communication nodes and thus requiring N×N number of optical sources, which is a problem to be resolved. Especially, providing N number of optical sources for each communication node not only results in the increase in the burdens such as the increase in the size and cost of the communication node but also results in the increase in total cost of the network system.
Next, a prior art relating to the second embodiment of the present invention will be described.
Conventionally, as an optical communication system for carrying out the optical communication among a plurality of communication nodes through a router, a system shown in FIG. 4 has been available.
The communication nodes 100a–100d are respectively provided with one of the corresponding optical signal transmitters 71a–71d for respectively transmitting one of the corresponding optical signals 76a–76d and also respectively provided with one of the corresponding optical label signal transmitters 72a–72d for respectively transmitting one of the corresponding optical label signals 77a–77d carrying the control information necessary for the routing of the optical signal.
The routing device 80 is connected respectively to each communication nodes 100a–100d through the corresponding optical transmission lines 81a–81d and comprises wavelength demultiplexers 74 for separating the optical signals and the optical label signals, optical receivers 78e for receiving the optical label signals separated by the wavelength multiplexers 74, optical splitters 79 for branching the optical signals separated by the wavelength demultiplexers 74 to a plurality of optical paths and a plurality of optical gates 75a–75d for selecting the optical path by the routing processing for passing or intercepting the optical signals according to the control information in the optical label signals 77a–77d respectively connected to a plurality of the corresponding optical paths. The control circuit section for controlling the optical gates 75a–75d are not shown in the figure.
When the optical signals 76a–76d and the optical label signals 77a–77d respectively including the control routing information of the optical signals are fed respectively to the router 80 through the optical transmission lines 81a–81d after being transmitted respectively from a plurality of communication nodes 100a–100d (the four communication nodes #1–#4 in the case shown in the figure), the optical signals 76a–76d and the optical label signals 77a–77d are respectively separated by the wavelength demultiplexers 74 provided in the router 80 respectively corresponding to the communication nodes.
Further, the optical signals 76a–76d are respectively branched by the optical splitter 79 in the stage following the wavelength demultiplexer 74 and respectively introduced into the corresponding optical gates (three optical gates among the optical gates 75a–75d in the case shown in the figure) through a plurality of optical paths of substantially the same length (three optical paths in the case shown in the figure). On the other hand, the optical label signals 77a–77d are respectively guided to the corresponding optical receivers 78e. Next, when the optical signal passes one or a plurality of optical gates among a plurality of optical gates 75a–75d, which is or are designed to be driven according to the information carried by the optical label signal received by the optical receiver 78e, the optical path for the optical signal is selected from among the optical paths 82a–82d.
The time required for the optical signal 76 (the representative number of 76a–76d) to arrive at the optical gate 75 (the representative number of 75a–75d) from the input port of the wavelength demultiplexer 74 of the router 80 is given as t1; the time required for the optical label signal 77 (the representative number of 77a–77d) corresponding to the optical signal 76 to arrive at the optical receiver 78e from the input port of the wavelength demultiplexer 74 is given as t2; the time required for the optical receiver 78e to drive the optical gate 75 (to permit the optical signal to pass) after completing the reception of the optical label signal 77. Under these conditions, in the optical gate 75, in order for the optical signal 76 to be processed for proper gating, it is necessary for each of the communication nodes 100 (the representative number of 100a–100d) to output both the optical signal 76 and the optical label signal 77 respectively with a time lag so that the time lag becomes equal to the relative time lag T′ (the time lag between the front of the optical signal 76 and the end of optical label signal 77 arrived at the input port of the wavelength demultiplexer 74, denoted by numeral 90 in FIG. 5) to satisfy the inequality (1) given below.T′>t2+t3−t1  (1)
On the other hand, in order to raise the data communication efficiency among the communication nodes 100, as shown in FIG. 6, it is necessary to adjust the relative time lag T′ in the above inequality (1) so that the time lag Δt (denoted by numeral 91) between the arrival time of the optical signal 76 at the optical gates 75 to drive the optical gates 75 and the time (denoted by numeral 92) at which the optical signal is allowed to pass is reduced as far as possible.
By predetermining the values of t1, t2 and t3 in the above inequality (1), the relative time lag T′ between the optical signal 76 and the optical label signal 77, which is necessary for proper gating of the optical signal 76 by the optical gate 75, can be determined.
However, in general, in the case of the optical communication system by using the optical label signal, for the easy separation of the optical signal and the optical label signal by the router 80, these signals have different wavelengths. Therefore, the relative time lag between the optical signal and the optical label signal varies according to transmission distance due to the effect of the wavelength dispersion of the optical fiber which is a transmission medium of the optical signal. In consequence, the time lag T between the transmission of the optical signal and that of the optical label signal set by the communication node 100 differs from the relative time lag T′ at immediately before the input port of the wavelength demultiplexer 74 of the router 80. Since the distances from various communication nodes 100 to the router 80 vary, it is necessary to adjust the transmission time lag T between the transmission of the optical signal and that of the optical label signal so that the relative time lag T′ for each of the communication nodes 100 satisfies the above inequality (1).
However, since the router and each communication node are, in general, arranged at physically separated locations, when setting the previously mentioned transmission time lag T at each communication node, it is necessary to adjust in real-time conjunction so that the data is transmitted properly to each communication node, but this process is very cumbersome in the case of the conventional system.

Optical packet routing network system based on optical label switching technique

Nippon Telegraph and Telephone Corporation


A transceiver configured to transmit data in a plurality of operating modes including a Wi-Fi mode and two or more different Bluetooth power modes, the transceiver comprising: a first power amplifier configured to amplify Bluetooth signals; a second power amplifier configured to amplify Wi-Fi signals; an antenna coupled to the second power amplifier; and a tunable load circuit, coupled between the first amplifier and the second amplifier, configured to provide a different load impedance for each of the plurality of operating modes, the tunable load circuit consisting of: two impedance paths coupled in parallel between output terminals of the first and second amplifiers; and a number of shunt paths coupled between the tunable load circuit and ground potential.

Modern wireless communications devices typically include multiple wireless radios (e.g., Bluetooth®, Wi-Fi, etc.). To achieve a smaller footprint, multiple wireless radios may share the same antenna. For example, a wireless device may include a Bluetooth radio and a Wi-Fi radio coupled to a single antenna. The Bluetooth radio may include a Bluetooth power amplifier to drive (e.g., amplify) outgoing data signals in accordance with one or more Bluetooth standards. The Wi-Fi radio may include a Wi-Fi power amplifier to drive outgoing data signals in accordance with one or more IEEE 802.11 standards. The Bluetooth and Wi-Fi radios typically operate on the 2.4 GHz frequency band, and may share an antenna to transmit signals to other wireless devices and/or to receive signals from other wireless devices.
Power transmission efficiency may depend upon how closely matched the load impedance of a power amplifier is relative to the impedance that the power amplifier is able to efficiently drive. Bluetooth power amplifiers may be configured to operate in several different power modes (e.g., a high power mode, a low power mode, and an ultra-low power mode). Wi-Fi power amplifiers are typically operated at higher power levels than Bluetooth power amplifiers, for example, because Wi-Fi signals are typically transmitted at higher power levels than Bluetooth signals. As a result, Wi-Fi power amplifiers and Bluetooth power amplifiers may have different configurations, different operating characteristics, and/or different operating points, and may be optimized for power transmission efficiency by different load impedances.
For wireless devices including a Wi-Fi power amplifier and a Bluetooth power amplifier that share the same output load, it may be difficult to configure the output load in a manner that optimizes power transmission efficiency for both the Wi-Fi power amplifier and the Bluetooth power amplifier. Further, for wireless devices in which an antenna is shared between the Wi-Fi power amplifier and the Bluetooth power amplifier, it may be difficult to ensure reliability of the Bluetooth power amplifier when the Wi-Fi power amplifier is transmitting (e.g., because the Wi-Fi power amplifier typically drives Wi-Fi signals at higher power levels than the power levels to which the Bluetooth power amplifier drives Bluetooth signals).
Thus, there is a need to dynamically configure and/or dynamically adjust one or more settings of the shared output load in a manner that optimizes the power transmission efficiency for both the Wi-Fi power amplifier and the Bluetooth power amplifier and that ensures reliability of the Bluetooth power amplifier when the Wi-Fi power amplifier is transmitting.

Switchable supply and tunable load impedance power amplifier