A test structure and a method for fabricating the same are disclosed. The test structure includes a plurality of sampling lines over a substrate located between a plurality of a first grounding lines and a plurality of a second grounding lines. The sampling lines are selectively electrically coupled to the first grounding line or the second grounding line and include at least one programmed defect. A double-patterning fabricating approach is utilized to produce such test structure which may be applied to a charged particle beam such as an electron-beam defect inspection system.

1. Field of the Invention
The present invention relates to a test structure for inspecting an electrical device; and more particularly, relates to a test structure, fabricated by double patterning technology, for inspecting an electrical device.
2. Description of the Prior Art
In material processing methodologies, pattern etching comprises application of a thin layer of light-sensitive material, such as photo-resist, to an upper surface of a substrate that is subsequently patterned to fabricate a mask suitable for transferring this pattern to an underlying thin film on a substrate. The patterning of the light-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) of the light-sensitive material using, for example, a photo-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in a case of positive photoresist), or non-irradiated regions (as in a case of negative resist) using a developing solvent. Moreover, this mask layer may comprise multiple sub-layers.
In a pattern of dense lines and spaces printed at a fine resolution, a line width critical dimension (CD) of the lines is substantially equal to the space width of the spaces, so that the line width is half of the pitch at which the lines are disposed in the pattern. A maximum density at which lines can be printed is determined by the characteristics of a lithographic apparatus as well as the printing process. The apparatus characteristics include characteristics of the imaging system (e.g. an optical projection system) of the apparatus. The process characteristics include characteristics of exposure and development processes, and that of the resist material.
More recently, a double patterning approach has been introduced to allow patterning of smaller features at a smaller pitch than what is currently possible with standard lithographic techniques. One approach to reduce the feature size is to use standard lithographic pattern and etch techniques on the same substrate twice, thereby forming larger number of patterns spaced closely together to achieve a smaller feature size than would be possible by single exposure. In, for example, a dual-trench double patterning process for printing dense lines and spaces, a first and a second pattern of spaces are etched, in interleaved position, in a target layer. The target layer may be, for example, a sacrificial etch mask to be used for an etching of a layer underlying the target layer. Such a double patterning technique exploits the possibility to print, in a single exposure process and for a given numerical aperture (NA) and wavelength λ, a semi-dense pattern of spaces at a width CDdp below the value CD when the spaces are arranged at a pitch greater than 2k1 (λ/NA). Thus, such a pattern is not a dense pattern in the sense that the widths of the lines and spaces are equal. Instead, a width of the lines is, for example, a factor three times the width CDdp of the spaces. For printing such a semi dense pattern of line-shaped spaces or a semi dense pattern of trenches, wherein CDdp<CD, generally a positive tone resist is used.
A dual-trench double patterning process for printing dense lines is characterized by the following three steps. In a first step, a first semi dense pattern of spaces is printed in resist material. After development of the resist material, the remaining resist material mask is used as etch mask for the second step. In the second step, the spaces are transferred to a target layer by applying an anisotropic etching process to the substrate, and the resist material mask is then stripped. In some cases, a Reactive Ion Etching (RIE) process is used. In a third step, the target layer is again coated with resist material, and a second semi dense pattern of spaces is printed in the resist material. The second printing is arranged such that the spaces of the second pattern are positioned interleaved with respect to spaces etched in the target layer. As a result of the interleaving, a subsequent etching of the target layer, again using an RIE process, yields lines of target layer material protruding from the surface of the substrate. By interleaving two patterns of semi dense spaces, each pattern characterized by a space width CDdp and a pitch 4 CDdp, the resulting lines have a width equal to the space width CDdp, so that a dense line pattern is obtained.
A charged particle beam imaging system, such as an electron beam imaging (EBI) system, is increasingly applied in advanced IC chip manufacturing to detect fetal defects which would result in waste devices. EBI can be used to inspect defects such as an open defect, a short defect or a leakage defect on or underneath the wafer surface by detecting voltage contrast (VC) due to the surface charge induced gray level (GL) variation. For such purpose, semiconductor test structures of various shapes, building materials and electrical characteristics have been developed to more easily identify the location of the defects. Nowadays, as the size of the semiconductor device is rapidly shrinking, test structures with finer features are needed to correctly reproduce the device at interest. Therefore, it is desirable to fabricate scaled test structures with desired pattern layout and electrical characteristics utilizing the double patterning technique, so the testing of an interested device can be realistically carried out.

Test structure for charged particle beam inspection and method for fabricating the same


In a method for detecting and picking up dies from a wafer, when a defective die is detected inside a predetermined reversing range defined on the wafer, the die detection and pick-up movement is shifted one pitch to the next row of dies so as to detect the first die of the next row. If the first die of the next row is not a defective die, the die detection and pick-up movement proceeds toward the edge of the wafer in the X direction and successively detects and picks up dies on that row. Then, when a defective die is detected on that row, the direction of the die detection and pick-up movement is reversed without picking up the defective die, so that the die located immediately at the inner side of the first die of that row is detected and picked up, and non-defective dies on that row are successively detected and picked up. If the first die on the next row described above is a defective die, then the die detection and pick-up movement proceeds in the reverse direction so that the dies on the that row are successively detected and picked up as long as they are not defective dies.

1. Field of the Invention
The present invention relates to a method for picking up dies from a semiconductor wafer on which a plurality of dies are formed.
2. Prior Art
Generally, wafers have a round shape, and a plurality of dies which have a square shape are formed in longitudinal and lateral rows on such wafers. As a result, the edges of dies located in the peripheral area of the round wafer have a circular arc shape, and the prescribed die shape cannot be obtained in such dies. Thus, such dies are called defectively shaped dies. Furthermore, the dies near defectively shaped dies often do not have completely formed circuits. Such dies on which no complete circuits are formed are generally called "mirror dies", and these mirror dies are defective. Recently, therefore, there has been a tendency of dies deliberately not formed in the peripheral areas of the round wafers.
Conventionally known methods detect dies having a defective shape in the peripheral areas of a wafer are disclosed in, for example, Japanese Patent Application Laid-Open (Kokai) No. 56-98835.
In the method disclosed in this prior art, the external shapes of the dies are detected by a detecting device that is moved in a detecting direction; and when a defectively shaped die is detected, the detecting device is moved to the next row and reverses the direction of detection (i. e., the direction in which die pick-up proceeds) and continues the detection.
Another method is disclosed in Japanese Patent Application Publication (Kokoku) No. 1-45221. In this method, the detecting device is moved to the next row and reverses the direction of detection when no die has been detected several consecutive times from the circumference of the wafer.
The prior arts described above, however, in fact, do not detect mirror dies or dies resembling mirror dies (which contain defective circuits) in the peripheral areas of the wafer. Accordingly, when these techniques are used to detect mirror dies or dies resembling mirror dies, the number of times to detect dies increases, and there is a significant drop in productivity.


In operation, the main pump (24) is activated and the main value (18) is opened in response to the ignition switch (28) being turned ON to pump fuel from the fuel supply tank (12) to the injectors in the injector manifold (14). During the ON condition, the return control valve (48) is closed to prevent back flow from the injector manifold (14) to the fuel tank (12). In response to the ignition switch (28) being turned to the OFF condition, the main valve (18) is closed and the main pump (24) is deactivated and, most importantly, the return control valve (48) is opened and the return pump (40) is activated to place a negative or vacuum pressure on the upstream side of the injectors to return the residual fuel therein to the fuel tank (12). This prevents the residual fuel from leaking through the injectors and into the combustion chambers of the engine (10), which, in turn, would make it difficult to immediately restart the engine (10) because of a fuel rich condition.

1. Field of the Invention
The subject invention relates to a fuel injection system including a fuel pump which pumps fuel from a fuel tank through an electronic control valve and to the fuel injectors in an internal combustion engine.
2. Description of the Prior Art
The injectors are frequently fed fuel from a common rail which, in turn, receives fuel from an electronic control valve. The fuel is pumped through the electronic fuel valve by a pump and the electronic fuel valve is closed to terminate flow in response to the ignition system being turned off. However, the residual pressure between the electronic fuel valve and the injectors is sufficient for fuel to leak through the injectors and into the combustion chambers thereby causing a fuel rich or "flooded" condition which impedes an engine re-start.
The U.S. Pat. No. 5,630,399, granted May 20, 1997, to Nomura et al. addresses this problem by placing a relief valve in the supply line to the injectors.

Method and apparatus for limiting fuel leakage through injectors after engine shutdown


A transmission includes a drive force transmission/interruption mechanism that restricts the rotation of a propeller shaft. By operating a shift lever, the shift operation of the transmission and the operation of the drive force transmission/interruption mechanism can be performed, and a lock operation and an unlock operation of a differential lock mechanism can be performed. When a driver wants to bring a vehicle into a parking state, by operating a shift lever, a state is provided where a drive force transmission/interruption mechanism is locked so that the rotation of a propeller shaft is restricted, and the vehicle can be held in a stopped state by bringing a differential lock mechanism into a locked state. Since the vehicle can be brought into a parking state using the shift lever, a so-called parking lever becomes unnecessary so that the number of operation elements can be reduced.

Field of the Invention
The present invention relates to a vehicle provided with a shift lever mechanism, and particularly to an improved shift lever mechanism.
Description of Related Art
There has been known a vehicle provided with a shift lever for changing over a traveling mode (for example, see JP-A-2007-62607 (FIG. 3))
In FIG. 3 of JP-A-2007-62607, an operation lever device (100) is disclosed (numerals with a parenthesis indicating symbols described in JP-A-2007-62607, the same being applied for the explanation made hereinafter). The operation lever device (100) includes an operation mode switching lever (102) and a shift lever (103).
Switching between 2-wheel driving and 4-wheel driving and lock-free switching of a differential-lock mechanism are performed by the operation mode switching lever (102). Switching between high-speed frontward traveling, low-speed frontward traveling and backward traveling is performed by the shift lever (103).
Although not described in JP-A-2007-62607, a parking lever or a parking pedal, which is operated in a parking state, is additionally provided to the vehicle.
Assuming that the parking lever is provided to the vehicle, it is necessary for a driver to operate three operation elements consisting of the parking lever, the operation mode switching lever (102) and the shift lever (103) and hence, the operation becomes cumbersome. Further, three levers are necessary and hence, the number of parts is increased whereby a space for mounting the parts becomes necessary.
There is a demand for reducing the number of operation elements to reduce the number of parts and required mounting space.


The disclosure is directed to a memory storage device and an automatic error repair method thereof. In an aspect, the memory storage device includes a connection interface configured to receive a write command and a word line address associated with the write command, a memory array including a memory bank which contains an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address, a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells, and a memory control circuit configured to transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

Presently, since user data stored in a memory storage device are expected to be highly reliable, a typical memory storage device would apply a particular error correction code (ECC) technique in order to detect bit failures and to subsequently restore the data associated with the bit failures. If cells in the memory storage device are damaged or have become weaker, memory bits stored in the damaged cells could be detected by the ECC. However, the cells that are physically damaged or worn out might not be repaired by the ECC, and thus memory bits stored on these damaged cells would likely continue to fail. Moreover, the ECC would only able to fix a predetermined number of bits. If one or more additional bits other than the predetermined number of bits within the same column or row address have failed, then the data cannot be repaired by the ECC.
Since any ECC technique has a limitation for fixing stored memory bits, a memory storage device may experience unrepairable errors under circumstances such as a cell to cell short, a word line direction failure (e.g. floating word line, word line short to bit line, etc.), and so forth. After a memory storage device has been sold to a customer and is under normal operation, bit failures to have be automatically fixed within a specified period which is predetermined by its product specification, and the bit failures may not exceed the maximum capability of the ECC scheme being used. Such problems could be fatal to a memory storage device that requires high reliability. Therefore, once a memory storage device is under normal operation after it is sold to a user, if failure bits could be automatically detected and physically repaired, then the probability of failures could be greatly reduced.
One way to repair the failure bits is to use a redundant memory block for storing data and address after a failure attempt. However, such scheme would often involve reading and/or writing data through a data line. Such scheme would have difficulties when integrated into existing architecture since the data line is not only used by the redundant memory block but also used by normal operation whenever a write command is received.

Memory storage device having automatic error repair mechanism and method thereof


A powered sliding device for sliding a vehicle sliding door along a guide rail comprises a base plate fixed to the vehicle body, a wire drum rotatably mounted on the base plate and rotated by a motor, a wire cable provided between the wire drum and the sliding door, a first holder provided in the vicinity of one end of the guide rail and having a first pulley making contact with the wire cable, a second holder provided in the vicinity of the other end of the guide rail and having a second pulley making contact with the wire cable, a tension roller provided on the base plate for making contact with the wire cable by resiliency of a spring, a flexible cable sheath covering the outer periphery of the wire cable between the first holder and the base plate and having one end to be connected to the first holder, a supporting member connected to the other end of the cable sheath. The supporting member is slidably mounted to the base plate in parallel with a running direction of the wire cable.

1. Field of the Invention
The present invention relates to a powered sliding device for a vehicle sliding door, and more particularly to a tension adjusting apparatus for use in a powered sliding device for a vehicle sliding door.
2. Description of the Related Art
There have been conventionally proposed many powered devices for sliding a sliding door which is slidably mounted to a vehicle body in a front-and-rear direction of the vehicle body under the power of the motor. For example, U.S. Pat. No. 5,046,283 discloses a powered sliding device which comprises a first wire drum connected with a first wire cable for pulling the sliding door forward, a second wire drum connected with a second wire cable for pulling the sliding door rearward and a tension spring provided between the first and second drums. The tension spring applies a predetermined tension to the wire cables by urging the first drum in the clockwise direction and urging the second drum in the counterclockwise direction.
The tension spring used in the powered sliding device has high resiliency so that it can resist a large force of the powered device with which the wire cable is pulled forward and rearward. The strong resiliency of the tension spring, however, causes difficulty in setting up the wire cable.
The present applicant (or Assignee) has proposed in U.S. patent application Ser. No. 08/702,956, UK Patent Application No. 9618139.1 and Korean Patent Application No. 96-36695 a tension mechanism which is divided into a first tension section for applying an initial tension to the wire cables after the completion of the set-up of the cables and a second tension section for absorbing looseness of the wire cables in use. In this tension mechanism, since the first tension section and the second tension section are independently provided at different positions, a plurality of processes are disadvantageously required for setting up the tension mechanism itself.

Tension adjusting apparatus for use in vehicle door powered sliding device


A method for securing residential and low rise commercial structures during periods of high wind employing mooring apparatus having a mooring cable (20), a ground anchor (22), and a tightening means (24). One end of the mooring cable (20) is permanently attached to a structural roof member, the remainder being stowed with the tightening means (24) in a roof housing (26). The ground anchor (22) is strategically installed exterior to the structure. Prior to the onset of a hurricane or other high wind condition, the mooring cable (20) is released from its roof housing (26), detachably fastened to the ground anchor (22), and made taught using the tightening means (24). A number of mooring apparatus are used to secure a given structure. Different ways of housing the stowed mooring cable in different types of structures are described.

1. Field of Invention
The present invention relates to securing low rise residential and commercial structures in high wind conditions including hurricanes, cyclones, and typhoons. More particularly, this invention describes mooring apparatus that are deployed from building roofs and attached to ground anchors in order to secure the roof and underlying structure during periods of high wind and inclement weather.
2. Description of the Prior Art
The threat posed by high winds to low rise structures in general, and to their roofs in particular, has long been appreciated. Recent hurricanes in Florida and Hawaii have served to underscore the threat and magnitude of the problem.
It is well known and understood that architectural design can been used to strengthen structures and render them less vulnerable to inclement weather. Geodesic domes, and to a lesser extent A-frame structures are, consequent to their shape and structural design, least susceptible among low rise structures to damage by high wind. While strong, these structures are not found aesthetically pleasing by many. Also, by virtue of their design they include much unusable interior space and occupy large amounts of land area relative to other structures.
A primary object of the present invention is to provide a means and method of securing low rise structures during periods of high wind and inclement weather without compromising the architectural aesthetics of the structure. A further object of the present invention is to provide said means and method without wasting interior structural space and without consuming unnecessary land area.
A variety of hardware has developed to protect conventional low-rise structures against the threat of high winds. This hardware, often referred to as hurricane clips, serves to strengthen the joint where structural roof members such as rafters and beams meet structural wall members such as posts. While hurricane clips help ensure that the structural frame aspects of a building do not pull apart, the clips are not capable of counterbalancing the lifting force of the wind on the structure. Accordingly, their usefulness is limited and they are only partially successful in protecting structures against hurricane and other wind damage.
A further object of the present invention is to secure roofs and structures during periods of high wind by increasing the strength of the structure through a means which counterbalances the lifting force of the wind on the roof and building structure.
Tie down devices used to secure structures against the force of high winds are also known and understood. Originally described to secure agricultural storage structures and mobile homes, tie down apparatus comprising cables, plates or straps attached to ground anchors have also been applied to secure residential structures. The known tie down devices are of two varieties, those permanently affixed to the structure and those which are attached only during periods of high wind and bad weather.
Permanently attached tie down apparatus are always in view and detract substantially from the aesthetics of the structure. Permanent tie down devices also cause a large area of space around the structure to become lost and unusable for normal activities.
Known temporary tie down devices require substantial time, tools, labor, skill and strength to assemble. A minimum of two strong adults using a ladder and other tools are required to fully deploy available tie down devices. Accordingly, these devices are cumbersome and potentially expensive to use, and of little use to the elderly, persons of living alone, and persons without appropriate tools on hand. Moreover, there is often insufficient warning of high wind conditions to permit full assembly of such apparatus even where sufficient manpower and tools are available.
A further object of the present invention is to secure roofs and low rise structures by means of a temporary tie down device which does not interfere with the everyday aesthetics of the structure nor occupy land area around the structure on a permanent basis, and which can be easily and quickly deployed and assembled by a single adult with few or no tools and a minimum of time and strength.

Apparatus and method for securing building during high wind conditions


The invention is directed to the preparation of organic or aqueous-organic hydrogen peroxide solutions by direct synthesis from a non-explosive gaseous mixture containing hydrogen and oxygen. The process is carried out in the presence of a noble metal catalyst, using a reaction medium containing a halide and a strong acid. It can be performed in a stainless steel reactor without corrosion occurring to the reactor material if, during the reaction, the surface of the stainless steel is, at no place, in permanent contact with the gaseous mixture passing through the reactor.

It is known that hydrogen peroxide may be prepared by direct synthesis from gaseous mixtures containing hydrogen and oxygen by reacting the gaseous mixture on a noble metal catalyst in the presence of a liquid aqueous, aqueous-organic or organic reaction medium. The organic or aqueous-organic hydrogen peroxide solutions obtainable by the direct synthesis process are of interest as oxidizing agents for the catalytic oxidation of organic compounds.
One problem with the direct synthesis of hydrogen peroxide is that the noble metal catalysts used have an unwanted catalytic activity in decomposing hydrogen peroxide to water and oxygen. This activity can be inhibited by adding a sufficient concentration of a strong acid and halide to the liquid reaction medium. However, the addition of acid and halide causes the reaction medium to become strongly corrosive towards metallic materials, particularly stainless steel. One problem that this creates is that, although metal reactors are desirable for use in processes on an industrial scale because of their ability to dissipate heat, corrosion of the reactor material gives rise to safety problems. This is especially true if the direct synthesis is carried out at elevated pressure, which is desirable for achieving a high space-time yield. In addition, metal ions dissolved out of the reactor material by corrosion have an adverse effect on the stability of the hydrogen peroxide solutions prepared, and may cause unwanted secondary reactions when the solutions are used in oxidation reactions.
The problem of corrosiveness due to the simultaneous presence of acid and halide ions in the reaction medium is known from EP-A 0 978 316 and EP-A 1 344 747, both of which suggest carrying out the reaction in the presence of special catalysts in which the noble metal is applied to a catalyst support containing acid groups. Although the use of the proposed catalyst supports makes it possible to lower the acid concentration in the reaction medium, it is still necessary to add 3 to 34 ppm of HBr in order to effectively inhibit the decomposition activity of the catalyst, and therefore the liquid reaction mixture remains corrosive. Because of this corrosiveness, EP-A 0 978 316 suggests using autoclaves which are either made of the particularly corrosion-resistant alloy Hastelloy C or are made of stainless steel and have a glass insert to contain the liquid reaction medium. The use of these materials or inert reactor coatings, for example glass or PTFE, increases production costs and may make the process uneconomical. There is therefore a need for a process for the direct synthesis of hydrogen peroxide in the presence of acid and halide that can be carried out in a reactor made of a commercially available stainless steel material without corrosion.
It is known from DE-A 196 42 770 to carry out direct synthesis reactions in a methanolic reaction medium containing 0.4 wt. % of sulfuric acid, 0.1 wt. % of phosphoric acid and 6 ppm of bromide in the form of sodium bromide, and to use a shaped body made of V4A steel fabric coated with palladium metal as the catalyst. Because of the coating, the V4A steel fabric used as the catalyst support is not in direct contact with the corrosive reaction mixture. The document does not teach how to avoid corrosion of stainless steel on direct contact with the corrosive reaction mixture.
DE-A 198 57 137 describes the direct synthesis of hydrogen peroxide in a methanolic reaction medium containing 0.3 wt. % of sulfuric acid, 0.03 wt. % of phosphoric acid and 5 ppm of bromide in the form of sodium bromide. The reaction is carried out in a V4A steel autoclave operated as a continuous stirred tank. The autoclave is operated in this case with a gas stirrer to disperse the gaseous mixture in the liquid reaction medium. For a construction of this type, the autoclave has to contain a gas cushion in the region of the cover so that the gas stirrer can suck in gas and distribute it in the reaction mixture. '137 does not disclose the period of time over which the direct synthesis was carried out in the V4A stirred autoclave. The document also does not disclose the extent to which corrosion occurred on the reaction vessel or how to avoid corrosion.
WO 03/082458 describes a process for the direct synthesis of hydrogen peroxide in which a gaseous mixture and a liquid reaction medium are passed at high velocity through a tubular reactor so that a coherent gas phase does not form in the reactor. As materials suitable for the reactor, the document mentions duplex stainless steels having a PREN number of more than 34. Since duplex stainless steels have a substantially higher chromium and molybdenum content than commercially available austenitic stainless steels, they are more expensive and also less readily available. Because of the necessary high flow velocity of 1.2 m/s or more, the process described in WO 03/082458 also requires particularly long and hence expensive reactors. Thus, for example, a pressure reactor with a length of more than 2000 m is used in Example 1.

Process for the direct synthesis of hydrogen peroxide


The present invention is directed to methods of administering a material to a patient for dermal enhancement and/or as soft tissue fillers. The invention also relates to double-gloved methods of molding such a material after administration to a patient to achieve a desired orientation of the material in the patient. The invention also relates to the use of certain materials, including polylactic acid, hyaluronic acid, hydrogel, and/or collagen or other suitable materials for the preparation of a pharmaceutical composition for dermal enhancement and/or as soft tissue filler. The invention further relates to kits or packages that include a material for dermal enhancement and/or soft tissue filler and instructions as to how dermal enhancement or the filling of soft tissue is achieved.

It is often desired to improve irregularities of the skin and/or to manage facial lipoatrophy. The use of certain materials for these purposes is known. It would be beneficial, however, to provide improved methods of administering, sculpting and/or molding certain materials in order to achieve a desired orientation of administered material.

Methods of administering a material into a patient for dermal enhancement


In the information process device 1, only when it is determined that the password rewritten in the change password memory area 14a of the backup RAM 14 and the password rewritten in the change password memory area 31a of the second flash memory 31 coincide with each other (S202: YES), the menu display of the liquid crystal display 21 is conducted (S107) and it is permitted to start execution of the application program (S123) based on that the menu M2 of “2. start of game” is selected in the menu display. Further, based on that the menu M1 of “1. set of password” is selected in the menu display (S109: 1), it is permitted input of the change password by touching each of the areas 22c to 22n of the transparent touch panel 22 (S112).

1. Field of the Invention
The present invention relates to an information process device in which illegal use of software stored in an extension board can be avoided.
2. Description of Related Art
Among conventional information process devices, for example, there exists an information process device in which an extension board installing a flash memory and the like storing game soft programs is used and the game soft programs are operated. Therefore, different game soft programs can be provided to such information process device by using another extension board.
And in the above method to provide the game soft programs, there is a case that the game soft programs stored in the extension board are illegally used, therefore in order to avoid the illegal use of the game soft programs a security system is required in the information process device. Thus, for example, as described in Unexamined Japanese Publication No. 2001-344096, it is disclosed an information process device in which discriminative information respectively stored in memory media of both a main body of the information process device and the game soft program is compared with each other and it is determined whether or not the game soft program is executed, thereby security to avoid the illegal use of the game soft program is raised.
However, in the above method to raise security, if the security system is constructed beforehand at a supplier side supplying the extension board, the security system cannot be changed at all. Therefore, such security system cannot be improved into the security system on which intention at a user side using the extension board is reflected.

Information process device and method for verifying discriminative informations


A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

The present invention relates to silicon carbide and other films, and, more particularly, to controlled deposition of these films on a substrate.
Semiconductor, micro- and nanoelectromechanical systems (MEMS/NEMS) apply integrated circuit fabrication technology to fabricate optical, mechanical, electrochemical, and biosensor devices. One of the important steps in creating MEMS and NEMS devices is the deposition of thin films of material onto substrates. Once the films are deposited, various etching techniques may be employed to shape the deposited film.
In typical MEMS/NEMS devices, silicon is a primary material. Silicon carbide is a material that has very good physical and chemical characteristics, and is noted for these properties at temperatures above about 300° C. Silicon carbide is an advantageous material for use in films for MEMS and NEMS, particularly because of its exceptional electrical, mechanical, and chemical properties compared to silicon in normal and harsh operating environments.
One of the barriers limiting development of silicon carbide in MEMS production has been the inability to deposit uniform films of silicon carbide on large area substrates having properties that are advantageous to and required for MEMS and NEMS. Deposition of silicon carbide is conventionally subject to variations in residual stress, residual stress gradient, and electrical resistivity. These properties are important to the proper operation of MEMS and NEMS devices.
With silicon, residual stress, residual stress gradient and electrical resistivity can be controlled after the film is deposited by annealing the film at elevated temperatures. Annealing in silicon induces crystallographic changes that result in the modification of these properties. With single crystalline and polycrystalline silicon carbide, such an approach is not feasible because silicon carbide is chemically and crystallographically stable at conventional annealing temperatures. For silicon carbide films deposited on silicon substrates, annealing is completely ineffective because the non-silicon carbide substrate limits the annealing temperatures to temperatures too low for effective annealing. The present invention bypasses the need for annealing altogether by implementing control of the residual stress, residual stress gradient, and electrical resistivity in the silicon carbide films during the film formation (deposition) process.

Silicon carbide and other films and method of deposition


A method for thermal pest control in fruit production and agriculture involves projecting at least one stream of hot air to a crop from a movable vehicle which moves in a direction substantially parallel to rows of the crop. The stream of hot air can be projected substantially parallel to, substantially transverse to, or substantially oblique to the rows of the crop.

Chemical pest control in agriculture and in fruit culture has been used very successfully to control pests during the past seventy years. Every year, more chemicals are developed, apparently with new advantages over their predecessors relating to cost, ease of application, and the varieties of pests controlled. Unfortunately, also for a long time, and currently, it has been discovered that many of these chemicals have undesirable secondary effects on the environment or on other plants and animals, including man. Some of these undesirable effects, due to a cumulative effect on the body or to genetic transmission affecting new generations, have been seen only after many years of continuous use of the chemical; other undesirable effects are seen very fast. For these reasons, there is a tendency to look for solutions with very little or no impact at all on the environment.
One of the first non-chemical solutions was a biological pest control provided by stimulating development of natural predators of pests. A problem with this is that sometimes a predator will eliminate not only a pest but also some of the natural controls, and then a serious ecological problem may result.
Other pest control alternatives to biological and chemical methods involve the modification of some physical variables of the pest habitat; in this way the pest is put in an environment which is unfriendly to its development and reproduction. These kinds of solutions include, among others, refrigeration, humidity reduction, heat application, and oxygen reduction. A problem with this kind of solution is determining the habitat variables to be modified and the magnitude and time of habitat variable modification in order to get desired effects on the pest without harming the species to be protected.
In these kinds of solutions, heat application has been shown to be very useful. One of the first solutions for eliminating microorganisms was the well-known method of pasteurization. This method is only applicable to inanimate substances of animal or plant origin, and cannot be used on live animals or plants. Other methods for pest control using heat have been proposed; such methods are disclosed in U.S. Pat. No. 4,817,329 to Forbes and U.S. Pat. No. 6,279,261 to Binker et al.
Forbes teaches a method to kill insects, such as termites, in an urban structure, such as an insulated space, in which a heated gas, with no phase changes, is insufflated. The gas is at a temperature above the ambient temperature which is lethal for the insect, and the temperature is maintained for a sufficient period of time to kill the insect. In the Forbes method, entrance ducts and exit ducts for the heated gases are installed. Forbes also teaches that the space to be treated has to be insulated with mats in windows and doors in order to facilitate accumulation of heated gases. As a result, the Forbes method cannot be used in open spaces and, therefore, cannot be used in agriculture or fruit production.
Binker et al. also teach a method to kill pests in closed spaces, like mills or food processing plants. The Binker et al. procedure does not require insulating spaces, but this is because the space in which the Binker et al. method is used is normally closed and without windows, like in the urban structures of Forbes. The Binker et al. method is not applicable in open fields like those used in agriculture or fruit production. The most important concerns of Binker et al. are to not contaminate or alter foods in a processing plant, to avoid the introduction of combustion gases, and to control the humidity of the heated air.
Neither Forbes nor Binker et al. teaches a pest control method using heated gases or heated air in an open space in which it is necessary to maintain or preserve, without any harm, living vegetable species like vines, fruit trees, or plants.


A method and system for correcting optical aberrations in a maskless lithography system. Adjusters move individual spatial light modulators (SLMs) in an SLM array so that the surface of the SLM array deviates from a flat plane. The deviation compensates for aberrations in the lithography system, such as total focus deviation. In an embodiment, an individual SLM can be tilted, bent, and/or have its elevation changed. Multiple SLMs in the SLM array can move in different ways depending on the compensation to be made. The adjusters can be either actively or passively controlled. The method may be performed only during initial setup of the maskless lithography system, periodically as needed for maintenance of the lithography system, or prior to each exposure in the lithography system.

1. Field of the Invention
The present invention is directed generally to lithography. More particularly, the present invention relates to maskless lithography.
2. Related Art
Lithography is a process used to create features on the surface of substrates. Such substrates can include those used in the manufacture of flat panel displays (e.g., liquid crystal displays), circuit boards, various integrated circuits, and the like. A frequently used substrate for such applications is a semiconductor wafer or glass substrate. While this description is written in terms of a semiconductor wafer for illustrative purposes, one skilled in the art would recognize that this description also applies to other types of substrates known to those skilled in the art.
During lithography, a wafer, which is disposed on a wafer stage, is exposed to an image projected onto the surface of the wafer by exposure optics located within a lithography apparatus. While exposure optics are used in the case of photolithography, a different type of exposure apparatus can be used depending on the particular application. For example, x-ray, ion, electron, or photon lithography each can require a different exposure apparatus, as is known to those skilled in the art. The particular example of photolithography is discussed here for illustrative purposes only.
The projected image produces changes in the characteristics of a layer, for example photoresist, deposited on the surface of the wafer. These changes correspond to the features projected onto the wafer during exposure. Subsequent to exposure, the layer can be etched to produce a patterned layer. The pattern corresponds to those features projected onto the wafer during exposure. This patterned layer is then used to remove or further process exposed portions of underlying structural layers within the wafer, such as conductive, semiconductive, or insulative layers. This process is then repeated, together with other steps, until the desired features have been formed on the surface, or in various layers, of the wafer.
Step-and-scan technology works in conjunction with a projection optics system that has a narrow imaging slot. Rather than expose the entire wafer at one time, individual fields are scanned onto the wafer one at a time. This is accomplished by moving the wafer and reticle simultaneously such that the imaging slot is moved across the field during the scan. The wafer stage must then be asynchronously stepped between field exposures to allow multiple copies of the reticle pattern to be exposed over the wafer surface. In this manner, the quality of the image projected onto the wafer is maximized.
Conventional lithographic systems and methods form images on a semiconductor wafer. The system typically has a lithographic chamber that is designed to contain an apparatus that performs the process of image formation on the semiconductor wafer. The chamber can be designed to have different gas mixtures and grades of vacuum depending on the wavelength of light being used. A reticle is positioned inside the chamber. A beam of light is passed from an illumination source (located outside the system) through an optical system, an image outline on the reticle, and a second optical system before interacting with a semiconductor wafer.
A plurality of reticles are required to fabricate a device on the substrate. These reticles are becoming increasingly costly and time consuming to manufacture due to the feature sizes and the exacting tolerances required for small feature sizes. Also, a reticle can only be used for a certain period of time before being worn out. Further costs are routinely incurred if a reticle is not within a certain tolerance or when the reticle is damaged. Thus, the manufacture of wafers using reticles is becoming increasingly, and possibly prohibitively expensive.
In order to overcome these drawbacks, maskless (e.g., direct write, digital, etc.) lithography systems have been developed. The maskless system replaces a reticle with a spatial light modulator (SLM) (e.g., a digital micromirror device (DMD), a liquid crystal display (LCD), or the like). The SLM includes an array of active areas (e.g., mirrors or transmissive areas) that are individually controlled to form a desired pattern. These active areas are also known in the art as "pixels." A stored control algorithm based on a desired exposure pattern is used to control the pixels. Each pixel in an SLM can vary its optical properties (e.g., amplitude/phase transmittance) in a controllable manner so as to provide a variation of a dose delivered to the wafer surface.
As maskless lithography capabilities increase, the tolerance for error in an exposure decreases. Among the errors present in an exposure are optical aberrations in the exposure optics, which are typically caused by manufacturing and assembly tolerance in the exposure optics. Aberrations can result in total focus deviation, among other exposure errors. Total focus deviation results when a focal length of the exposure optics is not identical in all areas of the exposure beam. In this case, a flat array of SLMs does not focus onto a flat plane at the image or wafer plane. When the optics are changed to correct for the error, movement of the optics components requires great precision. Otherwise, difficulties arise that can introduce additional error into the system. What is needed is a system and method for reducing aberrations without introducing additional error into the maskless system.

Method and systems for total focus deviation adjustments on maskless lithography systems


A composite crimped yarn comprising: at least two kinds of multifilament yarns, one of them being comprised of a crimped conjugate multifilament yarn comprising two kinds of polyester polymers different from each other in the heat shrinkability and positioned as a major component of the inner layer of the composite crimped yarn, the other of them being comprised of a crimped multifilament yarn of a single synthetic polymer and positioned as a major component in the outer layer of the composite crimped yarn. In the above, the length of the crimped multifilament yarn is 5 to 35% larger than that of the crimped conjugate multifilament yarn, part of the crimped multifilament yarn being migrated to the crimped conjugate multifilament yarn disposed in the inner layer and part of the crimped conjugate multifilament yarn being migrated to the crimped multifilament yarn disposed in the outer layer.

The present invention relates to a composite crimped yarn comprising at least two kinds of multifilament yarns and a woven fabric prepared therefrom, and more particularly, to a composite crimped yarn which can be woven into a fabric having a suitable stretching property capable of improving the sewablility while enjoying puffiness and koshi (stiffness) and hari (anti-drape stiffness) similar to those of a woven wool fabric and a drapability inherent in the polyester filament yarn, and a woven fabric prepared therefrom.
As compared with other synthetic fibers, a polyester filament yarn is featured by a less liability to creasing and an excellent adaptability to pleating. An effort has been made to apply a polyester filament yarn having the above-described properties to the fields of suits, bottoms (for example trousers and skirts), etc., where moderately thick or thick wool woven fabrics are extensively used. For the time being, the intention of preparing a polyester woven fabric having a texture close to that of the wool woven fabric, that is, puffiness and koshi and hori, has to be attained by the "woolie" processing method wherein polyester filament yarns are subjected to false twisting and a method wherein two kinds of polyester filament yarns different from each other in the properties are subjected to composite false twisting. However, the development has been further advanced and an attempt has been made not only to bring the texture of the woven polyester fabric close to that of the woven wool fabric but also to impart a drapability inherent in the polyester filament which the woven wool fabric cannot exhibit. As a result, a technique as described in Japanese patent publication No. 61-19733 has been developed.
This method for imparting not only puffiness and koshi and hari similar to those of the woven wool fabric but also a drapability inherent in the polyester filament comprises doubling two kinds of undrawn yarns or partially drawn yarns of polyester filaments different from each other in the elongation, subjecting the doubled yarns to composite false twisting and forming a woven fabric from the resultant composite crimped yarn, wherein the composite crimped yarn is previously subjected to additional twisting. In the twisted composite crimped yarn, when the number of twists (additional twisting) is increased, a core-sheath structure having a two layer structure wherein a multifilament yarn as the outer layer is randomly wound round another multifilament yarn as the inner layer, and curved monofilaments having a size of several microns to several tens of microns are allowed to exist on the outer surface. Therefore, when a fabric is woven out of this composite crimbed yarn, not only puffiness is imparted to the woven fabric but also drapability is imparted through an increase in the density of the multifilament yarn derived from additional twisting.
Although the composite crimped yarn comprising the conventional core-sheath structure imparts puffiness and drapability to the woven fabric, the development of crimping of the multifilament yarn in the core portion is restrained by the twisting applied for the purpose of imparting the drapability, so that the stretching property lowers to a great extent unfavorably. Therefore, when a moderately thick or thick fabric is woven out of the composite crimped yarn, the stretching property becomes so insufficient that the tension of sewing yarn cannot be absorbed during sewing. This gives rise to the occurrence of a crease called "puckering" at the seam, which worsens the tailorability.


A second electrode 20 having a container-like configuration defines a reaction space 29. A mounting portion 12 of a first electrode 10 and a workpiece W loaded on the mounting portion 12 are surrounded by the second electrode 20. A pair of auxiliary walls 27 project upwardly from a bottom wall 21 of the second electrode 20. The mounting portion 12 for the first electrode 10 is disposed in an arrangement area A defined by the auxiliary walls 27. The mounting portion 12 projects from upper end edges of the auxiliary walls 27.

This invention relates to a plasma CVD device used for forming a film on a workpiece.
Recently, much attention is paid to plasma CVD, i.e., chemical vapor deposition utilizing plasma as a method for forming a film at a comparatively low temperature, for example, at a room temperature. In a typical device for carrying out such plasma CVD, as disclosed in FIG. 3 of Japanese Laid-Open Utility Model Application No. 13119/89, a first and a second planar electrodes are arranged in parallel relation within a vacuum vessel which is appropriately grounded. A high frequency power source is connected to the first electrode and the second electrode is grounded. The internal space of the vacuum vessel is provided as a reaction space. A part of reaction gas supplied into this reaction space is caused to be plasma by high frequency field generated between the first electrode and the second electrode. Negative ion or electron of all the plasma is violently motioned by this high frequency field. As a consequence, the reaction gas is partly decomposed to generate a radical. In the second electrode, a planar workpiece is mounted along the second electrode. The positive ion and radical are adhered to the surface of this workpiece, thereby to form a film.
In the above device, since the positive ion is not biased toward the workpiece, the film formed on the workpiece is low in adhesive strength and thin. Further, because of the reasons that a film is also formed on the first and second electrodes and plasma is also generated between the first electrode and the wall of a chamber faced with the first electrode, electric power is wastefully consumed.
A plasma CVD device, which is more resemble the present invention, is disclosed in Japanese Laid-Open Patent Application No. 311448/93. In this device, the internal space of the vacuum vessel is divided into plural sections by a wire net. The divided spaces are surrounded by the wall of the vacuum vessel and the wire net and provided as reaction spaces. The vacuum vessel and the wire net are appropriately grounded so that they serve as a second electrode. A first planar electrode is received in each of the reaction spaces. This first electrode is connected to a high frequency power source through an impedance matching circuit. A workpiece of a generally three-dimensional configuration is loaded on an upper surface of the first electrode. The positive ion of all the plasma generated by the high frequency field proceeds toward the workpiece due to bias function of the impedance matching circuit and the radical, accompanied by the positive ion, also proceeds to the same direction. As a consequence, a film is formed on the surface of the first electrode.
In the device disclosed by the above Japanese Laid-Open Patent Application No. 311448/93, the upper surface among all surfaces of the workpiece is faced with the second electrode. Since the positive ion and its accompanying radical collide with the upper surface generally at right angles, the film formed there is large in adhesive strength and thick. However, the film, which is formed on other surfaces of the workpiece perpendicular to the upper surface of the first electrode, especially the film formed on a lower end portion near the first electrode is small in adhesive strength and thin. The reasons are guessed that since the positive ion and its accompanying radical are drawn toward the upper surface of the first electrode, the amount of ion, etc. colliding the lower end portion of the workpiece is small and the ion, etc. are collided with the lower end portion of the workpiece diagonally instead of at right angles.
Further, a film is formed on the wide area of the upper surface of the first electrode, and the plasma generated between the lower surface of the first electrode and the second electrode faced with the lower surface does not contribute to the formation of film on the workpiece at all. Thus, electric power is wastefully consumed.

c/o Higashimatsuyama Factory of Zexel Corporation, 13-26, Yakyu-cho 3-chome


A system and method for diagnosing faults that occur on a computer system. An executive unit loads an appropriate file set for a given fault from a database of file sets. An expert system unit analyzes the fault and uses the file set to determine a fact request to be asked or a remedy to be applied to the computer system. The executive unit directs a script management unit to run the fact request or remedy script selected by the expert system unit from the file set. If a response is given by a user or the computer system to the fact request, the executive unit returns the response to the expert system unit. The expert system unit engages in a further analysis based on the initial fault information and response received. The expert system makes additional fact requests if needed until a diagnosis is reached or the current file set is exhausted. File sets are linked in problem domains, and the executive unit can load another file set covering the same domain to continue the diagnostic process. If no local file sets are available, a remote unit determines if an appropriate remote file set is available and then retrieves it to continue the diagnostic process. An object management unit manages the file sets, which are structured into case-structured diagnostic sets, runtime files containing scripts and other information, and auxiliary files used by the scripts.

Computer based expert systems perform complex tasks such as aiding doctors and diagnosing illnesses, guiding engineers in controlling complex production processes and diagnosing and correcting computer failures. Typically, these expert systems employ knowledge bases that consist of a collection of data files loaded into a local memory device and made available to an expert system diagnostic computer program. The expert system diagnostic computer program employs the information stored in the data files to guide the user to a solution for the problem at hand. The knowledge base usually consists of a set of data files that contains information about the problem that the expert systems are working to solve. The diagnostic program will access the knowledge base to determine questions that are presented to a system user to collect information for diagnosing a particular problem.
To operate properly, the expert systems require knowledge bases that are complex and complete. The development of such expert system knowledge bases is a highly complex task. Each database contains information about the symptoms and characteristics that occur with a particular fault to provide for a proper diagnostic analysis of a particular problem. Moreover, for those expert systems that further attempt to correct the diagnosed faults, the knowledge bases contain information that instructs a user in correcting the diagnosed fault. Accordingly, these knowledge bases can be large and complex and contain different types of information; some types directed to the symptoms or fault, other types directed to solutions for a fault.
A problem that arises for many types of expert systems is that they depend upon a knowledge base that has current and accurate information. However, because it is a difficult task to update and maintain such complex databases of different types of information, the integration of new diagnostic information and solutions can be a complex and labor intensive procedure.
Accordingly, it is an object of the invention to provide systems and methods for performing expert system diagnostic analysis and resolution that employ a knowledge base that is segmented into specific file sets and domains that are easier to use, manage, update, and maintain.

System and method for diagnosing computer faults


A vaporization chamber for a substrate processing system includes a main body, a cover member and a transition member. The main body is made of aluminum and defines a first inner surface, which defines, at least in part, a cavity. The cover member is also made of aluminum. The cover member defines a second inner surface, which also defines, at least in part, the cavity. The cover member includes a carrier gas cover inlet, a liquid source cover inlet, a source cover outlet which extends from a first outer surface through the cover member to the second inner surface. The transition member is made of stainless steel and has a transition outer surface and a transition inner surface. The transition inner surface is aluminum cladded. The cover member including a carrier gas cover inlet, a liquid source cover inlet, a source cover outlet which extend from a first outer surface through the cover member to second inner surface. The transition inner surface and the cover outer surface are welded together.

1. Field of the Invention
This invention relates generally to the deposition of silicon-containing films, and more particularly to the use of trisilane, Si3H8, in chemical vapor deposition processes for the deposition of thin silicon-containing films on various substrates.
2. Description of the Related Art
Silane (SiH4) is widely used in the semiconductor manufacturing industry to deposit silicon-containing ("Si-containing") films by chemical vapor deposition (CVD). However, the deposition of very thin (e.g., about 150 Å or less) silicon-containing films using silane is very challenging, particularly over large area substrates. Very thin Si-containing films deposited using silane are often not continuous, due to island-like film nucleation processes, or have very rough surfaces due to the coalescence of island-like nuclei. In addition, the elemental composition of doped thin films is often not homogeneous in the cross-film and/or through-film directions because of differences in relative incorporation rates of the dopant elements. The resulting films do not exhibit uniform elemental concentrations and, therefore, do not exhibit uniform film physical properties across the surface and/or through the thickness of the film.
Deposition of such thin films with uniform elemental concentrations represents a serious challenge for deposition processes that rely on silane as the silicon source precursor. Typical furnace-based deposition processes that utilize silane are generally unable to deposit continuous, smooth and homogeneous films having a thickness of 100 Å or less. Plasma-enhanced CVD processes typically have serious limitations for the deposition of homogeneous, continuous thin films with thicknesses below about 200 Å. U.S. Pat. No. 5,648,293 states that, for an amorphous silicon layer over a transistor gate insulator, when the film thickness is less than approximately 15 nanometers (150 Å), both decrease of the electron mobility and increase of the transistor threshold voltage appear. Similarly, typical single wafer thermal CVD processes also suffer from an inability to deposit smooth, homogeneous thin film materials with a thickness of 150 Å or less.
Attempts to produce thin Si-containing films and incorporate them into devices have not been entirely satisfactory. For example, U.S. Pat. No. 6,194,237 discloses depositing a conductive layer of Si0.7Ge0.3 on SiO2, depositing another layer of SiO2 over the conductive layer, and then annealing so that the conductive layer forms quantum dots. The conductive layer is stated to have a thickness of 30 Å, but the wide variation in size and distribution for the resulting quantum dots indicates that the conductive layer was not deposited uniformly. Attempts to provide quantum dots of more uniform size and distribution have been disclosed, but typically involve high temperatures and/or more complicated deposition schemes, see e.g. U.S. Pat. No. 6,235,618.
Japanese Patent Application Disclosure No. H3-187215 discloses the use of pure disilane (free of silane and trisilane) in a thermal CVD device to deposit a film having a thickness of 180 Å; see also Japanese Publication No. 03187215 A. U.S. Pat. No. 5,789,030 discloses a low pressure CVD ("LPCVD") method for depositing an in-situ doped silicon thin film that involves first depositing a very thin layer of silicon before introducing a dopant gas species to form the doped film. While the initial undoped layer is stated to be only several monolayers thick, the overall thickness of the layer is 500 Å to 2,000 Å, including the in situ doped portion.
The use of higher silanes such as disilane and trisilane is sometimes mentioned in the art as an alternative to the use of silane, but in most cases the only data reported concern the use of silane. Disilane (Si2H6) is known to be less stable than silane, and in deposition experiments employing disilane it was reported that disilane gives poor step coverage and that the deposition reaction is too violent to be controlled within the temperature range of 400° to 600° C., see U.S. Pat. No. 5,227,329. Trisilane is even less thermally stable than silane.
The ability to deposit very thin, smooth Si-containing films would satisfy a long-felt need and represent a significant advance in the art of semiconductor manufacturing, particularly for making future generations of microelectronic devices having ever-smaller circuit dimensions.


In one embodiment, the present invention includes a method for obtaining file information regarding a file to be downloaded from a remote location to a computing device, creating at least one empty file in a destination storage based on the file information and communicating block information regarding the empty file to a network interface, and receiving a data packet of the file in the network interface and directly sending a payload of the data packet from the network interface to the destination storage according to the block information, while a host processor of the computing device is in a low power state. Other embodiments are described and claimed.

Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, ultrabooks, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to bio-technology).
As more consumers adopt portable and mobile devices such as smartphones, tablet computers, mobile computers, portable media players and so forth, there is tremendous growth for network-based content and services. Examples include movie downloads, quick synchronizations, e.g., portable media player music/movie synchronization, cloud-based storage, etc. These usage models are fueled by ubiquitous and faster connectivity as well as increased compute capabilities of mobile devices such as smartphones, tablets and ultrabooks.
One drawback in provision of these services on mobile devices is the power consumption that connectivity and communication of large amounts of media content can consume. The typical datapath for the above-mentioned services and many others is as follows: incoming data to a device is received in a source component of the device, e.g., a network interface controller (NIC), and transferred to a sink component of the device, e.g., a storage device. This datapath involves a host central processing unit (CPU) to handle the data movement from one component of the device to the other component through a system memory. According to typical device architectures and data-paths, the host CPU and system memory are heavily involved in the data control and movement from an input device to an output device, which includes handling multiple copies of the data between source component and system memory, or even between kernel space and user space. This overhead incurs high power consumption and lowers performance.

Storing data using a direct data path architecture to reduce energy consumption and improve performance


A headlight includes a first LED cluster having a plurality of first LEDs arranged next to one another on a common first substrate, a second LED cluster having a plurality of second LEDs arranged next to one another on a common second substrate, and an output coupling optical unit having a plurality of optical elements, of which an optical element which comes first in a beam path of the LED clusters has, a light incidence surface which is common to the LED clusters. The LED clusters have a lateral distance from one another which is at least as great as an extent of the LED clusters in the same direction. The common light incidence surface has a locally delimited light incidence region directly in front of an associated LED cluster. The locally delimited light incidence region deviates from the basic shape of the light incidence surface.

Conventional motor vehicles use a non-dazzling high beam (known as "adaptive driving beam," ADB) to dynamically adapt a light output pattern or a light intensity distribution (also referred to as LID). To produce the ADB high beam, it is possible to use a headlight having a light source that has a group, or a cluster, of light-emitting diodes (LEDs) which are settable individually in terms of their radiation intensity.
Vehicle front headlights frequently require a plurality of (i.e. two or more) said LED clusters to produce the desired light output pattern. To save space and costs, the plurality of LED clusters use the same output coupling optical unit. However, if, in the case that a lateral distance between two LED clusters is greater than an extent of the individual LED clusters in the same direction, conventional circularly symmetric output coupling optical units are used, some—e.g. stripe-type—regions in the light output pattern are not illuminated.
In order to avoid these non-illuminated regions, conventionally separate output coupling optical units having different horizontal magnification for different LED clusters are used to cause the associated partial light output patterns to overlap.
Another possibility for avoiding the non-illuminated partial regions is, in theory, to make the distance between the LED clusters smaller then their extent. However, this is not yet possible in practice at this time.

Headlight with clusters of semiconductor light sources


There is provided a method of producing a bonded SOI wafer wherein a silicon single crystal ingot is grown according to Czochralski method, the single crystal ingot is then sliced to produce a silicon single crystal wafer, the silicon single crystal wafer is subjected to heat treatment in a non-oxidizing atmosphere at a temperature of 1100xc2x0 C. to 1300xc2x0 C. for one minute or more and continuously to a heat treatment in an oxidizing atmosphere at a temperature of 700xc2x0 C. to 1300xc2x0 C. for one minute or more without cooling the wafer to a temperature less than 700xc2x0 C. to provide a silicon single crystal wafer wherein a silicon oxide film is formed on the surface, and the resultant wafer is used as the bond wafer, and a bonded SOI wafer produced by the method. There can be provided a SOI wafer that has a SOI layer having few crystal defects, good surface roughness and high quality in high productivity, in high yield and with low cost.

The present invention relates to a method of producing a bonded wafer having very few crystal defects on and near the surface and a bonded SOI wafer.
SOI (silicon on insulator) has a buried oxide film (BOX: Buried OXide) as a insulator film right below a silicon layer that is to be a region for fabrication of device, and is expected to be a silicon material for high speed device with electric power saving performance. One of methods for producing a SOI wafer is a bonding method wherein two silicon single crystal wafers, one of which is to be a bond wafer (a substrate that is to be a SOI layer on which a device is fabricated), and the other of which is to be a base wafer (a substrate supporting the SOI layer) are bonded via a oxide film, and then thickness of the bond wafer is decreased to form a SOI structure. The method has an advantage that crystallinity of the SOI layer is excellent, and insulating property of BOX is high, but has a disadvantage that quality of the SOI layer is influenced much by quality of the bond wafer.
Specifically, it has been known that there exist micro crystal defects (Grown-in defects) such as COP (Crystal Originated Particles) that is a void type defect or the like in a silicon wafer produced according to Czochralski method, which adversely affects characteristics of the device such as oxide dielectric breakdown voltage. In order to solve the problem, there have been known that visible defects can be reduced by using, as a substrate for a bond wafer, a wafer wherein a CZ wafer is subjected to annealing in a hydrogen atmosphere or an epitaxial wafer wherein an epitaxial layer is formed on a CZ wafer (See Japanese Patent Application Laid-open (kokai) No. 9-22993 and Japanese Patent Application Laid-open (kokai) No. 9-260619).
However, two heat treatments, namely heat treatment such as hydrogen annealing or epitaxial growth and heat treatment for forming a buried oxide film, which may lead to increase of cost and lowering of through put.
In the case of the epitaxial wafer, haze (surface roughness) is generated on the surface of the epitaxial layer, or projection called mound is sometimes formed. They may cause bonding failure when the wafers are bonded. Accordingly, it is sometimes necessary to polish the surface of the epitaxial layer before bonding in that case.
On the other hand, crystal defects are reduced by hydrogen annealing only at layer quite near the surface (about 0.5 xcexcm from the surface), and thus, if a SOI wafer having a thickness more than the value is produced, an area where crystal defects are not reduced is exposed. Therefore, crystal defects in the whole SOI layer cannot be reduced, unless any measures are taken, for example, further hydrogen annealing is conducted after SOI wafer is produced. Furthermore, according to annealing with hydrogen, quartz tube, a boat made of SiC or the like are always etched, and contamination with metal impurities or the like are caused thereby.
Furthermore, when heat treatment is conducted in a hydrogen atmosphere, it is necessary to take out the wafer after replacing the atmosphere in the heat treatment furnace with nitrogen gas for safety. At that time, the surface of the wafer is locally etched with slight amount of oxygen and water vapor contained in nitrogen gas, which may degrading surface roughness such as haze or the like, which may lead to bonding failure when they are bonded.
Recently, it has been reported that there can be produced CZ wafer wherein Grown-in defects are significantly reduced if crystal is pulled with strictly controlling a growth rate and temperature gradient of solid-liquid interface while single crystal is grown according to Czochralski method. It can be easily expected that SOI wafer having few defects in SOI layer can be produced if such a wafer is used as a bond wafer. However, if the crystal is pulled under such significantly strict growing condition may naturally lead to lowering in yield, resulting in significant increase of cost for production.
On the other hand, single crystal produced according to FZ method has no COP defects as observed in CZ single crystal, but FZ crystal having a diameter more than 150 mm cannot be produced at commercial level. Although FZ crystal having a diameter of 200 mm can be produced at experimental level, there is no hope for producing a large diameter wafer having a diameter of 300 mm, 400 mm in the future.
The present invention has been accomplished to solve the above-mentioned problems. A main object of the present invention is to provide a SOI wafer that has a SOI layer having few crystal defects and high quality in high productivity, in high yield and with low cost by using a wafer wherein grown-in defects in a surface-layer part of silicon single crystal wafer produced by CZ method are eliminated or reduced effectively by heat treatment as a bond wafer of a bonded wafer.
To achieve the above mentioned object, the present invention provides a method of producing a bonded SOI wafer comprising bonding a bond wafer and a base wafer via an oxide film and then reducing thickness of the bond wafer, wherein a silicon single crystal ingot is grown according to Czochralski method, the single crystal ingot is then sliced to produce a silicon single crystal wafer, the silicon single crystal wafer is subjected to heat treatment in a non-oxidizing atmosphere at a temperature of 1100xc2x0 C. to 1300xc2x0 C. for one minute or more and continuously to a heat treatment in an oxidizing atmosphere at a temperature of 700xc2x0 C. to 1300xc2x0 C. for one minute or more without cooling the wafer to a temperature less than 700xc2x0 C. to provide a silicon single crystal wafer wherein a silicon oxide film is formed on the surface, and the resultant wafer is used as the bond wafer.
As described above, if the wafer produced according to Czochralski method is subjected to heat treatment in a non-oxidizing atmosphere at a temperature of 1100xc2x0 C. to 1300xc2x0 C. for one minute or more and continuously to a heat treatment in an oxidizing atmosphere at a temperature of 700xc2x0 C. to 1300xc2x0 C. for one minute or more without cooling the wafer to a temperature less than 700xc2x0 C. to provide a silicon single crystal wafer wherein a silicon oxide film is formed on the surface, and the resultant wafer is used as the bond wafer, a silicon single crystal wafer having high quality wherein Grown-in defects near the surface of the wafer that are harmful for fabrication of semiconductor device can be eliminated or decreased in short time can be used as a bond wafer, so that SOI wafer that has a SOI layer having few crystal defects and high quality can be produced in high productivity, in high yield with low cost.
The present invention also provides a method of producing a bonded SOI wafer comprising bonding a bond wafer and a base wafer via an oxide film and then reducing thickness of the bond wafer, wherein a silicon single crystal ingot is grown according to Czochralski method, the single crystal ingot is then sliced to produce a silicon single crystal wafer, the silicon single crystal wafer is subjected to heat treatment in a non-oxidizing atmosphere at a temperature of 1100xc2x0 C. to 1300xc2x0 C. for one minute or more and continuously to a heat treatment in an oxidizing atmosphere at a temperature of 700xc2x0 C. to 1300xc2x0 C. for one minute or more without cooling the wafer to a temperature less than 700xc2x0 C. to provide a silicon single crystal wafer wherein a silicon oxide film is formed on the surface, at least one of hydrogen ions and rare gas ions are implanted into the surface via a silicon oxide film of the wafer to form an ion implanted layer, and the resultant wafer is used as the bond wafer, which is then brought into close contact with the base wafer via the silicon oxide film of the bond wafer, followed by delamination at the ion implanted layer by heat treatment.
As described above, in method of producing a bonded SOI wafer, by using the method wherein the wafer produced according to Czochralski method is subjected to heat treatment in a non-oxidizing atmosphere at a temperature of 1100xc2x0 C. to 1300xc2x0 C. for one minute or more and continuously to a heat treatment in an oxidizing atmosphere at a temperature of 700xc2x0 C. to 1300xc2x0 C. for one minute or more without cooling the wafer to a temperature less than 700xc2x0 C. to provide a silicon single crystal wafer wherein a silicon oxide film is formed on the surface, at least one of hydrogen ions and rare gas ions are implanted into the surface via a silicon oxide film of the wafer to form an ion implanted layer, and the resultant wafer is used as the bond wafer, which is then brought into close contact with the base wafer via the silicon oxide film of the bond wafer, followed by delamination at the ion implanted layer by heat treatment (so called ion implantation delamination method), a silicon single crystal wafer having high quality can be used as a bond wafer, and surface condition of the SOI wafer after delamination is good, so that SOI wafer having excellent thickness uniformity can be produced by a relatively easy method.
In that case, the bond wafer delaminated at the ion implanted layer in the above-mentioned method of producing a bonded SOI wafer of the present invention can be used as a new bond wafer.
As described above, in the bond wafer delaminated at the ion implanted layer in the method of producing a bonded SOI wafer of the present invention, grown-in defects in zone at a depth of about 5 to 10 xcexcm or more from the surface are eliminated, and thickness of the thin film delaminated at the ion implanted layer is about one xcexcm at thickest, so that the bond wafer has denuded (low-defect) zone with sufficient depth, even though it is a wafer after delamination of a thin film. Accordingly, even if the surface of the wafer is polished for reuse, sufficient denuded zone remains. Therefore, if it is used as a new bond wafer, and bonded to the base wafer via the oxide film, and thickness of the bond wafer is decreased to produce a SOI wafer, it is not necessary to conduct further heat treatment of the bond wafer before bonding for elimination of grown-in defects. Thereby, a bonded SOI wafer having high quality can be produced efficiently.
Furthermore, the bond wafer delaminated at the ion implanted layer in the above-mentioned method of producing a bonded SOI wafer of the present invention can be used as a new base wafer.
At an inner part (a bulk part) than denuded zone near the surface of the bond wafer after delamination of a thin film, a lot of oxide precipitates are sometimes generated due to influence of heat treatment. In that case, if the wafer is used as a new base wafer, and bonded to the bond wafer via the oxide film, and thickness of the bond wafer is decreased to produce a SOI wafer, the SOI wafer having high performance in gettering of heavy metal impurities or the like can be obtained. In that case, even though a lot of oxide precipitates are generated in a bulk part, a surface-layer part is denuded zone as described above, so that oxide precipitates are never exposed on the surface of the base wafer, and there is no adverse effect to bonding with a bond wafer.
The above-mentioned non-oxidizing atmosphere is preferably argon, nitrogen or a mixed gas of argon and nitrogen.
Because, the atmosphere of argon, nitrogen or a mixed gas of argon and nitrogen can be easily handled and inexpensive.
The above-mentioned oxidizing atmosphere may contain water vapor.
As described above, if the oxidizing atmosphere contains water vapor, an oxidation rate is high, and defects can be eliminated efficiently in quite short time by injection of interstitial silicon. Since the oxide film formed on the bond wafer gets relatively thick, it is suitable for production of SOI wafer having a thick BOX.
In that case, the above-mentioned oxidizing atmosphere can be dry oxygen atmosphere or a mixed gas atmosphere of dry oxygen and argon or nitrogen.
As described above, if the oxidizing atmosphere is dry oxygen atmosphere or a mixed gas atmosphere of dry oxygen and argon or nitrogen, a growth rate of the oxide film is low, and thickness of the oxide film formed on the surface of the bond wafer after heat treatment can be made thin, and thus, it is suitable for production of the SOI wafer having thin BOX.
The thickness of the oxide film formed by the above-mentioned heat treatment in the oxidizing atmosphere is preferably 20 to 100 nm.
As described above, if the thickness of the oxide film formed by the above-mentioned heat treatment in the oxidizing atmosphere is more than 20 nm, COP at a surface-layer part of the bond wafer can be removed sufficiently. If the thickness is 100 nm or less, time necessary for the step can be short even in the case that the formed oxide film needs to be removed. Furthermore, in the case that the SOI wafer is produced according to the above-mentioned ion implantation delamination method, thickness uniformity of the SOI layer gets better, since an absolute value of the deviation in thickness of the oxide film on the surface gets small.
The oxide film can be previously formed on the surface of the wafer before the heat treatment in a non-oxidizing atmosphere.
If such an oxide film is previously formed, the surface of the wafer can be protected so that formation of thermal nitride film on the surface of the wafer due to heat treatment or surface roughness due to etching can be prevented. Therefore, bonding failure when the wafers are bonded can be prevented.
In that case, thickness of the thermal oxide film on the surface of the wafer after the above-mentioned heat treatment in the oxidizing atmosphere is preferably 300 nm or more.
As described above, if the thermal oxide film having a thickness of 300 nm or more is grown, COP on the surface of the wafer can be eliminated by reflow phenomenon of silicon oxide during growth of the oxide film even when the oxide film is previously formed on the surface of the wafer before conducting the heat treatment in the non-oxidizing atmosphere, so that COP on the surface of the wafer can be eliminated more surely.
A silicon single crystal ingot is preferably grown according to Czochralski method with controlling a cooling rate at 1150xc2x0 C. to 1080xc2x0 C. of the single crystal ingot to be 2.3xc2x0 C./min or more.
As described above, if a silicon single crystal ingot is grown according to Czochralski method with controlling a cooling rate at 1150xc2x0 C. to 1080xc2x0 C. of the single crystal ingot to be 2.3xc2x0 C./min or more, a size of grown-in defect gets small. Since the above-mentioned heat treatment is conducted to such a wafer, grown-in defects in a surface-layer part of the wafer can be eliminated or reduced more efficiently. Accordingly, a SOI wafer having a SOI layer with higher quality can be produced in high productivity.
In that case, it is preferable that a silicon single crystal ingot in which nitrogen is doped is grown according to Czochralski method.
As described above, if a silicon single crystal ingot in which nitrogen is doped is grown according to Czochralski method, the size of grown-in defect becomes smaller by nitrogen doping. Further, and the heat treatment is conducted thereto, and thus grown-in defects in a surface-layer part of the wafer can be more efficiently eliminated or removed. Accordingly, a SOI wafer having a SOI layer with higher quality can be obtained in high productivity.
In that case, when growing silicon single crystal ingot in which nitrogen is doped according to Czochralski method, the concentration of nitrogen doped in the single crystal ingot is preferably 1xc3x971010 to 5xc3x971015 atoms/cm3.
Because, 1xc3x971010 atoms/cm3 or more is preferable in order to suppress growth of grown-in defects sufficiently, and 5xc3x971015 atoms/cm3 or less is preferable in order not to prevent formation of single crystal of silicon single crystal.
Furthermore, when the silicon single crystal ingot is grown according to Czochralski method, the concentration of oxygen contained in the single crystal ingot is preferably 18 ppma (JEIDA: Japan Electronic Industry Development Association) or less.
If oxygen concentration is low as described above, growth of crystal defects can be suppressed further, and formation of oxide precipitates at a surface layer can also be prevented.
A bonded SOI wafer produced according to the method of the present invention is, for example, a bonded SOI wafer wherein a SOI layer consists of CZ silicon single crystal wafer, thickness of the SOI layer is 5 xcexcm or less, and 1.3 number/cm2 or less of COP having a size of 0.09 xcexcm or more exist at any region in depth direction of the SOI layer.
As described above, in the bonded SOI wafer of the present invention, there exist very few COP at any region in depth direction of SOI layer, even if thickness of SOI layer is more than 0.5 xcexcm. Furthermore, SOI wafer of the present invention does not need to be subjected to hydrogen anneal or the like after production of SOI wafer, and thus productivity is also high.
According to the present invention, it is possible to eliminate void defects in deeper region efficiently compared with conventional methods, and therefore SOI layer with high quality can be formed. Furthermore, since heat treatment in non-oxidizing atmosphere and heat treatment in oxidizing atmosphere can be conducted in the same batch, the number of the steps in production of SOI does not increase, and thus cost therefor does not increase either. Furthermore, since heat treatment can be conducted without using hydrogen, heat treatment can be conducted with no danger of contamination from the furnace due to hydrogen and explosion. Furthermore, since CZ wafer is used, it can be applied to a wafer having a large diameter as 300 mm or more.

Method of producing a bonded wafer and the bonded wafer


A camshaft phaser is provided for controllably varying the phaser relationship between a crankshaft and a camshaft in an internal combustion engine which includes a camshaft bearing for supporting the camshaft and which defines a mounting bore for mounting the camshaft phaser to the internal combustion engine. The camshaft phaser includes a housing with a gear drive unit disposed within the housing. The gear drive unit includes an input gear member and an output gear member such that the input gear member is attachable to the crankshaft and such that the input gear member is attached to an output shaft of an electric motor. The output gear member is attachable to the camshaft such that rotation of the input gear member by the electric motor causes relative rotation between the crankshaft and the camshaft. The camshaft phaser is disposed between the mounting bore and the camshaft bearing.

Camshaft phasers for varying the timing of combustion valves in internal combustion engines are well known. A first element, known generally as a sprocket element, is driven by a chain, belt, or gearing from the crankshaft of the internal combustion engine. A second element, known generally as a camshaft plate, is mounted to the end of a camshaft of the internal combustion engine. A common type of camshaft phaser used by motor vehicle manufactures is known as a vane-type camshaft phaser. U.S. Pat. No. 7,421,989 shows a typical vane-type camshaft phaser which generally comprises a plurality of outwardly-extending vanes on a rotor interspersed with a plurality of inwardly-extending lobes on a stator, forming alternating advance and retard chambers between the vanes and lobes. Engine oil is supplied via a multiport oil control valve, in accordance with an engine control module, to either the advance or retard chambers, to change the angular position of the rotor relative to the stator, and consequently the angular position of the camshaft relative to the crankshaft, as required to meet current or anticipated engine operating conditions.
While vane-type camshaft phasers are effective and relatively inexpensive, they do suffer from drawbacks such as slow operation at low engine speeds due to low oil pressure, slow operation at low engine temperatures due to high oil viscosity, increased oil pump capacity requirement for the oil pump used to lubricate the internal combustion because the same pump is used to actuate the vane-type camshaft phaser, and the total amount of phase authority provided by vane-type camshaft phasers is limited by the amount of space between adjacent vanes and lobes and may not be sufficient to provide the desired amount of phase authority. For at least these reasons, the automotive industry is developing electrically driven camshaft phasers.
One type of electrically driven camshaft phaser being developed uses a harmonic gear drive unit, actuated by an electric motor, to change the angular position of the camshaft relative to the crankshaft. One example of such a camshaft phaser is shown in United States Patent Application Publication No. US 2012/0312258 A1 to Kimus et al. and U.S. Pat. No. 8,516,983 to David et al., the disclosures of which are both incorporated herein by reference in their entirety. While the camshaft phasers of Kimus et al. and David et al. may be effective, the disclosed camshaft phasers are mounted to the camshafts by bolting the camshaft phasers to the axial end of the camshafts. Some internal combustion engines utilize a camshaft with a timing sprocket secured thereto which is driven by a chain from the camshaft. The timing sprocket may be located axially between camshaft bearings which support the camshaft. The camshaft phasers of Kimus et al. and David et al. are not suitable for such a camshaft, timing sprocket, and camshaft bearing arrangement because bolting the camshaft phasers of Kimus et al. and David et al. to the axial end of the camshaft does not allow proper positioning of the camshaft phaser to connect to the chain to the corresponding sprocket of the camshaft phaser. Consequently, a significant redesign of the internal combustion engine would be necessary in order to mount the camshaft phasers of Kimus et al. and David et al. Such a redesign may be time consuming and costly to accomplish.
What is needed is a camshaft phaser which minimizes or eliminates one or more of the shortcomings as set forth above.

Camshaft phaser actuated by an electric motor


Compositions include modified adenoviruses. Nucleotides, cells, and methods associated with the compositions, including their use as vaccines. Viral vectors using a TET promoter system and methods of producing viruses having the same.

Therapeutic vaccines based on tumor-specific antigens hold great promise as a next-generation of personalized cancer immunotherapy. 1-3 For example, cancers with a high mutational burden, such as non-small cell lung cancer (NSCLC) and melanoma, are particularly attractive targets of such therapy given the relatively greater likelihood of neoantigen generation. 4,5 Early evidence shows that neoantigen-based vaccination can elicit T-cell responses6 and that neoantigen targeted cell-therapy can cause tumor regression under certain circumstances in selected patients.7
One question for antigen vaccine design in both cancer and infectious disease settings is which of the many coding mutations present generate the "best" therapeutic antigens, e.g., antigens that can elicit immunity.
In addition to the challenges of current antigen prediction methods certain challenges also exist with the available vector systems that can be used for antigen delivery in humans, many of which are derived from humans. For example, many humans have pre-existing immunity to human viruses as a result of previous natural exposure, and this immunity can be a major obstacle to the use of recombinant human viruses for antigen delivery in vaccination strategies, such as in cancer treatment or vaccinations against infectious diseases. While some progress has been made in vaccinations strategies addressing the above problems, improvements are still needed, particularly for clinical applications, such as improved vaccine potency and efficacy.