U-bolt toggle latch clamp actuated by power cylinder having piston rod extending at right angles to toggle linkage reaching aligned relation upon U-bolt retraction to clamping position. The toggle linkage is pivotally connected at one end to a fixed reaction pin, at the other end to a U-bolt crosspin and at the center to the actuating piston rod.

It is known in the art to provide a manually actuated toggle latch clamp wherein a U-bolt is drawn into latching engagement by pivotal alignment of toggle linkage through handle actuation. Models 323, 324, 331, 334, 341 and 344 over-center toggle locking pull action U-bolt clamps available from De-Sta-Co Division, Dover Resources Inc, are typical of prior art pull action latch clamps.


Since the majority of conventional organic/inorganic composite materials are obtained by mechanical blending of a silsesquioxane and an organic polymer or other means, it was extremely difficult to control the structure of the composite as a molecular agglomerate. In order to solve such a problem, the invention is to provide a silicon compound represented by Formula (1). This novel silicon compound has a living radical polymerization initiating ability for addition polymerizable monomers of a wide range. In Formula (1), R1 is hydrogen, an alkyl, an aryl, or an arylalkyl; R2 is an alkyl, phenyl, or cyclohexyl; and A is a group having a polymerization initiating ability for addition polymerizable monomers

Polymers have been utilized in various fields not only as general-purpose structure forming materials but also as high value added type materials having high function or performance. Following this, importance in manufacturing a polymer material on the basis of a precise design is increasing. Cage-type silsesquioxane derivatives having a dimethylsiloxane group are watched as an organic/inorganic composite material containing a silsesquioxane as an inorganic component. This is because they are expected to be utilized for precursors of organic/inorganic hybrid materials, low-dielectric materials, optical crystals, materials for forming a liquid crystal display element, and the like, and the reason for this resides in the matter that the silsesquioxane derivatives have a structure closed to silica or zeolite. Then, there are reported cage-type silsesquioxanes in which a hydroxyl group, an epoxy group or a methacryloyloxy group is bound to a dimethylsiloxane group (see Non-Patent Documents 1 to 3). So-called organic/inorganic composite materials between an organic polymer and a silsesquioxane are prepared by utilizing such functional groups. Organic/inorganic composite materials can be obtained by radical polymerizing a cage-type silsesquioxane having a methacryloyloxy group singly or in the co-presence of an acrylic monomer.
In order to optimize a function of a polymer material depending upon the purpose, it is necessary to precisely analyze molecular properties of a polymer or properties as a molecular agglomerate. For that reason, a polymer having a distinct structure must be used. However, conventional organic/inorganic composite materials including the foregoing composite materials do not contain a structure-controlled polymer as an organic component. Since the majority of organic/inorganic composite materials are obtained by mechanical blending of a silsesquioxane and an organic polymer or other means, it was extremely difficult to control the structure of the composite as a molecular agglomerate. Then, it was attempted to control the structure of the polymer by using a polymerization initiator. Non-Patent Document 4 discloses that an α-haloester group is a good initiator of living radical polymerization for a styrene based monomer and a methacrylic acid based monomer. However, any silsesquioxane derivative having an α-haloester group has not been known so far.    [Non-Patent Document 1]
J. Am. Chem. Soc., 122 (2000), 6979    [Non-Patent Document 2]
Chemistry of Materials, 8 (1996), 1592    [Non-Patent Document 3]
Macromolecules, 29 (1996), 2327    [Non-Patent Document 4]
Chem. Rev., 101 (2001), 2921
An object of the invention is to provide a novel silicon compound having a living radical polymerization initiating ability for addition polymerizable monomers of a wide range and a polymer obtained by using the same, thereby solving the foregoing problems regarding the conventional organic/inorganic composite materials.


A method of forming a film pattern includes the steps of forming a bank for partitioning a pattern forming area including a first pattern forming area and a second pattern forming area having an intersection with the first pattern forming area and divided in the intersection into sub-areas, disposing a functional liquid to the first pattern forming area to form a first film pattern, and disposing a functional liquid to the sub-areas to form second film patterns, executing a lyophobic process on the entire surface of a substrate including the first film pattern, the second film patterns, and the bank, weakening the lyophobicity on the substrate while selectively maintaining the lyophobicity on predetermined positions of the respective second film patterns formed in a divided condition after executing the lyophobic process, stacking a cap layer on the first film pattern and the second film patterns after weakening the lyophobicity, removing the lyophobicity in the predetermined positions of the respective second film patterns formed in the divided condition after stacking the cap layer, and forming a conductive film between the predetermined position of one of the second film patterns and the predetermined position of another of the second film patterns to electrically connect the second film patterns formed in the divided condition.

1. Technical Field
The present invention relates to a method of forming a film pattern, an active matrix substrate, an electro-optic device, and an electronic apparatus.
2. Related Art
A semiconductor device composed of a circuit wiring formed of a conductor thin film (film pattern) disposed therein, a thin film such as an insulating film covering the circuit wiring, and a thin film made of semiconductor all stacked on a substrate has been known from the past. As an efficient method of forming a thin film in such a semiconductor device, a droplet ejection method (inkjet method), in which droplets of a functional liquid containing a thin film material or the like as dispersoid is ejected from a droplet ejection head, and the landed functional liquid is dried to remove the dispersion medium thereby forming the thin film, is known to the public (see, for example, JP-A-11-274671).
In forming a film pattern by the droplet ejection method, banks for partitioning the pattern forming areas are formed, and the functional liquid is ejected towards the pattern forming areas partitioned with the banks and having recessed shapes. And, the film pattern is formed after drying the functional liquid ejected to the pattern forming areas.
In recent years, source wiring (film pattern) and gate wiring (film pattern) both electrically connected to a plurality of thin film transistors provided to an active matrix substrate are formed using the droplet ejection method described above.
The active matrix substrate is provided with the source wiring and gate wiring, which are electrically connected to each of the thin film transistors, disposed on the substrate in a lattice manner with each other, and typically has a structure in which the source wiring and the gate wiring are formed on different surfaces via an interlayer insulating film or the like.
And, since the source wiring and the gate wiring are made of metal materials, leak current might be caused by diffusion of metallic ions, which might prevent the transistor from operating preferably. Therefore, in some technologies, the diffusion of the metallic ions described above is prevented by stacking a cap layer, which is composed of Ni or the like having lower conductivity than the metal materials forming the source wiring and the gate wiring, on each wiring.
Incidentally, an active matrix substrate, which can be formed with a simplified wiring forming process of forming the gate wiring and the source wiring on the same surface in the same manufacturing process, can also be considered in contrast with the active matrix substrate having the gate wiring and the source wiring formed via the interlayer insulating film as the stacked structure. In this active matrix substrate, for example, the source wiring is formed so as to be divided by the gate wiring in intersections between the gate wiring and the source wiring. Further, the active matrix substrate is provided with conductive sections (conductive films) for connecting the source wiring thus divided.
Still further, an active matrix substrate, which is provided with the cap layer for preventing the diffusion of the metallic ions described above and has a structure of divided source wiring (film pattern), can also be considered.
However, if the cap layer is disposed on the gate wiring and the source wiring divided by the gate wiring, which are formed in the wiring forming areas (pattern forming areas) partitioned with the banks, using the droplet ejection method, the material forming the cap layer wets and extends on the wiring forming areas to form the cap layer covering the entire surface of the gate wiring and the source wiring. Note here that, as described above, the conductivity of the cap layer is lower than those of the metal materials forming the gate wiring and the source wiring. Therefore, in order for providing preferable electrical connection to the divided source wiring, it is necessary to remove the cap layer covering the source wiring to degrade the conductivity for connecting the divided source wiring by forming the conductive sections directly on the source wiring thus exposed.
However, if the process of removing the cap layer is required, as described above, in forming the conductive sections connecting between the divided pieces of the source wiring, it becomes difficult to simplify the process of forming the source wiring, thus contributing to preventing enhancement of productivity.

Method of forming film pattern, active matrix substrate, electro-optic device, and electronic apparatus


This invention provides methods and compositions for capturing circulating tumor cells (CTCs) as well as various divergent CTC phenotypes using seprase-specific affinity reagents. Methods of analyzing CTCs and assessing their metastatic potential in vivo and in vitro are also disclosed.

Metastasis to distal organs causes the majority of cancer deaths. Circulating tumor cells (CTCs) originate from a primary tumor and initiate a metastasis cascade that ultimately results in metastatic tumors appearing at distal sites. See Sun et al. (2011) Circulating tumor cells: advances in detection methods, biological issues, and clinical relevance, J. Cancer Res. Clin. Oncol. 137:1151-1173. Several genetic, morphological, immunological and physio-logical tests may be used to identify CTCs. See Id., and Man, et al. (2011) Currently used markers for CTC isolation—advantages, limitations and impact on cancer prognosis, J. Clin. Exper. Pathol. 1:1. Because the number of CTCs in peripheral blood even in patients with advanced metastatic disease, is extremely low compared to the number of normal blood cells (one in a billion), positive selection is a commonly used method for enumeration and isolation of CTCs. CTCs may be captured by using an antibody directed against the epithelial cell adhesion molecule (EpCAM) expressed within the cell membrane of many CTCs. Following selection, the CTCs are ultimately identified by immunostaining using a combination of reagents targeting live cells, leukocyte-specific markers and tumor-specific markers. For example, the FDA-approved CELLSEARCH® CTC test (Veridex, LLC, Raritan, N.J.) detects CTCs using anti-EpCAM monoclonal antibodies poised on paramagnetic beads, followed by CTC identification using DAPI, cytokeratins (CK) and CD45. See Hayes, D. F. and Smerage, J. (2008) Is there a role for circulating tumor cells in the management of breast cancer? Clin. Cancer Res., 14:3646-3650; Cristofanilli, M., et al. (2004) Circulating tumor cells, disease progression, and survival in mestatic breast cancer. N. Engl. J. Med., 351:781-791. However, reports have suggested that this approach does not capture cells with low or no expression of EpCAM; and the assay shows poor sensitivity and specificity for metastatic cases. See Lu, J. et al. (2010) Isolation of circulating epithelial and tumor progenitor cells with an invasive phenotype from breast cancer patients. Intl. J. of Cancer, 126:669-683; Sieuwerts, A. M. et al. (2009) Anti-epithelial adhesion molecule antibodies and the detection of circulating normal-like breast tumor cells. J. Natl Cancer Inst, 101:61-66. However, cells with low or no EpCAM expression are also likely to be highly clinically significant. It has been suggested that tumor cells expressing invasive phenotypes down-regulate and lose their epithelial antigens (including EpCAM) in a process called the epithelial-to-mesenchymal transition (EMT). Mego, M. et al. (2010) Molecular mechanisms of metastasis in breast cancer-clinical applications. Nat. Rev. Clin. Oncol., 7:693-701; Brabletz, T. et al. (2005) Invasion and metastasis in colorectal cancer: Epithelial-mesenchymal transition, mesenchymal-epithelial transition, stem cells and Beta-catenin. Cell Tissues Organs, 179:56-65; Raimondi, C. et al. (2011) Epithelial-mesenchymal transition and stemness features in circulating tumor cells from breast cancer patients. Breast Cancer Res, 130:449-455. It has also been suggested that CTCs contain sub-populations with a continuum of phenotypes besides the epithelial one. Therefore, attempts to capture all CTC sub-populations (especially invasive ones that have little if any EpCAM expression) by targeting EpCAM alone may be ineffectual. Sabile, A. et al. (1999) Efficiency of Ber-EP4 antibody for isolating circulating epithelial tumor cells before RT-PCR detection. Am. J. Clin. Pathol., 112:171-178; Thurm, H., et al. (2003) Rare expression of epithelial cell adhesion molecule on residual micrometastatic breast cancer cells after adjuvant chemotherapy. Clin. Cancer Res., 9:2598-2604. This is further substantiated by the observation that one gram of an epithelial-based tumor can release up to 106 cells per day. Butler, T. P. et al. (1975) Quantitation of cell shedding into efferent blood of mammary adenocarcinoma. Cancer Res., 35, 512-516. While clearly not all of these cells possess the ability to initiate metastasis, some rare and elusive sub-populations do.
It may be possible to select CTC sub-populations using a combination of antibodies, e.g., CD45 antibody combined with antibodies for various tumor makers, e.g., HER2 or estrogen receptor. Exemplary tests are offered by BioCept, Inc. (San Diego, Calif.). However, the antibody cocktails typically used in such tests are generated using immortalized cells lines that may not truly recapitulate the continuum of changes occurring in CTCs released from patient tumors. Pecot, C. V. et al. (2011) A novel platform for detection of CK+ and CK− CTCs. Cancer Discovery, 1(7):580-586. Accordingly, there is a need for a method able to effectively detect and target rare invasive sub-populations of CTCs present in patient samples.

In vitro capture and analysis of circulating tumor cells


A discrete cosine transform circuit for processing an 8.times.8 block and two 4.times.8 blocks, comprising a first shuffle circuit for performing a first one-dimensional discrete cosine transform, a second shuffle circuit for performing a second one-dimensional discrete cosine transform, a first multiplexing circuit for selecting inputs to input terminals of adders/subtracters in the second shuffle circuit according to an input block size, ROMs for storing a data table therein to support all cosine matrices to perform a matrix multiplication operation based on the input block size, and a second multiplexing circuit for selecting a desired one of outputs from the ROMs according to the input block size. Therefore, according to the present invention, common and different parts for the process of two different block sizes are all implemented on a single circuit and controlled to process forward and inverse discrete cosine transforms.

1. Field of the Invention
The present invention relates to a forward/inverse discrete cosine transform (referred to hereinafter as DCT) circuit using a distributed arithmetic processing manner.
2. Description of the Prior Art
Generally, conventional 8.times.1 DCT associated techniques relate to a forward/inverse DCT circuit using a distributed arithmetic processing manner. One example of such a conventional 8.times.1 DCT associated technique is disclosed in U.S. Pat. No. 5,357,453. The '453 patent shows a method for efficiently implementing a DCT circuit which is capable of converting a video signal into a frequency signal in real time.
FIG. 1 shows a conventional one-dimensional DCT circuit which performs forward and inverse 8.times.1 DCT operations using the distributed arithmetic processing manner. The operation and construction of the conventional 8.times.1 DCT circuit are disclosed in detail in the '453 patent.
The 8.times.1 DCT implementation in FIG. 1 can be extended to an 8.times.8 DCT. An example of such an 8.times.8 DCT implementation is shown in block form in FIG. 2. The representative method of 8.times.8 DCT implementation is to sequentially perform the 8.times.1 DCT operation with respect to an input 8.times.8 block in the order of row, a row/column substitution operation and the 8.times.1 DCT operation with respect to the input 8.times.8 block in the order of column. Of course, a circuitry is provided to perform the row/column substitution operation between the 8.times.1 DCT operation in the order of row and the 8.times.1 DCT operation in the order of column. As a result, the 8.times.8 DCT implementation is provided with two 8.times.1 DCT circuits, each of which is shown in FIG. 1, and a row/column substitution circuit, as shown in FIG. 2.
The 8.times.8 inverse DCT (referred to hereinafter as IDCT) operation is performed in the reverse order of the 8.times.8 forward DCT operation. Namely, the 8.times.8 IDCT operation is performed by sequentially carrying out the 8.times.1 IDCT operation with respect to DCT coefficients in the order of column, the row/column substitution operation and the 8.times.1 IDCT operation with respect to the DCT coefficients in the order of row. As a result, original pixels are restored.
The 8.times.8 DCT implementation requires no additional circuitry in performing the forward and inverse 8.times.8 DCT operations, because the conventional 8.times.1 DCT circuits of the same construction support both the forward and inverse 8.times.8 DCT operations.
As mentioned above, the two-dimensional 8.times.8 DCT operation is performed by using the conventional 8.times.1 DCT circuit. The compression efficiency of an image compression coding process is determined according to the size of a block to be DCT-processed. Namely, in the case where the block is small in size, it is readily processed but reduced in the compression efficiency. On the contrary, in the case where the block is large in size, it is increased in the compression efficiency but difficult to process. In other words, a larger image size is desirable in view of the compression efficiency, but has a difficulty in processing.
The sizes of blocks to be DCT-processed are 2.times.2, 4.times.4, 8.times.8, 16.times.16 and 32.times.32. The 4.times.4 and 8.times.8 block sizes among the above-listed block sizes are widely used in the standard compression/expansion coding process. In particular, the JPEG, H.261 AND MPEG standards prescribe the process of only 8.times.8 block.
However, in the digital video cassette recorder (referred to hereinafter as DVCR) standards, the size of an input block to be DCT-processed is determined according to a block motion. Namely, in the case where little block motion is present, an 8.times.8 DCT is processed. However, in the case where a large block motion is present, two 4.times.8 DCTs are processed by performing addition and subtraction operations with respect to two vertically adjacent pixels in block. Such a DCT process of different block sizes is performed for enhancing the coding efficiency and picture quality. However, the conventional 8.times.8 DCT processing circuit requires a large number of additional components to process two 4.times.8 DCTs.

Discrete cosine transform circuit for processing an 8.times.8 block and two 4.times.8 blocks

Electronics and Telecommunications Research Institute


Assembling a multi-component baseball bat includes disposing a rigid sleeve coaxially over a portion of an elongate composite handle. The rigid sleeve encircles a second end of the handle and extends toward a first end of the handle. A ring is positioned near a second end of a bat barrel. A first end of the bat barrel is inserted into the second end of the handle; the first end of the bat barrel being secured within the second end of the handle. An illustrative bat includes an elongate composite handle and an elongate barrel, each having opposite first and second ends. The first end of the barrel is disposed within the second end of handle. A mechanism secures the first end of the barrel within the second end of the handle. A rigid sleeve encircles the second end of the handle, extending towards the first end thereof.

The present invention relates to baseball and softball bats. More particularly, the present invention relates to a multi-component bat and a related assembly process.
Baseball and softball are very popular sports in the United States, Mexico, Cuba, Japan and elsewhere. Due to the competitive nature of the sports, players are constantly seeking ways of improving their performance. An important aspect of baseball and softball is the ability to effectively hit the ball. Aluminum (metal) bats are allowed in baseball amateur play from Little League to College levels. Metal bats are also typically used in slow and fast pitch softball. Such bats are advantageous over wood bats in that they do not break and splinter like wood bats and thus can be repeatedly used with consequent cost savings. Metal bats also have a larger optimal hitting area or power zone (commonly referred to as the "sweet spot") than wood bats. Furthermore, the ball comes off a metal bat faster than a wood bat resulting in longer hits.
However, metal bats have certain disadvantages. Metal bats vibrate upon impact and may send painful vibrations into the hands and arms of the batter if the ball is not hit within the power zone of the bat. Metal bats, particularly aluminum bats, may also dent or otherwise deform due to forceful impacts with the ball. Metal bats also emit an undesirable high-pitched metallic sound, as opposed to the traditional sound heard when a wood bat contacts the ball.
Various attempts have been made to overcome the problems associated with metal bats. Some attempts have been to coat or wrap the exterior of the metal bat with materials such as carbon reinforcing fibers to enhance batting performance. These externally wrapped bats have been found to be aesthetically unpleasant and lacking in significant improvement. Other attempts have been made to insert internal layers or compartments within the metal bat to improve performance. Bats have been devised that incorporate both metal and composite materials. Such designs include utilizing multiple-layered graphite inserts to provide durability and flexibility to the bat, tubular coiled spring steel inserts to improve the spring-board effect when the ball contacts the bat, and pressurized air chambers within the bat. Bats that incorporate composite materials tend to be much lighter than metal bats. While providing benefits, these designs also have drawbacks. Some designs are very expensive to manufacture and are prone to structural failure. The composite sheaths break down over time, the bats are subject to premature longitudinal cracks in the barrel of the bat and damage is created at an interface of the metal and composite materials due to differences in the impact absorption and resistance characteristics of the materials.
Accordingly, there is a need for a bat which enhances the performance of the bat and overcomes the disadvantages previously experienced with metal bats. The present invention fulfills these needs and provides other related advantages.

Multi-component bat and assembly process


A sensor diagnostic system comprises first, second, and third dosing agent sensors and a control module. The first, second, and third dosing agent sensors indicate whether a dosing agent is present at first, second, and third volumetric levels of a dosing agent tank, respectively. The second volumetric level is greater than the first volumetric level and the third volumetric level is greater than the second volumetric level. The control module selectively diagnoses a sensor fault in at least one of the first, second, and third dosing agent sensors based on the indications of the first, second, and third dosing agent sensors.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
To meet nitrogen oxide (NOx) emission requirements for a vehicle with a diesel engine, urea may be injected into an exhaust stream. The urea is stored in a tank that may be similar to a conventional fuel tank. Since the emissions impact of running out of urea is severe, correct urea level indication is required to inform the driver. For example, the vehicle may be required to operate in a limp home mode when the urea runs out.
Several unique characteristics of urea delivery systems make urea level sensing systems and on board diagnostic (OBD) monitoring different than fuel level monitoring systems. For example, urea freezes at low temperatures. In addition, the volume of urea consumed per mile may be as low as 5 gallons for 4000 miles. Level sensing systems may be required to independently verify range readings from the sensor.

Systems and method for monitoring urea level


A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third semiconductor region of the second conductivity type formed on the first semiconductor region; a fourth semiconductor region of the first conductivity type formed on a portion of the surface of the third semiconductor region; a control electrode provided via an first insulating film in a groove formed in contact with the fourth semiconductor region, the third semiconductor region, and the first semiconductor region; a first main electrode electrically connected to the first semiconductor layer; a second main electrode forming a junction with the third and fourth semiconductor region; and a fifth semiconductor region of the second conductivity type. The fifth semiconductor region is formed in contact with the first insulating film, the first semiconductor region, and the second semiconductor region. The bottom face of the fifth semiconductor region is deeper than the bottom face of the control electrode. Alternatively, the fifth semiconductor region may be spaced apart from the first insulating film.

1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device of the trench gate structure based on the superjunction structure.
2. Background Art
Circuits such as switching power supplies and inverters are based on power semiconductor devices including switching devices and diodes. Typically used are vertical power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a source, a gate, and a drain arranged vertically. Power semiconductor devices are required to have such characteristics as high breakdown voltage and low on-resistance (RON). The on-resistance (RON) of a vertical power MOSFET greatly depends on the electric resistance of the conduction layer (hereinafter referred to as drift layer) portion. The doping concentration determining the electric resistance of the drift layer cannot be increased above the limit corresponding to the breakdown voltage of the pn-junction formed by the base region and the drift layer. Thus there is a tradeoff between the device breakdown voltage and the on-resistance (RON) which depend on the device material. Improving this tradeoff has been a serious problem for vertical power MOSFETs.
Vertical MOSFETs to solve this problem include those of the superjunction structure. Instead of the n-type layer in the conventional structure, the superjunction structure has p-pillar regions and n-pillar regions alternately buried in the drift layer portion. By equalizing the amount of impurities contained in the p-pillar region and the n-pillar region, the drift layer is artificially made a non-doped layer. During the off-time, a horizontally spreading depletion layer maintains high breakdown voltage. During the on-time, a current is allowed to flow through the n-pillar region doped with high concentration. Thus, the superjunction structure has realized a device with a high breakdown voltage and a low on-resistance (RON) over the limit of the material.
Actually, the lateral period of the superjunction structure needs to be decreased for improving the tradeoff between the breakdown voltage and the on-resistance (RON) using the superjunction. Furthermore, the lateral period of the MOS gate structure, or the so-called cell pitch, also needs to be decreased simultaneously for reducing the overall on-resistance (RON) of the device.
In response to these requirements, a vertical MOSFET has been proposed (U.S. Pat. No. 5,216,275), where the MOS gate structure is based on the trench gate structure. For example, a vertical MOSFET of the trench gate structure shown in FIG. 4 of the '275 patent has a superjunction structure where n-pillar regions 6 and p-pillar regions 7 are alternately buried in a drift layer 5. A control gate electrode G is formed via a gate insulating film 1 in the trench provided in the p-base region 3. During the on-time, a channel is formed in the p-base region 3 being in contact with the gate insulating film 1, and a current flows from the source region 2 to the drain region 4.
In the trench gate structure described above, the trench bottom needs to be formed as deep as or deeper than the p-base region 3 for ensuring the channel. When the trench gate bottom is formed deeper than the p-base region 3, the electric field is maximized at the trench gate bottom during application of high voltage. Hence avalanche breakdown due to high voltage occurs at the trench bottom. Holes generated by the avalanche breakdown flow into the p-base region 3 via the MOS channel. Because of high release resistance of the channel against holes, holes are not rapidly released, and the avalanche withstand capability is decreased. Furthermore, carriers generated by the avalanche breakdown impinge into the gate insulating film 1, thereby decreasing the reliability of the gate insulating film.
Thus, there is a problem that vertical MOSFETs of the trench gate structure have lower avalanche withstand capability and hence lower reliability of the gate insulating film than lateral MOSFETs.


An adaptive digital power control system is disclosed, which implements a digitally controlled, near real-time algorithm to accommodate multiple loop current mode controls for low voltage, high performance computing system power needs. For example, an adaptive digital power control system that is implemented with an FPGA to generate low voltages for high performance computing systems is disclosed, which includes a current and voltage loop compensation algorithm that enables the adaptive digital power control system to dynamically compensate for high current transients and EMI-related noise. The current and voltage loop compensation algorithm uses a combination of linear predictive coding and Kalman filtering techniques to provide dynamic current and voltage compensation, and implement a feed-forward technique using knowledge of the power system's output parameters to adequately adapt to the system's compensation needs. More specifically, an adaptive digital power control system is disclosed, which includes a power stage for generating a plurality of low voltages, a multiplexer and A/D converter stage for receiving and converting the plurality of low voltages and a plurality of associated currents to a plurality of digital voltage and current signals, a current and voltage compensation algorithm stage for receiving the plurality of digital voltage and current signals and generating a plurality of digital voltage and current compensation control signals using linear predictive coding, Kalman filtering and feed-forward estimation techniques, and a digitally controlled pulse width modulator stage for receiving the plurality of digital voltage and current compensation control signals and controlling the duty cycles of a plurality of transistor switching devices in the power stage. Thus, the adaptive digital power control system can dynamically compensate for high current transients and EMI-related noise generated in low voltage power systems for high performance computing systems.

Modern high performance computing systems typically require the use of relatively low unit voltage levels (e.g., typically between 1.0V and 1.8V) as core voltages for their high performance processors operating in the GHz range. The primary aim of this requirement is to minimize the power consumption of the computing systems involved. However, a significant drawback of this requirement is that certain costs are incurred (in terms of dynamic system performance) due to the use of these low voltage levels at such high operating frequencies. For example, the use of low core voltages for processors operating in the GHz range results in the generation of high current transients (e.g., on the order of hundreds of amps per microsecond) and increased noise (e.g., caused by Electromagnetic Interference or EMI) in the power systems involved. Consequently, the high current transients and increased EMI-related noise generated in today's high performance computing systems can severely limit the dynamic response times of the power systems used. Thus, unless these high current transient and noise problems are properly compensated for and resolved, the stability, efficiency and accuracy of the existing high performance computing systems can be severely compromised. More importantly, unless these high current transient and EMI-related noise problems are successfully resolved, the capabilities of the existing high performance computing systems in terms of meeting the stringent requirements of high reliability applications (e.g., very long space missions, smart weapons, missiles, etc.) are in doubt. Therefore, it would be advantageous to have a solution to the problems of high current transients and EMI-related noise generated in the low voltage power supplies of today's high performance computing systems. As described in detail below, the present invention provides an adaptive digital power control system that resolves the high current transients and EMI-related noise problems and other similar noise problems encountered with today's high performance computing systems.


A data storage system for storing data for a host processor includes physical data storage devices each having data storage attributes and an outboard storage manager. The outboard storage manager is operable with the physical data storage devices for presenting to the host processor a virtual data storage image having a desired data storage attribute for a particular data storage application by organizing the physical data storage devices in an arrangement suitable for providing the desired data storage attribute irrespective of the data storage attributes of the physical data storage devices such that the combined physical data storage device arrangement emulates the virtual data storage image. The outboard storage manager is operable to transfer data between the host processor and the organized physical data storage device arrangement via the virtual data storage image.

Data storage subsystems include a plurality of different types of data storage devices for storing data for host processors. Each type of data storage device has different storage attributes that are suitable for storing data having certain data attributes. Data storage management systems route the data from the host processors to selected data storage devices. The data storage devices for storing the data are selected as a function of the data attributes. Typically, data storage management systems make available to the host processors the actual data storage devices which are to store the data. That is, the data is directly routed from the host processors to the selected data storage device.
A problem with this arrangement is that a selected data storage device may be unavailable at the time a host processor needs to access the selected data storage device or the data storage subsystem may not even have the selected data storage device. Another problem with this arrangement is that none of the data storage devices in the data storage subsystem may have the storage attributes suitable for storing the data.

This patent is subject to a terminal disclaimer.

Outboard data storage management system and method


Even in an apparatus connected to another apparatus which periodically transmits a command, a mode transition such as transition to a power saving stand-by mode can be performed. A mode change for Bluetooth communications and a mode change in a stand-by state are performed in cooperation with each other to efficiently switch between stand-by modes.

1. Field of the Invention
The present invention relates to an apparatus having a communication function, a method of controlling the apparatus, and a storage medium storing a program for controlling the apparatus.
2. Related Background Art
A system is known which has an intelligent terminal such as a personal computer connected to a facsimile apparatus via a wired interface such as a bidirectional parallel port (in conformity with IEEE1284), e.g., Centronics and a universal serial bus (USB).
In such a system, the intelligent terminal takes the initiative in the system control and data transfer by sending a command to the facsimile apparatus which returns a response.
Since such a facsimile apparatus is required to return a response to a command sent from the intelligent terminal, the facsimile apparatus connected to the intelligent terminal is controlled so as not to enter a power saving mode.
In the above-described system, since the facsimile apparatus connected to the intelligent terminal is controlled so as not to enter the power saving mode, the power is consumed wastefully.
Further, since a response to a command from the intelligent terminal is always required to be returned, even changing the mode during the stand-by mode has not been taken into consideration.

Apparatus with communication function, method of controlling apparatus, and storage medium storing program for controlling apparatus


A method and system for automated discovery of logical network elements in a communications network speeds up and reduces the cost of discovering network elements and mapping network topology of network inter-connections. The method comprises the steps of building a cache of protection mechanisms in the communications network, building a network graph based on physical links of the communications network, traversing the network graph, comprising the step of, at each vertex of the network graph, determining whether there is a deterministic path that leads to a next vertex of the network graph, performing a depth first search on the network graph to determine connected components of the network graph, and creating the logical network elements based on the connected components of the network graph.

1. Field of the Invention
The present invention relates to a system and method for automatically discovering network elements and mapping network topology of network inter-connections.
2. Description of the Related Art
As telecommunications services have proliferated, telecommunications networks have become increasingly complex. Today, telecommunications networks, using technologies such as Synchronous Optical Network (SONET), Dense Wavelength Division Multiplexing (DWDM), Asynchronous Transfer Mode (ATM), Ethernet, etc., may extend world-wide and may include thousands of network elements (NEs). One important aspect of managing such a network is the discovery of NEs (as they are added or removed from the network) and the mapping of the network topology (as inter-connections among NEs are added, removed, or changed).
Conventionally, the discovery of NEs and the mapping of the network topology is done manually, with operators having to determine and enter the identity of network elements and the topology of the network inter-connections. This is an expensive and time-consuming process. In a large network, which may include thousands of network elements, this manual process may take days to complete. A need arises for a technique by which network elements may be discovered and network topology mapped that is faster and less expensive than prior art techniques.
Among network topology configurations that are common are elements such as rings and chains. These elements are made up of defined linking patterns among network elements. Conventionally, network users manually defined rings and chains to provide paths through the network. This manual creation is an expensive and time-consuming process, especially in a large network, which may include thousands of network elements. In addition, these rings and chain definitions were not stored in a way that made them useful for network management. A need arises for a technique by which network elements, such as rings and chains, may be defined that is faster and less expensive than prior art techniques and that makes them useful for network management.

Automatic discovery of logical network elements from existing links in a network


The invention relates to an engine arrangement that increases the degree of freedom of the engine state sensor while decreasing the size of the engine body. More specifically, the engine is formed with a chamber for housing a valve train and serving dually as a return oil path of the lubricating oil after having lubricated the valve train. The engine includes an oil temperature sensor partially exposed on one side of a cylinder block and an exhaust pipe partially exposed on the opposite side of the cylinder block.

Oil temperature sensors for detecting temperature of lubricating oil in an internal combustion engine are conventionally used to detect temperature of lubricating oil within a lubricating oil passage or within an oil pan. For example, in an internal combustion engine disclosed in Japanese Patent No. 2000-213326, an oil return passage for returning the oil which has lubricated a valve train is formed by penetrating a cylinder block. An intermediate portion of the oil return passage bulges downward forming an oil reservoir and a detection unit of a temperature sensor which has been threadedly inserted from a side wall of the cylinder block faces the oil reservoir.
In the above-described system, a timing chain chamber, which is a housing chamber for housing a timing chain for driving a camshaft of a valve train, is formed by penetrating the cylinder block in parallel with the oil return passage. For this reason, there is a drawback that the cylinder block becomes large-sized by a portion corresponding to the oil return passage to be formed, and further the temperature sensor is to be arranged so as to avoid the timing chain chamber having comparatively large width in the circumferential direction with the cylinder axis as the center while excluding interference with and influence of peripheral members to be arranged around the cylinder block such as exhaust pipes. Therefore, layout of the temperature sensor has possibly been restricted.

Internal combustion engine with oil temperature sensor


A natural white balance is achieved in images that are captured while emitting a flash. The white balance of an image is adjusted using a WB adjustment portion and a mixture ratio calculation portion estimating a mixture ratio of an external light component and a flashed light component that are present in an image captured with emitting a flash, from the image obtained that is captured while emitting a flash and an image signal that is obtained without emitting a flash. Further, an external light WB coefficient determination portion determines an WB coefficient for the external light, a flashed light WB coefficient setting portion sets a WB coefficient for the flashed light, and a WB processing portion continuously performs WB processing on the image captured while emitting a flash by using the mixture ratio as an interpolation ratio.

1. Field of the Invention
The present invention relates to technologies for adjusting the white balance of a captured image. In particular, it relates to technologies for adjusting the white balance of an image that has been captured by an image capture device that is provided with an illumination portion (flash emission device) that allows the flashed light to be controlled.
2. Description of the Related Art
Image capture devices such as digital still cameras use a flash emission device in order to illuminate an object to be captured with a flashed light as a helper light, when the light that is reflected from the object to be captured during imaging is weak. Image capture devices may also employ a flash emission device as backlight correction in order to illuminate a flashed light on a person (captured object) to brighten the person, and in doing so keep the person from appearing dark when that person is imaged against a bright background such as sunlight.
On the other hand, there are instances when capturing an image of an object to be captured after a flash emission device has emitted a flashed light results in an photograph (captured image) with an unnatural color balance with respect to the captured object image with light (illumination light) due to the lighting originally present in the image capture environment (the captured object image on the captured image that is obtained from the illumination light that is reflected off of the captured object) and the captured object image due to the flashed light (that captured object image on the captured image that is obtained from the flashed light that is reflected by the object to be captured). This is because there is a difference in the color temperature between the illumination light that originally illuminates the captured object and the flashed light.
Image capture devices such as digital still cameras generally perform processing known as white balance (WB) adjustment (hereinafter, WB adjustment). An example of this would be a case in which the object to be captured is illuminated by lighting with a low color temperature, such as an incandescent lamp, in which case adjustment is performed to relatively weaken the red (R) component signal (image data values) of the captured image data, and conversely, to strengthen the blue (B) component signal (image data values), in order to express white in the object to be captured as white on the captured image. WB adjustment can remove the effects of the illumination light, so that white objects are white objects in the captured image. Methods for finding the color temperature of the lighting include using a color sensor, estimating from the color distribution of the image data that are captured (captured image data), and selection by the user. When the image capture device captures an image using a flashed light, it can perform WB adjustment in accordance with the color temperature of the flashed light, which is already known.
However, when an image is captured using a flashed light, in many situations light other than the flashed light, that is, the illumination light (external light) originally present in the image capture environment, blends with the flashed light, and together the two illuminate the object to be captured. For this reason, performing WB adjustment based on the flashed light results in natural correction for objects that are brightly illuminated by the flashed light, however, appropriate WB adjustment is not performed for objects that are poorly lit by the flashed light or objects that are not illuminated by the flashed light at all (such as background), and this leads to an unnatural captured image (areas originally white become colors other than white in the captured image).
The image capture device disclosed by Japanese Patent Publication 3540485 is an example of a conventional image capture device for solving this problem. Japanese Patent Publication 3540485 discloses a configuration for an image capture device (electric still camera) that finds, per pixel, the ratio of pixel values of two images that are captured with and without a flashed light and determines the contribution of the flashed light based on the value of this ratio, and then, based on the results of this determination, selects a WB coefficient for the external light, a WB coefficient for the flashed light, and WB coefficients between these two, and performs WB adjustment. When "a" is the pixel value of the image captured with the emission of a flash and "b" is the pixel value of the image captured without the emission of a flash, the ratio (flashed light contribution)=a/b. With the device of Japanese Patent Publication 3540485, when a/b≈1 it is determined that that pixel is in a region not reached by the flashed light, and when a/b>>1 it is determined that that pixel is in a region that is sufficiently reached by the flashed light. Japanese Patent Publication 3540485 further discloses that by restricting the variability of the WB coefficient for each pixel, it is possible to keep the WB coefficient from changing suddenly between pixels even when the captured object has moved between the capturing of the two images.
However, the structure of the conventional image capture device has the following three problems.
The first is that with the conventional image capture device, a color pseudo-border occurs in the region where the WB coefficients are switched.
In Japanese Patent Publication 3540485, a WB coefficient for the external light, a WB coefficient for the flashed light, and a WB coefficient between the two are "selected" based on the results of "determination" of the flashed light contribution, but this intermediate WB coefficient must be a "discrete value." Thus, a color pseudo-border occurs in the region in which the WB coefficient is switched when the ratio of both the external light and the flashed light are continuously altered while irradiating the object to be captured. This is because the flashed light contribution is "non-linear." This is explained below.
First, the flashed light contribution is shown to be "non-linear."
For each pixel, when C is the external light illumination, B is the flashed light illumination, R is the reflectance, and "a" and "b" are the pixel values of pixels with and without the emission of the flashed light, the pixel values a and b become:a=(C+B)·R, b=C·R and the flashed light contribution K isK=a/b=1+B/C. Thus, the flashed light contribution K is a "non-linear" parameter (value range=1 to ∞) in which the value increases sharply the smaller the external light illumination C.
Thus, to perform linear WB adjustment with respect to a change in the external light illumination C, it is necessary to partition more narrowly the smaller the range of values of the external light illumination C, and a large number of values must be readied in a table or the like.
Further, not only it is necessary to partition based on the range of values for the external light illumination C, but there are various types of external lighting (clear skies, fluorescent light, light bulbs, etc.), and a WB coefficient must be readied for each combination thereof, and thus significant circuitry and memory are needed.
In instances where the object to be captured has moved, attempting to continuously change the WB coefficient in the regions where it has moved (regions on the captured image) and the regions where it has not moved (regions on the captured image) similarly requires many WB coefficients.
As illustrated above, it is not realistic to solve the problem by increasing the number of WB coefficients, and thus intermediate WB coefficients must be made "discrete values," resulting in color pseudo-borders in regions where the WB coefficient is switched.
Secondly, with the conventional image capture device, the precision of WB adjustment is poor, and information dropping precludes complete WB adjustment.
The region of the flashed light contribution K (=a/b) is 1 to ∞, and since it is not possible to handle the value ∞, the flashed light contribution K must be restricted to a predetermined upper limit value th.
Captured objects where K≧th are all corrected with the same WB coefficient when the upper limit value th is set to a low value, and thus the precision of WB adjustment drops. A flash is often emitted primarily in order to brighten objects that are dark, and thus the external light illumination C tends to be small and the flashed light illumination B tends to be large. The flashed light contribution K (=1+B/C) thus becomes a large value, making K≧th and lowering the precision of WB adjustment.
On the other hand, when the upper limit value th is set to a high value, a high degree of bit precision is necessary in order to maintain accuracy within a small-value region because the flashed light contribution is a "non-linear" parameter that increases abruptly, and this increases the scale of the circuitry.
Further, truncation leads to information loss and complete WB adjustment thus is not possible in the first place.
Thirdly, with the conventional image capture device, shifts in color stand out in regions where the captured object has moved.
Movement of the captured object while capturing two images with and without a flash shifts the flashed light contribution that is calculated from the two images, and this results in inappropriate WB adjustment in regions where there is movement and is expressed as a shift in color.
In the present application, this problem is solved by using a low pass filter (LPF) as described later, but in general the linear nature of a filter does not allow an LPF to be adopted for the "non-linear" flashed light contribution of Japanese Patent Publication 3540485, and thus cannot reduce color shifting.
Specifically, the flashed light contribution increases sharply the smaller the external light illumination C. The value after LPF thus is strongly affected by neighboring pixels that have extremely large values, and this precludes appropriate LPF processing.
It is conceivable to use a non-linear LPF in order to change the weighting coefficient, for example, in accordance with the pixel value. Changing the weighting coefficient with high precision, however, similarly requires weighting coefficients to be readied in a table, etc., and increases the scale of the circuit too much, and thus is not practical.

White balance adjustment device, image capture device, white balance adjustment method, storage medium, and integrated circuit


An engine controller comprises a combustion state detection or estimation means for detecting or estimating a combustion state in the combustion chamber, a combustion air-fuel ratio estimation means for estimating a combustion air-fuel ratio in the combustion chamber according to an exhaust air-fuel ratio and the detected or estimated combustion state, and a means for calculating engine control parameters according to the estimated combustion air-fuel ratio.

In response to the recent enhanced exhaust emission control for automobiles in North America, Europe, Japan, and other countries, the improvement of engine exhaust emission characteristics is being strongly demanded. As the performance and control precision of catalysts are being improved, exhaust emission from engines is dominant when they are started. Highly precious air-fuel ratio control is also effective in improving the engine exhaust emission characteristics at the time of start. However, exhaust air-fuel ratio feedback control, in which an exhaust air-fuel ratio is detected and the amount of fuel to be injected is then corrected, is usually started at a fixed time (10 to 20 seconds) after the start.
An air-fuel ratio sensor is activated at an early stage and a preheat system is introduced, so there is the prospect that exhaust air-fuel ratio feedback control initiated at the start will be put into practical use. When the fuel vaporization rate is low because, for example, temperature is low or heavy fuel is used, fuel that entered the combustion chamber is exhausted into the exhaust path without being burned. The exhausted fuel is oxidized in the exhaust path and by an exhaust air-fuel ratio sensor probe. When this happens, the exhaust air-fuel ratio is higher than the actual combustion air-fuel ratio. If the exhaust air-fuel ratio is fed back and the amount of fuel is determined according to the feedback, the combustion air-fuel ratio is not properly controlled (the combustion does not approach stoichiometric combustion) and an excessively lean burn thereby occurs, lowering exhaust purifying performance and running operation. To avoid this situation, a technology for initiating the detection of the combustion air-fuel ratio with high precision at the time of start and controlling the combustion air-fuel ratio is necessary.
Accordingly, various control methods and apparatuses have been proposed as in Japanese Patent Laid-open No. 2003-83133 (Patent Document 1) and Japanese Patent Laid-open No. 10-30537 (Patent Document 2).


A data driving circuit of an LCD device includes a timing controller for formatting input data so that data and gate drivers of an LCD panel display a picture image, and outputting a selection signal; a plurality of digital to analog converters for converting digital signals output from the timing controller to analog signals based on a color gray level displayed; and a plurality of amplifiers for amplifying the signals output from the respective digital to analog converters and outputting the amplified signals to the LCD panel.

1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a data driving circuit of an LCD device that displays an image signal by driving a digital to analog converter based on a color gray level displayed, thereby reducing power consumption.
2. Discussion of the Related Art
In general, LCD devices have been widely used for monitors of portable electronic devices such as notebook computers, mobile phones, and personal data accessories. An LCD device typically includes an LCD panel and a data driving circuit. The LCD panel displays image signals, and the data driving circuit applies driving signals from the outside to the LCD panel.
A related art LCD device having an LCD panel and a data driving circuit will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram of the related art LCD device.
As shown in FIG. 1, the LCD device includes an LCD panel 1 and a data driving circuit 2. In the LCD panel 1, gate and data drivers 1a and 1b are formed in a peripheral region of a pixel array in a pixel region of a matrix, by arranging a plurality of gate and data lines. The data driving circuit 2 provides data to the LCD panel 1.
The data driving circuit 2 includes a timing controller 3, a level shifter 4, a digital to analog converter 5, a common voltage amplifier 6, and a power supply 7. The timing controller 3 formats input data, such as display data R, G, and B having, for example, one bit, four bits, or six bits, vertically and horizontally synchronized signals Vsync and Hsync, a clock signal DCLK, and a control signal DTEN. The formatted data is output to the gate and data drivers 1a and 1b so that the respective gate and data drivers 1a and 1b can display a picture image. The level shifter 4 amplifies voltage levels of the clock signal DCLK and the control signal DTEN among the signals output from the timing controller 3. The digital to analog converter 5 converts digital display signals output from the timing controller 3 to analog signals that are appropriate for a liquid crystal driving voltage, and then outputs the analog signals to the LCD panel 1. The common voltage amplifier 6 amplifies a common voltage, and supplies the common voltage to the LCD panel 1 through the power supply 7.
The timing controller 3 may further include a frame memory. Although not shown, two transparent substrates (glass substrates) are attached to each other and are separated by a constant distance, and a liquid crystal is injected between the two transparent substrates, thereby forming the LCD panel.
One of the two transparent substrates includes a plurality of gate lines, each of which are separated by a constant distance from one another. A plurality of data lines cross the gate lines and are also separated by a constant distance from one another. A plurality of pixel electrodes are formed in each pixel region of a matrix which includes the gate and data lines. A plurality of TFTs apply signals from the data lines to the pixel electrodes according to a signal of the gate line. The other transparent substrate includes a color filter film, a common electrode, and a black matrix film.
For LCD panels having the above structure, a circuit structure of a low polysilicon LCD panel is shown in FIG. 2.
Referring to FIG. 2, the LCD panel 1 includes a pixel array, a plurality of first shift registers 11 and first buffers 12, a plurality of second shift registers 13 and second buffers 14, a plurality of signal lines 15, and a plurality of switching devices 16.
In the pixel array, a plurality of gate lines G1–Gm vertically cross a plurality of data lines D1–Dn. The first shift registers 11 and the buffers 12 provide scan signals to each gate line. Each data line is divided into k blocks, and a unit second shift register 13 and a unit buffer 14 are formed in each block of the data line to drive the data line. The plurality of signal lines 15 transmit the image signals output from the digital to analog converter 5 of the data driving circuit 2 to each data line. The plurality of switching devices 16 sequentially apply the image signals of the signal lines 15 to the data lines in order of each block in accordance with driving signals output from the second shift registers 13 and the second buffers 14.
Unlike existing amorphous silicon data driving circuits, the data driving circuit of the low polysilicon TFT LCD panel divides a plurality of data lines into blocks to reduce the number of contact lines between an external circuit and the LCD panel when selecting the gate line, and then sequentially supplies display voltages to the data line.
Accordingly, the digital to analog converter requires a driving capability that can charge the data line for a shorter time as compared with amorphous silicon data driving circuits. To obtain the driving capability, the amplifying driving capability of the digital to analog converter has to be improved. To improve the amplifying driving capability, a standby current has to be increased.
The operation of the aforementioned LCD device will be described with reference to FIG. 3.
Pulse signals g1 and g2 are sequentially applied to each gate line by a gate start signal GSTART and clock signals GCLK and GCLKB. Then, data signals d1 and d2 are applied to each data line by a data start signal DSTART and clock signals DCLK and DCLKB to turn on the switching devices 16, thereby providing image signals of the signal lines 15 to each data line.
At this time, the data driving circuit repeats the operation in each pulse section. That is, the data driving circuit performs the operation of the section "a" in the unit gate pulse section. Accordingly, the driving capability of the data driving circuit of the low polysilicon LCD panel has to be improved as compared with that of the data driving circuit of the amorphous silicon LCD panel.
However, the data driving circuit of the related art LCD device has the following problems.
In general, in electronic devices such as notebook computers and mobile phones having an LCD device, image signals of full color or multigray (over 64 gray) are not always displayed. For example, in a standby mode of mobile phones, a low gray image signal of, for example, letters is displayed.
In electronic devices displaying image signals of full color, multigray level, or low gray level, the data driving circuit of the related art LCD device has only one digital to analog converter having a constant speed and standby current regardless of a gray level of an image picture displayed. Having only one digital to analog converter regardless of the gray level of the image displayed causes unnecessary power consumption.
If the data driving circuit includes a digital to analog converter that displays image signals of full color or a multigray level, even though image signals having a low gray level are displayed, the single digital to analog converter causes a consumption of power corresponding to that of multigray image signals. Accordingly, it is desirable to reduce power consumption in such electronic devices.

Data driving circuit of liquid crystal display device


A method that includes configuring a queue into a plurality of segments, wherein each segment is associated with a depth factor which defines number of entries of task elements capable of being added in each segment, and wherein each segment is associated with a requirement factor; generating a plurality of task elements, each task element having an importance factor; and if a value of an importance factor of a task element is at least equal to a value of a requirement factor of a segment with an available entry to add the task element, then adding the task element in the entry of the segment.

A queue is a data structure or abstract data type with entries which can be used to hold a plurality of data objects in a particular order. A system can perform operations on the queue such as adding data objects to the end position of the queue and removing data objects from the beginning position of the queue.

Hewlett-Packard Development Company, L.P.


A fitted sheet for a mattress comprises a rectangular panel of knit material having a central rectangular area extending from one end of said panel to the other end thereof. Side margins flank the central area, and folded under said central area and joined thereto by seams extending across each end of the central rectangular area. The sheet is characterized in that the seams at each end of said central rectangular area are arcuate.

The present applicant is the inventor of the fitted bed sheet described and claimed in U.S. Pat. No. 5,765,241. That sheet, which is fabricated from knit material, is known in the trade as an envelope sheet. It is made from a tube of knit fabric, slit along an edge to form a rectangle. The side margins of the rectangle are then folded inwardly to the midline of the sheet, and top and bottom edges are sewn, joining the top and bottom edges of the folded-over margins to the top and bottom edges of the sheet of fabric. The inwardly directed edges of the margins are then finished with binding in a continuous loop to finish the sheet. The advantages of such a sheet are that it is economical to manufacture, and it fits securely on a mattress, especially a multi-position hospital mattress, without coming off. It lays flat on the mattress, even when the mattress is articulated, which results in a comfortable surface that does not have wrinkles on it to promote bed sores.
The applicant has identified two areas of potential improvement in the envelope sheet. First, the sewing of the top and bottom edges of the folded-over sheet is substantially transverse to the longitudinal axis of the sheet. This does tend to create "ears" of material at the outer edge of the sheet when it is placed on a mattress. These ears tend to be positioned on the side surface of a mattress, near the corners of same. They are untidy looking, and a waste of material. That is, they create the appearance of an ill-fitting sheet.
The other area of improvement lies in the binding that is sewn in a continuous loop around the inward facing edge of the margins. The applicant has developed a technique that eliminates the need for such a binding.


A memory device output buffer circuit provides an output data signal only when data is valid. According to the present invention, the circuit for a memory read function provides a pair of signals equilibrated prior to each read operation. Data is valid when the signals are complementary. For a tristate output, the complementary condition enables the output buffer. In a semiconductor dynamic random access memory (DRAM) connectable to a bidirectional data bus, the three-state output buffer of the present invention is not enabled during a read operation until data is valid. Spurious output data signals are prevented from consuming power. As an additional benefit, the bus is not dedicated to the memory when valid data is not yet available.

The unit of information for storage and retrieval in digital systems is the data bit, a binary number having a value of zero or one. A data bit in a digital system has logic states of "high" and "low," often corresponding to a physical parameter such as the voltage at a node in a circuit. Information stored in semiconductor circuits is quantified in terms of the number of bits stored. These circuits, collectively called memory devices, include latches, flip-flops, registers, and memories depending to some extent on the number of bits stored. However, the fundamental circuit for storing a data bit, herein called a memory cell, is the common building block from which latches, flip-flops, registers, memories, and the like are made.
Several common circuits have been used for the memory cell in the various types of memory devices. Some devices including the dynamic random access memory (DRAM) employ a memory cell circuit having primarily one transistor. The DRAM cell provides one signal for stored data. Other devices including the static random access memory (SRAM) employ a memory cell circuit having primarily a cross coupled pair of transistors. The SRAM cell provides two complementary signals for stored data. For example, when the signals are respectively D and D*, a zero is represented when D is low and D* is high, a one is represented when D is high and D* is low. Other combinations of D and D* are undefined, that is they serve no purpose in the memory device.
Memory devices that are used for storing many bits of information provide an output data signal in response to an input address signal during a "read" operation called a read cycle. In a complex memory device the read operation may be performed as a process of selecting, sensing, and outputting the content of memory cells. The duration of such a process is called the access time. Complex memory devices may have several types of operations distinguished by control signals including read/write, address strobes, programming and erasure strobes, transfer enable, and output enable signals. The read cycle begins when the operation is defined by these control signals and an address is specified on the address input of the memory device.
The address can be specified in one of several ways depending on the design of the memory device. For example, an address can be specified in serial in conjunction with a clock signal or in parallel often accompanied by a strobe signal. A combination of these methods could be used, for example, by presenting on 16 parallel address lines a 32-bit address in two steps accompanied by upper and lower address strobes. In a conventional DRAM these strobes are associated with the row and column organization of memory cells in an array. Designs for high density memory devices employ several arrays of cells having minute dimensions. Typically, the signal or signals representing the data bit in a memory cell in such an array are weak.
The read cycle concludes with presentation of signals for use outside the memory device that represent the data addressed. The weak signal levels internal to the memory device are sensed and amplified. Amplified signals at internal signal levels are then translated to conventional logic levels and gated onto the output terminals of the memory device. The level translation and gating are accomplished by an output buffer circuit. When the output buffer is supplying a signal on the output terminal, it is said to be gated on, or enabled; otherwise it is off or disabled. One aspect of the present invention solves a timing problem associated with the interaction of the sensing circuit and the output buffer circuit.
Memory circuit timing is critical to the efficiency of many systems applications for memory devices. In a computer system, for example, the processor and memory devices are connected by a signal path called a bus. The bus is used for information flow to the processor and from the processor to other devices on the bus. One measure of system efficiency is the extent of time the bus is idle or unusable. The bus is idle when it is not being used by any device. The bus is unusable when it is dedicated to a device but the signal on the bus is invalid, conveying no useful information.
Conventional DRAM devices used in computer systems allow the output buffer to provide spurious signals on the bus causing the bus to be unusable for a period of time. This problem is described in terms of DRAM devices in a computer system but exists in other applications and with other types of memory devices. For the DRAM application, the bus is unusable for a time preceding output of valid data. A read cycle begins when the row address strobe (RAS*) falls (a high to low transition) at a time when the address input specifies the row address. When the column address is specified on the address input, the column address strobe (CAS*) falls. Conventionally, the output buffer is enabled a delay after CAS* falls and before data can be guaranteed to be valid. Hence, spurious signals can appear on the bus, and consequently other uses of the system bus must wait until the memory device is no longer dedicated to the bus; and, power is wasted while driving spurious signals to conventional logic levels.
In other conventional memory devices including DRAM and video random access memory (VRAM) devices, read operations include a so-called page mode having an access time. In page mode, a row address is specified for use with several subsequently specified column addresses. Column address changes are detected by a circuit that provides a timing pulse. The timing pulse enables the output buffer after a fixed predetermined delay. The delay may be too short for some memory cells and sense amplifiers that respond relatively slowly due to physical location or circuit element variations caused by fabrication process variations. In such a case the output buffer is enabled (upon the expiration of the delay) at a time when spurious signals exist on the data path. If the delay is long enough to avoid all spurious signals, data from faster cells will wait at the output buffer before the buffer is enabled. A faster access time would have been possible had the delay been shorter.
Some conventional memory devices perform back to back read operations. In such a device a subsequent read cycle immediately follows latching previously read data in the output buffer. A timing pulse operates the latch after a fixed predetermined delay. In some devices, column address changes are detected by a circuit that provides the timing pulse. The delay must be designed to allow for the precharge, address decoding, sensing, and driving required for the longest read operation in order to guarantee that the latched data represents the content of the memory and not spurious signals preceding the memory content signal. When the delay is long enough to avoid all spurious signals, data from faster cells will wait at the output buffer before the latch is enabled. A faster access time would have been possible had the delay been shorter.
DRAM or VRAM devices designed to enable the output buffer after a fixed predetermined delay cannot be effectively sorted by access time. When many devices are manufactured on a single wafer, the predetermined delay must be long enough to account for process variation. For example, if the delay is long enough to guarantee operation of all devices on the wafer, the performance of some of the devices is limited by the delay. These devices could have been sorted and guaranteed at a faster access time than the access time of other devices on the same wafer. Memory devices guaranteed at a faster access time command a higher market price and facilitate new and improved systems from integrated microprocessors to automated equipment.
Thus, there remains a need for a memory device whose output buffers do not output spurious signals. In addition, there remains a need for an improved method for reading a memory cell without dependence on predetermined delays. Further improvement in performance of systems using memory devices can be gained by employing methods of the present invention and incorporating circuits of the present invention in the design of memory devices.

Memory circuit with foreshortened data output signal


Methods of frequently monitoring glucose amounts and/or concentrations in a subject who is at risk for hypoglycemia, hyperglycemia, and/or glucose level fluctuations that put the subject at risk are provided. Also provided are methods of monitoring the effects of one or more pharmaceutical compositions on the levels of glucose in a subject.

The level, presence, and/or absence of glucose in a subject can have a number of consequences. For example, fluctuations of blood glucose levels can result in one of two physiological states, hypoglycemia and hyperglycemia. Hypoglycemia is defined as plasma glucose levels below normal. Hypoglycemia can be symptomatic or asymptomatic. For example, subjects suffering from postprandial hypoglycemia generally have symptoms of adrenergic stimulation including diaphoresis, anxiety, irritability, palpitations, tremor, and hunger. Such symptoms typically occur from about 2 to 4 hours postprandially and tend to occur suddenly with symptoms generally subsiding in about 15 to 20 minutes. Hypoglycemia can be caused by release of adrenergic and cholinergic hormones. Postprandial hypoglycemia is often idiopathic, however, it can be caused by early diabetes, alcohol intake, renal failure, and drug treatments. In addition, a category of hypoglycemia exists which is designated as fasting hypoglycemia. Clinically, this form of hypoglycemia may have symptoms of neuroglycopenia including headache, fatigue, and mental dullness. In more severe cases, hypoglycemia can progress to confusion, blurring of vision, seizure, and ultimately loss of consciousness or seizure. Fasting hypoglycemia can occur with a fast of greater than 4 hours, and further can be caused by insulinoma (resulting from self-administered insulin or intake of other hypoglycemic agents, alcohol abuse, liver disease (e.g., decreased gluconeogenesis), pituitary insufficiency, or adrenal insufficiency).
Hyperglycemia, on the other hand, refers to excessive levels of blood glucose in a subject. There are many forms of hyperglycemia, the primary form being diabetes mellitus (DM) which is defined as hyperglycemia secondary to decreased insulin production or an increase in peripheral tissue resistance to the action of insulin. There are several classifications of DM including, type 1 DM, type 2 DM, gestational DM, and secondary DM (which can, for example, be the result of a variety of drug therapies, disease states (e.g., pancreatitis, Cushing's syndrome), trauma, surgery, and others causes). Further, in the case of severe insulin deficiency, a starvation-like state develops resulting in acidosis (typically referred to as diabetic ketoacidosis). Symptoms of ketoacidosis can include rapid respiration, acetone breath, vomiting, dehydration, nausea, abdominal pain and changes in mental stability.
Thus, there is a need for frequent monitoring of glucose levels in many subjects who are at risk for hypogylcemia and hyperglycemia.

Methods of monitoring glucose levels in a subject and uses thereof


A driving force control system for a four-wheel drive vehicle[is disclosed] which enables the vehicle to smoothly start on a low-xcexc road surface, and is capable to distributing just required amounts or driving forces to auxiliary drive wheels depending on an actual accelerating condition of the vehicle, thereby improving the response and fuel economy of the vehicle. The four-wheel drive vehicle includes front wheels as main drive wheels, and rear wheels as auxiliary drive wheels. The driving force control system controls engagement forces of electromagnetic clutches to thereby control the driving forces (torques) distributed to the rear wheels. The 2/4WDxc2x7ECU of the driving force control system calculates a filtered vehicle acceleration XGF1F of the vehicle 2 based on a drive torque TD, and then calculates a basic VATC torque value VATC based on the calculated filtered vehicle acceleration XGF1F, for use in calculation of the final desired VATC torque value TOBJM of torque to be distributed to the rear wheels.

1. Field of the Invention
This invention relates to a driving force control system for a four-wheel drive vehicle including a pair of front wheels, and a pair of rear wheels, one of the pairs being main drive wheels, and another of the pairs being auxiliary drive wheels, the driving force control system controlling engagement forces of clutches to thereby control driving forces distributed to the auxiliary drive wheels.
2. Description of the Related Art
Conventionally, a driving force controls system of this kind has been proposed, e.g., by Japanese Laid-Open Patent Publication (Kokai) No. 9-109716, for a four-wheel drive vehicle (hereinafter referred to as he vehicle including rear wheels as main drive wheels, and front wheels as auxiliary drive wheels. This driving force control system controls the engagement forces of variable torque clutches to thereby control torque distributed or allocated to the front wheels, i.e., the auxiliary drive wheels. More specifically, a first front-wheel distribution torque is calculated based on the difference (hereinafter referred to as ear-front wheel speed difference obtained by subtracting the wheel speed of the front wheels from the wheel speed of the rear wheels. A second front-wheel distribution torque is also calculated based on the oil temperature of the variable torque clutches. Further, a third front-wheel distribution torque is calculated based on a throttle opening when the wheel speed of the front wheels is equal to or lower than a predetermined value (i.e., during the start of the vehicle), and set to a value of 0 when the wheel speed of the front wheels is larger than the predetermined value (i.e., after the start of the vehicle), or when the rear-front wheel speed difference assumes a negative value (i.e., during deceleration of the vehicle). Then, the maximum value of the above first to third front-wheel distribution torques is determined to be a final control value, based on which the variable torque clutches are driven to control the engagement forces thereof to thereby control the torque distribution to the front wheels.
According to the proposed prior art driving force control system, the torque distributed to the front wheels is calculated based on the above-mentioned three parameters: the rear-front wheel speed difference, the oil temperature, and the throttle opening. Therefore, it is impossible to perform delicate or fine control of torque distribution to the front wheels based on a state of slippage of the individual rear wheels. As a result, when the vehicle is being started on a road surface having a small frictional resistance xcexc (hereinafter referred to as xe2x80x9clow-xcexc road surfacexe2x80x9d, such as an icy road surface), for instance, only one of the rear wheels might undergo slippage, but the system cannot perform the driving force control such that suitable torque distribution to the front wheels is effected in response to this slipping condition of one rear wheel, which makes it impossible for the vehicle to start smoothly. Further, the throttle opening indicates a driver demand for acceleration, but does not faithfully reflect an actual accelerating condition of the vehicle, so that the torque distribution to the front wheels cannot be properly carried out accordingly to the actual accelerating condition of the vehicle. This sometimes results in an insufficient torque distribution to the front wheels, or inversely, an excessive torque distribution to the same, which leads to decreased response of the vehicle and degraded fuel economy.
It is an object of the invention to provide a driving force control system for a four-wheel drive vehicle, which enables the vehicle to smoothly start on a low-xcexc road surface, and is capable of distributing only the required amounts of driving forces to auxiliary drive wheels depending on an actual accelerating condition of the vehicle, thereby improving the response and fuel economy of the vehicle.
To attain the above object, according to a first aspect of the invention, there is provided a driving force control system for a four-wheel drive vehicle including a pair of front wheels, and a pair of rear wheels, one of the pairs being main drive wheels, and another of the pairs being auxiliary drive wheels, the driving force control system controlling engagement forces of clutches to thereby control driving forces distributed to the auxiliary drive wheels.
The driving force control system according to the first aspect of the invention comprises:
driving force control means for controlling the engagement forces of the clutches such that the driving forces are distributed to the auxiliary drive wheels, on condition that there is satisfied at least one of the following conditions that a wheel speed of one of the main drive wheels is equal to or higher than a first predetermined speed, and at the same time, a wheel speed of another of the main drive wheels is lower than the first predetermined speed, and that an average wheel speed of the main drive wheels is equal to or higher than a second predetermined speed, and at the same time, an average wheel speed of the auxiliary drive wheels is lower than the second predetermined speed, until the average wheel speed of the auxiliary drive wheels reaches a third predetermined speed equal to or higher than the second predetermined speed.
According to this driving force control system for a four-wheel drive vehicle, when the wheel speed of one of the main drive wheels is equal to or higher than the first predetermined speed, and at the same time, the wheel speed of another of the main drive wheels is lower than the first predetermined speed, i.e., when one of the main drive wheels is slipping, driving forces are distributed to the auxiliary drive wheels until the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed. Thus, the control of distribution of the driving forces to the auxiliary drive wheels can be delicately or finely carried out depending on a slipping condition of each of the individual main drive wheels. Further, even when the wheel speeds of the respective main drive wheels are equal to each other, if the average wheel speed of the main drive wheels is equal to or higher than the second predetermined speed, and at the same time, the average wheel speed of the auxiliary drive wheels is lower than the second predetermined speed, i.e., when both the main drive wheels are slipping, driving forces are distributed to the auxiliary drive wheels until the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed. This make it possible to carry out control of distribution of the driving forces to the auxiliary drive wheels delicately or finely depending on a slipping condition of both of the main drive wheels, and hence enables the vehicle to smoothly start even on a low-xcexc road surface.
To attain the above object, according to a second aspect of the invention, there is provided a driving force control system for a four-wheel drive vehicle including a pair of front wheels, and a pair of rear wheels, one of the pairs being main drive wheels, and another of the pairs being auxiliary drive wheels, the driving force control system controlling engagement forces of clutches to thereby control driving forces distributed to the auxiliary drive wheels.
The driving force control system according to the second aspect of the invention comprises:
vehicle acceleration-calculating means for calculating a vehicle acceleration of the vehicle based on a demanded driving force demanded by the main drive wheels; and
driving force-calculating means for calculating the driving forces to be distributed to the auxiliary drive wheels based on the calculate vehicle acceleration.
According to this driving force control system for a four-wheel drive vehicle, the vehicle acceleration of the vehicle is calculated based on a demanded driving force demanded by the main drive wheels. Based on the calculated vehicle acceleration, the driving forces to be distributed to the auxiliary drive wheels are calculated, and the engagement forces of the clutches are controlled such that the calculated driving forces are distributed to the auxiliary drive wheels. Thus, based on the demanded driving force actually demanded by the main drive wheels, the vehicle acceleration is calculated, which can faithfully reflect an actual accelerating condition of the vehicle on the calculated driving forces. Therefore, because the driving forces to be distributed to the auxiliary drive wheels are calculated based the vehicle acceleration calculated as described above, differently from conventional cases where the driving forces are calculated based on the throttle opening, only the required amounts of the driving forces can be distributed to the auxiliary drive wheels while taking the actual accelerating condition of the vehicle into account. This makes it possible to improve the response and fuel economy of the vehicle.
Preferably, the driving force control system further includes driving force-increasing means for increasing the driving forces distributed to the auxiliary drive wheels, on condition that there is satisfied at least one of the following conditions that a wheel speed of one of the main drive wheels is equal to or higher than a first predetermined speed, and at the same time, a wheel speed of another of the main drive wheels is lower than the first predetermined speed, and that an average wheel speed of the main drive wheels is equal to or higher than a second predetermined speed, and at the same time, an average wheel speed of the auxiliary drive wheels is lower than the second predetermined speed, until the average wheel speed of the auxiliary drive wheels reaches a third predetermined speed equal to or higher than the second predetermined speed.
According to this preferred embodiment, when wheel speeds of the respective main drive wheels are different from each other, or the average wheel speed of the main drive wheels is higher than that of the auxiliary drive wheels, i.e. when one or both of the main drive wheels is/are slipping, the driving forces distributed to the auxiliary drive wheels are increased until the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed. Therefore, when the vehicle is starting on an icy road surface, and the vehicle acceleration is small due to a small throttle opening, for instance, if one or both of the main drive wheels is/are slipping, the driving forces distributed to the auxiliary drive wheels are increased, thereby enabling the vehicle to start smoothly. As a result, the startability of the four-wheel drive vehicle can be further improved.
More preferably, the driving force-increasing means includes progressively-increasing means for progressively increasing the driving forces distributed to the auxiliary drive wheels with the lapse of time.
More preferably, the driving force control system further includes driving force-progressively decreasing means for progressively decreasing the driving forces distributed to the auxiliary drive wheels with the lapse of time, after the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed.
Preferably, the driving force control system further includes vehicle speed detection means for detecting a vehicle speed of the vehicle, and correction means for correcting the driving forces for prevention of tight turn, such that the driving forces are made smaller as the vehicle speed detected by the vehicle speed detection means is larger, and at the same time that the driving forces are made larger as the demanded driving force is larger.
Preferably, the demanded driving force is calculated based on a basic driving force calculated based on an engine rotational speed and an intake pipe absolute pressure, by using a coefficient corresponding to a gear ratio of the vehicle, and a correction term corresponding to an inertial force of the vehicle.
Preferably, the vehicle acceleration-calculating means calculates the vehicle acceleration by subtracting a value corresponding to a running resistance of the vehicle from a vehicle acceleration value calculated based on the demanded driving force.

Driving force control system for four-wheel drive vehicles


An organic light emitting diode display device includes a panel in which a plurality of pixels are disposed, a power supplier configured to supply a current to the panel, and a controller configured to acquire information about the current supplied to the panel and perform an automatic current limit so that the current supplied to the panel is controlled to a preset current limit value or less. The controller is configured to adjust the current limit value based on the information about the current supplied to the panel.

The present invention relates to an organic light emitting diode display device, and more particularly, to reduction in temperature of an organic light emitting diode display device.
In recent years, the types of display devices have been diversified. Among them, an organic light emitting diode (OLED) display device is widely used.
Since the OLED display device is a self-luminous device, the OLED display device has lower power consumption and can be made thinner than a liquid crystal display (LCD) requiring a backlight. In addition, the OLED display device has a wide viewing angle and a fast response time.
In a general OLED display device, red, green, and blue sub-pixels constitute one unit pixel and an image having various colors may be displayed through the three sub-pixels.
Specifically, the OLED display device may display an image by supplying a current to at least one of the red, green, and blue sub-pixels. For example, the OLED display device may implement a red color in a corresponding pixel by supplying a current to only a red sub-pixel and not supplying a current to green and blue sub-pixels. In addition, the OLED display device may implement secondary colors such as yellow, cyan, and magenta by supplying a current to two sub-pixels among red, green, and blue sub-pixels.
The OLED display device may require a high current when an image including a plurality of secondary colors, such as animation, is displayed or an image mode is set to a vivid mode which increases color saturation and/or contrast. In this case, the temperature of the panel may be excessively increased.
As the prior art for preventing overheating of the OLED display device, Korean Patent Registration No. 10-0680913 (published Feb. 8, 2007) discloses a configuration that measures a heat generated in the OLED display device by a temperature sensor and determines a power supply voltage applied to the OLED display device according to temperature data input by the temperature sensor.

Organic light emitting diode display device