An enabling circuit for use in a wideband signal distribution system is provided. The circuit includes a input port which receives a baseband source signal, a transmission path between the input port and the output port, an impedance matching device, and a power source connected to the impedance matching device which combines a biasing signal with the input signal in order to operate a diode switch which is connected to the output to the impedance matching device and located in a distribution unit of the system.

There are numerous instances where it is desirable to distribute signals within a relatively local area such as a building or series of buildings. A particular application is the distribution of video signals. For example, a school may have a number of classrooms or administrative offices, each having a television monitor, and it may be desired at a given time to provide a program to all the classrooms and offices, originating either from a source within one of the classrooms or offices, such as a VCR, or from an outside source such as a local cable system. A system capable of distributing wideband signals is necessary to provide these programs to the desired locations. Similarly, a corporation may have a building, or several closely spaced buildings, with numerous conference rooms equipped with television monitors and analogous program presentations may be desired.
An example of such a wideband distribution system is disclosed in International Publication Number WO 97/01931, titled "Wideband Signal Distribution System", which is assigned to the assignee hereof and is incorporated herein by reference. That Publication disclosed a wideband distribution system utilizing existing twisted pair cable which is typically installed in buildings for telephone communications. The system, therefore, would require no additional wiring to provide the wideband distribution system to an existing building. This system utilizes distribution units which can be cascaded in order to reach many rooms in the building which are connected to the telephone wiring system. Each distribution unit has a plurality of inputs and outputs, each of which is connected to a different room outlet. In order to reach additional rooms, another distribution unit is simply cascaded into the system. Any of the rooms connected to a distribution unit can be utilized either to transmit a source signal to the entire building or as a receiving location to receive any signal which is transmitted over the distribution system from another location. Since each outlet in this system is capable of both input and output, signals can be distributed to any location from any location. Signals at the input location are generated by a base band signal source and are modulated to a desired frequency channel.
A problem exists, however, when it is desirable to distribute wideband modulated signals to many classrooms or locations. As the number of classrooms increases the number of input and output locations increases, and the amount of near end cross talk also increases. This is due to increased length of cable in the system necessary to support the increased number of classrooms. Near end cross talk occurs as a result of capacitive coupling of signals between the input wires and output wires of each cable. It is therefore an object of this invention to reduce near end cross talk in a broadband distribution system having many input and output ports.
Another problem exists when many outlets are present in the distribution system in that the distance between each distribution unit and outlet is variable. Outlets which are farther from the distribution unit will necessarily contain longer lengths of cable between the distribution unit and the outlet. This results in signal attenuation levels at each outlet being different based on the distance each outlet is from the distribution unit. It is therefore an object of this invention to provide a circuit which simulates long and short lengths of cable in order to provide consistent system signal attenuation levels at each outlet.

Enabling and cable simulating circuits for wideband signal distribution system


A gear drive mechanism with two rotary gears meshing with each other has a first friction rim surface rotationally coupled to one of the two gears and a second friction rim surface rotationally coupled to the other of the two gears. The friction rim surfaces are in mutual contact with each other and thereby enabled to transmit a friction-based torque between each other.

The invention relates to a gear drive mechanism with an anti-rattle device. Rattling or clattering noises which are found irritating occur often in gear mechanisms as a result of non-uniformities in the movement of the shafts that are rotationally coupled to the gears and as a result of the play between the tooth flanks of the gears.

Gear drive mechanism with anti-rattle device


An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.

1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to system-on-a-chip integrated circuits.
2. The Prior Art
Usually system designers employ multiple analog-to-digital converter (ADC) parts to achieve simultaneous analog signal sampling capability. Some analog ADC integrated circuits, such as the ADuC824 manufactured and sold by Analog Devices, employ a multiplexer before an input buffer as shown in FIG. 1, making it impossible to achieve simultaneous sampling if only one ADC chip is used.
Some ADC integrated circuits, such as the ADS7869 manufactured and sold by Texas Instruments, provide three analog-to-digital converters on one chip, as shown in FIG. 2. The ADS7869 includes three, SAR-type, 12-bit ADCs, and three pairs of sample/hold capacitors, which are connected to ADC1 and ADC2, respectively. A single sample/hold capacitor is connected to ADC3. Each sample/hold input is selected from one of four analog inputs. Up to three on-chip ADCs are needed in order to implement simultaneous sampling for up to three analog inputs.
Analog comparators are usually discrete devices used in mixed-signal systems. Some ADC integrated circuits, such as the ADS7869 manufactured and sold by Texas Instruments, have an on-chip window comparator and sign comparator. The window comparator is used to test if the input voltage is within a certain range and the sign comparator is used, for example, for the position sensor inputs in motor control applications or to measure the sign of the main currents.

This patent is subject to a terminal disclaimer.

Mixed signal system-on-a-chip integrated simultaneous multiple sample/hold circuits and embedded analog comparators


In a display device (1) according to an aspect of the present invention, at least part of an N-M first sub pixel(s) is/are driven according to one of first and second gamma curve groups being selected depending on a position(s) where said at least part of the N-M first sub pixel(s) is/are located, and at least part of a second sub pixel(s) is/are driven according to one of the first and second gamma curve groups being selected depending on a position(s) where said at least part of the second sub pixel(s) is/are located.

In the field of a display panel provided in, e.g., a liquid crystal display device, there is a demand for a technique for improving visibility of the display panel when the display panel is viewed at an angle, for the purpose of improving a viewing angle.
Patent Literature 1 describes a liquid crystal display device including (i) a liquid crystal panel including a large number of pixels including a first pixel group and a second pixel group and (ii) a data driving section for respectively providing the first pixel group and the second pixel group with tone voltages corresponding to a first data signal and a second data signal that are for different gamma constants.
However, the conventional technique described in Patent Literature 1 involves a problem of displaying an image that is not an image desired to be displayed.
With reference to FIGS. 21 and 22, the following describes an example where a geometric pattern showing a black oblique line, for example, is displayed as a result of driving of the pixels according to the above-described conventional technique. FIG. 21 illustrates a display region of a conventional display device. FIG. 22 illustrates an image that is to be displayed in the display region shown in FIG. 21 but is not yet displayed by driving the pixels according to gamma curves having gamma characteristics being different for different pixels, that is, an image which is an original image to be displayed.
A display region 330 shown in FIGS. 21 and 22 includes a plurality of pixels 331 arranged in stripes. The description here deals with a configuration in which each of the pixels 331 is constituted by four sub pixels 341, 342, 343, and 344 displaying red (R), green (G), blue (B), and white (W), respectively.
The following method is considered as an example of the driving method carried out according to the above-described conventional technique, i.e., according to the gamma curves having different gamma characteristics for different pixels: As shown in FIG. 22, each of adjacent ones of the pixels 331 is driven with use of (i) a gamma curve having a gamma characteristic having a high (bright) relative luminance for each tone and (ii) a gamma curve having a gamma characteristic having a low (dark) relative luminance for each tone. However, with this method, there occurs a case where all pixels 331 located in positions (indicated by dotted-line rectangles in FIG. 22) corresponding to the oblique line that is to be displayed are driven according to the gamma curve having the bright gamma characteristic. This leads to a problem of failing to display the oblique line that is to be displayed.
Further, the sub pixels displaying different colors have different viewing angle characteristics and different chromaticity characteristics. This leads to a problem that a color is viewed differently (color deviation) between a case where the display region is viewed from the front and a case where the display region is viewed at an angle. FIG. 19 illustrates a positional relationship between (i) a case where the display region 330 is viewed from the front (front viewing) and (ii) a case where the display region 330 is viewed at a viewing angle of 60° (viewing at 60°). FIG. 20 illustrates RGBW tone characteristics observed when the display region of the conventional display device is viewed at a viewing angle of 60°, the conventional display device being adjusted so that its RGBW tone characteristics observed when the display region is viewed from the front become closer to a gamma curve C10 (γ=2.2) that is observed at a gamma characteristic of 2.2. Note that, in FIG. 20, a curve C11 indicates an R tone characteristic, a curve C12 indicates a G tone characteristic, a curve C13 indicates a B tone characteristic, and a curve C14 indicates a W tone characteristic.
As shown in FIG. 20, even in the case where the RGBW tone characteristics observed when the display region is viewed from the front are adjusted so as to be equal to each other, the RGBW tone characteristics observed when the display region is viewed at an angle become different. As is clear from this, the sub pixels displaying different colors have different viewing angle characteristics and different chromaticity characteristics.
In order to solve the problem of the color deviation in the above-described conventional technique, driving the sub pixels with use of the gamma curves individually adjusted for all the colors may be possible. However, this method involves another problem of making a configuration of an image processing section complicated.
With reference to FIG. 23, the following describes an image processing section employing the method of driving the sub pixels with use of the gamma curves individually adjusted for all the colors. FIG. 23 is a block diagram illustrating a configuration of an image processing section 322 in the conventional display device.
The image processing section 322 includes an RGBW developing section 351 and a tone characteristic adjusting section 352. The RGBW developing section 351 generates, from RGB data received from a video data processing section (not shown), red data (hereinafter, abbreviated as "R data"), green data (hereinafter, abbreviated as "G data"), blue data (hereinafter, abbreviated as "B data"), and white data (hereinafter, abbreviated as "W data").
The tone characteristic adjusting section 352 includes an R data processing section 353, a G data processing section 354, a B data processing section 355, and a W data processing section 356. The R data processing section 353 carries out a process of generating adjusted R data from the R data generated in the RGBW developing section 351 in order that the sub pixels for displaying red are driven according to a gamma curve individually adjusted for the sub pixels for displaying red. In a similar manner, the G data processing section 354 processes the G data, the B data processing section 355 processes the B data, and the W data processing section 356 processes the W data.
Thus, in order to drive the sub pixels with use of the gamma curves individually adjusted for all the colors, individual adjustments for RGBW are necessary. This increases a circuit scale in the image processing section, thereby leading to additional problems of, e.g., an increase in the cost and an increase in the power consumption.


Examples provide a configurable connection reset system for customized distribution of incoming traffic to a plurality of servers. The connection reset component routes incoming service requests to active servers based on server performance, configurable server failure criteria, user-selected inactive threshold wait time-period for each server and per-client distribution configurations, including server priorities and user-selected distribution methodology or combination of distribution methodologies. A configurable wait time-period is assigned to each inactive server removed from a distribution rotation for the incoming traffic. A next received request to the next available server for the identified client. An inactive server is updated to active status and returned to the distribution rotation after expiration of the configurable wait time-period.

Clients can send hundreds or thousands of service requests to servers each day. If too many of the service requests are received by the same server, the server can experience lag time responding to the requests or cause denial of service due to insufficient resources to respond to all the requests received simultaneously. A load balancer can be used to throttle or reduce the number of service requests going to each server to reduce lag time and service denials. However, these load balancers typically throttle requests in accordance with a predetermined schedule without regard to client preferences or dynamic state of various servers receiving the request. This can lead to inefficient routing of service requests, lack of flexibility and sub-optimal resource utilization.

Configurable connection reset for customized load balancing


The present disclosure discloses a method and device for localized blind watermark generation and detection. The method for localized blind watermark generation may include: generating an N-dimensional pseudorandom initial sequence according to a preset key, and generating a 2N-dimensional sequence by inverting the initial sequence bit by bit and appending the inverted sequence to the initial sequence; and extracting the first 2N coefficients of a feature point of an image to form a coefficient sequence, and acquiring a parity of a bit of the coefficient sequence according to a parity of a corresponding bit of the 2N-dimensional sequence. With the present disclosure, redundant expansion may be performed on watermark data to increase the scale of test data with respect to the original bit data before embedding the test data into a transformation domain of the vicinity of a feature point of an image; during detection, a sequence extracted from the transformation domain of the vicinity of a certain feature point is checked bit by bit, and it is determined whether a watermark is embedded in the vicinity of the point base on the result of the examination, thereby enhancing a watermark detecting efficiency.

A digital watermark is an invisible identifier embedded into image data, video data, or audio data, and can be used for copyright protection, authentication, and tracking of multi-media data, and the like.
Digital watermarking technologies may be divided into express watermarking and blind watermarking according to watermark extraction. Extraction of an express watermark requires original data in which the watermark is embedded, while a blind watermark only requires a key. Generally speaking, the express watermark is robust, but cost a lot in storage, and does not meet a practical requirement very well. Therefore, the blind watermark is a trend in watermarking algorithm research.
Image watermarking technologies may be divided into a globally embedded watermarking and a locally embedded watermarking according to the way in which a watermark is embedded. The watermark information in the globally embedded watermarking is embedded into a transformation domain of the whole image, such as a space domain, a frequency domain, a wavelet domain, or the like. Experiments show that such a method has a relatively robust resistance against an interference such as JPEG compression, interference by noise, filtering, or the like. However, as the information is embedded in the whole image, when the image is tailored, the size of the original image and the position of the tailored image in the original image are unavailable, it will be difficult to determine the position where the watermark is embedded, and therefore a globally embedded watermark is susceptible to an attack by tailoring; a locally embedded watermark is embedded based on content of the image, and the watermark information is repeatedly embedded onto a transformation domain of the vicinity of a relatively stable and prominent feature point in the image. Thus, even if image goes through a large-scale tailoring or modification, the position of the watermark can still be determined through the feature point, thereby recovering the watermark information. As in theory, the localized watermark has a good robustness against various attacks, and the localized watermark has become a hot spot of research in recent years.
Localized blind watermarking is a combination of both the blind watermarking and the localized watermarking. Localized blind watermarking in relevant art mainly relates to techniques such as watermark embedding, watermark detecting and extracting, and the like. A flow of embedding a localized blind watermark is as follows: first, a number of feature points in the original image is extracted, and local DCT (Discrete Cosine Transform) or Wavelet transformation is performed on the vicinity of the feature points; then, a pseudorandom bit sequence generated by a specific key (namely, the watermark information) is embedded into the transformation domain according to a preset embedding rule; finally, a local inverse transformation is performed to obtain a watermarked image. A flow of detecting and extracting a localized blind watermark is as follows: a feature point of an image is extracted, and local DCT or Wavelet transformation is performed on the vicinity of the feature point; then, a bit sequence with the same dimension as the watermark information is extracted based on a preset extracting rule, and a match is performed to obtain a degree of similarity of the bit sequence with a pre-embedded watermark information (available from the key); and a watermark is deemed to exist if the degree of similarity is greater than a certain threshold T, otherwise no watermark is deemed to exist.
There are some disadvantages associated with the aforementioned localized blind watermarking, namely:
1) Watermark detection is still key-dependent, and during the detection, different keys are required for the match in order to complete the detection, thus leading to a low detecting efficiency;
2) when performing the match to obtain a degree of similarity with the watermark information, each bit in a watermark information space has, by default, the same credibility in the match, leading to no accurate match in some cases, for example: assume an unknown sequence of 11111, watermark A of 11110, watermark B of 01111, in which case it is impossible to determine which one of watermarks A and B is more credible when the same extracted sequence has the same degree of similarity with the two different watermarks A and B; according to a match based on the difference, there is only one bit in both watermarks A and B that is different from that in the unknown sequence, and it is impossible to determine whether the unknown sequence is watermark A or watermark B, thus leading to a low detecting accuracy.

Method and device for localized blind watermark generation and detection

Tencent Technology (Shenzhen) Company Limited


Generally, in one aspect, apparatus features a structure for routing test signals between pads of a device under test and a tester circuit. The structure features a probe support that includes a substrate having contact points, one for each of the pads to be tested, a number of conductors for connection to the tester circuit, the number of conductors being fewer than the number of contact points on the substrate, and switching circuitry mounted on the probe support for routing the test signals between the conductors and the contact points. In another aspect, a method routes test signals between pads of a device under test and terminals of a tester circuit, the method features providing a test head in the vicinity of the device under test, the test head having a contact for each pad to be tested on the device under test and a separate conductor connecting each contact to a switching circuit located on the test head, passing test signals between the pads of the device under test and the switching circuit via the conductors, and passing test signals between the switching circuit and the terminals of the tester via wires that number fewer than half of the number of conductors on the test head.

This invention relates to high-density electronic device testing.
Testing of electronic circuits has been made much more difficult by two developments. First, manufacturers are placing more electronic components on a single integrated circuit substrate (IC). Second, multiple discrete ICs are being combined on printed wiring boards (PWBs) and multi-chip module substrates (MCMs) of ever smaller dimensions. MCMs typically include several ICs attached to a substrate. Etched interconnection wiring paths link nodes (e.g., terminals or pads) of one IC to another.
Testing of ICs may be done in situ on a semiconductor wafer, after the ICs are separated into individual dies, or after they are assembled onto PWBs or MCM substrates. The MCM substrates and PWBs may also be tested before ICs are mounted on them.
Continual miniaturization challenges existing testing equipment. One type of test performed on devices measures the integrity of node-to-node interconnections (called "nets"). The effectiveness of such testing is typically described by the number of tests per second (the speed), based on the smallest inter-node distance the measurement probe can safely access (the test probe size). As the number of nets goes up and the inter-node distance goes down, testing methods must provide higher speeds and a smaller test probe size to remain effective and cost-competitive.
One established testing method employs a so-called "bed of nails" tester, comprising an array of electrical contact points. During tests, the contact array simultaneously strikes a corresponding array of nodes. Testing of a PWB or MCM substrate for electrical continuity and shorts using a bed of nails tester proceeds rapidly in parallel, with many nodes being tested at the same time. But the size of bed of nails testers cannot be reduced indefinitely as circuit size shrinks.
Another testing method uses only one or a few probes that are rapidly moved from node to node across the circuit substrate, testing individual nodes (or small groups of nodes) serially. Testing speeds for such probe testers are limited by the velocity of the mechanical stage that holds the circuit substrate, or the probe, to a few tests per second, but research may extend this speed to 30 to 50 tests per second. One approach employs a multi-probe array (with, for example, two probe testers) that increases testing speed by performing more than one test at a time.
Researchers are also exploring the use of a focused beam of electrons to test circuit substrates. A rapidly moving electron beam alternately charges and then senses the voltage on individual circuit nets, all within a high vacuum.

Programmable high-density electronic device testing


Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance.

Integrated circuit memories use various clock signals to control the timing of internal operations. The clock signals may be generated by clock circuits included in the memories, which may include delay line circuits to adjust the timing of the clock signals relative to one another. In generating a clock signal, an input clock signal may be delayed through a delay line circuit to provide an output clock signal having a delay relative to the input clock signal. The delay line circuit ideally provides an output signal that is a true version of the input signal, but delayed. However, due to imbalances in electrical characteristics of circuits included in the delay line circuit, the input clock signal may be distorted as it propagates through the delay line circuit to provide the output clock signal. For example, a delay line circuit including circuits having imbalanced electrical characteristics may introduce duty cycle error when providing an output clock signal.
Electrical characteristics of circuits may become imbalanced due to operating conditions to which the circuits are subject during normal operation. For example, particular ones of the circuits included in a delay line circuit may be subjected to operating conditions (e.g., voltage and/or current conditions) that cause degradation of the electrical characteristics for those particular circuits. Other similar circuits also included in the delay line circuit, however, may not be subjected to the same operating condition and consequently do not degrade to the same extent. Thus, the circuits of the delay line circuit, which in theory should operate similarly, degrade unevenly. The resulting performance of the circuits subjected to the operating condition may be different than the performance of the circuits not subjected to the operating condition. The difference in performance of the circuits may cause the circuits to distort an input signal clock as it propagates through the delay line circuit to provide an output clock signal. As known, a distorted output clock signal may significantly limit memory performance.


A precipitated silica is disclosed. Said precipitated silica has a BET/CTAB in a range of 0.8-1.35; a DBP oil absorption in a range of 240-320 ml/100 g; and a CDBP coefficient (DA) in range of 0.65 to 0.9. The precipitated silica has a micro pore area ranging from 6 to 35 m2/g and a micro pore volume ranging from 0.01 to 0.06 cm3/g.

Silica is well-known for use as reinforcing filler in vulcanizable rubber mixtures, such as those used to form tyres. The reinforcing fillers used in tyre compounding are critical to achieving the performance requirements and substantially assist in strengthening the rubber network thereof, resulting in a substantial increase in stiffness, tensile strength, and resistance to abrasion. This in effect contributes in increasing the longevity of tyres while reducing the fuel consumption. The silica used in the tyre industry is generally precipitated silica, in particular characterized by its particle size, structure and surface activity.
An essential parameter for characterizing a precipitated silica is the surface area which is determined either by the adsorption of nitrogen (commonly referred to as BET (after Brunauer, Emmett and Teller) surface area) or, by the adsorption of Cetyl trimethyl ammonium bromide (CTAB) on the surface of silica (commonly referred to as CTAB surface area). BET surface area provides total surface area, whereas CTAB surface area provides external surface area of silica. The ratio of said two parameters viz. BET/CTAB provides a measure of microporosity. Pore volume and pore size distribution are also an important of better rubber to filler interaction. Also, total pore volume plays an important role for rubber penetration in the early stage of mixing.
Silica synthesis process follows the condensation of primary particles into aggregates of typical dimensions of 100-200 nm, which are the real reinforcing species in rubber compounds. As the concentration of the aggregate particles increases, an interaction between them leads to the formation of bigger agglomerates. The degree of condensation in aggregates is designated by structure, determines the inter-particle void volume and pore diameter within the aggregates. The measurement of this "structure" is based on the adsorption of dibutyl phthalate (DBP) and is measured by DBP oil absorption value. Another significant parameter which determines the dispersibility of silica is CDBP coeffficient (DA). This coefficient is calculated according to the difference in the DBP absorption between the primary uncompressed sample (DBPO) and sample after its compression at 40 MPa (Compressed DBP or CDBP), as shown in formula below:DA=1−(CDBP/DBPO)
This coefficient theoretically ranges from 0 to 1, wherein the higher the value of the coefficient, the weaker is the structure of the silica.
The Wk coefficient is the ratio of the peak height of the non-degradable particle, the maximum of which lies in the range of 1.0-100 microns, to the peak height of the degraded particles, the maximum of which lies in the range of <1 micron. The Wk coefficient is therefore a measure of the "degradability" (dispersibility) of the precipitated silica.
It is known that the properties of precipitated silica affect the reinforcement properties thereof. It necessitates the need to identify the characteristic attributes of silica suited for different requirement profile of different applications. Depending on the requirement profile, these properties may vary.
For instance, EP 0 937 755 discloses that precipitated silicas which possess a BET surface area from about 180 to about 430 m2/g and a CTAB surface area from about 160 to 340 m2/g and a BET to CTAB ratio of about 1.1 to 1.3 are particularly suitable as carrier material. However, such a precipitated silica is not meant for application in elastomer and rubber compositions.
US20030082090 discloses that precipitated silica having very different BET (≥135 m2/g) and CTAB surface areas (≥75 m2/g) while remaining above minimum values are particularly suitable as fillers.
Apart from surface area, surface activity of silica, which is usually defined in terms of Sears number influences the properties of silica. Sears number is a measurement of the concentration of silanol groups on the precipitated silica. The silanol groups on the surface of precipitated silica function as potential chemical reaction sites for a coupling reagent, which permit coupling of the silica to the elastomer matrix. The ratio of Sears Number/CTAB surface area provides the concentration of silanol groups for a given level of CTAB surface area.
U.S. Pat. No. 7,566,433 discloses precipitated silica having a relative breadth γ of pore size distribution of 4.0-10.0 (g nm)/ml, a Sears Number of 28-40 ml/(5 g), a Sears Number/CTAB ratio of 0.18-0.28 ml/(5 m2), and CTAB of 100-200 m2/g and suggests that such precipitated silica are particularly suitable as reinforcing fillers. Further, disclosed precipitated silica has a BET/CTAB ratio greater than 1.3 and a zeta potential at pH 5 from −12 to −30 mV. The precipitated silica is obtained by controlling the addition of sulphuric acid such that prevailing alkali number in the reaction medium is 30.0±0.3. Additionally, the process employs organic/inorganic salt, as a result of which it contains residues of Al2O3 ranging from 0.01 to 5%.
U.S. Pat. No. 7,790,131 discloses that highly dispersible silica having BET surface area 200-300 m2/g, CTAB surface area ≥170 m2/g, DBP number 200-300 g/(100 g), and Sears number 23-35 ml/(5 g) are particularly suited for use as a tire filler for utility vehicles, motor cycles and high speed vehicles. The precipitated silica having said properties is obtained by using organic and/or inorganic salt in the aqueous solution of 0.01 to 5 mol/l to get the desired properties.
Thus, although various grades of precipitated silica are available, these silicas have certain limitations which make their application difficult/limited. There is still a need to develop precipitated silica which have a desirable blend of properties and which could exhibit good dispersion and reinforcement when added to an elastomer.


Embodiments of the present invention provide for thresholding data elements (such as coefficients). According to one embodiment, a number of functions (including feature detector functions) can be applied to a data element to generate responses. Additionally, noise profiles can be consulted to determine an expected result for each function if the data element represents noise. An output value (e.g., after thresholding) for the data element can be generated based on the actual responses of the functions and the expected responses.

Devices like digital cameras, film scanners, x-ray machines, and radar imaging devices typically introduce noise into the resulting image. The noise can result from a variety of sources, including sampling errors, temperature-induced "dark current" noise, amplifier noise, and grain in scanned film images. The noise may appear as grain, speckles, and other artifacts. When the amount of noise is sufficiently high, it can detract significantly from the quality of the image, and so it is desirable to remove it.
With many devices, noise is not constant across the image. For instance, well-illuminated areas might have very little noise, while deep shadows may exhibit obvious noise artifacts. The relationship between noise and factors like image brightness is unique for every type of device.
Wavelet thresholding is a technique for removing noise from time-series data, images, and higher-dimensional signals, and it also has application to other areas such as compression. Typically, a wavelet transform is applied to the noisy signal, yielding a set of subbands corresponding to different frequency components of the signal. The noise coefficients in the subbands tend to have smaller magnitude than the coefficients corresponding to edges or other important features. By suppressing these small coefficients, the noise is removed, while the important features are preserved.
The idea of thresholding is not specific to wavelets. For instance, a low-pass filtered version of the original signal can be subtracted from the signal to yield a high-pass filtered version of the signal. Then thresholding can be applied to the high-pass data, and the thresholded high-pass data is added to the low-pass data to reconstruct a denoised signal.
A number of thresholding methods have been proposed in an attempt to improve the quality of thresholding results for wavelet and other noise reduction techniques, including hard thresholding, soft thresholding, sub-band adaptive thresholding, context modeling and frequency thresholding.
In hard thresholding, a coefficient is set to zero if it has absolute value less than a threshold, otherwise it is left unchanged. When used for image denoising, this approach yields undesirable visual artifacts where nearby pixels straddle the threshold value.
Some soft thresholding methods replace a coefficient x by max(0, sgn(x)·(abs(x)−t)), where t is a constant threshold value. This avoids the discontinuity in the hard thresholding function, which yields aesthetically more pleasing results for image denoising.
Hard or soft thresholding can be modified to use a different threshold value t for each subband, where each threshold value is determined by statistical analysis of each subband. In another subband-adaptive approach, Bayesian coring fits a parametric statistical model to each subband in order to exploit kurtosis or other higher-order statistics of the coefficients that can help to distinguish signal from noise. The resulting thresholding function is applied to all coefficients in the subband. That is, the function is not adaptive not within a subband.
In the context modeling approach, a generalized Gaussian distribution is assumed for the coefficients of each wavelet subband. Parameters of the distribution are fit to the coefficients, which requires a potentially time-consuming least-squares estimate of coefficients for a weighted average. The thresholding function is spatially adaptive. In other words, the behavior of the function is modified based on statistical properties of nearby coefficients. The actual threshold value for a particular coefficient is calculated based on a known mathematical relationship between the generalized Gaussian distribution and the noise variance.
The frequency thresholding approach of U.S. Pat. No. 6,741,739 appears to be, at least for conventional wavelet decompositions, algebraically similar to hard thresholding with an infinite threshold value. The method appears to reconstruct a "frequency thresholded" image from the wavelet decomposition using only the high-frequency coefficients of each wavelet level, and setting the low-pass coefficients to zero. This reconstructed image is subtracted from the original image.
Current thresholding methods suffer an additional shortcoming in that they assume that the amount of noise is either signal-independent, or dependent only on monochromatic signal levels in an image. Other methods only relate the noise level to luminance, or assume constant noise throughout a subband.


In one embodiment, an electrical power distribution apparatus is disclosed which includes a track made up of a plurality of track sections connected together by/to joints and end sections. The track sections are each provided with a slot with which a power point connector may be engaged at any point by inserting a contact member of the connector through the slot at a chosen point and then rotating the connector by 90 degrees to bring the contact member into engagement with electrical conductors of the track. The apparatus may comprise a further conduit containing conductors used to distribute communication signals.

This invention relates to apparatus for distributing electrical power and/or communication signals more particularly to an apparatus enabling an electrical power supply and/or communication signals to be provided to an electrical power or communication point respectively.
Communication signals are used in a wide sense in this application to include voice, data, text, image and/or video be it transmitted point-to-point or point-to-multipoint.
The conventional system of electrical power distribution in domestic and commercial environments is provided by power points which are installed in a wall cavity or a surface mounted power outlet at predetermined places. The location of such power points needs to be chosen in advance and often subsequent requirements can mean that the power points are provided in the wrong location and/or in insufficient numbers.
A similar disadvantage is also present for communications points used to distribute voice, data or text, for example.
It is an object of the invention to provide a more flexible apparatus for distributing electrical power and/or communication signals.

Apparatus for distributing electrical power and/or communication signals


A picture recording apparatus which can record a picture on a write-once medium having an element which specifies a first size on a recording area assigned to data saving in edit processing, and an element which subtracts the first size from a remaining amount of recording area in the write-once medium to calculate a second size secured for recording, characterized in that a recording size is managed using the second size as an upper limit of a recordable size, and that an editing area is secured using the first size as a lower limit.

1. Field of the Invention
This invention relates to a picture recording apparatus capable of reliably recording a picture on a write-once-read-many recording medium such as a DVD-R.
2. Description of the Related Art
Recording formats for digital versatile disks (DVDs) include a DVD video format used for sell DVD software and the like, and a DVD VR format used in DVD recorders and capable of edit processing.
The DVD VR format is mainly used in DVD-RAMs and DVD-RWs. The DVD-RAM and DVD-RW are rewritable media, which is convenient for users who often edit recorded pictures, but these are relatively high in unit cost.
On the contrary, DVD-Rs are relatively inexpensive media. Heretofore, recording on the DVD-R has mainly been performed in the DVD video format due to great importance placed on reproduction compatibility with DVD players, but recording on the DVD-R in the DVD VR format is also formally admitted as a standard in DVD Forum.
Many advantages are brought to the users in terms of operability and costs owing to the low-cost recording on the DVD-R in the DVD VR format that allows flexibility in editing.
However, the DVD-R is a write-once medium, so that a recording area of a disk is consumed by performing recording and editing.
This leads to such a problem that it might be impossible to implement editing because a remaining amount of recording area is not sufficient after a large volume of data has been recorded on the DVD-R.


A valve characteristic estimation device applied to an internal combustion engine provided with a valve characteristic adjustment mechanism for varying a valve characteristic including at least one of a valve open period and a lift amount of an intake valve. The estimation device detects intake air amount and intake air pressure of the engine, and calculates an estimated value for the valve characteristic based on the detected values of the intake air amount and the intake air pressure. Accordingly, the valve characteristic of the intake valve is accurately estimated.

The present invention relates to a valve characteristic estimation device for an internal combustion engine provided with a valve characteristic adjustment mechanism for varying valve characteristics including at least one of the valve open period and lift amount of an intake valve. The present invention further relates to a controller for an internal combustion engine provided with such a valve characteristic adjustment mechanism that controls the internal combustion engine based on the detected value from a sensor for detecting the current status of the value of the valve characteristic.
A valve characteristic adjustment mechanism is a well-known mechanism incorporated in an internal combustion engine. The valve characteristic adjustment mechanism variably adjusts a valve characteristic such as the valve open period and lift amount of an intake valve according to the operation state of the engine.
In an internal combustion engine provided with such a valve characteristic adjustment mechanism, the valve open period or lift amount of the intake valve is adjusted to change the condition of the air that flows into the corresponding cylinder. Such an internal combustion engine includes a sensor for detecting the operating status of the valve characteristic adjustment mechanism. More specifically, the sensor detects the current valve open period and lift amount of the intake valve. The internal combustion engine sets a target opening degree for the throttle valve (target throttle opening degree) based on the detection results of the sensor. The amount of overlap of the intake and exhaust valves also changes when the valve open period or the lift amount of the intake valve is changed. Thus, the internal combustion engine, which includes the valve timing adjustment mechanism for variously adjusting the valve timing of the intake valve, also sets a target value for the valve timing (target valve timing) based on the detection results of the valve open period and the lift amount of the intake valve. Further, the valve characteristic adjustment mechanism, which adjusts the valve open period and the lift amount of the intake valve, is feedback-controlled so that the actual valve characteristic detected by the sensor coincides with the target valve characteristic that is set in accordance with the operation state of the engine.
If, for example, an abnormality occurs in the sensor and direct detection of the valve open period and the lift amount of the intake valve are disabled, the engine control based on the detected values of the valve open period and the lift amount of the intake valve may not be executed properly. More specifically, the target throttle opening degree or the target valve timing may not be set correctly, or the feedback control of the valve characteristic adjustment mechanism may not be executed correctly. As a result, the engine output may not follow the driver's accelerator operation and the amount of intake air may become insufficient. In some cases, this may result in a misfire and make it difficult to drive the vehicle to a safe place. To avoid such a situation, it is preferable that the internal combustion engine have a means for determining the valve open period and lift amount of the intake valve even when direct detection of the valve open period and lift amount of the intake valve with the sensor is disabled.
Conventional methods for estimating the valve characteristic, such as the valve open period and the lift amount of the intake valve, without relying on direct detection with a sensor are described, for example, in Japanese Laid-Open Patent Publication Nos. 2000-282901 and 2000-314329. The methods described in these publications use a predetermined table associated with the engine speed, the intake air amount, and the valve characteristic. By referring to the table, an estimated value of the valve characteristic of the intake valve is calculated based on the detected intake air amount and engine speed. By estimating the valve characteristic indirectly from the detected engine speed and intake air amount, engine control may be continuously executed based on the roughly determined valve characteristic of the intake valve even if direct detection of the valve characteristic with the sensor is disabled. This enables the vehicle to be driven to a safe place.
However, recent internal combustion engines for vehicles execute more sophisticated intake air control. When employing the conventional methods described above in an internal combustion engine that executes such sophisticated intake air control, the valve characteristic of the intake valve cannot be accurately estimated.
For example, in an internal combustion engine provided with the above valve characteristic adjustment mechanism, the intake air amount may be adjusted not only by adjusting the throttle opening degree but also by adjusting the valve characteristic of the intake valve. Thus, the same intake air amount may be realized by various combinations of the throttle opening degree and the valve characteristic. From such various combinations, the optimum combination of the throttle opening degree and the valve characteristic may be selected in accordance with the engine operation state to obtain a desired intake air amount. This enables the execution of a more sophisticated intake air control. Under such sophisticated intake air control, the throttle opening degree is set differently depending on the operation state of the engine even when the engine load and engine speed are constant. This changes the condition of the intake air in accordance with the set throttle opening degree. Further, if the internal combustion engine is provided with a valve timing adjustment mechanism for variably adjusting the valve timing of the intake valve in accordance with the engine operation state, the condition of the intake air changes in accordance with the operating status of the valve timing adjustment mechanism. In this way, when there are a large number of factors that change the condition of the intake air, the valve characteristic, such as the valve open period and the lift amount of the intake valve, may not necessarily be directly determined from the engine speed and the intake air amount. Thus, the above conventional methods cannot accurately estimate the valve characteristic of the intake valve.

Valve characteristic estimation device and controller for internal combustion engine


A digital temperature compensation oscillator by which its AFC operation to a receive signal cannot be disturbed by temperature compensation operation. A digital temperature compensation oscillator comprises a temperature sensor, an address creating section, a ROM, latching means, and a voltage-controlled crystal oscillator. The temperature sensor produces an output signal varied according to ambient temperatures. The address creating section converts an output from the temperature sensor into a signal and then creating it as a ROM (read-only memory) address. The ROM stores a control voltage to compensate a frequency variation due to ambient temperatures of a voltage-controlled crystal oscillator. The latching means holds or passes data output from the ROM according to an external control signal. The D/A converter produces a control voltage for the voltage-controlled crystal oscillator according to the latching means. The voltage controlled crystal oscillator is fine adjusted based on two control voltages including the output signal from the D/A converter and an external analog AFC signal.

The present invention relates to an arrangement of a reference frequency oscillation source, which is used in a base station with high frequency precision and terminals for radio communications, capable of reducing variations in oscillation frequency due to its temperature changes or secular changes. The present invention also relates to a method for controlling the novel arrangement.
The oscillation frequency of a crystal oscillator is decided by the inherent frequency of the piezoelectric crystal resonator contained therein. The piezoelectric crystal has its stable inherent oscillation frequency and can advantageously provide a stable oscillator. This crystal element is particularly used as a time or frequency reference source in radio communications apparatuses.
In recent years, large capacity communication systems have been developed to respond to an increasing number of users of radio communications typically including cellular telephones. Such large capacity communication systems require oscillators with a frequency error of, for example, less than 1 ppm. There are strong demands for time or frequency reference sources with higher precision. Particularly, the direct sequence code division multiple access (DS-CDMA) system that basically adds receive signals in phase is used to realize excellent noise-resistance and anti-interference. However, an error in frequency between a transmitter and a receiver causes the addition in phase to fail, thus resulting in remarkable characteristic degradation. In general, the temperature compensation crystal oscillator (TCXO) for a frequency standard using a simple analog technique can realize a frequency precision of about 3 ppm. However, in the case of the DS-CDMA system, since the noise-resistance and anti-interference characteristics can be advantageously improved by increasing the number of symbols added in phase, the frequency reference with a high precision of less than 1 ppm is sometimes needed. In that case, the temperature compensation in an analog fashion leads to a complicated circuit configuration, thus increasing the manufacturing costs and the space for assembly. To solve such problems, JP-A 5605/1990, for example, discloses the method of storing data compensating the temperature characteristic indicating a frequency change to a frequency control signal of a crystal oscillator into a ROM, instead of a simple temperature compensation in an analog fashion, and then performing the digital temperature compensation based on the temperature measured with a temperature sensor.
FIG. 3 illustrate the configuration of the conventional digital temperature compensation crystal oscillator disclosed in JP-A 5605/1990. Referring to FIG. 3, a temperature sensor 1 measures the ambient temperature of the voltage controlled crystal oscillator 9. An address creating unit 2 creates an address at which corresponding compensation data is stored. A read-only memory (ROM) 3 previously stores compensation data over the entire temperature range for each crystal oscillator and outputs the compensation data for an address designated by the address creating unit. Successively, the D/A converter converts compensation data output from the ROM 3 into an analog signal. The resonator circuit 7 is controlled with the analog signal to compensate the oscillation frequency of the oscillator 8. Finally, the oscillator 8 outputs the reference frequency signal 800. The prior art publication further discloses the method of compensating the oscillation frequency by means of plural pairs of an analog switch and a capacitor, without using the D/A converter 6. The detail is not described here.
On the other hand, the automatic frequency control (AFC) is listed as a method of compensating errors in frequency between a transmitter and a receiver using the receive signal on the receiver side. There are various AFC methods. The JP-A 79145/1996, for example, discloses the frequency compensating method using two receiving systems. One desired wave extracting filter is just set to the signal band to be received while the other desired wave extracting filter is set to a broader band containing a variation in center frequency due to a frequency error between the transmitter and a receiver plus the signal band to be received. Thus, by preventing the attenuation of a receive signal power due to the desired wave extracting filter at the presence of a frequency error, the frequency pulling operation can be performed under the AFC even if the frequency error is large.
Moreover, JP-A 245563/1995 discloses another frequency compensating method. According to this method, the frequency offset data for several patterns stored in a ROM are swept on trial at the time of starting the AFC while a frequency error between a transmitter and a receiver is measured. Trial and error is repeated with various types of frequency offset data until the frequency error falls finally within the range in which the normal AFC operation can be executed.
The configuration disclosed in JP-A 5605/1990 performs only the step of compensating oscillation frequency variations due to temperature changes. Since the frequency error between a transmitter and a receiver has a relative value, the transmitter side with a frequency precision may sometimes need AFC to compensate the frequency error therebetween.
In the DS-CDMA system, the receiving operation is started with a certain frequency error (e.g. less than 1 ppm) between a transmitter and a receiver. Then, the relative error to the frequency of the transmitter must be controlled to a smaller value (e.g. less than 0.1 ppm) by performing the AFC operation using the receive signal received by a receiver.
On the condition that the frequency precision of a transmitter is so high that the frequency error can be ignored to an actual frequency, there is no problem if the frequency compensation of the configuration disclosed in JP-A 5605/1990 can improve the frequency precision of a receiver so as to ignore the frequency error to the actual frequency. However, it is difficult to actually satisfy such a condition because the amount of compensation data stored into the ROM 3 increases and the precision of the temperature sensor 1 is insufficient.
Even if the compensation of a variation in oscillation frequency due to temperature changes is merely combined with the AFC operation by a receive signal, the oscillation frequency varied due to ambient temperature changes is compensated during the AFC operation by the receive signal. As a result, the high precision frequency compensation under the AFC by the receive signal may be carried out in vain.
In addition, the frequency variation due to aging may cause a frequency error when the frequency variation caused by a temperature change is compensated with a preset compensation value, so that the receiving operation cannot be performed under the worst conditions.
According to, the configuration disclosed in, for example, JP-A 79145/1996, when there is a frequency error between a transmitter and a receiver, the desired wave extracting filter with the filtering characteristics fully matched to the band of a signal to be received attenuates its output. The output of the desired wave extracting filter with a slightly broader band contains undesired band noise components. Hence, the S/N ratio of the configuration is deteriorated. Moreover, in the DS-CDMA system, when the frequency error is large to some extent, the receive signal cannot be demodulated, so that even the AFC control cannot be performed.
According to JP-A 245563/1995, the configuration decides on trial the compensation amount for a frequency error without using information from the temperature sensor. Hence, a long period of time is taken to begin the frequency pulling operation under the AFC operation.

Compensated frequency source with latched temperature compensation, and method for it's control


This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.

The continuous scaling of transistor size makes it possible to integrate more and more signal processing functionalities into the same silicon with less area overhead. Employing extensive digital signal processing technologies, a digital radio processor (DRP) can process RF signals in the digital domain as much as possible to provide better performance with reduced cost. Based on an all digital PLL (ADPLL) architecture, a digital radio processor integrates all necessary blocks including RF, analog/mixed-signal and digital ones to provide a single-chip solution for GSM/GPRS/EDGE (GGE) and WCDMA applications.
The DRP receiver chain provides the signal processing for the received RF signals and includes both analog and digital blocks. Digital receiver (DRX) block provides RF signal processing in the digital domain. FIG. 1 illustrates the DRX architecture 100 including 9 blocks in the feed-forward path for GGE application. The DRX operates at two clock domains: channel-dependent ckvd64; and fixed ckres4X. These clock domain are bridged by the resampler (RES) 101. The Rate Change Filter (RCF1) 102 and Pre-Filter (PREF) 103 are located before RES 101. These blocks are driven by the ckvd64 clock derived from digital local oscillator (DLO). The other blocks operate at channel independent ckres4X clock domain and include a decimation finite impulse response (FIR) filter (RES) 104, IQMC computation engine (IQMC_CE) 105, residual offset cancellation infinite impulse response (IIR) filter (ROC_IIR) 106, zero-IF filter (ZIF) 107, channel select filter (CSF) 108 and droop cancellation filter (DCF) 109. The ROC_IIR can also be configured as high-pass (HPF) or low-pass (LPF) filters. The connection between these filters should be reconfigurable and it is currently implemented by a dedicated multiplexer block in DRPe. These blocks are referred as Fixed-rate Digital RX (FDRX) data path.
The current fixed-rate filtering blocks in the receiver chain (FDRX) of the digital radio processor (DRP) is implemented using fixed logic with very limited programmability. This makes it difficult to extend to support multi-standard wireless applications including GSM/GPRS/EDGE/WCDMA. Simply modifying the current GGE (GSM/GPRS/EDGE) FDRX by increasing the clock frequency cannot meet the WCDMA's sampling rate of 7.84 Msps without architectural change in those computationally-intensive blocks. Employing multiple dedicated data paths to cover these different standards would increase the area in proportion to the number of data paths. The flexibility problem needs to be resolved for the future multi-standard DRP products since providing both flexibility and performance is important for the low-cost 2G/2.5G/3G radio processors targeting the emerging market.
Currently the FDRX blocks shown in FIG. 1 are implemented by a fixed logic architecture. Each block operates at multiple clock domains to meet the data rate requirement of 1.083 Msps in GGE application. In this application specific integrated circuit (ASIC) each block is highly crafted to achieve the maximum efficiency in performance, area and power. The biggest pitfall of the fixed-logic architecture is the lack of configurability. Only limited intra-block connectivity is provided by the hardware multiplexes. This becomes worse when the DRP goes into 3G, where both 16-bit GGE and 8-bit/16 bit WCDMA modes are supported. Although WCDMA has less data width compared with GGE, its data path have different configurations which brings more complexity to the fixed-logic architecture. Supporting multiple wireless protocols on the same platform is becoming a natural trend with an increasing number of wireless applications. This requires maximum reconfigurability of FDRX to meet the data rate requirement.
Processor-based architecture has good flexibility and is controlled by instructions which share the common instruction fetch and decode logic. The execution of each instruction takes place in a heterogeneous functional unit. Most RISC processors are based on a load-store architecture, where memory access can only be implemented by a load (LD) instruction or a store (ST) instruction. This architecture simplifies the memory interface and the instruction set to achieve high operating frequency and throughput.
The trade-off in the general purpose processors is flexibility at the sacrifice of performance. In an experiment the GGE FDRX data path including the seven blocks illustrates in FIG. 1 was ported onto a 32-bit 8-issue high-performance general purpose DSP, the Texas Instruments TMS320C6201. The simulated sustaining data rate was only 90.49 Ksps, which is 11.96 times lower than the GGE requirement of 1.083 Msps under a 200 MHz clock frequency without any hardware customizations. Some customization of the processor's data path with application specific instructions is required to meet the performance requirement. This reduces the cycle count for computations in the FDRX critical path needed to meet the performance requirement. The customization of instructions doesn't reduce the processor's flexibility, but it provides a highly reconfigurable FDRX platform for the multi-mode 3G applications.

Application specific instruction set processor for digital radio processor receiving chain signal processing


A tooling system includes a plurality of elements arranged in an array, each element being moveable longitudinally relative to the other elements in the array and having a first end. The system further includes a device, adapted to adjust the relative longitudinal positions of the elements such that the free ends of the elements define approximately a desired surface contour and a device for retaining the elements in their adjusted positions. The first end of each element may be provided on a machinable portion removably mounted to a base portion, the arrangement being such that the free ends of the elements can be machined to produce the desired surface contour. The tooling system may include a plurality of elements arranged in an array, the elements of the array being movable between a closed position in which the elements contact one another and are secured in position, and an open position in which the elements of the array are spaced apart and are capable of vertical movement relative to one another, wherein it also includes a drive device for opening and closing the array.

The manufacture of a tool, or pattern, has conventionally involved machining from a billet of material, an additive process such as casting from a mould, sculpting or fettling, or fabrication, for example from sheet metal. For large scale tools, typically required in the aerospace and automotive industries, the length of time in preparing tools by such methods is slow, and is prohibitively expensive. This is due in part to the large size of the billets of material required, which must be committed to the tools in their manufacture, and which may have to be ordered months in advance of their supply.
Furthermore, the amount of skilled labor time and material required in producing a tool conventionally has made it uneconomical to produce a tool for limited volume production, for example in product development, limited batch production and mass customization.
In order to overcome these problems, reconfigurable modular tools have been developed, typified by that disclosed in U.S. Pat. No. 5,846,464. In the tool disclosed in this patent, an array of vertically adjustable pins are mounted on a drive base, such that the height of each pin above the base can be individually set. A flexible surface, or face sheet, is attached to flexible supports, which are mounted at the ends of the pins. The surface contour of the face sheet can therefore be set to a desired contour by adjusting the individual heights of the pins. The adjustments are controlled automatically through a computer, which is pre-programmed with the desired contour. When the tool is in use, the face sheet surface acts either as a primary tooling surface, or as a secondary tooling surface for producing a pattern or mould, for example, for casting.
Reconfigurable tools of the kind described are suitable for some applications, but for other applications do not have sufficient robustness and/or definition in the tooling surface. The pins which support the flexible face sheet are spaced apart, and do not lie in the plane of the desired surface contour. Therefore the face sheet surface is only a point to point approximation of the desired surface contour. The resolution of the surface is dependent on the density, number and size of pins in the tool array, but as the density of the pins increases, and their size reduces, it becomes increasingly difficult to adjust the positions of the pins.
The combined strength of the pins is also much less than the strength of a solid tool, and therefore the tool is not strong enough for the majority of tooling operations. Furthermore, the aspect ratio, that is, the range of depth in the tooling surface in comparison to its width, is limited by the amount the face sheet can deform.
It has also been proposed in GB patent No. 868,162 to provide a device for supporting workpieces during machining, including a holder in the form of a housing frame or body having an array of vertically adjustable plungers mounted therein, together with thrust-transmitting, vertically-disposed packing pieces between these plungers, and a device for exerting pressure laterally to the plungers through the packing pieces to clamp them in adjusted position.


A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set of Taylor's series coefficients for each segment of the input value range. Other aspects of the invention are methods for determining preferred parameters for elements of such a circuit, a circuit designed in accordance with such a method, and a system (e.g., a pipelined graphics processor) for and method of pipelined graphics data processing using any embodiment of the circuit. The preferred parameters are determined by minimizing the circuit's size subject to constraints on input and output value format and output accuracy, assuming a specific function to be approximated and a specific degree for the approximation but allowing variation of parameters such as coefficient width and number of input value range segments.

In three dimensional graphics, surfaces are typically rendered by assembling a plurality of polygons in a desired shape. The polygons (which are typically triangles) are defined by vertices, and each vertex is defined by three dimensional coordinates in world space, by color values, and by texture coordinates and other attributes.
The surface determined by an assembly of polygons is typically intended to be viewed in perspective. To display the surface on a computer monitor, the three dimensional world space coordinates of the vertices are transformed into screen coordinates in which horizontal and vertical values (x, y) define screen position and a depth value z determines how near a vertex is to the screen and thus whether that vertex is viewed with respect to other points at the same screen coordinates. The color values define the brightness of each of red/green/blue (r, g, b) color at each vertex and thus the color (often called diffuse color) at each vertex. Texture coordinates (u, v) define texture map coordinates for each vertex on a particular texture map defined by values stored in memory.
The world space coordinates for the vertices of each polygon are processed to determine the two-dimensional coordinates at which those vertices are to appear on the two-dimensional screen space of an output display. If a triangle's vertices are known in screen space, the positions of all pixels of the triangle vary linearly along scan lines within the triangle in screen space and can thus be determined.
Typically, a rasterizer uses (or a vertex processor and a rasterizer use) the three-dimensional world coordinates of the vertices of each polygon to determine the position of each pixel of each surface ("primitive" surface") bounded by one of the polygons.
The color values of each pixel of a primitive surface (sometimes referred to herein as a "primitive") vary linearly along lines through the primitive in world space. A rasterizer performs (or a rasterizer and a vertex processor perform) processes based on linear interpolation of pixel values in screen space, linear interpolation of depth and color values in world space, and perspective transformation between the two spaces to provide pixel coordinates and color values for each pixel of each primitive. The end result of this is that the rasterizer outputs a sequence red/green/blue color values (conventionally referred to as diffuse color values) for each pixel of each primitive.
One or more of the vertex processor, the rasterizer, and a texture processor compute texture coordinates for each pixel of each primitive. The texture coordinates of each pixel of a primitive vary linearly along lines through the primitive in world space. Thus, texture coordinates of a pixel at any position in the primitive can be determined in world space (from the texture coordinates of the vertices) by a process of perspective transformation, and the texture coordinates of each pixel to be displayed on the display screen can be determined. A texture processor can use the texture coordinates (of each pixel to be displayed on the display screen) to index into a corresponding texture map to determine texels (texture color values at the position defined by the texture coordinates for each pixel) to vary the diffuse color values for the pixel. Often the texture processor interpolates texels at a number of positions surrounding the texture coordinates of a pixel to determine a texture value for the pixel. The end result of this is that the texture processor generates data determining a textured version of each pixel (of each primitive) to be displayed on the display screen.
A texture map typically describes a pattern to be applied to a primitive to vary the color of each pixel of the primitive in accordance with the pattern. The texture coordinates of the vertices of the primitive fix the position of the vertices of a polygon on the texture map and thereby determine the texture detail applied to each of the other pixels of the primitive in accordance with the pattern.
FIG. 1 is a block diagram of a pipelined graphics processing system that can embody the present invention. Preferably, the FIG. 1 system is implemented as an integrated circuit (including other elements not shown in FIG. 1). Alternatively at least one portion (e.g., frame buffer 50) of the FIG. 1 system is implemented as a chip (or portion of a chip) and at least one other portion thereof (e.g., all elements of FIG. 1 other than frame buffer 50) is implemented as another chip (or portion of another chip). Vertex processor 10 of FIG. 1 generates vertex data indicative of the coordinates of the vertices of each primitive (typically a triangle) of each image to be rendered, and attributes (e.g., color values) of each vertex.
Rasterizer 20 generates pixel data in response to the vertex data from processor 10. The pixel data are indicative of the coordinates of pixels for each primitive, and attributes of each pixel (e.g., color values for each pixel and values that identify one or more textures to be blended with each set of color values). Rasterizer 20 asserts the pixel data to pixel shader 30.
Typically, pixel shader 30 combines the pixel data received from rasterizer 20 with texture data and may execute shader programs. For example, one or more texture maps (and a set of texels of each texture map), or no texture maps, are specified for each pixel, and pixel shader 30 implements an algorithm to generate a texel average in response to the specified texels of each texture map (by retrieving the texels from memory 25 coupled to pixel shader 30 and computing an average of the texels of each texture map) and to generate textured pixel data by combining the pixel with each of the texel averages. In typical implementations, pixel shader 30 can perform various operations in addition to (or instead of) texturing each pixel, such as one or more of the well known operations of format conversion, input swizzle (e.g., duplicating and/or reordering an ordered set of components of a pixel), scaling and biasing, inversion (and/or one or more other logic operations), clamping, and output swizzle.
When pixel shader 30 has completed all required processing operations on a quantity of pixel data, it asserts the updated (e.g., textured and/or programmably shaded) pixel data to pixel processor 40, and pixel processor 40 performs additional processing on the updated data. In variations on the system of FIG. 1, pixel processor 40 is omitted. In this case, pixel shader 30 is coupled directly to frame buffer 50, pixel shader 30 performs all required processing of the pixels generated by rasterizer 20, and pixel shader 30 is configured to assert the fully processed pixels to frame buffer 50. Pixel processor 40 and/or pixel shader 30 typically include the OpenGL® "fragment operations."
Although pixel shader 30 is sometimes referred to herein as a "texture processor," in typical implementations it can perform various operations in addition to (or instead of) texturing each pixel, such as one or more of the conventional operations of culling, frustum clipping, polymode operations, polygon offsetting, and fragmenting. Alternatively, texture processor 30 performs all required texturing operations and pixel processor 40 performs some or all required non-texturing operations for each pixel.
In typical implementations of pipelined (and other) graphics processors, there is a need to perform reciprocal and reciprocal square root operations (as well as other mathematical operations) on data values. Such operations are commonly performed in vertex processing, pixel shading, and pixel processing units of graphics processors.
Reciprocal and reciprocal square root functions having typically been implemented in hardware using variations of the conventional technique known as Newton-Rapheson iteration. However, the inventors have recognized that generation of the reciprocal (or the reciprocal of the square root) of an input value in pipelined fashion using Newton-Rapheson iteration would require pipelined processing circuitry having an undesirably large number of pipeline stages and an undesirably large footprint (in the case that the processing circuitry is implemented as an integrated circuit or portion of an integrated circuit).

Method and system for performing pipelined reciprocal and reciprocal square root operations


A device for leveling a laser transmitter is provided. An optical position sensor is used to measure the position of a compensator assembly. The compensator assembly automatically adjusts the position of the laser beam once the compensator assembly is within a specified range of level. Once the compensator assembly is within the specified range, the compensator assembly optically adjusts the laser beam so that it is plumb. A leveling device may be used to level the laser transmitter in response to the position of the compensator assembly as measured by the position sensor.

The present invention generally relates to a laser beam projection device and, in particular, to an arrangement for automatically leveling the device.
Laser light systems have been employed in numerous surveying and construction applications. In one such system, a laser light transmitting device provides a rotating laser beam which establishes a reference plane. In effect, the rotating laser beam is used to define a plane of light that acts as either a horizontal elevational reference or a sloped elevational reference, as desired, over an entire work area. The laser light is either detected by the naked eye or by one or more laser beam detectors, placed at considerable distances from the transmitting device. Various construction tasks may be performed based on visual perception of the laser light. Similarly, detectors may be used to intercept the rotating laser beam and determine a desired elevation and grade at selected points throughout the work area.
In the laser light transmitting device, the plane of light is produced by projecting the beam generally upward and then deflecting the beam ninety degrees within a pentaprism or pentamirror assembly. The pentaprism assembly is rotated about a vertical axis within the transmitting device to cause the beam to rotate, thereby defining the reference plane. The laser light transmitting device must be substantially level in order to function properly and to define the desired reference frame accurately. The beam of light which is projected upward will be substantially plumb with respect to the ground when the laser transmitting device is substantially level.
Prior art devices have included standard leveling vials attached to the housing of the laser light transmitting device to indicate to the transmitter operator that the transmitter is badly misaligned, and to permit manual adjustment of the transmitter to a more level position. Such leveling vials include a bubble suspended within a liquid medium, with the bubble position providing a rough indication of the degree of level of the housing. Leveling screws are included on the housing which may be adjusted by the operator to level the base. An automatic compensator may also be used to optically compensate for slight misalignments of the housing. The compensator includes a compensator cup which is suspended by thin wires within the housing, and a compensating lens in the cup, positioned in the path of the upwardly projected laser light. The compensator will automatically shift laterally so as to adjust the position of the laser beam so that it has a plumb orientation with respect to the ground as it emerges from the compensator. To function properly, the compensator must be within a certain degree of level, e.g. 12 minutes, in order to swing freely so as to have any effect on the orientation of the laser beam.
Such prior art devices are disadvantageous because the initial leveling of the base is dependent, in part, upon the skill of the operator. Manual leveling of the laser light transmitting device within 12 minutes is also tedious and time consuming for the operator. In addition, since the leveling operation is completed with respect to the base, the alignment between the housing and the compensator must be precise.
Other prior art systems include automatic leveling devices which attempt to level the laser light transmitting device based on a signal from an electronic leveling vial. The electronic leveling vials are similar to the standard leveling vials except the electronic leveling vials emit a signal representative of the relative position of the vial. The signal is then used to level the base of the laser light transmitting device to within 12 minutes so that the compensator may then adjust the position of the laser beam to a plumb orientation. Such systems are disadvantageous because the leveling activities are completed with respect to the base instead of the compensator. For accurate leveling so that the compensator is within 12 minutes of level, the alignment between the compensator and the housing must be precise.
Accordingly, there is a need for an accurate and automatic system for leveling a laser light transmitter which is independent of the alignment between the compensator and the housing.

Position leveling sensor for a laser transmitter


A terrestrial receiver at a premises includes a plurality of antennas and a corresponding plurality of tuners. The terrestrial receiver receives terrestrial television signals via the plurality of antennas and the plurality of tuners and diversity combines a corresponding plurality of terrestrial television channels within the received terrestrial television signals, for example, based on control signals received from one or more customer premises equipment (CPE). The terrestrial receiver processes the diversity combined corresponding plurality of terrestrial television channels and communicates the processed and diversity combined corresponding plurality of terrestrial television channels to the one or more CPE. The diversity combined corresponding plurality of terrestrial television channels may be remodulated, and converted to corresponding analog signals prior to being communicated to the one or more CPE. The diversity combined corresponding plurality of terrestrial television channels may be demodulated and converted to intermediate frequency signals prior to being communicated to the one or more CPE.

Existing methods and systems for delivery of non-satellite content (e.g., terrestrial content) to satellite customers can be costly, cumbersome, power hungry, expensive, inflexible and inefficient.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Method and system for diversity combining for high-performance signal reception


Relative directions of excitation and photoreceiving optical systems are so set that an angle formed by optical axes thereof in the air is 14.degree., and an eyeball is fixed in such a direction that its ocular axis divides the angle formed by the optical axes into two equal parts. On a light incidence side of a one-dimensional solid-state image pickup device of the photoreceiving optical system, a slit is arranged for inputting measuring light components generated from portions of the eyeball having different depth positions on an excitation light beam in photoelectric conversion elements of different positions of the image pickup device. The measuring light components generated from the respective portions of the eyeball parallel to the optical axis are incident upon the one-dimensional solid-state image pickup device through the slit and simultaneously detected, so that the positions of the photoelectric conversion elements and measuring light component generating positions at the eyeball correspond to each other.

1. Field of the Invention
The present invention relates to an apparatus for measuring intraocular substances by irradiating an eyeball with an excitation light beam from an excitation optical system and detecting measuring light components including at least either scattered light or fluorescence generated from the eyeball by a photoreceiving optical system.
2. Description of the Background Art
Vitreous fluorophotometry (VFP) is performed as an examination of quantitatively testing the function of a blood-ocular barrier by measuring intraocular fluorescence as a method of irradiating the eyeball with excitation light and obtaining information from scattered light or fluorescence from the eyeball.
In order to diagnose diabetes mellitus or judge necessity for insulin administration, blood-sugar level must be measured. Although a method of collecting blood for measuring the blood-sugar level is correct, this causes the patient pain, and the examination is troublesome and requires a long time.
Therefore, various methods of noninvasively measuring intraocular substances on the basis of optical information from eyeballs are studied. For example, methods of irradiating eyeballs with excitation light and measuring the blood-sugar levels on the basis of information obtained therefrom are studied. One of such methods is a method of irradiating the crystalline lens with excitation light, receiving back-scattered light thereof, separating the same into fluorescence and Rayleigh light through a spectroscope or a dichroic beam splitter, obtaining information allowing diagnosis of diabetes mellitus from a value obtained by normalizing the fluorescence intensity with the Rayleigh light intensity, and diagnosing diabetes mellitus, cataract or still another disease on the basis thereof (refer to U.S. Pat. No. 5,203,328).
In another method, infrared absorption by the crystalline lens or the refractive index of visible light is measured for obtaining the blood-sugar level in the crystalline lens on the basis thereof (refer to Japanese Patent Laying-Open Gazette No. 51-75498 (1976)). In still another method, aqueous humor filling up a clearance between the cornea and the crystalline lens is irradiated with plane polarized light so that the blood-sugar level is obtained by measuring the angle of rotation of the polarization axis or the refractive index (refer to U.S. Pat. No. 3,963,019).
A method of obtaining a cholesterol value as another vital substance is also proposed. In this method, aqueous humor is irradiated with excitation light, so that the intensity of scattered light therefrom or the mobility of protein which is a scatterer is measured for obtaining the cholesterol value (refer to U.S. Pat. No. 4,836,207).
Obtained information varies with the measured eyeball portion such as the vitreous body, the crystalline lens, the aqueous humor or the cornea. In order to obtain information from positions of the eyeball having different depths, therefore, an optical system is so scanned that places for generating fluorescence etc. to be received move along the depth direction of the eyeball (refer to "Ringan" Vol. 38, No. 11, 1195-1199 (1984)).
When the optical system is scanned for measurement for obtaining information from eyeball positions having different depths and the eyeball moves during the scanning, the depths of the measured portions are also changed and no correct measurement can be performed.
Further, the optical system is disadvantageously complicated and increased in size due to the scanning.

Measuring apparatus for intraocular substance employing light from eyeball


An apparatus for assisting in training players of golf includes a platform and a first coplanar foot support member and a second coplanar foot support member on the platform, with the first coplanar foot support member being fixed in position and the second coplanar foot support member able to be moved laterally and linearly on the platform relative to the first coplanar foot support member when a golf player places one foot on each of the two coplanar foot support members. A biasing device causes the second coplanar foot support member to be adjacent the first coplanar foot support member, so that in the absence of an externally applied force, the second coplanar foot member remains adjacent to the first coplanar foot support member.

Over the years there have been many inventions which have been devised to teach or correct a golfer's swing. The golf swing can be broken down into three basic phases: take-away, impact and follow through. Balance is essential in the follow through of a golf swing and is generally achieved with proper swing mechanics which occurs in the first two phases of the golf swing. For this to occur it is imperative that the lower part of the body be stabilised to prevent any unwanted vertical motion.
Erroneous swing mechanics can lead to an increase incidence of injury that is resultant from uncontrolled and misdirected shots. An incorrect balance of weight in the lower part of the body can cause a variety of errant shots including fat (striking ground first) and thin (striking only ball and no turf) shots. Other common swing faults pertinent to golfers, include right knee lateral sway, vertical motion, excessive lower body motion in the short game ie. Chipping and putting, and extra long swings.
Current devices that attempt to control the movement of the player's body are generally overly restrictive, complicated and inaccurate in the movement defined. The devices are designed to restrict the body movement of the player by securing or immobilising various parts of the body such as the head, waist, shoulders, arms or legs. However, often the devices are cumbersome and awkward including multi-strap hand or leg braces that are uncomfortable and require a fair amount of time to adjust their position. In addition, whilst these may support the players and guide their movement, the devices hinder the development and movement of supporting muscles which would otherwise occur if the player were self supported.
The previous devices fail to provide a method whereby the swing of a golfer can be easily and conveniently controlled in a round of golf, such that the golfer can adjust the stance throughout a round of golf depending on the characteristics of a particular golfer and environmental conditions such as variations in the inclination of a course, without the need to readjust settings or positioning of the device.