A lubrication apparatus of a fuel pump driven by a fuel pump drive cam, which lubricates a tappet moving reciprocally at an interior circumference of a fuel pump adaptor and the fuel pump operating the tappet, may include a cylinder head provided with a camshaft, an oil supplying passage formed in the camshaft as a hollow type so as to take oil to the interior of the camshaft, at least an oil branch passage formed to a cam lobe of the fuel pump drive cam so as to be communicated with the oil supplying passage, and a circular groove formed at the interior circumference of the fuel pump adaptor and corresponding to an injection direction of the oil supplied from the at least an oil branch passage.

1. Field of the Invention
This present invention relates to a lubrication structure of an engine, and more particularly to a fuel pump lubrication device that is capable of effectively lubricating a tappet of the engine, a tappet roller, and a cam.
2. Description of Related Art
Technologies for a gasoline direct injection (GDI) engine have been studied in order to improve fuel consumption and performance of the engine.
The GDI engine technologies are methods in which only air is drawn into the combustion chamber and is compressed and then fuel is injected therein, while in the case of a conventional gasoline engine, power is generated in a period of an intake stroke, a compression stroke, an ignition stroke, and an exhaust stroke process of an air/fuel mixture.
Such a method is similar to a compressed ignition engine method.
Due to a high compression ratio of the GDI engine, a high compression ratio that is capable of exceeding a limit of a usual gasoline engine results in maximization of fuel consumption.
The GDI engine depends on a high fuel pressure, and a high performance fuel pump is required.
The fuel pump is mechanically driven by a cam so as to operate a tappet, and friction inside the fuel pump is generated.
A great deal of friction occurs in the fuel pump due to the high pressure of the fuel.
Therefore, a lubrication device of the fuel pump for compressing the fuel in the GDI engine has been studied in order to improve durability and performance of the GDI engine.
To solve the problems, as an example, a method of lubricating the cam with oil stored in a predetermined space when a camshaft for the fuel pump is rotated is used.
Such a method has a merit of simplifying the structure, but it is difficult to lubricate throughout the fuel pump, and it is difficult to lubricate it at a slanted surface.
Further, there is a method, as another example, which forms an oil hole at the cam so as to flow oil therein.
However, the method mentioned above has a drawback in that it is capable of lubricating only a specific part that is provided with an oil hole, and it is impossible to form a hole at a portion of the cam contacting the tappet of the fuel pump.
In addition, the cam rotates in such a state in which it rotatably contacts the roller mounted at the bottom of the cam so as to operate the tappet upwardly and downwardly, and the conventional tappet lubrication structure of the engine guides the tappet upwardly and downwardly by the roller between the tappet and the cam, but contact surfaces between the tappet and the fuel pump adaptor and between the cam and the roller are not lubricated smoothly thereby inducing abrasion, and consequently durability and rotation thereof are deteriorated.
Therefore, due to the abrasion occurring at the roller interposed between the cam and the roller tappet, durability thereof is deteriorated and thereby manufacturing cost is increased, and noise occurs at the contact portion thereof.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Lubrication apparatus of fuel pump driven by fuel pump drive cam


The present invention provides methods and compositions for eliminating virally-infected cells by administering a Shiga-toxin composition, and the present invention provides methods and compositions for suppressing bovine leukemia-related cell proliferation. In the methods, a Shiga-toxin composition is administered in an amount effective to suppress bovine leukemia-related cell proliferation. The Shiga-toxin composition can include a Shiga-toxin polypeptide; a probiotic microorganism expressing a Shiga-toxin polypeptide; or a transgenic plant expressing a Shiga-toxin polypeptide. In one embodiment, the Shiga-toxin polypeptide is Stx1A and, in another embodiment, the Shiga-toxin polypeptide is Stx1 holotoxin. In yet a further embodiment, the Shiga-toxin polypeptide comprises Stx2.

Bovine Leukemia Virus (BLV) is an oncogenic retrovirus responsible for the enzootic form of bovine lymphosarcoma, the most frequent malignancy of domestic cattle (Ferrer (1980 Adv. Vet. Sci. Comp. Med. 24:1–68). BLV infection results in a 1–8 year long asymptomatic period (Ferrer et al. (1979) J. Am. Vet. Med. Assoc. 175(7):705–8), followed by development of persistent lymphocytosis (PL) in approximately 30% of infected cattle with progression to a malignant lymphosarcoma in fewer than 10% of the animals (Ferrer et al. (1979) J. Am. Vet. Med. Assoc. 175(7):705–8). The PL stage is a benign neoplasia of B lymphocytes, which are the predominant or exclusive targets of BLV (Esteban et al. (1985) Cancer Res. 45(7):3225–30). This stage of infection is associated with an increased percentage of peripheral B lymphocytes containing provirus as well as increased viral gene expression (Mirsky et al. (1996) J. Virol. 70(4):2178–83). The development of PL markedly enhances the probability of transmission (Mammerickx et al. (1987) Leuk Res. 11:353–58). The critical importance of PL to transmission of this blood-borne disease was demonstrated by experiments showing that it required significantly less blood from cattle with persistent lymphocytosis to transmit BLV than blood from infected cattle which did not have persistent lymphocytosis (Mammerickx et al. (1987) Leuk. Res. 11:353–58). Moreover, vertical transmission from BLV-infected dams to their calves has been shown to be strongly correlated with persistent lymphocytosis (Agresti et al. (1993) Amer. J. Vet. Res. 54:373–78).
In cattle, the ability to transmit BLV varies (Weber et al. (1983) Amer. J. Vel. Res. 44:1912–15); Marnmerickx et al. (1987) Leuk. Res. 11:353–58), and expression of antigen after in vitro culture has been shown to correlate with infectivity (Miller et al. (1985) Amer. J. Vet. Res. 46:808–13). The level of BLV expression in the animal also may correlate with the probability of development of persistent lymphocytosis (Cockerell et al. (1988) Leuk. Res. 12:465–69; Dropulic et al. (1992) J. Virol. 66:1432–41). Moreover, persistent lymphocytosis is a strong risk factor for development of lymphoma. In 1–10% of the animals with persistent lymphocytosis, B cell clones undergo neoplastic transformation, leading to leukemia or lymphoma, and cattle with persistent lymphocytosis are three times more likely to develop lymphoma than infected cattle without persistent lymphocytosis (Ferrer et al. (1979) J. Am. Vet. Med. Assoc. 175(7):705–8).
BLV is prevalent in dairy operations, with up to 89% of the U.S. dairy operation seropositive for BLV (Howie (1997) Feedstuffs 69:11). Not only does the virus kill cattle, milk and fat yields in BLV-infected cows with persistent lymphocytosis are greatly reduced (Da et al. (1993) Proc. Natl. Acad. Sci. U.S.A. 90:6538). Moreover, BLV also produces malignant lymphomas in sheep (Wittman et al. (1989) Arch. Exp. Veterinaermed. 23:709). However, the greatest economic impact of BLV infection in the United States arises from the fact that several countries will not import cattle from BLV-infested areas. Although various attempts have been made to develop a vaccine against BLV infection, an effective vaccine to protect cattle or sheep is not available (Miller et al. (1978) Annales de Recherches Veterinaires 9:871; U.S. Pat. No. 4,323,555). BLV infection is thus a costly impediment to cattle production.
Peripheral blood mononuclear cells (PBMC) from BLV-infected cattle proliferate spontaneously in vitro (Takashima & Olson (1981) Arch. Virol. 69(2):141–8; Thorn et al. (1981) Infect. Immun. 34(1):84–9). This spontaneous lymphocyte proliferation (SLP) is particularly vigorous in PBMC cultures from cattle in the PL stage of infection. Derepression of viral gene transcription and the synthesis of viral proteins precede SLP (Kettmann et al. (1976) Proc. Natl. Acad. Sci. USA. 74(4)1014–18; Baliga & Ferrer (1977) Proc. Soc. Exp. Biol. Med. 156(2):388–91; Ferrer (1980) Adv. Vet. Sci. Comp. Med. 24:1–68). Therefore, SLP provides a tractable model system for identifying factors that are capable of preventing BLV-induced neoplasia and malignant lymphoma in infected cattle. The present invention shows that Shiga-toxin type 1 (Stx1) is a potent and selective inhibitors of BLV-induced SLP. The present invention also shows that Shiga-toxin type 2 (Stx2) is a potent and selective inhibitors of BLV-induced SLP.
The family of Shiga toxins includes Stx type 1 (Stx1), Stx type 2 (Stx2) and Stx type 2 variants (Donahe-Rolfe et al. (1991) Rev. Infect. Dis. 13(Suppl. 4):S293–7). These toxins belong to a large family of ribosome-inactivating proteins (RIPs) that are found in a variety of higher plants and some bacteria. Most RIPs are hemitoxins (enzymatically active A chains) and some are holotoxins (one A chain associated with a specific number of B changes. Thus, class 1 RIPs (hemitoxins) are N-glycosidases that inactivate ribosomes by removing a single adenine in a specific ribosomal RNA sequence (Endo et al. (1987) J. Biol. Chem. 262:5908–12; Endo et al. (1988) Europ. J. Biochem. 171:45–50). Class 2 RIPs (holotoxins) are composed of an A subunit homologous to class 1 RIPs, noncovalently joined to one or more B subunits, usually galactose-specific lectins, that facilitate toxin binding and uptake into target cells. Holotoxins are highly toxic to cells expressing receptors for B subunit(s), but not to receptor-deprived cells, and are not toxic to normal cells as isolated A chains (Barnett et al. (1991) Antiviral. Res. 15:125–38; Dosio et al. (1994) J. Pharm. Sci. 83:206–11; Girbes et al. (1996) Cell. Mol. Biol. (Noisy-le-grand) 42:461–71). Plant hemitoxins are not toxic to the plants that synthesize them and have low cytotoxicity against animal cells, unless the cells have high pinocytic activity (Change et al. (1979) Contraception 19:175–84; Yeung et al. (1988) Int. J. Pept. Protein Res. 31:265–8).
Plant RIPs of both class 1 (e.g., pokeweed antiviral protein, titrin, trichosanthin) and class 2 (e.g., ricin) have potent antiviral activities (Stirpe et al. (1992) Biotechnology (NY) 10:405–12). These compounds often inhibit viral proliferation in mammalian cells in vitro, and some have been tested in vivo in clinical or laboratory settings. For example, plant hemitoxins can enter and eliminate virally-infected plant cells, and some are also found to be highly toxic to various virally-infected animal cells (Girbes et al. (1996) Cell Mol. Biol. (Noisy-le-grand) 42:461–71). The class 2 RIP ricin can eliminate latent herpes simplex virus in mice (Hino et al. (1988) J. Infect. Dis. 157(6):1270–1). Other plant RIPs inhibit replication of human immunodeficiency virus type 1 (HIV1) in human peripheral blood mononuclear cells at concentrations nontoxic to uninfected cells (Olson et al. (1991) AIDS Res. Hum. Retroviruses 7(12)1025–1030; Lee-Huang et al. (1995) Proc. Natl. Acad. Sci. U.S.A. 92(19):8818–22).
Shiga toxins are class 2 RIPs composed of an A subunit associated with a pentamer of receptor-binding B subunits. Because of their ability to bind to target cells, class 2 RIPs are potent cytotoxins. Stx1 is toxic to cells that express high levels of the toxin receptor, globotriosylceramide (Gb3 or CD77), most notably Vero cells and human glomerular endothelial cells (Jackson (1990) Microbial. Pathogenesis 8:235–42).
One problem associated with using RIPs as general antiviral agents is their specificity (Wachinger et al. (1993) Res. Exp. Med. 193(1):1–12; Watanabe et al. (1997) Biosci. Biotechnol. Biochem. 61:994–997). For example, the RIP Bryodin selectively inhibits the growth of HIV-1-infected cells, whereas RIPs gelonin and ricin did not (Wachinger et al. (1993) Res. Exp. Med. 193(1):1–12). Another concern is that RIPs are highly cytotoxic (Benigni et al. (1995) Int. J. Immunopharmacol. 17:829–39; Sparapani et al. (1997) Glia 20:203–9; Yoshida et al. (1999 J. Infect. Dis. 180:2048–52). Therefore, although the antiviral effects of some RIPs are known, the use of RIPs as antiviral agents has not been generally applicable. Surprisingly, it has been discovered that Stx1 strongly inhibits BLV-related cell proliferation and BLV expression and does not cause indiscriminate cell death (Ferens & Hovde (2000) Infect. Immun. 68:4462–9). Specifically, this activity is manifested by subunit A of Shiga-toxins, which is nontoxic to ruminants or humans.

This patent is subject to a terminal disclaimer.


A bussplate for an electronic device includes a plate having a plurality of integral electrical ground interfaces for commonizing electrical ground current within the electronic device. The plate grounds filter inserts that filter the electronic device from electronic noise and shields the electronic device from electromagnetic interference.

Motor vehicles, and in particular an automotive vehicle, frequently incorporate electronic components, such as an electronic controller, to functionally communicate with various systems in the automotive vehicle. For example, an engine controller functionally communicates with the engine and engine-related systems, while a vehicle body controller functionally communicates with vehicle body-related systems. Motor vehicles also contain other well known electronic components, such as a radio, or a compact disc player, or a cellular phone. With the proliferation of electronic components in a motor vehicle, there is an increased potential for electronic noise or electromagnetic interference from one electronic component to another. One potential path for electrical noise or electromagnetic interference in an electronic controller is through a connector that functionally connects the electronic controller with another component.
Filters and shields are frequently utilized to reduce or eliminate unwanted electrical signals and electromagnetic interference. In one such case, a filtered electrical connector having a die cast aluminum housing is mounted to a printed circuit board, for attaching a wiring harness to the printed circuit board. The die cast housing includes a plurality of compartments, with a filter insert contained within each compartment, for filtering electronic noise. While the filter insert works well, it does not completely shield an opening in the housing for an electrical connector.
As is known in the art, a bussplate is used to commonize electrical current in electrical circuits. It is also known in the art that all electrical circuits must be grounded to a common ground. In an electronic controller, multiple unique internal and external ground interfaces are typically utilized to ground individual components including the connector, filter insert, printed circuit board or housing. For example, a pin may be cast in the housing to ground the filter insert to the housing. A grounding clip may be used to ground the printed circuit board to the metal housing. An external ground, such as a cable, connector may ground the housing to a massive conductive structure, such as the engine. These grounding methods require that the housing must be made of a conductive metal material. In an underhood environment, a housing made from a material, such as a die cast aluminum, may be subject to corrosion. Thus, there is a need in the art for a bussplate that integrates multiple ground interfaces, while providing filtering and shielding from electrical noise and electromagnetic interference within a non-corrosive enclosure.


A lubricating structure of an automatic transmission is provided which is capable of realizing high lubrication efficiency by allowing lubricating oil to flow efficiently, and of retaining the durability of a member to be lubricated. In the lubricating structure of the automatic transmission, an oil seal line (35) corresponds to a line on which an oil catching member (29) comes into contact with a carrier plate (10), and the oil seal line (35) has a configuration in which the distance in radial directions from an input shaft (21) to each point on the oil seal line (35) is made unequal so that the lubricating oil caught by the oil catching member (29) flows along the oil seal line (35) toward the opening of an oil path (28) on the side opposite to the side on which a pinion is disposed by centrifugal force making rotation on the input shaft (21).

1. Field of the Invention
This invention relates to a lubricating structure of an automatic transmission principally used for controlling the transmission of driving force in a vehicle.
2. Description of the Prior Art
There has been known a conventional lubricating structure of an automatic transmission, such as that disclosed in Japanese Patent Application Laid-Open Publication No. Hei 5-61497.
As shown in FIGS. 9 to 10, a planetary gear device 5 is disposed around an output shaft 3 used as a rotational axis in such an automatic transmission 1.
An oil catching member 14 is disposed on a side of a carrier plate 12 of the planetary gear device 5, and the side is opposite to the side on which a pinion 7 is disposed.
The oil catching member 14 consists mainly of a guide portion 14a used as an oil receiver and an attachment portion 14b extending from the guide portion 14a. As shown in FIG. 9, the attachment portion 14b is caulked by the carrier plate 10, and thereby the oil catching member 14 is disposed circularly around the output shaft 3.
A platelike seal member 15 shown in FIG. 12 is disposed between the oil catching member 14 and the side 10a opposite to the side on which the pinion 7 of the carrier plate 10 is disposed. The inner circumferential line of the seal member 15 is constructed as an oil seal line 16 with which a leakage of lubricating oil from between both the members 10, 14 toward the outside in the radial direction is blocked.
As shown in FIG. 12, the oil seal line 16 includes enlarged diameter portions 17 each of which has a large distance in a diametrical direction, and shortened diameter portions 18 each of which has a smaller distance in a diametrical direction than the enlarged diameter portion 17. The enlarged diameter portion 17 corresponds to a position where each of pinion shafts 7a is disposed, as shown in a broken line of FIG. 10, and the shortened diameter portion 18 is formed between the enlarged diameter portions 17, 17.
The oil catching member 14 catches the lubricating oil emitted from an oil hole 3a formed in the output shaft 3 on the shortened diameter portion 18, then leads the lubricating oil to an oil path 12 formed in the pinion shaft 7a, then sends the lubricating oil led to the oil path 12 to the side of the pinion 7, and lubricates the tooth surface of the pinion 7, a bearing, and the like.
However, according to this conventional automatic transmission lubricating structure, the shortened diameter portion 18 of the oil seal line 16 is formed so that all points of the oil seal line 16 are positioned at equal distances from the rotational center of the output shaft 3, and therefore, unless the lubricating oil which has been caught overflows the oil catching member 14 by exceeding an allowable predetermined quantity, or unless acceleration in a circumferential direction generated by varied revolution speed of the oil catching member 14 is given to the lubricating oil, the lubricating oil does not flow toward the enlarged diameter portion 17.
Further, in the conventional structure, since a carrier 9 is connected to the output shaft 3, the carrier plate 10 continues to rotate and thus the oil catching member 14 also continues to rotate while a vehicle is traveling. However, when the oil catching member 14 is applied to the carrier plate 10 of the planet carrier 9, the carrier plate 10 stops rotating depending on the transmission gear, and thereby the oil catching member 14 may stop rotating. In this case, since the acceleration in a circumferential direction is lost, disadvantageously, the flow of the lubricating oil toward the enlarged diameter portion 17 may not occur.
Therefore, in order always to supply a sufficient quantity of lubricating oil to the pinion 7, after all, a larger quantity of lubricating oil than necessary is required to be emitted from the output shaft 3. As a result, a large quantity of lubricating oil is required, so that high lubrication efficiency did not seem to be obtained.
In the enlarged diameter portion 17, the lubricating oil which has been caught directly by the enlarged diameter portion 17 and the lubricating oil which has flowed from and has been collected into the adjacent right and left shortened diameter portions 18, 18 are transmitted to the side of the pinion 7 through the oil path 12. At this time, the total quantity of the collected lubricating oil flows through the narrow oil path 12, and thereby, disadvantageously, the flow of the lubricating oil is blocked with unnecessary substances, such as initially-worn powder and the like. As a result, the durability of a member to be lubricated, such as a bearing member or the like, might be lowered.

Lubricating structure of automatic transmission


Arrangements and procedures for compressing grayscale, binary and bi-level image data are disclosed. With respect to compressing binary and bi-level image data, individual byte image data values are retained that are different from a same row byte that is n-bytes back. For each retained byte image data value, individual byte image data values are encoded for bytes in a current byte row with replacement data strings. The replacement data strings include a replacement positioning code and a replacement count code for replicating retained byte image data values for subsequent data decompression as a group of substantially identical byte values.

Traditional grayscale and binary compression techniques analyze image data stream a single-bit at a time to generate compressed image data. Conventional grayscale image encoding techniques use run-length encoding techniques that can not typically be used effectively to compress binary image data because the concept of similar pixel color groupings at a byte-level in binary image data is not present. And, traditional binary image data compression techniques to replace juxtaposed pixels that match predetermined bit patterns in a dictionary are computationally intensive—often resulting in slow response times in software implementations, and complex and expensive to implement in hardware.
For instance, conventional color and grayscale data compression techniques typically analyze an image data stream a single-bit at a time to determine if a sequential number of pixels, wherein each pixel is typically defined by 8-24 bits of data, have respective color values that correspond to a current pixel. When multiple sequential pixels with the same color are identified, a code is inserted into a compressed data stream to describe a color value and a repeat length. In this manner, multiple bytes (e.g., hundreds or even thousands of bytes) of color data can be represented with a couple of bytes of encoded data in a compressed data stream. This type of image data compression is called run-length encoding. Run-length encoding is often used to compress color and grayscale data because colors tend to occur juxtaposed or side-by-side to one another in color and grayscale images.
Run-length encoding of side-by-side pixels representing a same color, as often performed in the compression of color and grayscale image data, does not work very well when considering the compression of binary image data. This is because a binary pixel is represented with a single bit of data, not 8-24 bits of data that are byte-aligned. This means that a byte or 8-bits represent 8 separate pixels of color. Because only a single bit is used to represent a pixel, binary images typically do not exhibit enough color similarity from bit-to-bit to efficiently leverage the run-length encoding techniques.
For example, consider that color data that is represented with 8-24 bits of data per pixel are often reduced to binary or bi-level image data (2-bits per pixel) by halftoning procedures to change the data's attributes to conform to specific printer, marker, or imaging device output requirements. Halftones are created through a process called dithering, in which a density and pattern of black and white dots are varied to simulate different shades of gray. Such patterns of black and white dot values do not typically exhibit enough color similarity from bit-to-bit to efficiently leverage the run-length encoding techniques used to compress color and grayscale images, which represent pixels with 8-24 bits. Because of this limitation of run-length encoding techniques when it comes to the compression of binary data, a number of other conventional compression techniques are used to compress binary image data (certain ones of these techniques may also be used to compress grayscale data).
For example, conventional binary compression techniques (e.g., those based on an international standard called JBIG or Lempel-Ziv (LZ) algorithms) typically analyze image data a single-bit at a time. JBIG attempts to guess the bit, and then code the error of the bit with the guess using an arithmetic coding. Whereas LZ operates on single-bits attempting to identify pre-determined bit-patterns (i.e., patterns stored in a pattern dictionary). Once such a pattern is identified, it is replaced in the original image data with a corresponding tag that has a smaller bit footprint than the identified bit pattern. The binary bit-pattern dictionary can be expanded. For instance if a certain number of pixels have been read without a corresponding dictionary pattern match, those unmatched pixels can be stored in the dictionary as another pattern. Using such techniques binary data can be compressed. However, these binary compression techniques are problematic for a number of reasons.
For example, even though a binary image bit-pattern dictionary can be expanded to include otherwise unrepresented bit patterns, it can be appreciated that the range of binary image data that can be effectively compressed using these techniques decreases rapidly as image complexity (i.e., image entropy) increases. Additionally, hardware implementations of such binary compression techniques are typically very costly to implement and require highly skilled technicians to implement complex timing algorithms. Moreover, software implementations of conventional binary compression techniques typically result in exceedingly slow binary compression response times due to the computationally intensive nature of analyzing image data for complex bit-patterns a single-bit at a time.
The following arrangements and procedures address these and other problems associated with compressing grayscale and binary data.

Grayscale and binary image data compression

Hewlett-Packard Development Company, L.P.


A browser-based personalized recommendation system and method for lifestyle items comprising style dimension mapping, inputs, outputs, and a computer-algorithm is described. The system gathers information about a user's unique lifestyle preferences, which is then correlated to clothing and lifestyle items. The recommendation system uniquely and directly matches users to discrete items without the need for historic user data.

1. Field of the Invention
The present invention relates to recommendation systems. More particularly, the present invention is related to computer-implemented personalized recommendation methods and systems used for lifestyle items.
2. Related Art
Evaluating lifestyle items is a highly subjective process. People often consider intangible style elements, branding, and public perception of themselves as well as the items in question in determining whether to make a purchase decision. This becomes complicated, in that people look to understand the style of a product, and then, how the product and its style relate to them individually. Since it is difficult to assign a quantitative estimate to style, a straightforward, non data-intensive approach to matching users with unique items has never been accomplished.
Currently, popular pre-existing recommendation systems involve singular value decomposition (SVD), collaborative filtering, attribute based tagging, and data mining algorithms. For singular value decomposition and collaborative filtering, millions of data are collected and then "factors" are mathematically determined between points in attempt to predict future data sets. In the case of Netflix, each user rates individual movies on a scale of 0-5 and then an algorithm attempts to derive how future movies will also be rated. Some of the data employed in this process are movie information and groupings, including genre, date, actors, user queue histories, and a set of user ratings from rented movies.
From this data, an algorithm can match users based on their rating history and the statistical likelihood that their ratings will correlate with those of similar users. Note that the "factors" that link users to ratings are not necessarily predicted in advance; rather the SVD approach determines the statistical significance of causal links after a considerable data set already exists. Despite the success of this system, there are some limitations: (1) it requires a very large initial dataset of user ratings (Netflix uses more than 100 million); (2) prior to obtaining relevant results, users are required to first create a baseline by rating several films; and (3) recommendations are based only on the rated items—users rate movies, and then are recommended movies.
These restrictions are also prevalent in many of the advanced data mining techniques comparing browser cookies, query results, purchasing behavior, and other rating systems. A popular alternative is an attribute based tagging system used by Pandora as part of the Music Genome Project. In this system, songs are manually tagged with over 400 distinct musical attributes such as vocal harmony, pitch, lyrics, and instruments. Users can then choose some of their favorite songs and an algorithm will map user preferences against the database of cataloged songs. As with the aforementioned recommendation systems, this approach also presents some limitations: (1) the user is required to rate a variety of music prior to generating relevant results; (2) the songs are tagged by attributes explicitly related to music, and not potential users (listeners); (3) a sufficient number of attributes for each song is required to provide beneficial results; and (4) recommendations are confined to the types of items rated.
Consequently, a need exists for a flexible personalized recommendation system that does not require an expansive data set to develop reliable recommendations for each individual user of the system.

Method and system for personalized recommendation of lifestyle items


A training system used while a person is speaking uses a feedback modification technique to reduce accents. As the speaker is speaking, the system feeds back to the speaker the speaker's speech in "real-time" so that the speaker, in effect, hears what he or she is saying while saying it. The system includes a detector configured to monitor a speaker's speech to detect a preselected target vowel sound that the speaker wishes to produce accurately. In response to the detector detecting a "target" vowel sound, a cue generator generates a sensory cue (e.g., an amplification of the "target" vowel sound) that is perceived by the speaker. As the speaker is speaking, the generator feeds back to the speaker the sensory cue along with the speech so that the cue is coincident with the "target" vowel sound.

As is commonly observed, a person that has learned to speak a second (or third, etc.) language will typically have an accent. A significant aspect of the accent is in the formation of vowel sounds.
FIG. 1 is a graph illustrating an exemplary vowel sound in the frequency domain (i.e., magnitude as a function of frequency). The vowel sound, when plotted as the magnitude of the sound as a function of frequency, generally forms a curve 100 having a series of local maxima at various frequencies along the frequency band of interest, generally about zero to about five kHz. FIG. 1 shows four local maxima 101-104. The frequencies of the local maxima are commonly referred to as "formants". The formant with the lowest frequency is referred to as formant F1. Similarly, the second lowest frequency formant is referred to as formant F2, the third lowest frequency formant is referred to as formant F3 and so on.
A vowel sound may be sufficiently identified by the frequencies of formants F1 and F2. FIG. 2 is a graph illustrating an exemplary group of vowel sounds produced by a native speaker of English. In particular, the graph was formed by plotting, for each vowel sound in the language's vowel set, formant F2 of that vowel sound as a function of that vowel sound's F1 formant. For example, the vowel sound [i] (using the well-known IPA nomenclature) has a relatively high F2 formant with a relatively low F1 formant. Conversely, the vowel sound "a" has a relatively low F2 formant with a relatively high F1 formant. A monotonic curve 200 can be drawn containing the vowel sounds [i], [I], [.epsilon.], [.ae butted.] and [a], as shown in FIG. 2.
However, it has been observed that the vowel set of a person's native language may not include one or more vowel sounds in the new language that the person is speaking. It is thought that the person speaking is not sensitive to these vowel sounds in either hearing or speaking these vowel sounds. Thus, the speaker typically cannot determine whether he or she is correctly producing the target sound. Of course, this deficiency hinders the speaker's training in reducing the speaker's accent. Accordingly, there is a need for a system that helps speakers to become sensitive to target vowel sounds when speaking a non-native language.

Feedback modification for accent reduction


The present invention discloses an LED display screen layout method, including an LED display screen, wherein the LED display screen is formed by splicing a plurality of LED modules; each LED module includes four tricolored LED lamps; the four tricolored LED lamps form a square; and the four tricolored LED lamps are arranged in directions formed by sequentially rotating one of the tricolored LED lamps by 90 degrees. With such layout design, when the LED display screen is rotated, no blue line appears at neighboring borders of the LED modules, thus not influencing the display effect of the display screen.

The present invention relates to the field of LED display screens, and more particularly to an LED display screen layout method.
Light emitting diode (LED) was invented in 1962; in nearly 40 years, the color of the LED developed from the early red, yellow and green to three primary colors red, green and blue at present, and the packaging form also developed from the early in-line single lamp, the later matrix module to the patch three-in-one full-color LED at present.
The layout of the three-in-one full-color LED display screen at present is the uniform arrangement and layout of a tricolored LED; such layout design is simple, and the production process is also comparatively simple. However, when a screen body of the LED display screen needs to rotate and splice modules, blue lines would appear at neighboring borders of the rotated modules because the arrangement directions of the LED lamps on the modules are consistent, thereby influencing the display effect of the display screen. In order to solve the blue line problem, the conventional design method needs to design and produce four different LED display modules, and then splices the LED display modules, which will greatly improve design and production cost.

LED display screen with rotated LED modules


An exercise apparatus having foot beams (38a, 40a) rotatably mounted to an upright post member (140a) of a frame to rotate about a first axis (322). Hand levers (132a, 134a) are secured to pivot members (152a) pivotally mounted to the upright post member to rotate about a second axis (328). The hand levers are coupled by resilient linkage members (380) including elastomeric joints (382) to the foot levers so that as each foot lever rotates about the first axis, the corresponding hand lever normally rotates a related distance about the second axis. The linkage members are resiliently deformable to allow discontinuity between the rotation of the foot levers and hand levers when an exerciser exerts a differential force on the hand levers relative to the corresponding foot levers.

Exercise equipment designed to simulate climbing stairs or jogging has long been known. One known type of such exercise equipment includes a frame and two foot beams or pedals which are pivotally mounted to the frame. In this equipment, the pedals are depressed alternately as the user climbs or jogs in place. The pedals are returned to an upper, typically generally horizontal, position by one of a variety of biasing means.
One group of biasing means for returning the foot pedals to the upper position comprises a pair of coil springs, each of which are positioned beneath a respective one of the foot pedals, as disclosed in U.S. Pat. No. 3,628,791 and German Patent No. 2,243,794. The use of coil springs alone as a means for biasing the foot pedals on exercise apparatus to the upper position has been found to be undesirable because the resistance generated by the springs typically does not vary linearly with displacement of the foot pedals. Such nonlinear resistance makes it difficult to develop an even exercise cadence.
Another system for returning the foot pedals of a stair climbing exercise apparatus to the upper position is disclosed in U.S. Pat. No. 4,838,543 (the "'543 patent"). The '543 patent discloses a rope and pulley arrangement for returning the foot pedal from which the user has removed his or her weight to the upper position. The rope and pulley system comprises a pulley centrally located between and above the foot pedals and a rope trained about the pulley and attached to each of the foot pedals so that when one of the foot pedals is pressed down by the user, the rope attached thereto is pulled down which in turn causes the other end of the rope attached to the other foot pedal to be pulled up. As a result of this upward movement of the other end of the rope, the foot pedal attached thereto is moved to an upper position. Although the rope and pulley arrangement disclosed in the '543 patent functions satisfactorily, a desire exists to provide a mechanism for returning the unweighted pedal to the upper position which has a higher degree of reliability and durability than that of the rope and pulley arrangement disclosed in the '543 patent.
Torsion springs of the type comprising an elongate, metal coil spring fixed to a pivotally mounted member so that the longitudinal axis of the spring is parallel to or coaxial with the axis of rotation of the member have been used in exercise equipment for biasing various pivotally mounted lever mechanisms in a given direction and for opposing movement of such lever mechanisms in an opposite direction. For instance, U.S. Pat. No. 4,684,126 discloses a rowing exercise apparatus comprising a pair of arm levers, each having a torsion spring associated therewith for opposing movement of the arm levers in a first direction and for biasing the arm levers in an opposite direction. German Patent No. 2,145,884 discloses a foot exerciser for bedridden patients comprising two foot pedals which are pivotally mounted to a frame. The foot exerciser includes a torsion spring associated with each of the foot pedals for resisting movement of the pedals in a first direction and biasing the pedals in a second, opposite direction. Soviet Union Inventor's Certificate 618,118 discloses a gymnast's springboard comprising a pair of lever mechanisms and a pair of torsion springs associated with each of the lever mechanisms for urging the mechanisms in a first direction and opposing movement of the lever mechanisms in an opposite direction. The lever mechanisms engage a horizontal bed and urge the bed upwardly and oppose movement of the bed in a downward direction. In addition to being relatively costly, the use of elongate, metal coil springs as torsion springs in exercise apparatus for biasing lever mechanism in a first direction tends to be undesirable due to inadequate longevity and durability of such torsion springs.
Thus, known mechanisms for returning the foot pedals of exercise apparatus to the upper position either do not function satisfactorily or lack sufficient durability and longevity.
Elastomeric torsion springs have been used in applications unrelated to exercise apparatus as a means for opposing rotation of various mechanisms in a first direction and for biasing the mechanism so as to cause it to rotate in a second, opposite direction. Such elastomeric torsion springs typically comprise an annular outer casing made from a rigid material such as steel or aluminum, an annular central member made from an elastomeric material and attached to the inside surface of the outer casing, and an inner casing which is also typically made from a rigid material such as steel or aluminum and is attached to the inner surface of the central member. In use, the inner casing is typically fixed to a first member and the outer casing is attached to a second member which is designed to pivot relative to the first member. As the second member is caused to rotate in a first direction relative to the first member, rotational force is applied to the central elastomeric member via the outer casing attached to the second member. Such rotation of the central member causes energy to be stored therein. When the second member is released, the energy stored in the elastomeric central member is transmitted via the outer casing to the second member so as to cause the latter to rotate in an opposite direction relative to the first member. One such elastomeric torsion spring is distributed by B. F. Goodrich Company of Akron, Ohio, under the federally registered trademark TORSILASTIC.
Exercise devices for simulating walking or climbing that include additional levers to be worked by a user's hands to exercise the upper body concurrently with the lower body are also known in the art. One such "full body" exerciser is disclosed by U.S. Pat. No. 4,934,690. The exerciser includes two foot beams pivotally secured to a frame. A hydraulic cylinder is connected from the frame to one of the foot beams, and a rocker arm assembly pivotally mounted to the frame below the foot beams links the foot beams together for opposing up and down motion. The exercise device further includes two hand levers rotatably mounted to the frame above the foot beams. Each hand lever is mounted to the first end of a pivot lever pivotally mounted to the frame. A tie rod connected from the second, opposite end of the pivot lever to a foot beam links the movement of the foot beams and hand levers. Depression of a particular foot beam results in the corresponding arm lever rotating away from the user in the opposite direction. Because of the linkage, a user acts on both foot beams as well as both arm levers to overcome the resistance of the hydraulic cylinder. However, in so doing the user is forced to coordinate the movement of all four of his or her limbs. This coordination may be difficult for many individuals. Further, an individual is not able to concentrate his or her efforts on the upper or lower body, as may be desired, but is forced to exercise upper and lower muscle groups affected equally.


An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

1. Field of the Invention
The present invention relates generally to binary data generating circuits and A/D converters, and more particularly, to a binary data generating circuit and an A/D converter which is less susceptible to noise. The present invention has particular applicability to a parallel-type and a serial-parallel type A/D converters.
2. Description of the Background Art
Conventionally, a converter which converts an analog signal to a digital signal (hereinafter "A/D converter") is widely used for performing digital signal processing with respect to an analog signal. High-speed conversion is also required in A/D converters, since high-speed digital signal processing is required, for example, in the field of video signal processing.
As A/D converters suitable for high-speed conversion, parallel-type and serial-parallel type A/D converters have been known conventionally. These A/D converters employ many comparators and generally, power consumption of A/D converter is approximately determined by the number of the comparators used. In any parallel-type and serial-parallel type A/D converters, the analog input signal is applied to the inputs of a plurality of comparators in parallel. In addition, in serial-parallel type A/D converter, the conversion of an analog signal to a digital signal is performed in series on time axis.
The parallel-type A/D converter is operable at high-speed. However, since it needs many more comparators than those needed by the serial-parallel type A/D converter, power consumption is greater and therefore often used for industrial or electronic machines for service, such as oscilloscope or the like. The serial-parallel type A/D converter is slower than the parallel-type converter. However, since it has small power consumption and can be formed within a small occupied region on a semiconductor substrate, that is to say, suitable for integration, it is often used in consumer products for the private sector. The present invention is applicable to both the parallel-type A/D converter and the serial-parallel type A/D converter.
FIG. 14 is a block diagram showing a general configuration for video signal processing. With reference to FIG. 14, an object not shown is imaged by a video camera 91. Since the video signal provided from video camera 91 is analog, it is converted to the digital video signal by an A/D converter 92. The digital video signal is applied to a digital video signal processing circuit 93, which performs digital signal processing of the video signal. Processed data is applied to a D/A converter 94 and converted to the analog signal therein. The processed analog signal provided from D/A converter 94 is applied to a display unit 95 and a processed image is represented on the screen provided therein (not shown). The foregoing parallel-type or serial-parallel type A/D converter is applicable to A/D converter 92 shown in FIG. 14.
FIG. 15 is a circuit block diagram of a conventional parallel-type A/D converter. The A/D converter shown in FIG. 15 is disclosed in the article entitled "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter", IEEE Journal of SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, pp. 926-931, Dec., 1979, by ANDREW G. F. DINGWALL. For simplicity of description, the A/D converter providing 3-bit digital data is illustrated in FIG. 15.
Referring to FIG. 15, an A/D converter includes a ladder resistance circuit 1 provided with resistors 60 to 70 connected in series between the externally applied reference potentials Vrel and Vre2, a comparator circuit 4 provided with seven comparators C0 to C6, a pre-encoder 2 provided with 8 AND gates A0 to A7 and an encoder 3 connected to the outputs of pre-encoder 2. Since ladder resistance circuit 1 is provided with resistors 60 to 67 each having the same resistance value, it generates seven reference voltages V0 to V6 determined by the resistance division. Seven reference voltages V0 to V6 are applied to comparators C0 to C6 provided within comparator circuit 4, respectively.
Each of the comparators C0 to C6 provided within comparator circuit 4 compares an analog signal with corresponding one reference voltage to provide 7-bit data (referred to as "thermometer code") which indicates a comparison result. Each bit of thermometer code is applied to respective two adjacent AND gates provided in pre-encoder 2.
Each of AND gates A0 to A7 in pre-encoder 2 has two inputs, one input thereof constituting an inversion input and being connected from an inverter. For example, the j-th AND gate Aj has its inversion input connected to the output of the j-1st comparator Cj-1 and its non-inversion input connected to the output of the j-th comparator Cj. The inversion input of AND gate A0 is grounded and the non-inversion input of AND gate A7 is connected to a power supply potential Vcc. Output signals j0 to j7 provided from AND gates A0 to A7 are applied to encoder 3, where the signals are converted to corresponding binary data B0 to B2.
FIG. 16 is a schematic diagram of a circuit of encoder 3 shown in FIG. 15. As shown in FIG. 16, encoder is implemented by a pseudo NMOS type read-only memory (hereinafter "ROM") to generate a straight binary code. This encoder 3 includes NMOS transistors, selectively turned on responsive to input signals J0 to J6 applied from pre-encoder 2 and PMOS transistors which are turned on by applying a bias voltage V.sub.B1 thereto. In normal operation, as one of the input signals J0 to J7 is at a high level (data "1"), only NMOS transistor supplied with high level input is turned on. As a result, binary data B0 to B2 corresponding to the input signals J0 to J7 are provided. A relationship between input signals J0 to J7 and binary data B0 to B2 is shown in the following Table 1.
TABLE 1 ______________________________________ B.sub.2 B.sub.1 B.sub.0 ______________________________________ J.sub.7 111 J.sub.6 110 J.sub.5 101 J.sub.4 100 J.sub.3 011 J.sub.2 010 J.sub.1 001 J.sub.0 000 ______________________________________
Since encoder 3 shown in FIG. 16 is of pseudo-NMOS type, current driving ability or load driving ability (corresponding to mutual conductance gm) of PMOS transistors in encoder 3 is indicated to be smaller than that of NMOS transistors. Therefore, only the transistor supplied with high level input is turned on, so that the potentials of bit lines BL0 to BL2 become selectively lowered. As a result, binary output data B0 to B2 are obtained through bit lines BL0 to BL2.
Therefore, in normal operation, when only any one of input signals J0 to J7 is at a high level (i.e., data "1"), binary data B0 to B2 shown in Table 1 are provided from encoder 3. Referring to Table 1, when only the input signal J3 is at a high level, for example, encoder 3 shown in FIG. 16 provides (0, 1, 1) as output data (B2, Bl, B0).
Now, the entire operation of A/D converter 5a shown in FIG. 15 will be explained. Predetermined reference voltages Vre1 and Vre2 are applied to a ladder resistance circuit 1. Reference voltages Vre1 and Vre2, in case that this A/D converter 5a is employed as A/D converter 92 shown in FIG. 14, for example, are determined by changeable maximum and minimum potentials of the video signal being input. Ladder resistance circuit 1 divides the voltage difference Vrel-Vre2 by eight resistors 60 to 67 to generate seven reference voltages V0 to V6. Seven reference voltages are applied to comparators C0 to C6 in comparator circuit 4, respectively. Each of the comparators C0 to C6 compares an applied reference voltage with the voltage of an analog input signal to provide data "1" when the analog signal voltage is larger than the reference voltage. On the other hand, when the analog signal voltage is smaller than the reference voltage, data "0" is provided.
FIG. 17 is a signal transition diagram showing the operation of encoder 3 of FIG. 15. With reference to FIG. 17, when potential Vin of analog input signal Si lies between the voltages V3 and V4, comparators C0 to C3 provide data "1". On the other hand, each of comparators C4 to C6 provides data "0", respectively. Therefore, comparator circuit 4 of FIG. 15 provides a thermometer code TC shown in FIG. 17.
Two gates, adjacent to each other, of AND gates A0 to A7 in pre-encoder 2 each receives one corresponding data in thermometer code TC1. Among AND gates A0 to A7, only AND gate A4 that receives data "0" and "1" provides data "1". Other AND gates A0 to A3 and A5 to A7 provide data "0". Therefore, output signals J0 to J7 are provided from pre-encoder 2, in which only signal J4 is "1". Encoder 3, therefore, provides binary output data (B2, Bl, B0) =(1, 0, 0) based on Table 1 described above.
The foregoing is a description of the case where A/D converter 5a shown in FIG. 15 operates normally; however, A/D converter 5a is affected by noise or the like, causing frequent malfunction as set forth in the following. First, the factor which causes noise in A/D converter 5a will be described hereinafter.
Referring to FIG. 28, it is assumed that some noise source NS exists in semiconductor substrate 5. In addition, it is also assumed that comparators C0 to C6 are located close to noise source NS on substrate 5 as shown in FIG. 28. Noise overlapped in inner circuits of comparators C0 to C6 becomes larger in the comparator closer to the noise source; however, the comparison result brought to the comparator having smaller difference between analog input signal Si and an applied reference voltage is more susceptible to noise. Accordingly, in the example shown in FIG. 28, comparators C0 and C1 are more susceptible to noise than comparators C3 and C4.
Referring to FIG. 29, it is assumed that signal Si is sampled at a time t2 after the sampling of analog input signal Si at a time t1. Preferably, only the output signal of comparator C0 should be changed from "1" to "0" by the sampling at the time t2; however, such a malfunction as in the following is caused by noise.
As shown in FIG. 30A, it is assumed that waveforms of the output signals of comparators C0 to C6 are changed by noise. At the time t2, in the case where comparators C0 to C6 operate at a time t4 after the sampling of input signal Si at the time t2, comparators C0 to C6 and AND gates A0 to A7 provide output signals as shown in FIG. 30B. That is, since output signals of comparators C0 to C6 are not affected by noise at the time t4, preferable comparison result can be obtained.
Conversely, in the case where comparators C0 to C6 operate at a time t3, comparator C1 erroneously provides "1" as shown in FIG. 30C, causing AND gates A0 and A2 to provide output signals J0 and J2 of "1". That is, pre-encoder 2 provides abnormal output signals J0 to J7, and this abnormal condition is referred to as "multi-addressing".
FIG. 18 is a signal transition diagram for illustrating an abnormal operation of encoder 3 shown in FIG. 15. Comparator 4 shown in FIG. 15 may provide a wrong thermometer code TC2 shown in FIG. 18 by an influence of noise or the like. That is, comparator C3 provides data "0", though it should provide data "1". In addition to this, comparator C4 provides data "1", though it should provide data "0". That is, an abnormal condition referred to as "multi-addressing" is occurring. Since abnormal thermometer code TC2 is applied to pre-encoder 2, as a result, AND gates A3 and A5 in pre-encoder 2 provide data "1". Therefore, as output signals J0 to J7 are provided, in which only signals J3 and J5 are "1", encoder 3 provides binary data, (B2, B1, B0) =(0, 0, 1).
The reason why the binary output data (0, 0, 1) can be obtained will be explained as follows. As shown in FIG. 18, binary output data is (0, 1, 1), when only signal J3 is data "1". On the other hand, binary output data is (1, 0, 1), when only signal J5 is "1". As encoder 3 has such a circuit configuration as shown in FIG. 16, that is, pseudo-NMOS type ROM, a logical product of corresponding bits of two pieces of data (0, 1, 1) and (1, 0, 1), that is "AND" data (0, 0, 1) is provided as binary output data.
In the example described above, binary output data (1, 0, 0) is provided in normal operation as shown in FIG. 17; however, in a wrong operation, binary output data (0, 0, 1) is obtained as shown in FIG. 18. Since a difference between normal data (1, 0, 0) and abnormal data (0, 0, 1) is 4LSB, it can be seen that binary output data having a large abnormal value by the generation of multi-addressing is provided.
Therefore, in a case where A/D converter 5a of FIG. 15 is applied to A/D converter 92 shown in FIG. 14, the binary output data having a large abnormal value is applied to the digital video signal processing circuit 93, and an abnormal image will be represented on the screen of display unit 95.
In the foregoing description, an explanation of a parallel-type A/D converter has been given, and a similar abnormal operation also occurs in a serial-parallel type A/D converter. This will be described hereinafter.
FIG. 19 is a circuit block diagram of a conventional serial-parallel type A/D converter. A/D converter 5b shown in FIG. 19 can be seen in the article entitled "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE Journal of SOLID-STATE CIRCUITS, VOL. SC-20, No. 6, pp. 1138-1143, Dec. 1985, by ANDREW G. F. DINGWALL.
Referring to FIG. 19, serial-parallel type A/D converter 5b includes a reference voltage generating circuit 11 which receives externally applied reference voltages Vre1 and Vre2 to generate the reference voltages of various levels. Reference voltage generating circuit 11 generates reference voltages for more significant bits F0 to F6 and reference voltages for less significant bits H0 to H12 in response to control signals J0 to J7, applying them to a more significant comparator 13 and a less significant comparator 14, respectively. In A/D converter 5b of FIG. 19, as an example, A/D conversion of 6 bits in total including 3 more significant bits and 3 less significant bits is performed. Therefore, more significant comparator 13 receives seven reference voltages for more significant bits F0 to F6 from reference voltage generating circuit 11. On the other hand, less significant comparator 14 receives 13 (=7+6) reference voltages for less significant bits H0 to H12 in order to perform .+-.3LSB error correction as will be described hereinafter.
More significant comparator circuit 13 has a circuit configuration similar to that of comparator circuit 4 shown in FIG. 15, and thus is provided with seven comparators (not shown) operating similarly. Seven output signals provided from more significant comparator circuit 13 are applied to a more significant pre-encoder 15.
More significant pre-encoder 15 also has a circuit configuration similar to that of pre-encoder 2 shown in FIG. 15, and operates similarly. Eight output signals provided from more significant pre-encoder 15 are applied to a more significant encoder 16. More significant encoder 16 also has a circuit configuration similar to that of encoder 3 shown in FIG. 16, and operates similarly. Therefore, binary output data of more significant bits B3 to B5 are provided from more significant encoder 16 and applied to an error correction circuit 19.
Less significant comparator circuit 14 also has a circuit configuration similar to that of more significant comparator circuit 13. That is, less significant comparator 14 is provided with 13 comparators (not shown) for comparing analog input signal Si with 13 reference voltages H0 to H12 applied from reference voltage generating circuit 11, respectively.
Output signals provided from less significant comparator circuit 14 are applied to a less significant pre-encoder 17. Less significant pre-encoder 17 also has a circuit configuration similar to that of more significant pre-encoder 15, and operates similarly. Output signals provided from less significant pre-encoder 17 are applied to a less significant pre-encoder 18. Less significant pre-encoder 18 also has a circuit configuration similar to that of more significant pre-encoder 16 and operates similarly.
Less significant encoder 18 provides output signals OS, US and B0 to B2 of 5 bits in total. Among these output signals, data indicating the result of the A/D conversion of less significant bits are less significant 3 bits B0 to B2. An overscale signal OS of the most significant bit is applied to error correction circuit 19. An underscale signal US of the second from the most significant bit is applied to error correction circuits 19 and 20. Therefore, error correction circuit 19 receives binary data of more significant bits B3 to B5 and signals OS and US to provide error correction codes E3 to E6. Error correction circuit 20 receives binary data of less significant bits B0 to B2, error correction codes E3 to E6 and signal US to provide binary output data D0 to D5 having the errors corrected.
FIG. 31 is a schematic diagram of less significant comparator 14, less significant pre-encoder 17 and less significant encoder 18 shown in FIG. 19.
FIG. 20 is a schematic diagram of a reference voltage generating circuit 11 shown in FIG. 19. Referring to FIG. 20, this reference voltage generating circuit 11 includes seven ladder resistance circuits 110 to 117 and seven switching circuits 100 to 107 each connected to the outputs of ladder circuits 110 to 117, respectively. Since this reference voltage generating circuit 11 is used for A/D conversion of 6 bits, a total of the 6th power of 2 resistance elements 6 are provided within ladder circuits 110 to 117. Each of ladder resistance circuits 110 to 117 is provided with eight resistance elements 6. For example, the j-th ladder resistance circuit 11j is provided with eight resistance elements 6 connected in series.
Each of switching circuits 100 to 107 connected to the outputs of each of ladder resistance circuits 110 to 117 is provided with thirteen switching elements in total. For example, the j-th switching circuit 10j is provided with thirteen switching elements and these are turned on when the j-th signal Jj of the output signals J0 to J7 provided from more significant pre-encoder 15 shown in FIG. 19 is at a high level.
One terminal of each of switching elements SW0 to SW12 is connected to thirteen comparators (not shown) provided within less significant comparator circuit 14 through the output lines H0 to H12 of reference voltages for less significant bits, respectively. The other terminal of each of switching elements SW3 to SW9 is connected to the connection nodes corresponding to two resistors, adjacent to each other, in ladder resistance circuit 11j. The other terminal of each of switching elements SW0, SW1, SW10 and SW11 is connected to the corresponding connection nodes *1 to *4, respectively as shown in FIG. 20. The output lines F0 to F6 of reference voltages for more significant bits are connected to seven comparators (not shown) provided in more significant comparator 13, respectively.
Generally, the reference voltage generating circuit is designed to generate various difference voltages according to the necessity in the device to which A/D converter is applicable. A/D converters 5a and 5b shown in FIGS. 15 and 19 are often employed in a video signal processing circuit in which high-speed operation is required. In the field of video signal processing, an A/D converter having a conversion rate of approximately 20 MHz, resolution of 8 to 10 bits and full scale voltage of 1.0 or 2.0 V is generally required.
For example, in the A/D converter having resolution of 8 bits and full scale voltage of 1.0 V is split into the reference voltages of 256 levels and the difference of the split voltage between two corresponds to the quantization width. Quantization width is represented by the unit "LSB". In the example described above, 1LSB corresponds to approximately 40 mVn. When A/D conversion of 8 bits is performed by the serial-parallel type A/D converter for more significant 4 bits and less significant 4 bits, the quantization width of less significant A/D conversion is ILSB (=about 4 mV), and the quantization width of more significant A/D conversion is 16 LSB (=about 64 mV).
FIG. 21 is a circuit block diagram illustrating the error correction circuit 19 shown in FIG. 19. Referring to FIG. 21, error correction circuit 19 includes OR gate 190 having 2 inputs, and full adders 193 to 196 each having 2 inputs. Respective input terminals A of full adders 193 to 195 receive binary data of more significant bits B3 to B5 provided from more significant encoder 16. Input terminal A of full adder 196 is grounded. OR gate 190 receives underscale signal US and overscale signal 0S applied from lower encoder 18. The output signal of 0R gate 190 is applied to an input terminal B of full adder 193. Respective input terminals B of full adders 194 to 196 receive underscale signal US. Respective carry output terminals and carry input terminals, adjacent to one another, of full adders 193 to 196 are connected in pairs. Error correction codes E3 to E6 are provided, respectively, through sum output terminals SUM of full adders 193 to 196.
FIG. 22 is a block diagram of the error correction circuit 20 shown in FIG. 19. Referring to FIG. 22, error correction circuit 20 includes six switching circuits 210 to 215, inverter 201 and AND gates 202 and 203. Each of the switching circuits 210 to 215 is provided with three switching elements 25 to 27. Inverter 201 receives error correction code E6 to apply inverted signal to each of switching elements 25. AND gate 202 receives error correction code E6 and inverted underscale signal US to apply an output signal to each of switching elements 26. AND gate 203 receives error correction code E6 and underscale signal US to apply an output signal UFW to each of switching elements 27. Switching elements 25 to 27 in switching circuits 210 to 215 turn on or off in response to the output signals provided from inverter 201, AND gates 202 and 203.
One end of each of respective switching elements 25 in switching circuits 210 to 215 receives each of error correction codes E0 to E5. One end of each of respective switching elements 26 is connected to the power supply potential Vcc. One end of each of respective switching elements 27 is connected to a ground potential. The other end of each of three switching elements provided in each of switching circuits 210 to 215 is connected to data output terminals D0 to D5, respectively. Respective switching elements 25 to 27 turn on when applied control signals are high.
Now, the operation of conventional serial-parallel type A/D converter 5b will be explained. Serial-parallel type A/D converter 5b operates in two stages. In the first stage, more significant comparator circuit 13, more significant pre-encoder 15 and more significant encoder 16 operate similarly to comparator circuit 4, pre-encoder 2 and encoder 3 in FIG. 15. That is, the operation similar to that shown in FIG. 17 is performed in circuits 13, 15 and 16. Consequently, more significant encoder 16 provides binary output data of more significant bits B3 to B5 to apply them to error correction circuit 19. Eight output signals J0 to J7 of more significant pre-encoder 15 are also applied to reference voltage generating circuit 11.
In the second stage, reference voltage generating circuit 11 is operated in response to the control signals J0 to J7. Referring to FIG. 20, when the j-th control signal Jj is "1", for example, all switching elements SW0 to SW12 in switching circuit 10j turn on. The fact that the j-th output signal of more significant pre-encoder 15 is "1" means that the potential of analog input signal Si is larger than the reference voltage for more significant bits Fj-1 and smaller than the reference voltage for more significant bits Fj. Therefore, the potential of analog input signal Si is determined in more detail between the reference voltages Fj-1 and Fj by less significant comparator circuit 14 and subsequent circuits.
However, between the A/D conversions of more significant bits and less significant bits, inconsistency in the output data often occurs in the result of A/D conversions of more significant bits and less significant bits by the difference of the characteristics in circuits. To solve these problems, in A/D conversion of less significant bits, conversion within its broader voltage region including applied reference voltages Fj-1 and Fj is performed. That is, in the example shown in FIG. 20, a margin of .+-.3 LSB including reference voltages Fj-1 and Fj is allowed. One LSB is an input voltage corresponding to 1-bit data "1" provided from A/D converter, and is equal to the difference of the voltages applied to both ends of resistance elements 6 shown in FIG. 20.
Thirteen comparators (not shown) provided in less significant comparator circuit 14 compare analog input signal Si with each of the reference voltages for less significant bits H0 to H12, respectively. Output signals representing a comparison result (thermometer code) are applied to less significant pre-encoder 17. Less significant pre-encoder 17 is responsive to applied thermometer code to provide fourteen output signals J0 to J13 with only one signal showing data "1". Less significant encoder 18 receives output signals J0 to J13, responsive to one signal showing data "1", to provide binary data of less significant bits B0 to B2, overscale signal OS and underscale signal US.
Encoder 18 provides binary data (US, OS, B2, B1, B0) shown in the following Table 2 in normal operation in response to the applied signals J0 to J13.
TABLE 2 ______________________________________ US, OS, B.sub.2, B.sub.1, B.sub.0 US', OS', B.sub.2 ', B.sub.1 ', B.sub.0 ' ______________________________________ J.sub.13 01010 01010 J.sub.12 01001 01000 J.sub.11 01000 00001 J.sub.10 00111 00000 J.sub.9 00110 00101 J.sub.8 00101 00100 J.sub.7 00100 00001 J.sub.6 00011 00000 J.sub.5 00010 00001 J.sub.4 00001 00000 J.sub.3 00000 00001 J.sub.2 10111 00000 J.sub.1 10110 10101 J.sub.0 10101 10101 ______________________________________
When this A/D converter 5b operates normally, only one of the signals J3 to J10 shows data "1". In comparison between analog input signal Si and the reference voltages for less significant bits H0 to H12, when the potential of analog input signal Si is outside of the region detected in A/D conversion of more significant bits, and is a lower voltage (referred to as "underscale"), one of the signals J0 to J2 shows data "1". On the other hand, when the potential of analog input signal Si is outside of the region detected in A/D conversion of more significant bits, and is a higher voltage (referred to as "overscale"), one of the signals J11 to J13 shows data "1".
When underscale is caused, in addition-subtraction in A/D conversion of more significant bits, the fact is utilized that the most significant bit is "1". When overscale is caused, by utilizing the fact that the second from the most significant bit is data "1", the addition-subtraction is performed in A/D conversion of more significant bits. At this stage, the signal of the most significant bit acts as underscale signal US, while the signal of the second from the most significant bit acts as overscale signal OS.
Error correction circuit 19 operates as an arithmetic unit performing an addition or a subtraction of data "1" to or from the resulting data of A/D conversion of more significant bits on the occurrence of overscale or underscale in A/D conversion of less significant bits. As shown in FIG. 21, error correction circuit 19 applies data (1, 0, 0, 0) to full adders 193 to 196 on the occurrence of overscale, and applies data (1, 1, 1, 1) on the occurrence of underscale. In case where no overscale and underscale happens, data (0, 0, 0, 0) is applied to full adders 193 to 196, and therefore the resulting data of A/D conversion of more significant bits are provided as data E3 to E6 without any change.
Referring to FIG. 22, in error correction circuit 20, an error is corrected on the occurrence of overflow or underflow. When the potential of analog input signal Si is larger than the reference voltage Vrel, overflow occurs. On the other hand, when the potential of analog input signal Si is smaller than the reference voltage Vre2, underflow occurs. The occurrence of overflow is detected when data (1, 1, 1) is provided as a result of A/D conversion of more significant 3 bits and overscale signal OS is "1". The occurrence of underflow is detected when data (0, 0, 0) is provided as a result of A/D conversion of more significant 3 bits and underscale signal US is "1".
In case of overflow, all bits of the output data of A/D converter are preferably "1". When underflow occurs, all bits of the output data of A/D converter are preferably "0". However, on the occurrence of overflow, less significant 3 bits of the output data of error correction circuit 19 is the sum of data (1, 1, 1) and (0, 0, 1), i.e., data (0, 0, 0). In case of underflow, less significant 3 bits of the output data of error correction circuit 19 is the sum of data (0, 0, 0) and (1, 1, 1), i.e., (1, 1, 1). Therefore, error correction circuit 20 is provided so that A/D converter 5b may provide preferable output data on the occurrence of overflow and underflow.
An error correction function in error correction circuit 20 utilizes the fact that signal E6 becomes "1" just in case overflow or underflow occurs in error correction circuit 19. That is, underflow signal UFW is obtained by a logical product (AND gate 203) of signal E6 and underscale signal US. Overflow signal OFW is obtained by a logical product (AND gate 202) of signal E6 and inverted underscale signal US. If neither overflow nor underflow does occur, since respective switching elements 25 in switching circuits 201 to 205 turn on, data E0 to E5 are provided as final output data D0 to D5.
The operation of serial-parallel type A/D converter 5b shown in FIG. 19 has been explained in the foregoing description; however, as the operation for A/D conversion is basically the same as that for parallel-type A/D converter 5a shown in FIG. 15, the foregoing problem of multi-addressing is also occurring in A/D converter 5b. As an example of the occurrence of multi-addressing, wrong output data (US', OS', B2', B1', B0') provided from encoder 18 are shown in the foregoing Table 2. The left side column of Table 2 shows data to be provided in normal operation. By comparing the corresponding data in Table 2, respectively, a big difference caused by the occurrence of multi-addressing can been seen. In addition to this, despite of the occurrence of underscale or overscale, it is pointed out that the case where signal US or OS of "1" can not be obtained may occur.
As described above, multi-addressing has often occurred in conventional parallel-type A/D converter 5a and serial-parallel type A/D converter 5b with data widely different from desired output data has been provided. Any noise or delay in the transmission of the applied clock signal is believed to cause the generation of multi-addressing. In addition to this, malfunction of the comparator in comparator circuit or the output timing gap in an encoder is also taken into account. However, as the occurrence of multi-addressing could not be prevented completely, a big error in the output data caused by multi-addressing has not been prevented.

Binary data generating circuit and A/D converter having immunity to noise


A support system comprises a support center 21 and a control measurement system 31 to be supported, which are connected via a computer network 28. The control measurement system 31 comprises means for collecting information which is available for support and when a predetermined condition holds, transmitting the collected information to the support center 21. The support center 21 comprises means for receiving the information transmitted from the control measurement system 31 and storing the received information. The information transmitted from the control measurement system 31 contains information concerning user's setting for the control measurement system 31.

1. Field of the Invention
This invention relates to a support system and more particularly to a support system by which a support providing party such as a support center supports the apparatus to be supported, delivered to each user.
2. Description of the Related Art
In recent years, a controller 2 also called an ECU (Electronic Control Unit) has been installed in a vehicle 1 and various signals are transferred between a control mechanism of the vehicle 1 and the controller 2 for the controller 2 to perform electronic control of the vehicle 1, as shown in FIG. 11(a).
For example, as shown in FIG. 11(b), signals indicating the engine speed, the vehicle speed, etc., detected by various sensors placed in the vehicle 1 are sent to an ECU 2a for engine control, which then performs predetermined calculation processing based on the sent signals and sends the calculation result (for example, signal to control the fuel oil consumption, the ignition timing, the bypass air amount, etc.,) to the control mechanism of an actuator, etc., placed in the vehicle 1 for totally performing ignition timing control, knock control, idle speed control, etc., centering on fuel oil consumption control.
The signal input to the ECU 2a for engine control and the signal output therefrom change from moment to moment and further some of the signals, such as the signals indicating the engine speed, the vehicle speed, etc., and the control signals, change while they depend on each other.
Thus, to perform operation check and performance evaluation of the ECU 2a for engine control, the ECU 2a for engine control needs to be installed in the actual vehicle 1 or a control measurement system 3 as shown in FIGS. 12 and 13 for simulating the behavior of the vehicle 1 (namely, putting into mathematical expression and performing calculation processing) needs to be used.
The control measurement system 3 includes a computer 4, a measurement board and rack 5, and an ECU interface box 6. The computer 4 includes a microcomputer 7 having a control measurement unit 8 registering application software for performing operation check and performance evaluation of the ECU 2a for engine control, etc., using the measurement board and rack 5, an input unit 9, and a display unit 10.
The measurement board and rack 5 includes a CPU board 11 for performing various types of data processing and simulation calculations (model calculations), an I/O control board 12, an analog input board 13, an analog output board 14, a digital input/output board 15, a pulse input/output board 16, and a variable resistor board 17.
The measurement board and rack 5 simulatedly calculates the state amounts of the parts of the vehicle 1 (for example, the engine speed, the vehicle speed, etc.,) based on the control signals sent from the ECU 2a for engine control and input elements input from the computer 4, and returns the calculation result to the ECU 2a for engine control through the ECU interface box 6.
That is, the control measurement system 3 is a system that can execute HIL (Hardware In the Loop) simulation and such a system is used as a vehicle model instead of the actual vehicle 1, whereby it is made possible to drastically decrease the weight of operation check and performance evaluation of the ECU 2a for engine control using the actual vehicle 1 and facilitate development of control logic, etc.
By the way, for a system for executing HIL simulation, such as the control measurement system 3, often the user changes setting of software and hardware as the user desires. Thus, it is difficult for the support providing party (for example, support center) to precisely keep track of the setup state (for example, I/O port assignment state), the operation state (for example, CPU load factor), etc., of each system.
For example, the user can design a vehicle model as desired using MATLAB/SIMULINK (registered trademark) of a control system design tool of The Math Works USA, etc., and I/O port assignment, numeric value conversion expression in I/O port (for example, conversion between voltage and physical value), calculation period, the number of sampling data pieces in one period, and the like are set based on the design.
Thus, it is difficult for the support providing party to keep track of the setup state, of course, and the support providing party cannot keep track of the operation state in the control measurement system 3 for realizing a vehicle model designed as desired by the user (for example, use frequency, CPU load factor, user operation procedure, model scale, failure state).
Therefore, if the support providing party receives a communication of a failure or a defective condition of the control measurement system 3 from the user, there is a problem of the incapability of quickly offering appropriate advice. The support person needs to make a visit to the place where the system is delivered to precisely keep track of the state depending on the situation; there is a problem of requiring much time and large cost.
When a new commodity that can be used with the control measurement system 3 is developed, if the support person cannot precisely keep track of the setup state or the operation state of the control measurement system 3 delivered to each user, there is a problem for the support person to be unable to properly determine which commodity is to be introduced to which user.

Support system for a vehicular ECU control measurement system


The invention is a process and the corresponding apparatus for producing light olefins from oxygenates in an OTO reactor comprising sending an oxygenate feed stream through a feed stream distributor into an OTO reactor, contacting the oxygenates with a catalyst to produce a mixture comprising light olefins, diolefins, unreacted oxygenate and other by-products; separating the unreacted oxygenate and diolefins from said light olefins and said by-products; and returning the unreacted oxygenate and diolefins to the OTO reactor. The unreacted oxygenate and diolefins are sent through at least one feed nozzle into said reactor at a point separate from the oxygenate feed stream.

A major portion of the worldwide petrochemical industry is concerned with the production of light olefin materials and their subsequent use in the production of numerous important chemical products via polymerization, oligomerization, alkylation and the like well-known chemical reactions. Light olefins include ethylene, propylene and mixtures thereof. These light olefins are essential building blocks for the modern petrochemical and chemical industries. The major source for these materials in present day refining is the steam cracking of petroleum feeds. The art has long sought a source other than petroleum for the massive quantities of raw materials that are needed to supply the demand for these light olefin materials. A great deal of the prior art's attention has been focused on the possibility of using hydrocarbon oxygenates and more specifically methanol as a prime source of the necessary alternative feedstock. Oxygenates are particularly attractive because they can be produced from such widely available materials as coal, natural gas, recycled plastics, various carbon waste streams from industry and various products and by-products from the agricultural industry. The art of making methanol and other oxygenates from these types of raw materials is well established and typically involves the use of one or more of the following procedures: (1) manufacture of synthesis gas by any of the known techniques typically using a nickel or cobalt catalyst followed by the well-known methanol synthesis step using relatively high pressure with a copper-based catalyst; (2) selective fermentation of various organic agricultural products and by-products in order to produce oxygenates; or (3) various combinations of these techniques.
The art has focused on different procedures for catalytically converting oxygenates such as methanol into the desired light olefin products. These light olefin products must be available in quantities and purities such that they are interchangeable in downstream processing with the materials that are presently produced using petroleum sources. Although many oxygenates have been discussed in the prior art, the principal focus of the two major routes to produce these desired light olefins has been on methanol conversion technology. There are two major techniques for conversion of methanol to light olefins. The first of these MTO processes is based on early German and American work with a catalytic conversion zone containing a zeolitic type of catalyst system. U.S. Pat. No. 4,387,263 reports on a series of experiments with methanol conversion techniques using a ZSM-5-type of catalyst system wherein the problem of DME recycle is a major focus of the technology disclosed.
Primarily because of an inability of this zeolitic MTO route to control the amounts of undesired C4+ hydrocarbon products produced by the ZSM-5 type of catalyst system, the art soon developed a second MTO conversion technology based on the use of a non-zeolitic molecular sieve catalytic material. This branch of the MTO art is perhaps best illustrated by reference to UOP's extensive work in this area as reported in numerous patents of which U.S. Pat. No. 5,095,163; U.S. Pat. No. 5,126,308 and U.S. Pat. No. 5,191,141 are representative. This second approach to MTO conversion technology was primarily based on using a catalyst system comprising a non-zeolitic molecular sieve, generally a metal aluminophosphate (ELAPO) and more specifically a silicoaluminophosphate molecular sieve (SAPO), with a strong preference for a SAPO species that is known as SAPO-34. This SAPO-34 material was found to have a very high selectivity for light olefins with a methanol feedstock and consequently very low selectivity for the undesired corresponding light paraffins and the heavier materials. This ELAPO catalyzed MTO approach is known to have at least the following advantages relative to the zeolitic catalyst route to light olefins: (1) greater yields of light olefins at equal quantities of methanol converted; (2) capability of direct recovery of polymer grade ethylene and propylene without the necessity of the use of extraordinary physical separation steps to separate ethylene and propylene from their corresponding paraffin analogs; (3) sharply limited production of by-products such as stabilized gasoline; (4) flexibility to adjust the product ethylene-to-propylene weight ratios over the range of 1.5:1 to 0.75:1 by minimal adjustment of the MTO conversion conditions; and (5) significantly less coke make in the MTO conversion zone relative to that experienced with the zeolitic catalyst system.
For various reasons well articulated in UOP's patents, U.S. Pat. No. 6,403,854; U.S. Pat. No. 6,166,282 and U.S. Pat. No. 5,744,680 (all of the teaching of which are hereby specifically incorporated by reference) the consensus of the practitioners in this OTO or MTO art points to the use of a fluidized reaction zone along with a fluidized regeneration zone as the preferred commercial solution to the problem of effectively and efficiently using an ELAPO or SAPO-type of catalyst system. As is well-understood by those of skill in the fluidization art, the use of this technology gives rise to a substantial problem of solid-vapor separation in order to efficiently separate the particles of the fluidized catalyst from the vapor products of the OTO or MTO reaction as well as from any unreacted oxygenate materials exiting the OTO or MTO conversion zone. Standard industry practice for accomplishing this difficult separation step involves its use of one or more vapor-solid cyclonic separating means which are well illustrated in the sole drawing of U.S. Pat. No. 6,166,282 where a series of three cyclonic separation means are used to separate spent OTO or MTO catalyst from the product effluent stream.
Despite the promising developments associated with the ELAPO or SAPO catalyzed routes to light olefins there are still substantial improvements needed in development of economically attractive OTO or MTO processes. Coking of surfaces within the reactor can reduce yield and productivity of these processes. Two particular potential coking problems have been discovered. One coking problem to resolve is the coking of surfaces as the result of reactive materials remaining in stagnant zones within the reactor. A second coking problem which is the subject of this invention can be the result of recycling of unreacted oxygenate together with recycling of various reaction by-products combined with the oxygenate feed stream. Both of these problems are resolved as described herein. A further problem has also been resolved. In previous designs, there have been consecutive stages of cyclones for separation of catalyst particles from product effluent gas. Such a design is susceptible to difficulties caused by pressure drop with the two stages of cyclones. In addition, in the event of an unexpected surge in pressure, such a design is susceptible to a significant loss of catalyst.

Direct return of oxygenate recycle stream in olefin production process


A music carrousel structure with various dynamic actions, including several decorative articles, a stem and a base. The power mechanism of the music box is fixed on a support tray. The power output shaft is engaged with a gear which is engaged with a toothed ring. The center of the toothed ring is disposed with a central disc which is on the same plane as the lower surface of the toothed ring. The above members are all hidden in a canopy. The canopy is fixed with a fixing disc or a hanging disc. The toy horses via copper rods are hung on outer periphery of the toothed ring or the support tray. The canopy is supported on the support rod. A stem in the support rod is connected with a transmission mechanism in the base, whereby the power is transmitted to the transmission mechanism. The decorative articles are fixed on the transverse levers and get into and out of the holes of the base by means of cooperation of the springs and waved block.

The present invention relates to a music carrousel structure with various dynamic actions. The music carrousel structure can be easily and conveniently operated.
Many kinds of decorative music carrousels are commercially available. These decorative carrousels can be substantially divided into two types. One is that the carrousel has monotonous action which can hardly meet the requirement of market. The other is that the decorative toy horses can be lifted and lowered. However, such carrousel has complicated structure and a lot of parts and is subject to mechanical malfunction. Moreover, it is inconvenient to operate such carrousel and the manufacturing cost for such carrousel is very high.

Music carrousel structure with various dynamic actions


A wafer packaging method is disclosed.

1. Technical Field
The present invention relates to a wafer packaging method.
2. Description of the Related Art
Wafer-level packaging method, all processes are progressed as a wafer, is improved actively. But, wafer-level packaging method is very expensive because it uses not only new equipment but also photo-sensitive film.
To reduce the manufacturing cost of packaging, many wafers must be packaged just one full process and use cheep materials during the process. But, we have used just one wafer while packaging process.
Therefore, we need new process to package wafer by using manufacturing process of PCB (Printed Circuit Pattern).

Abstract: A wafer packaging method is disclosed.

Abstract: An aspect of the invention is to provide a wafer packaging method comprising;    attaching tape onto one side of a carrier, the carrier having a through-hole formed therein; attaching a wafer onto the tape exposed inside the through-hole such that at least one electrode of the wafer is exposed; and            performing a packaging process on the carrier such that the wafer is packaged.


An electrosurgical system includes a power source, a microwave applicator, a switching mechanism, and a controller. The power source is configured to generate microwave energy. The microwave applicator is configured to deliver microwave energy from the power source to tissue. The switching mechanism includes a housing having input and output ports. The input port is connectable to the power source and the output port is connectable to the microwave applicator. The housing is configured to house one or more switches therein. The controller is in operative communication with the switching mechanism to toggle the switch from a first state, wherein microwave energy generated by the power source is directed to the microwave applicator to a second state, wherein microwave energy is directed to a resistive load operably coupled to the switching mechanism.

1. Technical Field
The present disclosure relates to peripheral switching devices and more particularly, to an in-line switching mechanism configured to control power output from a microwave generator to a microwave applicator.
2. Background of Related Art
Electrosurgical systems that utilize microwave generators in conjunction with microwave applicators to treat tissue, e.g., ablate tissue, are well known in the art. Conventional microwave generators are configured to provide microwave energy to the microwave applicator for a specific time frame, e.g., a duty cycle. In certain instances, however, it may prove necessary (or advantageous) to shut the power off prior to the termination of duty cycle. For example, the microwave applicator may need to be moved to a different area on the tissue being treated or to a different location within a patient. Typically, one or more of the "at-the-generator" controls on the microwave generator are activated to terminate or interrupt the duty cycle. In certain instances, for example, to terminate or interrupt the duty cycle, an on/off and/or a reset switch on microwave generator may be pressed. Typically, it is a surgical assistant and not a surgeon that presses these switches. While this approach to control the microwave generator may be effective under some surgical scenarios, hand/foot switching to control the microwave generator may prove advantageous. For example, hand/foot switching capabilities allow a surgeon to directly control the microwave generator, instead having to rely on a surgical assistant.

Peripheral switching device for microwave energy platforms


A microcomputer includes a central processing unit (CPU) and an electrically erasable and programmable nonvolatile memory (EEPROM) fabricated on a single semiconductor chip. When CPU issues a data write request to EEPROM, a data write control circuit is initiated to perform a data write-processing in which data in an address of EEPROM selected by CPU is first erased and thereafter data from CPU is written into that selected address. There is further provided an over-written detection circuit for detecting that CPU issues another data write request to EEPROM while the data write control circuit is performing the data write-processing and for producing an over-write detection signal to CPU.

The present invention relates to a microcomputer having a central prossing unit (CPU) and an electrically erasable and programmable nonvolatile memory (caller hereinafter "EEPROM") fabricated on a single semiconductor chip.
In a microcomputer, a static type random access memory (SRAM) is employed in general as a data memory for storing data to be processed and/or processed resultant data. However, SRAM has an unavoidable problem that data stored therein are destroyed when a power voltage applied thereto is cut off. Therefore, it has been proposed to employ, as a part of the data memory, EEPROM into which data can be written and from which data can be read out, and further EEPROM holding data written therein even after a power voltage applied thereto is cut off.
A data write-processing to EEPROM consists of a data erase-operation, which is first performed to erase data already stored in an address into which new data is to be written, and a data write-operation, which is thereafter performed to write the new data into that address. It is well known in the art that such a data write-processing requires a time period of about ten msec. This time period is extremely long as compared with the instruction execution speed of CPU. If CPU manages the data write-processing to EEPROM, therefore, the program execution efficiency is deteriorated remarkably.
An automaton circuit is thus provided to perform and manage the data write-processing to EEPROM in place of CPU. When CPU encounters a data write-instruction to EEPROM, it supplies the write-processing automaton circuit only with a write-command signal, data to be written and address information for selecting a desired address of EEPROM. Thereafter, the operation of CPU is shifted to execute a next instruction. On the other hand, the write-processing automaton circuit is initiated to first erase data stored in the selected address and then write new data into that address. Thus, CPU can execute the program during the data write-processing to EEPROM.
However, since the program execution advances during the data-write processing to EEPROM, there occurs a case that CPU encounters again a data write-instruction to EEPROM before the current data write-processing to EEPROM is completed. Also in that case, CPU generates a data write-request to the automaton circuit and thereafter shifts to execute a next instruction. On the other hand, since the data write-processing responsive to the previous data write-request is still being performed in EEPROM, the new data write-request is disregarded. As a result, data to be written into EEPROM is lost to cause a misoperation.

Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed